drivers/pci/intr_remapping.c

   1 #include <linux/interrupt.h>
   2 #include <linux/dmar.h>
   3 #include <linux/spinlock.h>
   4 #include <linux/slab.h>
   5 #include <linux/jiffies.h>
   6 #include <linux/hpet.h>
   7 #include <linux/pci.h>
   8 #include <linux/irq.h>
   9 #include <asm/io_apic.h>
  10 #include <asm/smp.h>
  11 #include <asm/cpu.h>
  12 #include <linux/intel-iommu.h>
  13 #include "intr_remapping.h"
  14 #include <acpi/acpi.h>
  15 #include <asm/pci-direct.h>
  16 #include "pci.h"
  17
  18 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  19 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
  20 static int ir_ioapic_num, ir_hpet_num;
  21 int intr_remapping_enabled;
  22
  23 static int disable_intremap;
  24 static int disable_sourceid_checking;
  25
  26 static __init int setup_nointremap(char *str)
  27 {
  28         disable_intremap = 1;
  29         return 0;
  30 }
  31 early_param("nointremap", setup_nointremap);
  32
  33 static __init int setup_intremap(char *str)
  34 {
  35         if (!str)
  36                 return -EINVAL;
  37
  38         if (!strncmp(str, "on", 2))
  39                 disable_intremap = 0;
  40         else if (!strncmp(str, "off", 3))
  41                 disable_intremap = 1;
  42         else if (!strncmp(str, "nosid", 5))
  43                 disable_sourceid_checking = 1;
  44
  45         return 0;
  46 }
  47 early_param("intremap", setup_intremap);
  48
  49 struct irq_2_iommu {
  50         struct intel_iommu *iommu;
  51         u16 irte_index;
  52         u16 sub_handle;
  53         u8  irte_mask;
  54 };
  55
  56 #ifdef CONFIG_GENERIC_HARDIRQS
  57 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  58 {
  59         return get_irq_iommu(irq);
  60 }
  61
  62 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  63 {
  64         struct irq_data *data = irq_get_irq_data(irq);
  65
  66         if (WARN_ONCE(data->irq_2_iommu,
  67                       KERN_DEBUG "irq_2_iommu!=NULL irq %u\n", irq))
  68                 return data->irq_2_iommu;
  69
  70         data->irq_2_iommu = kzalloc_node(sizeof(*data->irq_2_iommu),
  71                                          GFP_ATOMIC, data->node);
  72         return data->irq_2_iommu;
  73 }
  74
  75 static void irq_2_iommu_free(unsigned int irq)
  76 {
  77         struct irq_data *d = irq_get_irq_data(irq);
  78         struct irq_2_iommu *p = d->irq_2_iommu;
  79
  80         d->irq_2_iommu = NULL;
  81         kfree(p);
  82 }
  83
  84 #else /* !CONFIG_SPARSE_IRQ */
  85
  86 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
  87
  88 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  89 {
  90         if (irq < nr_irqs)
  91                 return &irq_2_iommuX[irq];
  92
  93         return NULL;
  94 }
  95 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  96 {
  97         return irq_2_iommu(irq);
  98 }
  99
 100 static void irq_2_iommu_free(unsigned int irq) { }
 101
 102 #endif
 103
 104 static DEFINE_SPINLOCK(irq_2_ir_lock);
 105
 106 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
 107 {
 108         struct irq_2_iommu *irq_iommu;
 109
 110         irq_iommu = irq_2_iommu(irq);
 111
 112         if (!irq_iommu)
 113                 return NULL;
 114
 115         if (!irq_iommu->iommu)
 116                 return NULL;
 117
 118         return irq_iommu;
 119 }
 120
 121 int irq_remapped(int irq)
 122 {
 123         return valid_irq_2_iommu(irq) != NULL;
 124 }
 125
 126 int get_irte(int irq, struct irte *entry)
 127 {
 128         int index;
 129         struct irq_2_iommu *irq_iommu;
 130         unsigned long flags;
 131
 132         if (!entry)
 133                 return -1;
 134
 135         spin_lock_irqsave(&irq_2_ir_lock, flags);
 136         irq_iommu = valid_irq_2_iommu(irq);
 137         if (!irq_iommu) {
 138                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 139                 return -1;
 140         }
 141
 142         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 143         *entry = *(irq_iommu->iommu->ir_table->base + index);
 144
 145         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 146         return 0;
 147 }
 148
 149 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
 150 {
 151         struct ir_table *table = iommu->ir_table;
 152         struct irq_2_iommu *irq_iommu;
 153         u16 index, start_index;
 154         unsigned int mask = 0;
 155         unsigned long flags;
 156         int i;
 157
 158         if (!count)
 159                 return -1;
 160
 161 #ifndef CONFIG_SPARSE_IRQ
 162         /* protect irq_2_iommu_alloc later */
 163         if (irq >= nr_irqs)
 164                 return -1;
 165 #endif
 166
 167         /*
 168          * start the IRTE search from index 0.
 169          */
 170         index = start_index = 0;
 171
 172         if (count > 1) {
 173                 count = __roundup_pow_of_two(count);
 174                 mask = ilog2(count);
 175         }
 176
 177         if (mask > ecap_max_handle_mask(iommu->ecap)) {
 178                 printk(KERN_ERR
 179                        "Requested mask %x exceeds the max invalidation handle"
 180                        " mask value %Lx\n", mask,
 181                        ecap_max_handle_mask(iommu->ecap));
 182                 return -1;
 183         }
 184
 185         spin_lock_irqsave(&irq_2_ir_lock, flags);
 186         do {
 187                 for (i = index; i < index + count; i++)
 188                         if  (table->base[i].present)
 189                                 break;
 190                 /* empty index found */
 191                 if (i == index + count)
 192                         break;
 193
 194                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
 195
 196                 if (index == start_index) {
 197                         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 198                         printk(KERN_ERR "can't allocate an IRTE\n");
 199                         return -1;
 200                 }
 201         } while (1);
 202
 203         for (i = index; i < index + count; i++)
 204                 table->base[i].present = 1;
 205
 206         irq_iommu = irq_2_iommu_alloc(irq);
 207         if (!irq_iommu) {
 208                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 209                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 210                 return -1;
 211         }
 212
 213         irq_iommu->iommu = iommu;
 214         irq_iommu->irte_index =  index;
 215         irq_iommu->sub_handle = 0;
 216         irq_iommu->irte_mask = mask;
 217
 218         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 219
 220         return index;
 221 }
 222
 223 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 224 {
 225         struct qi_desc desc;
 226
 227         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 228                    | QI_IEC_SELECTIVE;
 229         desc.high = 0;
 230
 231         return qi_submit_sync(&desc, iommu);
 232 }
 233
 234 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 235 {
 236         int index;
 237         struct irq_2_iommu *irq_iommu;
 238         unsigned long flags;
 239
 240         spin_lock_irqsave(&irq_2_ir_lock, flags);
 241         irq_iommu = valid_irq_2_iommu(irq);
 242         if (!irq_iommu) {
 243                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 244                 return -1;
 245         }
 246
 247         *sub_handle = irq_iommu->sub_handle;
 248         index = irq_iommu->irte_index;
 249         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 250         return index;
 251 }
 252
 253 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 254 {
 255         struct irq_2_iommu *irq_iommu;
 256         unsigned long flags;
 257
 258         spin_lock_irqsave(&irq_2_ir_lock, flags);
 259
 260         irq_iommu = irq_2_iommu_alloc(irq);
 261
 262         if (!irq_iommu) {
 263                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 264                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 265                 return -1;
 266         }
 267
 268         irq_iommu->iommu = iommu;
 269         irq_iommu->irte_index = index;
 270         irq_iommu->sub_handle = subhandle;
 271         irq_iommu->irte_mask = 0;
 272
 273         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 274
 275         return 0;
 276 }
 277
 278 int modify_irte(int irq, struct irte *irte_modified)
 279 {
 280         int rc;
 281         int index;
 282         struct irte *irte;
 283         struct intel_iommu *iommu;
 284         struct irq_2_iommu *irq_iommu;
 285         unsigned long flags;
 286
 287         spin_lock_irqsave(&irq_2_ir_lock, flags);
 288         irq_iommu = valid_irq_2_iommu(irq);
 289         if (!irq_iommu) {
 290                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 291                 return -1;
 292         }
 293
 294         iommu = irq_iommu->iommu;
 295
 296         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 297         irte = &iommu->ir_table->base[index];
 298
 299         set_64bit(&irte->low, irte_modified->low);
 300         set_64bit(&irte->high, irte_modified->high);
 301         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 302
 303         rc = qi_flush_iec(iommu, index, 0);
 304         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 305
 306         return rc;
 307 }
 308
 309 struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
 310 {
 311         int i;
 312
 313         for (i = 0; i < MAX_HPET_TBS; i++)
 314                 if (ir_hpet[i].id == hpet_id)
 315                         return ir_hpet[i].iommu;
 316         return NULL;
 317 }
 318
 319 struct intel_iommu *map_ioapic_to_ir(int apic)
 320 {
 321         int i;
 322
 323         for (i = 0; i < MAX_IO_APICS; i++)
 324                 if (ir_ioapic[i].id == apic)
 325                         return ir_ioapic[i].iommu;
 326         return NULL;
 327 }
 328
 329 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
 330 {
 331         struct dmar_drhd_unit *drhd;
 332
 333         drhd = dmar_find_matched_drhd_unit(dev);
 334         if (!drhd)
 335                 return NULL;
 336
 337         return drhd->iommu;
 338 }
 339
 340 static int clear_entries(struct irq_2_iommu *irq_iommu)
 341 {
 342         struct irte *start, *entry, *end;
 343         struct intel_iommu *iommu;
 344         int index;
 345
 346         if (irq_iommu->sub_handle)
 347                 return 0;
 348
 349         iommu = irq_iommu->iommu;
 350         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 351
 352         start = iommu->ir_table->base + index;
 353         end = start + (1 << irq_iommu->irte_mask);
 354
 355         for (entry = start; entry < end; entry++) {
 356                 set_64bit(&entry->low, 0);
 357                 set_64bit(&entry->high, 0);
 358         }
 359
 360         return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 361 }
 362
 363 int free_irte(int irq)
 364 {
 365         int rc = 0;
 366         struct irq_2_iommu *irq_iommu;
 367         unsigned long flags;
 368
 369         spin_lock_irqsave(&irq_2_ir_lock, flags);
 370         irq_iommu = valid_irq_2_iommu(irq);
 371         if (!irq_iommu) {
 372                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 373                 return -1;
 374         }
 375
 376         rc = clear_entries(irq_iommu);
 377
 378         irq_iommu->iommu = NULL;
 379         irq_iommu->irte_index = 0;
 380         irq_iommu->sub_handle = 0;
 381         irq_iommu->irte_mask = 0;
 382
 383         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 384
 385         irq_2_iommu_free(irq);
 386
 387         return rc;
 388 }
 389
 390 /*
 391  * source validation type
 392  */
 393 #define SVT_NO_VERIFY           0x0  /* no verification is required */
 394 #define SVT_VERIFY_SID_SQ       0x1  /* verify using SID and SQ fiels */
 395 #define SVT_VERIFY_BUS          0x2  /* verify bus of request-id */
 396
 397 /*
 398  * source-id qualifier
 399  */
 400 #define SQ_ALL_16       0x0  /* verify all 16 bits of request-id */
 401 #define SQ_13_IGNORE_1  0x1  /* verify most significant 13 bits, ignore
 402                               * the third least significant bit
 403                               */
 404 #define SQ_13_IGNORE_2  0x2  /* verify most significant 13 bits, ignore
 405                               * the second and third least significant bits
 406                               */
 407 #define SQ_13_IGNORE_3  0x3  /* verify most significant 13 bits, ignore
 408                               * the least three significant bits
 409                               */
 410
 411 /*
 412  * set SVT, SQ and SID fields of irte to verify
 413  * source ids of interrupt requests
 414  */
 415 static void set_irte_sid(struct irte *irte, unsigned int svt,
 416                          unsigned int sq, unsigned int sid)
 417 {
 418         if (disable_sourceid_checking)
 419                 svt = SVT_NO_VERIFY;
 420         irte->svt = svt;
 421         irte->sq = sq;
 422         irte->sid = sid;
 423 }
 424
 425 int set_ioapic_sid(struct irte *irte, int apic)
 426 {
 427         int i;
 428         u16 sid = 0;
 429
 430         if (!irte)
 431                 return -1;
 432
 433         for (i = 0; i < MAX_IO_APICS; i++) {
 434                 if (ir_ioapic[i].id == apic) {
 435                         sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
 436                         break;
 437                 }
 438         }
 439
 440         if (sid == 0) {
 441                 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
 442                 return -1;
 443         }
 444
 445         set_irte_sid(irte, 1, 0, sid);
 446
 447         return 0;
 448 }
 449
 450 int set_hpet_sid(struct irte *irte, u8 id)
 451 {
 452         int i;
 453         u16 sid = 0;
 454
 455         if (!irte)
 456                 return -1;
 457
 458         for (i = 0; i < MAX_HPET_TBS; i++) {
 459                 if (ir_hpet[i].id == id) {
 460                         sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
 461                         break;
 462                 }
 463         }
 464
 465         if (sid == 0) {
 466                 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
 467                 return -1;
 468         }
 469
 470         /*
 471          * Should really use SQ_ALL_16. Some platforms are broken.
 472          * While we figure out the right quirks for these broken platforms, use
 473          * SQ_13_IGNORE_3 for now.
 474          */
 475         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
 476
 477         return 0;
 478 }
 479
 480 int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 481 {
 482         struct pci_dev *bridge;
 483
 484         if (!irte || !dev)
 485                 return -1;
 486
 487         /* PCIe device or Root Complex integrated PCI device */
 488         if (pci_is_pcie(dev) || !dev->bus->parent) {
 489                 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 490                              (dev->bus->number << 8) | dev->devfn);
 491                 return 0;
 492         }
 493
 494         bridge = pci_find_upstream_pcie_bridge(dev);
 495         if (bridge) {
 496                 if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
 497                         set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
 498                                 (bridge->bus->number << 8) | dev->bus->number);
 499                 else /* this is a legacy PCI bridge */
 500                         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 501                                 (bridge->bus->number << 8) | bridge->devfn);
 502         }
 503
 504         return 0;
 505 }
 506
 507 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 508 {
 509         u64 addr;
 510         u32 sts;
 511         unsigned long flags;
 512
 513         addr = virt_to_phys((void *)iommu->ir_table->base);
 514
 515         spin_lock_irqsave(&iommu->register_lock, flags);
 516
 517         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 518                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 519
 520         /* Set interrupt-remapping table pointer */
 521         iommu->gcmd |= DMA_GCMD_SIRTP;
 522         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 523
 524         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 525                       readl, (sts & DMA_GSTS_IRTPS), sts);
 526         spin_unlock_irqrestore(&iommu->register_lock, flags);
 527
 528         /*
 529          * global invalidation of interrupt entry cache before enabling
 530          * interrupt-remapping.
 531          */
 532         qi_global_iec(iommu);
 533
 534         spin_lock_irqsave(&iommu->register_lock, flags);
 535
 536         /* Enable interrupt-remapping */
 537         iommu->gcmd |= DMA_GCMD_IRE;
 538         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 539
 540         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 541                       readl, (sts & DMA_GSTS_IRES), sts);
 542
 543         spin_unlock_irqrestore(&iommu->register_lock, flags);
 544 }
 545
 546
 547 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
 548 {
 549         struct ir_table *ir_table;
 550         struct page *pages;
 551
 552         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 553                                              GFP_ATOMIC);
 554
 555         if (!iommu->ir_table)
 556                 return -ENOMEM;
 557
 558         pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
 559                                  INTR_REMAP_PAGE_ORDER);
 560
 561         if (!pages) {
 562                 printk(KERN_ERR "failed to allocate pages of order %d\n",
 563                        INTR_REMAP_PAGE_ORDER);
 564                 kfree(iommu->ir_table);
 565                 return -ENOMEM;
 566         }
 567
 568         ir_table->base = page_address(pages);
 569
 570         iommu_set_intr_remapping(iommu, mode);
 571         return 0;
 572 }
 573
 574 /*
 575  * Disable Interrupt Remapping.
 576  */
 577 static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
 578 {
 579         unsigned long flags;
 580         u32 sts;
 581
 582         if (!ecap_ir_support(iommu->ecap))
 583                 return;
 584
 585         /*
 586          * global invalidation of interrupt entry cache before disabling
 587          * interrupt-remapping.
 588          */
 589         qi_global_iec(iommu);
 590
 591         spin_lock_irqsave(&iommu->register_lock, flags);
 592
 593         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
 594         if (!(sts & DMA_GSTS_IRES))
 595                 goto end;
 596
 597         iommu->gcmd &= ~DMA_GCMD_IRE;
 598         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 599
 600         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 601                       readl, !(sts & DMA_GSTS_IRES), sts);
 602
 603 end:
 604         spin_unlock_irqrestore(&iommu->register_lock, flags);
 605 }
 606
 607 int __init intr_remapping_supported(void)
 608 {
 609         struct dmar_drhd_unit *drhd;
 610
 611         if (disable_intremap)
 612                 return 0;
 613
 614         if (!dmar_ir_support())
 615                 return 0;
 616
 617         for_each_drhd_unit(drhd) {
 618                 struct intel_iommu *iommu = drhd->iommu;
 619
 620                 if (!ecap_ir_support(iommu->ecap))
 621                         return 0;
 622         }
 623
 624         return 1;
 625 }
 626
 627 int __init enable_intr_remapping(int eim)
 628 {
 629         struct dmar_drhd_unit *drhd;
 630         int setup = 0;
 631
 632         if (parse_ioapics_under_ir() != 1) {
 633                 printk(KERN_INFO "Not enable interrupt remapping\n");
 634                 return -1;
 635         }
 636
 637         for_each_drhd_unit(drhd) {
 638                 struct intel_iommu *iommu = drhd->iommu;
 639
 640                 /*
 641                  * If the queued invalidation is already initialized,
 642                  * shouldn't disable it.
 643                  */
 644                 if (iommu->qi)
 645                         continue;
 646
 647                 /*
 648                  * Clear previous faults.
 649                  */
 650                 dmar_fault(-1, iommu);
 651
 652                 /*
 653                  * Disable intr remapping and queued invalidation, if already
 654                  * enabled prior to OS handover.
 655                  */
 656                 iommu_disable_intr_remapping(iommu);
 657
 658                 dmar_disable_qi(iommu);
 659         }
 660
 661         /*
 662          * check for the Interrupt-remapping support
 663          */
 664         for_each_drhd_unit(drhd) {
 665                 struct intel_iommu *iommu = drhd->iommu;
 666
 667                 if (!ecap_ir_support(iommu->ecap))
 668                         continue;
 669
 670                 if (eim && !ecap_eim_support(iommu->ecap)) {
 671                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 672                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 673                         return -1;
 674                 }
 675         }
 676
 677         /*
 678          * Enable queued invalidation for all the DRHD's.
 679          */
 680         for_each_drhd_unit(drhd) {
 681                 int ret;
 682                 struct intel_iommu *iommu = drhd->iommu;
 683                 ret = dmar_enable_qi(iommu);
 684
 685                 if (ret) {
 686                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 687                                " invalidation, ecap %Lx, ret %d\n",
 688                                drhd->reg_base_addr, iommu->ecap, ret);
 689                         return -1;
 690                 }
 691         }
 692
 693         /*
 694          * Setup Interrupt-remapping for all the DRHD's now.
 695          */
 696         for_each_drhd_unit(drhd) {
 697                 struct intel_iommu *iommu = drhd->iommu;
 698
 699                 if (!ecap_ir_support(iommu->ecap))
 700                         continue;
 701
 702                 if (setup_intr_remapping(iommu, eim))
 703                         goto error;
 704
 705                 setup = 1;
 706         }
 707
 708         if (!setup)
 709                 goto error;
 710
 711         intr_remapping_enabled = 1;
 712
 713         return 0;
 714
 715 error:
 716         /*
 717          * handle error condition gracefully here!
 718          */
 719         return -1;
 720 }
 721
 722 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
 723                                       struct intel_iommu *iommu)
 724 {
 725         struct acpi_dmar_pci_path *path;
 726         u8 bus;
 727         int count;
 728
 729         bus = scope->bus;
 730         path = (struct acpi_dmar_pci_path *)(scope + 1);
 731         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 732                 / sizeof(struct acpi_dmar_pci_path);
 733
 734         while (--count > 0) {
 735                 /*
 736                  * Access PCI directly due to the PCI
 737                  * subsystem isn't initialized yet.
 738                  */
 739                 bus = read_pci_config_byte(bus, path->dev, path->fn,
 740                                            PCI_SECONDARY_BUS);
 741                 path++;
 742         }
 743         ir_hpet[ir_hpet_num].bus   = bus;
 744         ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn);
 745         ir_hpet[ir_hpet_num].iommu = iommu;
 746         ir_hpet[ir_hpet_num].id    = scope->enumeration_id;
 747         ir_hpet_num++;
 748 }
 749
 750 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
 751                                       struct intel_iommu *iommu)
 752 {
 753         struct acpi_dmar_pci_path *path;
 754         u8 bus;
 755         int count;
 756
 757         bus = scope->bus;
 758         path = (struct acpi_dmar_pci_path *)(scope + 1);
 759         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 760                 / sizeof(struct acpi_dmar_pci_path);
 761
 762         while (--count > 0) {
 763                 /*
 764                  * Access PCI directly due to the PCI
 765                  * subsystem isn't initialized yet.
 766                  */
 767                 bus = read_pci_config_byte(bus, path->dev, path->fn,
 768                                            PCI_SECONDARY_BUS);
 769                 path++;
 770         }
 771
 772         ir_ioapic[ir_ioapic_num].bus   = bus;
 773         ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn);
 774         ir_ioapic[ir_ioapic_num].iommu = iommu;
 775         ir_ioapic[ir_ioapic_num].id    = scope->enumeration_id;
 776         ir_ioapic_num++;
 777 }
 778
 779 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
 780                                       struct intel_iommu *iommu)
 781 {
 782         struct acpi_dmar_hardware_unit *drhd;
 783         struct acpi_dmar_device_scope *scope;
 784         void *start, *end;
 785
 786         drhd = (struct acpi_dmar_hardware_unit *)header;
 787
 788         start = (void *)(drhd + 1);
 789         end = ((void *)drhd) + header->length;
 790
 791         while (start < end) {
 792                 scope = start;
 793                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 794                         if (ir_ioapic_num == MAX_IO_APICS) {
 795                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 796                                 return -1;
 797                         }
 798
 799                         printk(KERN_INFO "IOAPIC id %d under DRHD base "
 800                                " 0x%Lx IOMMU %d\n", scope->enumeration_id,
 801                                drhd->address, iommu->seq_id);
 802
 803                         ir_parse_one_ioapic_scope(scope, iommu);
 804                 } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
 805                         if (ir_hpet_num == MAX_HPET_TBS) {
 806                                 printk(KERN_WARNING "Exceeded Max HPET blocks\n");
 807                                 return -1;
 808                         }
 809
 810                         printk(KERN_INFO "HPET id %d under DRHD base"
 811                                " 0x%Lx\n", scope->enumeration_id,
 812                                drhd->address);
 813
 814                         ir_parse_one_hpet_scope(scope, iommu);
 815                 }
 816                 start += scope->length;
 817         }
 818
 819         return 0;
 820 }
 821
 822 /*
 823  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 824  * hardware unit.
 825  */
 826 int __init parse_ioapics_under_ir(void)
 827 {
 828         struct dmar_drhd_unit *drhd;
 829         int ir_supported = 0;
 830
 831         for_each_drhd_unit(drhd) {
 832                 struct intel_iommu *iommu = drhd->iommu;
 833
 834                 if (ecap_ir_support(iommu->ecap)) {
 835                         if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
 836                                 return -1;
 837
 838                         ir_supported = 1;
 839                 }
 840         }
 841
 842         if (ir_supported && ir_ioapic_num != nr_ioapics) {
 843                 printk(KERN_WARNING
 844                        "Not all IO-APIC's listed under remapping hardware\n");
 845                 return -1;
 846         }
 847
 848         return ir_supported;
 849 }
 850
 851 void disable_intr_remapping(void)
 852 {
 853         struct dmar_drhd_unit *drhd;
 854         struct intel_iommu *iommu = NULL;
 855
 856         /*
 857          * Disable Interrupt-remapping for all the DRHD's now.
 858          */
 859         for_each_iommu(iommu, drhd) {
 860                 if (!ecap_ir_support(iommu->ecap))
 861                         continue;
 862
 863                 iommu_disable_intr_remapping(iommu);
 864         }
 865 }
 866
 867 int reenable_intr_remapping(int eim)
 868 {
 869         struct dmar_drhd_unit *drhd;
 870         int setup = 0;
 871         struct intel_iommu *iommu = NULL;
 872
 873         for_each_iommu(iommu, drhd)
 874                 if (iommu->qi)
 875                         dmar_reenable_qi(iommu);
 876
 877         /*
 878          * Setup Interrupt-remapping for all the DRHD's now.
 879          */
 880         for_each_iommu(iommu, drhd) {
 881                 if (!ecap_ir_support(iommu->ecap))
 882                         continue;
 883
 884                 /* Set up interrupt remapping for iommu.*/
 885                 iommu_set_intr_remapping(iommu, eim);
 886                 setup = 1;
 887         }
 888
 889         if (!setup)
 890                 goto error;
 891
 892         return 0;
 893
 894 error:
 895         /*
 896          * handle error condition gracefully here!
 897          */
 898         return -1;
 899 }
 900