2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
44 #define ROOT_SIZE VTD_PAGE_SIZE
45 #define CONTEXT_SIZE VTD_PAGE_SIZE
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50 #define IOAPIC_RANGE_START (0xfee00000)
51 #define IOAPIC_RANGE_END (0xfeefffff)
52 #define IOVA_START_ADDR (0x1000)
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56 #define MAX_AGAW_WIDTH 64
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
59 #define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
61 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
62 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
63 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67 are never going to work. */
68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
70 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
75 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
77 static inline unsigned long page_to_dma_pfn(struct page *pg)
79 return mm_to_dma_pfn(page_to_pfn(pg));
81 static inline unsigned long virt_to_dma_pfn(void *p)
83 return page_to_dma_pfn(virt_to_page(p));
86 /* global iommu list, set NULL for ignored DMAR units */
87 static struct intel_iommu **g_iommus;
89 static int rwbf_quirk;
94 * 12-63: Context Ptr (12 - (haw-1))
101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102 static inline bool root_present(struct root_entry *root)
104 return (root->val & 1);
106 static inline void set_root_present(struct root_entry *root)
110 static inline void set_root_value(struct root_entry *root, unsigned long value)
112 root->val |= value & VTD_PAGE_MASK;
115 static inline struct context_entry *
116 get_context_addr_from_root(struct root_entry *root)
118 return (struct context_entry *)
119 (root_present(root)?phys_to_virt(
120 root->val & VTD_PAGE_MASK) :
127 * 1: fault processing disable
128 * 2-3: translation type
129 * 12-63: address space root
135 struct context_entry {
140 static inline bool context_present(struct context_entry *context)
142 return (context->lo & 1);
144 static inline void context_set_present(struct context_entry *context)
149 static inline void context_set_fault_enable(struct context_entry *context)
151 context->lo &= (((u64)-1) << 2) | 1;
154 static inline void context_set_translation_type(struct context_entry *context,
157 context->lo &= (((u64)-1) << 4) | 3;
158 context->lo |= (value & 3) << 2;
161 static inline void context_set_address_root(struct context_entry *context,
164 context->lo |= value & VTD_PAGE_MASK;
167 static inline void context_set_address_width(struct context_entry *context,
170 context->hi |= value & 7;
173 static inline void context_set_domain_id(struct context_entry *context,
176 context->hi |= (value & ((1 << 16) - 1)) << 8;
179 static inline void context_clear_entry(struct context_entry *context)
192 * 12-63: Host physcial address
198 static inline void dma_clear_pte(struct dma_pte *pte)
203 static inline void dma_set_pte_readable(struct dma_pte *pte)
205 pte->val |= DMA_PTE_READ;
208 static inline void dma_set_pte_writable(struct dma_pte *pte)
210 pte->val |= DMA_PTE_WRITE;
213 static inline void dma_set_pte_snp(struct dma_pte *pte)
215 pte->val |= DMA_PTE_SNP;
218 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
220 pte->val = (pte->val & ~3) | (prot & 3);
223 static inline u64 dma_pte_addr(struct dma_pte *pte)
226 return pte->val & VTD_PAGE_MASK;
228 /* Must have a full atomic 64-bit read */
229 return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
233 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
235 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
238 static inline bool dma_pte_present(struct dma_pte *pte)
240 return (pte->val & 3) != 0;
243 static inline int first_pte_in_page(struct dma_pte *pte)
245 return !((unsigned long)pte & ~VTD_PAGE_MASK);
249 * This domain is a statically identity mapping domain.
250 * 1. This domain creats a static 1:1 mapping to all usable memory.
251 * 2. It maps to each iommu if successful.
252 * 3. Each iommu mapps to this domain if successful.
254 static struct dmar_domain *si_domain;
255 static int hw_pass_through = 1;
257 /* devices under the same p2p bridge are owned in one domain */
258 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
260 /* domain represents a virtual machine, more than one devices
261 * across iommus may be owned in one domain, e.g. kvm guest.
263 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
265 /* si_domain contains mulitple devices */
266 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
269 int id; /* domain id */
270 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
272 struct list_head devices; /* all devices' list */
273 struct iova_domain iovad; /* iova's that belong to this domain */
275 struct dma_pte *pgd; /* virtual address */
276 int gaw; /* max guest address width */
278 /* adjusted guest address width, 0 is level 2 30-bit */
281 int flags; /* flags to find out type of domain */
283 int iommu_coherency;/* indicate coherency of iommu access */
284 int iommu_snooping; /* indicate snooping control feature*/
285 int iommu_count; /* reference count of iommu */
286 spinlock_t iommu_lock; /* protect iommu set in domain */
287 u64 max_addr; /* maximum mapped address */
290 /* PCI domain-device relationship */
291 struct device_domain_info {
292 struct list_head link; /* link to domain siblings */
293 struct list_head global; /* link to global list */
294 int segment; /* PCI domain */
295 u8 bus; /* PCI bus number */
296 u8 devfn; /* PCI devfn number */
297 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
298 struct intel_iommu *iommu; /* IOMMU used by this device */
299 struct dmar_domain *domain; /* pointer to domain */
302 static void flush_unmaps_timeout(unsigned long data);
304 DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
306 #define HIGH_WATER_MARK 250
307 struct deferred_flush_tables {
309 struct iova *iova[HIGH_WATER_MARK];
310 struct dmar_domain *domain[HIGH_WATER_MARK];
313 static struct deferred_flush_tables *deferred_flush;
315 /* bitmap for indexing intel_iommus */
316 static int g_num_of_iommus;
318 static DEFINE_SPINLOCK(async_umap_flush_lock);
319 static LIST_HEAD(unmaps_to_do);
322 static long list_size;
324 static void domain_remove_dev_info(struct dmar_domain *domain);
326 #ifdef CONFIG_DMAR_DEFAULT_ON
327 int dmar_disabled = 0;
329 int dmar_disabled = 1;
330 #endif /*CONFIG_DMAR_DEFAULT_ON*/
332 static int __initdata dmar_map_gfx = 1;
333 static int dmar_forcedac;
334 static int intel_iommu_strict;
336 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
337 static DEFINE_SPINLOCK(device_domain_lock);
338 static LIST_HEAD(device_domain_list);
340 static struct iommu_ops intel_iommu_ops;
342 static int __init intel_iommu_setup(char *str)
347 if (!strncmp(str, "on", 2)) {
349 printk(KERN_INFO "Intel-IOMMU: enabled\n");
350 } else if (!strncmp(str, "off", 3)) {
352 printk(KERN_INFO "Intel-IOMMU: disabled\n");
353 } else if (!strncmp(str, "igfx_off", 8)) {
356 "Intel-IOMMU: disable GFX device mapping\n");
357 } else if (!strncmp(str, "forcedac", 8)) {
359 "Intel-IOMMU: Forcing DAC for PCI devices\n");
361 } else if (!strncmp(str, "strict", 6)) {
363 "Intel-IOMMU: disable batched IOTLB flush\n");
364 intel_iommu_strict = 1;
367 str += strcspn(str, ",");
373 __setup("intel_iommu=", intel_iommu_setup);
375 static struct kmem_cache *iommu_domain_cache;
376 static struct kmem_cache *iommu_devinfo_cache;
377 static struct kmem_cache *iommu_iova_cache;
379 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
384 /* trying to avoid low memory issues */
385 flags = current->flags & PF_MEMALLOC;
386 current->flags |= PF_MEMALLOC;
387 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
388 current->flags &= (~PF_MEMALLOC | flags);
393 static inline void *alloc_pgtable_page(void)
398 /* trying to avoid low memory issues */
399 flags = current->flags & PF_MEMALLOC;
400 current->flags |= PF_MEMALLOC;
401 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
402 current->flags &= (~PF_MEMALLOC | flags);
406 static inline void free_pgtable_page(void *vaddr)
408 free_page((unsigned long)vaddr);
411 static inline void *alloc_domain_mem(void)
413 return iommu_kmem_cache_alloc(iommu_domain_cache);
416 static void free_domain_mem(void *vaddr)
418 kmem_cache_free(iommu_domain_cache, vaddr);
421 static inline void * alloc_devinfo_mem(void)
423 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
426 static inline void free_devinfo_mem(void *vaddr)
428 kmem_cache_free(iommu_devinfo_cache, vaddr);
431 struct iova *alloc_iova_mem(void)
433 return iommu_kmem_cache_alloc(iommu_iova_cache);
436 void free_iova_mem(struct iova *iova)
438 kmem_cache_free(iommu_iova_cache, iova);
442 static inline int width_to_agaw(int width);
444 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
449 sagaw = cap_sagaw(iommu->cap);
450 for (agaw = width_to_agaw(max_gaw);
452 if (test_bit(agaw, &sagaw))
460 * Calculate max SAGAW for each iommu.
462 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
464 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
468 * calculate agaw for each iommu.
469 * "SAGAW" may be different across iommus, use a default agaw, and
470 * get a supported less agaw for iommus that don't support the default agaw.
472 int iommu_calculate_agaw(struct intel_iommu *iommu)
474 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
477 /* This functionin only returns single iommu in a domain */
478 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
482 /* si_domain and vm domain should not get here. */
483 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
484 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
486 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
487 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
490 return g_iommus[iommu_id];
493 static void domain_update_iommu_coherency(struct dmar_domain *domain)
497 domain->iommu_coherency = 1;
499 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
500 for (; i < g_num_of_iommus; ) {
501 if (!ecap_coherent(g_iommus[i]->ecap)) {
502 domain->iommu_coherency = 0;
505 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
509 static void domain_update_iommu_snooping(struct dmar_domain *domain)
513 domain->iommu_snooping = 1;
515 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
516 for (; i < g_num_of_iommus; ) {
517 if (!ecap_sc_support(g_iommus[i]->ecap)) {
518 domain->iommu_snooping = 0;
521 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
525 /* Some capabilities may be different across iommus */
526 static void domain_update_iommu_cap(struct dmar_domain *domain)
528 domain_update_iommu_coherency(domain);
529 domain_update_iommu_snooping(domain);
532 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
534 struct dmar_drhd_unit *drhd = NULL;
537 for_each_drhd_unit(drhd) {
540 if (segment != drhd->segment)
543 for (i = 0; i < drhd->devices_cnt; i++) {
544 if (drhd->devices[i] &&
545 drhd->devices[i]->bus->number == bus &&
546 drhd->devices[i]->devfn == devfn)
548 if (drhd->devices[i] &&
549 drhd->devices[i]->subordinate &&
550 drhd->devices[i]->subordinate->number <= bus &&
551 drhd->devices[i]->subordinate->subordinate >= bus)
555 if (drhd->include_all)
562 static void domain_flush_cache(struct dmar_domain *domain,
563 void *addr, int size)
565 if (!domain->iommu_coherency)
566 clflush_cache_range(addr, size);
569 /* Gets context entry for a given bus and devfn */
570 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
573 struct root_entry *root;
574 struct context_entry *context;
575 unsigned long phy_addr;
578 spin_lock_irqsave(&iommu->lock, flags);
579 root = &iommu->root_entry[bus];
580 context = get_context_addr_from_root(root);
582 context = (struct context_entry *)alloc_pgtable_page();
584 spin_unlock_irqrestore(&iommu->lock, flags);
587 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
588 phy_addr = virt_to_phys((void *)context);
589 set_root_value(root, phy_addr);
590 set_root_present(root);
591 __iommu_flush_cache(iommu, root, sizeof(*root));
593 spin_unlock_irqrestore(&iommu->lock, flags);
594 return &context[devfn];
597 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
599 struct root_entry *root;
600 struct context_entry *context;
604 spin_lock_irqsave(&iommu->lock, flags);
605 root = &iommu->root_entry[bus];
606 context = get_context_addr_from_root(root);
611 ret = context_present(&context[devfn]);
613 spin_unlock_irqrestore(&iommu->lock, flags);
617 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
619 struct root_entry *root;
620 struct context_entry *context;
623 spin_lock_irqsave(&iommu->lock, flags);
624 root = &iommu->root_entry[bus];
625 context = get_context_addr_from_root(root);
627 context_clear_entry(&context[devfn]);
628 __iommu_flush_cache(iommu, &context[devfn], \
631 spin_unlock_irqrestore(&iommu->lock, flags);
634 static void free_context_table(struct intel_iommu *iommu)
636 struct root_entry *root;
639 struct context_entry *context;
641 spin_lock_irqsave(&iommu->lock, flags);
642 if (!iommu->root_entry) {
645 for (i = 0; i < ROOT_ENTRY_NR; i++) {
646 root = &iommu->root_entry[i];
647 context = get_context_addr_from_root(root);
649 free_pgtable_page(context);
651 free_pgtable_page(iommu->root_entry);
652 iommu->root_entry = NULL;
654 spin_unlock_irqrestore(&iommu->lock, flags);
657 /* page table handling */
658 #define LEVEL_STRIDE (9)
659 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
661 static inline int agaw_to_level(int agaw)
666 static inline int agaw_to_width(int agaw)
668 return 30 + agaw * LEVEL_STRIDE;
672 static inline int width_to_agaw(int width)
674 return (width - 30) / LEVEL_STRIDE;
677 static inline unsigned int level_to_offset_bits(int level)
679 return (level - 1) * LEVEL_STRIDE;
682 static inline int pfn_level_offset(unsigned long pfn, int level)
684 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
687 static inline unsigned long level_mask(int level)
689 return -1UL << level_to_offset_bits(level);
692 static inline unsigned long level_size(int level)
694 return 1UL << level_to_offset_bits(level);
697 static inline unsigned long align_to_level(unsigned long pfn, int level)
699 return (pfn + level_size(level) - 1) & level_mask(level);
702 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
705 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
706 struct dma_pte *parent, *pte = NULL;
707 int level = agaw_to_level(domain->agaw);
710 BUG_ON(!domain->pgd);
711 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
712 parent = domain->pgd;
717 offset = pfn_level_offset(pfn, level);
718 pte = &parent[offset];
722 if (!dma_pte_present(pte)) {
725 tmp_page = alloc_pgtable_page();
730 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
731 pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
732 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
733 /* Someone else set it while we were thinking; use theirs. */
734 free_pgtable_page(tmp_page);
737 domain_flush_cache(domain, pte, sizeof(*pte));
740 parent = phys_to_virt(dma_pte_addr(pte));
747 /* return address's pte at specific level */
748 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
752 struct dma_pte *parent, *pte = NULL;
753 int total = agaw_to_level(domain->agaw);
756 parent = domain->pgd;
757 while (level <= total) {
758 offset = pfn_level_offset(pfn, total);
759 pte = &parent[offset];
763 if (!dma_pte_present(pte))
765 parent = phys_to_virt(dma_pte_addr(pte));
771 /* clear last level pte, a tlb flush should be followed */
772 static void dma_pte_clear_range(struct dmar_domain *domain,
773 unsigned long start_pfn,
774 unsigned long last_pfn)
776 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
777 struct dma_pte *first_pte, *pte;
779 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
780 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
782 /* we don't need lock here; nobody else touches the iova range */
783 while (start_pfn <= last_pfn) {
784 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
786 start_pfn = align_to_level(start_pfn + 1, 2);
793 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
795 domain_flush_cache(domain, first_pte,
796 (void *)pte - (void *)first_pte);
800 /* free page table pages. last level pte should already be cleared */
801 static void dma_pte_free_pagetable(struct dmar_domain *domain,
802 unsigned long start_pfn,
803 unsigned long last_pfn)
805 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
806 struct dma_pte *first_pte, *pte;
807 int total = agaw_to_level(domain->agaw);
811 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
812 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
814 /* We don't need lock here; nobody else touches the iova range */
816 while (level <= total) {
817 tmp = align_to_level(start_pfn, level);
819 /* If we can't even clear one PTE at this level, we're done */
820 if (tmp + level_size(level) - 1 > last_pfn)
823 while (tmp + level_size(level) - 1 <= last_pfn) {
824 first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
826 tmp = align_to_level(tmp + 1, level + 1);
830 if (dma_pte_present(pte)) {
831 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
835 tmp += level_size(level);
836 } while (!first_pte_in_page(pte) &&
837 tmp + level_size(level) - 1 <= last_pfn);
839 domain_flush_cache(domain, first_pte,
840 (void *)pte - (void *)first_pte);
846 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
847 free_pgtable_page(domain->pgd);
853 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
855 struct root_entry *root;
858 root = (struct root_entry *)alloc_pgtable_page();
862 __iommu_flush_cache(iommu, root, ROOT_SIZE);
864 spin_lock_irqsave(&iommu->lock, flags);
865 iommu->root_entry = root;
866 spin_unlock_irqrestore(&iommu->lock, flags);
871 static void iommu_set_root_entry(struct intel_iommu *iommu)
877 addr = iommu->root_entry;
879 spin_lock_irqsave(&iommu->register_lock, flag);
880 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
882 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
884 /* Make sure hardware complete it */
885 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
886 readl, (sts & DMA_GSTS_RTPS), sts);
888 spin_unlock_irqrestore(&iommu->register_lock, flag);
891 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
896 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
899 spin_lock_irqsave(&iommu->register_lock, flag);
900 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
902 /* Make sure hardware complete it */
903 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
904 readl, (!(val & DMA_GSTS_WBFS)), val);
906 spin_unlock_irqrestore(&iommu->register_lock, flag);
909 /* return value determine if we need a write buffer flush */
910 static void __iommu_flush_context(struct intel_iommu *iommu,
911 u16 did, u16 source_id, u8 function_mask,
918 case DMA_CCMD_GLOBAL_INVL:
919 val = DMA_CCMD_GLOBAL_INVL;
921 case DMA_CCMD_DOMAIN_INVL:
922 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
924 case DMA_CCMD_DEVICE_INVL:
925 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
926 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
933 spin_lock_irqsave(&iommu->register_lock, flag);
934 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
936 /* Make sure hardware complete it */
937 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
938 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
940 spin_unlock_irqrestore(&iommu->register_lock, flag);
943 /* return value determine if we need a write buffer flush */
944 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
945 u64 addr, unsigned int size_order, u64 type)
947 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
948 u64 val = 0, val_iva = 0;
952 case DMA_TLB_GLOBAL_FLUSH:
953 /* global flush doesn't need set IVA_REG */
954 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
956 case DMA_TLB_DSI_FLUSH:
957 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
959 case DMA_TLB_PSI_FLUSH:
960 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
961 /* Note: always flush non-leaf currently */
962 val_iva = size_order | addr;
967 /* Note: set drain read/write */
970 * This is probably to be super secure.. Looks like we can
971 * ignore it without any impact.
973 if (cap_read_drain(iommu->cap))
974 val |= DMA_TLB_READ_DRAIN;
976 if (cap_write_drain(iommu->cap))
977 val |= DMA_TLB_WRITE_DRAIN;
979 spin_lock_irqsave(&iommu->register_lock, flag);
980 /* Note: Only uses first TLB reg currently */
982 dmar_writeq(iommu->reg + tlb_offset, val_iva);
983 dmar_writeq(iommu->reg + tlb_offset + 8, val);
985 /* Make sure hardware complete it */
986 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
987 dmar_readq, (!(val & DMA_TLB_IVT)), val);
989 spin_unlock_irqrestore(&iommu->register_lock, flag);
991 /* check IOTLB invalidation granularity */
992 if (DMA_TLB_IAIG(val) == 0)
993 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
994 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
995 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
996 (unsigned long long)DMA_TLB_IIRG(type),
997 (unsigned long long)DMA_TLB_IAIG(val));
1000 static struct device_domain_info *iommu_support_dev_iotlb(
1001 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1004 unsigned long flags;
1005 struct device_domain_info *info;
1006 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1008 if (!ecap_dev_iotlb_support(iommu->ecap))
1014 spin_lock_irqsave(&device_domain_lock, flags);
1015 list_for_each_entry(info, &domain->devices, link)
1016 if (info->bus == bus && info->devfn == devfn) {
1020 spin_unlock_irqrestore(&device_domain_lock, flags);
1022 if (!found || !info->dev)
1025 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1028 if (!dmar_find_matched_atsr_unit(info->dev))
1031 info->iommu = iommu;
1036 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1041 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1044 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1046 if (!info->dev || !pci_ats_enabled(info->dev))
1049 pci_disable_ats(info->dev);
1052 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1053 u64 addr, unsigned mask)
1056 unsigned long flags;
1057 struct device_domain_info *info;
1059 spin_lock_irqsave(&device_domain_lock, flags);
1060 list_for_each_entry(info, &domain->devices, link) {
1061 if (!info->dev || !pci_ats_enabled(info->dev))
1064 sid = info->bus << 8 | info->devfn;
1065 qdep = pci_ats_queue_depth(info->dev);
1066 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1068 spin_unlock_irqrestore(&device_domain_lock, flags);
1071 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1072 unsigned long pfn, unsigned int pages)
1074 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1075 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1080 * Fallback to domain selective flush if no PSI support or the size is
1082 * PSI requires page size to be 2 ^ x, and the base address is naturally
1083 * aligned to the size
1085 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1086 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1089 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1093 * In caching mode, domain ID 0 is reserved for non-present to present
1094 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1096 if (!cap_caching_mode(iommu->cap) || did)
1097 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1100 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1103 unsigned long flags;
1105 spin_lock_irqsave(&iommu->register_lock, flags);
1106 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1107 pmen &= ~DMA_PMEN_EPM;
1108 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1110 /* wait for the protected region status bit to clear */
1111 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1112 readl, !(pmen & DMA_PMEN_PRS), pmen);
1114 spin_unlock_irqrestore(&iommu->register_lock, flags);
1117 static int iommu_enable_translation(struct intel_iommu *iommu)
1120 unsigned long flags;
1122 spin_lock_irqsave(&iommu->register_lock, flags);
1123 iommu->gcmd |= DMA_GCMD_TE;
1124 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1126 /* Make sure hardware complete it */
1127 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1128 readl, (sts & DMA_GSTS_TES), sts);
1130 spin_unlock_irqrestore(&iommu->register_lock, flags);
1134 static int iommu_disable_translation(struct intel_iommu *iommu)
1139 spin_lock_irqsave(&iommu->register_lock, flag);
1140 iommu->gcmd &= ~DMA_GCMD_TE;
1141 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1143 /* Make sure hardware complete it */
1144 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1145 readl, (!(sts & DMA_GSTS_TES)), sts);
1147 spin_unlock_irqrestore(&iommu->register_lock, flag);
1152 static int iommu_init_domains(struct intel_iommu *iommu)
1154 unsigned long ndomains;
1155 unsigned long nlongs;
1157 ndomains = cap_ndoms(iommu->cap);
1158 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1159 nlongs = BITS_TO_LONGS(ndomains);
1161 /* TBD: there might be 64K domains,
1162 * consider other allocation for future chip
1164 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1165 if (!iommu->domain_ids) {
1166 printk(KERN_ERR "Allocating domain id array failed\n");
1169 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1171 if (!iommu->domains) {
1172 printk(KERN_ERR "Allocating domain array failed\n");
1173 kfree(iommu->domain_ids);
1177 spin_lock_init(&iommu->lock);
1180 * if Caching mode is set, then invalid translations are tagged
1181 * with domainid 0. Hence we need to pre-allocate it.
1183 if (cap_caching_mode(iommu->cap))
1184 set_bit(0, iommu->domain_ids);
1189 static void domain_exit(struct dmar_domain *domain);
1190 static void vm_domain_exit(struct dmar_domain *domain);
1192 void free_dmar_iommu(struct intel_iommu *iommu)
1194 struct dmar_domain *domain;
1196 unsigned long flags;
1198 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1199 for (; i < cap_ndoms(iommu->cap); ) {
1200 domain = iommu->domains[i];
1201 clear_bit(i, iommu->domain_ids);
1203 spin_lock_irqsave(&domain->iommu_lock, flags);
1204 if (--domain->iommu_count == 0) {
1205 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1206 vm_domain_exit(domain);
1208 domain_exit(domain);
1210 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1212 i = find_next_bit(iommu->domain_ids,
1213 cap_ndoms(iommu->cap), i+1);
1216 if (iommu->gcmd & DMA_GCMD_TE)
1217 iommu_disable_translation(iommu);
1220 set_irq_data(iommu->irq, NULL);
1221 /* This will mask the irq */
1222 free_irq(iommu->irq, iommu);
1223 destroy_irq(iommu->irq);
1226 kfree(iommu->domains);
1227 kfree(iommu->domain_ids);
1229 g_iommus[iommu->seq_id] = NULL;
1231 /* if all iommus are freed, free g_iommus */
1232 for (i = 0; i < g_num_of_iommus; i++) {
1237 if (i == g_num_of_iommus)
1240 /* free context mapping */
1241 free_context_table(iommu);
1244 static struct dmar_domain *alloc_domain(void)
1246 struct dmar_domain *domain;
1248 domain = alloc_domain_mem();
1252 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1258 static int iommu_attach_domain(struct dmar_domain *domain,
1259 struct intel_iommu *iommu)
1262 unsigned long ndomains;
1263 unsigned long flags;
1265 ndomains = cap_ndoms(iommu->cap);
1267 spin_lock_irqsave(&iommu->lock, flags);
1269 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1270 if (num >= ndomains) {
1271 spin_unlock_irqrestore(&iommu->lock, flags);
1272 printk(KERN_ERR "IOMMU: no free domain ids\n");
1277 set_bit(num, iommu->domain_ids);
1278 set_bit(iommu->seq_id, &domain->iommu_bmp);
1279 iommu->domains[num] = domain;
1280 spin_unlock_irqrestore(&iommu->lock, flags);
1285 static void iommu_detach_domain(struct dmar_domain *domain,
1286 struct intel_iommu *iommu)
1288 unsigned long flags;
1292 spin_lock_irqsave(&iommu->lock, flags);
1293 ndomains = cap_ndoms(iommu->cap);
1294 num = find_first_bit(iommu->domain_ids, ndomains);
1295 for (; num < ndomains; ) {
1296 if (iommu->domains[num] == domain) {
1300 num = find_next_bit(iommu->domain_ids,
1301 cap_ndoms(iommu->cap), num+1);
1305 clear_bit(num, iommu->domain_ids);
1306 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1307 iommu->domains[num] = NULL;
1309 spin_unlock_irqrestore(&iommu->lock, flags);
1312 static struct iova_domain reserved_iova_list;
1313 static struct lock_class_key reserved_rbtree_key;
1315 static void dmar_init_reserved_ranges(void)
1317 struct pci_dev *pdev = NULL;
1321 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1323 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1324 &reserved_rbtree_key);
1326 /* IOAPIC ranges shouldn't be accessed by DMA */
1327 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1328 IOVA_PFN(IOAPIC_RANGE_END));
1330 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1332 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1333 for_each_pci_dev(pdev) {
1336 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1337 r = &pdev->resource[i];
1338 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1340 iova = reserve_iova(&reserved_iova_list,
1344 printk(KERN_ERR "Reserve iova failed\n");
1350 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1352 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1355 static inline int guestwidth_to_adjustwidth(int gaw)
1358 int r = (gaw - 12) % 9;
1369 static int domain_init(struct dmar_domain *domain, int guest_width)
1371 struct intel_iommu *iommu;
1372 int adjust_width, agaw;
1373 unsigned long sagaw;
1375 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1376 spin_lock_init(&domain->iommu_lock);
1378 domain_reserve_special_ranges(domain);
1380 /* calculate AGAW */
1381 iommu = domain_get_iommu(domain);
1382 if (guest_width > cap_mgaw(iommu->cap))
1383 guest_width = cap_mgaw(iommu->cap);
1384 domain->gaw = guest_width;
1385 adjust_width = guestwidth_to_adjustwidth(guest_width);
1386 agaw = width_to_agaw(adjust_width);
1387 sagaw = cap_sagaw(iommu->cap);
1388 if (!test_bit(agaw, &sagaw)) {
1389 /* hardware doesn't support it, choose a bigger one */
1390 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1391 agaw = find_next_bit(&sagaw, 5, agaw);
1395 domain->agaw = agaw;
1396 INIT_LIST_HEAD(&domain->devices);
1398 if (ecap_coherent(iommu->ecap))
1399 domain->iommu_coherency = 1;
1401 domain->iommu_coherency = 0;
1403 if (ecap_sc_support(iommu->ecap))
1404 domain->iommu_snooping = 1;
1406 domain->iommu_snooping = 0;
1408 domain->iommu_count = 1;
1410 /* always allocate the top pgd */
1411 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1414 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1418 static void domain_exit(struct dmar_domain *domain)
1420 struct dmar_drhd_unit *drhd;
1421 struct intel_iommu *iommu;
1423 /* Domain 0 is reserved, so dont process it */
1427 domain_remove_dev_info(domain);
1429 put_iova_domain(&domain->iovad);
1432 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1434 /* free page tables */
1435 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1437 for_each_active_iommu(iommu, drhd)
1438 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1439 iommu_detach_domain(domain, iommu);
1441 free_domain_mem(domain);
1444 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1445 u8 bus, u8 devfn, int translation)
1447 struct context_entry *context;
1448 unsigned long flags;
1449 struct intel_iommu *iommu;
1450 struct dma_pte *pgd;
1452 unsigned long ndomains;
1455 struct device_domain_info *info = NULL;
1457 pr_debug("Set context mapping for %02x:%02x.%d\n",
1458 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1460 BUG_ON(!domain->pgd);
1461 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1462 translation != CONTEXT_TT_MULTI_LEVEL);
1464 iommu = device_to_iommu(segment, bus, devfn);
1468 context = device_to_context_entry(iommu, bus, devfn);
1471 spin_lock_irqsave(&iommu->lock, flags);
1472 if (context_present(context)) {
1473 spin_unlock_irqrestore(&iommu->lock, flags);
1480 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1481 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1484 /* find an available domain id for this device in iommu */
1485 ndomains = cap_ndoms(iommu->cap);
1486 num = find_first_bit(iommu->domain_ids, ndomains);
1487 for (; num < ndomains; ) {
1488 if (iommu->domains[num] == domain) {
1493 num = find_next_bit(iommu->domain_ids,
1494 cap_ndoms(iommu->cap), num+1);
1498 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1499 if (num >= ndomains) {
1500 spin_unlock_irqrestore(&iommu->lock, flags);
1501 printk(KERN_ERR "IOMMU: no free domain ids\n");
1505 set_bit(num, iommu->domain_ids);
1506 iommu->domains[num] = domain;
1510 /* Skip top levels of page tables for
1511 * iommu which has less agaw than default.
1513 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1514 pgd = phys_to_virt(dma_pte_addr(pgd));
1515 if (!dma_pte_present(pgd)) {
1516 spin_unlock_irqrestore(&iommu->lock, flags);
1522 context_set_domain_id(context, id);
1524 if (translation != CONTEXT_TT_PASS_THROUGH) {
1525 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1526 translation = info ? CONTEXT_TT_DEV_IOTLB :
1527 CONTEXT_TT_MULTI_LEVEL;
1530 * In pass through mode, AW must be programmed to indicate the largest
1531 * AGAW value supported by hardware. And ASR is ignored by hardware.
1533 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1534 context_set_address_width(context, iommu->msagaw);
1536 context_set_address_root(context, virt_to_phys(pgd));
1537 context_set_address_width(context, iommu->agaw);
1540 context_set_translation_type(context, translation);
1541 context_set_fault_enable(context);
1542 context_set_present(context);
1543 domain_flush_cache(domain, context, sizeof(*context));
1546 * It's a non-present to present mapping. If hardware doesn't cache
1547 * non-present entry we only need to flush the write-buffer. If the
1548 * _does_ cache non-present entries, then it does so in the special
1549 * domain #0, which we have to flush:
1551 if (cap_caching_mode(iommu->cap)) {
1552 iommu->flush.flush_context(iommu, 0,
1553 (((u16)bus) << 8) | devfn,
1554 DMA_CCMD_MASK_NOBIT,
1555 DMA_CCMD_DEVICE_INVL);
1556 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1558 iommu_flush_write_buffer(iommu);
1560 iommu_enable_dev_iotlb(info);
1561 spin_unlock_irqrestore(&iommu->lock, flags);
1563 spin_lock_irqsave(&domain->iommu_lock, flags);
1564 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1565 domain->iommu_count++;
1566 domain_update_iommu_cap(domain);
1568 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1573 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1577 struct pci_dev *tmp, *parent;
1579 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1580 pdev->bus->number, pdev->devfn,
1585 /* dependent device mapping */
1586 tmp = pci_find_upstream_pcie_bridge(pdev);
1589 /* Secondary interface's bus number and devfn 0 */
1590 parent = pdev->bus->self;
1591 while (parent != tmp) {
1592 ret = domain_context_mapping_one(domain,
1593 pci_domain_nr(parent->bus),
1594 parent->bus->number,
1595 parent->devfn, translation);
1598 parent = parent->bus->self;
1600 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1601 return domain_context_mapping_one(domain,
1602 pci_domain_nr(tmp->subordinate),
1603 tmp->subordinate->number, 0,
1605 else /* this is a legacy PCI bridge */
1606 return domain_context_mapping_one(domain,
1607 pci_domain_nr(tmp->bus),
1613 static int domain_context_mapped(struct pci_dev *pdev)
1616 struct pci_dev *tmp, *parent;
1617 struct intel_iommu *iommu;
1619 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1624 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1627 /* dependent device mapping */
1628 tmp = pci_find_upstream_pcie_bridge(pdev);
1631 /* Secondary interface's bus number and devfn 0 */
1632 parent = pdev->bus->self;
1633 while (parent != tmp) {
1634 ret = device_context_mapped(iommu, parent->bus->number,
1638 parent = parent->bus->self;
1641 return device_context_mapped(iommu, tmp->subordinate->number,
1644 return device_context_mapped(iommu, tmp->bus->number,
1648 /* Returns a number of VTD pages, but aligned to MM page size */
1649 static inline unsigned long aligned_nrpages(unsigned long host_addr,
1652 host_addr &= ~PAGE_MASK;
1653 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1656 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1657 struct scatterlist *sg, unsigned long phys_pfn,
1658 unsigned long nr_pages, int prot)
1660 struct dma_pte *first_pte = NULL, *pte = NULL;
1661 phys_addr_t uninitialized_var(pteval);
1662 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1663 unsigned long sg_res;
1665 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1667 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1670 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1675 sg_res = nr_pages + 1;
1676 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1679 while (nr_pages--) {
1683 sg_res = aligned_nrpages(sg->offset, sg->length);
1684 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1685 sg->dma_length = sg->length;
1686 pteval = page_to_phys(sg_page(sg)) | prot;
1689 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1693 /* We don't need lock here, nobody else
1694 * touches the iova range
1696 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1698 static int dumps = 5;
1699 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1700 iov_pfn, tmp, (unsigned long long)pteval);
1703 debug_dma_dump_mappings(NULL);
1708 if (!nr_pages || first_pte_in_page(pte)) {
1709 domain_flush_cache(domain, first_pte,
1710 (void *)pte - (void *)first_pte);
1714 pteval += VTD_PAGE_SIZE;
1722 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1723 struct scatterlist *sg, unsigned long nr_pages,
1726 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1729 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1730 unsigned long phys_pfn, unsigned long nr_pages,
1733 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1736 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1741 clear_context_table(iommu, bus, devfn);
1742 iommu->flush.flush_context(iommu, 0, 0, 0,
1743 DMA_CCMD_GLOBAL_INVL);
1744 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1747 static void domain_remove_dev_info(struct dmar_domain *domain)
1749 struct device_domain_info *info;
1750 unsigned long flags;
1751 struct intel_iommu *iommu;
1753 spin_lock_irqsave(&device_domain_lock, flags);
1754 while (!list_empty(&domain->devices)) {
1755 info = list_entry(domain->devices.next,
1756 struct device_domain_info, link);
1757 list_del(&info->link);
1758 list_del(&info->global);
1760 info->dev->dev.archdata.iommu = NULL;
1761 spin_unlock_irqrestore(&device_domain_lock, flags);
1763 iommu_disable_dev_iotlb(info);
1764 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1765 iommu_detach_dev(iommu, info->bus, info->devfn);
1766 free_devinfo_mem(info);
1768 spin_lock_irqsave(&device_domain_lock, flags);
1770 spin_unlock_irqrestore(&device_domain_lock, flags);
1775 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1777 static struct dmar_domain *
1778 find_domain(struct pci_dev *pdev)
1780 struct device_domain_info *info;
1782 /* No lock here, assumes no domain exit in normal case */
1783 info = pdev->dev.archdata.iommu;
1785 return info->domain;
1789 /* domain is initialized */
1790 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1792 struct dmar_domain *domain, *found = NULL;
1793 struct intel_iommu *iommu;
1794 struct dmar_drhd_unit *drhd;
1795 struct device_domain_info *info, *tmp;
1796 struct pci_dev *dev_tmp;
1797 unsigned long flags;
1798 int bus = 0, devfn = 0;
1802 domain = find_domain(pdev);
1806 segment = pci_domain_nr(pdev->bus);
1808 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1810 if (dev_tmp->is_pcie) {
1811 bus = dev_tmp->subordinate->number;
1814 bus = dev_tmp->bus->number;
1815 devfn = dev_tmp->devfn;
1817 spin_lock_irqsave(&device_domain_lock, flags);
1818 list_for_each_entry(info, &device_domain_list, global) {
1819 if (info->segment == segment &&
1820 info->bus == bus && info->devfn == devfn) {
1821 found = info->domain;
1825 spin_unlock_irqrestore(&device_domain_lock, flags);
1826 /* pcie-pci bridge already has a domain, uses it */
1833 domain = alloc_domain();
1837 /* Allocate new domain for the device */
1838 drhd = dmar_find_matched_drhd_unit(pdev);
1840 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1844 iommu = drhd->iommu;
1846 ret = iommu_attach_domain(domain, iommu);
1848 domain_exit(domain);
1852 if (domain_init(domain, gaw)) {
1853 domain_exit(domain);
1857 /* register pcie-to-pci device */
1859 info = alloc_devinfo_mem();
1861 domain_exit(domain);
1864 info->segment = segment;
1866 info->devfn = devfn;
1868 info->domain = domain;
1869 /* This domain is shared by devices under p2p bridge */
1870 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1872 /* pcie-to-pci bridge already has a domain, uses it */
1874 spin_lock_irqsave(&device_domain_lock, flags);
1875 list_for_each_entry(tmp, &device_domain_list, global) {
1876 if (tmp->segment == segment &&
1877 tmp->bus == bus && tmp->devfn == devfn) {
1878 found = tmp->domain;
1883 free_devinfo_mem(info);
1884 domain_exit(domain);
1887 list_add(&info->link, &domain->devices);
1888 list_add(&info->global, &device_domain_list);
1890 spin_unlock_irqrestore(&device_domain_lock, flags);
1894 info = alloc_devinfo_mem();
1897 info->segment = segment;
1898 info->bus = pdev->bus->number;
1899 info->devfn = pdev->devfn;
1901 info->domain = domain;
1902 spin_lock_irqsave(&device_domain_lock, flags);
1903 /* somebody is fast */
1904 found = find_domain(pdev);
1905 if (found != NULL) {
1906 spin_unlock_irqrestore(&device_domain_lock, flags);
1907 if (found != domain) {
1908 domain_exit(domain);
1911 free_devinfo_mem(info);
1914 list_add(&info->link, &domain->devices);
1915 list_add(&info->global, &device_domain_list);
1916 pdev->dev.archdata.iommu = info;
1917 spin_unlock_irqrestore(&device_domain_lock, flags);
1920 /* recheck it here, maybe others set it */
1921 return find_domain(pdev);
1924 static int iommu_identity_mapping;
1926 static int iommu_domain_identity_map(struct dmar_domain *domain,
1927 unsigned long long start,
1928 unsigned long long end)
1930 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1931 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1933 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1934 dma_to_mm_pfn(last_vpfn))) {
1935 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1939 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1940 start, end, domain->id);
1942 * RMRR range might have overlap with physical memory range,
1945 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1947 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1948 last_vpfn - first_vpfn + 1,
1949 DMA_PTE_READ|DMA_PTE_WRITE);
1952 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1953 unsigned long long start,
1954 unsigned long long end)
1956 struct dmar_domain *domain;
1959 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1963 /* For _hardware_ passthrough, don't bother. But for software
1964 passthrough, we do it anyway -- it may indicate a memory
1965 range which is reserved in E820, so which didn't get set
1966 up to start with in si_domain */
1967 if (domain == si_domain && hw_pass_through) {
1968 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
1969 pci_name(pdev), start, end);
1974 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1975 pci_name(pdev), start, end);
1977 ret = iommu_domain_identity_map(domain, start, end);
1981 /* context entry init */
1982 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1989 domain_exit(domain);
1993 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1994 struct pci_dev *pdev)
1996 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1998 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1999 rmrr->end_address + 1);
2002 #ifdef CONFIG_DMAR_FLOPPY_WA
2003 static inline void iommu_prepare_isa(void)
2005 struct pci_dev *pdev;
2008 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2012 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2013 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2016 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2017 "floppy might not work\n");
2021 static inline void iommu_prepare_isa(void)
2025 #endif /* !CONFIG_DMAR_FLPY_WA */
2027 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2029 static int __init si_domain_work_fn(unsigned long start_pfn,
2030 unsigned long end_pfn, void *datax)
2034 *ret = iommu_domain_identity_map(si_domain,
2035 (uint64_t)start_pfn << PAGE_SHIFT,
2036 (uint64_t)end_pfn << PAGE_SHIFT);
2041 static int si_domain_init(int hw)
2043 struct dmar_drhd_unit *drhd;
2044 struct intel_iommu *iommu;
2047 si_domain = alloc_domain();
2051 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2053 for_each_active_iommu(iommu, drhd) {
2054 ret = iommu_attach_domain(si_domain, iommu);
2056 domain_exit(si_domain);
2061 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2062 domain_exit(si_domain);
2066 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2071 for_each_online_node(nid) {
2072 work_with_active_regions(nid, si_domain_work_fn, &ret);
2080 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2081 struct pci_dev *pdev);
2082 static int identity_mapping(struct pci_dev *pdev)
2084 struct device_domain_info *info;
2086 if (likely(!iommu_identity_mapping))
2090 list_for_each_entry(info, &si_domain->devices, link)
2091 if (info->dev == pdev)
2096 static int domain_add_dev_info(struct dmar_domain *domain,
2097 struct pci_dev *pdev)
2099 struct device_domain_info *info;
2100 unsigned long flags;
2102 info = alloc_devinfo_mem();
2106 info->segment = pci_domain_nr(pdev->bus);
2107 info->bus = pdev->bus->number;
2108 info->devfn = pdev->devfn;
2110 info->domain = domain;
2112 spin_lock_irqsave(&device_domain_lock, flags);
2113 list_add(&info->link, &domain->devices);
2114 list_add(&info->global, &device_domain_list);
2115 pdev->dev.archdata.iommu = info;
2116 spin_unlock_irqrestore(&device_domain_lock, flags);
2121 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2123 if (iommu_identity_mapping == 2)
2124 return IS_GFX_DEVICE(pdev);
2127 * We want to start off with all devices in the 1:1 domain, and
2128 * take them out later if we find they can't access all of memory.
2130 * However, we can't do this for PCI devices behind bridges,
2131 * because all PCI devices behind the same bridge will end up
2132 * with the same source-id on their transactions.
2134 * Practically speaking, we can't change things around for these
2135 * devices at run-time, because we can't be sure there'll be no
2136 * DMA transactions in flight for any of their siblings.
2138 * So PCI devices (unless they're on the root bus) as well as
2139 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2140 * the 1:1 domain, just in _case_ one of their siblings turns out
2141 * not to be able to map all of memory.
2143 if (!pdev->is_pcie) {
2144 if (!pci_is_root_bus(pdev->bus))
2146 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2148 } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2152 * At boot time, we don't yet know if devices will be 64-bit capable.
2153 * Assume that they will -- if they turn out not to be, then we can
2154 * take them out of the 1:1 domain later.
2157 return pdev->dma_mask > DMA_BIT_MASK(32);
2162 static int iommu_prepare_static_identity_mapping(int hw)
2164 struct pci_dev *pdev = NULL;
2167 ret = si_domain_init(hw);
2171 for_each_pci_dev(pdev) {
2172 if (iommu_should_identity_map(pdev, 1)) {
2173 printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2174 hw ? "hardware" : "software", pci_name(pdev));
2176 ret = domain_context_mapping(si_domain, pdev,
2177 hw ? CONTEXT_TT_PASS_THROUGH :
2178 CONTEXT_TT_MULTI_LEVEL);
2182 ret = domain_add_dev_info(si_domain, pdev);
2191 int __init init_dmars(void)
2193 struct dmar_drhd_unit *drhd;
2194 struct dmar_rmrr_unit *rmrr;
2195 struct pci_dev *pdev;
2196 struct intel_iommu *iommu;
2202 * initialize and program root entry to not present
2205 for_each_drhd_unit(drhd) {
2208 * lock not needed as this is only incremented in the single
2209 * threaded kernel __init code path all other access are read
2214 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2217 printk(KERN_ERR "Allocating global iommu array failed\n");
2222 deferred_flush = kzalloc(g_num_of_iommus *
2223 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2224 if (!deferred_flush) {
2229 for_each_drhd_unit(drhd) {
2233 iommu = drhd->iommu;
2234 g_iommus[iommu->seq_id] = iommu;
2236 ret = iommu_init_domains(iommu);
2242 * we could share the same root & context tables
2243 * amoung all IOMMU's. Need to Split it later.
2245 ret = iommu_alloc_root_entry(iommu);
2247 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2250 if (!ecap_pass_through(iommu->ecap))
2251 hw_pass_through = 0;
2255 * Start from the sane iommu hardware state.
2257 for_each_drhd_unit(drhd) {
2261 iommu = drhd->iommu;
2264 * If the queued invalidation is already initialized by us
2265 * (for example, while enabling interrupt-remapping) then
2266 * we got the things already rolling from a sane state.
2272 * Clear any previous faults.
2274 dmar_fault(-1, iommu);
2276 * Disable queued invalidation if supported and already enabled
2277 * before OS handover.
2279 dmar_disable_qi(iommu);
2282 for_each_drhd_unit(drhd) {
2286 iommu = drhd->iommu;
2288 if (dmar_enable_qi(iommu)) {
2290 * Queued Invalidate not enabled, use Register Based
2293 iommu->flush.flush_context = __iommu_flush_context;
2294 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2295 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2297 (unsigned long long)drhd->reg_base_addr);
2299 iommu->flush.flush_context = qi_flush_context;
2300 iommu->flush.flush_iotlb = qi_flush_iotlb;
2301 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2303 (unsigned long long)drhd->reg_base_addr);
2307 if (iommu_pass_through)
2308 iommu_identity_mapping = 1;
2309 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2311 iommu_identity_mapping = 2;
2314 * If pass through is not set or not enabled, setup context entries for
2315 * identity mappings for rmrr, gfx, and isa and may fall back to static
2316 * identity mapping if iommu_identity_mapping is set.
2318 if (iommu_identity_mapping) {
2319 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
2321 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2327 * for each dev attached to rmrr
2329 * locate drhd for dev, alloc domain for dev
2330 * allocate free domain
2331 * allocate page table entries for rmrr
2332 * if context not allocated for bus
2333 * allocate and init context
2334 * set present in root table for this bus
2335 * init context with domain, translation etc
2339 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2340 for_each_rmrr_units(rmrr) {
2341 for (i = 0; i < rmrr->devices_cnt; i++) {
2342 pdev = rmrr->devices[i];
2344 * some BIOS lists non-exist devices in DMAR
2349 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2352 "IOMMU: mapping reserved region failed\n");
2356 iommu_prepare_isa();
2361 * global invalidate context cache
2362 * global invalidate iotlb
2363 * enable translation
2365 for_each_drhd_unit(drhd) {
2368 iommu = drhd->iommu;
2370 iommu_flush_write_buffer(iommu);
2372 ret = dmar_set_interrupt(iommu);
2376 iommu_set_root_entry(iommu);
2378 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2379 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2380 iommu_disable_protect_mem_regions(iommu);
2382 ret = iommu_enable_translation(iommu);
2389 for_each_drhd_unit(drhd) {
2392 iommu = drhd->iommu;
2399 /* This takes a number of _MM_ pages, not VTD pages */
2400 static struct iova *intel_alloc_iova(struct device *dev,
2401 struct dmar_domain *domain,
2402 unsigned long nrpages, uint64_t dma_mask)
2404 struct pci_dev *pdev = to_pci_dev(dev);
2405 struct iova *iova = NULL;
2407 /* Restrict dma_mask to the width that the iommu can handle */
2408 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2410 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2412 * First try to allocate an io virtual address in
2413 * DMA_BIT_MASK(32) and if that fails then try allocating
2416 iova = alloc_iova(&domain->iovad, nrpages,
2417 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2421 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2422 if (unlikely(!iova)) {
2423 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2424 nrpages, pci_name(pdev));
2431 static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2433 struct dmar_domain *domain;
2436 domain = get_domain_for_dev(pdev,
2437 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2440 "Allocating domain for %s failed", pci_name(pdev));
2444 /* make sure context mapping is ok */
2445 if (unlikely(!domain_context_mapped(pdev))) {
2446 ret = domain_context_mapping(domain, pdev,
2447 CONTEXT_TT_MULTI_LEVEL);
2450 "Domain context map for %s failed",
2459 static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2461 struct device_domain_info *info;
2463 /* No lock here, assumes no domain exit in normal case */
2464 info = dev->dev.archdata.iommu;
2466 return info->domain;
2468 return __get_valid_domain_for_dev(dev);
2471 static int iommu_dummy(struct pci_dev *pdev)
2473 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2476 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2477 static int iommu_no_mapping(struct device *dev)
2479 struct pci_dev *pdev;
2482 if (unlikely(dev->bus != &pci_bus_type))
2485 pdev = to_pci_dev(dev);
2486 if (iommu_dummy(pdev))
2489 if (!iommu_identity_mapping)
2492 found = identity_mapping(pdev);
2494 if (iommu_should_identity_map(pdev, 0))
2498 * 32 bit DMA is removed from si_domain and fall back
2499 * to non-identity mapping.
2501 domain_remove_one_dev_info(si_domain, pdev);
2502 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2508 * In case of a detached 64 bit DMA device from vm, the device
2509 * is put into si_domain for identity mapping.
2511 if (iommu_should_identity_map(pdev, 0)) {
2513 ret = domain_add_dev_info(si_domain, pdev);
2516 ret = domain_context_mapping(si_domain, pdev,
2518 CONTEXT_TT_PASS_THROUGH :
2519 CONTEXT_TT_MULTI_LEVEL);
2521 printk(KERN_INFO "64bit %s uses identity mapping\n",
2531 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2532 size_t size, int dir, u64 dma_mask)
2534 struct pci_dev *pdev = to_pci_dev(hwdev);
2535 struct dmar_domain *domain;
2536 phys_addr_t start_paddr;
2540 struct intel_iommu *iommu;
2541 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2543 BUG_ON(dir == DMA_NONE);
2545 if (iommu_no_mapping(hwdev))
2548 domain = get_valid_domain_for_dev(pdev);
2552 iommu = domain_get_iommu(domain);
2553 size = aligned_nrpages(paddr, size);
2555 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2561 * Check if DMAR supports zero-length reads on write only
2564 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2565 !cap_zlr(iommu->cap))
2566 prot |= DMA_PTE_READ;
2567 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2568 prot |= DMA_PTE_WRITE;
2570 * paddr - (paddr + size) might be partial page, we should map the whole
2571 * page. Note: if two part of one page are separately mapped, we
2572 * might have two guest_addr mapping to the same host paddr, but this
2573 * is not a big problem
2575 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2576 mm_to_dma_pfn(paddr_pfn), size, prot);
2580 /* it's a non-present to present mapping. Only flush if caching mode */
2581 if (cap_caching_mode(iommu->cap))
2582 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2584 iommu_flush_write_buffer(iommu);
2586 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2587 start_paddr += paddr & ~PAGE_MASK;
2592 __free_iova(&domain->iovad, iova);
2593 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2594 pci_name(pdev), size, (unsigned long long)paddr, dir);
2598 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2599 unsigned long offset, size_t size,
2600 enum dma_data_direction dir,
2601 struct dma_attrs *attrs)
2603 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2604 dir, to_pci_dev(dev)->dma_mask);
2607 static void flush_unmaps(void)
2613 /* just flush them all */
2614 for (i = 0; i < g_num_of_iommus; i++) {
2615 struct intel_iommu *iommu = g_iommus[i];
2619 if (!deferred_flush[i].next)
2622 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2623 DMA_TLB_GLOBAL_FLUSH);
2624 for (j = 0; j < deferred_flush[i].next; j++) {
2626 struct iova *iova = deferred_flush[i].iova[j];
2628 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2629 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2630 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2631 iova->pfn_lo << PAGE_SHIFT, mask);
2632 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2634 deferred_flush[i].next = 0;
2640 static void flush_unmaps_timeout(unsigned long data)
2642 unsigned long flags;
2644 spin_lock_irqsave(&async_umap_flush_lock, flags);
2646 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2649 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2651 unsigned long flags;
2653 struct intel_iommu *iommu;
2655 spin_lock_irqsave(&async_umap_flush_lock, flags);
2656 if (list_size == HIGH_WATER_MARK)
2659 iommu = domain_get_iommu(dom);
2660 iommu_id = iommu->seq_id;
2662 next = deferred_flush[iommu_id].next;
2663 deferred_flush[iommu_id].domain[next] = dom;
2664 deferred_flush[iommu_id].iova[next] = iova;
2665 deferred_flush[iommu_id].next++;
2668 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2672 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2675 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2676 size_t size, enum dma_data_direction dir,
2677 struct dma_attrs *attrs)
2679 struct pci_dev *pdev = to_pci_dev(dev);
2680 struct dmar_domain *domain;
2681 unsigned long start_pfn, last_pfn;
2683 struct intel_iommu *iommu;
2685 if (iommu_no_mapping(dev))
2688 domain = find_domain(pdev);
2691 iommu = domain_get_iommu(domain);
2693 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2694 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2695 (unsigned long long)dev_addr))
2698 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2699 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2701 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2702 pci_name(pdev), start_pfn, last_pfn);
2704 /* clear the whole page */
2705 dma_pte_clear_range(domain, start_pfn, last_pfn);
2707 /* free page tables */
2708 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2710 if (intel_iommu_strict) {
2711 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2712 last_pfn - start_pfn + 1);
2714 __free_iova(&domain->iovad, iova);
2716 add_unmap(domain, iova);
2718 * queue up the release of the unmap to save the 1/6th of the
2719 * cpu used up by the iotlb flush operation...
2724 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2725 dma_addr_t *dma_handle, gfp_t flags)
2730 size = PAGE_ALIGN(size);
2731 order = get_order(size);
2732 flags &= ~(GFP_DMA | GFP_DMA32);
2734 vaddr = (void *)__get_free_pages(flags, order);
2737 memset(vaddr, 0, size);
2739 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2741 hwdev->coherent_dma_mask);
2744 free_pages((unsigned long)vaddr, order);
2748 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2749 dma_addr_t dma_handle)
2753 size = PAGE_ALIGN(size);
2754 order = get_order(size);
2756 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
2757 free_pages((unsigned long)vaddr, order);
2760 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2761 int nelems, enum dma_data_direction dir,
2762 struct dma_attrs *attrs)
2764 struct pci_dev *pdev = to_pci_dev(hwdev);
2765 struct dmar_domain *domain;
2766 unsigned long start_pfn, last_pfn;
2768 struct intel_iommu *iommu;
2770 if (iommu_no_mapping(hwdev))
2773 domain = find_domain(pdev);
2776 iommu = domain_get_iommu(domain);
2778 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2779 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2780 (unsigned long long)sglist[0].dma_address))
2783 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2784 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2786 /* clear the whole page */
2787 dma_pte_clear_range(domain, start_pfn, last_pfn);
2789 /* free page tables */
2790 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2792 if (intel_iommu_strict) {
2793 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2794 last_pfn - start_pfn + 1);
2796 __free_iova(&domain->iovad, iova);
2798 add_unmap(domain, iova);
2800 * queue up the release of the unmap to save the 1/6th of the
2801 * cpu used up by the iotlb flush operation...
2806 static int intel_nontranslate_map_sg(struct device *hddev,
2807 struct scatterlist *sglist, int nelems, int dir)
2810 struct scatterlist *sg;
2812 for_each_sg(sglist, sg, nelems, i) {
2813 BUG_ON(!sg_page(sg));
2814 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2815 sg->dma_length = sg->length;
2820 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2821 enum dma_data_direction dir, struct dma_attrs *attrs)
2824 struct pci_dev *pdev = to_pci_dev(hwdev);
2825 struct dmar_domain *domain;
2828 size_t offset_pfn = 0;
2829 struct iova *iova = NULL;
2831 struct scatterlist *sg;
2832 unsigned long start_vpfn;
2833 struct intel_iommu *iommu;
2835 BUG_ON(dir == DMA_NONE);
2836 if (iommu_no_mapping(hwdev))
2837 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2839 domain = get_valid_domain_for_dev(pdev);
2843 iommu = domain_get_iommu(domain);
2845 for_each_sg(sglist, sg, nelems, i)
2846 size += aligned_nrpages(sg->offset, sg->length);
2848 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2851 sglist->dma_length = 0;
2856 * Check if DMAR supports zero-length reads on write only
2859 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2860 !cap_zlr(iommu->cap))
2861 prot |= DMA_PTE_READ;
2862 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2863 prot |= DMA_PTE_WRITE;
2865 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2867 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
2868 if (unlikely(ret)) {
2869 /* clear the page */
2870 dma_pte_clear_range(domain, start_vpfn,
2871 start_vpfn + size - 1);
2872 /* free page tables */
2873 dma_pte_free_pagetable(domain, start_vpfn,
2874 start_vpfn + size - 1);
2876 __free_iova(&domain->iovad, iova);
2880 /* it's a non-present to present mapping. Only flush if caching mode */
2881 if (cap_caching_mode(iommu->cap))
2882 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2884 iommu_flush_write_buffer(iommu);
2889 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2894 struct dma_map_ops intel_dma_ops = {
2895 .alloc_coherent = intel_alloc_coherent,
2896 .free_coherent = intel_free_coherent,
2897 .map_sg = intel_map_sg,
2898 .unmap_sg = intel_unmap_sg,
2899 .map_page = intel_map_page,
2900 .unmap_page = intel_unmap_page,
2901 .mapping_error = intel_mapping_error,
2904 static inline int iommu_domain_cache_init(void)
2908 iommu_domain_cache = kmem_cache_create("iommu_domain",
2909 sizeof(struct dmar_domain),
2914 if (!iommu_domain_cache) {
2915 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2922 static inline int iommu_devinfo_cache_init(void)
2926 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2927 sizeof(struct device_domain_info),
2931 if (!iommu_devinfo_cache) {
2932 printk(KERN_ERR "Couldn't create devinfo cache\n");
2939 static inline int iommu_iova_cache_init(void)
2943 iommu_iova_cache = kmem_cache_create("iommu_iova",
2944 sizeof(struct iova),
2948 if (!iommu_iova_cache) {
2949 printk(KERN_ERR "Couldn't create iova cache\n");
2956 static int __init iommu_init_mempool(void)
2959 ret = iommu_iova_cache_init();
2963 ret = iommu_domain_cache_init();
2967 ret = iommu_devinfo_cache_init();
2971 kmem_cache_destroy(iommu_domain_cache);
2973 kmem_cache_destroy(iommu_iova_cache);
2978 static void __init iommu_exit_mempool(void)
2980 kmem_cache_destroy(iommu_devinfo_cache);
2981 kmem_cache_destroy(iommu_domain_cache);
2982 kmem_cache_destroy(iommu_iova_cache);
2986 static void __init init_no_remapping_devices(void)
2988 struct dmar_drhd_unit *drhd;
2990 for_each_drhd_unit(drhd) {
2991 if (!drhd->include_all) {
2993 for (i = 0; i < drhd->devices_cnt; i++)
2994 if (drhd->devices[i] != NULL)
2996 /* ignore DMAR unit if no pci devices exist */
2997 if (i == drhd->devices_cnt)
3005 for_each_drhd_unit(drhd) {
3007 if (drhd->ignored || drhd->include_all)
3010 for (i = 0; i < drhd->devices_cnt; i++)
3011 if (drhd->devices[i] &&
3012 !IS_GFX_DEVICE(drhd->devices[i]))
3015 if (i < drhd->devices_cnt)
3018 /* bypass IOMMU if it is just for gfx devices */
3020 for (i = 0; i < drhd->devices_cnt; i++) {
3021 if (!drhd->devices[i])
3023 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3028 #ifdef CONFIG_SUSPEND
3029 static int init_iommu_hw(void)
3031 struct dmar_drhd_unit *drhd;
3032 struct intel_iommu *iommu = NULL;
3034 for_each_active_iommu(iommu, drhd)
3036 dmar_reenable_qi(iommu);
3038 for_each_active_iommu(iommu, drhd) {
3039 iommu_flush_write_buffer(iommu);
3041 iommu_set_root_entry(iommu);
3043 iommu->flush.flush_context(iommu, 0, 0, 0,
3044 DMA_CCMD_GLOBAL_INVL);
3045 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3046 DMA_TLB_GLOBAL_FLUSH);
3047 iommu_disable_protect_mem_regions(iommu);
3048 iommu_enable_translation(iommu);
3054 static void iommu_flush_all(void)
3056 struct dmar_drhd_unit *drhd;
3057 struct intel_iommu *iommu;
3059 for_each_active_iommu(iommu, drhd) {
3060 iommu->flush.flush_context(iommu, 0, 0, 0,
3061 DMA_CCMD_GLOBAL_INVL);
3062 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3063 DMA_TLB_GLOBAL_FLUSH);
3067 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3069 struct dmar_drhd_unit *drhd;
3070 struct intel_iommu *iommu = NULL;
3073 for_each_active_iommu(iommu, drhd) {
3074 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3076 if (!iommu->iommu_state)
3082 for_each_active_iommu(iommu, drhd) {
3083 iommu_disable_translation(iommu);
3085 spin_lock_irqsave(&iommu->register_lock, flag);
3087 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3088 readl(iommu->reg + DMAR_FECTL_REG);
3089 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3090 readl(iommu->reg + DMAR_FEDATA_REG);
3091 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3092 readl(iommu->reg + DMAR_FEADDR_REG);
3093 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3094 readl(iommu->reg + DMAR_FEUADDR_REG);
3096 spin_unlock_irqrestore(&iommu->register_lock, flag);
3101 for_each_active_iommu(iommu, drhd)
3102 kfree(iommu->iommu_state);
3107 static int iommu_resume(struct sys_device *dev)
3109 struct dmar_drhd_unit *drhd;
3110 struct intel_iommu *iommu = NULL;
3113 if (init_iommu_hw()) {
3114 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3118 for_each_active_iommu(iommu, drhd) {
3120 spin_lock_irqsave(&iommu->register_lock, flag);
3122 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3123 iommu->reg + DMAR_FECTL_REG);
3124 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3125 iommu->reg + DMAR_FEDATA_REG);
3126 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3127 iommu->reg + DMAR_FEADDR_REG);
3128 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3129 iommu->reg + DMAR_FEUADDR_REG);
3131 spin_unlock_irqrestore(&iommu->register_lock, flag);
3134 for_each_active_iommu(iommu, drhd)
3135 kfree(iommu->iommu_state);
3140 static struct sysdev_class iommu_sysclass = {
3142 .resume = iommu_resume,
3143 .suspend = iommu_suspend,
3146 static struct sys_device device_iommu = {
3147 .cls = &iommu_sysclass,
3150 static int __init init_iommu_sysfs(void)
3154 error = sysdev_class_register(&iommu_sysclass);
3158 error = sysdev_register(&device_iommu);
3160 sysdev_class_unregister(&iommu_sysclass);
3166 static int __init init_iommu_sysfs(void)
3170 #endif /* CONFIG_PM */
3172 int __init intel_iommu_init(void)
3176 if (dmar_table_init())
3179 if (dmar_dev_scope_init())
3183 * Check the need for DMA-remapping initialization now.
3184 * Above initialization will also be used by Interrupt-remapping.
3186 if (no_iommu || swiotlb || dmar_disabled)
3189 iommu_init_mempool();
3190 dmar_init_reserved_ranges();
3192 init_no_remapping_devices();
3196 printk(KERN_ERR "IOMMU: dmar init failed\n");
3197 put_iova_domain(&reserved_iova_list);
3198 iommu_exit_mempool();
3202 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3204 init_timer(&unmap_timer);
3206 dma_ops = &intel_dma_ops;
3210 register_iommu(&intel_iommu_ops);
3215 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3216 struct pci_dev *pdev)
3218 struct pci_dev *tmp, *parent;
3220 if (!iommu || !pdev)
3223 /* dependent device detach */
3224 tmp = pci_find_upstream_pcie_bridge(pdev);
3225 /* Secondary interface's bus number and devfn 0 */
3227 parent = pdev->bus->self;
3228 while (parent != tmp) {
3229 iommu_detach_dev(iommu, parent->bus->number,
3231 parent = parent->bus->self;
3233 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3234 iommu_detach_dev(iommu,
3235 tmp->subordinate->number, 0);
3236 else /* this is a legacy PCI bridge */
3237 iommu_detach_dev(iommu, tmp->bus->number,
3242 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3243 struct pci_dev *pdev)
3245 struct device_domain_info *info;
3246 struct intel_iommu *iommu;
3247 unsigned long flags;
3249 struct list_head *entry, *tmp;
3251 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3256 spin_lock_irqsave(&device_domain_lock, flags);
3257 list_for_each_safe(entry, tmp, &domain->devices) {
3258 info = list_entry(entry, struct device_domain_info, link);
3259 /* No need to compare PCI domain; it has to be the same */
3260 if (info->bus == pdev->bus->number &&
3261 info->devfn == pdev->devfn) {
3262 list_del(&info->link);
3263 list_del(&info->global);
3265 info->dev->dev.archdata.iommu = NULL;
3266 spin_unlock_irqrestore(&device_domain_lock, flags);
3268 iommu_disable_dev_iotlb(info);
3269 iommu_detach_dev(iommu, info->bus, info->devfn);
3270 iommu_detach_dependent_devices(iommu, pdev);
3271 free_devinfo_mem(info);
3273 spin_lock_irqsave(&device_domain_lock, flags);
3281 /* if there is no other devices under the same iommu
3282 * owned by this domain, clear this iommu in iommu_bmp
3283 * update iommu count and coherency
3285 if (iommu == device_to_iommu(info->segment, info->bus,
3291 unsigned long tmp_flags;
3292 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3293 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3294 domain->iommu_count--;
3295 domain_update_iommu_cap(domain);
3296 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3299 spin_unlock_irqrestore(&device_domain_lock, flags);
3302 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3304 struct device_domain_info *info;
3305 struct intel_iommu *iommu;
3306 unsigned long flags1, flags2;
3308 spin_lock_irqsave(&device_domain_lock, flags1);
3309 while (!list_empty(&domain->devices)) {
3310 info = list_entry(domain->devices.next,
3311 struct device_domain_info, link);
3312 list_del(&info->link);
3313 list_del(&info->global);
3315 info->dev->dev.archdata.iommu = NULL;
3317 spin_unlock_irqrestore(&device_domain_lock, flags1);
3319 iommu_disable_dev_iotlb(info);
3320 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3321 iommu_detach_dev(iommu, info->bus, info->devfn);
3322 iommu_detach_dependent_devices(iommu, info->dev);
3324 /* clear this iommu in iommu_bmp, update iommu count
3327 spin_lock_irqsave(&domain->iommu_lock, flags2);
3328 if (test_and_clear_bit(iommu->seq_id,
3329 &domain->iommu_bmp)) {
3330 domain->iommu_count--;
3331 domain_update_iommu_cap(domain);
3333 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3335 free_devinfo_mem(info);
3336 spin_lock_irqsave(&device_domain_lock, flags1);
3338 spin_unlock_irqrestore(&device_domain_lock, flags1);
3341 /* domain id for virtual machine, it won't be set in context */
3342 static unsigned long vm_domid;
3344 static int vm_domain_min_agaw(struct dmar_domain *domain)
3347 int min_agaw = domain->agaw;
3349 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3350 for (; i < g_num_of_iommus; ) {
3351 if (min_agaw > g_iommus[i]->agaw)
3352 min_agaw = g_iommus[i]->agaw;
3354 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3360 static struct dmar_domain *iommu_alloc_vm_domain(void)
3362 struct dmar_domain *domain;
3364 domain = alloc_domain_mem();
3368 domain->id = vm_domid++;
3369 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3370 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3375 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3379 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3380 spin_lock_init(&domain->iommu_lock);
3382 domain_reserve_special_ranges(domain);
3384 /* calculate AGAW */
3385 domain->gaw = guest_width;
3386 adjust_width = guestwidth_to_adjustwidth(guest_width);
3387 domain->agaw = width_to_agaw(adjust_width);
3389 INIT_LIST_HEAD(&domain->devices);
3391 domain->iommu_count = 0;
3392 domain->iommu_coherency = 0;
3393 domain->iommu_snooping = 0;
3394 domain->max_addr = 0;
3396 /* always allocate the top pgd */
3397 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3400 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3404 static void iommu_free_vm_domain(struct dmar_domain *domain)
3406 unsigned long flags;
3407 struct dmar_drhd_unit *drhd;
3408 struct intel_iommu *iommu;
3410 unsigned long ndomains;
3412 for_each_drhd_unit(drhd) {
3415 iommu = drhd->iommu;
3417 ndomains = cap_ndoms(iommu->cap);
3418 i = find_first_bit(iommu->domain_ids, ndomains);
3419 for (; i < ndomains; ) {
3420 if (iommu->domains[i] == domain) {
3421 spin_lock_irqsave(&iommu->lock, flags);
3422 clear_bit(i, iommu->domain_ids);
3423 iommu->domains[i] = NULL;
3424 spin_unlock_irqrestore(&iommu->lock, flags);
3427 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3432 static void vm_domain_exit(struct dmar_domain *domain)
3434 /* Domain 0 is reserved, so dont process it */
3438 vm_domain_remove_all_dev_info(domain);
3440 put_iova_domain(&domain->iovad);
3443 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3445 /* free page tables */
3446 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3448 iommu_free_vm_domain(domain);
3449 free_domain_mem(domain);
3452 static int intel_iommu_domain_init(struct iommu_domain *domain)
3454 struct dmar_domain *dmar_domain;
3456 dmar_domain = iommu_alloc_vm_domain();
3459 "intel_iommu_domain_init: dmar_domain == NULL\n");
3462 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3464 "intel_iommu_domain_init() failed\n");
3465 vm_domain_exit(dmar_domain);
3468 domain->priv = dmar_domain;
3473 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3475 struct dmar_domain *dmar_domain = domain->priv;
3477 domain->priv = NULL;
3478 vm_domain_exit(dmar_domain);
3481 static int intel_iommu_attach_device(struct iommu_domain *domain,
3484 struct dmar_domain *dmar_domain = domain->priv;
3485 struct pci_dev *pdev = to_pci_dev(dev);
3486 struct intel_iommu *iommu;
3491 /* normally pdev is not mapped */
3492 if (unlikely(domain_context_mapped(pdev))) {
3493 struct dmar_domain *old_domain;
3495 old_domain = find_domain(pdev);
3497 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3498 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3499 domain_remove_one_dev_info(old_domain, pdev);
3501 domain_remove_dev_info(old_domain);
3505 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3510 /* check if this iommu agaw is sufficient for max mapped address */
3511 addr_width = agaw_to_width(iommu->agaw);
3512 end = DOMAIN_MAX_ADDR(addr_width);
3513 end = end & VTD_PAGE_MASK;
3514 if (end < dmar_domain->max_addr) {
3515 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3516 "sufficient for the mapped address (%llx)\n",
3517 __func__, iommu->agaw, dmar_domain->max_addr);
3521 ret = domain_add_dev_info(dmar_domain, pdev);
3525 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3529 static void intel_iommu_detach_device(struct iommu_domain *domain,
3532 struct dmar_domain *dmar_domain = domain->priv;
3533 struct pci_dev *pdev = to_pci_dev(dev);
3535 domain_remove_one_dev_info(dmar_domain, pdev);
3538 static int intel_iommu_map_range(struct iommu_domain *domain,
3539 unsigned long iova, phys_addr_t hpa,
3540 size_t size, int iommu_prot)
3542 struct dmar_domain *dmar_domain = domain->priv;
3548 if (iommu_prot & IOMMU_READ)
3549 prot |= DMA_PTE_READ;
3550 if (iommu_prot & IOMMU_WRITE)
3551 prot |= DMA_PTE_WRITE;
3552 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3553 prot |= DMA_PTE_SNP;
3555 max_addr = iova + size;
3556 if (dmar_domain->max_addr < max_addr) {
3560 /* check if minimum agaw is sufficient for mapped address */
3561 min_agaw = vm_domain_min_agaw(dmar_domain);
3562 addr_width = agaw_to_width(min_agaw);
3563 end = DOMAIN_MAX_ADDR(addr_width);
3564 end = end & VTD_PAGE_MASK;
3565 if (end < max_addr) {
3566 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3567 "sufficient for the mapped address (%llx)\n",
3568 __func__, min_agaw, max_addr);
3571 dmar_domain->max_addr = max_addr;
3573 /* Round up size to next multiple of PAGE_SIZE, if it and
3574 the low bits of hpa would take us onto the next page */
3575 size = aligned_nrpages(hpa, size);
3576 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3577 hpa >> VTD_PAGE_SHIFT, size, prot);
3581 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3582 unsigned long iova, size_t size)
3584 struct dmar_domain *dmar_domain = domain->priv;
3589 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3590 (iova + size - 1) >> VTD_PAGE_SHIFT);
3592 if (dmar_domain->max_addr == iova + size)
3593 dmar_domain->max_addr = iova;
3596 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3599 struct dmar_domain *dmar_domain = domain->priv;
3600 struct dma_pte *pte;
3603 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3605 phys = dma_pte_addr(pte);
3610 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3613 struct dmar_domain *dmar_domain = domain->priv;
3615 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3616 return dmar_domain->iommu_snooping;
3621 static struct iommu_ops intel_iommu_ops = {
3622 .domain_init = intel_iommu_domain_init,
3623 .domain_destroy = intel_iommu_domain_destroy,
3624 .attach_dev = intel_iommu_attach_device,
3625 .detach_dev = intel_iommu_detach_device,
3626 .map = intel_iommu_map_range,
3627 .unmap = intel_iommu_unmap_range,
3628 .iova_to_phys = intel_iommu_iova_to_phys,
3629 .domain_has_cap = intel_iommu_domain_has_cap,
3632 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3635 * Mobile 4 Series Chipset neglects to set RWBF capability,
3638 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);