drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/sched.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/wireless.h>
  38 #include <linux/firmware.h>
  39 #include <linux/etherdevice.h>
  40 #include <asm/unaligned.h>
  41 #include <net/mac80211.h>
  42
  43 #include "iwl-fh.h"
  44 #include "iwl-3945-fh.h"
  45 #include "iwl-commands.h"
  46 #include "iwl-sta.h"
  47 #include "iwl-3945.h"
  48 #include "iwl-eeprom.h"
  49 #include "iwl-core.h"
  50 #include "iwl-helpers.h"
  51 #include "iwl-led.h"
  52 #include "iwl-3945-led.h"
  53
  54 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  55         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  56                                     IWL_RATE_##r##M_IEEE,   \
  57                                     IWL_RATE_##ip##M_INDEX, \
  58                                     IWL_RATE_##in##M_INDEX, \
  59                                     IWL_RATE_##rp##M_INDEX, \
  60                                     IWL_RATE_##rn##M_INDEX, \
  61                                     IWL_RATE_##pp##M_INDEX, \
  62                                     IWL_RATE_##np##M_INDEX, \
  63                                     IWL_RATE_##r##M_INDEX_TABLE, \
  64                                     IWL_RATE_##ip##M_INDEX_TABLE }
  65
  66 /*
  67  * Parameter order:
  68  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  69  *
  70  * If there isn't a valid next or previous rate then INV is used which
  71  * maps to IWL_RATE_INVALID
  72  *
  73  */
  74 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  75         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  76         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  77         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  78         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  79         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  80         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  81         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  82         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  83         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  84         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  85         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  86         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  87 };
  88
  89 /* 1 = enable the iwl3945_disable_events() function */
  90 #define IWL_EVT_DISABLE (0)
  91 #define IWL_EVT_DISABLE_SIZE (1532/32)
  92
  93 /**
  94  * iwl3945_disable_events - Disable selected events in uCode event log
  95  *
  96  * Disable an event by writing "1"s into "disable"
  97  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  98  *   Default values of 0 enable uCode events to be logged.
  99  * Use for only special debugging.  This function is just a placeholder as-is,
 100  *   you'll need to provide the special bits! ...
 101  *   ... and set IWL_EVT_DISABLE to 1. */
 102 void iwl3945_disable_events(struct iwl_priv *priv)
 103 {
 104         int i;
 105         u32 base;               /* SRAM address of event log header */
 106         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 107         u32 array_size;         /* # of u32 entries in array */
 108         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 109                 0x00000000,     /*   31 -    0  Event id numbers */
 110                 0x00000000,     /*   63 -   32 */
 111                 0x00000000,     /*   95 -   64 */
 112                 0x00000000,     /*  127 -   96 */
 113                 0x00000000,     /*  159 -  128 */
 114                 0x00000000,     /*  191 -  160 */
 115                 0x00000000,     /*  223 -  192 */
 116                 0x00000000,     /*  255 -  224 */
 117                 0x00000000,     /*  287 -  256 */
 118                 0x00000000,     /*  319 -  288 */
 119                 0x00000000,     /*  351 -  320 */
 120                 0x00000000,     /*  383 -  352 */
 121                 0x00000000,     /*  415 -  384 */
 122                 0x00000000,     /*  447 -  416 */
 123                 0x00000000,     /*  479 -  448 */
 124                 0x00000000,     /*  511 -  480 */
 125                 0x00000000,     /*  543 -  512 */
 126                 0x00000000,     /*  575 -  544 */
 127                 0x00000000,     /*  607 -  576 */
 128                 0x00000000,     /*  639 -  608 */
 129                 0x00000000,     /*  671 -  640 */
 130                 0x00000000,     /*  703 -  672 */
 131                 0x00000000,     /*  735 -  704 */
 132                 0x00000000,     /*  767 -  736 */
 133                 0x00000000,     /*  799 -  768 */
 134                 0x00000000,     /*  831 -  800 */
 135                 0x00000000,     /*  863 -  832 */
 136                 0x00000000,     /*  895 -  864 */
 137                 0x00000000,     /*  927 -  896 */
 138                 0x00000000,     /*  959 -  928 */
 139                 0x00000000,     /*  991 -  960 */
 140                 0x00000000,     /* 1023 -  992 */
 141                 0x00000000,     /* 1055 - 1024 */
 142                 0x00000000,     /* 1087 - 1056 */
 143                 0x00000000,     /* 1119 - 1088 */
 144                 0x00000000,     /* 1151 - 1120 */
 145                 0x00000000,     /* 1183 - 1152 */
 146                 0x00000000,     /* 1215 - 1184 */
 147                 0x00000000,     /* 1247 - 1216 */
 148                 0x00000000,     /* 1279 - 1248 */
 149                 0x00000000,     /* 1311 - 1280 */
 150                 0x00000000,     /* 1343 - 1312 */
 151                 0x00000000,     /* 1375 - 1344 */
 152                 0x00000000,     /* 1407 - 1376 */
 153                 0x00000000,     /* 1439 - 1408 */
 154                 0x00000000,     /* 1471 - 1440 */
 155                 0x00000000,     /* 1503 - 1472 */
 156         };
 157
 158         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 159         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 160                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 161                 return;
 162         }
 163
 164         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 165         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 166
 167         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 168                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 169                                disable_ptr);
 170                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 171                         iwl_write_targ_mem(priv,
 172                                            disable_ptr + (i * sizeof(u32)),
 173                                            evt_disable[i]);
 174
 175         } else {
 176                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 177                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 178                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 179                                disable_ptr, array_size);
 180         }
 181
 182 }
 183
 184 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 185 {
 186         int idx;
 187
 188         for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
 189                 if (iwl3945_rates[idx].plcp == plcp)
 190                         return idx;
 191         return -1;
 192 }
 193
 194 #ifdef CONFIG_IWLWIFI_DEBUG
 195 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 196
 197 static const char *iwl3945_get_tx_fail_reason(u32 status)
 198 {
 199         switch (status & TX_STATUS_MSK) {
 200         case TX_STATUS_SUCCESS:
 201                 return "SUCCESS";
 202                 TX_STATUS_ENTRY(SHORT_LIMIT);
 203                 TX_STATUS_ENTRY(LONG_LIMIT);
 204                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 205                 TX_STATUS_ENTRY(MGMNT_ABORT);
 206                 TX_STATUS_ENTRY(NEXT_FRAG);
 207                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 208                 TX_STATUS_ENTRY(DEST_PS);
 209                 TX_STATUS_ENTRY(ABORTED);
 210                 TX_STATUS_ENTRY(BT_RETRY);
 211                 TX_STATUS_ENTRY(STA_INVALID);
 212                 TX_STATUS_ENTRY(FRAG_DROPPED);
 213                 TX_STATUS_ENTRY(TID_DISABLE);
 214                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 215                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 216                 TX_STATUS_ENTRY(TX_LOCKED);
 217                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 218         }
 219
 220         return "UNKNOWN";
 221 }
 222 #else
 223 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 224 {
 225         return "";
 226 }
 227 #endif
 228
 229 /*
 230  * get ieee prev rate from rate scale table.
 231  * for A and B mode we need to overright prev
 232  * value
 233  */
 234 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 235 {
 236         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 237
 238         switch (priv->band) {
 239         case IEEE80211_BAND_5GHZ:
 240                 if (rate == IWL_RATE_12M_INDEX)
 241                         next_rate = IWL_RATE_9M_INDEX;
 242                 else if (rate == IWL_RATE_6M_INDEX)
 243                         next_rate = IWL_RATE_6M_INDEX;
 244                 break;
 245         case IEEE80211_BAND_2GHZ:
 246                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 247                     iwl_is_associated(priv)) {
 248                         if (rate == IWL_RATE_11M_INDEX)
 249                                 next_rate = IWL_RATE_5M_INDEX;
 250                 }
 251                 break;
 252
 253         default:
 254                 break;
 255         }
 256
 257         return next_rate;
 258 }
 259
 260
 261 /**
 262  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 263  *
 264  * When FW advances 'R' index, all entries between old and new 'R' index
 265  * need to be reclaimed. As result, some free space forms. If there is
 266  * enough free space (> low mark), wake the stack that feeds us.
 267  */
 268 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 269                                      int txq_id, int index)
 270 {
 271         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 272         struct iwl_queue *q = &txq->q;
 273         struct iwl_tx_info *tx_info;
 274
 275         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 276
 277         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 278                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 279
 280                 tx_info = &txq->txb[txq->q.read_ptr];
 281                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 282                 tx_info->skb[0] = NULL;
 283                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 284         }
 285
 286         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 287                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 288                         priv->mac80211_registered)
 289                 iwl_wake_queue(priv, txq_id);
 290 }
 291
 292 /**
 293  * iwl3945_rx_reply_tx - Handle Tx response
 294  */
 295 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 296                             struct iwl_rx_mem_buffer *rxb)
 297 {
 298         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 299         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 300         int txq_id = SEQ_TO_QUEUE(sequence);
 301         int index = SEQ_TO_INDEX(sequence);
 302         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 303         struct ieee80211_tx_info *info;
 304         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 305         u32  status = le32_to_cpu(tx_resp->status);
 306         int rate_idx;
 307         int fail;
 308
 309         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 310                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 311                           "is out of range [0-%d] %d %d\n", txq_id,
 312                           index, txq->q.n_bd, txq->q.write_ptr,
 313                           txq->q.read_ptr);
 314                 return;
 315         }
 316
 317         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 318         ieee80211_tx_info_clear_status(info);
 319
 320         /* Fill the MRR chain with some info about on-chip retransmissions */
 321         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 322         if (info->band == IEEE80211_BAND_5GHZ)
 323                 rate_idx -= IWL_FIRST_OFDM_RATE;
 324
 325         fail = tx_resp->failure_frame;
 326
 327         info->status.rates[0].idx = rate_idx;
 328         info->status.rates[0].count = fail + 1; /* add final attempt */
 329
 330         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 331         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 332                                 IEEE80211_TX_STAT_ACK : 0;
 333
 334         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 335                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 336                         tx_resp->rate, tx_resp->failure_frame);
 337
 338         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 339         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 340
 341         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 342                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 343 }
 344
 345
 346
 347 /*****************************************************************************
 348  *
 349  * Intel PRO/Wireless 3945ABG/BG Network Connection
 350  *
 351  *  RX handler implementations
 352  *
 353  *****************************************************************************/
 354
 355 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 356                 struct iwl_rx_mem_buffer *rxb)
 357 {
 358         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 359         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 360                      (int)sizeof(struct iwl3945_notif_statistics),
 361                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 362
 363         memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
 364 }
 365
 366 /******************************************************************************
 367  *
 368  * Misc. internal state and helper functions
 369  *
 370  ******************************************************************************/
 371 #ifdef CONFIG_IWLWIFI_DEBUG
 372
 373 /**
 374  * iwl3945_report_frame - dump frame to syslog during debug sessions
 375  *
 376  * You may hack this function to show different aspects of received frames,
 377  * including selective frame dumps.
 378  * group100 parameter selects whether to show 1 out of 100 good frames.
 379  */
 380 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 381                       struct iwl_rx_packet *pkt,
 382                       struct ieee80211_hdr *header, int group100)
 383 {
 384         u32 to_us;
 385         u32 print_summary = 0;
 386         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 387         u32 hundred = 0;
 388         u32 dataframe = 0;
 389         __le16 fc;
 390         u16 seq_ctl;
 391         u16 channel;
 392         u16 phy_flags;
 393         u16 length;
 394         u16 status;
 395         u16 bcn_tmr;
 396         u32 tsf_low;
 397         u64 tsf;
 398         u8 rssi;
 399         u8 agc;
 400         u16 sig_avg;
 401         u16 noise_diff;
 402         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 403         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 404         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 405         u8 *data = IWL_RX_DATA(pkt);
 406
 407         /* MAC header */
 408         fc = header->frame_control;
 409         seq_ctl = le16_to_cpu(header->seq_ctrl);
 410
 411         /* metadata */
 412         channel = le16_to_cpu(rx_hdr->channel);
 413         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 414         length = le16_to_cpu(rx_hdr->len);
 415
 416         /* end-of-frame status and timestamp */
 417         status = le32_to_cpu(rx_end->status);
 418         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 419         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 420         tsf = le64_to_cpu(rx_end->timestamp);
 421
 422         /* signal statistics */
 423         rssi = rx_stats->rssi;
 424         agc = rx_stats->agc;
 425         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 426         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 427
 428         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 429
 430         /* if data frame is to us and all is good,
 431          *   (optionally) print summary for only 1 out of every 100 */
 432         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 433             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 434                 dataframe = 1;
 435                 if (!group100)
 436                         print_summary = 1;      /* print each frame */
 437                 else if (priv->framecnt_to_us < 100) {
 438                         priv->framecnt_to_us++;
 439                         print_summary = 0;
 440                 } else {
 441                         priv->framecnt_to_us = 0;
 442                         print_summary = 1;
 443                         hundred = 1;
 444                 }
 445         } else {
 446                 /* print summary for all other frames */
 447                 print_summary = 1;
 448         }
 449
 450         if (print_summary) {
 451                 char *title;
 452                 int rate;
 453
 454                 if (hundred)
 455                         title = "100Frames";
 456                 else if (ieee80211_has_retry(fc))
 457                         title = "Retry";
 458                 else if (ieee80211_is_assoc_resp(fc))
 459                         title = "AscRsp";
 460                 else if (ieee80211_is_reassoc_resp(fc))
 461                         title = "RasRsp";
 462                 else if (ieee80211_is_probe_resp(fc)) {
 463                         title = "PrbRsp";
 464                         print_dump = 1; /* dump frame contents */
 465                 } else if (ieee80211_is_beacon(fc)) {
 466                         title = "Beacon";
 467                         print_dump = 1; /* dump frame contents */
 468                 } else if (ieee80211_is_atim(fc))
 469                         title = "ATIM";
 470                 else if (ieee80211_is_auth(fc))
 471                         title = "Auth";
 472                 else if (ieee80211_is_deauth(fc))
 473                         title = "DeAuth";
 474                 else if (ieee80211_is_disassoc(fc))
 475                         title = "DisAssoc";
 476                 else
 477                         title = "Frame";
 478
 479                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 480                 if (rate == -1)
 481                         rate = 0;
 482                 else
 483                         rate = iwl3945_rates[rate].ieee / 2;
 484
 485                 /* print frame summary.
 486                  * MAC addresses show just the last byte (for brevity),
 487                  *    but you can hack it to show more, if you'd like to. */
 488                 if (dataframe)
 489                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 490                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 491                                      title, le16_to_cpu(fc), header->addr1[5],
 492                                      length, rssi, channel, rate);
 493                 else {
 494                         /* src/dst addresses assume managed mode */
 495                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 496                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 497                                      "phy=0x%02x, chnl=%d\n",
 498                                      title, le16_to_cpu(fc), header->addr1[5],
 499                                      header->addr3[5], rssi,
 500                                      tsf_low - priv->scan_start_tsf,
 501                                      phy_flags, channel);
 502                 }
 503         }
 504         if (print_dump)
 505                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 506 }
 507
 508 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 509                       struct iwl_rx_packet *pkt,
 510                       struct ieee80211_hdr *header, int group100)
 511 {
 512         if (iwl_get_debug_level(priv) & IWL_DL_RX)
 513                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 514 }
 515
 516 #else
 517 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 518                       struct iwl_rx_packet *pkt,
 519                       struct ieee80211_hdr *header, int group100)
 520 {
 521 }
 522 #endif
 523
 524 /* This is necessary only for a number of statistics, see the caller. */
 525 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 526                 struct ieee80211_hdr *header)
 527 {
 528         /* Filter incoming packets to determine if they are targeted toward
 529          * this network, discarding packets coming from ourselves */
 530         switch (priv->iw_mode) {
 531         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 532                 /* packets to our IBSS update information */
 533                 return !compare_ether_addr(header->addr3, priv->bssid);
 534         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 535                 /* packets to our IBSS update information */
 536                 return !compare_ether_addr(header->addr2, priv->bssid);
 537         default:
 538                 return 1;
 539         }
 540 }
 541
 542 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 543                                    struct iwl_rx_mem_buffer *rxb,
 544                                    struct ieee80211_rx_status *stats)
 545 {
 546         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 547         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 548         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 549         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 550         u16 len = le16_to_cpu(rx_hdr->len);
 551         struct sk_buff *skb;
 552         int ret;
 553         __le16 fc = hdr->frame_control;
 554
 555         /* We received data from the HW, so stop the watchdog */
 556         if (unlikely(len + IWL39_RX_FRAME_SIZE >
 557                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
 558                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 559                 return;
 560         }
 561
 562         /* We only process data packets if the interface is open */
 563         if (unlikely(!priv->is_open)) {
 564                 IWL_DEBUG_DROP_LIMIT(priv,
 565                         "Dropping packet while interface is not open.\n");
 566                 return;
 567         }
 568
 569         skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
 570         if (!skb) {
 571                 IWL_ERR(priv, "alloc_skb failed\n");
 572                 return;
 573         }
 574
 575         if (!iwl3945_mod_params.sw_crypto)
 576                 iwl_set_decrypted_flag(priv,
 577                                        (struct ieee80211_hdr *)rxb_addr(rxb),
 578                                        le32_to_cpu(rx_end->status), stats);
 579
 580         skb_reserve(skb, IWL_LINK_HDR_MAX);
 581         skb_add_rx_frag(skb, 0, rxb->page,
 582                         (void *)rx_hdr->payload - (void *)pkt, len);
 583
 584         /* mac80211 currently doesn't support paged SKB. Convert it to
 585          * linear SKB for management frame and data frame requires
 586          * software decryption or software defragementation. */
 587         if (ieee80211_is_mgmt(fc) ||
 588             ieee80211_has_protected(fc) ||
 589             ieee80211_has_morefrags(fc) ||
 590             le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
 591                 ret = skb_linearize(skb);
 592         else
 593                 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
 594                         0 : -ENOMEM;
 595
 596         if (ret) {
 597                 kfree_skb(skb);
 598                 goto out;
 599         }
 600
 601         /*
 602          * XXX: We cannot touch the page and its virtual memory (pkt) after
 603          * here. It might have already been freed by the above skb change.
 604          */
 605
 606         iwl_update_stats(priv, false, fc, len);
 607         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 608
 609         ieee80211_rx(priv->hw, skb);
 610  out:
 611         priv->alloc_rxb_page--;
 612         rxb->page = NULL;
 613 }
 614
 615 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 616
 617 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 618                                 struct iwl_rx_mem_buffer *rxb)
 619 {
 620         struct ieee80211_hdr *header;
 621         struct ieee80211_rx_status rx_status;
 622         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 623         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 624         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 625         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 626         int snr;
 627         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 628         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 629         u8 network_packet;
 630
 631         rx_status.flag = 0;
 632         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 633         rx_status.freq =
 634                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 635         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 636                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 637
 638         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 639         if (rx_status.band == IEEE80211_BAND_5GHZ)
 640                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 641
 642         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
 643                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 644
 645         /* set the preamble flag if appropriate */
 646         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 647                 rx_status.flag |= RX_FLAG_SHORTPRE;
 648
 649         if ((unlikely(rx_stats->phy_count > 20))) {
 650                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 651                                 rx_stats->phy_count);
 652                 return;
 653         }
 654
 655         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 656             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 657                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 658                 return;
 659         }
 660
 661
 662
 663         /* Convert 3945's rssi indicator to dBm */
 664         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 665
 666         /* Set default noise value to -127 */
 667         if (priv->last_rx_noise == 0)
 668                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 669
 670         /* 3945 provides noise info for OFDM frames only.
 671          * sig_avg and noise_diff are measured by the 3945's digital signal
 672          *   processor (DSP), and indicate linear levels of signal level and
 673          *   distortion/noise within the packet preamble after
 674          *   automatic gain control (AGC).  sig_avg should stay fairly
 675          *   constant if the radio's AGC is working well.
 676          * Since these values are linear (not dB or dBm), linear
 677          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 678          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 679          *   to obtain noise level in dBm.
 680          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 681         if (rx_stats_noise_diff) {
 682                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 683                 rx_status.noise = rx_status.signal -
 684                                         iwl3945_calc_db_from_ratio(snr);
 685         } else {
 686                 rx_status.noise = priv->last_rx_noise;
 687         }
 688
 689
 690         IWL_DEBUG_STATS(priv, "Rssi %d noise %d sig_avg %d noise_diff %d\n",
 691                         rx_status.signal, rx_status.noise,
 692                         rx_stats_sig_avg, rx_stats_noise_diff);
 693
 694         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 695
 696         network_packet = iwl3945_is_network_packet(priv, header);
 697
 698         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 699                               network_packet ? '*' : ' ',
 700                               le16_to_cpu(rx_hdr->channel),
 701                               rx_status.signal, rx_status.signal,
 702                               rx_status.noise, rx_status.rate_idx);
 703
 704         /* Set "1" to report good data frames in groups of 100 */
 705         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 706         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 707
 708         if (network_packet) {
 709                 priv->_3945.last_beacon_time =
 710                         le32_to_cpu(rx_end->beacon_timestamp);
 711                 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
 712                 priv->_3945.last_rx_rssi = rx_status.signal;
 713                 priv->last_rx_noise = rx_status.noise;
 714         }
 715
 716         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 717 }
 718
 719 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 720                                      struct iwl_tx_queue *txq,
 721                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 722 {
 723         int count;
 724         struct iwl_queue *q;
 725         struct iwl3945_tfd *tfd, *tfd_tmp;
 726
 727         q = &txq->q;
 728         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 729         tfd = &tfd_tmp[q->write_ptr];
 730
 731         if (reset)
 732                 memset(tfd, 0, sizeof(*tfd));
 733
 734         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 735
 736         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 737                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 738                           NUM_TFD_CHUNKS);
 739                 return -EINVAL;
 740         }
 741
 742         tfd->tbs[count].addr = cpu_to_le32(addr);
 743         tfd->tbs[count].len = cpu_to_le32(len);
 744
 745         count++;
 746
 747         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 748                                          TFD_CTL_PAD_SET(pad));
 749
 750         return 0;
 751 }
 752
 753 /**
 754  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 755  *
 756  * Does NOT advance any indexes
 757  */
 758 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 759 {
 760         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 761         int index = txq->q.read_ptr;
 762         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 763         struct pci_dev *dev = priv->pci_dev;
 764         int i;
 765         int counter;
 766
 767         /* sanity check */
 768         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 769         if (counter > NUM_TFD_CHUNKS) {
 770                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 771                 /* @todo issue fatal error, it is quite serious situation */
 772                 return;
 773         }
 774
 775         /* Unmap tx_cmd */
 776         if (counter)
 777                 pci_unmap_single(dev,
 778                                 pci_unmap_addr(&txq->meta[index], mapping),
 779                                 pci_unmap_len(&txq->meta[index], len),
 780                                 PCI_DMA_TODEVICE);
 781
 782         /* unmap chunks if any */
 783
 784         for (i = 1; i < counter; i++) {
 785                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 786                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 787                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 788                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 789                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 790                                 /* Can be called from interrupt context */
 791                                 dev_kfree_skb_any(skb);
 792                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 793                         }
 794                 }
 795         }
 796         return ;
 797 }
 798
 799 /**
 800  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 801  *
 802 */
 803 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 804                                   struct iwl_device_cmd *cmd,
 805                                   struct ieee80211_tx_info *info,
 806                                   struct ieee80211_hdr *hdr,
 807                                   int sta_id, int tx_id)
 808 {
 809         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 810         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
 811         u16 rate_mask;
 812         int rate;
 813         u8 rts_retry_limit;
 814         u8 data_retry_limit;
 815         __le32 tx_flags;
 816         __le16 fc = hdr->frame_control;
 817         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 818
 819         rate = iwl3945_rates[rate_index].plcp;
 820         tx_flags = tx_cmd->tx_flags;
 821
 822         /* We need to figure out how to get the sta->supp_rates while
 823          * in this running context */
 824         rate_mask = IWL_RATES_MASK;
 825
 826
 827         /* Set retry limit on DATA packets and Probe Responses*/
 828         if (ieee80211_is_probe_resp(fc))
 829                 data_retry_limit = 3;
 830         else
 831                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 832         tx_cmd->data_retry_limit = data_retry_limit;
 833
 834         if (tx_id >= IWL_CMD_QUEUE_NUM)
 835                 rts_retry_limit = 3;
 836         else
 837                 rts_retry_limit = 7;
 838
 839         if (data_retry_limit < rts_retry_limit)
 840                 rts_retry_limit = data_retry_limit;
 841         tx_cmd->rts_retry_limit = rts_retry_limit;
 842
 843         if (ieee80211_is_mgmt(fc)) {
 844                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 845                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 846                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 847                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 848                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 849                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 850                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 851                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 852                         }
 853                         break;
 854                 default:
 855                         break;
 856                 }
 857         }
 858
 859         tx_cmd->rate = rate;
 860         tx_cmd->tx_flags = tx_flags;
 861
 862         /* OFDM */
 863         tx_cmd->supp_rates[0] =
 864            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 865
 866         /* CCK */
 867         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
 868
 869         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 870                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 871                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
 872                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
 873 }
 874
 875 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 876 {
 877         unsigned long flags_spin;
 878         struct iwl_station_entry *station;
 879
 880         if (sta_id == IWL_INVALID_STATION)
 881                 return IWL_INVALID_STATION;
 882
 883         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 884         station = &priv->stations[sta_id];
 885
 886         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 887         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 888         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 889
 890         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 891
 892         iwl_send_add_sta(priv, &station->sta, flags);
 893         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 894                         sta_id, tx_rate);
 895         return sta_id;
 896 }
 897
 898 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 899 {
 900         if (src == IWL_PWR_SRC_VAUX) {
 901                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 902                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 903                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 904                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 905
 906                         iwl_poll_bit(priv, CSR_GPIO_IN,
 907                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 908                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 909                 }
 910         } else {
 911                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 912                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 913                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 914
 915                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 916                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 917         }
 918
 919         return 0;
 920 }
 921
 922 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 923 {
 924         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 925         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 926         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 927         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 928                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 929                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 930                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 931                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 932                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 933                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 934                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 935                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 936
 937         /* fake read to flush all prev I/O */
 938         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 939
 940         return 0;
 941 }
 942
 943 static int iwl3945_tx_reset(struct iwl_priv *priv)
 944 {
 945
 946         /* bypass mode */
 947         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 948
 949         /* RA 0 is active */
 950         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 951
 952         /* all 6 fifo are active */
 953         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 954
 955         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 956         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 957         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 958         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 959
 960         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 961                              priv->_3945.shared_phys);
 962
 963         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 964                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 965                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 966                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 967                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 968                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 969                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 970                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 971
 972
 973         return 0;
 974 }
 975
 976 /**
 977  * iwl3945_txq_ctx_reset - Reset TX queue context
 978  *
 979  * Destroys all DMA structures and initialize them again
 980  */
 981 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 982 {
 983         int rc;
 984         int txq_id, slots_num;
 985
 986         iwl3945_hw_txq_ctx_free(priv);
 987
 988         /* allocate tx queue structure */
 989         rc = iwl_alloc_txq_mem(priv);
 990         if (rc)
 991                 return rc;
 992
 993         /* Tx CMD queue */
 994         rc = iwl3945_tx_reset(priv);
 995         if (rc)
 996                 goto error;
 997
 998         /* Tx queue(s) */
 999         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1000                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1001                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1002                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1003                                        txq_id);
1004                 if (rc) {
1005                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1006                         goto error;
1007                 }
1008         }
1009
1010         return rc;
1011
1012  error:
1013         iwl3945_hw_txq_ctx_free(priv);
1014         return rc;
1015 }
1016
1017
1018 /*
1019  * Start up 3945's basic functionality after it has been reset
1020  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1021  * NOTE:  This does not load uCode nor start the embedded processor
1022  */
1023 static int iwl3945_apm_init(struct iwl_priv *priv)
1024 {
1025         int ret = iwl_apm_init(priv);
1026
1027         /* Clear APMG (NIC's internal power management) interrupts */
1028         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1029         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1030
1031         /* Reset radio chip */
1032         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1033         udelay(5);
1034         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1035
1036         return ret;
1037 }
1038
1039 static void iwl3945_nic_config(struct iwl_priv *priv)
1040 {
1041         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1042         unsigned long flags;
1043         u8 rev_id = 0;
1044
1045         spin_lock_irqsave(&priv->lock, flags);
1046
1047         /* Determine HW type */
1048         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1049
1050         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1051
1052         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1053                 IWL_DEBUG_INFO(priv, "RTP type \n");
1054         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1055                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1056                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1057                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1058         } else {
1059                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1060                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1061                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1062         }
1063
1064         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1065                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1066                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1067                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1068         } else
1069                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1070
1071         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1072                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1073                                eeprom->board_revision);
1074                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1075                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1076         } else {
1077                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1078                                eeprom->board_revision);
1079                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1080                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1081         }
1082
1083         if (eeprom->almgor_m_version <= 1) {
1084                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1085                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1086                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1087                                eeprom->almgor_m_version);
1088         } else {
1089                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1090                                eeprom->almgor_m_version);
1091                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1092                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1093         }
1094         spin_unlock_irqrestore(&priv->lock, flags);
1095
1096         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1097                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1098
1099         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1100                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1101 }
1102
1103 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1104 {
1105         int rc;
1106         unsigned long flags;
1107         struct iwl_rx_queue *rxq = &priv->rxq;
1108
1109         spin_lock_irqsave(&priv->lock, flags);
1110         priv->cfg->ops->lib->apm_ops.init(priv);
1111         spin_unlock_irqrestore(&priv->lock, flags);
1112
1113         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1114         if (rc)
1115                 return rc;
1116
1117         priv->cfg->ops->lib->apm_ops.config(priv);
1118
1119         /* Allocate the RX queue, or reset if it is already allocated */
1120         if (!rxq->bd) {
1121                 rc = iwl_rx_queue_alloc(priv);
1122                 if (rc) {
1123                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1124                         return -ENOMEM;
1125                 }
1126         } else
1127                 iwl3945_rx_queue_reset(priv, rxq);
1128
1129         iwl3945_rx_replenish(priv);
1130
1131         iwl3945_rx_init(priv, rxq);
1132
1133
1134         /* Look at using this instead:
1135         rxq->need_update = 1;
1136         iwl_rx_queue_update_write_ptr(priv, rxq);
1137         */
1138
1139         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1140
1141         rc = iwl3945_txq_ctx_reset(priv);
1142         if (rc)
1143                 return rc;
1144
1145         set_bit(STATUS_INIT, &priv->status);
1146
1147         return 0;
1148 }
1149
1150 /**
1151  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1152  *
1153  * Destroy all TX DMA queues and structures
1154  */
1155 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1156 {
1157         int txq_id;
1158
1159         /* Tx queues */
1160         if (priv->txq)
1161                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1162                      txq_id++)
1163                         if (txq_id == IWL_CMD_QUEUE_NUM)
1164                                 iwl_cmd_queue_free(priv);
1165                         else
1166                                 iwl_tx_queue_free(priv, txq_id);
1167
1168         /* free tx queue structure */
1169         iwl_free_txq_mem(priv);
1170 }
1171
1172 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1173 {
1174         int txq_id;
1175
1176         /* stop SCD */
1177         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1178         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1179
1180         /* reset TFD queues */
1181         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1182                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1183                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1184                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1185                                 1000);
1186         }
1187
1188         iwl3945_hw_txq_ctx_free(priv);
1189 }
1190
1191 /**
1192  * iwl3945_hw_reg_adjust_power_by_temp
1193  * return index delta into power gain settings table
1194 */
1195 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1196 {
1197         return (new_reading - old_reading) * (-11) / 100;
1198 }
1199
1200 /**
1201  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1202  */
1203 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1204 {
1205         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1206 }
1207
1208 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1209 {
1210         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1211 }
1212
1213 /**
1214  * iwl3945_hw_reg_txpower_get_temperature
1215  * get the current temperature by reading from NIC
1216 */
1217 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1218 {
1219         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1220         int temperature;
1221
1222         temperature = iwl3945_hw_get_temperature(priv);
1223
1224         /* driver's okay range is -260 to +25.
1225          *   human readable okay range is 0 to +285 */
1226         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1227
1228         /* handle insane temp reading */
1229         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1230                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1231
1232                 /* if really really hot(?),
1233                  *   substitute the 3rd band/group's temp measured at factory */
1234                 if (priv->last_temperature > 100)
1235                         temperature = eeprom->groups[2].temperature;
1236                 else /* else use most recent "sane" value from driver */
1237                         temperature = priv->last_temperature;
1238         }
1239
1240         return temperature;     /* raw, not "human readable" */
1241 }
1242
1243 /* Adjust Txpower only if temperature variance is greater than threshold.
1244  *
1245  * Both are lower than older versions' 9 degrees */
1246 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1247
1248 /**
1249  * is_temp_calib_needed - determines if new calibration is needed
1250  *
1251  * records new temperature in tx_mgr->temperature.
1252  * replaces tx_mgr->last_temperature *only* if calib needed
1253  *    (assumes caller will actually do the calibration!). */
1254 static int is_temp_calib_needed(struct iwl_priv *priv)
1255 {
1256         int temp_diff;
1257
1258         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1259         temp_diff = priv->temperature - priv->last_temperature;
1260
1261         /* get absolute value */
1262         if (temp_diff < 0) {
1263                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1264                 temp_diff = -temp_diff;
1265         } else if (temp_diff == 0)
1266                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1267         else
1268                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1269
1270         /* if we don't need calibration, *don't* update last_temperature */
1271         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1272                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1273                 return 0;
1274         }
1275
1276         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1277
1278         /* assume that caller will actually do calib ...
1279          *   update the "last temperature" value */
1280         priv->last_temperature = priv->temperature;
1281         return 1;
1282 }
1283
1284 #define IWL_MAX_GAIN_ENTRIES 78
1285 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1286 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1287
1288 /* radio and DSP power table, each step is 1/2 dB.
1289  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1290 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1291         {
1292          {251, 127},            /* 2.4 GHz, highest power */
1293          {251, 127},
1294          {251, 127},
1295          {251, 127},
1296          {251, 125},
1297          {251, 110},
1298          {251, 105},
1299          {251, 98},
1300          {187, 125},
1301          {187, 115},
1302          {187, 108},
1303          {187, 99},
1304          {243, 119},
1305          {243, 111},
1306          {243, 105},
1307          {243, 97},
1308          {243, 92},
1309          {211, 106},
1310          {211, 100},
1311          {179, 120},
1312          {179, 113},
1313          {179, 107},
1314          {147, 125},
1315          {147, 119},
1316          {147, 112},
1317          {147, 106},
1318          {147, 101},
1319          {147, 97},
1320          {147, 91},
1321          {115, 107},
1322          {235, 121},
1323          {235, 115},
1324          {235, 109},
1325          {203, 127},
1326          {203, 121},
1327          {203, 115},
1328          {203, 108},
1329          {203, 102},
1330          {203, 96},
1331          {203, 92},
1332          {171, 110},
1333          {171, 104},
1334          {171, 98},
1335          {139, 116},
1336          {227, 125},
1337          {227, 119},
1338          {227, 113},
1339          {227, 107},
1340          {227, 101},
1341          {227, 96},
1342          {195, 113},
1343          {195, 106},
1344          {195, 102},
1345          {195, 95},
1346          {163, 113},
1347          {163, 106},
1348          {163, 102},
1349          {163, 95},
1350          {131, 113},
1351          {131, 106},
1352          {131, 102},
1353          {131, 95},
1354          {99, 113},
1355          {99, 106},
1356          {99, 102},
1357          {99, 95},
1358          {67, 113},
1359          {67, 106},
1360          {67, 102},
1361          {67, 95},
1362          {35, 113},
1363          {35, 106},
1364          {35, 102},
1365          {35, 95},
1366          {3, 113},
1367          {3, 106},
1368          {3, 102},
1369          {3, 95} },             /* 2.4 GHz, lowest power */
1370         {
1371          {251, 127},            /* 5.x GHz, highest power */
1372          {251, 120},
1373          {251, 114},
1374          {219, 119},
1375          {219, 101},
1376          {187, 113},
1377          {187, 102},
1378          {155, 114},
1379          {155, 103},
1380          {123, 117},
1381          {123, 107},
1382          {123, 99},
1383          {123, 92},
1384          {91, 108},
1385          {59, 125},
1386          {59, 118},
1387          {59, 109},
1388          {59, 102},
1389          {59, 96},
1390          {59, 90},
1391          {27, 104},
1392          {27, 98},
1393          {27, 92},
1394          {115, 118},
1395          {115, 111},
1396          {115, 104},
1397          {83, 126},
1398          {83, 121},
1399          {83, 113},
1400          {83, 105},
1401          {83, 99},
1402          {51, 118},
1403          {51, 111},
1404          {51, 104},
1405          {51, 98},
1406          {19, 116},
1407          {19, 109},
1408          {19, 102},
1409          {19, 98},
1410          {19, 93},
1411          {171, 113},
1412          {171, 107},
1413          {171, 99},
1414          {139, 120},
1415          {139, 113},
1416          {139, 107},
1417          {139, 99},
1418          {107, 120},
1419          {107, 113},
1420          {107, 107},
1421          {107, 99},
1422          {75, 120},
1423          {75, 113},
1424          {75, 107},
1425          {75, 99},
1426          {43, 120},
1427          {43, 113},
1428          {43, 107},
1429          {43, 99},
1430          {11, 120},
1431          {11, 113},
1432          {11, 107},
1433          {11, 99},
1434          {131, 107},
1435          {131, 99},
1436          {99, 120},
1437          {99, 113},
1438          {99, 107},
1439          {99, 99},
1440          {67, 120},
1441          {67, 113},
1442          {67, 107},
1443          {67, 99},
1444          {35, 120},
1445          {35, 113},
1446          {35, 107},
1447          {35, 99},
1448          {3, 120} }             /* 5.x GHz, lowest power */
1449 };
1450
1451 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1452 {
1453         if (index < 0)
1454                 return 0;
1455         if (index >= IWL_MAX_GAIN_ENTRIES)
1456                 return IWL_MAX_GAIN_ENTRIES - 1;
1457         return (u8) index;
1458 }
1459
1460 /* Kick off thermal recalibration check every 60 seconds */
1461 #define REG_RECALIB_PERIOD (60)
1462
1463 /**
1464  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1465  *
1466  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1467  * or 6 Mbit (OFDM) rates.
1468  */
1469 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1470                                s32 rate_index, const s8 *clip_pwrs,
1471                                struct iwl_channel_info *ch_info,
1472                                int band_index)
1473 {
1474         struct iwl3945_scan_power_info *scan_power_info;
1475         s8 power;
1476         u8 power_index;
1477
1478         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1479
1480         /* use this channel group's 6Mbit clipping/saturation pwr,
1481          *   but cap at regulatory scan power restriction (set during init
1482          *   based on eeprom channel data) for this channel.  */
1483         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1484
1485         /* further limit to user's max power preference.
1486          * FIXME:  Other spectrum management power limitations do not
1487          *   seem to apply?? */
1488         power = min(power, priv->tx_power_user_lmt);
1489         scan_power_info->requested_power = power;
1490
1491         /* find difference between new scan *power* and current "normal"
1492          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1493          *   current "normal" temperature-compensated Tx power *index* for
1494          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1495          *   *index*. */
1496         power_index = ch_info->power_info[rate_index].power_table_index
1497             - (power - ch_info->power_info
1498                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1499
1500         /* store reference index that we use when adjusting *all* scan
1501          *   powers.  So we can accommodate user (all channel) or spectrum
1502          *   management (single channel) power changes "between" temperature
1503          *   feedback compensation procedures.
1504          * don't force fit this reference index into gain table; it may be a
1505          *   negative number.  This will help avoid errors when we're at
1506          *   the lower bounds (highest gains, for warmest temperatures)
1507          *   of the table. */
1508
1509         /* don't exceed table bounds for "real" setting */
1510         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1511
1512         scan_power_info->power_table_index = power_index;
1513         scan_power_info->tpc.tx_gain =
1514             power_gain_table[band_index][power_index].tx_gain;
1515         scan_power_info->tpc.dsp_atten =
1516             power_gain_table[band_index][power_index].dsp_atten;
1517 }
1518
1519 /**
1520  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1521  *
1522  * Configures power settings for all rates for the current channel,
1523  * using values from channel info struct, and send to NIC
1524  */
1525 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1526 {
1527         int rate_idx, i;
1528         const struct iwl_channel_info *ch_info = NULL;
1529         struct iwl3945_txpowertable_cmd txpower = {
1530                 .channel = priv->active_rxon.channel,
1531         };
1532
1533         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1534         ch_info = iwl_get_channel_info(priv,
1535                                        priv->band,
1536                                        le16_to_cpu(priv->active_rxon.channel));
1537         if (!ch_info) {
1538                 IWL_ERR(priv,
1539                         "Failed to get channel info for channel %d [%d]\n",
1540                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1541                 return -EINVAL;
1542         }
1543
1544         if (!is_channel_valid(ch_info)) {
1545                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1546                                 "non-Tx channel.\n");
1547                 return 0;
1548         }
1549
1550         /* fill cmd with power settings for all rates for current channel */
1551         /* Fill OFDM rate */
1552         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1553              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1554
1555                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1556                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1557
1558                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1559                                 le16_to_cpu(txpower.channel),
1560                                 txpower.band,
1561                                 txpower.power[i].tpc.tx_gain,
1562                                 txpower.power[i].tpc.dsp_atten,
1563                                 txpower.power[i].rate);
1564         }
1565         /* Fill CCK rates */
1566         for (rate_idx = IWL_FIRST_CCK_RATE;
1567              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1568                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1569                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1570
1571                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1572                                 le16_to_cpu(txpower.channel),
1573                                 txpower.band,
1574                                 txpower.power[i].tpc.tx_gain,
1575                                 txpower.power[i].tpc.dsp_atten,
1576                                 txpower.power[i].rate);
1577         }
1578
1579         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1580                                 sizeof(struct iwl3945_txpowertable_cmd),
1581                                 &txpower);
1582
1583 }
1584
1585 /**
1586  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1587  * @ch_info: Channel to update.  Uses power_info.requested_power.
1588  *
1589  * Replace requested_power and base_power_index ch_info fields for
1590  * one channel.
1591  *
1592  * Called if user or spectrum management changes power preferences.
1593  * Takes into account h/w and modulation limitations (clip power).
1594  *
1595  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1596  *
1597  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1598  *       properly fill out the scan powers, and actual h/w gain settings,
1599  *       and send changes to NIC
1600  */
1601 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1602                              struct iwl_channel_info *ch_info)
1603 {
1604         struct iwl3945_channel_power_info *power_info;
1605         int power_changed = 0;
1606         int i;
1607         const s8 *clip_pwrs;
1608         int power;
1609
1610         /* Get this chnlgrp's rate-to-max/clip-powers table */
1611         clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1612
1613         /* Get this channel's rate-to-current-power settings table */
1614         power_info = ch_info->power_info;
1615
1616         /* update OFDM Txpower settings */
1617         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1618              i++, ++power_info) {
1619                 int delta_idx;
1620
1621                 /* limit new power to be no more than h/w capability */
1622                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1623                 if (power == power_info->requested_power)
1624                         continue;
1625
1626                 /* find difference between old and new requested powers,
1627                  *    update base (non-temp-compensated) power index */
1628                 delta_idx = (power - power_info->requested_power) * 2;
1629                 power_info->base_power_index -= delta_idx;
1630
1631                 /* save new requested power value */
1632                 power_info->requested_power = power;
1633
1634                 power_changed = 1;
1635         }
1636
1637         /* update CCK Txpower settings, based on OFDM 12M setting ...
1638          *    ... all CCK power settings for a given channel are the *same*. */
1639         if (power_changed) {
1640                 power =
1641                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1642                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1643
1644                 /* do all CCK rates' iwl3945_channel_power_info structures */
1645                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1646                         power_info->requested_power = power;
1647                         power_info->base_power_index =
1648                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1649                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1650                         ++power_info;
1651                 }
1652         }
1653
1654         return 0;
1655 }
1656
1657 /**
1658  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1659  *
1660  * NOTE: Returned power limit may be less (but not more) than requested,
1661  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1662  *       (no consideration for h/w clipping limitations).
1663  */
1664 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1665 {
1666         s8 max_power;
1667
1668 #if 0
1669         /* if we're using TGd limits, use lower of TGd or EEPROM */
1670         if (ch_info->tgd_data.max_power != 0)
1671                 max_power = min(ch_info->tgd_data.max_power,
1672                                 ch_info->eeprom.max_power_avg);
1673
1674         /* else just use EEPROM limits */
1675         else
1676 #endif
1677                 max_power = ch_info->eeprom.max_power_avg;
1678
1679         return min(max_power, ch_info->max_power_avg);
1680 }
1681
1682 /**
1683  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1684  *
1685  * Compensate txpower settings of *all* channels for temperature.
1686  * This only accounts for the difference between current temperature
1687  *   and the factory calibration temperatures, and bases the new settings
1688  *   on the channel's base_power_index.
1689  *
1690  * If RxOn is "associated", this sends the new Txpower to NIC!
1691  */
1692 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1693 {
1694         struct iwl_channel_info *ch_info = NULL;
1695         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1696         int delta_index;
1697         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1698         u8 a_band;
1699         u8 rate_index;
1700         u8 scan_tbl_index;
1701         u8 i;
1702         int ref_temp;
1703         int temperature = priv->temperature;
1704
1705         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1706         for (i = 0; i < priv->channel_count; i++) {
1707                 ch_info = &priv->channel_info[i];
1708                 a_band = is_channel_a_band(ch_info);
1709
1710                 /* Get this chnlgrp's factory calibration temperature */
1711                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1712                     temperature;
1713
1714                 /* get power index adjustment based on current and factory
1715                  * temps */
1716                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1717                                                               ref_temp);
1718
1719                 /* set tx power value for all rates, OFDM and CCK */
1720                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1721                      rate_index++) {
1722                         int power_idx =
1723                             ch_info->power_info[rate_index].base_power_index;
1724
1725                         /* temperature compensate */
1726                         power_idx += delta_index;
1727
1728                         /* stay within table range */
1729                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1730                         ch_info->power_info[rate_index].
1731                             power_table_index = (u8) power_idx;
1732                         ch_info->power_info[rate_index].tpc =
1733                             power_gain_table[a_band][power_idx];
1734                 }
1735
1736                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1737                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1738
1739                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1740                 for (scan_tbl_index = 0;
1741                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1742                         s32 actual_index = (scan_tbl_index == 0) ?
1743                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1744                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1745                                            actual_index, clip_pwrs,
1746                                            ch_info, a_band);
1747                 }
1748         }
1749
1750         /* send Txpower command for current channel to ucode */
1751         return priv->cfg->ops->lib->send_tx_power(priv);
1752 }
1753
1754 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1755 {
1756         struct iwl_channel_info *ch_info;
1757         s8 max_power;
1758         u8 a_band;
1759         u8 i;
1760
1761         if (priv->tx_power_user_lmt == power) {
1762                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1763                                 "limit: %ddBm.\n", power);
1764                 return 0;
1765         }
1766
1767         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1768         priv->tx_power_user_lmt = power;
1769
1770         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1771
1772         for (i = 0; i < priv->channel_count; i++) {
1773                 ch_info = &priv->channel_info[i];
1774                 a_band = is_channel_a_band(ch_info);
1775
1776                 /* find minimum power of all user and regulatory constraints
1777                  *    (does not consider h/w clipping limitations) */
1778                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1779                 max_power = min(power, max_power);
1780                 if (max_power != ch_info->curr_txpow) {
1781                         ch_info->curr_txpow = max_power;
1782
1783                         /* this considers the h/w clipping limitations */
1784                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1785                 }
1786         }
1787
1788         /* update txpower settings for all channels,
1789          *   send to NIC if associated. */
1790         is_temp_calib_needed(priv);
1791         iwl3945_hw_reg_comp_txpower_temp(priv);
1792
1793         return 0;
1794 }
1795
1796 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1797 {
1798         int rc = 0;
1799         struct iwl_rx_packet *pkt;
1800         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1801         struct iwl_host_cmd cmd = {
1802                 .id = REPLY_RXON_ASSOC,
1803                 .len = sizeof(rxon_assoc),
1804                 .flags = CMD_WANT_SKB,
1805                 .data = &rxon_assoc,
1806         };
1807         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1808         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1809
1810         if ((rxon1->flags == rxon2->flags) &&
1811             (rxon1->filter_flags == rxon2->filter_flags) &&
1812             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1813             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1814                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1815                 return 0;
1816         }
1817
1818         rxon_assoc.flags = priv->staging_rxon.flags;
1819         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1820         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1821         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1822         rxon_assoc.reserved = 0;
1823
1824         rc = iwl_send_cmd_sync(priv, &cmd);
1825         if (rc)
1826                 return rc;
1827
1828         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1829         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1830                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1831                 rc = -EIO;
1832         }
1833
1834         iwl_free_pages(priv, cmd.reply_page);
1835
1836         return rc;
1837 }
1838
1839 /**
1840  * iwl3945_commit_rxon - commit staging_rxon to hardware
1841  *
1842  * The RXON command in staging_rxon is committed to the hardware and
1843  * the active_rxon structure is updated with the new data.  This
1844  * function correctly transitions out of the RXON_ASSOC_MSK state if
1845  * a HW tune is required based on the RXON structure changes.
1846  */
1847 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1848 {
1849         /* cast away the const for active_rxon in this function */
1850         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1851         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1852         int rc = 0;
1853         bool new_assoc =
1854                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1855
1856         if (!iwl_is_alive(priv))
1857                 return -1;
1858
1859         /* always get timestamp with Rx frame */
1860         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1861
1862         /* select antenna */
1863         staging_rxon->flags &=
1864             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1865         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1866
1867         rc = iwl_check_rxon_cmd(priv);
1868         if (rc) {
1869                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1870                 return -EINVAL;
1871         }
1872
1873         /* If we don't need to send a full RXON, we can use
1874          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1875          * and other flags for the current radio configuration. */
1876         if (!iwl_full_rxon_required(priv)) {
1877                 rc = iwl_send_rxon_assoc(priv);
1878                 if (rc) {
1879                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1880                                   "configuration (%d).\n", rc);
1881                         return rc;
1882                 }
1883
1884                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1885
1886                 return 0;
1887         }
1888
1889         /* If we are currently associated and the new config requires
1890          * an RXON_ASSOC and the new config wants the associated mask enabled,
1891          * we must clear the associated from the active configuration
1892          * before we apply the new config */
1893         if (iwl_is_associated(priv) && new_assoc) {
1894                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1895                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1896
1897                 /*
1898                  * reserved4 and 5 could have been filled by the iwlcore code.
1899                  * Let's clear them before pushing to the 3945.
1900                  */
1901                 active_rxon->reserved4 = 0;
1902                 active_rxon->reserved5 = 0;
1903                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1904                                       sizeof(struct iwl3945_rxon_cmd),
1905                                       &priv->active_rxon);
1906
1907                 /* If the mask clearing failed then we set
1908                  * active_rxon back to what it was previously */
1909                 if (rc) {
1910                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1911                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1912                                   "configuration (%d).\n", rc);
1913                         return rc;
1914                 }
1915                 iwl_clear_ucode_stations(priv, false);
1916                 iwl_restore_stations(priv);
1917         }
1918
1919         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1920                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1921                        "* channel = %d\n"
1922                        "* bssid = %pM\n",
1923                        (new_assoc ? "" : "out"),
1924                        le16_to_cpu(staging_rxon->channel),
1925                        staging_rxon->bssid_addr);
1926
1927         /*
1928          * reserved4 and 5 could have been filled by the iwlcore code.
1929          * Let's clear them before pushing to the 3945.
1930          */
1931         staging_rxon->reserved4 = 0;
1932         staging_rxon->reserved5 = 0;
1933
1934         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1935
1936         /* Apply the new configuration */
1937         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1938                               sizeof(struct iwl3945_rxon_cmd),
1939                               staging_rxon);
1940         if (rc) {
1941                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1942                 return rc;
1943         }
1944
1945         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1946
1947         if (!new_assoc) {
1948                 iwl_clear_ucode_stations(priv, false);
1949                 iwl_restore_stations(priv);
1950         }
1951
1952         /* If we issue a new RXON command which required a tune then we must
1953          * send a new TXPOWER command or we won't be able to Tx any frames */
1954         rc = priv->cfg->ops->lib->send_tx_power(priv);
1955         if (rc) {
1956                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1957                 return rc;
1958         }
1959
1960         /* Init the hardware's rate fallback order based on the band */
1961         rc = iwl3945_init_hw_rate_table(priv);
1962         if (rc) {
1963                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1964                 return -EIO;
1965         }
1966
1967         return 0;
1968 }
1969
1970 /**
1971  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1972  *
1973  * -- reset periodic timer
1974  * -- see if temp has changed enough to warrant re-calibration ... if so:
1975  *     -- correct coeffs for temp (can reset temp timer)
1976  *     -- save this temp as "last",
1977  *     -- send new set of gain settings to NIC
1978  * NOTE:  This should continue working, even when we're not associated,
1979  *   so we can keep our internal table of scan powers current. */
1980 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1981 {
1982         /* This will kick in the "brute force"
1983          * iwl3945_hw_reg_comp_txpower_temp() below */
1984         if (!is_temp_calib_needed(priv))
1985                 goto reschedule;
1986
1987         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1988          * This is based *only* on current temperature,
1989          * ignoring any previous power measurements */
1990         iwl3945_hw_reg_comp_txpower_temp(priv);
1991
1992  reschedule:
1993         queue_delayed_work(priv->workqueue,
1994                            &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1995 }
1996
1997 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1998 {
1999         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2000                                              _3945.thermal_periodic.work);
2001
2002         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2003                 return;
2004
2005         mutex_lock(&priv->mutex);
2006         iwl3945_reg_txpower_periodic(priv);
2007         mutex_unlock(&priv->mutex);
2008 }
2009
2010 /**
2011  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2012  *                                 for the channel.
2013  *
2014  * This function is used when initializing channel-info structs.
2015  *
2016  * NOTE: These channel groups do *NOT* match the bands above!
2017  *       These channel groups are based on factory-tested channels;
2018  *       on A-band, EEPROM's "group frequency" entries represent the top
2019  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2020  */
2021 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2022                                        const struct iwl_channel_info *ch_info)
2023 {
2024         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2025         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2026         u8 group;
2027         u16 group_index = 0;    /* based on factory calib frequencies */
2028         u8 grp_channel;
2029
2030         /* Find the group index for the channel ... don't use index 1(?) */
2031         if (is_channel_a_band(ch_info)) {
2032                 for (group = 1; group < 5; group++) {
2033                         grp_channel = ch_grp[group].group_channel;
2034                         if (ch_info->channel <= grp_channel) {
2035                                 group_index = group;
2036                                 break;
2037                         }
2038                 }
2039                 /* group 4 has a few channels *above* its factory cal freq */
2040                 if (group == 5)
2041                         group_index = 4;
2042         } else
2043                 group_index = 0;        /* 2.4 GHz, group 0 */
2044
2045         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2046                         group_index);
2047         return group_index;
2048 }
2049
2050 /**
2051  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2052  *
2053  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2054  *   into radio/DSP gain settings table for requested power.
2055  */
2056 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2057                                        s8 requested_power,
2058                                        s32 setting_index, s32 *new_index)
2059 {
2060         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2061         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2062         s32 index0, index1;
2063         s32 power = 2 * requested_power;
2064         s32 i;
2065         const struct iwl3945_eeprom_txpower_sample *samples;
2066         s32 gains0, gains1;
2067         s32 res;
2068         s32 denominator;
2069
2070         chnl_grp = &eeprom->groups[setting_index];
2071         samples = chnl_grp->samples;
2072         for (i = 0; i < 5; i++) {
2073                 if (power == samples[i].power) {
2074                         *new_index = samples[i].gain_index;
2075                         return 0;
2076                 }
2077         }
2078
2079         if (power > samples[1].power) {
2080                 index0 = 0;
2081                 index1 = 1;
2082         } else if (power > samples[2].power) {
2083                 index0 = 1;
2084                 index1 = 2;
2085         } else if (power > samples[3].power) {
2086                 index0 = 2;
2087                 index1 = 3;
2088         } else {
2089                 index0 = 3;
2090                 index1 = 4;
2091         }
2092
2093         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2094         if (denominator == 0)
2095                 return -EINVAL;
2096         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2097         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2098         res = gains0 + (gains1 - gains0) *
2099             ((s32) power - (s32) samples[index0].power) / denominator +
2100             (1 << 18);
2101         *new_index = res >> 19;
2102         return 0;
2103 }
2104
2105 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2106 {
2107         u32 i;
2108         s32 rate_index;
2109         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2110         const struct iwl3945_eeprom_txpower_group *group;
2111
2112         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2113
2114         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2115                 s8 *clip_pwrs;  /* table of power levels for each rate */
2116                 s8 satur_pwr;   /* saturation power for each chnl group */
2117                 group = &eeprom->groups[i];
2118
2119                 /* sanity check on factory saturation power value */
2120                 if (group->saturation_power < 40) {
2121                         IWL_WARN(priv, "Error: saturation power is %d, "
2122                                     "less than minimum expected 40\n",
2123                                     group->saturation_power);
2124                         return;
2125                 }
2126
2127                 /*
2128                  * Derive requested power levels for each rate, based on
2129                  *   hardware capabilities (saturation power for band).
2130                  * Basic value is 3dB down from saturation, with further
2131                  *   power reductions for highest 3 data rates.  These
2132                  *   backoffs provide headroom for high rate modulation
2133                  *   power peaks, without too much distortion (clipping).
2134                  */
2135                 /* we'll fill in this array with h/w max power levels */
2136                 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2137
2138                 /* divide factory saturation power by 2 to find -3dB level */
2139                 satur_pwr = (s8) (group->saturation_power >> 1);
2140
2141                 /* fill in channel group's nominal powers for each rate */
2142                 for (rate_index = 0;
2143                      rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2144                         switch (rate_index) {
2145                         case IWL_RATE_36M_INDEX_TABLE:
2146                                 if (i == 0)     /* B/G */
2147                                         *clip_pwrs = satur_pwr;
2148                                 else    /* A */
2149                                         *clip_pwrs = satur_pwr - 5;
2150                                 break;
2151                         case IWL_RATE_48M_INDEX_TABLE:
2152                                 if (i == 0)
2153                                         *clip_pwrs = satur_pwr - 7;
2154                                 else
2155                                         *clip_pwrs = satur_pwr - 10;
2156                                 break;
2157                         case IWL_RATE_54M_INDEX_TABLE:
2158                                 if (i == 0)
2159                                         *clip_pwrs = satur_pwr - 9;
2160                                 else
2161                                         *clip_pwrs = satur_pwr - 12;
2162                                 break;
2163                         default:
2164                                 *clip_pwrs = satur_pwr;
2165                                 break;
2166                         }
2167                 }
2168         }
2169 }
2170
2171 /**
2172  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2173  *
2174  * Second pass (during init) to set up priv->channel_info
2175  *
2176  * Set up Tx-power settings in our channel info database for each VALID
2177  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2178  * and current temperature.
2179  *
2180  * Since this is based on current temperature (at init time), these values may
2181  * not be valid for very long, but it gives us a starting/default point,
2182  * and allows us to active (i.e. using Tx) scan.
2183  *
2184  * This does *not* write values to NIC, just sets up our internal table.
2185  */
2186 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2187 {
2188         struct iwl_channel_info *ch_info = NULL;
2189         struct iwl3945_channel_power_info *pwr_info;
2190         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2191         int delta_index;
2192         u8 rate_index;
2193         u8 scan_tbl_index;
2194         const s8 *clip_pwrs;    /* array of power levels for each rate */
2195         u8 gain, dsp_atten;
2196         s8 power;
2197         u8 pwr_index, base_pwr_index, a_band;
2198         u8 i;
2199         int temperature;
2200
2201         /* save temperature reference,
2202          *   so we can determine next time to calibrate */
2203         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2204         priv->last_temperature = temperature;
2205
2206         iwl3945_hw_reg_init_channel_groups(priv);
2207
2208         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2209         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2210              i++, ch_info++) {
2211                 a_band = is_channel_a_band(ch_info);
2212                 if (!is_channel_valid(ch_info))
2213                         continue;
2214
2215                 /* find this channel's channel group (*not* "band") index */
2216                 ch_info->group_index =
2217                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2218
2219                 /* Get this chnlgrp's rate->max/clip-powers table */
2220                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2221
2222                 /* calculate power index *adjustment* value according to
2223                  *  diff between current temperature and factory temperature */
2224                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2225                                 eeprom->groups[ch_info->group_index].
2226                                 temperature);
2227
2228                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2229                                 ch_info->channel, delta_index, temperature +
2230                                 IWL_TEMP_CONVERT);
2231
2232                 /* set tx power value for all OFDM rates */
2233                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2234                      rate_index++) {
2235                         s32 uninitialized_var(power_idx);
2236                         int rc;
2237
2238                         /* use channel group's clip-power table,
2239                          *   but don't exceed channel's max power */
2240                         s8 pwr = min(ch_info->max_power_avg,
2241                                      clip_pwrs[rate_index]);
2242
2243                         pwr_info = &ch_info->power_info[rate_index];
2244
2245                         /* get base (i.e. at factory-measured temperature)
2246                          *    power table index for this rate's power */
2247                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2248                                                          ch_info->group_index,
2249                                                          &power_idx);
2250                         if (rc) {
2251                                 IWL_ERR(priv, "Invalid power index\n");
2252                                 return rc;
2253                         }
2254                         pwr_info->base_power_index = (u8) power_idx;
2255
2256                         /* temperature compensate */
2257                         power_idx += delta_index;
2258
2259                         /* stay within range of gain table */
2260                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2261
2262                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2263                         pwr_info->requested_power = pwr;
2264                         pwr_info->power_table_index = (u8) power_idx;
2265                         pwr_info->tpc.tx_gain =
2266                             power_gain_table[a_band][power_idx].tx_gain;
2267                         pwr_info->tpc.dsp_atten =
2268                             power_gain_table[a_band][power_idx].dsp_atten;
2269                 }
2270
2271                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2272                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2273                 power = pwr_info->requested_power +
2274                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2275                 pwr_index = pwr_info->power_table_index +
2276                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2277                 base_pwr_index = pwr_info->base_power_index +
2278                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2279
2280                 /* stay within table range */
2281                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2282                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2283                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2284
2285                 /* fill each CCK rate's iwl3945_channel_power_info structure
2286                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2287                  * NOTE:  CCK rates start at end of OFDM rates! */
2288                 for (rate_index = 0;
2289                      rate_index < IWL_CCK_RATES; rate_index++) {
2290                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2291                         pwr_info->requested_power = power;
2292                         pwr_info->power_table_index = pwr_index;
2293                         pwr_info->base_power_index = base_pwr_index;
2294                         pwr_info->tpc.tx_gain = gain;
2295                         pwr_info->tpc.dsp_atten = dsp_atten;
2296                 }
2297
2298                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2299                 for (scan_tbl_index = 0;
2300                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2301                         s32 actual_index = (scan_tbl_index == 0) ?
2302                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2303                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2304                                 actual_index, clip_pwrs, ch_info, a_band);
2305                 }
2306         }
2307
2308         return 0;
2309 }
2310
2311 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2312 {
2313         int rc;
2314
2315         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2316         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2317                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2318         if (rc < 0)
2319                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2320
2321         return 0;
2322 }
2323
2324 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2325 {
2326         int txq_id = txq->q.id;
2327
2328         struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2329
2330         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2331
2332         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2333         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2334
2335         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2336                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2337                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2338                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2339                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2340                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2341
2342         /* fake read to flush all prev. writes */
2343         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2344
2345         return 0;
2346 }
2347
2348 /*
2349  * HCMD utils
2350  */
2351 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2352 {
2353         switch (cmd_id) {
2354         case REPLY_RXON:
2355                 return sizeof(struct iwl3945_rxon_cmd);
2356         case POWER_TABLE_CMD:
2357                 return sizeof(struct iwl3945_powertable_cmd);
2358         default:
2359                 return len;
2360         }
2361 }
2362
2363
2364 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2365 {
2366         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2367         addsta->mode = cmd->mode;
2368         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2369         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2370         addsta->station_flags = cmd->station_flags;
2371         addsta->station_flags_msk = cmd->station_flags_msk;
2372         addsta->tid_disable_tx = cpu_to_le16(0);
2373         addsta->rate_n_flags = cmd->rate_n_flags;
2374         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2375         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2376         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2377
2378         return (u16)sizeof(struct iwl3945_addsta_cmd);
2379 }
2380
2381
2382 /**
2383  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2384  */
2385 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2386 {
2387         int rc, i, index, prev_index;
2388         struct iwl3945_rate_scaling_cmd rate_cmd = {
2389                 .reserved = {0, 0, 0},
2390         };
2391         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2392
2393         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2394                 index = iwl3945_rates[i].table_rs_index;
2395
2396                 table[index].rate_n_flags =
2397                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2398                 table[index].try_cnt = priv->retry_rate;
2399                 prev_index = iwl3945_get_prev_ieee_rate(i);
2400                 table[index].next_rate_index =
2401                                 iwl3945_rates[prev_index].table_rs_index;
2402         }
2403
2404         switch (priv->band) {
2405         case IEEE80211_BAND_5GHZ:
2406                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2407                 /* If one of the following CCK rates is used,
2408                  * have it fall back to the 6M OFDM rate */
2409                 for (i = IWL_RATE_1M_INDEX_TABLE;
2410                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2411                         table[i].next_rate_index =
2412                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2413
2414                 /* Don't fall back to CCK rates */
2415                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2416                                                 IWL_RATE_9M_INDEX_TABLE;
2417
2418                 /* Don't drop out of OFDM rates */
2419                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2420                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2421                 break;
2422
2423         case IEEE80211_BAND_2GHZ:
2424                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2425                 /* If an OFDM rate is used, have it fall back to the
2426                  * 1M CCK rates */
2427
2428                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2429                     iwl_is_associated(priv)) {
2430
2431                         index = IWL_FIRST_CCK_RATE;
2432                         for (i = IWL_RATE_6M_INDEX_TABLE;
2433                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2434                                 table[i].next_rate_index =
2435                                         iwl3945_rates[index].table_rs_index;
2436
2437                         index = IWL_RATE_11M_INDEX_TABLE;
2438                         /* CCK shouldn't fall back to OFDM... */
2439                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2440                 }
2441                 break;
2442
2443         default:
2444                 WARN_ON(1);
2445                 break;
2446         }
2447
2448         /* Update the rate scaling for control frame Tx */
2449         rate_cmd.table_id = 0;
2450         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2451                               &rate_cmd);
2452         if (rc)
2453                 return rc;
2454
2455         /* Update the rate scaling for data frame Tx */
2456         rate_cmd.table_id = 1;
2457         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2458                                 &rate_cmd);
2459 }
2460
2461 /* Called when initializing driver */
2462 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2463 {
2464         memset((void *)&priv->hw_params, 0,
2465                sizeof(struct iwl_hw_params));
2466
2467         priv->_3945.shared_virt =
2468                 dma_alloc_coherent(&priv->pci_dev->dev,
2469                                    sizeof(struct iwl3945_shared),
2470                                    &priv->_3945.shared_phys, GFP_KERNEL);
2471         if (!priv->_3945.shared_virt) {
2472                 IWL_ERR(priv, "failed to allocate pci memory\n");
2473                 mutex_unlock(&priv->mutex);
2474                 return -ENOMEM;
2475         }
2476
2477         /* Assign number of Usable TX queues */
2478         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2479
2480         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2481         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2482         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2483         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2484         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2485         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2486
2487         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2488         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2489
2490         return 0;
2491 }
2492
2493 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2494                           struct iwl3945_frame *frame, u8 rate)
2495 {
2496         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2497         unsigned int frame_size;
2498
2499         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2500         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2501
2502         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2503         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2504
2505         frame_size = iwl3945_fill_beacon_frame(priv,
2506                                 tx_beacon_cmd->frame,
2507                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2508
2509         BUG_ON(frame_size > MAX_MPDU_SIZE);
2510         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2511
2512         tx_beacon_cmd->tx.rate = rate;
2513         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2514                                       TX_CMD_FLG_TSF_MSK);
2515
2516         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2517         tx_beacon_cmd->tx.supp_rates[0] =
2518                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2519
2520         tx_beacon_cmd->tx.supp_rates[1] =
2521                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2522
2523         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2524 }
2525
2526 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2527 {
2528         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2529         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2530 }
2531
2532 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2533 {
2534         INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2535                           iwl3945_bg_reg_txpower_periodic);
2536 }
2537
2538 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2539 {
2540         cancel_delayed_work(&priv->_3945.thermal_periodic);
2541 }
2542
2543 /* check contents of special bootstrap uCode SRAM */
2544 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2545  {
2546         __le32 *image = priv->ucode_boot.v_addr;
2547         u32 len = priv->ucode_boot.len;
2548         u32 reg;
2549         u32 val;
2550
2551         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2552
2553         /* verify BSM SRAM contents */
2554         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2555         for (reg = BSM_SRAM_LOWER_BOUND;
2556              reg < BSM_SRAM_LOWER_BOUND + len;
2557              reg += sizeof(u32), image++) {
2558                 val = iwl_read_prph(priv, reg);
2559                 if (val != le32_to_cpu(*image)) {
2560                         IWL_ERR(priv, "BSM uCode verification failed at "
2561                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2562                                   BSM_SRAM_LOWER_BOUND,
2563                                   reg - BSM_SRAM_LOWER_BOUND, len,
2564                                   val, le32_to_cpu(*image));
2565                         return -EIO;
2566                 }
2567         }
2568
2569         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2570
2571         return 0;
2572 }
2573
2574
2575 /******************************************************************************
2576  *
2577  * EEPROM related functions
2578  *
2579  ******************************************************************************/
2580
2581 /*
2582  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2583  * embedded controller) as EEPROM reader; each read is a series of pulses
2584  * to/from the EEPROM chip, not a single event, so even reads could conflict
2585  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2586  * simply claims ownership, which should be safe when this function is called
2587  * (i.e. before loading uCode!).
2588  */
2589 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2590 {
2591         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2592         return 0;
2593 }
2594
2595
2596 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2597 {
2598         return;
2599 }
2600
2601  /**
2602   * iwl3945_load_bsm - Load bootstrap instructions
2603   *
2604   * BSM operation:
2605   *
2606   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2607   * in special SRAM that does not power down during RFKILL.  When powering back
2608   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2609   * the bootstrap program into the on-board processor, and starts it.
2610   *
2611   * The bootstrap program loads (via DMA) instructions and data for a new
2612   * program from host DRAM locations indicated by the host driver in the
2613   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2614   * automatically.
2615   *
2616   * When initializing the NIC, the host driver points the BSM to the
2617   * "initialize" uCode image.  This uCode sets up some internal data, then
2618   * notifies host via "initialize alive" that it is complete.
2619   *
2620   * The host then replaces the BSM_DRAM_* pointer values to point to the
2621   * normal runtime uCode instructions and a backup uCode data cache buffer
2622   * (filled initially with starting data values for the on-board processor),
2623   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2624   * which begins normal operation.
2625   *
2626   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2627   * the backup data cache in DRAM before SRAM is powered down.
2628   *
2629   * When powering back up, the BSM loads the bootstrap program.  This reloads
2630   * the runtime uCode instructions and the backup data cache into SRAM,
2631   * and re-launches the runtime uCode from where it left off.
2632   */
2633 static int iwl3945_load_bsm(struct iwl_priv *priv)
2634 {
2635         __le32 *image = priv->ucode_boot.v_addr;
2636         u32 len = priv->ucode_boot.len;
2637         dma_addr_t pinst;
2638         dma_addr_t pdata;
2639         u32 inst_len;
2640         u32 data_len;
2641         int rc;
2642         int i;
2643         u32 done;
2644         u32 reg_offset;
2645
2646         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2647
2648         /* make sure bootstrap program is no larger than BSM's SRAM size */
2649         if (len > IWL39_MAX_BSM_SIZE)
2650                 return -EINVAL;
2651
2652         /* Tell bootstrap uCode where to find the "Initialize" uCode
2653         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2654         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2655         *        after the "initialize" uCode has run, to point to
2656         *        runtime/protocol instructions and backup data cache. */
2657         pinst = priv->ucode_init.p_addr;
2658         pdata = priv->ucode_init_data.p_addr;
2659         inst_len = priv->ucode_init.len;
2660         data_len = priv->ucode_init_data.len;
2661
2662         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2663         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2664         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2665         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2666
2667         /* Fill BSM memory with bootstrap instructions */
2668         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2669              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2670              reg_offset += sizeof(u32), image++)
2671                 _iwl_write_prph(priv, reg_offset,
2672                                           le32_to_cpu(*image));
2673
2674         rc = iwl3945_verify_bsm(priv);
2675         if (rc)
2676                 return rc;
2677
2678         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2679         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2680         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2681                                  IWL39_RTC_INST_LOWER_BOUND);
2682         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2683
2684         /* Load bootstrap code into instruction SRAM now,
2685          *   to prepare to load "initialize" uCode */
2686         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2687                 BSM_WR_CTRL_REG_BIT_START);
2688
2689         /* Wait for load of bootstrap uCode to finish */
2690         for (i = 0; i < 100; i++) {
2691                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2692                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2693                         break;
2694                 udelay(10);
2695         }
2696         if (i < 100)
2697                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2698         else {
2699                 IWL_ERR(priv, "BSM write did not complete!\n");
2700                 return -EIO;
2701         }
2702
2703         /* Enable future boot loads whenever power management unit triggers it
2704          *   (e.g. when powering back up after power-save shutdown) */
2705         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2706                 BSM_WR_CTRL_REG_BIT_START_EN);
2707
2708         return 0;
2709 }
2710
2711 #define IWL3945_UCODE_GET(item)                                         \
2712 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2713                                     u32 api_ver)                        \
2714 {                                                                       \
2715         return le32_to_cpu(ucode->u.v1.item);                           \
2716 }
2717
2718 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2719 {
2720         return UCODE_HEADER_SIZE(1);
2721 }
2722 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2723                                    u32 api_ver)
2724 {
2725         return 0;
2726 }
2727 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2728                                   u32 api_ver)
2729 {
2730         return (u8 *) ucode->u.v1.data;
2731 }
2732
2733 IWL3945_UCODE_GET(inst_size);
2734 IWL3945_UCODE_GET(data_size);
2735 IWL3945_UCODE_GET(init_size);
2736 IWL3945_UCODE_GET(init_data_size);
2737 IWL3945_UCODE_GET(boot_size);
2738
2739 static struct iwl_hcmd_ops iwl3945_hcmd = {
2740         .rxon_assoc = iwl3945_send_rxon_assoc,
2741         .commit_rxon = iwl3945_commit_rxon,
2742 };
2743
2744 static struct iwl_ucode_ops iwl3945_ucode = {
2745         .get_header_size = iwl3945_ucode_get_header_size,
2746         .get_build = iwl3945_ucode_get_build,
2747         .get_inst_size = iwl3945_ucode_get_inst_size,
2748         .get_data_size = iwl3945_ucode_get_data_size,
2749         .get_init_size = iwl3945_ucode_get_init_size,
2750         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2751         .get_boot_size = iwl3945_ucode_get_boot_size,
2752         .get_data = iwl3945_ucode_get_data,
2753 };
2754
2755 static struct iwl_lib_ops iwl3945_lib = {
2756         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2757         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2758         .txq_init = iwl3945_hw_tx_queue_init,
2759         .load_ucode = iwl3945_load_bsm,
2760         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2761         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2762         .apm_ops = {
2763                 .init = iwl3945_apm_init,
2764                 .stop = iwl_apm_stop,
2765                 .config = iwl3945_nic_config,
2766                 .set_pwr_src = iwl3945_set_pwr_src,
2767         },
2768         .eeprom_ops = {
2769                 .regulatory_bands = {
2770                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2771                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2772                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2773                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2774                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2775                         EEPROM_REGULATORY_BAND_NO_HT40,
2776                         EEPROM_REGULATORY_BAND_NO_HT40,
2777                 },
2778                 .verify_signature  = iwlcore_eeprom_verify_signature,
2779                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2780                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2781                 .query_addr = iwlcore_eeprom_query_addr,
2782         },
2783         .send_tx_power  = iwl3945_send_tx_power,
2784         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2785         .post_associate = iwl3945_post_associate,
2786         .isr = iwl_isr_legacy,
2787         .config_ap = iwl3945_config_ap,
2788         .add_bcast_station = iwl3945_add_bcast_station,
2789 };
2790
2791 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2792         .get_hcmd_size = iwl3945_get_hcmd_size,
2793         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2794         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2795 };
2796
2797 static const struct iwl_ops iwl3945_ops = {
2798         .ucode = &iwl3945_ucode,
2799         .lib = &iwl3945_lib,
2800         .hcmd = &iwl3945_hcmd,
2801         .utils = &iwl3945_hcmd_utils,
2802         .led = &iwl3945_led_ops,
2803 };
2804
2805 static struct iwl_cfg iwl3945_bg_cfg = {
2806         .name = "3945BG",
2807         .fw_name_pre = IWL3945_FW_PRE,
2808         .ucode_api_max = IWL3945_UCODE_API_MAX,
2809         .ucode_api_min = IWL3945_UCODE_API_MIN,
2810         .sku = IWL_SKU_G,
2811         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2812         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2813         .ops = &iwl3945_ops,
2814         .num_of_queues = IWL39_NUM_QUEUES,
2815         .mod_params = &iwl3945_mod_params,
2816         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2817         .set_l0s = false,
2818         .use_bsm = true,
2819         .use_isr_legacy = true,
2820         .ht_greenfield_support = false,
2821         .led_compensation = 64,
2822         .broken_powersave = true,
2823         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2824         .monitor_recover_period = IWL_MONITORING_PERIOD,
2825 };
2826
2827 static struct iwl_cfg iwl3945_abg_cfg = {
2828         .name = "3945ABG",
2829         .fw_name_pre = IWL3945_FW_PRE,
2830         .ucode_api_max = IWL3945_UCODE_API_MAX,
2831         .ucode_api_min = IWL3945_UCODE_API_MIN,
2832         .sku = IWL_SKU_A|IWL_SKU_G,
2833         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2834         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2835         .ops = &iwl3945_ops,
2836         .num_of_queues = IWL39_NUM_QUEUES,
2837         .mod_params = &iwl3945_mod_params,
2838         .use_isr_legacy = true,
2839         .ht_greenfield_support = false,
2840         .led_compensation = 64,
2841         .broken_powersave = true,
2842         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2843         .monitor_recover_period = IWL_MONITORING_PERIOD,
2844 };
2845
2846 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2847         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2848         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2849         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2850         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2851         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2852         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2853         {0}
2854 };
2855
2856 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);