2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53 #include <linux/slab.h>
55 #include <net/ieee80211_radiotap.h>
57 #include <asm/unaligned.h>
63 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
64 static int modparam_nohwcrypt;
65 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
66 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
68 static int modparam_all_channels;
69 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
70 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
87 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
108 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
111 static const struct ath5k_srev_name srev_names[] = {
112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150 static const struct ieee80211_rate ath5k_rates[] = {
152 .hw_value = ATH5K_RATE_CODE_1M, },
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
166 .hw_value = ATH5K_RATE_CODE_6M,
169 .hw_value = ATH5K_RATE_CODE_9M,
172 .hw_value = ATH5K_RATE_CODE_12M,
175 .hw_value = ATH5K_RATE_CODE_18M,
178 .hw_value = ATH5K_RATE_CODE_24M,
181 .hw_value = ATH5K_RATE_CODE_36M,
184 .hw_value = ATH5K_RATE_CODE_48M,
187 .hw_value = ATH5K_RATE_CODE_54M,
193 * Prototypes - PCI stack related functions
195 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
196 const struct pci_device_id *id);
197 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
199 static int ath5k_pci_suspend(struct device *dev);
200 static int ath5k_pci_resume(struct device *dev);
202 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
203 #define ATH5K_PM_OPS (&ath5k_pm_ops)
205 #define ATH5K_PM_OPS NULL
206 #endif /* CONFIG_PM */
208 static struct pci_driver ath5k_pci_driver = {
209 .name = KBUILD_MODNAME,
210 .id_table = ath5k_pci_id_table,
211 .probe = ath5k_pci_probe,
212 .remove = __devexit_p(ath5k_pci_remove),
213 .driver.pm = ATH5K_PM_OPS,
219 * Prototypes - MAC 802.11 stack related functions
221 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
222 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
223 struct ath5k_txq *txq);
224 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
225 static int ath5k_reset_wake(struct ath5k_softc *sc);
226 static int ath5k_start(struct ieee80211_hw *hw);
227 static void ath5k_stop(struct ieee80211_hw *hw);
228 static int ath5k_add_interface(struct ieee80211_hw *hw,
229 struct ieee80211_vif *vif);
230 static void ath5k_remove_interface(struct ieee80211_hw *hw,
231 struct ieee80211_vif *vif);
232 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
233 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
234 struct netdev_hw_addr_list *mc_list);
235 static void ath5k_configure_filter(struct ieee80211_hw *hw,
236 unsigned int changed_flags,
237 unsigned int *new_flags,
239 static int ath5k_set_key(struct ieee80211_hw *hw,
240 enum set_key_cmd cmd,
241 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
242 struct ieee80211_key_conf *key);
243 static int ath5k_get_stats(struct ieee80211_hw *hw,
244 struct ieee80211_low_level_stats *stats);
245 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
246 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
247 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
248 static int ath5k_beacon_update(struct ieee80211_hw *hw,
249 struct ieee80211_vif *vif);
250 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
251 struct ieee80211_vif *vif,
252 struct ieee80211_bss_conf *bss_conf,
254 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
255 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
256 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
259 static const struct ieee80211_ops ath5k_hw_ops = {
261 .start = ath5k_start,
263 .add_interface = ath5k_add_interface,
264 .remove_interface = ath5k_remove_interface,
265 .config = ath5k_config,
266 .prepare_multicast = ath5k_prepare_multicast,
267 .configure_filter = ath5k_configure_filter,
268 .set_key = ath5k_set_key,
269 .get_stats = ath5k_get_stats,
271 .get_tsf = ath5k_get_tsf,
272 .set_tsf = ath5k_set_tsf,
273 .reset_tsf = ath5k_reset_tsf,
274 .bss_info_changed = ath5k_bss_info_changed,
275 .sw_scan_start = ath5k_sw_scan_start,
276 .sw_scan_complete = ath5k_sw_scan_complete,
277 .set_coverage_class = ath5k_set_coverage_class,
281 * Prototypes - Internal functions
284 static int ath5k_attach(struct pci_dev *pdev,
285 struct ieee80211_hw *hw);
286 static void ath5k_detach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288 /* Channel/mode setup */
289 static inline short ath5k_ieee2mhz(short chan);
290 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
291 struct ieee80211_channel *channels,
294 static int ath5k_setup_bands(struct ieee80211_hw *hw);
295 static int ath5k_chan_set(struct ath5k_softc *sc,
296 struct ieee80211_channel *chan);
297 static void ath5k_setcurmode(struct ath5k_softc *sc,
299 static void ath5k_mode_setup(struct ath5k_softc *sc);
301 /* Descriptor setup */
302 static int ath5k_desc_alloc(struct ath5k_softc *sc,
303 struct pci_dev *pdev);
304 static void ath5k_desc_free(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
307 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
308 struct ath5k_buf *bf);
309 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
310 struct ath5k_buf *bf,
311 struct ath5k_txq *txq, int padsize);
312 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
313 struct ath5k_buf *bf)
318 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
320 dev_kfree_skb_any(bf->skb);
324 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
325 struct ath5k_buf *bf)
327 struct ath5k_hw *ah = sc->ah;
328 struct ath_common *common = ath5k_hw_common(ah);
333 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
335 dev_kfree_skb_any(bf->skb);
341 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
342 int qtype, int subtype);
343 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
344 static int ath5k_beaconq_config(struct ath5k_softc *sc);
345 static void ath5k_txq_drainq(struct ath5k_softc *sc,
346 struct ath5k_txq *txq);
347 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
348 static void ath5k_txq_release(struct ath5k_softc *sc);
350 static int ath5k_rx_start(struct ath5k_softc *sc);
351 static void ath5k_rx_stop(struct ath5k_softc *sc);
352 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
353 struct ath5k_desc *ds,
355 struct ath5k_rx_status *rs);
356 static void ath5k_tasklet_rx(unsigned long data);
358 static void ath5k_tx_processq(struct ath5k_softc *sc,
359 struct ath5k_txq *txq);
360 static void ath5k_tasklet_tx(unsigned long data);
361 /* Beacon handling */
362 static int ath5k_beacon_setup(struct ath5k_softc *sc,
363 struct ath5k_buf *bf);
364 static void ath5k_beacon_send(struct ath5k_softc *sc);
365 static void ath5k_beacon_config(struct ath5k_softc *sc);
366 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
367 static void ath5k_tasklet_beacon(unsigned long data);
369 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
371 u64 tsf = ath5k_hw_get_tsf64(ah);
373 if ((tsf & 0x7fff) < rstamp)
376 return (tsf & ~0x7fff) | rstamp;
379 /* Interrupt handling */
380 static int ath5k_init(struct ath5k_softc *sc);
381 static int ath5k_stop_locked(struct ath5k_softc *sc);
382 static int ath5k_stop_hw(struct ath5k_softc *sc);
383 static irqreturn_t ath5k_intr(int irq, void *dev_id);
384 static void ath5k_tasklet_reset(unsigned long data);
386 static void ath5k_tasklet_calibrate(unsigned long data);
389 * Module init/exit functions
398 ret = pci_register_driver(&ath5k_pci_driver);
400 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
410 pci_unregister_driver(&ath5k_pci_driver);
412 ath5k_debug_finish();
415 module_init(init_ath5k_pci);
416 module_exit(exit_ath5k_pci);
419 /********************\
420 * PCI Initialization *
421 \********************/
424 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
426 const char *name = "xxxxx";
429 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
430 if (srev_names[i].sr_type != type)
433 if ((val & 0xf0) == srev_names[i].sr_val)
434 name = srev_names[i].sr_name;
436 if ((val & 0xff) == srev_names[i].sr_val) {
437 name = srev_names[i].sr_name;
444 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
446 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
447 return ath5k_hw_reg_read(ah, reg_offset);
450 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
452 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
453 ath5k_hw_reg_write(ah, val, reg_offset);
456 static const struct ath_ops ath5k_common_ops = {
457 .read = ath5k_ioread32,
458 .write = ath5k_iowrite32,
462 ath5k_pci_probe(struct pci_dev *pdev,
463 const struct pci_device_id *id)
466 struct ath5k_softc *sc;
467 struct ath_common *common;
468 struct ieee80211_hw *hw;
472 ret = pci_enable_device(pdev);
474 dev_err(&pdev->dev, "can't enable device\n");
478 /* XXX 32-bit addressing only */
479 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
481 dev_err(&pdev->dev, "32-bit DMA not available\n");
486 * Cache line size is used to size and align various
487 * structures used to communicate with the hardware.
489 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
492 * Linux 2.4.18 (at least) writes the cache line size
493 * register as a 16-bit wide register which is wrong.
494 * We must have this setup properly for rx buffer
495 * DMA to work so force a reasonable value here if it
498 csz = L1_CACHE_BYTES >> 2;
499 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
502 * The default setting of latency timer yields poor results,
503 * set it to the value used by other systems. It may be worth
504 * tweaking this setting more.
506 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
508 /* Enable bus mastering */
509 pci_set_master(pdev);
512 * Disable the RETRY_TIMEOUT register (0x41) to keep
513 * PCI Tx retries from interfering with C3 CPU state.
515 pci_write_config_byte(pdev, 0x41, 0);
517 ret = pci_request_region(pdev, 0, "ath5k");
519 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
523 mem = pci_iomap(pdev, 0, 0);
525 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
531 * Allocate hw (mac80211 main struct)
532 * and hw->priv (driver private data)
534 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
536 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
541 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
543 /* Initialize driver private data */
544 SET_IEEE80211_DEV(hw, &pdev->dev);
545 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
546 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
547 IEEE80211_HW_SIGNAL_DBM |
548 IEEE80211_HW_NOISE_DBM;
550 hw->wiphy->interface_modes =
551 BIT(NL80211_IFTYPE_AP) |
552 BIT(NL80211_IFTYPE_STATION) |
553 BIT(NL80211_IFTYPE_ADHOC) |
554 BIT(NL80211_IFTYPE_MESH_POINT);
556 hw->extra_tx_headroom = 2;
557 hw->channel_change_time = 5000;
562 ath5k_debug_init_device(sc);
565 * Mark the device as detached to avoid processing
566 * interrupts until setup is complete.
568 __set_bit(ATH_STAT_INVALID, sc->status);
570 sc->iobase = mem; /* So we can unmap it on detach */
571 sc->opmode = NL80211_IFTYPE_STATION;
573 mutex_init(&sc->lock);
574 spin_lock_init(&sc->rxbuflock);
575 spin_lock_init(&sc->txbuflock);
576 spin_lock_init(&sc->block);
578 /* Set private data */
579 pci_set_drvdata(pdev, hw);
581 /* Setup interrupt handler */
582 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
584 ATH5K_ERR(sc, "request_irq failed\n");
588 /*If we passed the test malloc a ath5k_hw struct*/
589 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
592 ATH5K_ERR(sc, "out of memory\n");
597 sc->ah->ah_iobase = sc->iobase;
598 common = ath5k_hw_common(sc->ah);
599 common->ops = &ath5k_common_ops;
602 common->cachelsz = csz << 2; /* convert to bytes */
604 /* Initialize device */
605 ret = ath5k_hw_attach(sc);
610 /* set up multi-rate retry capabilities */
611 if (sc->ah->ah_version == AR5K_AR5212) {
613 hw->max_rate_tries = 11;
616 /* Finish private driver data initialization */
617 ret = ath5k_attach(pdev, hw);
621 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
622 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
624 sc->ah->ah_phy_revision);
626 if (!sc->ah->ah_single_chip) {
627 /* Single chip radio (!RF5111) */
628 if (sc->ah->ah_radio_5ghz_revision &&
629 !sc->ah->ah_radio_2ghz_revision) {
630 /* No 5GHz support -> report 2GHz radio */
631 if (!test_bit(AR5K_MODE_11A,
632 sc->ah->ah_capabilities.cap_mode)) {
633 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
634 ath5k_chip_name(AR5K_VERSION_RAD,
635 sc->ah->ah_radio_5ghz_revision),
636 sc->ah->ah_radio_5ghz_revision);
637 /* No 2GHz support (5110 and some
638 * 5Ghz only cards) -> report 5Ghz radio */
639 } else if (!test_bit(AR5K_MODE_11B,
640 sc->ah->ah_capabilities.cap_mode)) {
641 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
642 ath5k_chip_name(AR5K_VERSION_RAD,
643 sc->ah->ah_radio_5ghz_revision),
644 sc->ah->ah_radio_5ghz_revision);
645 /* Multiband radio */
647 ATH5K_INFO(sc, "RF%s multiband radio found"
649 ath5k_chip_name(AR5K_VERSION_RAD,
650 sc->ah->ah_radio_5ghz_revision),
651 sc->ah->ah_radio_5ghz_revision);
654 /* Multi chip radio (RF5111 - RF2111) ->
655 * report both 2GHz/5GHz radios */
656 else if (sc->ah->ah_radio_5ghz_revision &&
657 sc->ah->ah_radio_2ghz_revision){
658 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
659 ath5k_chip_name(AR5K_VERSION_RAD,
660 sc->ah->ah_radio_5ghz_revision),
661 sc->ah->ah_radio_5ghz_revision);
662 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
663 ath5k_chip_name(AR5K_VERSION_RAD,
664 sc->ah->ah_radio_2ghz_revision),
665 sc->ah->ah_radio_2ghz_revision);
670 /* ready to process interrupts */
671 __clear_bit(ATH_STAT_INVALID, sc->status);
675 ath5k_hw_detach(sc->ah);
677 free_irq(pdev->irq, sc);
681 ieee80211_free_hw(hw);
683 pci_iounmap(pdev, mem);
685 pci_release_region(pdev, 0);
687 pci_disable_device(pdev);
692 static void __devexit
693 ath5k_pci_remove(struct pci_dev *pdev)
695 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
696 struct ath5k_softc *sc = hw->priv;
698 ath5k_debug_finish_device(sc);
699 ath5k_detach(pdev, hw);
700 ath5k_hw_detach(sc->ah);
702 free_irq(pdev->irq, sc);
703 pci_iounmap(pdev, sc->iobase);
704 pci_release_region(pdev, 0);
705 pci_disable_device(pdev);
706 ieee80211_free_hw(hw);
710 static int ath5k_pci_suspend(struct device *dev)
712 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
713 struct ath5k_softc *sc = hw->priv;
719 static int ath5k_pci_resume(struct device *dev)
721 struct pci_dev *pdev = to_pci_dev(dev);
722 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
723 struct ath5k_softc *sc = hw->priv;
726 * Suspend/Resume resets the PCI configuration space, so we have to
727 * re-disable the RETRY_TIMEOUT register (0x41) to keep
728 * PCI Tx retries from interfering with C3 CPU state
730 pci_write_config_byte(pdev, 0x41, 0);
732 ath5k_led_enable(sc);
735 #endif /* CONFIG_PM */
738 /***********************\
739 * Driver Initialization *
740 \***********************/
742 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
744 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
745 struct ath5k_softc *sc = hw->priv;
746 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
748 return ath_reg_notifier_apply(wiphy, request, regulatory);
752 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
754 struct ath5k_softc *sc = hw->priv;
755 struct ath5k_hw *ah = sc->ah;
756 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
757 u8 mac[ETH_ALEN] = {};
760 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
763 * Check if the MAC has multi-rate retry support.
764 * We do this by trying to setup a fake extended
765 * descriptor. MAC's that don't have support will
766 * return false w/o doing anything. MAC's that do
767 * support it will return true w/o doing anything.
769 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
773 __set_bit(ATH_STAT_MRRETRY, sc->status);
776 * Collect the channel list. The 802.11 layer
777 * is resposible for filtering this list based
778 * on settings like the phy mode and regulatory
779 * domain restrictions.
781 ret = ath5k_setup_bands(hw);
783 ATH5K_ERR(sc, "can't get channels\n");
787 /* NB: setup here so ath5k_rate_update is happy */
788 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
789 ath5k_setcurmode(sc, AR5K_MODE_11A);
791 ath5k_setcurmode(sc, AR5K_MODE_11B);
794 * Allocate tx+rx descriptors and populate the lists.
796 ret = ath5k_desc_alloc(sc, pdev);
798 ATH5K_ERR(sc, "can't allocate descriptors\n");
803 * Allocate hardware transmit queues: one queue for
804 * beacon frames and one data queue for each QoS
805 * priority. Note that hw functions handle reseting
806 * these queues at the needed time.
808 ret = ath5k_beaconq_setup(ah);
810 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
814 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
815 if (IS_ERR(sc->cabq)) {
816 ATH5K_ERR(sc, "can't setup cab queue\n");
817 ret = PTR_ERR(sc->cabq);
821 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
822 if (IS_ERR(sc->txq)) {
823 ATH5K_ERR(sc, "can't setup xmit queue\n");
824 ret = PTR_ERR(sc->txq);
828 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
829 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
830 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
831 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
832 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
834 ret = ath5k_eeprom_read_mac(ah, mac);
836 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
841 SET_IEEE80211_PERM_ADDR(hw, mac);
842 /* All MAC address bits matter for ACKs */
843 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
844 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
846 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
847 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
849 ATH5K_ERR(sc, "can't initialize regulatory system\n");
853 ret = ieee80211_register_hw(hw);
855 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
859 if (!ath_is_world_regd(regulatory))
860 regulatory_hint(hw->wiphy, regulatory->alpha2);
866 ath5k_txq_release(sc);
868 ath5k_hw_release_tx_queue(ah, sc->bhalq);
870 ath5k_desc_free(sc, pdev);
876 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
878 struct ath5k_softc *sc = hw->priv;
881 * NB: the order of these is important:
882 * o call the 802.11 layer before detaching ath5k_hw to
883 * insure callbacks into the driver to delete global
884 * key cache entries can be handled
885 * o reclaim the tx queue data structures after calling
886 * the 802.11 layer as we'll get called back to reclaim
887 * node state and potentially want to use them
888 * o to cleanup the tx queues the hal is called, so detach
890 * XXX: ??? detach ath5k_hw ???
891 * Other than that, it's straightforward...
893 ieee80211_unregister_hw(hw);
894 ath5k_desc_free(sc, pdev);
895 ath5k_txq_release(sc);
896 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
897 ath5k_unregister_leds(sc);
900 * NB: can't reclaim these until after ieee80211_ifdetach
901 * returns because we'll get called back to reclaim node
902 * state and potentially want to use them.
909 /********************\
910 * Channel/mode setup *
911 \********************/
914 * Convert IEEE channel number to MHz frequency.
917 ath5k_ieee2mhz(short chan)
919 if (chan <= 14 || chan >= 27)
920 return ieee80211chan2mhz(chan);
922 return 2212 + chan * 20;
926 * Returns true for the channel numbers used without all_channels modparam.
928 static bool ath5k_is_standard_channel(short chan)
930 return ((chan <= 14) ||
932 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
934 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
936 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
940 ath5k_copy_channels(struct ath5k_hw *ah,
941 struct ieee80211_channel *channels,
945 unsigned int i, count, size, chfreq, freq, ch;
947 if (!test_bit(mode, ah->ah_modes))
952 case AR5K_MODE_11A_TURBO:
953 /* 1..220, but 2GHz frequencies are filtered by check_channel */
955 chfreq = CHANNEL_5GHZ;
959 case AR5K_MODE_11G_TURBO:
961 chfreq = CHANNEL_2GHZ;
964 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
968 for (i = 0, count = 0; i < size && max > 0; i++) {
970 freq = ath5k_ieee2mhz(ch);
972 /* Check if channel is supported by the chipset */
973 if (!ath5k_channel_ok(ah, freq, chfreq))
976 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
979 /* Write channel info and increment counter */
980 channels[count].center_freq = freq;
981 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
982 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
986 channels[count].hw_value = chfreq | CHANNEL_OFDM;
988 case AR5K_MODE_11A_TURBO:
989 case AR5K_MODE_11G_TURBO:
990 channels[count].hw_value = chfreq |
991 CHANNEL_OFDM | CHANNEL_TURBO;
994 channels[count].hw_value = CHANNEL_B;
1005 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1009 for (i = 0; i < AR5K_MAX_RATES; i++)
1010 sc->rate_idx[b->band][i] = -1;
1012 for (i = 0; i < b->n_bitrates; i++) {
1013 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1014 if (b->bitrates[i].hw_value_short)
1015 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1020 ath5k_setup_bands(struct ieee80211_hw *hw)
1022 struct ath5k_softc *sc = hw->priv;
1023 struct ath5k_hw *ah = sc->ah;
1024 struct ieee80211_supported_band *sband;
1025 int max_c, count_c = 0;
1028 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1029 max_c = ARRAY_SIZE(sc->channels);
1032 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1033 sband->band = IEEE80211_BAND_2GHZ;
1034 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1036 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1038 memcpy(sband->bitrates, &ath5k_rates[0],
1039 sizeof(struct ieee80211_rate) * 12);
1040 sband->n_bitrates = 12;
1042 sband->channels = sc->channels;
1043 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1044 AR5K_MODE_11G, max_c);
1046 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1047 count_c = sband->n_channels;
1049 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1051 memcpy(sband->bitrates, &ath5k_rates[0],
1052 sizeof(struct ieee80211_rate) * 4);
1053 sband->n_bitrates = 4;
1055 /* 5211 only supports B rates and uses 4bit rate codes
1056 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1059 if (ah->ah_version == AR5K_AR5211) {
1060 for (i = 0; i < 4; i++) {
1061 sband->bitrates[i].hw_value =
1062 sband->bitrates[i].hw_value & 0xF;
1063 sband->bitrates[i].hw_value_short =
1064 sband->bitrates[i].hw_value_short & 0xF;
1068 sband->channels = sc->channels;
1069 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1070 AR5K_MODE_11B, max_c);
1072 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1073 count_c = sband->n_channels;
1076 ath5k_setup_rate_idx(sc, sband);
1078 /* 5GHz band, A mode */
1079 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1080 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1081 sband->band = IEEE80211_BAND_5GHZ;
1082 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1084 memcpy(sband->bitrates, &ath5k_rates[4],
1085 sizeof(struct ieee80211_rate) * 8);
1086 sband->n_bitrates = 8;
1088 sband->channels = &sc->channels[count_c];
1089 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1090 AR5K_MODE_11A, max_c);
1092 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1094 ath5k_setup_rate_idx(sc, sband);
1096 ath5k_debug_dump_bands(sc);
1102 * Set/change channels. We always reset the chip.
1103 * To accomplish this we must first cleanup any pending DMA,
1104 * then restart stuff after a la ath5k_init.
1106 * Called with sc->lock.
1109 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1111 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1112 sc->curchan->center_freq, chan->center_freq);
1115 * To switch channels clear any pending DMA operations;
1116 * wait long enough for the RX fifo to drain, reset the
1117 * hardware at the new frequency, and then re-enable
1118 * the relevant bits of the h/w.
1120 return ath5k_reset(sc, chan);
1124 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1128 if (mode == AR5K_MODE_11A) {
1129 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1131 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1136 ath5k_mode_setup(struct ath5k_softc *sc)
1138 struct ath5k_hw *ah = sc->ah;
1141 /* configure rx filter */
1142 rfilt = sc->filter_flags;
1143 ath5k_hw_set_rx_filter(ah, rfilt);
1145 if (ath5k_hw_hasbssidmask(ah))
1146 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1148 /* configure operational mode */
1149 ath5k_hw_set_opmode(ah, sc->opmode);
1151 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
1152 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1156 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1160 /* return base rate on errors */
1161 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1162 "hw_rix out of bounds: %x\n", hw_rix))
1165 rix = sc->rate_idx[sc->curband->band][hw_rix];
1166 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1177 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1179 struct ath_common *common = ath5k_hw_common(sc->ah);
1180 struct sk_buff *skb;
1183 * Allocate buffer with headroom_needed space for the
1184 * fake physical layer header at the start.
1186 skb = ath_rxbuf_alloc(common,
1191 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1192 common->rx_bufsize);
1196 *skb_addr = pci_map_single(sc->pdev,
1197 skb->data, common->rx_bufsize,
1198 PCI_DMA_FROMDEVICE);
1199 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1200 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1208 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1210 struct ath5k_hw *ah = sc->ah;
1211 struct sk_buff *skb = bf->skb;
1212 struct ath5k_desc *ds;
1215 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1222 * Setup descriptors. For receive we always terminate
1223 * the descriptor list with a self-linked entry so we'll
1224 * not get overrun under high load (as can happen with a
1225 * 5212 when ANI processing enables PHY error frames).
1227 * To insure the last descriptor is self-linked we create
1228 * each descriptor as self-linked and add it to the end. As
1229 * each additional descriptor is added the previous self-linked
1230 * entry is ``fixed'' naturally. This should be safe even
1231 * if DMA is happening. When processing RX interrupts we
1232 * never remove/process the last, self-linked, entry on the
1233 * descriptor list. This insures the hardware always has
1234 * someplace to write a new frame.
1237 ds->ds_link = bf->daddr; /* link to self */
1238 ds->ds_data = bf->skbaddr;
1239 ah->ah_setup_rx_desc(ah, ds,
1240 skb_tailroom(skb), /* buffer size */
1243 if (sc->rxlink != NULL)
1244 *sc->rxlink = bf->daddr;
1245 sc->rxlink = &ds->ds_link;
1249 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1251 struct ieee80211_hdr *hdr;
1252 enum ath5k_pkt_type htype;
1255 hdr = (struct ieee80211_hdr *)skb->data;
1256 fc = hdr->frame_control;
1258 if (ieee80211_is_beacon(fc))
1259 htype = AR5K_PKT_TYPE_BEACON;
1260 else if (ieee80211_is_probe_resp(fc))
1261 htype = AR5K_PKT_TYPE_PROBE_RESP;
1262 else if (ieee80211_is_atim(fc))
1263 htype = AR5K_PKT_TYPE_ATIM;
1264 else if (ieee80211_is_pspoll(fc))
1265 htype = AR5K_PKT_TYPE_PSPOLL;
1267 htype = AR5K_PKT_TYPE_NORMAL;
1273 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1274 struct ath5k_txq *txq, int padsize)
1276 struct ath5k_hw *ah = sc->ah;
1277 struct ath5k_desc *ds = bf->desc;
1278 struct sk_buff *skb = bf->skb;
1279 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1280 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1281 struct ieee80211_rate *rate;
1282 unsigned int mrr_rate[3], mrr_tries[3];
1289 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1291 /* XXX endianness */
1292 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1295 rate = ieee80211_get_tx_rate(sc->hw, info);
1297 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1298 flags |= AR5K_TXDESC_NOACK;
1300 rc_flags = info->control.rates[0].flags;
1301 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1302 rate->hw_value_short : rate->hw_value;
1306 /* FIXME: If we are in g mode and rate is a CCK rate
1307 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1308 * from tx power (value is in dB units already) */
1309 if (info->control.hw_key) {
1310 keyidx = info->control.hw_key->hw_key_idx;
1311 pktlen += info->control.hw_key->icv_len;
1313 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1314 flags |= AR5K_TXDESC_RTSENA;
1315 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1316 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1317 sc->vif, pktlen, info));
1319 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1320 flags |= AR5K_TXDESC_CTSENA;
1321 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1322 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1323 sc->vif, pktlen, info));
1325 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1326 ieee80211_get_hdrlen_from_skb(skb), padsize,
1327 get_hw_packet_type(skb),
1328 (sc->power_level * 2),
1330 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1331 cts_rate, duration);
1335 memset(mrr_rate, 0, sizeof(mrr_rate));
1336 memset(mrr_tries, 0, sizeof(mrr_tries));
1337 for (i = 0; i < 3; i++) {
1338 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1342 mrr_rate[i] = rate->hw_value;
1343 mrr_tries[i] = info->control.rates[i + 1].count;
1346 ah->ah_setup_mrr_tx_desc(ah, ds,
1347 mrr_rate[0], mrr_tries[0],
1348 mrr_rate[1], mrr_tries[1],
1349 mrr_rate[2], mrr_tries[2]);
1352 ds->ds_data = bf->skbaddr;
1354 spin_lock_bh(&txq->lock);
1355 list_add_tail(&bf->list, &txq->q);
1356 if (txq->link == NULL) /* is this first packet? */
1357 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1358 else /* no, so only link it */
1359 *txq->link = bf->daddr;
1361 txq->link = &ds->ds_link;
1362 ath5k_hw_start_tx_dma(ah, txq->qnum);
1364 spin_unlock_bh(&txq->lock);
1368 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1372 /*******************\
1373 * Descriptors setup *
1374 \*******************/
1377 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1379 struct ath5k_desc *ds;
1380 struct ath5k_buf *bf;
1385 /* allocate descriptors */
1386 sc->desc_len = sizeof(struct ath5k_desc) *
1387 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1388 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1389 if (sc->desc == NULL) {
1390 ATH5K_ERR(sc, "can't allocate descriptors\n");
1395 da = sc->desc_daddr;
1396 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1397 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1399 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1400 sizeof(struct ath5k_buf), GFP_KERNEL);
1402 ATH5K_ERR(sc, "can't allocate bufptr\n");
1408 INIT_LIST_HEAD(&sc->rxbuf);
1409 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1412 list_add_tail(&bf->list, &sc->rxbuf);
1415 INIT_LIST_HEAD(&sc->txbuf);
1416 sc->txbuf_len = ATH_TXBUF;
1417 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1418 da += sizeof(*ds)) {
1421 list_add_tail(&bf->list, &sc->txbuf);
1431 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1438 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1440 struct ath5k_buf *bf;
1442 ath5k_txbuf_free(sc, sc->bbuf);
1443 list_for_each_entry(bf, &sc->txbuf, list)
1444 ath5k_txbuf_free(sc, bf);
1445 list_for_each_entry(bf, &sc->rxbuf, list)
1446 ath5k_rxbuf_free(sc, bf);
1448 /* Free memory associated with all descriptors */
1449 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1463 static struct ath5k_txq *
1464 ath5k_txq_setup(struct ath5k_softc *sc,
1465 int qtype, int subtype)
1467 struct ath5k_hw *ah = sc->ah;
1468 struct ath5k_txq *txq;
1469 struct ath5k_txq_info qi = {
1470 .tqi_subtype = subtype,
1471 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1472 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1473 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1478 * Enable interrupts only for EOL and DESC conditions.
1479 * We mark tx descriptors to receive a DESC interrupt
1480 * when a tx queue gets deep; otherwise waiting for the
1481 * EOL to reap descriptors. Note that this is done to
1482 * reduce interrupt load and this only defers reaping
1483 * descriptors, never transmitting frames. Aside from
1484 * reducing interrupts this also permits more concurrency.
1485 * The only potential downside is if the tx queue backs
1486 * up in which case the top half of the kernel may backup
1487 * due to a lack of tx descriptors.
1489 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1490 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1491 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1494 * NB: don't print a message, this happens
1495 * normally on parts with too few tx queues
1497 return ERR_PTR(qnum);
1499 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1500 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1501 qnum, ARRAY_SIZE(sc->txqs));
1502 ath5k_hw_release_tx_queue(ah, qnum);
1503 return ERR_PTR(-EINVAL);
1505 txq = &sc->txqs[qnum];
1509 INIT_LIST_HEAD(&txq->q);
1510 spin_lock_init(&txq->lock);
1513 return &sc->txqs[qnum];
1517 ath5k_beaconq_setup(struct ath5k_hw *ah)
1519 struct ath5k_txq_info qi = {
1520 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1521 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1522 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1523 /* NB: for dynamic turbo, don't enable any other interrupts */
1524 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1527 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1531 ath5k_beaconq_config(struct ath5k_softc *sc)
1533 struct ath5k_hw *ah = sc->ah;
1534 struct ath5k_txq_info qi;
1537 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1541 if (sc->opmode == NL80211_IFTYPE_AP ||
1542 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1544 * Always burst out beacon and CAB traffic
1545 * (aifs = cwmin = cwmax = 0)
1550 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1552 * Adhoc mode; backoff between 0 and (2 * cw_min).
1556 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1559 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1560 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1561 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1563 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1565 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1566 "hardware queue!\n", __func__);
1569 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1573 /* reconfigure cabq with ready time to 80% of beacon_interval */
1574 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1578 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1579 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1583 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1589 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1591 struct ath5k_buf *bf, *bf0;
1594 * NB: this assumes output has been stopped and
1595 * we do not need to block ath5k_tx_tasklet
1597 spin_lock_bh(&txq->lock);
1598 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1599 ath5k_debug_printtxbuf(sc, bf);
1601 ath5k_txbuf_free(sc, bf);
1603 spin_lock_bh(&sc->txbuflock);
1604 list_move_tail(&bf->list, &sc->txbuf);
1606 spin_unlock_bh(&sc->txbuflock);
1609 spin_unlock_bh(&txq->lock);
1613 * Drain the transmit queues and reclaim resources.
1616 ath5k_txq_cleanup(struct ath5k_softc *sc)
1618 struct ath5k_hw *ah = sc->ah;
1621 /* XXX return value */
1622 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1623 /* don't touch the hardware if marked invalid */
1624 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1625 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1626 ath5k_hw_get_txdp(ah, sc->bhalq));
1627 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1628 if (sc->txqs[i].setup) {
1629 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1630 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1633 ath5k_hw_get_txdp(ah,
1638 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1640 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1641 if (sc->txqs[i].setup)
1642 ath5k_txq_drainq(sc, &sc->txqs[i]);
1646 ath5k_txq_release(struct ath5k_softc *sc)
1648 struct ath5k_txq *txq = sc->txqs;
1651 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1653 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1666 * Enable the receive h/w following a reset.
1669 ath5k_rx_start(struct ath5k_softc *sc)
1671 struct ath5k_hw *ah = sc->ah;
1672 struct ath_common *common = ath5k_hw_common(ah);
1673 struct ath5k_buf *bf;
1676 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1678 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1679 common->cachelsz, common->rx_bufsize);
1681 spin_lock_bh(&sc->rxbuflock);
1683 list_for_each_entry(bf, &sc->rxbuf, list) {
1684 ret = ath5k_rxbuf_setup(sc, bf);
1686 spin_unlock_bh(&sc->rxbuflock);
1690 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1691 ath5k_hw_set_rxdp(ah, bf->daddr);
1692 spin_unlock_bh(&sc->rxbuflock);
1694 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1695 ath5k_mode_setup(sc); /* set filters, etc. */
1696 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1704 * Disable the receive h/w in preparation for a reset.
1707 ath5k_rx_stop(struct ath5k_softc *sc)
1709 struct ath5k_hw *ah = sc->ah;
1711 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1712 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1713 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1715 ath5k_debug_printrxbuffs(sc, ah);
1717 sc->rxlink = NULL; /* just in case */
1721 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1722 struct sk_buff *skb, struct ath5k_rx_status *rs)
1724 struct ath5k_hw *ah = sc->ah;
1725 struct ath_common *common = ath5k_hw_common(ah);
1726 struct ieee80211_hdr *hdr = (void *)skb->data;
1727 unsigned int keyix, hlen;
1729 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1730 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1731 return RX_FLAG_DECRYPTED;
1733 /* Apparently when a default key is used to decrypt the packet
1734 the hw does not set the index used to decrypt. In such cases
1735 get the index from the packet. */
1736 hlen = ieee80211_hdrlen(hdr->frame_control);
1737 if (ieee80211_has_protected(hdr->frame_control) &&
1738 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1739 skb->len >= hlen + 4) {
1740 keyix = skb->data[hlen + 3] >> 6;
1742 if (test_bit(keyix, common->keymap))
1743 return RX_FLAG_DECRYPTED;
1751 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1752 struct ieee80211_rx_status *rxs)
1754 struct ath_common *common = ath5k_hw_common(sc->ah);
1757 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1759 if (ieee80211_is_beacon(mgmt->frame_control) &&
1760 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1761 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1763 * Received an IBSS beacon with the same BSSID. Hardware *must*
1764 * have updated the local TSF. We have to work around various
1765 * hardware bugs, though...
1767 tsf = ath5k_hw_get_tsf64(sc->ah);
1768 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1769 hw_tu = TSF_TO_TU(tsf);
1771 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1772 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1773 (unsigned long long)bc_tstamp,
1774 (unsigned long long)rxs->mactime,
1775 (unsigned long long)(rxs->mactime - bc_tstamp),
1776 (unsigned long long)tsf);
1779 * Sometimes the HW will give us a wrong tstamp in the rx
1780 * status, causing the timestamp extension to go wrong.
1781 * (This seems to happen especially with beacon frames bigger
1782 * than 78 byte (incl. FCS))
1783 * But we know that the receive timestamp must be later than the
1784 * timestamp of the beacon since HW must have synced to that.
1786 * NOTE: here we assume mactime to be after the frame was
1787 * received, not like mac80211 which defines it at the start.
1789 if (bc_tstamp > rxs->mactime) {
1790 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1791 "fixing mactime from %llx to %llx\n",
1792 (unsigned long long)rxs->mactime,
1793 (unsigned long long)tsf);
1798 * Local TSF might have moved higher than our beacon timers,
1799 * in that case we have to update them to continue sending
1800 * beacons. This also takes care of synchronizing beacon sending
1801 * times with other stations.
1803 if (hw_tu >= sc->nexttbtt)
1804 ath5k_beacon_update_timers(sc, bc_tstamp);
1809 * Compute padding position. skb must contains an IEEE 802.11 frame
1811 static int ath5k_common_padpos(struct sk_buff *skb)
1813 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1814 __le16 frame_control = hdr->frame_control;
1817 if (ieee80211_has_a4(frame_control)) {
1820 if (ieee80211_is_data_qos(frame_control)) {
1821 padpos += IEEE80211_QOS_CTL_LEN;
1828 * This function expects a 802.11 frame and returns the number of
1829 * bytes added, or -1 if we don't have enought header room.
1832 static int ath5k_add_padding(struct sk_buff *skb)
1834 int padpos = ath5k_common_padpos(skb);
1835 int padsize = padpos & 3;
1837 if (padsize && skb->len>padpos) {
1839 if (skb_headroom(skb) < padsize)
1842 skb_push(skb, padsize);
1843 memmove(skb->data, skb->data+padsize, padpos);
1851 * This function expects a 802.11 frame and returns the number of
1855 static int ath5k_remove_padding(struct sk_buff *skb)
1857 int padpos = ath5k_common_padpos(skb);
1858 int padsize = padpos & 3;
1860 if (padsize && skb->len>=padpos+padsize) {
1861 memmove(skb->data + padsize, skb->data, padpos);
1862 skb_pull(skb, padsize);
1870 ath5k_tasklet_rx(unsigned long data)
1872 struct ieee80211_rx_status *rxs;
1873 struct ath5k_rx_status rs = {};
1874 struct sk_buff *skb, *next_skb;
1875 dma_addr_t next_skb_addr;
1876 struct ath5k_softc *sc = (void *)data;
1877 struct ath5k_hw *ah = sc->ah;
1878 struct ath_common *common = ath5k_hw_common(ah);
1879 struct ath5k_buf *bf;
1880 struct ath5k_desc *ds;
1884 spin_lock(&sc->rxbuflock);
1885 if (list_empty(&sc->rxbuf)) {
1886 ATH5K_WARN(sc, "empty rx buf pool\n");
1892 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1893 BUG_ON(bf->skb == NULL);
1897 /* bail if HW is still using self-linked descriptor */
1898 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1901 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1902 if (unlikely(ret == -EINPROGRESS))
1904 else if (unlikely(ret)) {
1905 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1906 sc->stats.rxerr_proc++;
1907 spin_unlock(&sc->rxbuflock);
1911 sc->stats.rx_all_count++;
1913 if (unlikely(rs.rs_more)) {
1914 ATH5K_WARN(sc, "unsupported jumbo\n");
1915 sc->stats.rxerr_jumbo++;
1919 if (unlikely(rs.rs_status)) {
1920 if (rs.rs_status & AR5K_RXERR_CRC)
1921 sc->stats.rxerr_crc++;
1922 if (rs.rs_status & AR5K_RXERR_FIFO)
1923 sc->stats.rxerr_fifo++;
1924 if (rs.rs_status & AR5K_RXERR_PHY) {
1925 sc->stats.rxerr_phy++;
1928 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1930 * Decrypt error. If the error occurred
1931 * because there was no hardware key, then
1932 * let the frame through so the upper layers
1933 * can process it. This is necessary for 5210
1934 * parts which have no way to setup a ``clear''
1937 * XXX do key cache faulting
1939 sc->stats.rxerr_decrypt++;
1940 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1941 !(rs.rs_status & AR5K_RXERR_CRC))
1944 if (rs.rs_status & AR5K_RXERR_MIC) {
1945 rx_flag |= RX_FLAG_MMIC_ERROR;
1946 sc->stats.rxerr_mic++;
1950 /* let crypto-error packets fall through in MNTR */
1952 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1953 sc->opmode != NL80211_IFTYPE_MONITOR)
1957 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1960 * If we can't replace bf->skb with a new skb under memory
1961 * pressure, just skip this packet
1966 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
1967 PCI_DMA_FROMDEVICE);
1968 skb_put(skb, rs.rs_datalen);
1970 /* The MAC header is padded to have 32-bit boundary if the
1971 * packet payload is non-zero. The general calculation for
1972 * padsize would take into account odd header lengths:
1973 * padsize = (4 - hdrlen % 4) % 4; However, since only
1974 * even-length headers are used, padding can only be 0 or 2
1975 * bytes and we can optimize this a bit. In addition, we must
1976 * not try to remove padding from short control frames that do
1977 * not have payload. */
1978 ath5k_remove_padding(skb);
1980 rxs = IEEE80211_SKB_RXCB(skb);
1983 * always extend the mac timestamp, since this information is
1984 * also needed for proper IBSS merging.
1986 * XXX: it might be too late to do it here, since rs_tstamp is
1987 * 15bit only. that means TSF extension has to be done within
1988 * 32768usec (about 32ms). it might be necessary to move this to
1989 * the interrupt handler, like it is done in madwifi.
1991 * Unfortunately we don't know when the hardware takes the rx
1992 * timestamp (beginning of phy frame, data frame, end of rx?).
1993 * The only thing we know is that it is hardware specific...
1994 * On AR5213 it seems the rx timestamp is at the end of the
1995 * frame, but i'm not sure.
1997 * NOTE: mac80211 defines mactime at the beginning of the first
1998 * data symbol. Since we don't have any time references it's
1999 * impossible to comply to that. This affects IBSS merge only
2000 * right now, so it's not too bad...
2002 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2003 rxs->flag = rx_flag | RX_FLAG_TSFT;
2005 rxs->freq = sc->curchan->center_freq;
2006 rxs->band = sc->curband->band;
2008 rxs->noise = sc->ah->ah_noise_floor;
2009 rxs->signal = rxs->noise + rs.rs_rssi;
2011 rxs->antenna = rs.rs_antenna;
2013 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2014 sc->stats.antenna_rx[rs.rs_antenna]++;
2016 sc->stats.antenna_rx[0]++; /* invalid */
2018 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2019 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
2021 if (rxs->rate_idx >= 0 && rs.rs_rate ==
2022 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2023 rxs->flag |= RX_FLAG_SHORTPRE;
2025 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
2027 /* check beacons in IBSS mode */
2028 if (sc->opmode == NL80211_IFTYPE_ADHOC)
2029 ath5k_check_ibss_tsf(sc, skb, rxs);
2031 ieee80211_rx(sc->hw, skb);
2034 bf->skbaddr = next_skb_addr;
2036 list_move_tail(&bf->list, &sc->rxbuf);
2037 } while (ath5k_rxbuf_setup(sc, bf) == 0);
2039 spin_unlock(&sc->rxbuflock);
2050 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2052 struct ath5k_tx_status ts = {};
2053 struct ath5k_buf *bf, *bf0;
2054 struct ath5k_desc *ds;
2055 struct sk_buff *skb;
2056 struct ieee80211_tx_info *info;
2059 spin_lock(&txq->lock);
2060 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2063 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
2064 if (unlikely(ret == -EINPROGRESS))
2066 else if (unlikely(ret)) {
2067 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2072 sc->stats.tx_all_count++;
2074 info = IEEE80211_SKB_CB(skb);
2077 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2080 ieee80211_tx_info_clear_status(info);
2081 for (i = 0; i < 4; i++) {
2082 struct ieee80211_tx_rate *r =
2083 &info->status.rates[i];
2085 if (ts.ts_rate[i]) {
2086 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2087 r->count = ts.ts_retry[i];
2094 /* count the successful attempt as well */
2095 info->status.rates[ts.ts_final_idx].count++;
2097 if (unlikely(ts.ts_status)) {
2098 sc->ll_stats.dot11ACKFailureCount++;
2099 if (ts.ts_status & AR5K_TXERR_FILT) {
2100 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2101 sc->stats.txerr_filt++;
2103 if (ts.ts_status & AR5K_TXERR_XRETRY)
2104 sc->stats.txerr_retry++;
2105 if (ts.ts_status & AR5K_TXERR_FIFO)
2106 sc->stats.txerr_fifo++;
2108 info->flags |= IEEE80211_TX_STAT_ACK;
2109 info->status.ack_signal = ts.ts_rssi;
2113 * Remove MAC header padding before giving the frame
2116 ath5k_remove_padding(skb);
2118 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2119 sc->stats.antenna_tx[ts.ts_antenna]++;
2121 sc->stats.antenna_tx[0]++; /* invalid */
2123 ieee80211_tx_status(sc->hw, skb);
2125 spin_lock(&sc->txbuflock);
2126 list_move_tail(&bf->list, &sc->txbuf);
2128 spin_unlock(&sc->txbuflock);
2130 if (likely(list_empty(&txq->q)))
2132 spin_unlock(&txq->lock);
2133 if (sc->txbuf_len > ATH_TXBUF / 5)
2134 ieee80211_wake_queues(sc->hw);
2138 ath5k_tasklet_tx(unsigned long data)
2141 struct ath5k_softc *sc = (void *)data;
2143 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2144 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2145 ath5k_tx_processq(sc, &sc->txqs[i]);
2154 * Setup the beacon frame for transmit.
2157 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2159 struct sk_buff *skb = bf->skb;
2160 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2161 struct ath5k_hw *ah = sc->ah;
2162 struct ath5k_desc *ds;
2166 const int padsize = 0;
2168 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2170 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2171 "skbaddr %llx\n", skb, skb->data, skb->len,
2172 (unsigned long long)bf->skbaddr);
2173 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2174 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2179 antenna = ah->ah_tx_ant;
2181 flags = AR5K_TXDESC_NOACK;
2182 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2183 ds->ds_link = bf->daddr; /* self-linked */
2184 flags |= AR5K_TXDESC_VEOL;
2189 * If we use multiple antennas on AP and use
2190 * the Sectored AP scenario, switch antenna every
2191 * 4 beacons to make sure everybody hears our AP.
2192 * When a client tries to associate, hw will keep
2193 * track of the tx antenna to be used for this client
2194 * automaticaly, based on ACKed packets.
2196 * Note: AP still listens and transmits RTS on the
2197 * default antenna which is supposed to be an omni.
2199 * Note2: On sectored scenarios it's possible to have
2200 * multiple antennas (1omni -the default- and 14 sectors)
2201 * so if we choose to actually support this mode we need
2202 * to allow user to set how many antennas we have and tweak
2203 * the code below to send beacons on all of them.
2205 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2206 antenna = sc->bsent & 4 ? 2 : 1;
2209 /* FIXME: If we are in g mode and rate is a CCK rate
2210 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2211 * from tx power (value is in dB units already) */
2212 ds->ds_data = bf->skbaddr;
2213 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2214 ieee80211_get_hdrlen_from_skb(skb), padsize,
2215 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2216 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2217 1, AR5K_TXKEYIX_INVALID,
2218 antenna, flags, 0, 0);
2224 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2229 * Transmit a beacon frame at SWBA. Dynamic updates to the
2230 * frame contents are done as needed and the slot time is
2231 * also adjusted based on current state.
2233 * This is called from software irq context (beacontq or restq
2234 * tasklets) or user context from ath5k_beacon_config.
2237 ath5k_beacon_send(struct ath5k_softc *sc)
2239 struct ath5k_buf *bf = sc->bbuf;
2240 struct ath5k_hw *ah = sc->ah;
2241 struct sk_buff *skb;
2243 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2245 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2246 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2247 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2251 * Check if the previous beacon has gone out. If
2252 * not don't don't try to post another, skip this
2253 * period and wait for the next. Missed beacons
2254 * indicate a problem and should not occur. If we
2255 * miss too many consecutive beacons reset the device.
2257 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2259 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2260 "missed %u consecutive beacons\n", sc->bmisscount);
2261 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2262 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2263 "stuck beacon time (%u missed)\n",
2265 tasklet_schedule(&sc->restq);
2269 if (unlikely(sc->bmisscount != 0)) {
2270 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2271 "resume beacon xmit after %u misses\n",
2277 * Stop any current dma and put the new frame on the queue.
2278 * This should never fail since we check above that no frames
2279 * are still pending on the queue.
2281 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2282 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2283 /* NB: hw still stops DMA, so proceed */
2286 /* refresh the beacon for AP mode */
2287 if (sc->opmode == NL80211_IFTYPE_AP)
2288 ath5k_beacon_update(sc->hw, sc->vif);
2290 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2291 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2292 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2293 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2295 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2297 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2298 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2306 * ath5k_beacon_update_timers - update beacon timers
2308 * @sc: struct ath5k_softc pointer we are operating on
2309 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2310 * beacon timer update based on the current HW TSF.
2312 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2313 * of a received beacon or the current local hardware TSF and write it to the
2314 * beacon timer registers.
2316 * This is called in a variety of situations, e.g. when a beacon is received,
2317 * when a TSF update has been detected, but also when an new IBSS is created or
2318 * when we otherwise know we have to update the timers, but we keep it in this
2319 * function to have it all together in one place.
2322 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2324 struct ath5k_hw *ah = sc->ah;
2325 u32 nexttbtt, intval, hw_tu, bc_tu;
2328 intval = sc->bintval & AR5K_BEACON_PERIOD;
2329 if (WARN_ON(!intval))
2332 /* beacon TSF converted to TU */
2333 bc_tu = TSF_TO_TU(bc_tsf);
2335 /* current TSF converted to TU */
2336 hw_tsf = ath5k_hw_get_tsf64(ah);
2337 hw_tu = TSF_TO_TU(hw_tsf);
2340 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2343 * no beacons received, called internally.
2344 * just need to refresh timers based on HW TSF.
2346 nexttbtt = roundup(hw_tu + FUDGE, intval);
2347 } else if (bc_tsf == 0) {
2349 * no beacon received, probably called by ath5k_reset_tsf().
2350 * reset TSF to start with 0.
2353 intval |= AR5K_BEACON_RESET_TSF;
2354 } else if (bc_tsf > hw_tsf) {
2356 * beacon received, SW merge happend but HW TSF not yet updated.
2357 * not possible to reconfigure timers yet, but next time we
2358 * receive a beacon with the same BSSID, the hardware will
2359 * automatically update the TSF and then we need to reconfigure
2362 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2363 "need to wait for HW TSF sync\n");
2367 * most important case for beacon synchronization between STA.
2369 * beacon received and HW TSF has been already updated by HW.
2370 * update next TBTT based on the TSF of the beacon, but make
2371 * sure it is ahead of our local TSF timer.
2373 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2377 sc->nexttbtt = nexttbtt;
2379 intval |= AR5K_BEACON_ENA;
2380 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2383 * debugging output last in order to preserve the time critical aspect
2387 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2388 "reconfigured timers based on HW TSF\n");
2389 else if (bc_tsf == 0)
2390 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2391 "reset HW TSF and timers\n");
2393 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2394 "updated timers based on beacon TSF\n");
2396 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2397 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2398 (unsigned long long) bc_tsf,
2399 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2400 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2401 intval & AR5K_BEACON_PERIOD,
2402 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2403 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2408 * ath5k_beacon_config - Configure the beacon queues and interrupts
2410 * @sc: struct ath5k_softc pointer we are operating on
2412 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2413 * interrupts to detect TSF updates only.
2416 ath5k_beacon_config(struct ath5k_softc *sc)
2418 struct ath5k_hw *ah = sc->ah;
2419 unsigned long flags;
2421 spin_lock_irqsave(&sc->block, flags);
2423 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2425 if (sc->enable_beacon) {
2427 * In IBSS mode we use a self-linked tx descriptor and let the
2428 * hardware send the beacons automatically. We have to load it
2430 * We use the SWBA interrupt only to keep track of the beacon
2431 * timers in order to detect automatic TSF updates.
2433 ath5k_beaconq_config(sc);
2435 sc->imask |= AR5K_INT_SWBA;
2437 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2438 if (ath5k_hw_hasveol(ah))
2439 ath5k_beacon_send(sc);
2441 ath5k_beacon_update_timers(sc, -1);
2443 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2446 ath5k_hw_set_imr(ah, sc->imask);
2448 spin_unlock_irqrestore(&sc->block, flags);
2451 static void ath5k_tasklet_beacon(unsigned long data)
2453 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2456 * Software beacon alert--time to send a beacon.
2458 * In IBSS mode we use this interrupt just to
2459 * keep track of the next TBTT (target beacon
2460 * transmission time) in order to detect wether
2461 * automatic TSF updates happened.
2463 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2464 /* XXX: only if VEOL suppported */
2465 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2466 sc->nexttbtt += sc->bintval;
2467 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2468 "SWBA nexttbtt: %x hw_tu: %x "
2472 (unsigned long long) tsf);
2474 spin_lock(&sc->block);
2475 ath5k_beacon_send(sc);
2476 spin_unlock(&sc->block);
2481 /********************\
2482 * Interrupt handling *
2483 \********************/
2486 ath5k_init(struct ath5k_softc *sc)
2488 struct ath5k_hw *ah = sc->ah;
2491 mutex_lock(&sc->lock);
2493 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2496 * Stop anything previously setup. This is safe
2497 * no matter this is the first time through or not.
2499 ath5k_stop_locked(sc);
2501 /* Set PHY calibration interval */
2502 ah->ah_cal_intval = ath5k_calinterval;
2505 * The basic interface to setting the hardware in a good
2506 * state is ``reset''. On return the hardware is known to
2507 * be powered up and with interrupts disabled. This must
2508 * be followed by initialization of the appropriate bits
2509 * and then setup of the interrupt mask.
2511 sc->curchan = sc->hw->conf.channel;
2512 sc->curband = &sc->sbands[sc->curchan->band];
2513 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2514 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2515 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
2516 ret = ath5k_reset(sc, NULL);
2520 ath5k_rfkill_hw_start(ah);
2523 * Reset the key cache since some parts do not reset the
2524 * contents on initial power up or resume from suspend.
2526 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2527 ath5k_hw_reset_key(ah, i);
2529 /* Set ack to be sent at low bit-rates */
2530 ath5k_hw_set_ack_bitrate_high(ah, false);
2534 mutex_unlock(&sc->lock);
2539 ath5k_stop_locked(struct ath5k_softc *sc)
2541 struct ath5k_hw *ah = sc->ah;
2543 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2544 test_bit(ATH_STAT_INVALID, sc->status));
2547 * Shutdown the hardware and driver:
2548 * stop output from above
2549 * disable interrupts
2551 * turn off the radio
2552 * clear transmit machinery
2553 * clear receive machinery
2554 * drain and release tx queues
2555 * reclaim beacon resources
2556 * power down hardware
2558 * Note that some of this work is not possible if the
2559 * hardware is gone (invalid).
2561 ieee80211_stop_queues(sc->hw);
2563 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2565 ath5k_hw_set_imr(ah, 0);
2566 synchronize_irq(sc->pdev->irq);
2568 ath5k_txq_cleanup(sc);
2569 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2571 ath5k_hw_phy_disable(ah);
2579 * Stop the device, grabbing the top-level lock to protect
2580 * against concurrent entry through ath5k_init (which can happen
2581 * if another thread does a system call and the thread doing the
2582 * stop is preempted).
2585 ath5k_stop_hw(struct ath5k_softc *sc)
2589 mutex_lock(&sc->lock);
2590 ret = ath5k_stop_locked(sc);
2591 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2593 * Don't set the card in full sleep mode!
2595 * a) When the device is in this state it must be carefully
2596 * woken up or references to registers in the PCI clock
2597 * domain may freeze the bus (and system). This varies
2598 * by chip and is mostly an issue with newer parts
2599 * (madwifi sources mentioned srev >= 0x78) that go to
2600 * sleep more quickly.
2602 * b) On older chips full sleep results a weird behaviour
2603 * during wakeup. I tested various cards with srev < 0x78
2604 * and they don't wake up after module reload, a second
2605 * module reload is needed to bring the card up again.
2607 * Until we figure out what's going on don't enable
2608 * full chip reset on any chip (this is what Legacy HAL
2609 * and Sam's HAL do anyway). Instead Perform a full reset
2610 * on the device (same as initial state after attach) and
2611 * leave it idle (keep MAC/BB on warm reset) */
2612 ret = ath5k_hw_on_hold(sc->ah);
2614 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2615 "putting device to sleep\n");
2617 ath5k_txbuf_free(sc, sc->bbuf);
2620 mutex_unlock(&sc->lock);
2622 tasklet_kill(&sc->rxtq);
2623 tasklet_kill(&sc->txtq);
2624 tasklet_kill(&sc->restq);
2625 tasklet_kill(&sc->calib);
2626 tasklet_kill(&sc->beacontq);
2628 ath5k_rfkill_hw_stop(sc->ah);
2634 ath5k_intr(int irq, void *dev_id)
2636 struct ath5k_softc *sc = dev_id;
2637 struct ath5k_hw *ah = sc->ah;
2638 enum ath5k_int status;
2639 unsigned int counter = 1000;
2641 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2642 !ath5k_hw_is_intr_pending(ah)))
2646 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2647 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2649 if (unlikely(status & AR5K_INT_FATAL)) {
2651 * Fatal errors are unrecoverable.
2652 * Typically these are caused by DMA errors.
2654 tasklet_schedule(&sc->restq);
2655 } else if (unlikely(status & AR5K_INT_RXORN)) {
2656 tasklet_schedule(&sc->restq);
2658 if (status & AR5K_INT_SWBA) {
2659 tasklet_hi_schedule(&sc->beacontq);
2661 if (status & AR5K_INT_RXEOL) {
2663 * NB: the hardware should re-read the link when
2664 * RXE bit is written, but it doesn't work at
2665 * least on older hardware revs.
2669 if (status & AR5K_INT_TXURN) {
2670 /* bump tx trigger level */
2671 ath5k_hw_update_tx_triglevel(ah, true);
2673 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2674 tasklet_schedule(&sc->rxtq);
2675 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2676 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2677 tasklet_schedule(&sc->txtq);
2678 if (status & AR5K_INT_BMISS) {
2681 if (status & AR5K_INT_SWI) {
2682 tasklet_schedule(&sc->calib);
2684 if (status & AR5K_INT_MIB) {
2686 * These stats are also used for ANI i think
2687 * so how about updating them more often ?
2689 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2691 if (status & AR5K_INT_GPIO)
2692 tasklet_schedule(&sc->rf_kill.toggleq);
2695 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2697 if (unlikely(!counter))
2698 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2700 ath5k_hw_calibration_poll(ah);
2706 ath5k_tasklet_reset(unsigned long data)
2708 struct ath5k_softc *sc = (void *)data;
2710 ath5k_reset_wake(sc);
2714 * Periodically recalibrate the PHY to account
2715 * for temperature/environment changes.
2718 ath5k_tasklet_calibrate(unsigned long data)
2720 struct ath5k_softc *sc = (void *)data;
2721 struct ath5k_hw *ah = sc->ah;
2723 /* Only full calibration for now */
2724 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2727 /* Stop queues so that calibration
2728 * doesn't interfere with tx */
2729 ieee80211_stop_queues(sc->hw);
2731 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2732 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2733 sc->curchan->hw_value);
2735 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2737 * Rfgain is out of bounds, reset the chip
2738 * to load new gain values.
2740 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2741 ath5k_reset_wake(sc);
2743 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2744 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2745 ieee80211_frequency_to_channel(
2746 sc->curchan->center_freq));
2748 ah->ah_swi_mask = 0;
2751 ieee80211_wake_queues(sc->hw);
2756 /********************\
2757 * Mac80211 functions *
2758 \********************/
2761 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2763 struct ath5k_softc *sc = hw->priv;
2765 return ath5k_tx_queue(hw, skb, sc->txq);
2768 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2769 struct ath5k_txq *txq)
2771 struct ath5k_softc *sc = hw->priv;
2772 struct ath5k_buf *bf;
2773 unsigned long flags;
2776 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2778 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2779 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2782 * the hardware expects the header padded to 4 byte boundaries
2783 * if this is not the case we add the padding after the header
2785 padsize = ath5k_add_padding(skb);
2787 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2788 " headroom to pad");
2792 spin_lock_irqsave(&sc->txbuflock, flags);
2793 if (list_empty(&sc->txbuf)) {
2794 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2795 spin_unlock_irqrestore(&sc->txbuflock, flags);
2796 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2799 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2800 list_del(&bf->list);
2802 if (list_empty(&sc->txbuf))
2803 ieee80211_stop_queues(hw);
2804 spin_unlock_irqrestore(&sc->txbuflock, flags);
2808 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
2810 spin_lock_irqsave(&sc->txbuflock, flags);
2811 list_add_tail(&bf->list, &sc->txbuf);
2813 spin_unlock_irqrestore(&sc->txbuflock, flags);
2816 return NETDEV_TX_OK;
2819 dev_kfree_skb_any(skb);
2820 return NETDEV_TX_OK;
2824 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2825 * and change to the given channel.
2828 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2830 struct ath5k_hw *ah = sc->ah;
2833 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2836 ath5k_hw_set_imr(ah, 0);
2837 ath5k_txq_cleanup(sc);
2841 sc->curband = &sc->sbands[chan->band];
2843 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2845 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2849 ret = ath5k_rx_start(sc);
2851 ATH5K_ERR(sc, "can't start recv logic\n");
2856 * Change channels and update the h/w rate map if we're switching;
2857 * e.g. 11a to 11b/g.
2859 * We may be doing a reset in response to an ioctl that changes the
2860 * channel so update any state that might change as a result.
2864 /* ath5k_chan_change(sc, c); */
2866 ath5k_beacon_config(sc);
2867 /* intrs are enabled by ath5k_beacon_config */
2875 ath5k_reset_wake(struct ath5k_softc *sc)
2879 ret = ath5k_reset(sc, sc->curchan);
2881 ieee80211_wake_queues(sc->hw);
2886 static int ath5k_start(struct ieee80211_hw *hw)
2888 return ath5k_init(hw->priv);
2891 static void ath5k_stop(struct ieee80211_hw *hw)
2893 ath5k_stop_hw(hw->priv);
2896 static int ath5k_add_interface(struct ieee80211_hw *hw,
2897 struct ieee80211_vif *vif)
2899 struct ath5k_softc *sc = hw->priv;
2902 mutex_lock(&sc->lock);
2910 switch (vif->type) {
2911 case NL80211_IFTYPE_AP:
2912 case NL80211_IFTYPE_STATION:
2913 case NL80211_IFTYPE_ADHOC:
2914 case NL80211_IFTYPE_MESH_POINT:
2915 case NL80211_IFTYPE_MONITOR:
2916 sc->opmode = vif->type;
2923 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2925 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2926 ath5k_mode_setup(sc);
2930 mutex_unlock(&sc->lock);
2935 ath5k_remove_interface(struct ieee80211_hw *hw,
2936 struct ieee80211_vif *vif)
2938 struct ath5k_softc *sc = hw->priv;
2939 u8 mac[ETH_ALEN] = {};
2941 mutex_lock(&sc->lock);
2945 ath5k_hw_set_lladdr(sc->ah, mac);
2948 mutex_unlock(&sc->lock);
2952 * TODO: Phy disable/diversity etc
2955 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2957 struct ath5k_softc *sc = hw->priv;
2958 struct ath5k_hw *ah = sc->ah;
2959 struct ieee80211_conf *conf = &hw->conf;
2962 mutex_lock(&sc->lock);
2964 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2965 ret = ath5k_chan_set(sc, conf->channel);
2970 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2971 (sc->power_level != conf->power_level)) {
2972 sc->power_level = conf->power_level;
2975 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2979 * 1) Move this on config_interface and handle each case
2980 * separately eg. when we have only one STA vif, use
2981 * AR5K_ANTMODE_SINGLE_AP
2983 * 2) Allow the user to change antenna mode eg. when only
2984 * one antenna is present
2986 * 3) Allow the user to set default/tx antenna when possible
2988 * 4) Default mode should handle 90% of the cases, together
2989 * with fixed a/b and single AP modes we should be able to
2990 * handle 99%. Sectored modes are extreme cases and i still
2991 * haven't found a usage for them. If we decide to support them,
2992 * then we must allow the user to set how many tx antennas we
2995 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
2998 mutex_unlock(&sc->lock);
3002 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3003 struct netdev_hw_addr_list *mc_list)
3007 struct netdev_hw_addr *ha;
3012 netdev_hw_addr_list_for_each(ha, mc_list) {
3013 /* calculate XOR of eight 6-bit values */
3014 val = get_unaligned_le32(ha->addr + 0);
3015 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3016 val = get_unaligned_le32(ha->addr + 3);
3017 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3019 mfilt[pos / 32] |= (1 << (pos % 32));
3020 /* XXX: we might be able to just do this instead,
3021 * but not sure, needs testing, if we do use this we'd
3022 * neet to inform below to not reset the mcast */
3023 /* ath5k_hw_set_mcast_filterindex(ah,
3027 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3030 #define SUPPORTED_FIF_FLAGS \
3031 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3032 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3033 FIF_BCN_PRBRESP_PROMISC
3035 * o always accept unicast, broadcast, and multicast traffic
3036 * o multicast traffic for all BSSIDs will be enabled if mac80211
3038 * o maintain current state of phy ofdm or phy cck error reception.
3039 * If the hardware detects any of these type of errors then
3040 * ath5k_hw_get_rx_filter() will pass to us the respective
3041 * hardware filters to be able to receive these type of frames.
3042 * o probe request frames are accepted only when operating in
3043 * hostap, adhoc, or monitor modes
3044 * o enable promiscuous mode according to the interface state
3046 * - when operating in adhoc mode so the 802.11 layer creates
3047 * node table entries for peers,
3048 * - when operating in station mode for collecting rssi data when
3049 * the station is otherwise quiet, or
3052 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3053 unsigned int changed_flags,
3054 unsigned int *new_flags,
3057 struct ath5k_softc *sc = hw->priv;
3058 struct ath5k_hw *ah = sc->ah;
3059 u32 mfilt[2], rfilt;
3061 mutex_lock(&sc->lock);
3063 mfilt[0] = multicast;
3064 mfilt[1] = multicast >> 32;
3066 /* Only deal with supported flags */
3067 changed_flags &= SUPPORTED_FIF_FLAGS;
3068 *new_flags &= SUPPORTED_FIF_FLAGS;
3070 /* If HW detects any phy or radar errors, leave those filters on.
3071 * Also, always enable Unicast, Broadcasts and Multicast
3072 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3073 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3074 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3075 AR5K_RX_FILTER_MCAST);
3077 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3078 if (*new_flags & FIF_PROMISC_IN_BSS) {
3079 rfilt |= AR5K_RX_FILTER_PROM;
3080 __set_bit(ATH_STAT_PROMISC, sc->status);
3082 __clear_bit(ATH_STAT_PROMISC, sc->status);
3086 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3087 if (*new_flags & FIF_ALLMULTI) {
3092 /* This is the best we can do */
3093 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3094 rfilt |= AR5K_RX_FILTER_PHYERR;
3096 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3097 * and probes for any BSSID, this needs testing */
3098 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3099 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3101 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3102 * set we should only pass on control frames for this
3103 * station. This needs testing. I believe right now this
3104 * enables *all* control frames, which is OK.. but
3105 * but we should see if we can improve on granularity */
3106 if (*new_flags & FIF_CONTROL)
3107 rfilt |= AR5K_RX_FILTER_CONTROL;
3109 /* Additional settings per mode -- this is per ath5k */
3111 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3113 switch (sc->opmode) {
3114 case NL80211_IFTYPE_MESH_POINT:
3115 case NL80211_IFTYPE_MONITOR:
3116 rfilt |= AR5K_RX_FILTER_CONTROL |
3117 AR5K_RX_FILTER_BEACON |
3118 AR5K_RX_FILTER_PROBEREQ |
3119 AR5K_RX_FILTER_PROM;
3121 case NL80211_IFTYPE_AP:
3122 case NL80211_IFTYPE_ADHOC:
3123 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3124 AR5K_RX_FILTER_BEACON;
3126 case NL80211_IFTYPE_STATION:
3128 rfilt |= AR5K_RX_FILTER_BEACON;
3134 ath5k_hw_set_rx_filter(ah, rfilt);
3136 /* Set multicast bits */
3137 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3138 /* Set the cached hw filter flags, this will alter actually
3140 sc->filter_flags = rfilt;
3142 mutex_unlock(&sc->lock);
3146 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3147 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3148 struct ieee80211_key_conf *key)
3150 struct ath5k_softc *sc = hw->priv;
3151 struct ath5k_hw *ah = sc->ah;
3152 struct ath_common *common = ath5k_hw_common(ah);
3155 if (modparam_nohwcrypt)
3158 if (sc->opmode == NL80211_IFTYPE_AP)
3166 if (sc->ah->ah_aes_support)
3175 mutex_lock(&sc->lock);
3179 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3180 sta ? sta->addr : NULL);
3182 ATH5K_ERR(sc, "can't set the key\n");
3185 __set_bit(key->keyidx, common->keymap);
3186 key->hw_key_idx = key->keyidx;
3187 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3188 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3191 ath5k_hw_reset_key(sc->ah, key->keyidx);
3192 __clear_bit(key->keyidx, common->keymap);
3201 mutex_unlock(&sc->lock);
3206 ath5k_get_stats(struct ieee80211_hw *hw,
3207 struct ieee80211_low_level_stats *stats)
3209 struct ath5k_softc *sc = hw->priv;
3210 struct ath5k_hw *ah = sc->ah;
3213 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3215 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3221 ath5k_get_tsf(struct ieee80211_hw *hw)
3223 struct ath5k_softc *sc = hw->priv;
3225 return ath5k_hw_get_tsf64(sc->ah);
3229 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3231 struct ath5k_softc *sc = hw->priv;
3233 ath5k_hw_set_tsf64(sc->ah, tsf);
3237 ath5k_reset_tsf(struct ieee80211_hw *hw)
3239 struct ath5k_softc *sc = hw->priv;
3242 * in IBSS mode we need to update the beacon timers too.
3243 * this will also reset the TSF if we call it with 0
3245 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3246 ath5k_beacon_update_timers(sc, 0);
3248 ath5k_hw_reset_tsf(sc->ah);
3252 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3253 * this is called only once at config_bss time, for AP we do it every
3254 * SWBA interrupt so that the TIM will reflect buffered frames.
3256 * Called with the beacon lock.
3259 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3262 struct ath5k_softc *sc = hw->priv;
3263 struct sk_buff *skb;
3265 if (WARN_ON(!vif)) {
3270 skb = ieee80211_beacon_get(hw, vif);
3277 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3279 ath5k_txbuf_free(sc, sc->bbuf);
3280 sc->bbuf->skb = skb;
3281 ret = ath5k_beacon_setup(sc, sc->bbuf);
3283 sc->bbuf->skb = NULL;
3289 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3291 struct ath5k_softc *sc = hw->priv;
3292 struct ath5k_hw *ah = sc->ah;
3294 rfilt = ath5k_hw_get_rx_filter(ah);
3296 rfilt |= AR5K_RX_FILTER_BEACON;
3298 rfilt &= ~AR5K_RX_FILTER_BEACON;
3299 ath5k_hw_set_rx_filter(ah, rfilt);
3300 sc->filter_flags = rfilt;
3303 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3304 struct ieee80211_vif *vif,
3305 struct ieee80211_bss_conf *bss_conf,
3308 struct ath5k_softc *sc = hw->priv;
3309 struct ath5k_hw *ah = sc->ah;
3310 struct ath_common *common = ath5k_hw_common(ah);
3311 unsigned long flags;
3313 mutex_lock(&sc->lock);
3314 if (WARN_ON(sc->vif != vif))
3317 if (changes & BSS_CHANGED_BSSID) {
3318 /* Cache for later use during resets */
3319 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3321 ath5k_hw_set_associd(ah);
3325 if (changes & BSS_CHANGED_BEACON_INT)
3326 sc->bintval = bss_conf->beacon_int;
3328 if (changes & BSS_CHANGED_ASSOC) {
3329 sc->assoc = bss_conf->assoc;
3330 if (sc->opmode == NL80211_IFTYPE_STATION)
3331 set_beacon_filter(hw, sc->assoc);
3332 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3333 AR5K_LED_ASSOC : AR5K_LED_INIT);
3334 if (bss_conf->assoc) {
3335 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3336 "Bss Info ASSOC %d, bssid: %pM\n",
3337 bss_conf->aid, common->curbssid);
3338 common->curaid = bss_conf->aid;
3339 ath5k_hw_set_associd(ah);
3340 /* Once ANI is available you would start it here */
3344 if (changes & BSS_CHANGED_BEACON) {
3345 spin_lock_irqsave(&sc->block, flags);
3346 ath5k_beacon_update(hw, vif);
3347 spin_unlock_irqrestore(&sc->block, flags);
3350 if (changes & BSS_CHANGED_BEACON_ENABLED)
3351 sc->enable_beacon = bss_conf->enable_beacon;
3353 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3354 BSS_CHANGED_BEACON_INT))
3355 ath5k_beacon_config(sc);
3358 mutex_unlock(&sc->lock);
3361 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3363 struct ath5k_softc *sc = hw->priv;
3365 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3368 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3370 struct ath5k_softc *sc = hw->priv;
3371 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3372 AR5K_LED_ASSOC : AR5K_LED_INIT);
3376 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3378 * @hw: struct ieee80211_hw pointer
3379 * @coverage_class: IEEE 802.11 coverage class number
3381 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3382 * coverage class. The values are persistent, they are restored after device
3385 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3387 struct ath5k_softc *sc = hw->priv;
3389 mutex_lock(&sc->lock);
3390 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3391 mutex_unlock(&sc->lock);
git://bbs.cooldavid.org / net-next-2.6.git / blob