drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.101"
  72 #define DRV_MODULE_RELDATE      "August 28, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                  TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define TG3_DMA_BYTE_ENAB               64
 129
 130 #define TG3_RX_STD_DMA_SZ               1536
 131 #define TG3_RX_JMB_DMA_SZ               9046
 132
 133 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 134
 135 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 136 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 137
 138 /* minimum number of free TX descriptors required to wake up TX process */
 139 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 140
 141 #define TG3_RAW_IP_ALIGN 2
 142
 143 /* number of ETHTOOL_GSTATS u64's */
 144 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 145
 146 #define TG3_NUM_TEST            6
 147
 148 #define FIRMWARE_TG3            "tigon/tg3.bin"
 149 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 150 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 151
 152 static char version[] __devinitdata =
 153         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 154
 155 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 156 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 157 MODULE_LICENSE("GPL");
 158 MODULE_VERSION(DRV_MODULE_VERSION);
 159 MODULE_FIRMWARE(FIRMWARE_TG3);
 160 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 161 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 162
 163 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 164
 165 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 166 module_param(tg3_debug, int, 0);
 167 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 168
 169 static struct pci_device_id tg3_pci_tbl[] = {
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 243         {}
 244 };
 245
 246 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 247
 248 static const struct {
 249         const char string[ETH_GSTRING_LEN];
 250 } ethtool_stats_keys[TG3_NUM_STATS] = {
 251         { "rx_octets" },
 252         { "rx_fragments" },
 253         { "rx_ucast_packets" },
 254         { "rx_mcast_packets" },
 255         { "rx_bcast_packets" },
 256         { "rx_fcs_errors" },
 257         { "rx_align_errors" },
 258         { "rx_xon_pause_rcvd" },
 259         { "rx_xoff_pause_rcvd" },
 260         { "rx_mac_ctrl_rcvd" },
 261         { "rx_xoff_entered" },
 262         { "rx_frame_too_long_errors" },
 263         { "rx_jabbers" },
 264         { "rx_undersize_packets" },
 265         { "rx_in_length_errors" },
 266         { "rx_out_length_errors" },
 267         { "rx_64_or_less_octet_packets" },
 268         { "rx_65_to_127_octet_packets" },
 269         { "rx_128_to_255_octet_packets" },
 270         { "rx_256_to_511_octet_packets" },
 271         { "rx_512_to_1023_octet_packets" },
 272         { "rx_1024_to_1522_octet_packets" },
 273         { "rx_1523_to_2047_octet_packets" },
 274         { "rx_2048_to_4095_octet_packets" },
 275         { "rx_4096_to_8191_octet_packets" },
 276         { "rx_8192_to_9022_octet_packets" },
 277
 278         { "tx_octets" },
 279         { "tx_collisions" },
 280
 281         { "tx_xon_sent" },
 282         { "tx_xoff_sent" },
 283         { "tx_flow_control" },
 284         { "tx_mac_errors" },
 285         { "tx_single_collisions" },
 286         { "tx_mult_collisions" },
 287         { "tx_deferred" },
 288         { "tx_excessive_collisions" },
 289         { "tx_late_collisions" },
 290         { "tx_collide_2times" },
 291         { "tx_collide_3times" },
 292         { "tx_collide_4times" },
 293         { "tx_collide_5times" },
 294         { "tx_collide_6times" },
 295         { "tx_collide_7times" },
 296         { "tx_collide_8times" },
 297         { "tx_collide_9times" },
 298         { "tx_collide_10times" },
 299         { "tx_collide_11times" },
 300         { "tx_collide_12times" },
 301         { "tx_collide_13times" },
 302         { "tx_collide_14times" },
 303         { "tx_collide_15times" },
 304         { "tx_ucast_packets" },
 305         { "tx_mcast_packets" },
 306         { "tx_bcast_packets" },
 307         { "tx_carrier_sense_errors" },
 308         { "tx_discards" },
 309         { "tx_errors" },
 310
 311         { "dma_writeq_full" },
 312         { "dma_write_prioq_full" },
 313         { "rxbds_empty" },
 314         { "rx_discards" },
 315         { "rx_errors" },
 316         { "rx_threshold_hit" },
 317
 318         { "dma_readq_full" },
 319         { "dma_read_prioq_full" },
 320         { "tx_comp_queue_full" },
 321
 322         { "ring_set_send_prod_index" },
 323         { "ring_status_update" },
 324         { "nic_irqs" },
 325         { "nic_avoided_irqs" },
 326         { "nic_tx_threshold_hit" }
 327 };
 328
 329 static const struct {
 330         const char string[ETH_GSTRING_LEN];
 331 } ethtool_test_keys[TG3_NUM_TEST] = {
 332         { "nvram test     (online) " },
 333         { "link test      (online) " },
 334         { "register test  (offline)" },
 335         { "memory test    (offline)" },
 336         { "loopback test  (offline)" },
 337         { "interrupt test (offline)" },
 338 };
 339
 340 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 341 {
 342         writel(val, tp->regs + off);
 343 }
 344
 345 static u32 tg3_read32(struct tg3 *tp, u32 off)
 346 {
 347         return (readl(tp->regs + off));
 348 }
 349
 350 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 351 {
 352         writel(val, tp->aperegs + off);
 353 }
 354
 355 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 356 {
 357         return (readl(tp->aperegs + off));
 358 }
 359
 360 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 361 {
 362         unsigned long flags;
 363
 364         spin_lock_irqsave(&tp->indirect_lock, flags);
 365         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 366         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 367         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 368 }
 369
 370 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 371 {
 372         writel(val, tp->regs + off);
 373         readl(tp->regs + off);
 374 }
 375
 376 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 377 {
 378         unsigned long flags;
 379         u32 val;
 380
 381         spin_lock_irqsave(&tp->indirect_lock, flags);
 382         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 383         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 384         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 385         return val;
 386 }
 387
 388 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 389 {
 390         unsigned long flags;
 391
 392         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 393                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 394                                        TG3_64BIT_REG_LOW, val);
 395                 return;
 396         }
 397         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 398                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 399                                        TG3_64BIT_REG_LOW, val);
 400                 return;
 401         }
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407
 408         /* In indirect mode when disabling interrupts, we also need
 409          * to clear the interrupt bit in the GRC local ctrl register.
 410          */
 411         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 412             (val == 0x1)) {
 413                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 414                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 415         }
 416 }
 417
 418 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 419 {
 420         unsigned long flags;
 421         u32 val;
 422
 423         spin_lock_irqsave(&tp->indirect_lock, flags);
 424         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 425         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 426         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 427         return val;
 428 }
 429
 430 /* usec_wait specifies the wait time in usec when writing to certain registers
 431  * where it is unsafe to read back the register without some delay.
 432  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 433  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 434  */
 435 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 436 {
 437         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 438             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 439                 /* Non-posted methods */
 440                 tp->write32(tp, off, val);
 441         else {
 442                 /* Posted method */
 443                 tg3_write32(tp, off, val);
 444                 if (usec_wait)
 445                         udelay(usec_wait);
 446                 tp->read32(tp, off);
 447         }
 448         /* Wait again after the read for the posted method to guarantee that
 449          * the wait time is met.
 450          */
 451         if (usec_wait)
 452                 udelay(usec_wait);
 453 }
 454
 455 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 456 {
 457         tp->write32_mbox(tp, off, val);
 458         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 459             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 460                 tp->read32_mbox(tp, off);
 461 }
 462
 463 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 464 {
 465         void __iomem *mbox = tp->regs + off;
 466         writel(val, mbox);
 467         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 468                 writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 470                 readl(mbox);
 471 }
 472
 473 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 474 {
 475         return (readl(tp->regs + off + GRCMBOX_BASE));
 476 }
 477
 478 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 479 {
 480         writel(val, tp->regs + off + GRCMBOX_BASE);
 481 }
 482
 483 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 484 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 485 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 486 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 487 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 488
 489 #define tw32(reg,val)           tp->write32(tp, reg, val)
 490 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 491 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 492 #define tr32(reg)               tp->read32(tp, reg)
 493
 494 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         unsigned long flags;
 497
 498         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 499             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 500                 return;
 501
 502         spin_lock_irqsave(&tp->indirect_lock, flags);
 503         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 504                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 505                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 506
 507                 /* Always leave this as zero. */
 508                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 509         } else {
 510                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 511                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 512
 513                 /* Always leave this as zero. */
 514                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 515         }
 516         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 517 }
 518
 519 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 520 {
 521         unsigned long flags;
 522
 523         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 524             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 525                 *val = 0;
 526                 return;
 527         }
 528
 529         spin_lock_irqsave(&tp->indirect_lock, flags);
 530         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 531                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 532                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 533
 534                 /* Always leave this as zero. */
 535                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 536         } else {
 537                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 538                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 539
 540                 /* Always leave this as zero. */
 541                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 542         }
 543         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 544 }
 545
 546 static void tg3_ape_lock_init(struct tg3 *tp)
 547 {
 548         int i;
 549
 550         /* Make sure the driver hasn't any stale locks. */
 551         for (i = 0; i < 8; i++)
 552                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 553                                 APE_LOCK_GRANT_DRIVER);
 554 }
 555
 556 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 557 {
 558         int i, off;
 559         int ret = 0;
 560         u32 status;
 561
 562         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 563                 return 0;
 564
 565         switch (locknum) {
 566                 case TG3_APE_LOCK_GRC:
 567                 case TG3_APE_LOCK_MEM:
 568                         break;
 569                 default:
 570                         return -EINVAL;
 571         }
 572
 573         off = 4 * locknum;
 574
 575         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 576
 577         /* Wait for up to 1 millisecond to acquire lock. */
 578         for (i = 0; i < 100; i++) {
 579                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 580                 if (status == APE_LOCK_GRANT_DRIVER)
 581                         break;
 582                 udelay(10);
 583         }
 584
 585         if (status != APE_LOCK_GRANT_DRIVER) {
 586                 /* Revoke the lock request. */
 587                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 588                                 APE_LOCK_GRANT_DRIVER);
 589
 590                 ret = -EBUSY;
 591         }
 592
 593         return ret;
 594 }
 595
 596 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 597 {
 598         int off;
 599
 600         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 601                 return;
 602
 603         switch (locknum) {
 604                 case TG3_APE_LOCK_GRC:
 605                 case TG3_APE_LOCK_MEM:
 606                         break;
 607                 default:
 608                         return;
 609         }
 610
 611         off = 4 * locknum;
 612         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 613 }
 614
 615 static void tg3_disable_ints(struct tg3 *tp)
 616 {
 617         int i;
 618
 619         tw32(TG3PCI_MISC_HOST_CTRL,
 620              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 621         for (i = 0; i < tp->irq_max; i++)
 622                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 623 }
 624
 625 static void tg3_enable_ints(struct tg3 *tp)
 626 {
 627         int i;
 628         u32 coal_now = 0;
 629
 630         tp->irq_sync = 0;
 631         wmb();
 632
 633         tw32(TG3PCI_MISC_HOST_CTRL,
 634              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 635
 636         for (i = 0; i < tp->irq_cnt; i++) {
 637                 struct tg3_napi *tnapi = &tp->napi[i];
 638                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 639                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 640                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641
 642                 coal_now |= tnapi->coal_now;
 643         }
 644
 645         /* Force an initial interrupt */
 646         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 647             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 648                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 649         else
 650                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 651                      HOSTCC_MODE_ENABLE | coal_now);
 652 }
 653
 654 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 655 {
 656         struct tg3 *tp = tnapi->tp;
 657         struct tg3_hw_status *sblk = tnapi->hw_status;
 658         unsigned int work_exists = 0;
 659
 660         /* check for phy events */
 661         if (!(tp->tg3_flags &
 662               (TG3_FLAG_USE_LINKCHG_REG |
 663                TG3_FLAG_POLL_SERDES))) {
 664                 if (sblk->status & SD_STATUS_LINK_CHG)
 665                         work_exists = 1;
 666         }
 667         /* check for RX/TX work to do */
 668         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 669             sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
 670                 work_exists = 1;
 671
 672         return work_exists;
 673 }
 674
 675 /* tg3_int_reenable
 676  *  similar to tg3_enable_ints, but it accurately determines whether there
 677  *  is new work pending and can return without flushing the PIO write
 678  *  which reenables interrupts
 679  */
 680 static void tg3_int_reenable(struct tg3_napi *tnapi)
 681 {
 682         struct tg3 *tp = tnapi->tp;
 683
 684         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 685         mmiowb();
 686
 687         /* When doing tagged status, this work check is unnecessary.
 688          * The last_tag we write above tells the chip which piece of
 689          * work we've completed.
 690          */
 691         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 692             tg3_has_work(tnapi))
 693                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 694                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 695 }
 696
 697 static inline void tg3_netif_stop(struct tg3 *tp)
 698 {
 699         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 700         napi_disable(&tp->napi[0].napi);
 701         netif_tx_disable(tp->dev);
 702 }
 703
 704 static inline void tg3_netif_start(struct tg3 *tp)
 705 {
 706         struct tg3_napi *tnapi = &tp->napi[0];
 707
 708         /* NOTE: unconditional netif_tx_wake_all_queues is only
 709          * appropriate so long as all callers are assured to
 710          * have free tx slots (such as after tg3_init_hw)
 711          */
 712         netif_tx_wake_all_queues(tp->dev);
 713
 714         napi_enable(&tnapi->napi);
 715         tnapi->hw_status->status |= SD_STATUS_UPDATED;
 716         tg3_enable_ints(tp);
 717 }
 718
 719 static void tg3_switch_clocks(struct tg3 *tp)
 720 {
 721         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 722         u32 orig_clock_ctrl;
 723
 724         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 725             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 726                 return;
 727
 728         orig_clock_ctrl = clock_ctrl;
 729         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 730                        CLOCK_CTRL_CLKRUN_OENABLE |
 731                        0x1f);
 732         tp->pci_clock_ctrl = clock_ctrl;
 733
 734         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 735                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 736                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 737                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 738                 }
 739         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 740                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 741                             clock_ctrl |
 742                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 743                             40);
 744                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 745                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 746                             40);
 747         }
 748         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 749 }
 750
 751 #define PHY_BUSY_LOOPS  5000
 752
 753 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 754 {
 755         u32 frame_val;
 756         unsigned int loops;
 757         int ret;
 758
 759         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 760                 tw32_f(MAC_MI_MODE,
 761                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 762                 udelay(80);
 763         }
 764
 765         *val = 0x0;
 766
 767         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 768                       MI_COM_PHY_ADDR_MASK);
 769         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 770                       MI_COM_REG_ADDR_MASK);
 771         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 772
 773         tw32_f(MAC_MI_COM, frame_val);
 774
 775         loops = PHY_BUSY_LOOPS;
 776         while (loops != 0) {
 777                 udelay(10);
 778                 frame_val = tr32(MAC_MI_COM);
 779
 780                 if ((frame_val & MI_COM_BUSY) == 0) {
 781                         udelay(5);
 782                         frame_val = tr32(MAC_MI_COM);
 783                         break;
 784                 }
 785                 loops -= 1;
 786         }
 787
 788         ret = -EBUSY;
 789         if (loops != 0) {
 790                 *val = frame_val & MI_COM_DATA_MASK;
 791                 ret = 0;
 792         }
 793
 794         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 795                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 796                 udelay(80);
 797         }
 798
 799         return ret;
 800 }
 801
 802 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 803 {
 804         u32 frame_val;
 805         unsigned int loops;
 806         int ret;
 807
 808         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 809             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 810                 return 0;
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE,
 814                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 815                 udelay(80);
 816         }
 817
 818         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 819                       MI_COM_PHY_ADDR_MASK);
 820         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 821                       MI_COM_REG_ADDR_MASK);
 822         frame_val |= (val & MI_COM_DATA_MASK);
 823         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 824
 825         tw32_f(MAC_MI_COM, frame_val);
 826
 827         loops = PHY_BUSY_LOOPS;
 828         while (loops != 0) {
 829                 udelay(10);
 830                 frame_val = tr32(MAC_MI_COM);
 831                 if ((frame_val & MI_COM_BUSY) == 0) {
 832                         udelay(5);
 833                         frame_val = tr32(MAC_MI_COM);
 834                         break;
 835                 }
 836                 loops -= 1;
 837         }
 838
 839         ret = -EBUSY;
 840         if (loops != 0)
 841                 ret = 0;
 842
 843         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 844                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 845                 udelay(80);
 846         }
 847
 848         return ret;
 849 }
 850
 851 static int tg3_bmcr_reset(struct tg3 *tp)
 852 {
 853         u32 phy_control;
 854         int limit, err;
 855
 856         /* OK, reset it, and poll the BMCR_RESET bit until it
 857          * clears or we time out.
 858          */
 859         phy_control = BMCR_RESET;
 860         err = tg3_writephy(tp, MII_BMCR, phy_control);
 861         if (err != 0)
 862                 return -EBUSY;
 863
 864         limit = 5000;
 865         while (limit--) {
 866                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 867                 if (err != 0)
 868                         return -EBUSY;
 869
 870                 if ((phy_control & BMCR_RESET) == 0) {
 871                         udelay(40);
 872                         break;
 873                 }
 874                 udelay(10);
 875         }
 876         if (limit < 0)
 877                 return -EBUSY;
 878
 879         return 0;
 880 }
 881
 882 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 883 {
 884         struct tg3 *tp = bp->priv;
 885         u32 val;
 886
 887         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 888                 return -EAGAIN;
 889
 890         if (tg3_readphy(tp, reg, &val))
 891                 return -EIO;
 892
 893         return val;
 894 }
 895
 896 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 897 {
 898         struct tg3 *tp = bp->priv;
 899
 900         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 901                 return -EAGAIN;
 902
 903         if (tg3_writephy(tp, reg, val))
 904                 return -EIO;
 905
 906         return 0;
 907 }
 908
 909 static int tg3_mdio_reset(struct mii_bus *bp)
 910 {
 911         return 0;
 912 }
 913
 914 static void tg3_mdio_config_5785(struct tg3 *tp)
 915 {
 916         u32 val;
 917         struct phy_device *phydev;
 918
 919         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 920         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 921         case TG3_PHY_ID_BCM50610:
 922                 val = MAC_PHYCFG2_50610_LED_MODES;
 923                 break;
 924         case TG3_PHY_ID_BCMAC131:
 925                 val = MAC_PHYCFG2_AC131_LED_MODES;
 926                 break;
 927         case TG3_PHY_ID_RTL8211C:
 928                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 929                 break;
 930         case TG3_PHY_ID_RTL8201E:
 931                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 932                 break;
 933         default:
 934                 return;
 935         }
 936
 937         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 938                 tw32(MAC_PHYCFG2, val);
 939
 940                 val = tr32(MAC_PHYCFG1);
 941                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 942                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 943                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 944                 tw32(MAC_PHYCFG1, val);
 945
 946                 return;
 947         }
 948
 949         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 950                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 951                        MAC_PHYCFG2_FMODE_MASK_MASK |
 952                        MAC_PHYCFG2_GMODE_MASK_MASK |
 953                        MAC_PHYCFG2_ACT_MASK_MASK   |
 954                        MAC_PHYCFG2_QUAL_MASK_MASK |
 955                        MAC_PHYCFG2_INBAND_ENABLE;
 956
 957         tw32(MAC_PHYCFG2, val);
 958
 959         val = tr32(MAC_PHYCFG1);
 960         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 961                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 962         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 963                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 964                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 965                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 966                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 967         }
 968         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 969                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 970         tw32(MAC_PHYCFG1, val);
 971
 972         val = tr32(MAC_EXT_RGMII_MODE);
 973         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 974                  MAC_RGMII_MODE_RX_QUALITY |
 975                  MAC_RGMII_MODE_RX_ACTIVITY |
 976                  MAC_RGMII_MODE_RX_ENG_DET |
 977                  MAC_RGMII_MODE_TX_ENABLE |
 978                  MAC_RGMII_MODE_TX_LOWPWR |
 979                  MAC_RGMII_MODE_TX_RESET);
 980         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 981                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 982                         val |= MAC_RGMII_MODE_RX_INT_B |
 983                                MAC_RGMII_MODE_RX_QUALITY |
 984                                MAC_RGMII_MODE_RX_ACTIVITY |
 985                                MAC_RGMII_MODE_RX_ENG_DET;
 986                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 987                         val |= MAC_RGMII_MODE_TX_ENABLE |
 988                                MAC_RGMII_MODE_TX_LOWPWR |
 989                                MAC_RGMII_MODE_TX_RESET;
 990         }
 991         tw32(MAC_EXT_RGMII_MODE, val);
 992 }
 993
 994 static void tg3_mdio_start(struct tg3 *tp)
 995 {
 996         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 997                 mutex_lock(&tp->mdio_bus->mdio_lock);
 998                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 999                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1000         }
1001
1002         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1003         tw32_f(MAC_MI_MODE, tp->mi_mode);
1004         udelay(80);
1005
1006         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1007             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1008                 tg3_mdio_config_5785(tp);
1009 }
1010
1011 static void tg3_mdio_stop(struct tg3 *tp)
1012 {
1013         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1014                 mutex_lock(&tp->mdio_bus->mdio_lock);
1015                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
1016                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1017         }
1018 }
1019
1020 static int tg3_mdio_init(struct tg3 *tp)
1021 {
1022         int i;
1023         u32 reg;
1024         struct phy_device *phydev;
1025
1026         tg3_mdio_start(tp);
1027
1028         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1029             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1030                 return 0;
1031
1032         tp->mdio_bus = mdiobus_alloc();
1033         if (tp->mdio_bus == NULL)
1034                 return -ENOMEM;
1035
1036         tp->mdio_bus->name     = "tg3 mdio bus";
1037         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1038                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1039         tp->mdio_bus->priv     = tp;
1040         tp->mdio_bus->parent   = &tp->pdev->dev;
1041         tp->mdio_bus->read     = &tg3_mdio_read;
1042         tp->mdio_bus->write    = &tg3_mdio_write;
1043         tp->mdio_bus->reset    = &tg3_mdio_reset;
1044         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1045         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1046
1047         for (i = 0; i < PHY_MAX_ADDR; i++)
1048                 tp->mdio_bus->irq[i] = PHY_POLL;
1049
1050         /* The bus registration will look for all the PHYs on the mdio bus.
1051          * Unfortunately, it does not ensure the PHY is powered up before
1052          * accessing the PHY ID registers.  A chip reset is the
1053          * quickest way to bring the device back to an operational state..
1054          */
1055         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1056                 tg3_bmcr_reset(tp);
1057
1058         i = mdiobus_register(tp->mdio_bus);
1059         if (i) {
1060                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1061                         tp->dev->name, i);
1062                 mdiobus_free(tp->mdio_bus);
1063                 return i;
1064         }
1065
1066         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1067
1068         if (!phydev || !phydev->drv) {
1069                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1070                 mdiobus_unregister(tp->mdio_bus);
1071                 mdiobus_free(tp->mdio_bus);
1072                 return -ENODEV;
1073         }
1074
1075         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1076         case TG3_PHY_ID_BCM57780:
1077                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1078                 break;
1079         case TG3_PHY_ID_BCM50610:
1080                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1081                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1082                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1083                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1084                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1085                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1086                 /* fallthru */
1087         case TG3_PHY_ID_RTL8211C:
1088                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1089                 break;
1090         case TG3_PHY_ID_RTL8201E:
1091         case TG3_PHY_ID_BCMAC131:
1092                 phydev->interface = PHY_INTERFACE_MODE_MII;
1093                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1094                 break;
1095         }
1096
1097         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1098
1099         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1100                 tg3_mdio_config_5785(tp);
1101
1102         return 0;
1103 }
1104
1105 static void tg3_mdio_fini(struct tg3 *tp)
1106 {
1107         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1108                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1109                 mdiobus_unregister(tp->mdio_bus);
1110                 mdiobus_free(tp->mdio_bus);
1111                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1112         }
1113 }
1114
1115 /* tp->lock is held. */
1116 static inline void tg3_generate_fw_event(struct tg3 *tp)
1117 {
1118         u32 val;
1119
1120         val = tr32(GRC_RX_CPU_EVENT);
1121         val |= GRC_RX_CPU_DRIVER_EVENT;
1122         tw32_f(GRC_RX_CPU_EVENT, val);
1123
1124         tp->last_event_jiffies = jiffies;
1125 }
1126
1127 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1128
1129 /* tp->lock is held. */
1130 static void tg3_wait_for_event_ack(struct tg3 *tp)
1131 {
1132         int i;
1133         unsigned int delay_cnt;
1134         long time_remain;
1135
1136         /* If enough time has passed, no wait is necessary. */
1137         time_remain = (long)(tp->last_event_jiffies + 1 +
1138                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1139                       (long)jiffies;
1140         if (time_remain < 0)
1141                 return;
1142
1143         /* Check if we can shorten the wait time. */
1144         delay_cnt = jiffies_to_usecs(time_remain);
1145         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1146                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1147         delay_cnt = (delay_cnt >> 3) + 1;
1148
1149         for (i = 0; i < delay_cnt; i++) {
1150                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1151                         break;
1152                 udelay(8);
1153         }
1154 }
1155
1156 /* tp->lock is held. */
1157 static void tg3_ump_link_report(struct tg3 *tp)
1158 {
1159         u32 reg;
1160         u32 val;
1161
1162         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1163             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1164                 return;
1165
1166         tg3_wait_for_event_ack(tp);
1167
1168         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1169
1170         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1171
1172         val = 0;
1173         if (!tg3_readphy(tp, MII_BMCR, &reg))
1174                 val = reg << 16;
1175         if (!tg3_readphy(tp, MII_BMSR, &reg))
1176                 val |= (reg & 0xffff);
1177         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1178
1179         val = 0;
1180         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1181                 val = reg << 16;
1182         if (!tg3_readphy(tp, MII_LPA, &reg))
1183                 val |= (reg & 0xffff);
1184         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1185
1186         val = 0;
1187         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1188                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1189                         val = reg << 16;
1190                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1191                         val |= (reg & 0xffff);
1192         }
1193         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1194
1195         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1196                 val = reg << 16;
1197         else
1198                 val = 0;
1199         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1200
1201         tg3_generate_fw_event(tp);
1202 }
1203
1204 static void tg3_link_report(struct tg3 *tp)
1205 {
1206         if (!netif_carrier_ok(tp->dev)) {
1207                 if (netif_msg_link(tp))
1208                         printk(KERN_INFO PFX "%s: Link is down.\n",
1209                                tp->dev->name);
1210                 tg3_ump_link_report(tp);
1211         } else if (netif_msg_link(tp)) {
1212                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1213                        tp->dev->name,
1214                        (tp->link_config.active_speed == SPEED_1000 ?
1215                         1000 :
1216                         (tp->link_config.active_speed == SPEED_100 ?
1217                          100 : 10)),
1218                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1219                         "full" : "half"));
1220
1221                 printk(KERN_INFO PFX
1222                        "%s: Flow control is %s for TX and %s for RX.\n",
1223                        tp->dev->name,
1224                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1225                        "on" : "off",
1226                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1227                        "on" : "off");
1228                 tg3_ump_link_report(tp);
1229         }
1230 }
1231
1232 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1233 {
1234         u16 miireg;
1235
1236         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1237                 miireg = ADVERTISE_PAUSE_CAP;
1238         else if (flow_ctrl & FLOW_CTRL_TX)
1239                 miireg = ADVERTISE_PAUSE_ASYM;
1240         else if (flow_ctrl & FLOW_CTRL_RX)
1241                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1242         else
1243                 miireg = 0;
1244
1245         return miireg;
1246 }
1247
1248 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1249 {
1250         u16 miireg;
1251
1252         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1253                 miireg = ADVERTISE_1000XPAUSE;
1254         else if (flow_ctrl & FLOW_CTRL_TX)
1255                 miireg = ADVERTISE_1000XPSE_ASYM;
1256         else if (flow_ctrl & FLOW_CTRL_RX)
1257                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1258         else
1259                 miireg = 0;
1260
1261         return miireg;
1262 }
1263
1264 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1265 {
1266         u8 cap = 0;
1267
1268         if (lcladv & ADVERTISE_1000XPAUSE) {
1269                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1270                         if (rmtadv & LPA_1000XPAUSE)
1271                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1272                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1273                                 cap = FLOW_CTRL_RX;
1274                 } else {
1275                         if (rmtadv & LPA_1000XPAUSE)
1276                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1277                 }
1278         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1279                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1280                         cap = FLOW_CTRL_TX;
1281         }
1282
1283         return cap;
1284 }
1285
1286 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1287 {
1288         u8 autoneg;
1289         u8 flowctrl = 0;
1290         u32 old_rx_mode = tp->rx_mode;
1291         u32 old_tx_mode = tp->tx_mode;
1292
1293         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1294                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1295         else
1296                 autoneg = tp->link_config.autoneg;
1297
1298         if (autoneg == AUTONEG_ENABLE &&
1299             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1300                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1301                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1302                 else
1303                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1304         } else
1305                 flowctrl = tp->link_config.flowctrl;
1306
1307         tp->link_config.active_flowctrl = flowctrl;
1308
1309         if (flowctrl & FLOW_CTRL_RX)
1310                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1311         else
1312                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1313
1314         if (old_rx_mode != tp->rx_mode)
1315                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1316
1317         if (flowctrl & FLOW_CTRL_TX)
1318                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1319         else
1320                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1321
1322         if (old_tx_mode != tp->tx_mode)
1323                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1324 }
1325
1326 static void tg3_adjust_link(struct net_device *dev)
1327 {
1328         u8 oldflowctrl, linkmesg = 0;
1329         u32 mac_mode, lcl_adv, rmt_adv;
1330         struct tg3 *tp = netdev_priv(dev);
1331         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1332
1333         spin_lock(&tp->lock);
1334
1335         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1336                                     MAC_MODE_HALF_DUPLEX);
1337
1338         oldflowctrl = tp->link_config.active_flowctrl;
1339
1340         if (phydev->link) {
1341                 lcl_adv = 0;
1342                 rmt_adv = 0;
1343
1344                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1345                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1346                 else
1347                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1348
1349                 if (phydev->duplex == DUPLEX_HALF)
1350                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1351                 else {
1352                         lcl_adv = tg3_advert_flowctrl_1000T(
1353                                   tp->link_config.flowctrl);
1354
1355                         if (phydev->pause)
1356                                 rmt_adv = LPA_PAUSE_CAP;
1357                         if (phydev->asym_pause)
1358                                 rmt_adv |= LPA_PAUSE_ASYM;
1359                 }
1360
1361                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1362         } else
1363                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1364
1365         if (mac_mode != tp->mac_mode) {
1366                 tp->mac_mode = mac_mode;
1367                 tw32_f(MAC_MODE, tp->mac_mode);
1368                 udelay(40);
1369         }
1370
1371         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1372                 if (phydev->speed == SPEED_10)
1373                         tw32(MAC_MI_STAT,
1374                              MAC_MI_STAT_10MBPS_MODE |
1375                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1376                 else
1377                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1378         }
1379
1380         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1381                 tw32(MAC_TX_LENGTHS,
1382                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1383                       (6 << TX_LENGTHS_IPG_SHIFT) |
1384                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1385         else
1386                 tw32(MAC_TX_LENGTHS,
1387                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1388                       (6 << TX_LENGTHS_IPG_SHIFT) |
1389                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1390
1391         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1392             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1393             phydev->speed != tp->link_config.active_speed ||
1394             phydev->duplex != tp->link_config.active_duplex ||
1395             oldflowctrl != tp->link_config.active_flowctrl)
1396             linkmesg = 1;
1397
1398         tp->link_config.active_speed = phydev->speed;
1399         tp->link_config.active_duplex = phydev->duplex;
1400
1401         spin_unlock(&tp->lock);
1402
1403         if (linkmesg)
1404                 tg3_link_report(tp);
1405 }
1406
1407 static int tg3_phy_init(struct tg3 *tp)
1408 {
1409         struct phy_device *phydev;
1410
1411         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1412                 return 0;
1413
1414         /* Bring the PHY back to a known state. */
1415         tg3_bmcr_reset(tp);
1416
1417         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1418
1419         /* Attach the MAC to the PHY. */
1420         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1421                              phydev->dev_flags, phydev->interface);
1422         if (IS_ERR(phydev)) {
1423                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1424                 return PTR_ERR(phydev);
1425         }
1426
1427         /* Mask with MAC supported features. */
1428         switch (phydev->interface) {
1429         case PHY_INTERFACE_MODE_GMII:
1430         case PHY_INTERFACE_MODE_RGMII:
1431                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1432                         phydev->supported &= (PHY_GBIT_FEATURES |
1433                                               SUPPORTED_Pause |
1434                                               SUPPORTED_Asym_Pause);
1435                         break;
1436                 }
1437                 /* fallthru */
1438         case PHY_INTERFACE_MODE_MII:
1439                 phydev->supported &= (PHY_BASIC_FEATURES |
1440                                       SUPPORTED_Pause |
1441                                       SUPPORTED_Asym_Pause);
1442                 break;
1443         default:
1444                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1445                 return -EINVAL;
1446         }
1447
1448         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1449
1450         phydev->advertising = phydev->supported;
1451
1452         return 0;
1453 }
1454
1455 static void tg3_phy_start(struct tg3 *tp)
1456 {
1457         struct phy_device *phydev;
1458
1459         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1460                 return;
1461
1462         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1463
1464         if (tp->link_config.phy_is_low_power) {
1465                 tp->link_config.phy_is_low_power = 0;
1466                 phydev->speed = tp->link_config.orig_speed;
1467                 phydev->duplex = tp->link_config.orig_duplex;
1468                 phydev->autoneg = tp->link_config.orig_autoneg;
1469                 phydev->advertising = tp->link_config.orig_advertising;
1470         }
1471
1472         phy_start(phydev);
1473
1474         phy_start_aneg(phydev);
1475 }
1476
1477 static void tg3_phy_stop(struct tg3 *tp)
1478 {
1479         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1480                 return;
1481
1482         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1483 }
1484
1485 static void tg3_phy_fini(struct tg3 *tp)
1486 {
1487         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1488                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1489                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1490         }
1491 }
1492
1493 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1494 {
1495         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1496         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1497 }
1498
1499 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1500 {
1501         u32 phytest;
1502
1503         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1504                 u32 phy;
1505
1506                 tg3_writephy(tp, MII_TG3_FET_TEST,
1507                              phytest | MII_TG3_FET_SHADOW_EN);
1508                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1509                         if (enable)
1510                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1511                         else
1512                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1513                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1514                 }
1515                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1516         }
1517 }
1518
1519 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1520 {
1521         u32 reg;
1522
1523         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1524                 return;
1525
1526         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1527                 tg3_phy_fet_toggle_apd(tp, enable);
1528                 return;
1529         }
1530
1531         reg = MII_TG3_MISC_SHDW_WREN |
1532               MII_TG3_MISC_SHDW_SCR5_SEL |
1533               MII_TG3_MISC_SHDW_SCR5_LPED |
1534               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1535               MII_TG3_MISC_SHDW_SCR5_SDTL |
1536               MII_TG3_MISC_SHDW_SCR5_C125OE;
1537         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1538                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1539
1540         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1541
1542
1543         reg = MII_TG3_MISC_SHDW_WREN |
1544               MII_TG3_MISC_SHDW_APD_SEL |
1545               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1546         if (enable)
1547                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1548
1549         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1550 }
1551
1552 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1553 {
1554         u32 phy;
1555
1556         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1557             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1558                 return;
1559
1560         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1561                 u32 ephy;
1562
1563                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1564                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1565
1566                         tg3_writephy(tp, MII_TG3_FET_TEST,
1567                                      ephy | MII_TG3_FET_SHADOW_EN);
1568                         if (!tg3_readphy(tp, reg, &phy)) {
1569                                 if (enable)
1570                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1571                                 else
1572                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1573                                 tg3_writephy(tp, reg, phy);
1574                         }
1575                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1576                 }
1577         } else {
1578                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1579                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1580                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1581                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1582                         if (enable)
1583                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1584                         else
1585                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1586                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1587                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1588                 }
1589         }
1590 }
1591
1592 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1593 {
1594         u32 val;
1595
1596         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1597                 return;
1598
1599         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1600             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1601                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1602                              (val | (1 << 15) | (1 << 4)));
1603 }
1604
1605 static void tg3_phy_apply_otp(struct tg3 *tp)
1606 {
1607         u32 otp, phy;
1608
1609         if (!tp->phy_otp)
1610                 return;
1611
1612         otp = tp->phy_otp;
1613
1614         /* Enable SM_DSP clock and tx 6dB coding. */
1615         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1616               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1617               MII_TG3_AUXCTL_ACTL_TX_6DB;
1618         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619
1620         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1621         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1622         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1623
1624         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1625               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1626         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1627
1628         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1629         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1630         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1631
1632         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1633         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1634
1635         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1636         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1637
1638         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1639               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1640         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1641
1642         /* Turn off SM_DSP clock. */
1643         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1644               MII_TG3_AUXCTL_ACTL_TX_6DB;
1645         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1646 }
1647
1648 static int tg3_wait_macro_done(struct tg3 *tp)
1649 {
1650         int limit = 100;
1651
1652         while (limit--) {
1653                 u32 tmp32;
1654
1655                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1656                         if ((tmp32 & 0x1000) == 0)
1657                                 break;
1658                 }
1659         }
1660         if (limit < 0)
1661                 return -EBUSY;
1662
1663         return 0;
1664 }
1665
1666 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1667 {
1668         static const u32 test_pat[4][6] = {
1669         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1670         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1671         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1672         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1673         };
1674         int chan;
1675
1676         for (chan = 0; chan < 4; chan++) {
1677                 int i;
1678
1679                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1680                              (chan * 0x2000) | 0x0200);
1681                 tg3_writephy(tp, 0x16, 0x0002);
1682
1683                 for (i = 0; i < 6; i++)
1684                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1685                                      test_pat[chan][i]);
1686
1687                 tg3_writephy(tp, 0x16, 0x0202);
1688                 if (tg3_wait_macro_done(tp)) {
1689                         *resetp = 1;
1690                         return -EBUSY;
1691                 }
1692
1693                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1694                              (chan * 0x2000) | 0x0200);
1695                 tg3_writephy(tp, 0x16, 0x0082);
1696                 if (tg3_wait_macro_done(tp)) {
1697                         *resetp = 1;
1698                         return -EBUSY;
1699                 }
1700
1701                 tg3_writephy(tp, 0x16, 0x0802);
1702                 if (tg3_wait_macro_done(tp)) {
1703                         *resetp = 1;
1704                         return -EBUSY;
1705                 }
1706
1707                 for (i = 0; i < 6; i += 2) {
1708                         u32 low, high;
1709
1710                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1711                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1712                             tg3_wait_macro_done(tp)) {
1713                                 *resetp = 1;
1714                                 return -EBUSY;
1715                         }
1716                         low &= 0x7fff;
1717                         high &= 0x000f;
1718                         if (low != test_pat[chan][i] ||
1719                             high != test_pat[chan][i+1]) {
1720                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1721                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1722                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1723
1724                                 return -EBUSY;
1725                         }
1726                 }
1727         }
1728
1729         return 0;
1730 }
1731
1732 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1733 {
1734         int chan;
1735
1736         for (chan = 0; chan < 4; chan++) {
1737                 int i;
1738
1739                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1740                              (chan * 0x2000) | 0x0200);
1741                 tg3_writephy(tp, 0x16, 0x0002);
1742                 for (i = 0; i < 6; i++)
1743                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1744                 tg3_writephy(tp, 0x16, 0x0202);
1745                 if (tg3_wait_macro_done(tp))
1746                         return -EBUSY;
1747         }
1748
1749         return 0;
1750 }
1751
1752 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1753 {
1754         u32 reg32, phy9_orig;
1755         int retries, do_phy_reset, err;
1756
1757         retries = 10;
1758         do_phy_reset = 1;
1759         do {
1760                 if (do_phy_reset) {
1761                         err = tg3_bmcr_reset(tp);
1762                         if (err)
1763                                 return err;
1764                         do_phy_reset = 0;
1765                 }
1766
1767                 /* Disable transmitter and interrupt.  */
1768                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1769                         continue;
1770
1771                 reg32 |= 0x3000;
1772                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1773
1774                 /* Set full-duplex, 1000 mbps.  */
1775                 tg3_writephy(tp, MII_BMCR,
1776                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1777
1778                 /* Set to master mode.  */
1779                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1780                         continue;
1781
1782                 tg3_writephy(tp, MII_TG3_CTRL,
1783                              (MII_TG3_CTRL_AS_MASTER |
1784                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1785
1786                 /* Enable SM_DSP_CLOCK and 6dB.  */
1787                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1788
1789                 /* Block the PHY control access.  */
1790                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1791                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1792
1793                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1794                 if (!err)
1795                         break;
1796         } while (--retries);
1797
1798         err = tg3_phy_reset_chanpat(tp);
1799         if (err)
1800                 return err;
1801
1802         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1803         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1804
1805         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1806         tg3_writephy(tp, 0x16, 0x0000);
1807
1808         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1809             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1810                 /* Set Extended packet length bit for jumbo frames */
1811                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1812         }
1813         else {
1814                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1815         }
1816
1817         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1818
1819         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1820                 reg32 &= ~0x3000;
1821                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1822         } else if (!err)
1823                 err = -EBUSY;
1824
1825         return err;
1826 }
1827
1828 /* This will reset the tigon3 PHY if there is no valid
1829  * link unless the FORCE argument is non-zero.
1830  */
1831 static int tg3_phy_reset(struct tg3 *tp)
1832 {
1833         u32 cpmuctrl;
1834         u32 phy_status;
1835         int err;
1836
1837         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1838                 u32 val;
1839
1840                 val = tr32(GRC_MISC_CFG);
1841                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1842                 udelay(40);
1843         }
1844         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1845         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1846         if (err != 0)
1847                 return -EBUSY;
1848
1849         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1850                 netif_carrier_off(tp->dev);
1851                 tg3_link_report(tp);
1852         }
1853
1854         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1855             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1856             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1857                 err = tg3_phy_reset_5703_4_5(tp);
1858                 if (err)
1859                         return err;
1860                 goto out;
1861         }
1862
1863         cpmuctrl = 0;
1864         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1865             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1866                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1867                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1868                         tw32(TG3_CPMU_CTRL,
1869                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1870         }
1871
1872         err = tg3_bmcr_reset(tp);
1873         if (err)
1874                 return err;
1875
1876         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1877                 u32 phy;
1878
1879                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1880                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1881
1882                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1883         }
1884
1885         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1886             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1887                 u32 val;
1888
1889                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1890                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1891                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1892                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1893                         udelay(40);
1894                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1895                 }
1896         }
1897
1898         tg3_phy_apply_otp(tp);
1899
1900         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1901                 tg3_phy_toggle_apd(tp, true);
1902         else
1903                 tg3_phy_toggle_apd(tp, false);
1904
1905 out:
1906         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1907                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1908                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1909                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1911                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1912                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1913         }
1914         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1915                 tg3_writephy(tp, 0x1c, 0x8d68);
1916                 tg3_writephy(tp, 0x1c, 0x8d68);
1917         }
1918         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1919                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1920                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1921                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1922                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1923                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1924                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1925                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1926                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1927         }
1928         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1929                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1930                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1931                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1932                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1933                         tg3_writephy(tp, MII_TG3_TEST1,
1934                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1935                 } else
1936                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1937                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1938         }
1939         /* Set Extended packet length bit (bit 14) on all chips that */
1940         /* support jumbo frames */
1941         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1942                 /* Cannot do read-modify-write on 5401 */
1943                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1944         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1945                 u32 phy_reg;
1946
1947                 /* Set bit 14 with read-modify-write to preserve other bits */
1948                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1949                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1950                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1951         }
1952
1953         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1954          * jumbo frames transmission.
1955          */
1956         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1957                 u32 phy_reg;
1958
1959                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1960                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1961                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1962         }
1963
1964         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1965                 /* adjust output voltage */
1966                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1967         }
1968
1969         tg3_phy_toggle_automdix(tp, 1);
1970         tg3_phy_set_wirespeed(tp);
1971         return 0;
1972 }
1973
1974 static void tg3_frob_aux_power(struct tg3 *tp)
1975 {
1976         struct tg3 *tp_peer = tp;
1977
1978         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1979                 return;
1980
1981         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1982             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1983                 struct net_device *dev_peer;
1984
1985                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1986                 /* remove_one() may have been run on the peer. */
1987                 if (!dev_peer)
1988                         tp_peer = tp;
1989                 else
1990                         tp_peer = netdev_priv(dev_peer);
1991         }
1992
1993         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1994             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1995             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1996             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1997                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1998                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1999                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2000                                     (GRC_LCLCTRL_GPIO_OE0 |
2001                                      GRC_LCLCTRL_GPIO_OE1 |
2002                                      GRC_LCLCTRL_GPIO_OE2 |
2003                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2004                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2005                                     100);
2006                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2007                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2008                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2009                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2010                                              GRC_LCLCTRL_GPIO_OE1 |
2011                                              GRC_LCLCTRL_GPIO_OE2 |
2012                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2013                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2014                                              tp->grc_local_ctrl;
2015                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2016
2017                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2018                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2019
2020                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2021                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2022                 } else {
2023                         u32 no_gpio2;
2024                         u32 grc_local_ctrl = 0;
2025
2026                         if (tp_peer != tp &&
2027                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2028                                 return;
2029
2030                         /* Workaround to prevent overdrawing Amps. */
2031                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2032                             ASIC_REV_5714) {
2033                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2034                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2035                                             grc_local_ctrl, 100);
2036                         }
2037
2038                         /* On 5753 and variants, GPIO2 cannot be used. */
2039                         no_gpio2 = tp->nic_sram_data_cfg &
2040                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2041
2042                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2043                                          GRC_LCLCTRL_GPIO_OE1 |
2044                                          GRC_LCLCTRL_GPIO_OE2 |
2045                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2046                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2047                         if (no_gpio2) {
2048                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2049                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2050                         }
2051                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2052                                                     grc_local_ctrl, 100);
2053
2054                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2055
2056                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2057                                                     grc_local_ctrl, 100);
2058
2059                         if (!no_gpio2) {
2060                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2061                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2062                                             grc_local_ctrl, 100);
2063                         }
2064                 }
2065         } else {
2066                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2067                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2068                         if (tp_peer != tp &&
2069                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2070                                 return;
2071
2072                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2073                                     (GRC_LCLCTRL_GPIO_OE1 |
2074                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2075
2076                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2077                                     GRC_LCLCTRL_GPIO_OE1, 100);
2078
2079                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2080                                     (GRC_LCLCTRL_GPIO_OE1 |
2081                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2082                 }
2083         }
2084 }
2085
2086 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2087 {
2088         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2089                 return 1;
2090         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2091                 if (speed != SPEED_10)
2092                         return 1;
2093         } else if (speed == SPEED_10)
2094                 return 1;
2095
2096         return 0;
2097 }
2098
2099 static int tg3_setup_phy(struct tg3 *, int);
2100
2101 #define RESET_KIND_SHUTDOWN     0
2102 #define RESET_KIND_INIT         1
2103 #define RESET_KIND_SUSPEND      2
2104
2105 static void tg3_write_sig_post_reset(struct tg3 *, int);
2106 static int tg3_halt_cpu(struct tg3 *, u32);
2107
2108 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2109 {
2110         u32 val;
2111
2112         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2113                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2114                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2115                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2116
2117                         sg_dig_ctrl |=
2118                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2119                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2120                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2121                 }
2122                 return;
2123         }
2124
2125         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2126                 tg3_bmcr_reset(tp);
2127                 val = tr32(GRC_MISC_CFG);
2128                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2129                 udelay(40);
2130                 return;
2131         } else if (do_low_power) {
2132                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2133                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2134
2135                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2136                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2137                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2138                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2139                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2140         }
2141
2142         /* The PHY should not be powered down on some chips because
2143          * of bugs.
2144          */
2145         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2146             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2147             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2148              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2149                 return;
2150
2151         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2152             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2153                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2154                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2155                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2156                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2157         }
2158
2159         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2160 }
2161
2162 /* tp->lock is held. */
2163 static int tg3_nvram_lock(struct tg3 *tp)
2164 {
2165         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2166                 int i;
2167
2168                 if (tp->nvram_lock_cnt == 0) {
2169                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2170                         for (i = 0; i < 8000; i++) {
2171                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2172                                         break;
2173                                 udelay(20);
2174                         }
2175                         if (i == 8000) {
2176                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2177                                 return -ENODEV;
2178                         }
2179                 }
2180                 tp->nvram_lock_cnt++;
2181         }
2182         return 0;
2183 }
2184
2185 /* tp->lock is held. */
2186 static void tg3_nvram_unlock(struct tg3 *tp)
2187 {
2188         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2189                 if (tp->nvram_lock_cnt > 0)
2190                         tp->nvram_lock_cnt--;
2191                 if (tp->nvram_lock_cnt == 0)
2192                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2193         }
2194 }
2195
2196 /* tp->lock is held. */
2197 static void tg3_enable_nvram_access(struct tg3 *tp)
2198 {
2199         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2200             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2201                 u32 nvaccess = tr32(NVRAM_ACCESS);
2202
2203                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2204         }
2205 }
2206
2207 /* tp->lock is held. */
2208 static void tg3_disable_nvram_access(struct tg3 *tp)
2209 {
2210         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2211             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2212                 u32 nvaccess = tr32(NVRAM_ACCESS);
2213
2214                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2215         }
2216 }
2217
2218 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2219                                         u32 offset, u32 *val)
2220 {
2221         u32 tmp;
2222         int i;
2223
2224         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2225                 return -EINVAL;
2226
2227         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2228                                         EEPROM_ADDR_DEVID_MASK |
2229                                         EEPROM_ADDR_READ);
2230         tw32(GRC_EEPROM_ADDR,
2231              tmp |
2232              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2233              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2234               EEPROM_ADDR_ADDR_MASK) |
2235              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2236
2237         for (i = 0; i < 1000; i++) {
2238                 tmp = tr32(GRC_EEPROM_ADDR);
2239
2240                 if (tmp & EEPROM_ADDR_COMPLETE)
2241                         break;
2242                 msleep(1);
2243         }
2244         if (!(tmp & EEPROM_ADDR_COMPLETE))
2245                 return -EBUSY;
2246
2247         tmp = tr32(GRC_EEPROM_DATA);
2248
2249         /*
2250          * The data will always be opposite the native endian
2251          * format.  Perform a blind byteswap to compensate.
2252          */
2253         *val = swab32(tmp);
2254
2255         return 0;
2256 }
2257
2258 #define NVRAM_CMD_TIMEOUT 10000
2259
2260 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2261 {
2262         int i;
2263
2264         tw32(NVRAM_CMD, nvram_cmd);
2265         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2266                 udelay(10);
2267                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2268                         udelay(10);
2269                         break;
2270                 }
2271         }
2272
2273         if (i == NVRAM_CMD_TIMEOUT)
2274                 return -EBUSY;
2275
2276         return 0;
2277 }
2278
2279 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2280 {
2281         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2282             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2283             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2284            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2285             (tp->nvram_jedecnum == JEDEC_ATMEL))
2286
2287                 addr = ((addr / tp->nvram_pagesize) <<
2288                         ATMEL_AT45DB0X1B_PAGE_POS) +
2289                        (addr % tp->nvram_pagesize);
2290
2291         return addr;
2292 }
2293
2294 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2295 {
2296         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2297             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2298             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2299            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2300             (tp->nvram_jedecnum == JEDEC_ATMEL))
2301
2302                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2303                         tp->nvram_pagesize) +
2304                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2305
2306         return addr;
2307 }
2308
2309 /* NOTE: Data read in from NVRAM is byteswapped according to
2310  * the byteswapping settings for all other register accesses.
2311  * tg3 devices are BE devices, so on a BE machine, the data
2312  * returned will be exactly as it is seen in NVRAM.  On a LE
2313  * machine, the 32-bit value will be byteswapped.
2314  */
2315 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2316 {
2317         int ret;
2318
2319         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2320                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2321
2322         offset = tg3_nvram_phys_addr(tp, offset);
2323
2324         if (offset > NVRAM_ADDR_MSK)
2325                 return -EINVAL;
2326
2327         ret = tg3_nvram_lock(tp);
2328         if (ret)
2329                 return ret;
2330
2331         tg3_enable_nvram_access(tp);
2332
2333         tw32(NVRAM_ADDR, offset);
2334         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2335                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2336
2337         if (ret == 0)
2338                 *val = tr32(NVRAM_RDDATA);
2339
2340         tg3_disable_nvram_access(tp);
2341
2342         tg3_nvram_unlock(tp);
2343
2344         return ret;
2345 }
2346
2347 /* Ensures NVRAM data is in bytestream format. */
2348 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2349 {
2350         u32 v;
2351         int res = tg3_nvram_read(tp, offset, &v);
2352         if (!res)
2353                 *val = cpu_to_be32(v);
2354         return res;
2355 }
2356
2357 /* tp->lock is held. */
2358 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2359 {
2360         u32 addr_high, addr_low;
2361         int i;
2362
2363         addr_high = ((tp->dev->dev_addr[0] << 8) |
2364                      tp->dev->dev_addr[1]);
2365         addr_low = ((tp->dev->dev_addr[2] << 24) |
2366                     (tp->dev->dev_addr[3] << 16) |
2367                     (tp->dev->dev_addr[4] <<  8) |
2368                     (tp->dev->dev_addr[5] <<  0));
2369         for (i = 0; i < 4; i++) {
2370                 if (i == 1 && skip_mac_1)
2371                         continue;
2372                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2373                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2374         }
2375
2376         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2377             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2378                 for (i = 0; i < 12; i++) {
2379                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2380                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2381                 }
2382         }
2383
2384         addr_high = (tp->dev->dev_addr[0] +
2385                      tp->dev->dev_addr[1] +
2386                      tp->dev->dev_addr[2] +
2387                      tp->dev->dev_addr[3] +
2388                      tp->dev->dev_addr[4] +
2389                      tp->dev->dev_addr[5]) &
2390                 TX_BACKOFF_SEED_MASK;
2391         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2392 }
2393
2394 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2395 {
2396         u32 misc_host_ctrl;
2397         bool device_should_wake, do_low_power;
2398
2399         /* Make sure register accesses (indirect or otherwise)
2400          * will function correctly.
2401          */
2402         pci_write_config_dword(tp->pdev,
2403                                TG3PCI_MISC_HOST_CTRL,
2404                                tp->misc_host_ctrl);
2405
2406         switch (state) {
2407         case PCI_D0:
2408                 pci_enable_wake(tp->pdev, state, false);
2409                 pci_set_power_state(tp->pdev, PCI_D0);
2410
2411                 /* Switch out of Vaux if it is a NIC */
2412                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2413                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2414
2415                 return 0;
2416
2417         case PCI_D1:
2418         case PCI_D2:
2419         case PCI_D3hot:
2420                 break;
2421
2422         default:
2423                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2424                         tp->dev->name, state);
2425                 return -EINVAL;
2426         }
2427
2428         /* Restore the CLKREQ setting. */
2429         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2430                 u16 lnkctl;
2431
2432                 pci_read_config_word(tp->pdev,
2433                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2434                                      &lnkctl);
2435                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2436                 pci_write_config_word(tp->pdev,
2437                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2438                                       lnkctl);
2439         }
2440
2441         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2442         tw32(TG3PCI_MISC_HOST_CTRL,
2443              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2444
2445         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2446                              device_may_wakeup(&tp->pdev->dev) &&
2447                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2448
2449         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2450                 do_low_power = false;
2451                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2452                     !tp->link_config.phy_is_low_power) {
2453                         struct phy_device *phydev;
2454                         u32 phyid, advertising;
2455
2456                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2457
2458                         tp->link_config.phy_is_low_power = 1;
2459
2460                         tp->link_config.orig_speed = phydev->speed;
2461                         tp->link_config.orig_duplex = phydev->duplex;
2462                         tp->link_config.orig_autoneg = phydev->autoneg;
2463                         tp->link_config.orig_advertising = phydev->advertising;
2464
2465                         advertising = ADVERTISED_TP |
2466                                       ADVERTISED_Pause |
2467                                       ADVERTISED_Autoneg |
2468                                       ADVERTISED_10baseT_Half;
2469
2470                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2471                             device_should_wake) {
2472                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2473                                         advertising |=
2474                                                 ADVERTISED_100baseT_Half |
2475                                                 ADVERTISED_100baseT_Full |
2476                                                 ADVERTISED_10baseT_Full;
2477                                 else
2478                                         advertising |= ADVERTISED_10baseT_Full;
2479                         }
2480
2481                         phydev->advertising = advertising;
2482
2483                         phy_start_aneg(phydev);
2484
2485                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2486                         if (phyid != TG3_PHY_ID_BCMAC131) {
2487                                 phyid &= TG3_PHY_OUI_MASK;
2488                                 if (phyid == TG3_PHY_OUI_1 ||
2489                                     phyid == TG3_PHY_OUI_2 ||
2490                                     phyid == TG3_PHY_OUI_3)
2491                                         do_low_power = true;
2492                         }
2493                 }
2494         } else {
2495                 do_low_power = true;
2496
2497                 if (tp->link_config.phy_is_low_power == 0) {
2498                         tp->link_config.phy_is_low_power = 1;
2499                         tp->link_config.orig_speed = tp->link_config.speed;
2500                         tp->link_config.orig_duplex = tp->link_config.duplex;
2501                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2502                 }
2503
2504                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2505                         tp->link_config.speed = SPEED_10;
2506                         tp->link_config.duplex = DUPLEX_HALF;
2507                         tp->link_config.autoneg = AUTONEG_ENABLE;
2508                         tg3_setup_phy(tp, 0);
2509                 }
2510         }
2511
2512         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2513                 u32 val;
2514
2515                 val = tr32(GRC_VCPU_EXT_CTRL);
2516                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2517         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2518                 int i;
2519                 u32 val;
2520
2521                 for (i = 0; i < 200; i++) {
2522                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2523                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2524                                 break;
2525                         msleep(1);
2526                 }
2527         }
2528         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2529                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2530                                                      WOL_DRV_STATE_SHUTDOWN |
2531                                                      WOL_DRV_WOL |
2532                                                      WOL_SET_MAGIC_PKT);
2533
2534         if (device_should_wake) {
2535                 u32 mac_mode;
2536
2537                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2538                         if (do_low_power) {
2539                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2540                                 udelay(40);
2541                         }
2542
2543                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2544                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2545                         else
2546                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2547
2548                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2549                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2550                             ASIC_REV_5700) {
2551                                 u32 speed = (tp->tg3_flags &
2552                                              TG3_FLAG_WOL_SPEED_100MB) ?
2553                                              SPEED_100 : SPEED_10;
2554                                 if (tg3_5700_link_polarity(tp, speed))
2555                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2556                                 else
2557                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2558                         }
2559                 } else {
2560                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2561                 }
2562
2563                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2564                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2565
2566                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2567                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2568                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2569                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2570                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2571                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2572
2573                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2574                         mac_mode |= tp->mac_mode &
2575                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2576                         if (mac_mode & MAC_MODE_APE_TX_EN)
2577                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2578                 }
2579
2580                 tw32_f(MAC_MODE, mac_mode);
2581                 udelay(100);
2582
2583                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2584                 udelay(10);
2585         }
2586
2587         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2588             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2589              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2590                 u32 base_val;
2591
2592                 base_val = tp->pci_clock_ctrl;
2593                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2594                              CLOCK_CTRL_TXCLK_DISABLE);
2595
2596                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2597                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2598         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2599                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2600                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2601                 /* do nothing */
2602         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2603                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2604                 u32 newbits1, newbits2;
2605
2606                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2607                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2608                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2609                                     CLOCK_CTRL_TXCLK_DISABLE |
2610                                     CLOCK_CTRL_ALTCLK);
2611                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2612                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2613                         newbits1 = CLOCK_CTRL_625_CORE;
2614                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2615                 } else {
2616                         newbits1 = CLOCK_CTRL_ALTCLK;
2617                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2618                 }
2619
2620                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2621                             40);
2622
2623                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2624                             40);
2625
2626                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2627                         u32 newbits3;
2628
2629                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2630                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2631                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2632                                             CLOCK_CTRL_TXCLK_DISABLE |
2633                                             CLOCK_CTRL_44MHZ_CORE);
2634                         } else {
2635                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2636                         }
2637
2638                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2639                                     tp->pci_clock_ctrl | newbits3, 40);
2640                 }
2641         }
2642
2643         if (!(device_should_wake) &&
2644             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2645                 tg3_power_down_phy(tp, do_low_power);
2646
2647         tg3_frob_aux_power(tp);
2648
2649         /* Workaround for unstable PLL clock */
2650         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2651             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2652                 u32 val = tr32(0x7d00);
2653
2654                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2655                 tw32(0x7d00, val);
2656                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2657                         int err;
2658
2659                         err = tg3_nvram_lock(tp);
2660                         tg3_halt_cpu(tp, RX_CPU_BASE);
2661                         if (!err)
2662                                 tg3_nvram_unlock(tp);
2663                 }
2664         }
2665
2666         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2667
2668         if (device_should_wake)
2669                 pci_enable_wake(tp->pdev, state, true);
2670
2671         /* Finally, set the new power state. */
2672         pci_set_power_state(tp->pdev, state);
2673
2674         return 0;
2675 }
2676
2677 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2678 {
2679         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2680         case MII_TG3_AUX_STAT_10HALF:
2681                 *speed = SPEED_10;
2682                 *duplex = DUPLEX_HALF;
2683                 break;
2684
2685         case MII_TG3_AUX_STAT_10FULL:
2686                 *speed = SPEED_10;
2687                 *duplex = DUPLEX_FULL;
2688                 break;
2689
2690         case MII_TG3_AUX_STAT_100HALF:
2691                 *speed = SPEED_100;
2692                 *duplex = DUPLEX_HALF;
2693                 break;
2694
2695         case MII_TG3_AUX_STAT_100FULL:
2696                 *speed = SPEED_100;
2697                 *duplex = DUPLEX_FULL;
2698                 break;
2699
2700         case MII_TG3_AUX_STAT_1000HALF:
2701                 *speed = SPEED_1000;
2702                 *duplex = DUPLEX_HALF;
2703                 break;
2704
2705         case MII_TG3_AUX_STAT_1000FULL:
2706                 *speed = SPEED_1000;
2707                 *duplex = DUPLEX_FULL;
2708                 break;
2709
2710         default:
2711                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2712                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2713                                  SPEED_10;
2714                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2715                                   DUPLEX_HALF;
2716                         break;
2717                 }
2718                 *speed = SPEED_INVALID;
2719                 *duplex = DUPLEX_INVALID;
2720                 break;
2721         }
2722 }
2723
2724 static void tg3_phy_copper_begin(struct tg3 *tp)
2725 {
2726         u32 new_adv;
2727         int i;
2728
2729         if (tp->link_config.phy_is_low_power) {
2730                 /* Entering low power mode.  Disable gigabit and
2731                  * 100baseT advertisements.
2732                  */
2733                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2734
2735                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2736                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2737                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2738                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2739
2740                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2741         } else if (tp->link_config.speed == SPEED_INVALID) {
2742                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2743                         tp->link_config.advertising &=
2744                                 ~(ADVERTISED_1000baseT_Half |
2745                                   ADVERTISED_1000baseT_Full);
2746
2747                 new_adv = ADVERTISE_CSMA;
2748                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2749                         new_adv |= ADVERTISE_10HALF;
2750                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2751                         new_adv |= ADVERTISE_10FULL;
2752                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2753                         new_adv |= ADVERTISE_100HALF;
2754                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2755                         new_adv |= ADVERTISE_100FULL;
2756
2757                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2758
2759                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2760
2761                 if (tp->link_config.advertising &
2762                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2763                         new_adv = 0;
2764                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2765                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2766                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2767                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2768                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2769                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2770                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2771                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2772                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2773                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2774                 } else {
2775                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2776                 }
2777         } else {
2778                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2779                 new_adv |= ADVERTISE_CSMA;
2780
2781                 /* Asking for a specific link mode. */
2782                 if (tp->link_config.speed == SPEED_1000) {
2783                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2784
2785                         if (tp->link_config.duplex == DUPLEX_FULL)
2786                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2787                         else
2788                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2789                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2790                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2791                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2792                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2793                 } else {
2794                         if (tp->link_config.speed == SPEED_100) {
2795                                 if (tp->link_config.duplex == DUPLEX_FULL)
2796                                         new_adv |= ADVERTISE_100FULL;
2797                                 else
2798                                         new_adv |= ADVERTISE_100HALF;
2799                         } else {
2800                                 if (tp->link_config.duplex == DUPLEX_FULL)
2801                                         new_adv |= ADVERTISE_10FULL;
2802                                 else
2803                                         new_adv |= ADVERTISE_10HALF;
2804                         }
2805                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2806
2807                         new_adv = 0;
2808                 }
2809
2810                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2811         }
2812
2813         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2814             tp->link_config.speed != SPEED_INVALID) {
2815                 u32 bmcr, orig_bmcr;
2816
2817                 tp->link_config.active_speed = tp->link_config.speed;
2818                 tp->link_config.active_duplex = tp->link_config.duplex;
2819
2820                 bmcr = 0;
2821                 switch (tp->link_config.speed) {
2822                 default:
2823                 case SPEED_10:
2824                         break;
2825
2826                 case SPEED_100:
2827                         bmcr |= BMCR_SPEED100;
2828                         break;
2829
2830                 case SPEED_1000:
2831                         bmcr |= TG3_BMCR_SPEED1000;
2832                         break;
2833                 }
2834
2835                 if (tp->link_config.duplex == DUPLEX_FULL)
2836                         bmcr |= BMCR_FULLDPLX;
2837
2838                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2839                     (bmcr != orig_bmcr)) {
2840                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2841                         for (i = 0; i < 1500; i++) {
2842                                 u32 tmp;
2843
2844                                 udelay(10);
2845                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2846                                     tg3_readphy(tp, MII_BMSR, &tmp))
2847                                         continue;
2848                                 if (!(tmp & BMSR_LSTATUS)) {
2849                                         udelay(40);
2850                                         break;
2851                                 }
2852                         }
2853                         tg3_writephy(tp, MII_BMCR, bmcr);
2854                         udelay(40);
2855                 }
2856         } else {
2857                 tg3_writephy(tp, MII_BMCR,
2858                              BMCR_ANENABLE | BMCR_ANRESTART);
2859         }
2860 }
2861
2862 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2863 {
2864         int err;
2865
2866         /* Turn off tap power management. */
2867         /* Set Extended packet length bit */
2868         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2869
2870         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2871         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2872
2873         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2874         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2875
2876         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2877         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2878
2879         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2880         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2881
2882         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2883         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2884
2885         udelay(40);
2886
2887         return err;
2888 }
2889
2890 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2891 {
2892         u32 adv_reg, all_mask = 0;
2893
2894         if (mask & ADVERTISED_10baseT_Half)
2895                 all_mask |= ADVERTISE_10HALF;
2896         if (mask & ADVERTISED_10baseT_Full)
2897                 all_mask |= ADVERTISE_10FULL;
2898         if (mask & ADVERTISED_100baseT_Half)
2899                 all_mask |= ADVERTISE_100HALF;
2900         if (mask & ADVERTISED_100baseT_Full)
2901                 all_mask |= ADVERTISE_100FULL;
2902
2903         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2904                 return 0;
2905
2906         if ((adv_reg & all_mask) != all_mask)
2907                 return 0;
2908         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2909                 u32 tg3_ctrl;
2910
2911                 all_mask = 0;
2912                 if (mask & ADVERTISED_1000baseT_Half)
2913                         all_mask |= ADVERTISE_1000HALF;
2914                 if (mask & ADVERTISED_1000baseT_Full)
2915                         all_mask |= ADVERTISE_1000FULL;
2916
2917                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2918                         return 0;
2919
2920                 if ((tg3_ctrl & all_mask) != all_mask)
2921                         return 0;
2922         }
2923         return 1;
2924 }
2925
2926 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2927 {
2928         u32 curadv, reqadv;
2929
2930         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2931                 return 1;
2932
2933         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2934         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2935
2936         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2937                 if (curadv != reqadv)
2938                         return 0;
2939
2940                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2941                         tg3_readphy(tp, MII_LPA, rmtadv);
2942         } else {
2943                 /* Reprogram the advertisement register, even if it
2944                  * does not affect the current link.  If the link
2945                  * gets renegotiated in the future, we can save an
2946                  * additional renegotiation cycle by advertising
2947                  * it correctly in the first place.
2948                  */
2949                 if (curadv != reqadv) {
2950                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2951                                      ADVERTISE_PAUSE_ASYM);
2952                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2953                 }
2954         }
2955
2956         return 1;
2957 }
2958
2959 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2960 {
2961         int current_link_up;
2962         u32 bmsr, dummy;
2963         u32 lcl_adv, rmt_adv;
2964         u16 current_speed;
2965         u8 current_duplex;
2966         int i, err;
2967
2968         tw32(MAC_EVENT, 0);
2969
2970         tw32_f(MAC_STATUS,
2971              (MAC_STATUS_SYNC_CHANGED |
2972               MAC_STATUS_CFG_CHANGED |
2973               MAC_STATUS_MI_COMPLETION |
2974               MAC_STATUS_LNKSTATE_CHANGED));
2975         udelay(40);
2976
2977         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2978                 tw32_f(MAC_MI_MODE,
2979                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2980                 udelay(80);
2981         }
2982
2983         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2984
2985         /* Some third-party PHYs need to be reset on link going
2986          * down.
2987          */
2988         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2989              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2990              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2991             netif_carrier_ok(tp->dev)) {
2992                 tg3_readphy(tp, MII_BMSR, &bmsr);
2993                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2994                     !(bmsr & BMSR_LSTATUS))
2995                         force_reset = 1;
2996         }
2997         if (force_reset)
2998                 tg3_phy_reset(tp);
2999
3000         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3001                 tg3_readphy(tp, MII_BMSR, &bmsr);
3002                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3003                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3004                         bmsr = 0;
3005
3006                 if (!(bmsr & BMSR_LSTATUS)) {
3007                         err = tg3_init_5401phy_dsp(tp);
3008                         if (err)
3009                                 return err;
3010
3011                         tg3_readphy(tp, MII_BMSR, &bmsr);
3012                         for (i = 0; i < 1000; i++) {
3013                                 udelay(10);
3014                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3015                                     (bmsr & BMSR_LSTATUS)) {
3016                                         udelay(40);
3017                                         break;
3018                                 }
3019                         }
3020
3021                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3022                             !(bmsr & BMSR_LSTATUS) &&
3023                             tp->link_config.active_speed == SPEED_1000) {
3024                                 err = tg3_phy_reset(tp);
3025                                 if (!err)
3026                                         err = tg3_init_5401phy_dsp(tp);
3027                                 if (err)
3028                                         return err;
3029                         }
3030                 }
3031         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3032                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3033                 /* 5701 {A0,B0} CRC bug workaround */
3034                 tg3_writephy(tp, 0x15, 0x0a75);
3035                 tg3_writephy(tp, 0x1c, 0x8c68);
3036                 tg3_writephy(tp, 0x1c, 0x8d68);
3037                 tg3_writephy(tp, 0x1c, 0x8c68);
3038         }
3039
3040         /* Clear pending interrupts... */
3041         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3042         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3043
3044         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3045                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3046         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3047                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3048
3049         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3050             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3051                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3052                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3053                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3054                 else
3055                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3056         }
3057
3058         current_link_up = 0;
3059         current_speed = SPEED_INVALID;
3060         current_duplex = DUPLEX_INVALID;
3061
3062         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3063                 u32 val;
3064
3065                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3066                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3067                 if (!(val & (1 << 10))) {
3068                         val |= (1 << 10);
3069                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3070                         goto relink;
3071                 }
3072         }
3073
3074         bmsr = 0;
3075         for (i = 0; i < 100; i++) {
3076                 tg3_readphy(tp, MII_BMSR, &bmsr);
3077                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3078                     (bmsr & BMSR_LSTATUS))
3079                         break;
3080                 udelay(40);
3081         }
3082
3083         if (bmsr & BMSR_LSTATUS) {
3084                 u32 aux_stat, bmcr;
3085
3086                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3087                 for (i = 0; i < 2000; i++) {
3088                         udelay(10);
3089                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3090                             aux_stat)
3091                                 break;
3092                 }
3093
3094                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3095                                              &current_speed,
3096                                              &current_duplex);
3097
3098                 bmcr = 0;
3099                 for (i = 0; i < 200; i++) {
3100                         tg3_readphy(tp, MII_BMCR, &bmcr);
3101                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3102                                 continue;
3103                         if (bmcr && bmcr != 0x7fff)
3104                                 break;
3105                         udelay(10);
3106                 }
3107
3108                 lcl_adv = 0;
3109                 rmt_adv = 0;
3110
3111                 tp->link_config.active_speed = current_speed;
3112                 tp->link_config.active_duplex = current_duplex;
3113
3114                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3115                         if ((bmcr & BMCR_ANENABLE) &&
3116                             tg3_copper_is_advertising_all(tp,
3117                                                 tp->link_config.advertising)) {
3118                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3119                                                                   &rmt_adv))
3120                                         current_link_up = 1;
3121                         }
3122                 } else {
3123                         if (!(bmcr & BMCR_ANENABLE) &&
3124                             tp->link_config.speed == current_speed &&
3125                             tp->link_config.duplex == current_duplex &&
3126                             tp->link_config.flowctrl ==
3127                             tp->link_config.active_flowctrl) {
3128                                 current_link_up = 1;
3129                         }
3130                 }
3131
3132                 if (current_link_up == 1 &&
3133                     tp->link_config.active_duplex == DUPLEX_FULL)
3134                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3135         }
3136
3137 relink:
3138         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3139                 u32 tmp;
3140
3141                 tg3_phy_copper_begin(tp);
3142
3143                 tg3_readphy(tp, MII_BMSR, &tmp);
3144                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3145                     (tmp & BMSR_LSTATUS))
3146                         current_link_up = 1;
3147         }
3148
3149         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3150         if (current_link_up == 1) {
3151                 if (tp->link_config.active_speed == SPEED_100 ||
3152                     tp->link_config.active_speed == SPEED_10)
3153                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3154                 else
3155                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3156         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3157                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3158         else
3159                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3160
3161         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3162         if (tp->link_config.active_duplex == DUPLEX_HALF)
3163                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3164
3165         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3166                 if (current_link_up == 1 &&
3167                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3168                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3169                 else
3170                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3171         }
3172
3173         /* ??? Without this setting Netgear GA302T PHY does not
3174          * ??? send/receive packets...
3175          */
3176         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3177             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3178                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3179                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3180                 udelay(80);
3181         }
3182
3183         tw32_f(MAC_MODE, tp->mac_mode);
3184         udelay(40);
3185
3186         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3187                 /* Polled via timer. */
3188                 tw32_f(MAC_EVENT, 0);
3189         } else {
3190                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3191         }
3192         udelay(40);
3193
3194         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3195             current_link_up == 1 &&
3196             tp->link_config.active_speed == SPEED_1000 &&
3197             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3198              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3199                 udelay(120);
3200                 tw32_f(MAC_STATUS,
3201                      (MAC_STATUS_SYNC_CHANGED |
3202                       MAC_STATUS_CFG_CHANGED));
3203                 udelay(40);
3204                 tg3_write_mem(tp,
3205                               NIC_SRAM_FIRMWARE_MBOX,
3206                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3207         }
3208
3209         /* Prevent send BD corruption. */
3210         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3211                 u16 oldlnkctl, newlnkctl;
3212
3213                 pci_read_config_word(tp->pdev,
3214                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3215                                      &oldlnkctl);
3216                 if (tp->link_config.active_speed == SPEED_100 ||
3217                     tp->link_config.active_speed == SPEED_10)
3218                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3219                 else
3220                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3221                 if (newlnkctl != oldlnkctl)
3222                         pci_write_config_word(tp->pdev,
3223                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3224                                               newlnkctl);
3225         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3226                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3227                 if (tp->link_config.active_speed == SPEED_100 ||
3228                     tp->link_config.active_speed == SPEED_10)
3229                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3230                 else
3231                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3232                 if (newreg != oldreg)
3233                         tw32(TG3_PCIE_LNKCTL, newreg);
3234         }
3235
3236         if (current_link_up != netif_carrier_ok(tp->dev)) {
3237                 if (current_link_up)
3238                         netif_carrier_on(tp->dev);
3239                 else
3240                         netif_carrier_off(tp->dev);
3241                 tg3_link_report(tp);
3242         }
3243
3244         return 0;
3245 }
3246
3247 struct tg3_fiber_aneginfo {
3248         int state;
3249 #define ANEG_STATE_UNKNOWN              0
3250 #define ANEG_STATE_AN_ENABLE            1
3251 #define ANEG_STATE_RESTART_INIT         2
3252 #define ANEG_STATE_RESTART              3
3253 #define ANEG_STATE_DISABLE_LINK_OK      4
3254 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3255 #define ANEG_STATE_ABILITY_DETECT       6
3256 #define ANEG_STATE_ACK_DETECT_INIT      7
3257 #define ANEG_STATE_ACK_DETECT           8
3258 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3259 #define ANEG_STATE_COMPLETE_ACK         10
3260 #define ANEG_STATE_IDLE_DETECT_INIT     11
3261 #define ANEG_STATE_IDLE_DETECT          12
3262 #define ANEG_STATE_LINK_OK              13
3263 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3264 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3265
3266         u32 flags;
3267 #define MR_AN_ENABLE            0x00000001
3268 #define MR_RESTART_AN           0x00000002
3269 #define MR_AN_COMPLETE          0x00000004
3270 #define MR_PAGE_RX              0x00000008
3271 #define MR_NP_LOADED            0x00000010
3272 #define MR_TOGGLE_TX            0x00000020
3273 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3274 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3275 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3276 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3277 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3278 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3279 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3280 #define MR_TOGGLE_RX            0x00002000
3281 #define MR_NP_RX                0x00004000
3282
3283 #define MR_LINK_OK              0x80000000
3284
3285         unsigned long link_time, cur_time;
3286
3287         u32 ability_match_cfg;
3288         int ability_match_count;
3289
3290         char ability_match, idle_match, ack_match;
3291
3292         u32 txconfig, rxconfig;
3293 #define ANEG_CFG_NP             0x00000080
3294 #define ANEG_CFG_ACK            0x00000040
3295 #define ANEG_CFG_RF2            0x00000020
3296 #define ANEG_CFG_RF1            0x00000010
3297 #define ANEG_CFG_PS2            0x00000001
3298 #define ANEG_CFG_PS1            0x00008000
3299 #define ANEG_CFG_HD             0x00004000
3300 #define ANEG_CFG_FD             0x00002000
3301 #define ANEG_CFG_INVAL          0x00001f06
3302
3303 };
3304 #define ANEG_OK         0
3305 #define ANEG_DONE       1
3306 #define ANEG_TIMER_ENAB 2
3307 #define ANEG_FAILED     -1
3308
3309 #define ANEG_STATE_SETTLE_TIME  10000
3310
3311 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3312                                    struct tg3_fiber_aneginfo *ap)
3313 {
3314         u16 flowctrl;
3315         unsigned long delta;
3316         u32 rx_cfg_reg;
3317         int ret;
3318
3319         if (ap->state == ANEG_STATE_UNKNOWN) {
3320                 ap->rxconfig = 0;
3321                 ap->link_time = 0;
3322                 ap->cur_time = 0;
3323                 ap->ability_match_cfg = 0;
3324                 ap->ability_match_count = 0;
3325                 ap->ability_match = 0;
3326                 ap->idle_match = 0;
3327                 ap->ack_match = 0;
3328         }
3329         ap->cur_time++;
3330
3331         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3332                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3333
3334                 if (rx_cfg_reg != ap->ability_match_cfg) {
3335                         ap->ability_match_cfg = rx_cfg_reg;
3336                         ap->ability_match = 0;
3337                         ap->ability_match_count = 0;
3338                 } else {
3339                         if (++ap->ability_match_count > 1) {
3340                                 ap->ability_match = 1;
3341                                 ap->ability_match_cfg = rx_cfg_reg;
3342                         }
3343                 }
3344                 if (rx_cfg_reg & ANEG_CFG_ACK)
3345                         ap->ack_match = 1;
3346                 else
3347                         ap->ack_match = 0;
3348
3349                 ap->idle_match = 0;
3350         } else {
3351                 ap->idle_match = 1;
3352                 ap->ability_match_cfg = 0;
3353                 ap->ability_match_count = 0;
3354                 ap->ability_match = 0;
3355                 ap->ack_match = 0;
3356
3357                 rx_cfg_reg = 0;
3358         }
3359
3360         ap->rxconfig = rx_cfg_reg;
3361         ret = ANEG_OK;
3362
3363         switch(ap->state) {
3364         case ANEG_STATE_UNKNOWN:
3365                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3366                         ap->state = ANEG_STATE_AN_ENABLE;
3367
3368                 /* fallthru */
3369         case ANEG_STATE_AN_ENABLE:
3370                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3371                 if (ap->flags & MR_AN_ENABLE) {
3372                         ap->link_time = 0;
3373                         ap->cur_time = 0;
3374                         ap->ability_match_cfg = 0;
3375                         ap->ability_match_count = 0;
3376                         ap->ability_match = 0;
3377                         ap->idle_match = 0;
3378                         ap->ack_match = 0;
3379
3380                         ap->state = ANEG_STATE_RESTART_INIT;
3381                 } else {
3382                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3383                 }
3384                 break;
3385
3386         case ANEG_STATE_RESTART_INIT:
3387                 ap->link_time = ap->cur_time;
3388                 ap->flags &= ~(MR_NP_LOADED);
3389                 ap->txconfig = 0;
3390                 tw32(MAC_TX_AUTO_NEG, 0);
3391                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3392                 tw32_f(MAC_MODE, tp->mac_mode);
3393                 udelay(40);
3394
3395                 ret = ANEG_TIMER_ENAB;
3396                 ap->state = ANEG_STATE_RESTART;
3397
3398                 /* fallthru */
3399         case ANEG_STATE_RESTART:
3400                 delta = ap->cur_time - ap->link_time;
3401                 if (delta > ANEG_STATE_SETTLE_TIME) {
3402                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3403                 } else {
3404                         ret = ANEG_TIMER_ENAB;
3405                 }
3406                 break;
3407
3408         case ANEG_STATE_DISABLE_LINK_OK:
3409                 ret = ANEG_DONE;
3410                 break;
3411
3412         case ANEG_STATE_ABILITY_DETECT_INIT:
3413                 ap->flags &= ~(MR_TOGGLE_TX);
3414                 ap->txconfig = ANEG_CFG_FD;
3415                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3416                 if (flowctrl & ADVERTISE_1000XPAUSE)
3417                         ap->txconfig |= ANEG_CFG_PS1;
3418                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3419                         ap->txconfig |= ANEG_CFG_PS2;
3420                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3421                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3422                 tw32_f(MAC_MODE, tp->mac_mode);
3423                 udelay(40);
3424
3425                 ap->state = ANEG_STATE_ABILITY_DETECT;
3426                 break;
3427
3428         case ANEG_STATE_ABILITY_DETECT:
3429                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3430                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3431                 }
3432                 break;
3433
3434         case ANEG_STATE_ACK_DETECT_INIT:
3435                 ap->txconfig |= ANEG_CFG_ACK;
3436                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3437                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3438                 tw32_f(MAC_MODE, tp->mac_mode);
3439                 udelay(40);
3440
3441                 ap->state = ANEG_STATE_ACK_DETECT;
3442
3443                 /* fallthru */
3444         case ANEG_STATE_ACK_DETECT:
3445                 if (ap->ack_match != 0) {
3446                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3447                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3448                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3449                         } else {
3450                                 ap->state = ANEG_STATE_AN_ENABLE;
3451                         }
3452                 } else if (ap->ability_match != 0 &&
3453                            ap->rxconfig == 0) {
3454                         ap->state = ANEG_STATE_AN_ENABLE;
3455                 }
3456                 break;
3457
3458         case ANEG_STATE_COMPLETE_ACK_INIT:
3459                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3460                         ret = ANEG_FAILED;
3461                         break;
3462                 }
3463                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3464                                MR_LP_ADV_HALF_DUPLEX |
3465                                MR_LP_ADV_SYM_PAUSE |
3466                                MR_LP_ADV_ASYM_PAUSE |
3467                                MR_LP_ADV_REMOTE_FAULT1 |
3468                                MR_LP_ADV_REMOTE_FAULT2 |
3469                                MR_LP_ADV_NEXT_PAGE |
3470                                MR_TOGGLE_RX |
3471                                MR_NP_RX);
3472                 if (ap->rxconfig & ANEG_CFG_FD)
3473                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3474                 if (ap->rxconfig & ANEG_CFG_HD)
3475                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3476                 if (ap->rxconfig & ANEG_CFG_PS1)
3477                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3478                 if (ap->rxconfig & ANEG_CFG_PS2)
3479                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3480                 if (ap->rxconfig & ANEG_CFG_RF1)
3481                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3482                 if (ap->rxconfig & ANEG_CFG_RF2)
3483                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3484                 if (ap->rxconfig & ANEG_CFG_NP)
3485                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3486
3487                 ap->link_time = ap->cur_time;
3488
3489                 ap->flags ^= (MR_TOGGLE_TX);
3490                 if (ap->rxconfig & 0x0008)
3491                         ap->flags |= MR_TOGGLE_RX;
3492                 if (ap->rxconfig & ANEG_CFG_NP)
3493                         ap->flags |= MR_NP_RX;
3494                 ap->flags |= MR_PAGE_RX;
3495
3496                 ap->state = ANEG_STATE_COMPLETE_ACK;
3497                 ret = ANEG_TIMER_ENAB;
3498                 break;
3499
3500         case ANEG_STATE_COMPLETE_ACK:
3501                 if (ap->ability_match != 0 &&
3502                     ap->rxconfig == 0) {
3503                         ap->state = ANEG_STATE_AN_ENABLE;
3504                         break;
3505                 }
3506                 delta = ap->cur_time - ap->link_time;
3507                 if (delta > ANEG_STATE_SETTLE_TIME) {
3508                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3509                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3510                         } else {
3511                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3512                                     !(ap->flags & MR_NP_RX)) {
3513                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3514                                 } else {
3515                                         ret = ANEG_FAILED;
3516                                 }
3517                         }
3518                 }
3519                 break;
3520
3521         case ANEG_STATE_IDLE_DETECT_INIT:
3522                 ap->link_time = ap->cur_time;
3523                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3524                 tw32_f(MAC_MODE, tp->mac_mode);
3525                 udelay(40);
3526
3527                 ap->state = ANEG_STATE_IDLE_DETECT;
3528                 ret = ANEG_TIMER_ENAB;
3529                 break;
3530
3531         case ANEG_STATE_IDLE_DETECT:
3532                 if (ap->ability_match != 0 &&
3533                     ap->rxconfig == 0) {
3534                         ap->state = ANEG_STATE_AN_ENABLE;
3535                         break;
3536                 }
3537                 delta = ap->cur_time - ap->link_time;
3538                 if (delta > ANEG_STATE_SETTLE_TIME) {
3539                         /* XXX another gem from the Broadcom driver :( */
3540                         ap->state = ANEG_STATE_LINK_OK;
3541                 }
3542                 break;
3543
3544         case ANEG_STATE_LINK_OK:
3545                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3546                 ret = ANEG_DONE;
3547                 break;
3548
3549         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3550                 /* ??? unimplemented */
3551                 break;
3552
3553         case ANEG_STATE_NEXT_PAGE_WAIT:
3554                 /* ??? unimplemented */
3555                 break;
3556
3557         default:
3558                 ret = ANEG_FAILED;
3559                 break;
3560         }
3561
3562         return ret;
3563 }
3564
3565 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3566 {
3567         int res = 0;
3568         struct tg3_fiber_aneginfo aninfo;
3569         int status = ANEG_FAILED;
3570         unsigned int tick;
3571         u32 tmp;
3572
3573         tw32_f(MAC_TX_AUTO_NEG, 0);
3574
3575         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3576         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3577         udelay(40);
3578
3579         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3580         udelay(40);
3581
3582         memset(&aninfo, 0, sizeof(aninfo));
3583         aninfo.flags |= MR_AN_ENABLE;
3584         aninfo.state = ANEG_STATE_UNKNOWN;
3585         aninfo.cur_time = 0;
3586         tick = 0;
3587         while (++tick < 195000) {
3588                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3589                 if (status == ANEG_DONE || status == ANEG_FAILED)
3590                         break;
3591
3592                 udelay(1);
3593         }
3594
3595         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3596         tw32_f(MAC_MODE, tp->mac_mode);
3597         udelay(40);
3598
3599         *txflags = aninfo.txconfig;
3600         *rxflags = aninfo.flags;
3601
3602         if (status == ANEG_DONE &&
3603             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3604                              MR_LP_ADV_FULL_DUPLEX)))
3605                 res = 1;
3606
3607         return res;
3608 }
3609
3610 static void tg3_init_bcm8002(struct tg3 *tp)
3611 {
3612         u32 mac_status = tr32(MAC_STATUS);
3613         int i;
3614
3615         /* Reset when initting first time or we have a link. */
3616         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3617             !(mac_status & MAC_STATUS_PCS_SYNCED))
3618                 return;
3619
3620         /* Set PLL lock range. */
3621         tg3_writephy(tp, 0x16, 0x8007);
3622
3623         /* SW reset */
3624         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3625
3626         /* Wait for reset to complete. */
3627         /* XXX schedule_timeout() ... */
3628         for (i = 0; i < 500; i++)
3629                 udelay(10);
3630
3631         /* Config mode; select PMA/Ch 1 regs. */
3632         tg3_writephy(tp, 0x10, 0x8411);
3633
3634         /* Enable auto-lock and comdet, select txclk for tx. */
3635         tg3_writephy(tp, 0x11, 0x0a10);
3636
3637         tg3_writephy(tp, 0x18, 0x00a0);
3638         tg3_writephy(tp, 0x16, 0x41ff);
3639
3640         /* Assert and deassert POR. */
3641         tg3_writephy(tp, 0x13, 0x0400);
3642         udelay(40);
3643         tg3_writephy(tp, 0x13, 0x0000);
3644
3645         tg3_writephy(tp, 0x11, 0x0a50);
3646         udelay(40);
3647         tg3_writephy(tp, 0x11, 0x0a10);
3648
3649         /* Wait for signal to stabilize */
3650         /* XXX schedule_timeout() ... */
3651         for (i = 0; i < 15000; i++)
3652                 udelay(10);
3653
3654         /* Deselect the channel register so we can read the PHYID
3655          * later.
3656          */
3657         tg3_writephy(tp, 0x10, 0x8011);
3658 }
3659
3660 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3661 {
3662         u16 flowctrl;
3663         u32 sg_dig_ctrl, sg_dig_status;
3664         u32 serdes_cfg, expected_sg_dig_ctrl;
3665         int workaround, port_a;
3666         int current_link_up;
3667
3668         serdes_cfg = 0;
3669         expected_sg_dig_ctrl = 0;
3670         workaround = 0;
3671         port_a = 1;
3672         current_link_up = 0;
3673
3674         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3675             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3676                 workaround = 1;
3677                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3678                         port_a = 0;
3679
3680                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3681                 /* preserve bits 20-23 for voltage regulator */
3682                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3683         }
3684
3685         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3686
3687         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3688                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3689                         if (workaround) {
3690                                 u32 val = serdes_cfg;
3691
3692                                 if (port_a)
3693                                         val |= 0xc010000;
3694                                 else
3695                                         val |= 0x4010000;
3696                                 tw32_f(MAC_SERDES_CFG, val);
3697                         }
3698
3699                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3700                 }
3701                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3702                         tg3_setup_flow_control(tp, 0, 0);
3703                         current_link_up = 1;
3704                 }
3705                 goto out;
3706         }
3707
3708         /* Want auto-negotiation.  */
3709         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3710
3711         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3712         if (flowctrl & ADVERTISE_1000XPAUSE)
3713                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3714         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3715                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3716
3717         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3718                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3719                     tp->serdes_counter &&
3720                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3721                                     MAC_STATUS_RCVD_CFG)) ==
3722                      MAC_STATUS_PCS_SYNCED)) {
3723                         tp->serdes_counter--;
3724                         current_link_up = 1;
3725                         goto out;
3726                 }
3727 restart_autoneg:
3728                 if (workaround)
3729                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3730                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3731                 udelay(5);
3732                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3733
3734                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3735                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3736         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3737                                  MAC_STATUS_SIGNAL_DET)) {
3738                 sg_dig_status = tr32(SG_DIG_STATUS);
3739                 mac_status = tr32(MAC_STATUS);
3740
3741                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3742                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3743                         u32 local_adv = 0, remote_adv = 0;
3744
3745                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3746                                 local_adv |= ADVERTISE_1000XPAUSE;
3747                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3748                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3749
3750                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3751                                 remote_adv |= LPA_1000XPAUSE;
3752                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3753                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3754
3755                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3756                         current_link_up = 1;
3757                         tp->serdes_counter = 0;
3758                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3759                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3760                         if (tp->serdes_counter)
3761                                 tp->serdes_counter--;
3762                         else {
3763                                 if (workaround) {
3764                                         u32 val = serdes_cfg;
3765
3766                                         if (port_a)
3767                                                 val |= 0xc010000;
3768                                         else
3769                                                 val |= 0x4010000;
3770
3771                                         tw32_f(MAC_SERDES_CFG, val);
3772                                 }
3773
3774                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3775                                 udelay(40);
3776
3777                                 /* Link parallel detection - link is up */
3778                                 /* only if we have PCS_SYNC and not */
3779                                 /* receiving config code words */
3780                                 mac_status = tr32(MAC_STATUS);
3781                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3782                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3783                                         tg3_setup_flow_control(tp, 0, 0);
3784                                         current_link_up = 1;
3785                                         tp->tg3_flags2 |=
3786                                                 TG3_FLG2_PARALLEL_DETECT;
3787                                         tp->serdes_counter =
3788                                                 SERDES_PARALLEL_DET_TIMEOUT;
3789                                 } else
3790                                         goto restart_autoneg;
3791                         }
3792                 }
3793         } else {
3794                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3795                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3796         }
3797
3798 out:
3799         return current_link_up;
3800 }
3801
3802 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3803 {
3804         int current_link_up = 0;
3805
3806         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3807                 goto out;
3808
3809         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3810                 u32 txflags, rxflags;
3811                 int i;
3812
3813                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3814                         u32 local_adv = 0, remote_adv = 0;
3815
3816                         if (txflags & ANEG_CFG_PS1)
3817                                 local_adv |= ADVERTISE_1000XPAUSE;
3818                         if (txflags & ANEG_CFG_PS2)
3819                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3820
3821                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3822                                 remote_adv |= LPA_1000XPAUSE;
3823                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3824                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3825
3826                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3827
3828                         current_link_up = 1;
3829                 }
3830                 for (i = 0; i < 30; i++) {
3831                         udelay(20);
3832                         tw32_f(MAC_STATUS,
3833                                (MAC_STATUS_SYNC_CHANGED |
3834                                 MAC_STATUS_CFG_CHANGED));
3835                         udelay(40);
3836                         if ((tr32(MAC_STATUS) &
3837                              (MAC_STATUS_SYNC_CHANGED |
3838                               MAC_STATUS_CFG_CHANGED)) == 0)
3839                                 break;
3840                 }
3841
3842                 mac_status = tr32(MAC_STATUS);
3843                 if (current_link_up == 0 &&
3844                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3845                     !(mac_status & MAC_STATUS_RCVD_CFG))
3846                         current_link_up = 1;
3847         } else {
3848                 tg3_setup_flow_control(tp, 0, 0);
3849
3850                 /* Forcing 1000FD link up. */
3851                 current_link_up = 1;
3852
3853                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3854                 udelay(40);
3855
3856                 tw32_f(MAC_MODE, tp->mac_mode);
3857                 udelay(40);
3858         }
3859
3860 out:
3861         return current_link_up;
3862 }
3863
3864 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3865 {
3866         u32 orig_pause_cfg;
3867         u16 orig_active_speed;
3868         u8 orig_active_duplex;
3869         u32 mac_status;
3870         int current_link_up;
3871         int i;
3872
3873         orig_pause_cfg = tp->link_config.active_flowctrl;
3874         orig_active_speed = tp->link_config.active_speed;
3875         orig_active_duplex = tp->link_config.active_duplex;
3876
3877         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3878             netif_carrier_ok(tp->dev) &&
3879             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3880                 mac_status = tr32(MAC_STATUS);
3881                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3882                                MAC_STATUS_SIGNAL_DET |
3883                                MAC_STATUS_CFG_CHANGED |
3884                                MAC_STATUS_RCVD_CFG);
3885                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3886                                    MAC_STATUS_SIGNAL_DET)) {
3887                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3888                                             MAC_STATUS_CFG_CHANGED));
3889                         return 0;
3890                 }
3891         }
3892
3893         tw32_f(MAC_TX_AUTO_NEG, 0);
3894
3895         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3896         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3897         tw32_f(MAC_MODE, tp->mac_mode);
3898         udelay(40);
3899
3900         if (tp->phy_id == PHY_ID_BCM8002)
3901                 tg3_init_bcm8002(tp);
3902
3903         /* Enable link change event even when serdes polling.  */
3904         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3905         udelay(40);
3906
3907         current_link_up = 0;
3908         mac_status = tr32(MAC_STATUS);
3909
3910         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3911                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3912         else
3913                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3914
3915         tp->napi[0].hw_status->status =
3916                 (SD_STATUS_UPDATED |
3917                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3918
3919         for (i = 0; i < 100; i++) {
3920                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3921                                     MAC_STATUS_CFG_CHANGED));
3922                 udelay(5);
3923                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3924                                          MAC_STATUS_CFG_CHANGED |
3925                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3926                         break;
3927         }
3928
3929         mac_status = tr32(MAC_STATUS);
3930         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3931                 current_link_up = 0;
3932                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3933                     tp->serdes_counter == 0) {
3934                         tw32_f(MAC_MODE, (tp->mac_mode |
3935                                           MAC_MODE_SEND_CONFIGS));
3936                         udelay(1);
3937                         tw32_f(MAC_MODE, tp->mac_mode);
3938                 }
3939         }
3940
3941         if (current_link_up == 1) {
3942                 tp->link_config.active_speed = SPEED_1000;
3943                 tp->link_config.active_duplex = DUPLEX_FULL;
3944                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3945                                     LED_CTRL_LNKLED_OVERRIDE |
3946                                     LED_CTRL_1000MBPS_ON));
3947         } else {
3948                 tp->link_config.active_speed = SPEED_INVALID;
3949                 tp->link_config.active_duplex = DUPLEX_INVALID;
3950                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3951                                     LED_CTRL_LNKLED_OVERRIDE |
3952                                     LED_CTRL_TRAFFIC_OVERRIDE));
3953         }
3954
3955         if (current_link_up != netif_carrier_ok(tp->dev)) {
3956                 if (current_link_up)
3957                         netif_carrier_on(tp->dev);
3958                 else
3959                         netif_carrier_off(tp->dev);
3960                 tg3_link_report(tp);
3961         } else {
3962                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3963                 if (orig_pause_cfg != now_pause_cfg ||
3964                     orig_active_speed != tp->link_config.active_speed ||
3965                     orig_active_duplex != tp->link_config.active_duplex)
3966                         tg3_link_report(tp);
3967         }
3968
3969         return 0;
3970 }
3971
3972 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3973 {
3974         int current_link_up, err = 0;
3975         u32 bmsr, bmcr;
3976         u16 current_speed;
3977         u8 current_duplex;
3978         u32 local_adv, remote_adv;
3979
3980         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3981         tw32_f(MAC_MODE, tp->mac_mode);
3982         udelay(40);
3983
3984         tw32(MAC_EVENT, 0);
3985
3986         tw32_f(MAC_STATUS,
3987              (MAC_STATUS_SYNC_CHANGED |
3988               MAC_STATUS_CFG_CHANGED |
3989               MAC_STATUS_MI_COMPLETION |
3990               MAC_STATUS_LNKSTATE_CHANGED));
3991         udelay(40);
3992
3993         if (force_reset)
3994                 tg3_phy_reset(tp);
3995
3996         current_link_up = 0;
3997         current_speed = SPEED_INVALID;
3998         current_duplex = DUPLEX_INVALID;
3999
4000         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4001         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4003                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4004                         bmsr |= BMSR_LSTATUS;
4005                 else
4006                         bmsr &= ~BMSR_LSTATUS;
4007         }
4008
4009         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4010
4011         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4012             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4013                 /* do nothing, just check for link up at the end */
4014         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4015                 u32 adv, new_adv;
4016
4017                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4018                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4019                                   ADVERTISE_1000XPAUSE |
4020                                   ADVERTISE_1000XPSE_ASYM |
4021                                   ADVERTISE_SLCT);
4022
4023                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4024
4025                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4026                         new_adv |= ADVERTISE_1000XHALF;
4027                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4028                         new_adv |= ADVERTISE_1000XFULL;
4029
4030                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4031                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4032                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4033                         tg3_writephy(tp, MII_BMCR, bmcr);
4034
4035                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4036                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4037                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4038
4039                         return err;
4040                 }
4041         } else {
4042                 u32 new_bmcr;
4043
4044                 bmcr &= ~BMCR_SPEED1000;
4045                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4046
4047                 if (tp->link_config.duplex == DUPLEX_FULL)
4048                         new_bmcr |= BMCR_FULLDPLX;
4049
4050                 if (new_bmcr != bmcr) {
4051                         /* BMCR_SPEED1000 is a reserved bit that needs
4052                          * to be set on write.
4053                          */
4054                         new_bmcr |= BMCR_SPEED1000;
4055
4056                         /* Force a linkdown */
4057                         if (netif_carrier_ok(tp->dev)) {
4058                                 u32 adv;
4059
4060                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061                                 adv &= ~(ADVERTISE_1000XFULL |
4062                                          ADVERTISE_1000XHALF |
4063                                          ADVERTISE_SLCT);
4064                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4065                                 tg3_writephy(tp, MII_BMCR, bmcr |
4066                                                            BMCR_ANRESTART |
4067                                                            BMCR_ANENABLE);
4068                                 udelay(10);
4069                                 netif_carrier_off(tp->dev);
4070                         }
4071                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4072                         bmcr = new_bmcr;
4073                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4074                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4075                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4076                             ASIC_REV_5714) {
4077                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4078                                         bmsr |= BMSR_LSTATUS;
4079                                 else
4080                                         bmsr &= ~BMSR_LSTATUS;
4081                         }
4082                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4083                 }
4084         }
4085
4086         if (bmsr & BMSR_LSTATUS) {
4087                 current_speed = SPEED_1000;
4088                 current_link_up = 1;
4089                 if (bmcr & BMCR_FULLDPLX)
4090                         current_duplex = DUPLEX_FULL;
4091                 else
4092                         current_duplex = DUPLEX_HALF;
4093
4094                 local_adv = 0;
4095                 remote_adv = 0;
4096
4097                 if (bmcr & BMCR_ANENABLE) {
4098                         u32 common;
4099
4100                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4101                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4102                         common = local_adv & remote_adv;
4103                         if (common & (ADVERTISE_1000XHALF |
4104                                       ADVERTISE_1000XFULL)) {
4105                                 if (common & ADVERTISE_1000XFULL)
4106                                         current_duplex = DUPLEX_FULL;
4107                                 else
4108                                         current_duplex = DUPLEX_HALF;
4109                         }
4110                         else
4111                                 current_link_up = 0;
4112                 }
4113         }
4114
4115         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4116                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4117
4118         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4119         if (tp->link_config.active_duplex == DUPLEX_HALF)
4120                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4121
4122         tw32_f(MAC_MODE, tp->mac_mode);
4123         udelay(40);
4124
4125         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4126
4127         tp->link_config.active_speed = current_speed;
4128         tp->link_config.active_duplex = current_duplex;
4129
4130         if (current_link_up != netif_carrier_ok(tp->dev)) {
4131                 if (current_link_up)
4132                         netif_carrier_on(tp->dev);
4133                 else {
4134                         netif_carrier_off(tp->dev);
4135                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4136                 }
4137                 tg3_link_report(tp);
4138         }
4139         return err;
4140 }
4141
4142 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4143 {
4144         if (tp->serdes_counter) {
4145                 /* Give autoneg time to complete. */
4146                 tp->serdes_counter--;
4147                 return;
4148         }
4149         if (!netif_carrier_ok(tp->dev) &&
4150             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4151                 u32 bmcr;
4152
4153                 tg3_readphy(tp, MII_BMCR, &bmcr);
4154                 if (bmcr & BMCR_ANENABLE) {
4155                         u32 phy1, phy2;
4156
4157                         /* Select shadow register 0x1f */
4158                         tg3_writephy(tp, 0x1c, 0x7c00);
4159                         tg3_readphy(tp, 0x1c, &phy1);
4160
4161                         /* Select expansion interrupt status register */
4162                         tg3_writephy(tp, 0x17, 0x0f01);
4163                         tg3_readphy(tp, 0x15, &phy2);
4164                         tg3_readphy(tp, 0x15, &phy2);
4165
4166                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4167                                 /* We have signal detect and not receiving
4168                                  * config code words, link is up by parallel
4169                                  * detection.
4170                                  */
4171
4172                                 bmcr &= ~BMCR_ANENABLE;
4173                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4174                                 tg3_writephy(tp, MII_BMCR, bmcr);
4175                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4176                         }
4177                 }
4178         }
4179         else if (netif_carrier_ok(tp->dev) &&
4180                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4181                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4182                 u32 phy2;
4183
4184                 /* Select expansion interrupt status register */
4185                 tg3_writephy(tp, 0x17, 0x0f01);
4186                 tg3_readphy(tp, 0x15, &phy2);
4187                 if (phy2 & 0x20) {
4188                         u32 bmcr;
4189
4190                         /* Config code words received, turn on autoneg. */
4191                         tg3_readphy(tp, MII_BMCR, &bmcr);
4192                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4193
4194                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4195
4196                 }
4197         }
4198 }
4199
4200 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4201 {
4202         int err;
4203
4204         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4205                 err = tg3_setup_fiber_phy(tp, force_reset);
4206         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4207                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4208         } else {
4209                 err = tg3_setup_copper_phy(tp, force_reset);
4210         }
4211
4212         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4213                 u32 val, scale;
4214
4215                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4216                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4217                         scale = 65;
4218                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4219                         scale = 6;
4220                 else
4221                         scale = 12;
4222
4223                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4224                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4225                 tw32(GRC_MISC_CFG, val);
4226         }
4227
4228         if (tp->link_config.active_speed == SPEED_1000 &&
4229             tp->link_config.active_duplex == DUPLEX_HALF)
4230                 tw32(MAC_TX_LENGTHS,
4231                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4232                       (6 << TX_LENGTHS_IPG_SHIFT) |
4233                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4234         else
4235                 tw32(MAC_TX_LENGTHS,
4236                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4237                       (6 << TX_LENGTHS_IPG_SHIFT) |
4238                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4239
4240         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4241                 if (netif_carrier_ok(tp->dev)) {
4242                         tw32(HOSTCC_STAT_COAL_TICKS,
4243                              tp->coal.stats_block_coalesce_usecs);
4244                 } else {
4245                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4246                 }
4247         }
4248
4249         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4250                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4251                 if (!netif_carrier_ok(tp->dev))
4252                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4253                               tp->pwrmgmt_thresh;
4254                 else
4255                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4256                 tw32(PCIE_PWR_MGMT_THRESH, val);
4257         }
4258
4259         return err;
4260 }
4261
4262 /* This is called whenever we suspect that the system chipset is re-
4263  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4264  * is bogus tx completions. We try to recover by setting the
4265  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4266  * in the workqueue.
4267  */
4268 static void tg3_tx_recover(struct tg3 *tp)
4269 {
4270         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4271                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4272
4273         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4274                "mapped I/O cycles to the network device, attempting to "
4275                "recover. Please report the problem to the driver maintainer "
4276                "and include system chipset information.\n", tp->dev->name);
4277
4278         spin_lock(&tp->lock);
4279         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4280         spin_unlock(&tp->lock);
4281 }
4282
4283 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4284 {
4285         smp_mb();
4286         return tnapi->tx_pending -
4287                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4288 }
4289
4290 /* Tigon3 never reports partial packet sends.  So we do not
4291  * need special logic to handle SKBs that have not had all
4292  * of their frags sent yet, like SunGEM does.
4293  */
4294 static void tg3_tx(struct tg3_napi *tnapi)
4295 {
4296         struct tg3 *tp = tnapi->tp;
4297         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4298         u32 sw_idx = tnapi->tx_cons;
4299         struct netdev_queue *txq;
4300         int index = tnapi - tp->napi;
4301
4302         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4303                 index--;
4304
4305         txq = netdev_get_tx_queue(tp->dev, index);
4306
4307         while (sw_idx != hw_idx) {
4308                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4309                 struct sk_buff *skb = ri->skb;
4310                 int i, tx_bug = 0;
4311
4312                 if (unlikely(skb == NULL)) {
4313                         tg3_tx_recover(tp);
4314                         return;
4315                 }
4316
4317                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4318
4319                 ri->skb = NULL;
4320
4321                 sw_idx = NEXT_TX(sw_idx);
4322
4323                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4324                         ri = &tnapi->tx_buffers[sw_idx];
4325                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4326                                 tx_bug = 1;
4327                         sw_idx = NEXT_TX(sw_idx);
4328                 }
4329
4330                 dev_kfree_skb(skb);
4331
4332                 if (unlikely(tx_bug)) {
4333                         tg3_tx_recover(tp);
4334                         return;
4335                 }
4336         }
4337
4338         tnapi->tx_cons = sw_idx;
4339
4340         /* Need to make the tx_cons update visible to tg3_start_xmit()
4341          * before checking for netif_queue_stopped().  Without the
4342          * memory barrier, there is a small possibility that tg3_start_xmit()
4343          * will miss it and cause the queue to be stopped forever.
4344          */
4345         smp_mb();
4346
4347         if (unlikely(netif_tx_queue_stopped(txq) &&
4348                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4349                 __netif_tx_lock(txq, smp_processor_id());
4350                 if (netif_tx_queue_stopped(txq) &&
4351                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4352                         netif_tx_wake_queue(txq);
4353                 __netif_tx_unlock(txq);
4354         }
4355 }
4356
4357 /* Returns size of skb allocated or < 0 on error.
4358  *
4359  * We only need to fill in the address because the other members
4360  * of the RX descriptor are invariant, see tg3_init_rings.
4361  *
4362  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4363  * posting buffers we only dirty the first cache line of the RX
4364  * descriptor (containing the address).  Whereas for the RX status
4365  * buffers the cpu only reads the last cacheline of the RX descriptor
4366  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4367  */
4368 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4369                             int src_idx, u32 dest_idx_unmasked)
4370 {
4371         struct tg3 *tp = tnapi->tp;
4372         struct tg3_rx_buffer_desc *desc;
4373         struct ring_info *map, *src_map;
4374         struct sk_buff *skb;
4375         dma_addr_t mapping;
4376         int skb_size, dest_idx;
4377         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4378
4379         src_map = NULL;
4380         switch (opaque_key) {
4381         case RXD_OPAQUE_RING_STD:
4382                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4383                 desc = &tpr->rx_std[dest_idx];
4384                 map = &tpr->rx_std_buffers[dest_idx];
4385                 if (src_idx >= 0)
4386                         src_map = &tpr->rx_std_buffers[src_idx];
4387                 skb_size = tp->rx_pkt_map_sz;
4388                 break;
4389
4390         case RXD_OPAQUE_RING_JUMBO:
4391                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4392                 desc = &tpr->rx_jmb[dest_idx].std;
4393                 map = &tpr->rx_jmb_buffers[dest_idx];
4394                 if (src_idx >= 0)
4395                         src_map = &tpr->rx_jmb_buffers[src_idx];
4396                 skb_size = TG3_RX_JMB_MAP_SZ;
4397                 break;
4398
4399         default:
4400                 return -EINVAL;
4401         }
4402
4403         /* Do not overwrite any of the map or rp information
4404          * until we are sure we can commit to a new buffer.
4405          *
4406          * Callers depend upon this behavior and assume that
4407          * we leave everything unchanged if we fail.
4408          */
4409         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4410         if (skb == NULL)
4411                 return -ENOMEM;
4412
4413         skb_reserve(skb, tp->rx_offset);
4414
4415         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4416                                  PCI_DMA_FROMDEVICE);
4417
4418         map->skb = skb;
4419         pci_unmap_addr_set(map, mapping, mapping);
4420
4421         if (src_map != NULL)
4422                 src_map->skb = NULL;
4423
4424         desc->addr_hi = ((u64)mapping >> 32);
4425         desc->addr_lo = ((u64)mapping & 0xffffffff);
4426
4427         return skb_size;
4428 }
4429
4430 /* We only need to move over in the address because the other
4431  * members of the RX descriptor are invariant.  See notes above
4432  * tg3_alloc_rx_skb for full details.
4433  */
4434 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4435                            int src_idx, u32 dest_idx_unmasked)
4436 {
4437         struct tg3 *tp = tnapi->tp;
4438         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4439         struct ring_info *src_map, *dest_map;
4440         int dest_idx;
4441         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4442
4443         switch (opaque_key) {
4444         case RXD_OPAQUE_RING_STD:
4445                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4446                 dest_desc = &tpr->rx_std[dest_idx];
4447                 dest_map = &tpr->rx_std_buffers[dest_idx];
4448                 src_desc = &tpr->rx_std[src_idx];
4449                 src_map = &tpr->rx_std_buffers[src_idx];
4450                 break;
4451
4452         case RXD_OPAQUE_RING_JUMBO:
4453                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4454                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4455                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4456                 src_desc = &tpr->rx_jmb[src_idx].std;
4457                 src_map = &tpr->rx_jmb_buffers[src_idx];
4458                 break;
4459
4460         default:
4461                 return;
4462         }
4463
4464         dest_map->skb = src_map->skb;
4465         pci_unmap_addr_set(dest_map, mapping,
4466                            pci_unmap_addr(src_map, mapping));
4467         dest_desc->addr_hi = src_desc->addr_hi;
4468         dest_desc->addr_lo = src_desc->addr_lo;
4469
4470         src_map->skb = NULL;
4471 }
4472
4473 /* The RX ring scheme is composed of multiple rings which post fresh
4474  * buffers to the chip, and one special ring the chip uses to report
4475  * status back to the host.
4476  *
4477  * The special ring reports the status of received packets to the
4478  * host.  The chip does not write into the original descriptor the
4479  * RX buffer was obtained from.  The chip simply takes the original
4480  * descriptor as provided by the host, updates the status and length
4481  * field, then writes this into the next status ring entry.
4482  *
4483  * Each ring the host uses to post buffers to the chip is described
4484  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4485  * it is first placed into the on-chip ram.  When the packet's length
4486  * is known, it walks down the TG3_BDINFO entries to select the ring.
4487  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4488  * which is within the range of the new packet's length is chosen.
4489  *
4490  * The "separate ring for rx status" scheme may sound queer, but it makes
4491  * sense from a cache coherency perspective.  If only the host writes
4492  * to the buffer post rings, and only the chip writes to the rx status
4493  * rings, then cache lines never move beyond shared-modified state.
4494  * If both the host and chip were to write into the same ring, cache line
4495  * eviction could occur since both entities want it in an exclusive state.
4496  */
4497 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4498 {
4499         struct tg3 *tp = tnapi->tp;
4500         u32 work_mask, rx_std_posted = 0;
4501         u32 sw_idx = tnapi->rx_rcb_ptr;
4502         u16 hw_idx;
4503         int received;
4504         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4505
4506         hw_idx = tnapi->hw_status->idx[0].rx_producer;
4507         /*
4508          * We need to order the read of hw_idx and the read of
4509          * the opaque cookie.
4510          */
4511         rmb();
4512         work_mask = 0;
4513         received = 0;
4514         while (sw_idx != hw_idx && budget > 0) {
4515                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4516                 unsigned int len;
4517                 struct sk_buff *skb;
4518                 dma_addr_t dma_addr;
4519                 u32 opaque_key, desc_idx, *post_ptr;
4520
4521                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4522                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4523                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4524                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4525                         dma_addr = pci_unmap_addr(ri, mapping);
4526                         skb = ri->skb;
4527                         post_ptr = &tpr->rx_std_ptr;
4528                         rx_std_posted++;
4529                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4530                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4531                         dma_addr = pci_unmap_addr(ri, mapping);
4532                         skb = ri->skb;
4533                         post_ptr = &tpr->rx_jmb_ptr;
4534                 } else
4535                         goto next_pkt_nopost;
4536
4537                 work_mask |= opaque_key;
4538
4539                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4540                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4541                 drop_it:
4542                         tg3_recycle_rx(tnapi, opaque_key,
4543                                        desc_idx, *post_ptr);
4544                 drop_it_no_recycle:
4545                         /* Other statistics kept track of by card. */
4546                         tp->net_stats.rx_dropped++;
4547                         goto next_pkt;
4548                 }
4549
4550                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4551                       ETH_FCS_LEN;
4552
4553                 if (len > RX_COPY_THRESHOLD
4554                         && tp->rx_offset == NET_IP_ALIGN
4555                         /* rx_offset will likely not equal NET_IP_ALIGN
4556                          * if this is a 5701 card running in PCI-X mode
4557                          * [see tg3_get_invariants()]
4558                          */
4559                 ) {
4560                         int skb_size;
4561
4562                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4563                                                     desc_idx, *post_ptr);
4564                         if (skb_size < 0)
4565                                 goto drop_it;
4566
4567                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4568                                          PCI_DMA_FROMDEVICE);
4569
4570                         skb_put(skb, len);
4571                 } else {
4572                         struct sk_buff *copy_skb;
4573
4574                         tg3_recycle_rx(tnapi, opaque_key,
4575                                        desc_idx, *post_ptr);
4576
4577                         copy_skb = netdev_alloc_skb(tp->dev,
4578                                                     len + TG3_RAW_IP_ALIGN);
4579                         if (copy_skb == NULL)
4580                                 goto drop_it_no_recycle;
4581
4582                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4583                         skb_put(copy_skb, len);
4584                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4585                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4586                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4587
4588                         /* We'll reuse the original ring buffer. */
4589                         skb = copy_skb;
4590                 }
4591
4592                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4593                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4594                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4595                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4596                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4597                 else
4598                         skb->ip_summed = CHECKSUM_NONE;
4599
4600                 skb->protocol = eth_type_trans(skb, tp->dev);
4601
4602                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4603                     skb->protocol != htons(ETH_P_8021Q)) {
4604                         dev_kfree_skb(skb);
4605                         goto next_pkt;
4606                 }
4607
4608 #if TG3_VLAN_TAG_USED
4609                 if (tp->vlgrp != NULL &&
4610                     desc->type_flags & RXD_FLAG_VLAN) {
4611                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4612                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4613                 } else
4614 #endif
4615                         napi_gro_receive(&tnapi->napi, skb);
4616
4617                 received++;
4618                 budget--;
4619
4620 next_pkt:
4621                 (*post_ptr)++;
4622
4623                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4624                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4625
4626                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4627                                      TG3_64BIT_REG_LOW, idx);
4628                         work_mask &= ~RXD_OPAQUE_RING_STD;
4629                         rx_std_posted = 0;
4630                 }
4631 next_pkt_nopost:
4632                 sw_idx++;
4633                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4634
4635                 /* Refresh hw_idx to see if there is new work */
4636                 if (sw_idx == hw_idx) {
4637                         hw_idx = tnapi->hw_status->idx[0].rx_producer;
4638                         rmb();
4639                 }
4640         }
4641
4642         /* ACK the status ring. */
4643         tnapi->rx_rcb_ptr = sw_idx;
4644         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4645
4646         /* Refill RX ring(s). */
4647         if (work_mask & RXD_OPAQUE_RING_STD) {
4648                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4649                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4650                              sw_idx);
4651         }
4652         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4653                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4654                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4655                              sw_idx);
4656         }
4657         mmiowb();
4658
4659         return received;
4660 }
4661
4662 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4663 {
4664         struct tg3 *tp = tnapi->tp;
4665         struct tg3_hw_status *sblk = tnapi->hw_status;
4666
4667         /* handle link change and other phy events */
4668         if (!(tp->tg3_flags &
4669               (TG3_FLAG_USE_LINKCHG_REG |
4670                TG3_FLAG_POLL_SERDES))) {
4671                 if (sblk->status & SD_STATUS_LINK_CHG) {
4672                         sblk->status = SD_STATUS_UPDATED |
4673                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4674                         spin_lock(&tp->lock);
4675                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4676                                 tw32_f(MAC_STATUS,
4677                                      (MAC_STATUS_SYNC_CHANGED |
4678                                       MAC_STATUS_CFG_CHANGED |
4679                                       MAC_STATUS_MI_COMPLETION |
4680                                       MAC_STATUS_LNKSTATE_CHANGED));
4681                                 udelay(40);
4682                         } else
4683                                 tg3_setup_phy(tp, 0);
4684                         spin_unlock(&tp->lock);
4685                 }
4686         }
4687
4688         /* run TX completion thread */
4689         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4690                 tg3_tx(tnapi);
4691                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4692                         return work_done;
4693         }
4694
4695         /* run RX thread, within the bounds set by NAPI.
4696          * All RX "locking" is done by ensuring outside
4697          * code synchronizes with tg3->napi.poll()
4698          */
4699         if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
4700                 work_done += tg3_rx(tnapi, budget - work_done);
4701
4702         return work_done;
4703 }
4704
4705 static int tg3_poll(struct napi_struct *napi, int budget)
4706 {
4707         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4708         struct tg3 *tp = tnapi->tp;
4709         int work_done = 0;
4710         struct tg3_hw_status *sblk = tnapi->hw_status;
4711
4712         while (1) {
4713                 work_done = tg3_poll_work(tnapi, work_done, budget);
4714
4715                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4716                         goto tx_recovery;
4717
4718                 if (unlikely(work_done >= budget))
4719                         break;
4720
4721                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4722                         /* tp->last_tag is used in tg3_int_reenable() below
4723                          * to tell the hw how much work has been processed,
4724                          * so we must read it before checking for more work.
4725                          */
4726                         tnapi->last_tag = sblk->status_tag;
4727                         tnapi->last_irq_tag = tnapi->last_tag;
4728                         rmb();
4729                 } else
4730                         sblk->status &= ~SD_STATUS_UPDATED;
4731
4732                 if (likely(!tg3_has_work(tnapi))) {
4733                         napi_complete(napi);
4734                         tg3_int_reenable(tnapi);
4735                         break;
4736                 }
4737         }
4738
4739         return work_done;
4740
4741 tx_recovery:
4742         /* work_done is guaranteed to be less than budget. */
4743         napi_complete(napi);
4744         schedule_work(&tp->reset_task);
4745         return work_done;
4746 }
4747
4748 static void tg3_irq_quiesce(struct tg3 *tp)
4749 {
4750         int i;
4751
4752         BUG_ON(tp->irq_sync);
4753
4754         tp->irq_sync = 1;
4755         smp_mb();
4756
4757         for (i = 0; i < tp->irq_cnt; i++)
4758                 synchronize_irq(tp->napi[i].irq_vec);
4759 }
4760
4761 static inline int tg3_irq_sync(struct tg3 *tp)
4762 {
4763         return tp->irq_sync;
4764 }
4765
4766 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4767  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4768  * with as well.  Most of the time, this is not necessary except when
4769  * shutting down the device.
4770  */
4771 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4772 {
4773         spin_lock_bh(&tp->lock);
4774         if (irq_sync)
4775                 tg3_irq_quiesce(tp);
4776 }
4777
4778 static inline void tg3_full_unlock(struct tg3 *tp)
4779 {
4780         spin_unlock_bh(&tp->lock);
4781 }
4782
4783 /* One-shot MSI handler - Chip automatically disables interrupt
4784  * after sending MSI so driver doesn't have to do it.
4785  */
4786 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4787 {
4788         struct tg3_napi *tnapi = dev_id;
4789         struct tg3 *tp = tnapi->tp;
4790
4791         prefetch(tnapi->hw_status);
4792         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4793
4794         if (likely(!tg3_irq_sync(tp)))
4795                 napi_schedule(&tnapi->napi);
4796
4797         return IRQ_HANDLED;
4798 }
4799
4800 /* MSI ISR - No need to check for interrupt sharing and no need to
4801  * flush status block and interrupt mailbox. PCI ordering rules
4802  * guarantee that MSI will arrive after the status block.
4803  */
4804 static irqreturn_t tg3_msi(int irq, void *dev_id)
4805 {
4806         struct tg3_napi *tnapi = dev_id;
4807         struct tg3 *tp = tnapi->tp;
4808
4809         prefetch(tnapi->hw_status);
4810         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4811         /*
4812          * Writing any value to intr-mbox-0 clears PCI INTA# and
4813          * chip-internal interrupt pending events.
4814          * Writing non-zero to intr-mbox-0 additional tells the
4815          * NIC to stop sending us irqs, engaging "in-intr-handler"
4816          * event coalescing.
4817          */
4818         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4819         if (likely(!tg3_irq_sync(tp)))
4820                 napi_schedule(&tnapi->napi);
4821
4822         return IRQ_RETVAL(1);
4823 }
4824
4825 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4826 {
4827         struct tg3_napi *tnapi = dev_id;
4828         struct tg3 *tp = tnapi->tp;
4829         struct tg3_hw_status *sblk = tnapi->hw_status;
4830         unsigned int handled = 1;
4831
4832         /* In INTx mode, it is possible for the interrupt to arrive at
4833          * the CPU before the status block posted prior to the interrupt.
4834          * Reading the PCI State register will confirm whether the
4835          * interrupt is ours and will flush the status block.
4836          */
4837         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4838                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4839                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4840                         handled = 0;
4841                         goto out;
4842                 }
4843         }
4844
4845         /*
4846          * Writing any value to intr-mbox-0 clears PCI INTA# and
4847          * chip-internal interrupt pending events.
4848          * Writing non-zero to intr-mbox-0 additional tells the
4849          * NIC to stop sending us irqs, engaging "in-intr-handler"
4850          * event coalescing.
4851          *
4852          * Flush the mailbox to de-assert the IRQ immediately to prevent
4853          * spurious interrupts.  The flush impacts performance but
4854          * excessive spurious interrupts can be worse in some cases.
4855          */
4856         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4857         if (tg3_irq_sync(tp))
4858                 goto out;
4859         sblk->status &= ~SD_STATUS_UPDATED;
4860         if (likely(tg3_has_work(tnapi))) {
4861                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4862                 napi_schedule(&tnapi->napi);
4863         } else {
4864                 /* No work, shared interrupt perhaps?  re-enable
4865                  * interrupts, and flush that PCI write
4866                  */
4867                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4868                                0x00000000);
4869         }
4870 out:
4871         return IRQ_RETVAL(handled);
4872 }
4873
4874 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4875 {
4876         struct tg3_napi *tnapi = dev_id;
4877         struct tg3 *tp = tnapi->tp;
4878         struct tg3_hw_status *sblk = tnapi->hw_status;
4879         unsigned int handled = 1;
4880
4881         /* In INTx mode, it is possible for the interrupt to arrive at
4882          * the CPU before the status block posted prior to the interrupt.
4883          * Reading the PCI State register will confirm whether the
4884          * interrupt is ours and will flush the status block.
4885          */
4886         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4887                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4888                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4889                         handled = 0;
4890                         goto out;
4891                 }
4892         }
4893
4894         /*
4895          * writing any value to intr-mbox-0 clears PCI INTA# and
4896          * chip-internal interrupt pending events.
4897          * writing non-zero to intr-mbox-0 additional tells the
4898          * NIC to stop sending us irqs, engaging "in-intr-handler"
4899          * event coalescing.
4900          *
4901          * Flush the mailbox to de-assert the IRQ immediately to prevent
4902          * spurious interrupts.  The flush impacts performance but
4903          * excessive spurious interrupts can be worse in some cases.
4904          */
4905         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4906
4907         /*
4908          * In a shared interrupt configuration, sometimes other devices'
4909          * interrupts will scream.  We record the current status tag here
4910          * so that the above check can report that the screaming interrupts
4911          * are unhandled.  Eventually they will be silenced.
4912          */
4913         tnapi->last_irq_tag = sblk->status_tag;
4914
4915         if (tg3_irq_sync(tp))
4916                 goto out;
4917
4918         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4919
4920         napi_schedule(&tnapi->napi);
4921
4922 out:
4923         return IRQ_RETVAL(handled);
4924 }
4925
4926 /* ISR for interrupt test */
4927 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4928 {
4929         struct tg3_napi *tnapi = dev_id;
4930         struct tg3 *tp = tnapi->tp;
4931         struct tg3_hw_status *sblk = tnapi->hw_status;
4932
4933         if ((sblk->status & SD_STATUS_UPDATED) ||
4934             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4935                 tg3_disable_ints(tp);
4936                 return IRQ_RETVAL(1);
4937         }
4938         return IRQ_RETVAL(0);
4939 }
4940
4941 static int tg3_init_hw(struct tg3 *, int);
4942 static int tg3_halt(struct tg3 *, int, int);
4943
4944 /* Restart hardware after configuration changes, self-test, etc.
4945  * Invoked with tp->lock held.
4946  */
4947 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4948         __releases(tp->lock)
4949         __acquires(tp->lock)
4950 {
4951         int err;
4952
4953         err = tg3_init_hw(tp, reset_phy);
4954         if (err) {
4955                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4956                        "aborting.\n", tp->dev->name);
4957                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4958                 tg3_full_unlock(tp);
4959                 del_timer_sync(&tp->timer);
4960                 tp->irq_sync = 0;
4961                 napi_enable(&tp->napi[0].napi);
4962                 dev_close(tp->dev);
4963                 tg3_full_lock(tp, 0);
4964         }
4965         return err;
4966 }
4967
4968 #ifdef CONFIG_NET_POLL_CONTROLLER
4969 static void tg3_poll_controller(struct net_device *dev)
4970 {
4971         int i;
4972         struct tg3 *tp = netdev_priv(dev);
4973
4974         for (i = 0; i < tp->irq_cnt; i++)
4975                 tg3_interrupt(tp->napi[i].irq_vec, dev);
4976 }
4977 #endif
4978
4979 static void tg3_reset_task(struct work_struct *work)
4980 {
4981         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4982         int err;
4983         unsigned int restart_timer;
4984
4985         tg3_full_lock(tp, 0);
4986
4987         if (!netif_running(tp->dev)) {
4988                 tg3_full_unlock(tp);
4989                 return;
4990         }
4991
4992         tg3_full_unlock(tp);
4993
4994         tg3_phy_stop(tp);
4995
4996         tg3_netif_stop(tp);
4997
4998         tg3_full_lock(tp, 1);
4999
5000         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5001         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5002
5003         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5004                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5005                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5006                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5007                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5008         }
5009
5010         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5011         err = tg3_init_hw(tp, 1);
5012         if (err)
5013                 goto out;
5014
5015         tg3_netif_start(tp);
5016
5017         if (restart_timer)
5018                 mod_timer(&tp->timer, jiffies + 1);
5019
5020 out:
5021         tg3_full_unlock(tp);
5022
5023         if (!err)
5024                 tg3_phy_start(tp);
5025 }
5026
5027 static void tg3_dump_short_state(struct tg3 *tp)
5028 {
5029         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5030                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5031         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5032                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5033 }
5034
5035 static void tg3_tx_timeout(struct net_device *dev)
5036 {
5037         struct tg3 *tp = netdev_priv(dev);
5038
5039         if (netif_msg_tx_err(tp)) {
5040                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5041                        dev->name);
5042                 tg3_dump_short_state(tp);
5043         }
5044
5045         schedule_work(&tp->reset_task);
5046 }
5047
5048 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5049 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5050 {
5051         u32 base = (u32) mapping & 0xffffffff;
5052
5053         return ((base > 0xffffdcc0) &&
5054                 (base + len + 8 < base));
5055 }
5056
5057 /* Test for DMA addresses > 40-bit */
5058 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5059                                           int len)
5060 {
5061 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5062         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5063                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5064         return 0;
5065 #else
5066         return 0;
5067 #endif
5068 }
5069
5070 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5071
5072 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5073 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5074                                        u32 last_plus_one, u32 *start,
5075                                        u32 base_flags, u32 mss)
5076 {
5077         struct tg3_napi *tnapi = &tp->napi[0];
5078         struct sk_buff *new_skb;
5079         dma_addr_t new_addr = 0;
5080         u32 entry = *start;
5081         int i, ret = 0;
5082
5083         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5084                 new_skb = skb_copy(skb, GFP_ATOMIC);
5085         else {
5086                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5087
5088                 new_skb = skb_copy_expand(skb,
5089                                           skb_headroom(skb) + more_headroom,
5090                                           skb_tailroom(skb), GFP_ATOMIC);
5091         }
5092
5093         if (!new_skb) {
5094                 ret = -1;
5095         } else {
5096                 /* New SKB is guaranteed to be linear. */
5097                 entry = *start;
5098                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5099                 new_addr = skb_shinfo(new_skb)->dma_head;
5100
5101                 /* Make sure new skb does not cross any 4G boundaries.
5102                  * Drop the packet if it does.
5103                  */
5104                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5105                         if (!ret)
5106                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5107                                               DMA_TO_DEVICE);
5108                         ret = -1;
5109                         dev_kfree_skb(new_skb);
5110                         new_skb = NULL;
5111                 } else {
5112                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5113                                     base_flags, 1 | (mss << 1));
5114                         *start = NEXT_TX(entry);
5115                 }
5116         }
5117
5118         /* Now clean up the sw ring entries. */
5119         i = 0;
5120         while (entry != last_plus_one) {
5121                 if (i == 0)
5122                         tnapi->tx_buffers[entry].skb = new_skb;
5123                 else
5124                         tnapi->tx_buffers[entry].skb = NULL;
5125                 entry = NEXT_TX(entry);
5126                 i++;
5127         }
5128
5129         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5130         dev_kfree_skb(skb);
5131
5132         return ret;
5133 }
5134
5135 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5136                         dma_addr_t mapping, int len, u32 flags,
5137                         u32 mss_and_is_end)
5138 {
5139         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5140         int is_end = (mss_and_is_end & 0x1);
5141         u32 mss = (mss_and_is_end >> 1);
5142         u32 vlan_tag = 0;
5143
5144         if (is_end)
5145                 flags |= TXD_FLAG_END;
5146         if (flags & TXD_FLAG_VLAN) {
5147                 vlan_tag = flags >> 16;
5148                 flags &= 0xffff;
5149         }
5150         vlan_tag |= (mss << TXD_MSS_SHIFT);
5151
5152         txd->addr_hi = ((u64) mapping >> 32);
5153         txd->addr_lo = ((u64) mapping & 0xffffffff);
5154         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5155         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5156 }
5157
5158 /* hard_start_xmit for devices that don't have any bugs and
5159  * support TG3_FLG2_HW_TSO_2 only.
5160  */
5161 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5162                                   struct net_device *dev)
5163 {
5164         struct tg3 *tp = netdev_priv(dev);
5165         u32 len, entry, base_flags, mss;
5166         struct skb_shared_info *sp;
5167         dma_addr_t mapping;
5168         struct tg3_napi *tnapi;
5169         struct netdev_queue *txq;
5170
5171         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5172         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5173         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5174                 tnapi++;
5175
5176         /* We are running in BH disabled context with netif_tx_lock
5177          * and TX reclaim runs via tp->napi.poll inside of a software
5178          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5179          * no IRQ context deadlocks to worry about either.  Rejoice!
5180          */
5181         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5182                 if (!netif_tx_queue_stopped(txq)) {
5183                         netif_tx_stop_queue(txq);
5184
5185                         /* This is a hard error, log it. */
5186                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5187                                "queue awake!\n", dev->name);
5188                 }
5189                 return NETDEV_TX_BUSY;
5190         }
5191
5192         entry = tnapi->tx_prod;
5193         base_flags = 0;
5194         mss = 0;
5195         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5196                 int tcp_opt_len, ip_tcp_len;
5197
5198                 if (skb_header_cloned(skb) &&
5199                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5200                         dev_kfree_skb(skb);
5201                         goto out_unlock;
5202                 }
5203
5204                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5205                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5206                 else {
5207                         struct iphdr *iph = ip_hdr(skb);
5208
5209                         tcp_opt_len = tcp_optlen(skb);
5210                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5211
5212                         iph->check = 0;
5213                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5214                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5215                 }
5216
5217                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5218                                TXD_FLAG_CPU_POST_DMA);
5219
5220                 tcp_hdr(skb)->check = 0;
5221
5222         }
5223         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5224                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5225 #if TG3_VLAN_TAG_USED
5226         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5227                 base_flags |= (TXD_FLAG_VLAN |
5228                                (vlan_tx_tag_get(skb) << 16));
5229 #endif
5230
5231         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5232                 dev_kfree_skb(skb);
5233                 goto out_unlock;
5234         }
5235
5236         sp = skb_shinfo(skb);
5237
5238         mapping = sp->dma_head;
5239
5240         tnapi->tx_buffers[entry].skb = skb;
5241
5242         len = skb_headlen(skb);
5243
5244         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5245                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5246
5247         entry = NEXT_TX(entry);
5248
5249         /* Now loop through additional data fragments, and queue them. */
5250         if (skb_shinfo(skb)->nr_frags > 0) {
5251                 unsigned int i, last;
5252
5253                 last = skb_shinfo(skb)->nr_frags - 1;
5254                 for (i = 0; i <= last; i++) {
5255                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5256
5257                         len = frag->size;
5258                         mapping = sp->dma_maps[i];
5259                         tnapi->tx_buffers[entry].skb = NULL;
5260
5261                         tg3_set_txd(tnapi, entry, mapping, len,
5262                                     base_flags, (i == last) | (mss << 1));
5263
5264                         entry = NEXT_TX(entry);
5265                 }
5266         }
5267
5268         /* Packets are ready, update Tx producer idx local and on card. */
5269         tw32_tx_mbox(tnapi->prodmbox, entry);
5270
5271         tnapi->tx_prod = entry;
5272         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5273                 netif_tx_stop_queue(txq);
5274                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5275                         netif_tx_wake_queue(txq);
5276         }
5277
5278 out_unlock:
5279         mmiowb();
5280
5281         return NETDEV_TX_OK;
5282 }
5283
5284 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5285                                           struct net_device *);
5286
5287 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5288  * TSO header is greater than 80 bytes.
5289  */
5290 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5291 {
5292         struct sk_buff *segs, *nskb;
5293         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5294
5295         /* Estimate the number of fragments in the worst case */
5296         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5297                 netif_stop_queue(tp->dev);
5298                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5299                         return NETDEV_TX_BUSY;
5300
5301                 netif_wake_queue(tp->dev);
5302         }
5303
5304         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5305         if (IS_ERR(segs))
5306                 goto tg3_tso_bug_end;
5307
5308         do {
5309                 nskb = segs;
5310                 segs = segs->next;
5311                 nskb->next = NULL;
5312                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5313         } while (segs);
5314
5315 tg3_tso_bug_end:
5316         dev_kfree_skb(skb);
5317
5318         return NETDEV_TX_OK;
5319 }
5320
5321 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5322  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5323  */
5324 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5325                                           struct net_device *dev)
5326 {
5327         struct tg3 *tp = netdev_priv(dev);
5328         u32 len, entry, base_flags, mss;
5329         struct skb_shared_info *sp;
5330         int would_hit_hwbug;
5331         dma_addr_t mapping;
5332         struct tg3_napi *tnapi = &tp->napi[0];
5333
5334         len = skb_headlen(skb);
5335
5336         /* We are running in BH disabled context with netif_tx_lock
5337          * and TX reclaim runs via tp->napi.poll inside of a software
5338          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5339          * no IRQ context deadlocks to worry about either.  Rejoice!
5340          */
5341         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5342                 if (!netif_queue_stopped(dev)) {
5343                         netif_stop_queue(dev);
5344
5345                         /* This is a hard error, log it. */
5346                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5347                                "queue awake!\n", dev->name);
5348                 }
5349                 return NETDEV_TX_BUSY;
5350         }
5351
5352         entry = tnapi->tx_prod;
5353         base_flags = 0;
5354         if (skb->ip_summed == CHECKSUM_PARTIAL)
5355                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5356         mss = 0;
5357         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5358                 struct iphdr *iph;
5359                 int tcp_opt_len, ip_tcp_len, hdr_len;
5360
5361                 if (skb_header_cloned(skb) &&
5362                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5363                         dev_kfree_skb(skb);
5364                         goto out_unlock;
5365                 }
5366
5367                 tcp_opt_len = tcp_optlen(skb);
5368                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5369
5370                 hdr_len = ip_tcp_len + tcp_opt_len;
5371                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5372                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5373                         return (tg3_tso_bug(tp, skb));
5374
5375                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5376                                TXD_FLAG_CPU_POST_DMA);
5377
5378                 iph = ip_hdr(skb);
5379                 iph->check = 0;
5380                 iph->tot_len = htons(mss + hdr_len);
5381                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5382                         tcp_hdr(skb)->check = 0;
5383                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5384                 } else
5385                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5386                                                                  iph->daddr, 0,
5387                                                                  IPPROTO_TCP,
5388                                                                  0);
5389
5390                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5391                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5392                         if (tcp_opt_len || iph->ihl > 5) {
5393                                 int tsflags;
5394
5395                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5396                                 mss |= (tsflags << 11);
5397                         }
5398                 } else {
5399                         if (tcp_opt_len || iph->ihl > 5) {
5400                                 int tsflags;
5401
5402                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5403                                 base_flags |= tsflags << 12;
5404                         }
5405                 }
5406         }
5407 #if TG3_VLAN_TAG_USED
5408         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5409                 base_flags |= (TXD_FLAG_VLAN |
5410                                (vlan_tx_tag_get(skb) << 16));
5411 #endif
5412
5413         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5414                 dev_kfree_skb(skb);
5415                 goto out_unlock;
5416         }
5417
5418         sp = skb_shinfo(skb);
5419
5420         mapping = sp->dma_head;
5421
5422         tnapi->tx_buffers[entry].skb = skb;
5423
5424         would_hit_hwbug = 0;
5425
5426         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5427                 would_hit_hwbug = 1;
5428         else if (tg3_4g_overflow_test(mapping, len))
5429                 would_hit_hwbug = 1;
5430
5431         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5432                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5433
5434         entry = NEXT_TX(entry);
5435
5436         /* Now loop through additional data fragments, and queue them. */
5437         if (skb_shinfo(skb)->nr_frags > 0) {
5438                 unsigned int i, last;
5439
5440                 last = skb_shinfo(skb)->nr_frags - 1;
5441                 for (i = 0; i <= last; i++) {
5442                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5443
5444                         len = frag->size;
5445                         mapping = sp->dma_maps[i];
5446
5447                         tnapi->tx_buffers[entry].skb = NULL;
5448
5449                         if (tg3_4g_overflow_test(mapping, len))
5450                                 would_hit_hwbug = 1;
5451
5452                         if (tg3_40bit_overflow_test(tp, mapping, len))
5453                                 would_hit_hwbug = 1;
5454
5455                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5456                                 tg3_set_txd(tnapi, entry, mapping, len,
5457                                             base_flags, (i == last)|(mss << 1));
5458                         else
5459                                 tg3_set_txd(tnapi, entry, mapping, len,
5460                                             base_flags, (i == last));
5461
5462                         entry = NEXT_TX(entry);
5463                 }
5464         }
5465
5466         if (would_hit_hwbug) {
5467                 u32 last_plus_one = entry;
5468                 u32 start;
5469
5470                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5471                 start &= (TG3_TX_RING_SIZE - 1);
5472
5473                 /* If the workaround fails due to memory/mapping
5474                  * failure, silently drop this packet.
5475                  */
5476                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5477                                                 &start, base_flags, mss))
5478                         goto out_unlock;
5479
5480                 entry = start;
5481         }
5482
5483         /* Packets are ready, update Tx producer idx local and on card. */
5484         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5485
5486         tnapi->tx_prod = entry;
5487         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5488                 netif_stop_queue(dev);
5489                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5490                         netif_wake_queue(tp->dev);
5491         }
5492
5493 out_unlock:
5494         mmiowb();
5495
5496         return NETDEV_TX_OK;
5497 }
5498
5499 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5500                                int new_mtu)
5501 {
5502         dev->mtu = new_mtu;
5503
5504         if (new_mtu > ETH_DATA_LEN) {
5505                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5506                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5507                         ethtool_op_set_tso(dev, 0);
5508                 }
5509                 else
5510                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5511         } else {
5512                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5513                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5514                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5515         }
5516 }
5517
5518 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5519 {
5520         struct tg3 *tp = netdev_priv(dev);
5521         int err;
5522
5523         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5524                 return -EINVAL;
5525
5526         if (!netif_running(dev)) {
5527                 /* We'll just catch it later when the
5528                  * device is up'd.
5529                  */
5530                 tg3_set_mtu(dev, tp, new_mtu);
5531                 return 0;
5532         }
5533
5534         tg3_phy_stop(tp);
5535
5536         tg3_netif_stop(tp);
5537
5538         tg3_full_lock(tp, 1);
5539
5540         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5541
5542         tg3_set_mtu(dev, tp, new_mtu);
5543
5544         err = tg3_restart_hw(tp, 0);
5545
5546         if (!err)
5547                 tg3_netif_start(tp);
5548
5549         tg3_full_unlock(tp);
5550
5551         if (!err)
5552                 tg3_phy_start(tp);
5553
5554         return err;
5555 }
5556
5557 static void tg3_rx_prodring_free(struct tg3 *tp,
5558                                  struct tg3_rx_prodring_set *tpr)
5559 {
5560         int i;
5561         struct ring_info *rxp;
5562
5563         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5564                 rxp = &tpr->rx_std_buffers[i];
5565
5566                 if (rxp->skb == NULL)
5567                         continue;
5568
5569                 pci_unmap_single(tp->pdev,
5570                                  pci_unmap_addr(rxp, mapping),
5571                                  tp->rx_pkt_map_sz,
5572                                  PCI_DMA_FROMDEVICE);
5573                 dev_kfree_skb_any(rxp->skb);
5574                 rxp->skb = NULL;
5575         }
5576
5577         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5578                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5579                         rxp = &tpr->rx_jmb_buffers[i];
5580
5581                         if (rxp->skb == NULL)
5582                                 continue;
5583
5584                         pci_unmap_single(tp->pdev,
5585                                          pci_unmap_addr(rxp, mapping),
5586                                          TG3_RX_JMB_MAP_SZ,
5587                                          PCI_DMA_FROMDEVICE);
5588                         dev_kfree_skb_any(rxp->skb);
5589                         rxp->skb = NULL;
5590                 }
5591         }
5592 }
5593
5594 /* Initialize tx/rx rings for packet processing.
5595  *
5596  * The chip has been shut down and the driver detached from
5597  * the networking, so no interrupts or new tx packets will
5598  * end up in the driver.  tp->{tx,}lock are held and thus
5599  * we may not sleep.
5600  */
5601 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5602                                  struct tg3_rx_prodring_set *tpr)
5603 {
5604         u32 i, rx_pkt_dma_sz;
5605         struct tg3_napi *tnapi = &tp->napi[0];
5606
5607         /* Zero out all descriptors. */
5608         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5609
5610         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5611         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5612             tp->dev->mtu > ETH_DATA_LEN)
5613                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5614         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5615
5616         /* Initialize invariants of the rings, we only set this
5617          * stuff once.  This works because the card does not
5618          * write into the rx buffer posting rings.
5619          */
5620         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5621                 struct tg3_rx_buffer_desc *rxd;
5622
5623                 rxd = &tpr->rx_std[i];
5624                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5625                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5626                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5627                                (i << RXD_OPAQUE_INDEX_SHIFT));
5628         }
5629
5630         /* Now allocate fresh SKBs for each rx ring. */
5631         for (i = 0; i < tp->rx_pending; i++) {
5632                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5633                         printk(KERN_WARNING PFX
5634                                "%s: Using a smaller RX standard ring, "
5635                                "only %d out of %d buffers were allocated "
5636                                "successfully.\n",
5637                                tp->dev->name, i, tp->rx_pending);
5638                         if (i == 0)
5639                                 goto initfail;
5640                         tp->rx_pending = i;
5641                         break;
5642                 }
5643         }
5644
5645         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5646                 goto done;
5647
5648         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5649
5650         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5651                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5652                         struct tg3_rx_buffer_desc *rxd;
5653
5654                         rxd = &tpr->rx_jmb[i].std;
5655                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5656                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5657                                 RXD_FLAG_JUMBO;
5658                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5659                                (i << RXD_OPAQUE_INDEX_SHIFT));
5660                 }
5661
5662                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5663                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5664                                              -1, i) < 0) {
5665                                 printk(KERN_WARNING PFX
5666                                        "%s: Using a smaller RX jumbo ring, "
5667                                        "only %d out of %d buffers were "
5668                                        "allocated successfully.\n",
5669                                        tp->dev->name, i, tp->rx_jumbo_pending);
5670                                 if (i == 0)
5671                                         goto initfail;
5672                                 tp->rx_jumbo_pending = i;
5673                                 break;
5674                         }
5675                 }
5676         }
5677
5678 done:
5679         return 0;
5680
5681 initfail:
5682         tg3_rx_prodring_free(tp, tpr);
5683         return -ENOMEM;
5684 }
5685
5686 static void tg3_rx_prodring_fini(struct tg3 *tp,
5687                                  struct tg3_rx_prodring_set *tpr)
5688 {
5689         kfree(tpr->rx_std_buffers);
5690         tpr->rx_std_buffers = NULL;
5691         kfree(tpr->rx_jmb_buffers);
5692         tpr->rx_jmb_buffers = NULL;
5693         if (tpr->rx_std) {
5694                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5695                                     tpr->rx_std, tpr->rx_std_mapping);
5696                 tpr->rx_std = NULL;
5697         }
5698         if (tpr->rx_jmb) {
5699                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5700                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5701                 tpr->rx_jmb = NULL;
5702         }
5703 }
5704
5705 static int tg3_rx_prodring_init(struct tg3 *tp,
5706                                 struct tg3_rx_prodring_set *tpr)
5707 {
5708         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5709                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5710         if (!tpr->rx_std_buffers)
5711                 return -ENOMEM;
5712
5713         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5714                                            &tpr->rx_std_mapping);
5715         if (!tpr->rx_std)
5716                 goto err_out;
5717
5718         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5719                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5720                                               TG3_RX_JUMBO_RING_SIZE,
5721                                               GFP_KERNEL);
5722                 if (!tpr->rx_jmb_buffers)
5723                         goto err_out;
5724
5725                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5726                                                    TG3_RX_JUMBO_RING_BYTES,
5727                                                    &tpr->rx_jmb_mapping);
5728                 if (!tpr->rx_jmb)
5729                         goto err_out;
5730         }
5731
5732         return 0;
5733
5734 err_out:
5735         tg3_rx_prodring_fini(tp, tpr);
5736         return -ENOMEM;
5737 }
5738
5739 /* Free up pending packets in all rx/tx rings.
5740  *
5741  * The chip has been shut down and the driver detached from
5742  * the networking, so no interrupts or new tx packets will
5743  * end up in the driver.  tp->{tx,}lock is not held and we are not
5744  * in an interrupt context and thus may sleep.
5745  */
5746 static void tg3_free_rings(struct tg3 *tp)
5747 {
5748         int i, j;
5749
5750         for (j = 0; j < tp->irq_cnt; j++) {
5751                 struct tg3_napi *tnapi = &tp->napi[j];
5752
5753                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5754                         struct tx_ring_info *txp;
5755                         struct sk_buff *skb;
5756
5757                         txp = &tnapi->tx_buffers[i];
5758                         skb = txp->skb;
5759
5760                         if (skb == NULL) {
5761                                 i++;
5762                                 continue;
5763                         }
5764
5765                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5766
5767                         txp->skb = NULL;
5768
5769                         i += skb_shinfo(skb)->nr_frags + 1;
5770
5771                         dev_kfree_skb_any(skb);
5772                 }
5773         }
5774
5775         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5776 }
5777
5778 /* Initialize tx/rx rings for packet processing.
5779  *
5780  * The chip has been shut down and the driver detached from
5781  * the networking, so no interrupts or new tx packets will
5782  * end up in the driver.  tp->{tx,}lock are held and thus
5783  * we may not sleep.
5784  */
5785 static int tg3_init_rings(struct tg3 *tp)
5786 {
5787         int i;
5788
5789         /* Free up all the SKBs. */
5790         tg3_free_rings(tp);
5791
5792         for (i = 0; i < tp->irq_cnt; i++) {
5793                 struct tg3_napi *tnapi = &tp->napi[i];
5794
5795                 tnapi->last_tag = 0;
5796                 tnapi->last_irq_tag = 0;
5797                 tnapi->hw_status->status = 0;
5798                 tnapi->hw_status->status_tag = 0;
5799                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5800
5801                 tnapi->tx_prod = 0;
5802                 tnapi->tx_cons = 0;
5803                 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5804
5805                 tnapi->rx_rcb_ptr = 0;
5806                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5807         }
5808
5809         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5810 }
5811
5812 /*
5813  * Must not be invoked with interrupt sources disabled and
5814  * the hardware shutdown down.
5815  */
5816 static void tg3_free_consistent(struct tg3 *tp)
5817 {
5818         int i;
5819
5820         for (i = 0; i < tp->irq_cnt; i++) {
5821                 struct tg3_napi *tnapi = &tp->napi[i];
5822
5823                 if (tnapi->tx_ring) {
5824                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5825                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5826                         tnapi->tx_ring = NULL;
5827                 }
5828
5829                 kfree(tnapi->tx_buffers);
5830                 tnapi->tx_buffers = NULL;
5831
5832                 if (tnapi->rx_rcb) {
5833                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5834                                             tnapi->rx_rcb,
5835                                             tnapi->rx_rcb_mapping);
5836                         tnapi->rx_rcb = NULL;
5837                 }
5838
5839                 if (tnapi->hw_status) {
5840                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5841                                             tnapi->hw_status,
5842                                             tnapi->status_mapping);
5843                         tnapi->hw_status = NULL;
5844                 }
5845         }
5846
5847         if (tp->hw_stats) {
5848                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5849                                     tp->hw_stats, tp->stats_mapping);
5850                 tp->hw_stats = NULL;
5851         }
5852
5853         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5854 }
5855
5856 /*
5857  * Must not be invoked with interrupt sources disabled and
5858  * the hardware shutdown down.  Can sleep.
5859  */
5860 static int tg3_alloc_consistent(struct tg3 *tp)
5861 {
5862         int i;
5863
5864         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5865                 return -ENOMEM;
5866
5867         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5868                                             sizeof(struct tg3_hw_stats),
5869                                             &tp->stats_mapping);
5870         if (!tp->hw_stats)
5871                 goto err_out;
5872
5873         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5874
5875         for (i = 0; i < tp->irq_cnt; i++) {
5876                 struct tg3_napi *tnapi = &tp->napi[i];
5877
5878                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5879                                                         TG3_HW_STATUS_SIZE,
5880                                                         &tnapi->status_mapping);
5881                 if (!tnapi->hw_status)
5882                         goto err_out;
5883
5884                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5885
5886                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5887                                                      TG3_RX_RCB_RING_BYTES(tp),
5888                                                      &tnapi->rx_rcb_mapping);
5889                 if (!tnapi->rx_rcb)
5890                         goto err_out;
5891
5892                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5893
5894                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5895                                             TG3_TX_RING_SIZE, GFP_KERNEL);
5896                 if (!tnapi->tx_buffers)
5897                         goto err_out;
5898
5899                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
5900                                                       TG3_TX_RING_BYTES,
5901                                                       &tnapi->tx_desc_mapping);
5902                 if (!tnapi->tx_ring)
5903                         goto err_out;
5904         }
5905
5906         return 0;
5907
5908 err_out:
5909         tg3_free_consistent(tp);
5910         return -ENOMEM;
5911 }
5912
5913 #define MAX_WAIT_CNT 1000
5914
5915 /* To stop a block, clear the enable bit and poll till it
5916  * clears.  tp->lock is held.
5917  */
5918 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5919 {
5920         unsigned int i;
5921         u32 val;
5922
5923         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5924                 switch (ofs) {
5925                 case RCVLSC_MODE:
5926                 case DMAC_MODE:
5927                 case MBFREE_MODE:
5928                 case BUFMGR_MODE:
5929                 case MEMARB_MODE:
5930                         /* We can't enable/disable these bits of the
5931                          * 5705/5750, just say success.
5932                          */
5933                         return 0;
5934
5935                 default:
5936                         break;
5937                 }
5938         }
5939
5940         val = tr32(ofs);
5941         val &= ~enable_bit;
5942         tw32_f(ofs, val);
5943
5944         for (i = 0; i < MAX_WAIT_CNT; i++) {
5945                 udelay(100);
5946                 val = tr32(ofs);
5947                 if ((val & enable_bit) == 0)
5948                         break;
5949         }
5950
5951         if (i == MAX_WAIT_CNT && !silent) {
5952                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5953                        "ofs=%lx enable_bit=%x\n",
5954                        ofs, enable_bit);
5955                 return -ENODEV;
5956         }
5957
5958         return 0;
5959 }
5960
5961 /* tp->lock is held. */
5962 static int tg3_abort_hw(struct tg3 *tp, int silent)
5963 {
5964         int i, err;
5965
5966         tg3_disable_ints(tp);
5967
5968         tp->rx_mode &= ~RX_MODE_ENABLE;
5969         tw32_f(MAC_RX_MODE, tp->rx_mode);
5970         udelay(10);
5971
5972         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5973         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5974         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5975         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5976         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5977         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5978
5979         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5980         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5981         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5982         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5983         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5984         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5985         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5986
5987         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5988         tw32_f(MAC_MODE, tp->mac_mode);
5989         udelay(40);
5990
5991         tp->tx_mode &= ~TX_MODE_ENABLE;
5992         tw32_f(MAC_TX_MODE, tp->tx_mode);
5993
5994         for (i = 0; i < MAX_WAIT_CNT; i++) {
5995                 udelay(100);
5996                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5997                         break;
5998         }
5999         if (i >= MAX_WAIT_CNT) {
6000                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6001                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6002                        tp->dev->name, tr32(MAC_TX_MODE));
6003                 err |= -ENODEV;
6004         }
6005
6006         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6007         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6008         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6009
6010         tw32(FTQ_RESET, 0xffffffff);
6011         tw32(FTQ_RESET, 0x00000000);
6012
6013         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6014         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6015
6016         for (i = 0; i < tp->irq_cnt; i++) {
6017                 struct tg3_napi *tnapi = &tp->napi[i];
6018                 if (tnapi->hw_status)
6019                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6020         }
6021         if (tp->hw_stats)
6022                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6023
6024         return err;
6025 }
6026
6027 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6028 {
6029         int i;
6030         u32 apedata;
6031
6032         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6033         if (apedata != APE_SEG_SIG_MAGIC)
6034                 return;
6035
6036         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6037         if (!(apedata & APE_FW_STATUS_READY))
6038                 return;
6039
6040         /* Wait for up to 1 millisecond for APE to service previous event. */
6041         for (i = 0; i < 10; i++) {
6042                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6043                         return;
6044
6045                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6046
6047                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6048                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6049                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6050
6051                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6052
6053                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6054                         break;
6055
6056                 udelay(100);
6057         }
6058
6059         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6060                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6061 }
6062
6063 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6064 {
6065         u32 event;
6066         u32 apedata;
6067
6068         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6069                 return;
6070
6071         switch (kind) {
6072                 case RESET_KIND_INIT:
6073                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6074                                         APE_HOST_SEG_SIG_MAGIC);
6075                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6076                                         APE_HOST_SEG_LEN_MAGIC);
6077                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6078                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6079                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6080                                         APE_HOST_DRIVER_ID_MAGIC);
6081                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6082                                         APE_HOST_BEHAV_NO_PHYLOCK);
6083
6084                         event = APE_EVENT_STATUS_STATE_START;
6085                         break;
6086                 case RESET_KIND_SHUTDOWN:
6087                         /* With the interface we are currently using,
6088                          * APE does not track driver state.  Wiping
6089                          * out the HOST SEGMENT SIGNATURE forces
6090                          * the APE to assume OS absent status.
6091                          */
6092                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6093
6094                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6095                         break;
6096                 case RESET_KIND_SUSPEND:
6097                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6098                         break;
6099                 default:
6100                         return;
6101         }
6102
6103         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6104
6105         tg3_ape_send_event(tp, event);
6106 }
6107
6108 /* tp->lock is held. */
6109 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6110 {
6111         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6112                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6113
6114         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6115                 switch (kind) {
6116                 case RESET_KIND_INIT:
6117                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6118                                       DRV_STATE_START);
6119                         break;
6120
6121                 case RESET_KIND_SHUTDOWN:
6122                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6123                                       DRV_STATE_UNLOAD);
6124                         break;
6125
6126                 case RESET_KIND_SUSPEND:
6127                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6128                                       DRV_STATE_SUSPEND);
6129                         break;
6130
6131                 default:
6132                         break;
6133                 }
6134         }
6135
6136         if (kind == RESET_KIND_INIT ||
6137             kind == RESET_KIND_SUSPEND)
6138                 tg3_ape_driver_state_change(tp, kind);
6139 }
6140
6141 /* tp->lock is held. */
6142 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6143 {
6144         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6145                 switch (kind) {
6146                 case RESET_KIND_INIT:
6147                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6148                                       DRV_STATE_START_DONE);
6149                         break;
6150
6151                 case RESET_KIND_SHUTDOWN:
6152                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6153                                       DRV_STATE_UNLOAD_DONE);
6154                         break;
6155
6156                 default:
6157                         break;
6158                 }
6159         }
6160
6161         if (kind == RESET_KIND_SHUTDOWN)
6162                 tg3_ape_driver_state_change(tp, kind);
6163 }
6164
6165 /* tp->lock is held. */
6166 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6167 {
6168         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6169                 switch (kind) {
6170                 case RESET_KIND_INIT:
6171                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6172                                       DRV_STATE_START);
6173                         break;
6174
6175                 case RESET_KIND_SHUTDOWN:
6176                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6177                                       DRV_STATE_UNLOAD);
6178                         break;
6179
6180                 case RESET_KIND_SUSPEND:
6181                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6182                                       DRV_STATE_SUSPEND);
6183                         break;
6184
6185                 default:
6186                         break;
6187                 }
6188         }
6189 }
6190
6191 static int tg3_poll_fw(struct tg3 *tp)
6192 {
6193         int i;
6194         u32 val;
6195
6196         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6197                 /* Wait up to 20ms for init done. */
6198                 for (i = 0; i < 200; i++) {
6199                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6200                                 return 0;
6201                         udelay(100);
6202                 }
6203                 return -ENODEV;
6204         }
6205
6206         /* Wait for firmware initialization to complete. */
6207         for (i = 0; i < 100000; i++) {
6208                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6209                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6210                         break;
6211                 udelay(10);
6212         }
6213
6214         /* Chip might not be fitted with firmware.  Some Sun onboard
6215          * parts are configured like that.  So don't signal the timeout
6216          * of the above loop as an error, but do report the lack of
6217          * running firmware once.
6218          */
6219         if (i >= 100000 &&
6220             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6221                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6222
6223                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6224                        tp->dev->name);
6225         }
6226
6227         return 0;
6228 }
6229
6230 /* Save PCI command register before chip reset */
6231 static void tg3_save_pci_state(struct tg3 *tp)
6232 {
6233         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6234 }
6235
6236 /* Restore PCI state after chip reset */
6237 static void tg3_restore_pci_state(struct tg3 *tp)
6238 {
6239         u32 val;
6240
6241         /* Re-enable indirect register accesses. */
6242         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6243                                tp->misc_host_ctrl);
6244
6245         /* Set MAX PCI retry to zero. */
6246         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6247         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6248             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6249                 val |= PCISTATE_RETRY_SAME_DMA;
6250         /* Allow reads and writes to the APE register and memory space. */
6251         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6252                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6253                        PCISTATE_ALLOW_APE_SHMEM_WR;
6254         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6255
6256         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6257
6258         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6259                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6260                         pcie_set_readrq(tp->pdev, 4096);
6261                 else {
6262                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6263                                               tp->pci_cacheline_sz);
6264                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6265                                               tp->pci_lat_timer);
6266                 }
6267         }
6268
6269         /* Make sure PCI-X relaxed ordering bit is clear. */
6270         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6271                 u16 pcix_cmd;
6272
6273                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6274                                      &pcix_cmd);
6275                 pcix_cmd &= ~PCI_X_CMD_ERO;
6276                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6277                                       pcix_cmd);
6278         }
6279
6280         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6281
6282                 /* Chip reset on 5780 will reset MSI enable bit,
6283                  * so need to restore it.
6284                  */
6285                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6286                         u16 ctrl;
6287
6288                         pci_read_config_word(tp->pdev,
6289                                              tp->msi_cap + PCI_MSI_FLAGS,
6290                                              &ctrl);
6291                         pci_write_config_word(tp->pdev,
6292                                               tp->msi_cap + PCI_MSI_FLAGS,
6293                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6294                         val = tr32(MSGINT_MODE);
6295                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6296                 }
6297         }
6298 }
6299
6300 static void tg3_stop_fw(struct tg3 *);
6301
6302 /* tp->lock is held. */
6303 static int tg3_chip_reset(struct tg3 *tp)
6304 {
6305         u32 val;
6306         void (*write_op)(struct tg3 *, u32, u32);
6307         int i, err;
6308
6309         tg3_nvram_lock(tp);
6310
6311         tg3_mdio_stop(tp);
6312
6313         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6314
6315         /* No matching tg3_nvram_unlock() after this because
6316          * chip reset below will undo the nvram lock.
6317          */
6318         tp->nvram_lock_cnt = 0;
6319
6320         /* GRC_MISC_CFG core clock reset will clear the memory
6321          * enable bit in PCI register 4 and the MSI enable bit
6322          * on some chips, so we save relevant registers here.
6323          */
6324         tg3_save_pci_state(tp);
6325
6326         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6327             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6328                 tw32(GRC_FASTBOOT_PC, 0);
6329
6330         /*
6331          * We must avoid the readl() that normally takes place.
6332          * It locks machines, causes machine checks, and other
6333          * fun things.  So, temporarily disable the 5701
6334          * hardware workaround, while we do the reset.
6335          */
6336         write_op = tp->write32;
6337         if (write_op == tg3_write_flush_reg32)
6338                 tp->write32 = tg3_write32;
6339
6340         /* Prevent the irq handler from reading or writing PCI registers
6341          * during chip reset when the memory enable bit in the PCI command
6342          * register may be cleared.  The chip does not generate interrupt
6343          * at this time, but the irq handler may still be called due to irq
6344          * sharing or irqpoll.
6345          */
6346         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6347         for (i = 0; i < tp->irq_cnt; i++) {
6348                 struct tg3_napi *tnapi = &tp->napi[i];
6349                 if (tnapi->hw_status) {
6350                         tnapi->hw_status->status = 0;
6351                         tnapi->hw_status->status_tag = 0;
6352                 }
6353                 tnapi->last_tag = 0;
6354                 tnapi->last_irq_tag = 0;
6355         }
6356         smp_mb();
6357
6358         for (i = 0; i < tp->irq_cnt; i++)
6359                 synchronize_irq(tp->napi[i].irq_vec);
6360
6361         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6362                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6363                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6364         }
6365
6366         /* do the reset */
6367         val = GRC_MISC_CFG_CORECLK_RESET;
6368
6369         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6370                 if (tr32(0x7e2c) == 0x60) {
6371                         tw32(0x7e2c, 0x20);
6372                 }
6373                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6374                         tw32(GRC_MISC_CFG, (1 << 29));
6375                         val |= (1 << 29);
6376                 }
6377         }
6378
6379         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6380                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6381                 tw32(GRC_VCPU_EXT_CTRL,
6382                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6383         }
6384
6385         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6386                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6387         tw32(GRC_MISC_CFG, val);
6388
6389         /* restore 5701 hardware bug workaround write method */
6390         tp->write32 = write_op;
6391
6392         /* Unfortunately, we have to delay before the PCI read back.
6393          * Some 575X chips even will not respond to a PCI cfg access
6394          * when the reset command is given to the chip.
6395          *
6396          * How do these hardware designers expect things to work
6397          * properly if the PCI write is posted for a long period
6398          * of time?  It is always necessary to have some method by
6399          * which a register read back can occur to push the write
6400          * out which does the reset.
6401          *
6402          * For most tg3 variants the trick below was working.
6403          * Ho hum...
6404          */
6405         udelay(120);
6406
6407         /* Flush PCI posted writes.  The normal MMIO registers
6408          * are inaccessible at this time so this is the only
6409          * way to make this reliably (actually, this is no longer
6410          * the case, see above).  I tried to use indirect
6411          * register read/write but this upset some 5701 variants.
6412          */
6413         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6414
6415         udelay(120);
6416
6417         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6418                 u16 val16;
6419
6420                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6421                         int i;
6422                         u32 cfg_val;
6423
6424                         /* Wait for link training to complete.  */
6425                         for (i = 0; i < 5000; i++)
6426                                 udelay(100);
6427
6428                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6429                         pci_write_config_dword(tp->pdev, 0xc4,
6430                                                cfg_val | (1 << 15));
6431                 }
6432
6433                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6434                 pci_read_config_word(tp->pdev,
6435                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6436                                      &val16);
6437                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6438                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6439                 /*
6440                  * Older PCIe devices only support the 128 byte
6441                  * MPS setting.  Enforce the restriction.
6442                  */
6443                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6444                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6445                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6446                 pci_write_config_word(tp->pdev,
6447                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6448                                       val16);
6449
6450                 pcie_set_readrq(tp->pdev, 4096);
6451
6452                 /* Clear error status */
6453                 pci_write_config_word(tp->pdev,
6454                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6455                                       PCI_EXP_DEVSTA_CED |
6456                                       PCI_EXP_DEVSTA_NFED |
6457                                       PCI_EXP_DEVSTA_FED |
6458                                       PCI_EXP_DEVSTA_URD);
6459         }
6460
6461         tg3_restore_pci_state(tp);
6462
6463         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6464
6465         val = 0;
6466         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6467                 val = tr32(MEMARB_MODE);
6468         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6469
6470         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6471                 tg3_stop_fw(tp);
6472                 tw32(0x5000, 0x400);
6473         }
6474
6475         tw32(GRC_MODE, tp->grc_mode);
6476
6477         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6478                 val = tr32(0xc4);
6479
6480                 tw32(0xc4, val | (1 << 15));
6481         }
6482
6483         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6484             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6485                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6486                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6487                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6488                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6489         }
6490
6491         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6492                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6493                 tw32_f(MAC_MODE, tp->mac_mode);
6494         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6495                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6496                 tw32_f(MAC_MODE, tp->mac_mode);
6497         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6498                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6499                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6500                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6501                 tw32_f(MAC_MODE, tp->mac_mode);
6502         } else
6503                 tw32_f(MAC_MODE, 0);
6504         udelay(40);
6505
6506         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6507
6508         err = tg3_poll_fw(tp);
6509         if (err)
6510                 return err;
6511
6512         tg3_mdio_start(tp);
6513
6514         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6515             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6516                 val = tr32(0x7c00);
6517
6518                 tw32(0x7c00, val | (1 << 25));
6519         }
6520
6521         /* Reprobe ASF enable state.  */
6522         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6523         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6524         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6525         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6526                 u32 nic_cfg;
6527
6528                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6529                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6530                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6531                         tp->last_event_jiffies = jiffies;
6532                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6533                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6534                 }
6535         }
6536
6537         return 0;
6538 }
6539
6540 /* tp->lock is held. */
6541 static void tg3_stop_fw(struct tg3 *tp)
6542 {
6543         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6544            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6545                 /* Wait for RX cpu to ACK the previous event. */
6546                 tg3_wait_for_event_ack(tp);
6547
6548                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6549
6550                 tg3_generate_fw_event(tp);
6551
6552                 /* Wait for RX cpu to ACK this event. */
6553                 tg3_wait_for_event_ack(tp);
6554         }
6555 }
6556
6557 /* tp->lock is held. */
6558 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6559 {
6560         int err;
6561
6562         tg3_stop_fw(tp);
6563
6564         tg3_write_sig_pre_reset(tp, kind);
6565
6566         tg3_abort_hw(tp, silent);
6567         err = tg3_chip_reset(tp);
6568
6569         __tg3_set_mac_addr(tp, 0);
6570
6571         tg3_write_sig_legacy(tp, kind);
6572         tg3_write_sig_post_reset(tp, kind);
6573
6574         if (err)
6575                 return err;
6576
6577         return 0;
6578 }
6579
6580 #define RX_CPU_SCRATCH_BASE     0x30000
6581 #define RX_CPU_SCRATCH_SIZE     0x04000
6582 #define TX_CPU_SCRATCH_BASE     0x34000
6583 #define TX_CPU_SCRATCH_SIZE     0x04000
6584
6585 /* tp->lock is held. */
6586 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6587 {
6588         int i;
6589
6590         BUG_ON(offset == TX_CPU_BASE &&
6591             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6592
6593         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6594                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6595
6596                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6597                 return 0;
6598         }
6599         if (offset == RX_CPU_BASE) {
6600                 for (i = 0; i < 10000; i++) {
6601                         tw32(offset + CPU_STATE, 0xffffffff);
6602                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6603                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6604                                 break;
6605                 }
6606
6607                 tw32(offset + CPU_STATE, 0xffffffff);
6608                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6609                 udelay(10);
6610         } else {
6611                 for (i = 0; i < 10000; i++) {
6612                         tw32(offset + CPU_STATE, 0xffffffff);
6613                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6614                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6615                                 break;
6616                 }
6617         }
6618
6619         if (i >= 10000) {
6620                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6621                        "and %s CPU\n",
6622                        tp->dev->name,
6623                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6624                 return -ENODEV;
6625         }
6626
6627         /* Clear firmware's nvram arbitration. */
6628         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6629                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6630         return 0;
6631 }
6632
6633 struct fw_info {
6634         unsigned int fw_base;
6635         unsigned int fw_len;
6636         const __be32 *fw_data;
6637 };
6638
6639 /* tp->lock is held. */
6640 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6641                                  int cpu_scratch_size, struct fw_info *info)
6642 {
6643         int err, lock_err, i;
6644         void (*write_op)(struct tg3 *, u32, u32);
6645
6646         if (cpu_base == TX_CPU_BASE &&
6647             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6648                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6649                        "TX cpu firmware on %s which is 5705.\n",
6650                        tp->dev->name);
6651                 return -EINVAL;
6652         }
6653
6654         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6655                 write_op = tg3_write_mem;
6656         else
6657                 write_op = tg3_write_indirect_reg32;
6658
6659         /* It is possible that bootcode is still loading at this point.
6660          * Get the nvram lock first before halting the cpu.
6661          */
6662         lock_err = tg3_nvram_lock(tp);
6663         err = tg3_halt_cpu(tp, cpu_base);
6664         if (!lock_err)
6665                 tg3_nvram_unlock(tp);
6666         if (err)
6667                 goto out;
6668
6669         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6670                 write_op(tp, cpu_scratch_base + i, 0);
6671         tw32(cpu_base + CPU_STATE, 0xffffffff);
6672         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6673         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6674                 write_op(tp, (cpu_scratch_base +
6675                               (info->fw_base & 0xffff) +
6676                               (i * sizeof(u32))),
6677                               be32_to_cpu(info->fw_data[i]));
6678
6679         err = 0;
6680
6681 out:
6682         return err;
6683 }
6684
6685 /* tp->lock is held. */
6686 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6687 {
6688         struct fw_info info;
6689         const __be32 *fw_data;
6690         int err, i;
6691
6692         fw_data = (void *)tp->fw->data;
6693
6694         /* Firmware blob starts with version numbers, followed by
6695            start address and length. We are setting complete length.
6696            length = end_address_of_bss - start_address_of_text.
6697            Remainder is the blob to be loaded contiguously
6698            from start address. */
6699
6700         info.fw_base = be32_to_cpu(fw_data[1]);
6701         info.fw_len = tp->fw->size - 12;
6702         info.fw_data = &fw_data[3];
6703
6704         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6705                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6706                                     &info);
6707         if (err)
6708                 return err;
6709
6710         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6711                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6712                                     &info);
6713         if (err)
6714                 return err;
6715
6716         /* Now startup only the RX cpu. */
6717         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6718         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6719
6720         for (i = 0; i < 5; i++) {
6721                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6722                         break;
6723                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6724                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6725                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6726                 udelay(1000);
6727         }
6728         if (i >= 5) {
6729                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6730                        "to set RX CPU PC, is %08x should be %08x\n",
6731                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6732                        info.fw_base);
6733                 return -ENODEV;
6734         }
6735         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6736         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6737
6738         return 0;
6739 }
6740
6741 /* 5705 needs a special version of the TSO firmware.  */
6742
6743 /* tp->lock is held. */
6744 static int tg3_load_tso_firmware(struct tg3 *tp)
6745 {
6746         struct fw_info info;
6747         const __be32 *fw_data;
6748         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6749         int err, i;
6750
6751         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6752                 return 0;
6753
6754         fw_data = (void *)tp->fw->data;
6755
6756         /* Firmware blob starts with version numbers, followed by
6757            start address and length. We are setting complete length.
6758            length = end_address_of_bss - start_address_of_text.
6759            Remainder is the blob to be loaded contiguously
6760            from start address. */
6761
6762         info.fw_base = be32_to_cpu(fw_data[1]);
6763         cpu_scratch_size = tp->fw_len;
6764         info.fw_len = tp->fw->size - 12;
6765         info.fw_data = &fw_data[3];
6766
6767         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6768                 cpu_base = RX_CPU_BASE;
6769                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6770         } else {
6771                 cpu_base = TX_CPU_BASE;
6772                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6773                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6774         }
6775
6776         err = tg3_load_firmware_cpu(tp, cpu_base,
6777                                     cpu_scratch_base, cpu_scratch_size,
6778                                     &info);
6779         if (err)
6780                 return err;
6781
6782         /* Now startup the cpu. */
6783         tw32(cpu_base + CPU_STATE, 0xffffffff);
6784         tw32_f(cpu_base + CPU_PC, info.fw_base);
6785
6786         for (i = 0; i < 5; i++) {
6787                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6788                         break;
6789                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6790                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6791                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6792                 udelay(1000);
6793         }
6794         if (i >= 5) {
6795                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6796                        "to set CPU PC, is %08x should be %08x\n",
6797                        tp->dev->name, tr32(cpu_base + CPU_PC),
6798                        info.fw_base);
6799                 return -ENODEV;
6800         }
6801         tw32(cpu_base + CPU_STATE, 0xffffffff);
6802         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6803         return 0;
6804 }
6805
6806
6807 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6808 {
6809         struct tg3 *tp = netdev_priv(dev);
6810         struct sockaddr *addr = p;
6811         int err = 0, skip_mac_1 = 0;
6812
6813         if (!is_valid_ether_addr(addr->sa_data))
6814                 return -EINVAL;
6815
6816         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6817
6818         if (!netif_running(dev))
6819                 return 0;
6820
6821         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6822                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6823
6824                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6825                 addr0_low = tr32(MAC_ADDR_0_LOW);
6826                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6827                 addr1_low = tr32(MAC_ADDR_1_LOW);
6828
6829                 /* Skip MAC addr 1 if ASF is using it. */
6830                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6831                     !(addr1_high == 0 && addr1_low == 0))
6832                         skip_mac_1 = 1;
6833         }
6834         spin_lock_bh(&tp->lock);
6835         __tg3_set_mac_addr(tp, skip_mac_1);
6836         spin_unlock_bh(&tp->lock);
6837
6838         return err;
6839 }
6840
6841 /* tp->lock is held. */
6842 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6843                            dma_addr_t mapping, u32 maxlen_flags,
6844                            u32 nic_addr)
6845 {
6846         tg3_write_mem(tp,
6847                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6848                       ((u64) mapping >> 32));
6849         tg3_write_mem(tp,
6850                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6851                       ((u64) mapping & 0xffffffff));
6852         tg3_write_mem(tp,
6853                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6854                        maxlen_flags);
6855
6856         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6857                 tg3_write_mem(tp,
6858                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6859                               nic_addr);
6860 }
6861
6862 static void __tg3_set_rx_mode(struct net_device *);
6863 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6864 {
6865         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6866         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6867         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6868         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6869         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6870                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6871                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6872         }
6873         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6874         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6875         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6876                 u32 val = ec->stats_block_coalesce_usecs;
6877
6878                 if (!netif_carrier_ok(tp->dev))
6879                         val = 0;
6880
6881                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6882         }
6883 }
6884
6885 /* tp->lock is held. */
6886 static void tg3_rings_reset(struct tg3 *tp)
6887 {
6888         int i;
6889         u32 stblk, txrcb, rxrcb, limit;
6890         struct tg3_napi *tnapi = &tp->napi[0];
6891
6892         /* Disable all transmit rings but the first. */
6893         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6894                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
6895         else
6896                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6897
6898         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6899              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
6900                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
6901                               BDINFO_FLAGS_DISABLED);
6902
6903
6904         /* Disable all receive return rings but the first. */
6905         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6906                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
6907         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6908                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
6909         else
6910                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6911
6912         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6913              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
6914                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
6915                               BDINFO_FLAGS_DISABLED);
6916
6917         /* Disable interrupts */
6918         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
6919
6920         /* Zero mailbox registers. */
6921         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
6922                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
6923                         tp->napi[i].tx_prod = 0;
6924                         tp->napi[i].tx_cons = 0;
6925                         tw32_mailbox(tp->napi[i].prodmbox, 0);
6926                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
6927                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
6928                 }
6929         } else {
6930                 tp->napi[0].tx_prod = 0;
6931                 tp->napi[0].tx_cons = 0;
6932                 tw32_mailbox(tp->napi[0].prodmbox, 0);
6933                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
6934         }
6935
6936         /* Make sure the NIC-based send BD rings are disabled. */
6937         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6938                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6939                 for (i = 0; i < 16; i++)
6940                         tw32_tx_mbox(mbox + i * 8, 0);
6941         }
6942
6943         txrcb = NIC_SRAM_SEND_RCB;
6944         rxrcb = NIC_SRAM_RCV_RET_RCB;
6945
6946         /* Clear status block in ram. */
6947         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6948
6949         /* Set status block DMA address */
6950         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6951              ((u64) tnapi->status_mapping >> 32));
6952         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6953              ((u64) tnapi->status_mapping & 0xffffffff));
6954
6955         if (tnapi->tx_ring) {
6956                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
6957                                (TG3_TX_RING_SIZE <<
6958                                 BDINFO_FLAGS_MAXLEN_SHIFT),
6959                                NIC_SRAM_TX_BUFFER_DESC);
6960                 txrcb += TG3_BDINFO_SIZE;
6961         }
6962
6963         if (tnapi->rx_rcb) {
6964                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
6965                                (TG3_RX_RCB_RING_SIZE(tp) <<
6966                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
6967                 rxrcb += TG3_BDINFO_SIZE;
6968         }
6969
6970         stblk = HOSTCC_STATBLCK_RING1;
6971
6972         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
6973                 u64 mapping = (u64)tnapi->status_mapping;
6974                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
6975                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
6976
6977                 /* Clear status block in ram. */
6978                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6979
6980                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
6981                                (TG3_TX_RING_SIZE <<
6982                                 BDINFO_FLAGS_MAXLEN_SHIFT),
6983                                NIC_SRAM_TX_BUFFER_DESC);
6984
6985                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
6986                                (TG3_RX_RCB_RING_SIZE(tp) <<
6987                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
6988
6989                 stblk += 8;
6990                 txrcb += TG3_BDINFO_SIZE;
6991                 rxrcb += TG3_BDINFO_SIZE;
6992         }
6993 }
6994
6995 /* tp->lock is held. */
6996 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6997 {
6998         u32 val, rdmac_mode;
6999         int i, err, limit;
7000         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7001
7002         tg3_disable_ints(tp);
7003
7004         tg3_stop_fw(tp);
7005
7006         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7007
7008         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7009                 tg3_abort_hw(tp, 1);
7010         }
7011
7012         if (reset_phy &&
7013             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7014                 tg3_phy_reset(tp);
7015
7016         err = tg3_chip_reset(tp);
7017         if (err)
7018                 return err;
7019
7020         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7021
7022         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7023                 val = tr32(TG3_CPMU_CTRL);
7024                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7025                 tw32(TG3_CPMU_CTRL, val);
7026
7027                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7028                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7029                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7030                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7031
7032                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7033                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7034                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7035                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7036
7037                 val = tr32(TG3_CPMU_HST_ACC);
7038                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7039                 val |= CPMU_HST_ACC_MACCLK_6_25;
7040                 tw32(TG3_CPMU_HST_ACC, val);
7041         }
7042
7043         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7044                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7045                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7046                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7047                 tw32(PCIE_PWR_MGMT_THRESH, val);
7048
7049                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7050                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7051
7052                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7053         }
7054
7055         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
7056                 val = tr32(TG3_PCIE_LNKCTL);
7057                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
7058                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7059                 else
7060                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7061                 tw32(TG3_PCIE_LNKCTL, val);
7062         }
7063
7064         /* This works around an issue with Athlon chipsets on
7065          * B3 tigon3 silicon.  This bit has no effect on any
7066          * other revision.  But do not set this on PCI Express
7067          * chips and don't even touch the clocks if the CPMU is present.
7068          */
7069         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7070                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7071                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7072                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7073         }
7074
7075         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7076             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7077                 val = tr32(TG3PCI_PCISTATE);
7078                 val |= PCISTATE_RETRY_SAME_DMA;
7079                 tw32(TG3PCI_PCISTATE, val);
7080         }
7081
7082         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7083                 /* Allow reads and writes to the
7084                  * APE register and memory space.
7085                  */
7086                 val = tr32(TG3PCI_PCISTATE);
7087                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7088                        PCISTATE_ALLOW_APE_SHMEM_WR;
7089                 tw32(TG3PCI_PCISTATE, val);
7090         }
7091
7092         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7093                 /* Enable some hw fixes.  */
7094                 val = tr32(TG3PCI_MSI_DATA);
7095                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7096                 tw32(TG3PCI_MSI_DATA, val);
7097         }
7098
7099         /* Descriptor ring init may make accesses to the
7100          * NIC SRAM area to setup the TX descriptors, so we
7101          * can only do this after the hardware has been
7102          * successfully reset.
7103          */
7104         err = tg3_init_rings(tp);
7105         if (err)
7106                 return err;
7107
7108         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7109             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7110                 /* This value is determined during the probe time DMA
7111                  * engine test, tg3_test_dma.
7112                  */
7113                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7114         }
7115
7116         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7117                           GRC_MODE_4X_NIC_SEND_RINGS |
7118                           GRC_MODE_NO_TX_PHDR_CSUM |
7119                           GRC_MODE_NO_RX_PHDR_CSUM);
7120         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7121
7122         /* Pseudo-header checksum is done by hardware logic and not
7123          * the offload processers, so make the chip do the pseudo-
7124          * header checksums on receive.  For transmit it is more
7125          * convenient to do the pseudo-header checksum in software
7126          * as Linux does that on transmit for us in all cases.
7127          */
7128         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7129
7130         tw32(GRC_MODE,
7131              tp->grc_mode |
7132              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7133
7134         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7135         val = tr32(GRC_MISC_CFG);
7136         val &= ~0xff;
7137         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7138         tw32(GRC_MISC_CFG, val);
7139
7140         /* Initialize MBUF/DESC pool. */
7141         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7142                 /* Do nothing.  */
7143         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7144                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7146                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7147                 else
7148                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7149                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7150                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7151         }
7152         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7153                 int fw_len;
7154
7155                 fw_len = tp->fw_len;
7156                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7157                 tw32(BUFMGR_MB_POOL_ADDR,
7158                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7159                 tw32(BUFMGR_MB_POOL_SIZE,
7160                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7161         }
7162
7163         if (tp->dev->mtu <= ETH_DATA_LEN) {
7164                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7165                      tp->bufmgr_config.mbuf_read_dma_low_water);
7166                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7167                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7168                 tw32(BUFMGR_MB_HIGH_WATER,
7169                      tp->bufmgr_config.mbuf_high_water);
7170         } else {
7171                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7172                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7173                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7174                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7175                 tw32(BUFMGR_MB_HIGH_WATER,
7176                      tp->bufmgr_config.mbuf_high_water_jumbo);
7177         }
7178         tw32(BUFMGR_DMA_LOW_WATER,
7179              tp->bufmgr_config.dma_low_water);
7180         tw32(BUFMGR_DMA_HIGH_WATER,
7181              tp->bufmgr_config.dma_high_water);
7182
7183         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7184         for (i = 0; i < 2000; i++) {
7185                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7186                         break;
7187                 udelay(10);
7188         }
7189         if (i >= 2000) {
7190                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7191                        tp->dev->name);
7192                 return -ENODEV;
7193         }
7194
7195         /* Setup replenish threshold. */
7196         val = tp->rx_pending / 8;
7197         if (val == 0)
7198                 val = 1;
7199         else if (val > tp->rx_std_max_post)
7200                 val = tp->rx_std_max_post;
7201         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7202                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7203                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7204
7205                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7206                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7207         }
7208
7209         tw32(RCVBDI_STD_THRESH, val);
7210
7211         /* Initialize TG3_BDINFO's at:
7212          *  RCVDBDI_STD_BD:     standard eth size rx ring
7213          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7214          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7215          *
7216          * like so:
7217          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7218          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7219          *                              ring attribute flags
7220          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7221          *
7222          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7223          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7224          *
7225          * The size of each ring is fixed in the firmware, but the location is
7226          * configurable.
7227          */
7228         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7229              ((u64) tpr->rx_std_mapping >> 32));
7230         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7231              ((u64) tpr->rx_std_mapping & 0xffffffff));
7232         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7233              NIC_SRAM_RX_BUFFER_DESC);
7234
7235         /* Disable the mini ring */
7236         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7237                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7238                      BDINFO_FLAGS_DISABLED);
7239
7240         /* Program the jumbo buffer descriptor ring control
7241          * blocks on those devices that have them.
7242          */
7243         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7244             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7245                 /* Setup replenish threshold. */
7246                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7247
7248                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7249                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7250                              ((u64) tpr->rx_jmb_mapping >> 32));
7251                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7252                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7253                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7254                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7255                              BDINFO_FLAGS_USE_EXT_RECV);
7256                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7257                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7258                 } else {
7259                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7260                              BDINFO_FLAGS_DISABLED);
7261                 }
7262
7263                 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7264         } else
7265                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7266
7267         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7268
7269         tpr->rx_std_ptr = tp->rx_pending;
7270         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7271                      tpr->rx_std_ptr);
7272
7273         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7274                           tp->rx_jumbo_pending : 0;
7275         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7276                      tpr->rx_jmb_ptr);
7277
7278         tg3_rings_reset(tp);
7279
7280         /* Initialize MAC address and backoff seed. */
7281         __tg3_set_mac_addr(tp, 0);
7282
7283         /* MTU + ethernet header + FCS + optional VLAN tag */
7284         tw32(MAC_RX_MTU_SIZE,
7285              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7286
7287         /* The slot time is changed by tg3_setup_phy if we
7288          * run at gigabit with half duplex.
7289          */
7290         tw32(MAC_TX_LENGTHS,
7291              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7292              (6 << TX_LENGTHS_IPG_SHIFT) |
7293              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7294
7295         /* Receive rules. */
7296         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7297         tw32(RCVLPC_CONFIG, 0x0181);
7298
7299         /* Calculate RDMAC_MODE setting early, we need it to determine
7300          * the RCVLPC_STATE_ENABLE mask.
7301          */
7302         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7303                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7304                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7305                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7306                       RDMAC_MODE_LNGREAD_ENAB);
7307
7308         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7309             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7310             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7311                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7312                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7313                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7314
7315         /* If statement applies to 5705 and 5750 PCI devices only */
7316         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7317              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7318             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7319                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7320                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7321                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7322                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7323                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7324                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7325                 }
7326         }
7327
7328         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7329                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7330
7331         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7332                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7333
7334         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7335             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7336                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7337
7338         /* Receive/send statistics. */
7339         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7340                 val = tr32(RCVLPC_STATS_ENABLE);
7341                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7342                 tw32(RCVLPC_STATS_ENABLE, val);
7343         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7344                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7345                 val = tr32(RCVLPC_STATS_ENABLE);
7346                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7347                 tw32(RCVLPC_STATS_ENABLE, val);
7348         } else {
7349                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7350         }
7351         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7352         tw32(SNDDATAI_STATSENAB, 0xffffff);
7353         tw32(SNDDATAI_STATSCTRL,
7354              (SNDDATAI_SCTRL_ENABLE |
7355               SNDDATAI_SCTRL_FASTUPD));
7356
7357         /* Setup host coalescing engine. */
7358         tw32(HOSTCC_MODE, 0);
7359         for (i = 0; i < 2000; i++) {
7360                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7361                         break;
7362                 udelay(10);
7363         }
7364
7365         __tg3_set_coalesce(tp, &tp->coal);
7366
7367         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7368                 /* Status/statistics block address.  See tg3_timer,
7369                  * the tg3_periodic_fetch_stats call there, and
7370                  * tg3_get_stats to see how this works for 5705/5750 chips.
7371                  */
7372                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7373                      ((u64) tp->stats_mapping >> 32));
7374                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7375                      ((u64) tp->stats_mapping & 0xffffffff));
7376                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7377
7378                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7379
7380                 /* Clear statistics and status block memory areas */
7381                 for (i = NIC_SRAM_STATS_BLK;
7382                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7383                      i += sizeof(u32)) {
7384                         tg3_write_mem(tp, i, 0);
7385                         udelay(40);
7386                 }
7387         }
7388
7389         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7390
7391         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7392         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7393         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7394                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7395
7396         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7397                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7398                 /* reset to prevent losing 1st rx packet intermittently */
7399                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7400                 udelay(10);
7401         }
7402
7403         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7404                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7405         else
7406                 tp->mac_mode = 0;
7407         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7408                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7409         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7410             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7411             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7412                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7413         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7414         udelay(40);
7415
7416         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7417          * If TG3_FLG2_IS_NIC is zero, we should read the
7418          * register to preserve the GPIO settings for LOMs. The GPIOs,
7419          * whether used as inputs or outputs, are set by boot code after
7420          * reset.
7421          */
7422         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7423                 u32 gpio_mask;
7424
7425                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7426                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7427                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7428
7429                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7430                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7431                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7432
7433                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7434                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7435
7436                 tp->grc_local_ctrl &= ~gpio_mask;
7437                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7438
7439                 /* GPIO1 must be driven high for eeprom write protect */
7440                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7441                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7442                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7443         }
7444         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7445         udelay(100);
7446
7447         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7448                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7449                 udelay(40);
7450         }
7451
7452         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7453                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7454                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7455                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7456                WDMAC_MODE_LNGREAD_ENAB);
7457
7458         /* If statement applies to 5705 and 5750 PCI devices only */
7459         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7460              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7461             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7462                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7463                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7464                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7465                         /* nothing */
7466                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7467                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7468                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7469                         val |= WDMAC_MODE_RX_ACCEL;
7470                 }
7471         }
7472
7473         /* Enable host coalescing bug fix */
7474         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7475                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7476
7477         tw32_f(WDMAC_MODE, val);
7478         udelay(40);
7479
7480         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7481                 u16 pcix_cmd;
7482
7483                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7484                                      &pcix_cmd);
7485                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7486                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7487                         pcix_cmd |= PCI_X_CMD_READ_2K;
7488                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7489                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7490                         pcix_cmd |= PCI_X_CMD_READ_2K;
7491                 }
7492                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7493                                       pcix_cmd);
7494         }
7495
7496         tw32_f(RDMAC_MODE, rdmac_mode);
7497         udelay(40);
7498
7499         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7500         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7501                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7502
7503         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7504                 tw32(SNDDATAC_MODE,
7505                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7506         else
7507                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7508
7509         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7510         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7511         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7512         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7513         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7514                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7515         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7516         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7517
7518         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7519                 err = tg3_load_5701_a0_firmware_fix(tp);
7520                 if (err)
7521                         return err;
7522         }
7523
7524         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7525                 err = tg3_load_tso_firmware(tp);
7526                 if (err)
7527                         return err;
7528         }
7529
7530         tp->tx_mode = TX_MODE_ENABLE;
7531         tw32_f(MAC_TX_MODE, tp->tx_mode);
7532         udelay(100);
7533
7534         tp->rx_mode = RX_MODE_ENABLE;
7535         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7536                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7537
7538         tw32_f(MAC_RX_MODE, tp->rx_mode);
7539         udelay(10);
7540
7541         tw32(MAC_LED_CTRL, tp->led_ctrl);
7542
7543         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7544         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7545                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7546                 udelay(10);
7547         }
7548         tw32_f(MAC_RX_MODE, tp->rx_mode);
7549         udelay(10);
7550
7551         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7552                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7553                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7554                         /* Set drive transmission level to 1.2V  */
7555                         /* only if the signal pre-emphasis bit is not set  */
7556                         val = tr32(MAC_SERDES_CFG);
7557                         val &= 0xfffff000;
7558                         val |= 0x880;
7559                         tw32(MAC_SERDES_CFG, val);
7560                 }
7561                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7562                         tw32(MAC_SERDES_CFG, 0x616000);
7563         }
7564
7565         /* Prevent chip from dropping frames when flow control
7566          * is enabled.
7567          */
7568         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7569
7570         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7571             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7572                 /* Use hardware link auto-negotiation */
7573                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7574         }
7575
7576         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7577             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7578                 u32 tmp;
7579
7580                 tmp = tr32(SERDES_RX_CTRL);
7581                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7582                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7583                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7584                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7585         }
7586
7587         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7588                 if (tp->link_config.phy_is_low_power) {
7589                         tp->link_config.phy_is_low_power = 0;
7590                         tp->link_config.speed = tp->link_config.orig_speed;
7591                         tp->link_config.duplex = tp->link_config.orig_duplex;
7592                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7593                 }
7594
7595                 err = tg3_setup_phy(tp, 0);
7596                 if (err)
7597                         return err;
7598
7599                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7600                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7601                         u32 tmp;
7602
7603                         /* Clear CRC stats. */
7604                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7605                                 tg3_writephy(tp, MII_TG3_TEST1,
7606                                              tmp | MII_TG3_TEST1_CRC_EN);
7607                                 tg3_readphy(tp, 0x14, &tmp);
7608                         }
7609                 }
7610         }
7611
7612         __tg3_set_rx_mode(tp->dev);
7613
7614         /* Initialize receive rules. */
7615         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7616         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7617         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7618         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7619
7620         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7621             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7622                 limit = 8;
7623         else
7624                 limit = 16;
7625         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7626                 limit -= 4;
7627         switch (limit) {
7628         case 16:
7629                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7630         case 15:
7631                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7632         case 14:
7633                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7634         case 13:
7635                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7636         case 12:
7637                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7638         case 11:
7639                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7640         case 10:
7641                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7642         case 9:
7643                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7644         case 8:
7645                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7646         case 7:
7647                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7648         case 6:
7649                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7650         case 5:
7651                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7652         case 4:
7653                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7654         case 3:
7655                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7656         case 2:
7657         case 1:
7658
7659         default:
7660                 break;
7661         }
7662
7663         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7664                 /* Write our heartbeat update interval to APE. */
7665                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7666                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7667
7668         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7669
7670         return 0;
7671 }
7672
7673 /* Called at device open time to get the chip ready for
7674  * packet processing.  Invoked with tp->lock held.
7675  */
7676 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7677 {
7678         tg3_switch_clocks(tp);
7679
7680         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7681
7682         return tg3_reset_hw(tp, reset_phy);
7683 }
7684
7685 #define TG3_STAT_ADD32(PSTAT, REG) \
7686 do {    u32 __val = tr32(REG); \
7687         (PSTAT)->low += __val; \
7688         if ((PSTAT)->low < __val) \
7689                 (PSTAT)->high += 1; \
7690 } while (0)
7691
7692 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7693 {
7694         struct tg3_hw_stats *sp = tp->hw_stats;
7695
7696         if (!netif_carrier_ok(tp->dev))
7697                 return;
7698
7699         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7700         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7701         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7702         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7703         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7704         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7705         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7706         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7707         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7708         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7709         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7710         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7711         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7712
7713         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7714         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7715         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7716         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7717         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7718         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7719         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7720         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7721         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7722         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7723         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7724         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7725         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7726         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7727
7728         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7729         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7730         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7731 }
7732
7733 static void tg3_timer(unsigned long __opaque)
7734 {
7735         struct tg3 *tp = (struct tg3 *) __opaque;
7736
7737         if (tp->irq_sync)
7738                 goto restart_timer;
7739
7740         spin_lock(&tp->lock);
7741
7742         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7743                 /* All of this garbage is because when using non-tagged
7744                  * IRQ status the mailbox/status_block protocol the chip
7745                  * uses with the cpu is race prone.
7746                  */
7747                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7748                         tw32(GRC_LOCAL_CTRL,
7749                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7750                 } else {
7751                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7752                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7753                 }
7754
7755                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7756                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7757                         spin_unlock(&tp->lock);
7758                         schedule_work(&tp->reset_task);
7759                         return;
7760                 }
7761         }
7762
7763         /* This part only runs once per second. */
7764         if (!--tp->timer_counter) {
7765                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7766                         tg3_periodic_fetch_stats(tp);
7767
7768                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7769                         u32 mac_stat;
7770                         int phy_event;
7771
7772                         mac_stat = tr32(MAC_STATUS);
7773
7774                         phy_event = 0;
7775                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7776                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7777                                         phy_event = 1;
7778                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7779                                 phy_event = 1;
7780
7781                         if (phy_event)
7782                                 tg3_setup_phy(tp, 0);
7783                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7784                         u32 mac_stat = tr32(MAC_STATUS);
7785                         int need_setup = 0;
7786
7787                         if (netif_carrier_ok(tp->dev) &&
7788                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7789                                 need_setup = 1;
7790                         }
7791                         if (! netif_carrier_ok(tp->dev) &&
7792                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7793                                          MAC_STATUS_SIGNAL_DET))) {
7794                                 need_setup = 1;
7795                         }
7796                         if (need_setup) {
7797                                 if (!tp->serdes_counter) {
7798                                         tw32_f(MAC_MODE,
7799                                              (tp->mac_mode &
7800                                               ~MAC_MODE_PORT_MODE_MASK));
7801                                         udelay(40);
7802                                         tw32_f(MAC_MODE, tp->mac_mode);
7803                                         udelay(40);
7804                                 }
7805                                 tg3_setup_phy(tp, 0);
7806                         }
7807                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7808                         tg3_serdes_parallel_detect(tp);
7809
7810                 tp->timer_counter = tp->timer_multiplier;
7811         }
7812
7813         /* Heartbeat is only sent once every 2 seconds.
7814          *
7815          * The heartbeat is to tell the ASF firmware that the host
7816          * driver is still alive.  In the event that the OS crashes,
7817          * ASF needs to reset the hardware to free up the FIFO space
7818          * that may be filled with rx packets destined for the host.
7819          * If the FIFO is full, ASF will no longer function properly.
7820          *
7821          * Unintended resets have been reported on real time kernels
7822          * where the timer doesn't run on time.  Netpoll will also have
7823          * same problem.
7824          *
7825          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7826          * to check the ring condition when the heartbeat is expiring
7827          * before doing the reset.  This will prevent most unintended
7828          * resets.
7829          */
7830         if (!--tp->asf_counter) {
7831                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7832                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7833                         tg3_wait_for_event_ack(tp);
7834
7835                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7836                                       FWCMD_NICDRV_ALIVE3);
7837                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7838                         /* 5 seconds timeout */
7839                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7840
7841                         tg3_generate_fw_event(tp);
7842                 }
7843                 tp->asf_counter = tp->asf_multiplier;
7844         }
7845
7846         spin_unlock(&tp->lock);
7847
7848 restart_timer:
7849         tp->timer.expires = jiffies + tp->timer_offset;
7850         add_timer(&tp->timer);
7851 }
7852
7853 static int tg3_request_irq(struct tg3 *tp, int irq_num)
7854 {
7855         irq_handler_t fn;
7856         unsigned long flags;
7857         char *name;
7858         struct tg3_napi *tnapi = &tp->napi[irq_num];
7859
7860         if (tp->irq_cnt == 1)
7861                 name = tp->dev->name;
7862         else {
7863                 name = &tnapi->irq_lbl[0];
7864                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
7865                 name[IFNAMSIZ-1] = 0;
7866         }
7867
7868         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
7869                 fn = tg3_msi;
7870                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7871                         fn = tg3_msi_1shot;
7872                 flags = IRQF_SAMPLE_RANDOM;
7873         } else {
7874                 fn = tg3_interrupt;
7875                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7876                         fn = tg3_interrupt_tagged;
7877                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7878         }
7879
7880         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
7881 }
7882
7883 static int tg3_test_interrupt(struct tg3 *tp)
7884 {
7885         struct tg3_napi *tnapi = &tp->napi[0];
7886         struct net_device *dev = tp->dev;
7887         int err, i, intr_ok = 0;
7888
7889         if (!netif_running(dev))
7890                 return -ENODEV;
7891
7892         tg3_disable_ints(tp);
7893
7894         free_irq(tnapi->irq_vec, tnapi);
7895
7896         err = request_irq(tnapi->irq_vec, tg3_test_isr,
7897                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7898         if (err)
7899                 return err;
7900
7901         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7902         tg3_enable_ints(tp);
7903
7904         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7905                tnapi->coal_now);
7906
7907         for (i = 0; i < 5; i++) {
7908                 u32 int_mbox, misc_host_ctrl;
7909
7910                 int_mbox = tr32_mailbox(tnapi->int_mbox);
7911                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7912
7913                 if ((int_mbox != 0) ||
7914                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7915                         intr_ok = 1;
7916                         break;
7917                 }
7918
7919                 msleep(10);
7920         }
7921
7922         tg3_disable_ints(tp);
7923
7924         free_irq(tnapi->irq_vec, tnapi);
7925
7926         err = tg3_request_irq(tp, 0);
7927
7928         if (err)
7929                 return err;
7930
7931         if (intr_ok)
7932                 return 0;
7933
7934         return -EIO;
7935 }
7936
7937 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7938  * successfully restored
7939  */
7940 static int tg3_test_msi(struct tg3 *tp)
7941 {
7942         int err;
7943         u16 pci_cmd;
7944
7945         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7946                 return 0;
7947
7948         /* Turn off SERR reporting in case MSI terminates with Master
7949          * Abort.
7950          */
7951         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7952         pci_write_config_word(tp->pdev, PCI_COMMAND,
7953                               pci_cmd & ~PCI_COMMAND_SERR);
7954
7955         err = tg3_test_interrupt(tp);
7956
7957         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7958
7959         if (!err)
7960                 return 0;
7961
7962         /* other failures */
7963         if (err != -EIO)
7964                 return err;
7965
7966         /* MSI test failed, go back to INTx mode */
7967         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7968                "switching to INTx mode. Please report this failure to "
7969                "the PCI maintainer and include system chipset information.\n",
7970                        tp->dev->name);
7971
7972         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7973
7974         pci_disable_msi(tp->pdev);
7975
7976         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7977
7978         err = tg3_request_irq(tp, 0);
7979         if (err)
7980                 return err;
7981
7982         /* Need to reset the chip because the MSI cycle may have terminated
7983          * with Master Abort.
7984          */
7985         tg3_full_lock(tp, 1);
7986
7987         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7988         err = tg3_init_hw(tp, 1);
7989
7990         tg3_full_unlock(tp);
7991
7992         if (err)
7993                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7994
7995         return err;
7996 }
7997
7998 static int tg3_request_firmware(struct tg3 *tp)
7999 {
8000         const __be32 *fw_data;
8001
8002         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8003                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8004                        tp->dev->name, tp->fw_needed);
8005                 return -ENOENT;
8006         }
8007
8008         fw_data = (void *)tp->fw->data;
8009
8010         /* Firmware blob starts with version numbers, followed by
8011          * start address and _full_ length including BSS sections
8012          * (which must be longer than the actual data, of course
8013          */
8014
8015         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8016         if (tp->fw_len < (tp->fw->size - 12)) {
8017                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8018                        tp->dev->name, tp->fw_len, tp->fw_needed);
8019                 release_firmware(tp->fw);
8020                 tp->fw = NULL;
8021                 return -EINVAL;
8022         }
8023
8024         /* We no longer need firmware; we have it. */
8025         tp->fw_needed = NULL;
8026         return 0;
8027 }
8028
8029 static bool tg3_enable_msix(struct tg3 *tp)
8030 {
8031         int i, rc, cpus = num_online_cpus();
8032         struct msix_entry msix_ent[tp->irq_max];
8033
8034         if (cpus == 1)
8035                 /* Just fallback to the simpler MSI mode. */
8036                 return false;
8037
8038         /*
8039          * We want as many rx rings enabled as there are cpus.
8040          * The first MSIX vector only deals with link interrupts, etc,
8041          * so we add one to the number of vectors we are requesting.
8042          */
8043         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8044
8045         for (i = 0; i < tp->irq_max; i++) {
8046                 msix_ent[i].entry  = i;
8047                 msix_ent[i].vector = 0;
8048         }
8049
8050         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8051         if (rc != 0) {
8052                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8053                         return false;
8054                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8055                         return false;
8056                 printk(KERN_NOTICE
8057                        "%s: Requested %d MSI-X vectors, received %d\n",
8058                        tp->dev->name, tp->irq_cnt, rc);
8059                 tp->irq_cnt = rc;
8060         }
8061
8062         for (i = 0; i < tp->irq_max; i++)
8063                 tp->napi[i].irq_vec = msix_ent[i].vector;
8064
8065         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8066
8067         return true;
8068 }
8069
8070 static void tg3_ints_init(struct tg3 *tp)
8071 {
8072         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8073             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8074                 /* All MSI supporting chips should support tagged
8075                  * status.  Assert that this is the case.
8076                  */
8077                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8078                        "Not using MSI.\n", tp->dev->name);
8079                 goto defcfg;
8080         }
8081
8082         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8083                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8084         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8085                  pci_enable_msi(tp->pdev) == 0)
8086                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8087
8088         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8089                 u32 msi_mode = tr32(MSGINT_MODE);
8090                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8091         }
8092 defcfg:
8093         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8094                 tp->irq_cnt = 1;
8095                 tp->napi[0].irq_vec = tp->pdev->irq;
8096                 tp->dev->real_num_tx_queues = 1;
8097         }
8098 }
8099
8100 static void tg3_ints_fini(struct tg3 *tp)
8101 {
8102         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8103                 pci_disable_msix(tp->pdev);
8104         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8105                 pci_disable_msi(tp->pdev);
8106         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8107 }
8108
8109 static int tg3_open(struct net_device *dev)
8110 {
8111         struct tg3 *tp = netdev_priv(dev);
8112         int i, err;
8113
8114         if (tp->fw_needed) {
8115                 err = tg3_request_firmware(tp);
8116                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8117                         if (err)
8118                                 return err;
8119                 } else if (err) {
8120                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8121                                tp->dev->name);
8122                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8123                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8124                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8125                                tp->dev->name);
8126                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8127                 }
8128         }
8129
8130         netif_carrier_off(tp->dev);
8131
8132         err = tg3_set_power_state(tp, PCI_D0);
8133         if (err)
8134                 return err;
8135
8136         tg3_full_lock(tp, 0);
8137
8138         tg3_disable_ints(tp);
8139         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8140
8141         tg3_full_unlock(tp);
8142
8143         /*
8144          * Setup interrupts first so we know how
8145          * many NAPI resources to allocate
8146          */
8147         tg3_ints_init(tp);
8148
8149         /* The placement of this call is tied
8150          * to the setup and use of Host TX descriptors.
8151          */
8152         err = tg3_alloc_consistent(tp);
8153         if (err)
8154                 goto err_out1;
8155
8156         napi_enable(&tp->napi[0].napi);
8157
8158         for (i = 0; i < tp->irq_cnt; i++) {
8159                 struct tg3_napi *tnapi = &tp->napi[i];
8160                 err = tg3_request_irq(tp, i);
8161                 if (err) {
8162                         for (i--; i >= 0; i--)
8163                                 free_irq(tnapi->irq_vec, tnapi);
8164                         break;
8165                 }
8166         }
8167
8168         if (err)
8169                 goto err_out2;
8170
8171         tg3_full_lock(tp, 0);
8172
8173         err = tg3_init_hw(tp, 1);
8174         if (err) {
8175                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8176                 tg3_free_rings(tp);
8177         } else {
8178                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8179                         tp->timer_offset = HZ;
8180                 else
8181                         tp->timer_offset = HZ / 10;
8182
8183                 BUG_ON(tp->timer_offset > HZ);
8184                 tp->timer_counter = tp->timer_multiplier =
8185                         (HZ / tp->timer_offset);
8186                 tp->asf_counter = tp->asf_multiplier =
8187                         ((HZ / tp->timer_offset) * 2);
8188
8189                 init_timer(&tp->timer);
8190                 tp->timer.expires = jiffies + tp->timer_offset;
8191                 tp->timer.data = (unsigned long) tp;
8192                 tp->timer.function = tg3_timer;
8193         }
8194
8195         tg3_full_unlock(tp);
8196
8197         if (err)
8198                 goto err_out3;
8199
8200         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8201                 err = tg3_test_msi(tp);
8202
8203                 if (err) {
8204                         tg3_full_lock(tp, 0);
8205                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8206                         tg3_free_rings(tp);
8207                         tg3_full_unlock(tp);
8208
8209                         goto err_out2;
8210                 }
8211
8212                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8213                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8214                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
8215
8216                                 tw32(PCIE_TRANSACTION_CFG,
8217                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
8218                         }
8219                 }
8220         }
8221
8222         tg3_phy_start(tp);
8223
8224         tg3_full_lock(tp, 0);
8225
8226         add_timer(&tp->timer);
8227         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8228         tg3_enable_ints(tp);
8229
8230         tg3_full_unlock(tp);
8231
8232         netif_tx_start_all_queues(dev);
8233
8234         return 0;
8235
8236 err_out3:
8237         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8238                 struct tg3_napi *tnapi = &tp->napi[i];
8239                 free_irq(tnapi->irq_vec, tnapi);
8240         }
8241
8242 err_out2:
8243         napi_disable(&tp->napi[0].napi);
8244         tg3_free_consistent(tp);
8245
8246 err_out1:
8247         tg3_ints_fini(tp);
8248         return err;
8249 }
8250
8251 #if 0
8252 /*static*/ void tg3_dump_state(struct tg3 *tp)
8253 {
8254         u32 val32, val32_2, val32_3, val32_4, val32_5;
8255         u16 val16;
8256         int i;
8257         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8258
8259         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8260         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8261         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8262                val16, val32);
8263
8264         /* MAC block */
8265         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8266                tr32(MAC_MODE), tr32(MAC_STATUS));
8267         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8268                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8269         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8270                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8271         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8272                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8273
8274         /* Send data initiator control block */
8275         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8276                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8277         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8278                tr32(SNDDATAI_STATSCTRL));
8279
8280         /* Send data completion control block */
8281         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8282
8283         /* Send BD ring selector block */
8284         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8285                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8286
8287         /* Send BD initiator control block */
8288         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8289                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8290
8291         /* Send BD completion control block */
8292         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8293
8294         /* Receive list placement control block */
8295         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8296                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8297         printk("       RCVLPC_STATSCTRL[%08x]\n",
8298                tr32(RCVLPC_STATSCTRL));
8299
8300         /* Receive data and receive BD initiator control block */
8301         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8302                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8303
8304         /* Receive data completion control block */
8305         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8306                tr32(RCVDCC_MODE));
8307
8308         /* Receive BD initiator control block */
8309         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8310                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8311
8312         /* Receive BD completion control block */
8313         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8314                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8315
8316         /* Receive list selector control block */
8317         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8318                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8319
8320         /* Mbuf cluster free block */
8321         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8322                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8323
8324         /* Host coalescing control block */
8325         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8326                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8327         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8328                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8329                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8330         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8331                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8332                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8333         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8334                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8335         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8336                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8337
8338         /* Memory arbiter control block */
8339         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8340                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8341
8342         /* Buffer manager control block */
8343         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8344                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8345         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8346                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8347         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8348                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8349                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8350                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8351
8352         /* Read DMA control block */
8353         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8354                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8355
8356         /* Write DMA control block */
8357         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8358                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8359
8360         /* DMA completion block */
8361         printk("DEBUG: DMAC_MODE[%08x]\n",
8362                tr32(DMAC_MODE));
8363
8364         /* GRC block */
8365         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8366                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8367         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8368                tr32(GRC_LOCAL_CTRL));
8369
8370         /* TG3_BDINFOs */
8371         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8372                tr32(RCVDBDI_JUMBO_BD + 0x0),
8373                tr32(RCVDBDI_JUMBO_BD + 0x4),
8374                tr32(RCVDBDI_JUMBO_BD + 0x8),
8375                tr32(RCVDBDI_JUMBO_BD + 0xc));
8376         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8377                tr32(RCVDBDI_STD_BD + 0x0),
8378                tr32(RCVDBDI_STD_BD + 0x4),
8379                tr32(RCVDBDI_STD_BD + 0x8),
8380                tr32(RCVDBDI_STD_BD + 0xc));
8381         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8382                tr32(RCVDBDI_MINI_BD + 0x0),
8383                tr32(RCVDBDI_MINI_BD + 0x4),
8384                tr32(RCVDBDI_MINI_BD + 0x8),
8385                tr32(RCVDBDI_MINI_BD + 0xc));
8386
8387         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8388         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8389         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8390         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8391         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8392                val32, val32_2, val32_3, val32_4);
8393
8394         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8395         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8396         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8397         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8398         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8399                val32, val32_2, val32_3, val32_4);
8400
8401         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8402         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8403         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8404         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8405         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8406         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8407                val32, val32_2, val32_3, val32_4, val32_5);
8408
8409         /* SW status block */
8410         printk(KERN_DEBUG
8411          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8412                sblk->status,
8413                sblk->status_tag,
8414                sblk->rx_jumbo_consumer,
8415                sblk->rx_consumer,
8416                sblk->rx_mini_consumer,
8417                sblk->idx[0].rx_producer,
8418                sblk->idx[0].tx_consumer);
8419
8420         /* SW statistics block */
8421         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8422                ((u32 *)tp->hw_stats)[0],
8423                ((u32 *)tp->hw_stats)[1],
8424                ((u32 *)tp->hw_stats)[2],
8425                ((u32 *)tp->hw_stats)[3]);
8426
8427         /* Mailboxes */
8428         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8429                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8430                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8431                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8432                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8433
8434         /* NIC side send descriptors. */
8435         for (i = 0; i < 6; i++) {
8436                 unsigned long txd;
8437
8438                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8439                         + (i * sizeof(struct tg3_tx_buffer_desc));
8440                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8441                        i,
8442                        readl(txd + 0x0), readl(txd + 0x4),
8443                        readl(txd + 0x8), readl(txd + 0xc));
8444         }
8445
8446         /* NIC side RX descriptors. */
8447         for (i = 0; i < 6; i++) {
8448                 unsigned long rxd;
8449
8450                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8451                         + (i * sizeof(struct tg3_rx_buffer_desc));
8452                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8453                        i,
8454                        readl(rxd + 0x0), readl(rxd + 0x4),
8455                        readl(rxd + 0x8), readl(rxd + 0xc));
8456                 rxd += (4 * sizeof(u32));
8457                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8458                        i,
8459                        readl(rxd + 0x0), readl(rxd + 0x4),
8460                        readl(rxd + 0x8), readl(rxd + 0xc));
8461         }
8462
8463         for (i = 0; i < 6; i++) {
8464                 unsigned long rxd;
8465
8466                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8467                         + (i * sizeof(struct tg3_rx_buffer_desc));
8468                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8469                        i,
8470                        readl(rxd + 0x0), readl(rxd + 0x4),
8471                        readl(rxd + 0x8), readl(rxd + 0xc));
8472                 rxd += (4 * sizeof(u32));
8473                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8474                        i,
8475                        readl(rxd + 0x0), readl(rxd + 0x4),
8476                        readl(rxd + 0x8), readl(rxd + 0xc));
8477         }
8478 }
8479 #endif
8480
8481 static struct net_device_stats *tg3_get_stats(struct net_device *);
8482 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8483
8484 static int tg3_close(struct net_device *dev)
8485 {
8486         int i;
8487         struct tg3 *tp = netdev_priv(dev);
8488
8489         napi_disable(&tp->napi[0].napi);
8490         cancel_work_sync(&tp->reset_task);
8491
8492         netif_tx_stop_all_queues(dev);
8493
8494         del_timer_sync(&tp->timer);
8495
8496         tg3_full_lock(tp, 1);
8497 #if 0
8498         tg3_dump_state(tp);
8499 #endif
8500
8501         tg3_disable_ints(tp);
8502
8503         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8504         tg3_free_rings(tp);
8505         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8506
8507         tg3_full_unlock(tp);
8508
8509         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8510                 struct tg3_napi *tnapi = &tp->napi[i];
8511                 free_irq(tnapi->irq_vec, tnapi);
8512         }
8513
8514         tg3_ints_fini(tp);
8515
8516         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8517                sizeof(tp->net_stats_prev));
8518         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8519                sizeof(tp->estats_prev));
8520
8521         tg3_free_consistent(tp);
8522
8523         tg3_set_power_state(tp, PCI_D3hot);
8524
8525         netif_carrier_off(tp->dev);
8526
8527         return 0;
8528 }
8529
8530 static inline unsigned long get_stat64(tg3_stat64_t *val)
8531 {
8532         unsigned long ret;
8533
8534 #if (BITS_PER_LONG == 32)
8535         ret = val->low;
8536 #else
8537         ret = ((u64)val->high << 32) | ((u64)val->low);
8538 #endif
8539         return ret;
8540 }
8541
8542 static inline u64 get_estat64(tg3_stat64_t *val)
8543 {
8544        return ((u64)val->high << 32) | ((u64)val->low);
8545 }
8546
8547 static unsigned long calc_crc_errors(struct tg3 *tp)
8548 {
8549         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8550
8551         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8552             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8553              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8554                 u32 val;
8555
8556                 spin_lock_bh(&tp->lock);
8557                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8558                         tg3_writephy(tp, MII_TG3_TEST1,
8559                                      val | MII_TG3_TEST1_CRC_EN);
8560                         tg3_readphy(tp, 0x14, &val);
8561                 } else
8562                         val = 0;
8563                 spin_unlock_bh(&tp->lock);
8564
8565                 tp->phy_crc_errors += val;
8566
8567                 return tp->phy_crc_errors;
8568         }
8569
8570         return get_stat64(&hw_stats->rx_fcs_errors);
8571 }
8572
8573 #define ESTAT_ADD(member) \
8574         estats->member =        old_estats->member + \
8575                                 get_estat64(&hw_stats->member)
8576
8577 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8578 {
8579         struct tg3_ethtool_stats *estats = &tp->estats;
8580         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8581         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8582
8583         if (!hw_stats)
8584                 return old_estats;
8585
8586         ESTAT_ADD(rx_octets);
8587         ESTAT_ADD(rx_fragments);
8588         ESTAT_ADD(rx_ucast_packets);
8589         ESTAT_ADD(rx_mcast_packets);
8590         ESTAT_ADD(rx_bcast_packets);
8591         ESTAT_ADD(rx_fcs_errors);
8592         ESTAT_ADD(rx_align_errors);
8593         ESTAT_ADD(rx_xon_pause_rcvd);
8594         ESTAT_ADD(rx_xoff_pause_rcvd);
8595         ESTAT_ADD(rx_mac_ctrl_rcvd);
8596         ESTAT_ADD(rx_xoff_entered);
8597         ESTAT_ADD(rx_frame_too_long_errors);
8598         ESTAT_ADD(rx_jabbers);
8599         ESTAT_ADD(rx_undersize_packets);
8600         ESTAT_ADD(rx_in_length_errors);
8601         ESTAT_ADD(rx_out_length_errors);
8602         ESTAT_ADD(rx_64_or_less_octet_packets);
8603         ESTAT_ADD(rx_65_to_127_octet_packets);
8604         ESTAT_ADD(rx_128_to_255_octet_packets);
8605         ESTAT_ADD(rx_256_to_511_octet_packets);
8606         ESTAT_ADD(rx_512_to_1023_octet_packets);
8607         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8608         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8609         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8610         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8611         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8612
8613         ESTAT_ADD(tx_octets);
8614         ESTAT_ADD(tx_collisions);
8615         ESTAT_ADD(tx_xon_sent);
8616         ESTAT_ADD(tx_xoff_sent);
8617         ESTAT_ADD(tx_flow_control);
8618         ESTAT_ADD(tx_mac_errors);
8619         ESTAT_ADD(tx_single_collisions);
8620         ESTAT_ADD(tx_mult_collisions);
8621         ESTAT_ADD(tx_deferred);
8622         ESTAT_ADD(tx_excessive_collisions);
8623         ESTAT_ADD(tx_late_collisions);
8624         ESTAT_ADD(tx_collide_2times);
8625         ESTAT_ADD(tx_collide_3times);
8626         ESTAT_ADD(tx_collide_4times);
8627         ESTAT_ADD(tx_collide_5times);
8628         ESTAT_ADD(tx_collide_6times);
8629         ESTAT_ADD(tx_collide_7times);
8630         ESTAT_ADD(tx_collide_8times);
8631         ESTAT_ADD(tx_collide_9times);
8632         ESTAT_ADD(tx_collide_10times);
8633         ESTAT_ADD(tx_collide_11times);
8634         ESTAT_ADD(tx_collide_12times);
8635         ESTAT_ADD(tx_collide_13times);
8636         ESTAT_ADD(tx_collide_14times);
8637         ESTAT_ADD(tx_collide_15times);
8638         ESTAT_ADD(tx_ucast_packets);
8639         ESTAT_ADD(tx_mcast_packets);
8640         ESTAT_ADD(tx_bcast_packets);
8641         ESTAT_ADD(tx_carrier_sense_errors);
8642         ESTAT_ADD(tx_discards);
8643         ESTAT_ADD(tx_errors);
8644
8645         ESTAT_ADD(dma_writeq_full);
8646         ESTAT_ADD(dma_write_prioq_full);
8647         ESTAT_ADD(rxbds_empty);
8648         ESTAT_ADD(rx_discards);
8649         ESTAT_ADD(rx_errors);
8650         ESTAT_ADD(rx_threshold_hit);
8651
8652         ESTAT_ADD(dma_readq_full);
8653         ESTAT_ADD(dma_read_prioq_full);
8654         ESTAT_ADD(tx_comp_queue_full);
8655
8656         ESTAT_ADD(ring_set_send_prod_index);
8657         ESTAT_ADD(ring_status_update);
8658         ESTAT_ADD(nic_irqs);
8659         ESTAT_ADD(nic_avoided_irqs);
8660         ESTAT_ADD(nic_tx_threshold_hit);
8661
8662         return estats;
8663 }
8664
8665 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8666 {
8667         struct tg3 *tp = netdev_priv(dev);
8668         struct net_device_stats *stats = &tp->net_stats;
8669         struct net_device_stats *old_stats = &tp->net_stats_prev;
8670         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8671
8672         if (!hw_stats)
8673                 return old_stats;
8674
8675         stats->rx_packets = old_stats->rx_packets +
8676                 get_stat64(&hw_stats->rx_ucast_packets) +
8677                 get_stat64(&hw_stats->rx_mcast_packets) +
8678                 get_stat64(&hw_stats->rx_bcast_packets);
8679
8680         stats->tx_packets = old_stats->tx_packets +
8681                 get_stat64(&hw_stats->tx_ucast_packets) +
8682                 get_stat64(&hw_stats->tx_mcast_packets) +
8683                 get_stat64(&hw_stats->tx_bcast_packets);
8684
8685         stats->rx_bytes = old_stats->rx_bytes +
8686                 get_stat64(&hw_stats->rx_octets);
8687         stats->tx_bytes = old_stats->tx_bytes +
8688                 get_stat64(&hw_stats->tx_octets);
8689
8690         stats->rx_errors = old_stats->rx_errors +
8691                 get_stat64(&hw_stats->rx_errors);
8692         stats->tx_errors = old_stats->tx_errors +
8693                 get_stat64(&hw_stats->tx_errors) +
8694                 get_stat64(&hw_stats->tx_mac_errors) +
8695                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8696                 get_stat64(&hw_stats->tx_discards);
8697
8698         stats->multicast = old_stats->multicast +
8699                 get_stat64(&hw_stats->rx_mcast_packets);
8700         stats->collisions = old_stats->collisions +
8701                 get_stat64(&hw_stats->tx_collisions);
8702
8703         stats->rx_length_errors = old_stats->rx_length_errors +
8704                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8705                 get_stat64(&hw_stats->rx_undersize_packets);
8706
8707         stats->rx_over_errors = old_stats->rx_over_errors +
8708                 get_stat64(&hw_stats->rxbds_empty);
8709         stats->rx_frame_errors = old_stats->rx_frame_errors +
8710                 get_stat64(&hw_stats->rx_align_errors);
8711         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8712                 get_stat64(&hw_stats->tx_discards);
8713         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8714                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8715
8716         stats->rx_crc_errors = old_stats->rx_crc_errors +
8717                 calc_crc_errors(tp);
8718
8719         stats->rx_missed_errors = old_stats->rx_missed_errors +
8720                 get_stat64(&hw_stats->rx_discards);
8721
8722         return stats;
8723 }
8724
8725 static inline u32 calc_crc(unsigned char *buf, int len)
8726 {
8727         u32 reg;
8728         u32 tmp;
8729         int j, k;
8730
8731         reg = 0xffffffff;
8732
8733         for (j = 0; j < len; j++) {
8734                 reg ^= buf[j];
8735
8736                 for (k = 0; k < 8; k++) {
8737                         tmp = reg & 0x01;
8738
8739                         reg >>= 1;
8740
8741                         if (tmp) {
8742                                 reg ^= 0xedb88320;
8743                         }
8744                 }
8745         }
8746
8747         return ~reg;
8748 }
8749
8750 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8751 {
8752         /* accept or reject all multicast frames */
8753         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8754         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8755         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8756         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8757 }
8758
8759 static void __tg3_set_rx_mode(struct net_device *dev)
8760 {
8761         struct tg3 *tp = netdev_priv(dev);
8762         u32 rx_mode;
8763
8764         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8765                                   RX_MODE_KEEP_VLAN_TAG);
8766
8767         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8768          * flag clear.
8769          */
8770 #if TG3_VLAN_TAG_USED
8771         if (!tp->vlgrp &&
8772             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8773                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8774 #else
8775         /* By definition, VLAN is disabled always in this
8776          * case.
8777          */
8778         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8779                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8780 #endif
8781
8782         if (dev->flags & IFF_PROMISC) {
8783                 /* Promiscuous mode. */
8784                 rx_mode |= RX_MODE_PROMISC;
8785         } else if (dev->flags & IFF_ALLMULTI) {
8786                 /* Accept all multicast. */
8787                 tg3_set_multi (tp, 1);
8788         } else if (dev->mc_count < 1) {
8789                 /* Reject all multicast. */
8790                 tg3_set_multi (tp, 0);
8791         } else {
8792                 /* Accept one or more multicast(s). */
8793                 struct dev_mc_list *mclist;
8794                 unsigned int i;
8795                 u32 mc_filter[4] = { 0, };
8796                 u32 regidx;
8797                 u32 bit;
8798                 u32 crc;
8799
8800                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8801                      i++, mclist = mclist->next) {
8802
8803                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8804                         bit = ~crc & 0x7f;
8805                         regidx = (bit & 0x60) >> 5;
8806                         bit &= 0x1f;
8807                         mc_filter[regidx] |= (1 << bit);
8808                 }
8809
8810                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8811                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8812                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8813                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8814         }
8815
8816         if (rx_mode != tp->rx_mode) {
8817                 tp->rx_mode = rx_mode;
8818                 tw32_f(MAC_RX_MODE, rx_mode);
8819                 udelay(10);
8820         }
8821 }
8822
8823 static void tg3_set_rx_mode(struct net_device *dev)
8824 {
8825         struct tg3 *tp = netdev_priv(dev);
8826
8827         if (!netif_running(dev))
8828                 return;
8829
8830         tg3_full_lock(tp, 0);
8831         __tg3_set_rx_mode(dev);
8832         tg3_full_unlock(tp);
8833 }
8834
8835 #define TG3_REGDUMP_LEN         (32 * 1024)
8836
8837 static int tg3_get_regs_len(struct net_device *dev)
8838 {
8839         return TG3_REGDUMP_LEN;
8840 }
8841
8842 static void tg3_get_regs(struct net_device *dev,
8843                 struct ethtool_regs *regs, void *_p)
8844 {
8845         u32 *p = _p;
8846         struct tg3 *tp = netdev_priv(dev);
8847         u8 *orig_p = _p;
8848         int i;
8849
8850         regs->version = 0;
8851
8852         memset(p, 0, TG3_REGDUMP_LEN);
8853
8854         if (tp->link_config.phy_is_low_power)
8855                 return;
8856
8857         tg3_full_lock(tp, 0);
8858
8859 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8860 #define GET_REG32_LOOP(base,len)                \
8861 do {    p = (u32 *)(orig_p + (base));           \
8862         for (i = 0; i < len; i += 4)            \
8863                 __GET_REG32((base) + i);        \
8864 } while (0)
8865 #define GET_REG32_1(reg)                        \
8866 do {    p = (u32 *)(orig_p + (reg));            \
8867         __GET_REG32((reg));                     \
8868 } while (0)
8869
8870         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8871         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8872         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8873         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8874         GET_REG32_1(SNDDATAC_MODE);
8875         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8876         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8877         GET_REG32_1(SNDBDC_MODE);
8878         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8879         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8880         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8881         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8882         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8883         GET_REG32_1(RCVDCC_MODE);
8884         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8885         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8886         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8887         GET_REG32_1(MBFREE_MODE);
8888         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8889         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8890         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8891         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8892         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8893         GET_REG32_1(RX_CPU_MODE);
8894         GET_REG32_1(RX_CPU_STATE);
8895         GET_REG32_1(RX_CPU_PGMCTR);
8896         GET_REG32_1(RX_CPU_HWBKPT);
8897         GET_REG32_1(TX_CPU_MODE);
8898         GET_REG32_1(TX_CPU_STATE);
8899         GET_REG32_1(TX_CPU_PGMCTR);
8900         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8901         GET_REG32_LOOP(FTQ_RESET, 0x120);
8902         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8903         GET_REG32_1(DMAC_MODE);
8904         GET_REG32_LOOP(GRC_MODE, 0x4c);
8905         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8906                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8907
8908 #undef __GET_REG32
8909 #undef GET_REG32_LOOP
8910 #undef GET_REG32_1
8911
8912         tg3_full_unlock(tp);
8913 }
8914
8915 static int tg3_get_eeprom_len(struct net_device *dev)
8916 {
8917         struct tg3 *tp = netdev_priv(dev);
8918
8919         return tp->nvram_size;
8920 }
8921
8922 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8923 {
8924         struct tg3 *tp = netdev_priv(dev);
8925         int ret;
8926         u8  *pd;
8927         u32 i, offset, len, b_offset, b_count;
8928         __be32 val;
8929
8930         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8931                 return -EINVAL;
8932
8933         if (tp->link_config.phy_is_low_power)
8934                 return -EAGAIN;
8935
8936         offset = eeprom->offset;
8937         len = eeprom->len;
8938         eeprom->len = 0;
8939
8940         eeprom->magic = TG3_EEPROM_MAGIC;
8941
8942         if (offset & 3) {
8943                 /* adjustments to start on required 4 byte boundary */
8944                 b_offset = offset & 3;
8945                 b_count = 4 - b_offset;
8946                 if (b_count > len) {
8947                         /* i.e. offset=1 len=2 */
8948                         b_count = len;
8949                 }
8950                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8951                 if (ret)
8952                         return ret;
8953                 memcpy(data, ((char*)&val) + b_offset, b_count);
8954                 len -= b_count;
8955                 offset += b_count;
8956                 eeprom->len += b_count;
8957         }
8958
8959         /* read bytes upto the last 4 byte boundary */
8960         pd = &data[eeprom->len];
8961         for (i = 0; i < (len - (len & 3)); i += 4) {
8962                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8963                 if (ret) {
8964                         eeprom->len += i;
8965                         return ret;
8966                 }
8967                 memcpy(pd + i, &val, 4);
8968         }
8969         eeprom->len += i;
8970
8971         if (len & 3) {
8972                 /* read last bytes not ending on 4 byte boundary */
8973                 pd = &data[eeprom->len];
8974                 b_count = len & 3;
8975                 b_offset = offset + len - b_count;
8976                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8977                 if (ret)
8978                         return ret;
8979                 memcpy(pd, &val, b_count);
8980                 eeprom->len += b_count;
8981         }
8982         return 0;
8983 }
8984
8985 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8986
8987 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8988 {
8989         struct tg3 *tp = netdev_priv(dev);
8990         int ret;
8991         u32 offset, len, b_offset, odd_len;
8992         u8 *buf;
8993         __be32 start, end;
8994
8995         if (tp->link_config.phy_is_low_power)
8996                 return -EAGAIN;
8997
8998         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8999             eeprom->magic != TG3_EEPROM_MAGIC)
9000                 return -EINVAL;
9001
9002         offset = eeprom->offset;
9003         len = eeprom->len;
9004
9005         if ((b_offset = (offset & 3))) {
9006                 /* adjustments to start on required 4 byte boundary */
9007                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9008                 if (ret)
9009                         return ret;
9010                 len += b_offset;
9011                 offset &= ~3;
9012                 if (len < 4)
9013                         len = 4;
9014         }
9015
9016         odd_len = 0;
9017         if (len & 3) {
9018                 /* adjustments to end on required 4 byte boundary */
9019                 odd_len = 1;
9020                 len = (len + 3) & ~3;
9021                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9022                 if (ret)
9023                         return ret;
9024         }
9025
9026         buf = data;
9027         if (b_offset || odd_len) {
9028                 buf = kmalloc(len, GFP_KERNEL);
9029                 if (!buf)
9030                         return -ENOMEM;
9031                 if (b_offset)
9032                         memcpy(buf, &start, 4);
9033                 if (odd_len)
9034                         memcpy(buf+len-4, &end, 4);
9035                 memcpy(buf + b_offset, data, eeprom->len);
9036         }
9037
9038         ret = tg3_nvram_write_block(tp, offset, len, buf);
9039
9040         if (buf != data)
9041                 kfree(buf);
9042
9043         return ret;
9044 }
9045
9046 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9047 {
9048         struct tg3 *tp = netdev_priv(dev);
9049
9050         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9051                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9052                         return -EAGAIN;
9053                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9054         }
9055
9056         cmd->supported = (SUPPORTED_Autoneg);
9057
9058         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9059                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9060                                    SUPPORTED_1000baseT_Full);
9061
9062         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9063                 cmd->supported |= (SUPPORTED_100baseT_Half |
9064                                   SUPPORTED_100baseT_Full |
9065                                   SUPPORTED_10baseT_Half |
9066                                   SUPPORTED_10baseT_Full |
9067                                   SUPPORTED_TP);
9068                 cmd->port = PORT_TP;
9069         } else {
9070                 cmd->supported |= SUPPORTED_FIBRE;
9071                 cmd->port = PORT_FIBRE;
9072         }
9073
9074         cmd->advertising = tp->link_config.advertising;
9075         if (netif_running(dev)) {
9076                 cmd->speed = tp->link_config.active_speed;
9077                 cmd->duplex = tp->link_config.active_duplex;
9078         }
9079         cmd->phy_address = PHY_ADDR;
9080         cmd->transceiver = XCVR_INTERNAL;
9081         cmd->autoneg = tp->link_config.autoneg;
9082         cmd->maxtxpkt = 0;
9083         cmd->maxrxpkt = 0;
9084         return 0;
9085 }
9086
9087 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9088 {
9089         struct tg3 *tp = netdev_priv(dev);
9090
9091         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9092                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9093                         return -EAGAIN;
9094                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9095         }
9096
9097         if (cmd->autoneg != AUTONEG_ENABLE &&
9098             cmd->autoneg != AUTONEG_DISABLE)
9099                 return -EINVAL;
9100
9101         if (cmd->autoneg == AUTONEG_DISABLE &&
9102             cmd->duplex != DUPLEX_FULL &&
9103             cmd->duplex != DUPLEX_HALF)
9104                 return -EINVAL;
9105
9106         if (cmd->autoneg == AUTONEG_ENABLE) {
9107                 u32 mask = ADVERTISED_Autoneg |
9108                            ADVERTISED_Pause |
9109                            ADVERTISED_Asym_Pause;
9110
9111                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9112                         mask |= ADVERTISED_1000baseT_Half |
9113                                 ADVERTISED_1000baseT_Full;
9114
9115                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9116                         mask |= ADVERTISED_100baseT_Half |
9117                                 ADVERTISED_100baseT_Full |
9118                                 ADVERTISED_10baseT_Half |
9119                                 ADVERTISED_10baseT_Full |
9120                                 ADVERTISED_TP;
9121                 else
9122                         mask |= ADVERTISED_FIBRE;
9123
9124                 if (cmd->advertising & ~mask)
9125                         return -EINVAL;
9126
9127                 mask &= (ADVERTISED_1000baseT_Half |
9128                          ADVERTISED_1000baseT_Full |
9129                          ADVERTISED_100baseT_Half |
9130                          ADVERTISED_100baseT_Full |
9131                          ADVERTISED_10baseT_Half |
9132                          ADVERTISED_10baseT_Full);
9133
9134                 cmd->advertising &= mask;
9135         } else {
9136                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9137                         if (cmd->speed != SPEED_1000)
9138                                 return -EINVAL;
9139
9140                         if (cmd->duplex != DUPLEX_FULL)
9141                                 return -EINVAL;
9142                 } else {
9143                         if (cmd->speed != SPEED_100 &&
9144                             cmd->speed != SPEED_10)
9145                                 return -EINVAL;
9146                 }
9147         }
9148
9149         tg3_full_lock(tp, 0);
9150
9151         tp->link_config.autoneg = cmd->autoneg;
9152         if (cmd->autoneg == AUTONEG_ENABLE) {
9153                 tp->link_config.advertising = (cmd->advertising |
9154                                               ADVERTISED_Autoneg);
9155                 tp->link_config.speed = SPEED_INVALID;
9156                 tp->link_config.duplex = DUPLEX_INVALID;
9157         } else {
9158                 tp->link_config.advertising = 0;
9159                 tp->link_config.speed = cmd->speed;
9160                 tp->link_config.duplex = cmd->duplex;
9161         }
9162
9163         tp->link_config.orig_speed = tp->link_config.speed;
9164         tp->link_config.orig_duplex = tp->link_config.duplex;
9165         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9166
9167         if (netif_running(dev))
9168                 tg3_setup_phy(tp, 1);
9169
9170         tg3_full_unlock(tp);
9171
9172         return 0;
9173 }
9174
9175 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9176 {
9177         struct tg3 *tp = netdev_priv(dev);
9178
9179         strcpy(info->driver, DRV_MODULE_NAME);
9180         strcpy(info->version, DRV_MODULE_VERSION);
9181         strcpy(info->fw_version, tp->fw_ver);
9182         strcpy(info->bus_info, pci_name(tp->pdev));
9183 }
9184
9185 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9186 {
9187         struct tg3 *tp = netdev_priv(dev);
9188
9189         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9190             device_can_wakeup(&tp->pdev->dev))
9191                 wol->supported = WAKE_MAGIC;
9192         else
9193                 wol->supported = 0;
9194         wol->wolopts = 0;
9195         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9196             device_can_wakeup(&tp->pdev->dev))
9197                 wol->wolopts = WAKE_MAGIC;
9198         memset(&wol->sopass, 0, sizeof(wol->sopass));
9199 }
9200
9201 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9202 {
9203         struct tg3 *tp = netdev_priv(dev);
9204         struct device *dp = &tp->pdev->dev;
9205
9206         if (wol->wolopts & ~WAKE_MAGIC)
9207                 return -EINVAL;
9208         if ((wol->wolopts & WAKE_MAGIC) &&
9209             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9210                 return -EINVAL;
9211
9212         spin_lock_bh(&tp->lock);
9213         if (wol->wolopts & WAKE_MAGIC) {
9214                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9215                 device_set_wakeup_enable(dp, true);
9216         } else {
9217                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9218                 device_set_wakeup_enable(dp, false);
9219         }
9220         spin_unlock_bh(&tp->lock);
9221
9222         return 0;
9223 }
9224
9225 static u32 tg3_get_msglevel(struct net_device *dev)
9226 {
9227         struct tg3 *tp = netdev_priv(dev);
9228         return tp->msg_enable;
9229 }
9230
9231 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9232 {
9233         struct tg3 *tp = netdev_priv(dev);
9234         tp->msg_enable = value;
9235 }
9236
9237 static int tg3_set_tso(struct net_device *dev, u32 value)
9238 {
9239         struct tg3 *tp = netdev_priv(dev);
9240
9241         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9242                 if (value)
9243                         return -EINVAL;
9244                 return 0;
9245         }
9246         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9247             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9248                 if (value) {
9249                         dev->features |= NETIF_F_TSO6;
9250                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9251                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9252                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9253                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9254                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9255                                 dev->features |= NETIF_F_TSO_ECN;
9256                 } else
9257                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9258         }
9259         return ethtool_op_set_tso(dev, value);
9260 }
9261
9262 static int tg3_nway_reset(struct net_device *dev)
9263 {
9264         struct tg3 *tp = netdev_priv(dev);
9265         int r;
9266
9267         if (!netif_running(dev))
9268                 return -EAGAIN;
9269
9270         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9271                 return -EINVAL;
9272
9273         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9274                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9275                         return -EAGAIN;
9276                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9277         } else {
9278                 u32 bmcr;
9279
9280                 spin_lock_bh(&tp->lock);
9281                 r = -EINVAL;
9282                 tg3_readphy(tp, MII_BMCR, &bmcr);
9283                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9284                     ((bmcr & BMCR_ANENABLE) ||
9285                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9286                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9287                                                    BMCR_ANENABLE);
9288                         r = 0;
9289                 }
9290                 spin_unlock_bh(&tp->lock);
9291         }
9292
9293         return r;
9294 }
9295
9296 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9297 {
9298         struct tg3 *tp = netdev_priv(dev);
9299
9300         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9301         ering->rx_mini_max_pending = 0;
9302         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9303                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9304         else
9305                 ering->rx_jumbo_max_pending = 0;
9306
9307         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9308
9309         ering->rx_pending = tp->rx_pending;
9310         ering->rx_mini_pending = 0;
9311         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9312                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9313         else
9314                 ering->rx_jumbo_pending = 0;
9315
9316         ering->tx_pending = tp->napi[0].tx_pending;
9317 }
9318
9319 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9320 {
9321         struct tg3 *tp = netdev_priv(dev);
9322         int i, irq_sync = 0, err = 0;
9323
9324         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9325             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9326             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9327             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9328             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9329              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9330                 return -EINVAL;
9331
9332         if (netif_running(dev)) {
9333                 tg3_phy_stop(tp);
9334                 tg3_netif_stop(tp);
9335                 irq_sync = 1;
9336         }
9337
9338         tg3_full_lock(tp, irq_sync);
9339
9340         tp->rx_pending = ering->rx_pending;
9341
9342         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9343             tp->rx_pending > 63)
9344                 tp->rx_pending = 63;
9345         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9346
9347         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9348                 tp->napi[i].tx_pending = ering->tx_pending;
9349
9350         if (netif_running(dev)) {
9351                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9352                 err = tg3_restart_hw(tp, 1);
9353                 if (!err)
9354                         tg3_netif_start(tp);
9355         }
9356
9357         tg3_full_unlock(tp);
9358
9359         if (irq_sync && !err)
9360                 tg3_phy_start(tp);
9361
9362         return err;
9363 }
9364
9365 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9366 {
9367         struct tg3 *tp = netdev_priv(dev);
9368
9369         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9370
9371         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9372                 epause->rx_pause = 1;
9373         else
9374                 epause->rx_pause = 0;
9375
9376         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9377                 epause->tx_pause = 1;
9378         else
9379                 epause->tx_pause = 0;
9380 }
9381
9382 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9383 {
9384         struct tg3 *tp = netdev_priv(dev);
9385         int err = 0;
9386
9387         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9388                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9389                         return -EAGAIN;
9390
9391                 if (epause->autoneg) {
9392                         u32 newadv;
9393                         struct phy_device *phydev;
9394
9395                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9396
9397                         if (epause->rx_pause) {
9398                                 if (epause->tx_pause)
9399                                         newadv = ADVERTISED_Pause;
9400                                 else
9401                                         newadv = ADVERTISED_Pause |
9402                                                  ADVERTISED_Asym_Pause;
9403                         } else if (epause->tx_pause) {
9404                                 newadv = ADVERTISED_Asym_Pause;
9405                         } else
9406                                 newadv = 0;
9407
9408                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9409                                 u32 oldadv = phydev->advertising &
9410                                              (ADVERTISED_Pause |
9411                                               ADVERTISED_Asym_Pause);
9412                                 if (oldadv != newadv) {
9413                                         phydev->advertising &=
9414                                                 ~(ADVERTISED_Pause |
9415                                                   ADVERTISED_Asym_Pause);
9416                                         phydev->advertising |= newadv;
9417                                         err = phy_start_aneg(phydev);
9418                                 }
9419                         } else {
9420                                 tp->link_config.advertising &=
9421                                                 ~(ADVERTISED_Pause |
9422                                                   ADVERTISED_Asym_Pause);
9423                                 tp->link_config.advertising |= newadv;
9424                         }
9425                 } else {
9426                         if (epause->rx_pause)
9427                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9428                         else
9429                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9430
9431                         if (epause->tx_pause)
9432                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9433                         else
9434                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9435
9436                         if (netif_running(dev))
9437                                 tg3_setup_flow_control(tp, 0, 0);
9438                 }
9439         } else {
9440                 int irq_sync = 0;
9441
9442                 if (netif_running(dev)) {
9443                         tg3_netif_stop(tp);
9444                         irq_sync = 1;
9445                 }
9446
9447                 tg3_full_lock(tp, irq_sync);
9448
9449                 if (epause->autoneg)
9450                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9451                 else
9452                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9453                 if (epause->rx_pause)
9454                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9455                 else
9456                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9457                 if (epause->tx_pause)
9458                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9459                 else
9460                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9461
9462                 if (netif_running(dev)) {
9463                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9464                         err = tg3_restart_hw(tp, 1);
9465                         if (!err)
9466                                 tg3_netif_start(tp);
9467                 }
9468
9469                 tg3_full_unlock(tp);
9470         }
9471
9472         return err;
9473 }
9474
9475 static u32 tg3_get_rx_csum(struct net_device *dev)
9476 {
9477         struct tg3 *tp = netdev_priv(dev);
9478         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9479 }
9480
9481 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9482 {
9483         struct tg3 *tp = netdev_priv(dev);
9484
9485         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9486                 if (data != 0)
9487                         return -EINVAL;
9488                 return 0;
9489         }
9490
9491         spin_lock_bh(&tp->lock);
9492         if (data)
9493                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9494         else
9495                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9496         spin_unlock_bh(&tp->lock);
9497
9498         return 0;
9499 }
9500
9501 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9502 {
9503         struct tg3 *tp = netdev_priv(dev);
9504
9505         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9506                 if (data != 0)
9507                         return -EINVAL;
9508                 return 0;
9509         }
9510
9511         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9512                 ethtool_op_set_tx_ipv6_csum(dev, data);
9513         else
9514                 ethtool_op_set_tx_csum(dev, data);
9515
9516         return 0;
9517 }
9518
9519 static int tg3_get_sset_count (struct net_device *dev, int sset)
9520 {
9521         switch (sset) {
9522         case ETH_SS_TEST:
9523                 return TG3_NUM_TEST;
9524         case ETH_SS_STATS:
9525                 return TG3_NUM_STATS;
9526         default:
9527                 return -EOPNOTSUPP;
9528         }
9529 }
9530
9531 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9532 {
9533         switch (stringset) {
9534         case ETH_SS_STATS:
9535                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9536                 break;
9537         case ETH_SS_TEST:
9538                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9539                 break;
9540         default:
9541                 WARN_ON(1);     /* we need a WARN() */
9542                 break;
9543         }
9544 }
9545
9546 static int tg3_phys_id(struct net_device *dev, u32 data)
9547 {
9548         struct tg3 *tp = netdev_priv(dev);
9549         int i;
9550
9551         if (!netif_running(tp->dev))
9552                 return -EAGAIN;
9553
9554         if (data == 0)
9555                 data = UINT_MAX / 2;
9556
9557         for (i = 0; i < (data * 2); i++) {
9558                 if ((i % 2) == 0)
9559                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9560                                            LED_CTRL_1000MBPS_ON |
9561                                            LED_CTRL_100MBPS_ON |
9562                                            LED_CTRL_10MBPS_ON |
9563                                            LED_CTRL_TRAFFIC_OVERRIDE |
9564                                            LED_CTRL_TRAFFIC_BLINK |
9565                                            LED_CTRL_TRAFFIC_LED);
9566
9567                 else
9568                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9569                                            LED_CTRL_TRAFFIC_OVERRIDE);
9570
9571                 if (msleep_interruptible(500))
9572                         break;
9573         }
9574         tw32(MAC_LED_CTRL, tp->led_ctrl);
9575         return 0;
9576 }
9577
9578 static void tg3_get_ethtool_stats (struct net_device *dev,
9579                                    struct ethtool_stats *estats, u64 *tmp_stats)
9580 {
9581         struct tg3 *tp = netdev_priv(dev);
9582         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9583 }
9584
9585 #define NVRAM_TEST_SIZE 0x100
9586 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9587 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9588 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9589 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9590 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9591
9592 static int tg3_test_nvram(struct tg3 *tp)
9593 {
9594         u32 csum, magic;
9595         __be32 *buf;
9596         int i, j, k, err = 0, size;
9597
9598         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9599                 return 0;
9600
9601         if (tg3_nvram_read(tp, 0, &magic) != 0)
9602                 return -EIO;
9603
9604         if (magic == TG3_EEPROM_MAGIC)
9605                 size = NVRAM_TEST_SIZE;
9606         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9607                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9608                     TG3_EEPROM_SB_FORMAT_1) {
9609                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9610                         case TG3_EEPROM_SB_REVISION_0:
9611                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9612                                 break;
9613                         case TG3_EEPROM_SB_REVISION_2:
9614                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9615                                 break;
9616                         case TG3_EEPROM_SB_REVISION_3:
9617                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9618                                 break;
9619                         default:
9620                                 return 0;
9621                         }
9622                 } else
9623                         return 0;
9624         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9625                 size = NVRAM_SELFBOOT_HW_SIZE;
9626         else
9627                 return -EIO;
9628
9629         buf = kmalloc(size, GFP_KERNEL);
9630         if (buf == NULL)
9631                 return -ENOMEM;
9632
9633         err = -EIO;
9634         for (i = 0, j = 0; i < size; i += 4, j++) {
9635                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9636                 if (err)
9637                         break;
9638         }
9639         if (i < size)
9640                 goto out;
9641
9642         /* Selfboot format */
9643         magic = be32_to_cpu(buf[0]);
9644         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9645             TG3_EEPROM_MAGIC_FW) {
9646                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9647
9648                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9649                     TG3_EEPROM_SB_REVISION_2) {
9650                         /* For rev 2, the csum doesn't include the MBA. */
9651                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9652                                 csum8 += buf8[i];
9653                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9654                                 csum8 += buf8[i];
9655                 } else {
9656                         for (i = 0; i < size; i++)
9657                                 csum8 += buf8[i];
9658                 }
9659
9660                 if (csum8 == 0) {
9661                         err = 0;
9662                         goto out;
9663                 }
9664
9665                 err = -EIO;
9666                 goto out;
9667         }
9668
9669         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9670             TG3_EEPROM_MAGIC_HW) {
9671                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9672                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9673                 u8 *buf8 = (u8 *) buf;
9674
9675                 /* Separate the parity bits and the data bytes.  */
9676                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9677                         if ((i == 0) || (i == 8)) {
9678                                 int l;
9679                                 u8 msk;
9680
9681                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9682                                         parity[k++] = buf8[i] & msk;
9683                                 i++;
9684                         }
9685                         else if (i == 16) {
9686                                 int l;
9687                                 u8 msk;
9688
9689                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9690                                         parity[k++] = buf8[i] & msk;
9691                                 i++;
9692
9693                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9694                                         parity[k++] = buf8[i] & msk;
9695                                 i++;
9696                         }
9697                         data[j++] = buf8[i];
9698                 }
9699
9700                 err = -EIO;
9701                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9702                         u8 hw8 = hweight8(data[i]);
9703
9704                         if ((hw8 & 0x1) && parity[i])
9705                                 goto out;
9706                         else if (!(hw8 & 0x1) && !parity[i])
9707                                 goto out;
9708                 }
9709                 err = 0;
9710                 goto out;
9711         }
9712
9713         /* Bootstrap checksum at offset 0x10 */
9714         csum = calc_crc((unsigned char *) buf, 0x10);
9715         if (csum != be32_to_cpu(buf[0x10/4]))
9716                 goto out;
9717
9718         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9719         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9720         if (csum != be32_to_cpu(buf[0xfc/4]))
9721                 goto out;
9722
9723         err = 0;
9724
9725 out:
9726         kfree(buf);
9727         return err;
9728 }
9729
9730 #define TG3_SERDES_TIMEOUT_SEC  2
9731 #define TG3_COPPER_TIMEOUT_SEC  6
9732
9733 static int tg3_test_link(struct tg3 *tp)
9734 {
9735         int i, max;
9736
9737         if (!netif_running(tp->dev))
9738                 return -ENODEV;
9739
9740         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9741                 max = TG3_SERDES_TIMEOUT_SEC;
9742         else
9743                 max = TG3_COPPER_TIMEOUT_SEC;
9744
9745         for (i = 0; i < max; i++) {
9746                 if (netif_carrier_ok(tp->dev))
9747                         return 0;
9748
9749                 if (msleep_interruptible(1000))
9750                         break;
9751         }
9752
9753         return -EIO;
9754 }
9755
9756 /* Only test the commonly used registers */
9757 static int tg3_test_registers(struct tg3 *tp)
9758 {
9759         int i, is_5705, is_5750;
9760         u32 offset, read_mask, write_mask, val, save_val, read_val;
9761         static struct {
9762                 u16 offset;
9763                 u16 flags;
9764 #define TG3_FL_5705     0x1
9765 #define TG3_FL_NOT_5705 0x2
9766 #define TG3_FL_NOT_5788 0x4
9767 #define TG3_FL_NOT_5750 0x8
9768                 u32 read_mask;
9769                 u32 write_mask;
9770         } reg_tbl[] = {
9771                 /* MAC Control Registers */
9772                 { MAC_MODE, TG3_FL_NOT_5705,
9773                         0x00000000, 0x00ef6f8c },
9774                 { MAC_MODE, TG3_FL_5705,
9775                         0x00000000, 0x01ef6b8c },
9776                 { MAC_STATUS, TG3_FL_NOT_5705,
9777                         0x03800107, 0x00000000 },
9778                 { MAC_STATUS, TG3_FL_5705,
9779                         0x03800100, 0x00000000 },
9780                 { MAC_ADDR_0_HIGH, 0x0000,
9781                         0x00000000, 0x0000ffff },
9782                 { MAC_ADDR_0_LOW, 0x0000,
9783                         0x00000000, 0xffffffff },
9784                 { MAC_RX_MTU_SIZE, 0x0000,
9785                         0x00000000, 0x0000ffff },
9786                 { MAC_TX_MODE, 0x0000,
9787                         0x00000000, 0x00000070 },
9788                 { MAC_TX_LENGTHS, 0x0000,
9789                         0x00000000, 0x00003fff },
9790                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9791                         0x00000000, 0x000007fc },
9792                 { MAC_RX_MODE, TG3_FL_5705,
9793                         0x00000000, 0x000007dc },
9794                 { MAC_HASH_REG_0, 0x0000,
9795                         0x00000000, 0xffffffff },
9796                 { MAC_HASH_REG_1, 0x0000,
9797                         0x00000000, 0xffffffff },
9798                 { MAC_HASH_REG_2, 0x0000,
9799                         0x00000000, 0xffffffff },
9800                 { MAC_HASH_REG_3, 0x0000,
9801                         0x00000000, 0xffffffff },
9802
9803                 /* Receive Data and Receive BD Initiator Control Registers. */
9804                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9805                         0x00000000, 0xffffffff },
9806                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9807                         0x00000000, 0xffffffff },
9808                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9809                         0x00000000, 0x00000003 },
9810                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9811                         0x00000000, 0xffffffff },
9812                 { RCVDBDI_STD_BD+0, 0x0000,
9813                         0x00000000, 0xffffffff },
9814                 { RCVDBDI_STD_BD+4, 0x0000,
9815                         0x00000000, 0xffffffff },
9816                 { RCVDBDI_STD_BD+8, 0x0000,
9817                         0x00000000, 0xffff0002 },
9818                 { RCVDBDI_STD_BD+0xc, 0x0000,
9819                         0x00000000, 0xffffffff },
9820
9821                 /* Receive BD Initiator Control Registers. */
9822                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9823                         0x00000000, 0xffffffff },
9824                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9825                         0x00000000, 0x000003ff },
9826                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9827                         0x00000000, 0xffffffff },
9828
9829                 /* Host Coalescing Control Registers. */
9830                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9831                         0x00000000, 0x00000004 },
9832                 { HOSTCC_MODE, TG3_FL_5705,
9833                         0x00000000, 0x000000f6 },
9834                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9835                         0x00000000, 0xffffffff },
9836                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9837                         0x00000000, 0x000003ff },
9838                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9839                         0x00000000, 0xffffffff },
9840                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9841                         0x00000000, 0x000003ff },
9842                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9843                         0x00000000, 0xffffffff },
9844                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9845                         0x00000000, 0x000000ff },
9846                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9847                         0x00000000, 0xffffffff },
9848                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9849                         0x00000000, 0x000000ff },
9850                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9851                         0x00000000, 0xffffffff },
9852                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9853                         0x00000000, 0xffffffff },
9854                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9855                         0x00000000, 0xffffffff },
9856                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9857                         0x00000000, 0x000000ff },
9858                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9859                         0x00000000, 0xffffffff },
9860                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9861                         0x00000000, 0x000000ff },
9862                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9863                         0x00000000, 0xffffffff },
9864                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9865                         0x00000000, 0xffffffff },
9866                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9867                         0x00000000, 0xffffffff },
9868                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9869                         0x00000000, 0xffffffff },
9870                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9871                         0x00000000, 0xffffffff },
9872                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9873                         0xffffffff, 0x00000000 },
9874                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9875                         0xffffffff, 0x00000000 },
9876
9877                 /* Buffer Manager Control Registers. */
9878                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9879                         0x00000000, 0x007fff80 },
9880                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9881                         0x00000000, 0x007fffff },
9882                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9883                         0x00000000, 0x0000003f },
9884                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9885                         0x00000000, 0x000001ff },
9886                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9887                         0x00000000, 0x000001ff },
9888                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9889                         0xffffffff, 0x00000000 },
9890                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9891                         0xffffffff, 0x00000000 },
9892
9893                 /* Mailbox Registers */
9894                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9895                         0x00000000, 0x000001ff },
9896                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9897                         0x00000000, 0x000001ff },
9898                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9899                         0x00000000, 0x000007ff },
9900                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9901                         0x00000000, 0x000001ff },
9902
9903                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9904         };
9905
9906         is_5705 = is_5750 = 0;
9907         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9908                 is_5705 = 1;
9909                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9910                         is_5750 = 1;
9911         }
9912
9913         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9914                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9915                         continue;
9916
9917                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9918                         continue;
9919
9920                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9921                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9922                         continue;
9923
9924                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9925                         continue;
9926
9927                 offset = (u32) reg_tbl[i].offset;
9928                 read_mask = reg_tbl[i].read_mask;
9929                 write_mask = reg_tbl[i].write_mask;
9930
9931                 /* Save the original register content */
9932                 save_val = tr32(offset);
9933
9934                 /* Determine the read-only value. */
9935                 read_val = save_val & read_mask;
9936
9937                 /* Write zero to the register, then make sure the read-only bits
9938                  * are not changed and the read/write bits are all zeros.
9939                  */
9940                 tw32(offset, 0);
9941
9942                 val = tr32(offset);
9943
9944                 /* Test the read-only and read/write bits. */
9945                 if (((val & read_mask) != read_val) || (val & write_mask))
9946                         goto out;
9947
9948                 /* Write ones to all the bits defined by RdMask and WrMask, then
9949                  * make sure the read-only bits are not changed and the
9950                  * read/write bits are all ones.
9951                  */
9952                 tw32(offset, read_mask | write_mask);
9953
9954                 val = tr32(offset);
9955
9956                 /* Test the read-only bits. */
9957                 if ((val & read_mask) != read_val)
9958                         goto out;
9959
9960                 /* Test the read/write bits. */
9961                 if ((val & write_mask) != write_mask)
9962                         goto out;
9963
9964                 tw32(offset, save_val);
9965         }
9966
9967         return 0;
9968
9969 out:
9970         if (netif_msg_hw(tp))
9971                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9972                        offset);
9973         tw32(offset, save_val);
9974         return -EIO;
9975 }
9976
9977 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9978 {
9979         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9980         int i;
9981         u32 j;
9982
9983         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9984                 for (j = 0; j < len; j += 4) {
9985                         u32 val;
9986
9987                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9988                         tg3_read_mem(tp, offset + j, &val);
9989                         if (val != test_pattern[i])
9990                                 return -EIO;
9991                 }
9992         }
9993         return 0;
9994 }
9995
9996 static int tg3_test_memory(struct tg3 *tp)
9997 {
9998         static struct mem_entry {
9999                 u32 offset;
10000                 u32 len;
10001         } mem_tbl_570x[] = {
10002                 { 0x00000000, 0x00b50},
10003                 { 0x00002000, 0x1c000},
10004                 { 0xffffffff, 0x00000}
10005         }, mem_tbl_5705[] = {
10006                 { 0x00000100, 0x0000c},
10007                 { 0x00000200, 0x00008},
10008                 { 0x00004000, 0x00800},
10009                 { 0x00006000, 0x01000},
10010                 { 0x00008000, 0x02000},
10011                 { 0x00010000, 0x0e000},
10012                 { 0xffffffff, 0x00000}
10013         }, mem_tbl_5755[] = {
10014                 { 0x00000200, 0x00008},
10015                 { 0x00004000, 0x00800},
10016                 { 0x00006000, 0x00800},
10017                 { 0x00008000, 0x02000},
10018                 { 0x00010000, 0x0c000},
10019                 { 0xffffffff, 0x00000}
10020         }, mem_tbl_5906[] = {
10021                 { 0x00000200, 0x00008},
10022                 { 0x00004000, 0x00400},
10023                 { 0x00006000, 0x00400},
10024                 { 0x00008000, 0x01000},
10025                 { 0x00010000, 0x01000},
10026                 { 0xffffffff, 0x00000}
10027         };
10028         struct mem_entry *mem_tbl;
10029         int err = 0;
10030         int i;
10031
10032         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10033                 mem_tbl = mem_tbl_5755;
10034         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10035                 mem_tbl = mem_tbl_5906;
10036         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10037                 mem_tbl = mem_tbl_5705;
10038         else
10039                 mem_tbl = mem_tbl_570x;
10040
10041         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10042                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10043                     mem_tbl[i].len)) != 0)
10044                         break;
10045         }
10046
10047         return err;
10048 }
10049
10050 #define TG3_MAC_LOOPBACK        0
10051 #define TG3_PHY_LOOPBACK        1
10052
10053 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10054 {
10055         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10056         u32 desc_idx, coal_now;
10057         struct sk_buff *skb, *rx_skb;
10058         u8 *tx_data;
10059         dma_addr_t map;
10060         int num_pkts, tx_len, rx_len, i, err;
10061         struct tg3_rx_buffer_desc *desc;
10062         struct tg3_napi *tnapi, *rnapi;
10063         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10064
10065         tnapi = &tp->napi[0];
10066         rnapi = &tp->napi[0];
10067         coal_now = tnapi->coal_now | rnapi->coal_now;
10068
10069         if (loopback_mode == TG3_MAC_LOOPBACK) {
10070                 /* HW errata - mac loopback fails in some cases on 5780.
10071                  * Normal traffic and PHY loopback are not affected by
10072                  * errata.
10073                  */
10074                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10075                         return 0;
10076
10077                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10078                            MAC_MODE_PORT_INT_LPBACK;
10079                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10080                         mac_mode |= MAC_MODE_LINK_POLARITY;
10081                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10082                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10083                 else
10084                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10085                 tw32(MAC_MODE, mac_mode);
10086         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10087                 u32 val;
10088
10089                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10090                         tg3_phy_fet_toggle_apd(tp, false);
10091                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10092                 } else
10093                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10094
10095                 tg3_phy_toggle_automdix(tp, 0);
10096
10097                 tg3_writephy(tp, MII_BMCR, val);
10098                 udelay(40);
10099
10100                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10101                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10102                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10103                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10104                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10105                 } else
10106                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10107
10108                 /* reset to prevent losing 1st rx packet intermittently */
10109                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10110                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10111                         udelay(10);
10112                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10113                 }
10114                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10115                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10116                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10117                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10118                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10119                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10120                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10121                 }
10122                 tw32(MAC_MODE, mac_mode);
10123         }
10124         else
10125                 return -EINVAL;
10126
10127         err = -EIO;
10128
10129         tx_len = 1514;
10130         skb = netdev_alloc_skb(tp->dev, tx_len);
10131         if (!skb)
10132                 return -ENOMEM;
10133
10134         tx_data = skb_put(skb, tx_len);
10135         memcpy(tx_data, tp->dev->dev_addr, 6);
10136         memset(tx_data + 6, 0x0, 8);
10137
10138         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10139
10140         for (i = 14; i < tx_len; i++)
10141                 tx_data[i] = (u8) (i & 0xff);
10142
10143         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10144
10145         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10146                rnapi->coal_now);
10147
10148         udelay(10);
10149
10150         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10151
10152         num_pkts = 0;
10153
10154         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10155
10156         tnapi->tx_prod++;
10157         num_pkts++;
10158
10159         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10160         tr32_mailbox(tnapi->prodmbox);
10161
10162         udelay(10);
10163
10164         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10165         for (i = 0; i < 25; i++) {
10166                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10167                        coal_now);
10168
10169                 udelay(10);
10170
10171                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10172                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10173                 if ((tx_idx == tnapi->tx_prod) &&
10174                     (rx_idx == (rx_start_idx + num_pkts)))
10175                         break;
10176         }
10177
10178         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10179         dev_kfree_skb(skb);
10180
10181         if (tx_idx != tnapi->tx_prod)
10182                 goto out;
10183
10184         if (rx_idx != rx_start_idx + num_pkts)
10185                 goto out;
10186
10187         desc = &rnapi->rx_rcb[rx_start_idx];
10188         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10189         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10190         if (opaque_key != RXD_OPAQUE_RING_STD)
10191                 goto out;
10192
10193         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10194             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10195                 goto out;
10196
10197         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10198         if (rx_len != tx_len)
10199                 goto out;
10200
10201         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10202
10203         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10204         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10205
10206         for (i = 14; i < tx_len; i++) {
10207                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10208                         goto out;
10209         }
10210         err = 0;
10211
10212         /* tg3_free_rings will unmap and free the rx_skb */
10213 out:
10214         return err;
10215 }
10216
10217 #define TG3_MAC_LOOPBACK_FAILED         1
10218 #define TG3_PHY_LOOPBACK_FAILED         2
10219 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10220                                          TG3_PHY_LOOPBACK_FAILED)
10221
10222 static int tg3_test_loopback(struct tg3 *tp)
10223 {
10224         int err = 0;
10225         u32 cpmuctrl = 0;
10226
10227         if (!netif_running(tp->dev))
10228                 return TG3_LOOPBACK_FAILED;
10229
10230         err = tg3_reset_hw(tp, 1);
10231         if (err)
10232                 return TG3_LOOPBACK_FAILED;
10233
10234         /* Turn off gphy autopowerdown. */
10235         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10236                 tg3_phy_toggle_apd(tp, false);
10237
10238         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10239                 int i;
10240                 u32 status;
10241
10242                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10243
10244                 /* Wait for up to 40 microseconds to acquire lock. */
10245                 for (i = 0; i < 4; i++) {
10246                         status = tr32(TG3_CPMU_MUTEX_GNT);
10247                         if (status == CPMU_MUTEX_GNT_DRIVER)
10248                                 break;
10249                         udelay(10);
10250                 }
10251
10252                 if (status != CPMU_MUTEX_GNT_DRIVER)
10253                         return TG3_LOOPBACK_FAILED;
10254
10255                 /* Turn off link-based power management. */
10256                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10257                 tw32(TG3_CPMU_CTRL,
10258                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10259                                   CPMU_CTRL_LINK_AWARE_MODE));
10260         }
10261
10262         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10263                 err |= TG3_MAC_LOOPBACK_FAILED;
10264
10265         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10266                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10267
10268                 /* Release the mutex */
10269                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10270         }
10271
10272         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10273             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10274                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10275                         err |= TG3_PHY_LOOPBACK_FAILED;
10276         }
10277
10278         /* Re-enable gphy autopowerdown. */
10279         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10280                 tg3_phy_toggle_apd(tp, true);
10281
10282         return err;
10283 }
10284
10285 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10286                           u64 *data)
10287 {
10288         struct tg3 *tp = netdev_priv(dev);
10289
10290         if (tp->link_config.phy_is_low_power)
10291                 tg3_set_power_state(tp, PCI_D0);
10292
10293         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10294
10295         if (tg3_test_nvram(tp) != 0) {
10296                 etest->flags |= ETH_TEST_FL_FAILED;
10297                 data[0] = 1;
10298         }
10299         if (tg3_test_link(tp) != 0) {
10300                 etest->flags |= ETH_TEST_FL_FAILED;
10301                 data[1] = 1;
10302         }
10303         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10304                 int err, err2 = 0, irq_sync = 0;
10305
10306                 if (netif_running(dev)) {
10307                         tg3_phy_stop(tp);
10308                         tg3_netif_stop(tp);
10309                         irq_sync = 1;
10310                 }
10311
10312                 tg3_full_lock(tp, irq_sync);
10313
10314                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10315                 err = tg3_nvram_lock(tp);
10316                 tg3_halt_cpu(tp, RX_CPU_BASE);
10317                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10318                         tg3_halt_cpu(tp, TX_CPU_BASE);
10319                 if (!err)
10320                         tg3_nvram_unlock(tp);
10321
10322                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10323                         tg3_phy_reset(tp);
10324
10325                 if (tg3_test_registers(tp) != 0) {
10326                         etest->flags |= ETH_TEST_FL_FAILED;
10327                         data[2] = 1;
10328                 }
10329                 if (tg3_test_memory(tp) != 0) {
10330                         etest->flags |= ETH_TEST_FL_FAILED;
10331                         data[3] = 1;
10332                 }
10333                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10334                         etest->flags |= ETH_TEST_FL_FAILED;
10335
10336                 tg3_full_unlock(tp);
10337
10338                 if (tg3_test_interrupt(tp) != 0) {
10339                         etest->flags |= ETH_TEST_FL_FAILED;
10340                         data[5] = 1;
10341                 }
10342
10343                 tg3_full_lock(tp, 0);
10344
10345                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10346                 if (netif_running(dev)) {
10347                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10348                         err2 = tg3_restart_hw(tp, 1);
10349                         if (!err2)
10350                                 tg3_netif_start(tp);
10351                 }
10352
10353                 tg3_full_unlock(tp);
10354
10355                 if (irq_sync && !err2)
10356                         tg3_phy_start(tp);
10357         }
10358         if (tp->link_config.phy_is_low_power)
10359                 tg3_set_power_state(tp, PCI_D3hot);
10360
10361 }
10362
10363 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10364 {
10365         struct mii_ioctl_data *data = if_mii(ifr);
10366         struct tg3 *tp = netdev_priv(dev);
10367         int err;
10368
10369         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10370                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10371                         return -EAGAIN;
10372                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10373         }
10374
10375         switch(cmd) {
10376         case SIOCGMIIPHY:
10377                 data->phy_id = PHY_ADDR;
10378
10379                 /* fallthru */
10380         case SIOCGMIIREG: {
10381                 u32 mii_regval;
10382
10383                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10384                         break;                  /* We have no PHY */
10385
10386                 if (tp->link_config.phy_is_low_power)
10387                         return -EAGAIN;
10388
10389                 spin_lock_bh(&tp->lock);
10390                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10391                 spin_unlock_bh(&tp->lock);
10392
10393                 data->val_out = mii_regval;
10394
10395                 return err;
10396         }
10397
10398         case SIOCSMIIREG:
10399                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10400                         break;                  /* We have no PHY */
10401
10402                 if (!capable(CAP_NET_ADMIN))
10403                         return -EPERM;
10404
10405                 if (tp->link_config.phy_is_low_power)
10406                         return -EAGAIN;
10407
10408                 spin_lock_bh(&tp->lock);
10409                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10410                 spin_unlock_bh(&tp->lock);
10411
10412                 return err;
10413
10414         default:
10415                 /* do nothing */
10416                 break;
10417         }
10418         return -EOPNOTSUPP;
10419 }
10420
10421 #if TG3_VLAN_TAG_USED
10422 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10423 {
10424         struct tg3 *tp = netdev_priv(dev);
10425
10426         if (!netif_running(dev)) {
10427                 tp->vlgrp = grp;
10428                 return;
10429         }
10430
10431         tg3_netif_stop(tp);
10432
10433         tg3_full_lock(tp, 0);
10434
10435         tp->vlgrp = grp;
10436
10437         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10438         __tg3_set_rx_mode(dev);
10439
10440         tg3_netif_start(tp);
10441
10442         tg3_full_unlock(tp);
10443 }
10444 #endif
10445
10446 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10447 {
10448         struct tg3 *tp = netdev_priv(dev);
10449
10450         memcpy(ec, &tp->coal, sizeof(*ec));
10451         return 0;
10452 }
10453
10454 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10455 {
10456         struct tg3 *tp = netdev_priv(dev);
10457         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10458         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10459
10460         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10461                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10462                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10463                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10464                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10465         }
10466
10467         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10468             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10469             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10470             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10471             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10472             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10473             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10474             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10475             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10476             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10477                 return -EINVAL;
10478
10479         /* No rx interrupts will be generated if both are zero */
10480         if ((ec->rx_coalesce_usecs == 0) &&
10481             (ec->rx_max_coalesced_frames == 0))
10482                 return -EINVAL;
10483
10484         /* No tx interrupts will be generated if both are zero */
10485         if ((ec->tx_coalesce_usecs == 0) &&
10486             (ec->tx_max_coalesced_frames == 0))
10487                 return -EINVAL;
10488
10489         /* Only copy relevant parameters, ignore all others. */
10490         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10491         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10492         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10493         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10494         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10495         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10496         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10497         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10498         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10499
10500         if (netif_running(dev)) {
10501                 tg3_full_lock(tp, 0);
10502                 __tg3_set_coalesce(tp, &tp->coal);
10503                 tg3_full_unlock(tp);
10504         }
10505         return 0;
10506 }
10507
10508 static const struct ethtool_ops tg3_ethtool_ops = {
10509         .get_settings           = tg3_get_settings,
10510         .set_settings           = tg3_set_settings,
10511         .get_drvinfo            = tg3_get_drvinfo,
10512         .get_regs_len           = tg3_get_regs_len,
10513         .get_regs               = tg3_get_regs,
10514         .get_wol                = tg3_get_wol,
10515         .set_wol                = tg3_set_wol,
10516         .get_msglevel           = tg3_get_msglevel,
10517         .set_msglevel           = tg3_set_msglevel,
10518         .nway_reset             = tg3_nway_reset,
10519         .get_link               = ethtool_op_get_link,
10520         .get_eeprom_len         = tg3_get_eeprom_len,
10521         .get_eeprom             = tg3_get_eeprom,
10522         .set_eeprom             = tg3_set_eeprom,
10523         .get_ringparam          = tg3_get_ringparam,
10524         .set_ringparam          = tg3_set_ringparam,
10525         .get_pauseparam         = tg3_get_pauseparam,
10526         .set_pauseparam         = tg3_set_pauseparam,
10527         .get_rx_csum            = tg3_get_rx_csum,
10528         .set_rx_csum            = tg3_set_rx_csum,
10529         .set_tx_csum            = tg3_set_tx_csum,
10530         .set_sg                 = ethtool_op_set_sg,
10531         .set_tso                = tg3_set_tso,
10532         .self_test              = tg3_self_test,
10533         .get_strings            = tg3_get_strings,
10534         .phys_id                = tg3_phys_id,
10535         .get_ethtool_stats      = tg3_get_ethtool_stats,
10536         .get_coalesce           = tg3_get_coalesce,
10537         .set_coalesce           = tg3_set_coalesce,
10538         .get_sset_count         = tg3_get_sset_count,
10539 };
10540
10541 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10542 {
10543         u32 cursize, val, magic;
10544
10545         tp->nvram_size = EEPROM_CHIP_SIZE;
10546
10547         if (tg3_nvram_read(tp, 0, &magic) != 0)
10548                 return;
10549
10550         if ((magic != TG3_EEPROM_MAGIC) &&
10551             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10552             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10553                 return;
10554
10555         /*
10556          * Size the chip by reading offsets at increasing powers of two.
10557          * When we encounter our validation signature, we know the addressing
10558          * has wrapped around, and thus have our chip size.
10559          */
10560         cursize = 0x10;
10561
10562         while (cursize < tp->nvram_size) {
10563                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10564                         return;
10565
10566                 if (val == magic)
10567                         break;
10568
10569                 cursize <<= 1;
10570         }
10571
10572         tp->nvram_size = cursize;
10573 }
10574
10575 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10576 {
10577         u32 val;
10578
10579         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10580             tg3_nvram_read(tp, 0, &val) != 0)
10581                 return;
10582
10583         /* Selfboot format */
10584         if (val != TG3_EEPROM_MAGIC) {
10585                 tg3_get_eeprom_size(tp);
10586                 return;
10587         }
10588
10589         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10590                 if (val != 0) {
10591                         /* This is confusing.  We want to operate on the
10592                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10593                          * call will read from NVRAM and byteswap the data
10594                          * according to the byteswapping settings for all
10595                          * other register accesses.  This ensures the data we
10596                          * want will always reside in the lower 16-bits.
10597                          * However, the data in NVRAM is in LE format, which
10598                          * means the data from the NVRAM read will always be
10599                          * opposite the endianness of the CPU.  The 16-bit
10600                          * byteswap then brings the data to CPU endianness.
10601                          */
10602                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10603                         return;
10604                 }
10605         }
10606         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10607 }
10608
10609 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10610 {
10611         u32 nvcfg1;
10612
10613         nvcfg1 = tr32(NVRAM_CFG1);
10614         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10615                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10616         } else {
10617                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10618                 tw32(NVRAM_CFG1, nvcfg1);
10619         }
10620
10621         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10622             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10623                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10624                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10625                         tp->nvram_jedecnum = JEDEC_ATMEL;
10626                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10627                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10628                         break;
10629                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10630                         tp->nvram_jedecnum = JEDEC_ATMEL;
10631                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10632                         break;
10633                 case FLASH_VENDOR_ATMEL_EEPROM:
10634                         tp->nvram_jedecnum = JEDEC_ATMEL;
10635                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10636                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10637                         break;
10638                 case FLASH_VENDOR_ST:
10639                         tp->nvram_jedecnum = JEDEC_ST;
10640                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10641                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10642                         break;
10643                 case FLASH_VENDOR_SAIFUN:
10644                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10645                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10646                         break;
10647                 case FLASH_VENDOR_SST_SMALL:
10648                 case FLASH_VENDOR_SST_LARGE:
10649                         tp->nvram_jedecnum = JEDEC_SST;
10650                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10651                         break;
10652                 }
10653         } else {
10654                 tp->nvram_jedecnum = JEDEC_ATMEL;
10655                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10656                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10657         }
10658 }
10659
10660 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10661 {
10662         u32 nvcfg1;
10663
10664         nvcfg1 = tr32(NVRAM_CFG1);
10665
10666         /* NVRAM protection for TPM */
10667         if (nvcfg1 & (1 << 27))
10668                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10669
10670         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10671         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10672         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10673                 tp->nvram_jedecnum = JEDEC_ATMEL;
10674                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10675                 break;
10676         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10677                 tp->nvram_jedecnum = JEDEC_ATMEL;
10678                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10679                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10680                 break;
10681         case FLASH_5752VENDOR_ST_M45PE10:
10682         case FLASH_5752VENDOR_ST_M45PE20:
10683         case FLASH_5752VENDOR_ST_M45PE40:
10684                 tp->nvram_jedecnum = JEDEC_ST;
10685                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10686                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10687                 break;
10688         }
10689
10690         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10691                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10692                 case FLASH_5752PAGE_SIZE_256:
10693                         tp->nvram_pagesize = 256;
10694                         break;
10695                 case FLASH_5752PAGE_SIZE_512:
10696                         tp->nvram_pagesize = 512;
10697                         break;
10698                 case FLASH_5752PAGE_SIZE_1K:
10699                         tp->nvram_pagesize = 1024;
10700                         break;
10701                 case FLASH_5752PAGE_SIZE_2K:
10702                         tp->nvram_pagesize = 2048;
10703                         break;
10704                 case FLASH_5752PAGE_SIZE_4K:
10705                         tp->nvram_pagesize = 4096;
10706                         break;
10707                 case FLASH_5752PAGE_SIZE_264:
10708                         tp->nvram_pagesize = 264;
10709                         break;
10710                 }
10711         } else {
10712                 /* For eeprom, set pagesize to maximum eeprom size */
10713                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10714
10715                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10716                 tw32(NVRAM_CFG1, nvcfg1);
10717         }
10718 }
10719
10720 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10721 {
10722         u32 nvcfg1, protect = 0;
10723
10724         nvcfg1 = tr32(NVRAM_CFG1);
10725
10726         /* NVRAM protection for TPM */
10727         if (nvcfg1 & (1 << 27)) {
10728                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10729                 protect = 1;
10730         }
10731
10732         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10733         switch (nvcfg1) {
10734         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10735         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10736         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10737         case FLASH_5755VENDOR_ATMEL_FLASH_5:
10738                 tp->nvram_jedecnum = JEDEC_ATMEL;
10739                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10740                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10741                 tp->nvram_pagesize = 264;
10742                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10743                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10744                         tp->nvram_size = (protect ? 0x3e200 :
10745                                           TG3_NVRAM_SIZE_512KB);
10746                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10747                         tp->nvram_size = (protect ? 0x1f200 :
10748                                           TG3_NVRAM_SIZE_256KB);
10749                 else
10750                         tp->nvram_size = (protect ? 0x1f200 :
10751                                           TG3_NVRAM_SIZE_128KB);
10752                 break;
10753         case FLASH_5752VENDOR_ST_M45PE10:
10754         case FLASH_5752VENDOR_ST_M45PE20:
10755         case FLASH_5752VENDOR_ST_M45PE40:
10756                 tp->nvram_jedecnum = JEDEC_ST;
10757                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10758                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10759                 tp->nvram_pagesize = 256;
10760                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10761                         tp->nvram_size = (protect ?
10762                                           TG3_NVRAM_SIZE_64KB :
10763                                           TG3_NVRAM_SIZE_128KB);
10764                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10765                         tp->nvram_size = (protect ?
10766                                           TG3_NVRAM_SIZE_64KB :
10767                                           TG3_NVRAM_SIZE_256KB);
10768                 else
10769                         tp->nvram_size = (protect ?
10770                                           TG3_NVRAM_SIZE_128KB :
10771                                           TG3_NVRAM_SIZE_512KB);
10772                 break;
10773         }
10774 }
10775
10776 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10777 {
10778         u32 nvcfg1;
10779
10780         nvcfg1 = tr32(NVRAM_CFG1);
10781
10782         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10783         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10784         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10785         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10786         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10787                 tp->nvram_jedecnum = JEDEC_ATMEL;
10788                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10789                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10790
10791                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10792                 tw32(NVRAM_CFG1, nvcfg1);
10793                 break;
10794         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10795         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10796         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10797         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10798                 tp->nvram_jedecnum = JEDEC_ATMEL;
10799                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10800                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10801                 tp->nvram_pagesize = 264;
10802                 break;
10803         case FLASH_5752VENDOR_ST_M45PE10:
10804         case FLASH_5752VENDOR_ST_M45PE20:
10805         case FLASH_5752VENDOR_ST_M45PE40:
10806                 tp->nvram_jedecnum = JEDEC_ST;
10807                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10808                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10809                 tp->nvram_pagesize = 256;
10810                 break;
10811         }
10812 }
10813
10814 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10815 {
10816         u32 nvcfg1, protect = 0;
10817
10818         nvcfg1 = tr32(NVRAM_CFG1);
10819
10820         /* NVRAM protection for TPM */
10821         if (nvcfg1 & (1 << 27)) {
10822                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10823                 protect = 1;
10824         }
10825
10826         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10827         switch (nvcfg1) {
10828         case FLASH_5761VENDOR_ATMEL_ADB021D:
10829         case FLASH_5761VENDOR_ATMEL_ADB041D:
10830         case FLASH_5761VENDOR_ATMEL_ADB081D:
10831         case FLASH_5761VENDOR_ATMEL_ADB161D:
10832         case FLASH_5761VENDOR_ATMEL_MDB021D:
10833         case FLASH_5761VENDOR_ATMEL_MDB041D:
10834         case FLASH_5761VENDOR_ATMEL_MDB081D:
10835         case FLASH_5761VENDOR_ATMEL_MDB161D:
10836                 tp->nvram_jedecnum = JEDEC_ATMEL;
10837                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10838                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10839                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10840                 tp->nvram_pagesize = 256;
10841                 break;
10842         case FLASH_5761VENDOR_ST_A_M45PE20:
10843         case FLASH_5761VENDOR_ST_A_M45PE40:
10844         case FLASH_5761VENDOR_ST_A_M45PE80:
10845         case FLASH_5761VENDOR_ST_A_M45PE16:
10846         case FLASH_5761VENDOR_ST_M_M45PE20:
10847         case FLASH_5761VENDOR_ST_M_M45PE40:
10848         case FLASH_5761VENDOR_ST_M_M45PE80:
10849         case FLASH_5761VENDOR_ST_M_M45PE16:
10850                 tp->nvram_jedecnum = JEDEC_ST;
10851                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10852                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10853                 tp->nvram_pagesize = 256;
10854                 break;
10855         }
10856
10857         if (protect) {
10858                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10859         } else {
10860                 switch (nvcfg1) {
10861                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10862                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10863                 case FLASH_5761VENDOR_ST_A_M45PE16:
10864                 case FLASH_5761VENDOR_ST_M_M45PE16:
10865                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10866                         break;
10867                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10868                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10869                 case FLASH_5761VENDOR_ST_A_M45PE80:
10870                 case FLASH_5761VENDOR_ST_M_M45PE80:
10871                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10872                         break;
10873                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10874                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10875                 case FLASH_5761VENDOR_ST_A_M45PE40:
10876                 case FLASH_5761VENDOR_ST_M_M45PE40:
10877                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10878                         break;
10879                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10880                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10881                 case FLASH_5761VENDOR_ST_A_M45PE20:
10882                 case FLASH_5761VENDOR_ST_M_M45PE20:
10883                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10884                         break;
10885                 }
10886         }
10887 }
10888
10889 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10890 {
10891         tp->nvram_jedecnum = JEDEC_ATMEL;
10892         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10893         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10894 }
10895
10896 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10897 {
10898         u32 nvcfg1;
10899
10900         nvcfg1 = tr32(NVRAM_CFG1);
10901
10902         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10903         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10904         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10905                 tp->nvram_jedecnum = JEDEC_ATMEL;
10906                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10907                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10908
10909                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10910                 tw32(NVRAM_CFG1, nvcfg1);
10911                 return;
10912         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10913         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10914         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10915         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10916         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10917         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10918         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10919                 tp->nvram_jedecnum = JEDEC_ATMEL;
10920                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10921                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10922
10923                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10924                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10925                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10926                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10927                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10928                         break;
10929                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10930                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10931                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10932                         break;
10933                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10934                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10935                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10936                         break;
10937                 }
10938                 break;
10939         case FLASH_5752VENDOR_ST_M45PE10:
10940         case FLASH_5752VENDOR_ST_M45PE20:
10941         case FLASH_5752VENDOR_ST_M45PE40:
10942                 tp->nvram_jedecnum = JEDEC_ST;
10943                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10944                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10945
10946                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10947                 case FLASH_5752VENDOR_ST_M45PE10:
10948                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10949                         break;
10950                 case FLASH_5752VENDOR_ST_M45PE20:
10951                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10952                         break;
10953                 case FLASH_5752VENDOR_ST_M45PE40:
10954                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10955                         break;
10956                 }
10957                 break;
10958         default:
10959                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10960                 return;
10961         }
10962
10963         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10964         case FLASH_5752PAGE_SIZE_256:
10965                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10966                 tp->nvram_pagesize = 256;
10967                 break;
10968         case FLASH_5752PAGE_SIZE_512:
10969                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10970                 tp->nvram_pagesize = 512;
10971                 break;
10972         case FLASH_5752PAGE_SIZE_1K:
10973                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10974                 tp->nvram_pagesize = 1024;
10975                 break;
10976         case FLASH_5752PAGE_SIZE_2K:
10977                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10978                 tp->nvram_pagesize = 2048;
10979                 break;
10980         case FLASH_5752PAGE_SIZE_4K:
10981                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10982                 tp->nvram_pagesize = 4096;
10983                 break;
10984         case FLASH_5752PAGE_SIZE_264:
10985                 tp->nvram_pagesize = 264;
10986                 break;
10987         case FLASH_5752PAGE_SIZE_528:
10988                 tp->nvram_pagesize = 528;
10989                 break;
10990         }
10991 }
10992
10993 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10994 static void __devinit tg3_nvram_init(struct tg3 *tp)
10995 {
10996         tw32_f(GRC_EEPROM_ADDR,
10997              (EEPROM_ADDR_FSM_RESET |
10998               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10999                EEPROM_ADDR_CLKPERD_SHIFT)));
11000
11001         msleep(1);
11002
11003         /* Enable seeprom accesses. */
11004         tw32_f(GRC_LOCAL_CTRL,
11005              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11006         udelay(100);
11007
11008         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11009             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11010                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11011
11012                 if (tg3_nvram_lock(tp)) {
11013                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11014                                "tg3_nvram_init failed.\n", tp->dev->name);
11015                         return;
11016                 }
11017                 tg3_enable_nvram_access(tp);
11018
11019                 tp->nvram_size = 0;
11020
11021                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11022                         tg3_get_5752_nvram_info(tp);
11023                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11024                         tg3_get_5755_nvram_info(tp);
11025                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11026                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11027                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11028                         tg3_get_5787_nvram_info(tp);
11029                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11030                         tg3_get_5761_nvram_info(tp);
11031                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11032                         tg3_get_5906_nvram_info(tp);
11033                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11034                         tg3_get_57780_nvram_info(tp);
11035                 else
11036                         tg3_get_nvram_info(tp);
11037
11038                 if (tp->nvram_size == 0)
11039                         tg3_get_nvram_size(tp);
11040
11041                 tg3_disable_nvram_access(tp);
11042                 tg3_nvram_unlock(tp);
11043
11044         } else {
11045                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11046
11047                 tg3_get_eeprom_size(tp);
11048         }
11049 }
11050
11051 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11052                                     u32 offset, u32 len, u8 *buf)
11053 {
11054         int i, j, rc = 0;
11055         u32 val;
11056
11057         for (i = 0; i < len; i += 4) {
11058                 u32 addr;
11059                 __be32 data;
11060
11061                 addr = offset + i;
11062
11063                 memcpy(&data, buf + i, 4);
11064
11065                 /*
11066                  * The SEEPROM interface expects the data to always be opposite
11067                  * the native endian format.  We accomplish this by reversing
11068                  * all the operations that would have been performed on the
11069                  * data from a call to tg3_nvram_read_be32().
11070                  */
11071                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11072
11073                 val = tr32(GRC_EEPROM_ADDR);
11074                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11075
11076                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11077                         EEPROM_ADDR_READ);
11078                 tw32(GRC_EEPROM_ADDR, val |
11079                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11080                         (addr & EEPROM_ADDR_ADDR_MASK) |
11081                         EEPROM_ADDR_START |
11082                         EEPROM_ADDR_WRITE);
11083
11084                 for (j = 0; j < 1000; j++) {
11085                         val = tr32(GRC_EEPROM_ADDR);
11086
11087                         if (val & EEPROM_ADDR_COMPLETE)
11088                                 break;
11089                         msleep(1);
11090                 }
11091                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11092                         rc = -EBUSY;
11093                         break;
11094                 }
11095         }
11096
11097         return rc;
11098 }
11099
11100 /* offset and length are dword aligned */
11101 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11102                 u8 *buf)
11103 {
11104         int ret = 0;
11105         u32 pagesize = tp->nvram_pagesize;
11106         u32 pagemask = pagesize - 1;
11107         u32 nvram_cmd;
11108         u8 *tmp;
11109
11110         tmp = kmalloc(pagesize, GFP_KERNEL);
11111         if (tmp == NULL)
11112                 return -ENOMEM;
11113
11114         while (len) {
11115                 int j;
11116                 u32 phy_addr, page_off, size;
11117
11118                 phy_addr = offset & ~pagemask;
11119
11120                 for (j = 0; j < pagesize; j += 4) {
11121                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11122                                                   (__be32 *) (tmp + j));
11123                         if (ret)
11124                                 break;
11125                 }
11126                 if (ret)
11127                         break;
11128
11129                 page_off = offset & pagemask;
11130                 size = pagesize;
11131                 if (len < size)
11132                         size = len;
11133
11134                 len -= size;
11135
11136                 memcpy(tmp + page_off, buf, size);
11137
11138                 offset = offset + (pagesize - page_off);
11139
11140                 tg3_enable_nvram_access(tp);
11141
11142                 /*
11143                  * Before we can erase the flash page, we need
11144                  * to issue a special "write enable" command.
11145                  */
11146                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11147
11148                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11149                         break;
11150
11151                 /* Erase the target page */
11152                 tw32(NVRAM_ADDR, phy_addr);
11153
11154                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11155                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11156
11157                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11158                         break;
11159
11160                 /* Issue another write enable to start the write. */
11161                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11162
11163                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11164                         break;
11165
11166                 for (j = 0; j < pagesize; j += 4) {
11167                         __be32 data;
11168
11169                         data = *((__be32 *) (tmp + j));
11170
11171                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11172
11173                         tw32(NVRAM_ADDR, phy_addr + j);
11174
11175                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11176                                 NVRAM_CMD_WR;
11177
11178                         if (j == 0)
11179                                 nvram_cmd |= NVRAM_CMD_FIRST;
11180                         else if (j == (pagesize - 4))
11181                                 nvram_cmd |= NVRAM_CMD_LAST;
11182
11183                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11184                                 break;
11185                 }
11186                 if (ret)
11187                         break;
11188         }
11189
11190         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11191         tg3_nvram_exec_cmd(tp, nvram_cmd);
11192
11193         kfree(tmp);
11194
11195         return ret;
11196 }
11197
11198 /* offset and length are dword aligned */
11199 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11200                 u8 *buf)
11201 {
11202         int i, ret = 0;
11203
11204         for (i = 0; i < len; i += 4, offset += 4) {
11205                 u32 page_off, phy_addr, nvram_cmd;
11206                 __be32 data;
11207
11208                 memcpy(&data, buf + i, 4);
11209                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11210
11211                 page_off = offset % tp->nvram_pagesize;
11212
11213                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11214
11215                 tw32(NVRAM_ADDR, phy_addr);
11216
11217                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11218
11219                 if ((page_off == 0) || (i == 0))
11220                         nvram_cmd |= NVRAM_CMD_FIRST;
11221                 if (page_off == (tp->nvram_pagesize - 4))
11222                         nvram_cmd |= NVRAM_CMD_LAST;
11223
11224                 if (i == (len - 4))
11225                         nvram_cmd |= NVRAM_CMD_LAST;
11226
11227                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11228                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11229                     (tp->nvram_jedecnum == JEDEC_ST) &&
11230                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11231
11232                         if ((ret = tg3_nvram_exec_cmd(tp,
11233                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11234                                 NVRAM_CMD_DONE)))
11235
11236                                 break;
11237                 }
11238                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11239                         /* We always do complete word writes to eeprom. */
11240                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11241                 }
11242
11243                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11244                         break;
11245         }
11246         return ret;
11247 }
11248
11249 /* offset and length are dword aligned */
11250 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11251 {
11252         int ret;
11253
11254         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11255                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11256                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11257                 udelay(40);
11258         }
11259
11260         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11261                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11262         }
11263         else {
11264                 u32 grc_mode;
11265
11266                 ret = tg3_nvram_lock(tp);
11267                 if (ret)
11268                         return ret;
11269
11270                 tg3_enable_nvram_access(tp);
11271                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11272                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11273                         tw32(NVRAM_WRITE1, 0x406);
11274
11275                 grc_mode = tr32(GRC_MODE);
11276                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11277
11278                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11279                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11280
11281                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11282                                 buf);
11283                 }
11284                 else {
11285                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11286                                 buf);
11287                 }
11288
11289                 grc_mode = tr32(GRC_MODE);
11290                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11291
11292                 tg3_disable_nvram_access(tp);
11293                 tg3_nvram_unlock(tp);
11294         }
11295
11296         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11297                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11298                 udelay(40);
11299         }
11300
11301         return ret;
11302 }
11303
11304 struct subsys_tbl_ent {
11305         u16 subsys_vendor, subsys_devid;
11306         u32 phy_id;
11307 };
11308
11309 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11310         /* Broadcom boards. */
11311         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11312         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11313         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11314         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11315         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11316         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11317         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11318         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11319         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11320         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11321         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11322
11323         /* 3com boards. */
11324         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11325         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11326         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11327         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11328         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11329
11330         /* DELL boards. */
11331         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11332         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11333         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11334         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11335
11336         /* Compaq boards. */
11337         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11338         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11339         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11340         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11341         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11342
11343         /* IBM boards. */
11344         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11345 };
11346
11347 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11348 {
11349         int i;
11350
11351         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11352                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11353                      tp->pdev->subsystem_vendor) &&
11354                     (subsys_id_to_phy_id[i].subsys_devid ==
11355                      tp->pdev->subsystem_device))
11356                         return &subsys_id_to_phy_id[i];
11357         }
11358         return NULL;
11359 }
11360
11361 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11362 {
11363         u32 val;
11364         u16 pmcsr;
11365
11366         /* On some early chips the SRAM cannot be accessed in D3hot state,
11367          * so need make sure we're in D0.
11368          */
11369         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11370         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11371         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11372         msleep(1);
11373
11374         /* Make sure register accesses (indirect or otherwise)
11375          * will function correctly.
11376          */
11377         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11378                                tp->misc_host_ctrl);
11379
11380         /* The memory arbiter has to be enabled in order for SRAM accesses
11381          * to succeed.  Normally on powerup the tg3 chip firmware will make
11382          * sure it is enabled, but other entities such as system netboot
11383          * code might disable it.
11384          */
11385         val = tr32(MEMARB_MODE);
11386         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11387
11388         tp->phy_id = PHY_ID_INVALID;
11389         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11390
11391         /* Assume an onboard device and WOL capable by default.  */
11392         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11393
11394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11395                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11396                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11397                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11398                 }
11399                 val = tr32(VCPU_CFGSHDW);
11400                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11401                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11402                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11403                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11404                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11405                 goto done;
11406         }
11407
11408         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11409         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11410                 u32 nic_cfg, led_cfg;
11411                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11412                 int eeprom_phy_serdes = 0;
11413
11414                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11415                 tp->nic_sram_data_cfg = nic_cfg;
11416
11417                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11418                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11419                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11420                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11421                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11422                     (ver > 0) && (ver < 0x100))
11423                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11424
11425                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11426                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11427
11428                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11429                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11430                         eeprom_phy_serdes = 1;
11431
11432                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11433                 if (nic_phy_id != 0) {
11434                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11435                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11436
11437                         eeprom_phy_id  = (id1 >> 16) << 10;
11438                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11439                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11440                 } else
11441                         eeprom_phy_id = 0;
11442
11443                 tp->phy_id = eeprom_phy_id;
11444                 if (eeprom_phy_serdes) {
11445                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11446                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11447                         else
11448                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11449                 }
11450
11451                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11452                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11453                                     SHASTA_EXT_LED_MODE_MASK);
11454                 else
11455                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11456
11457                 switch (led_cfg) {
11458                 default:
11459                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11460                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11461                         break;
11462
11463                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11464                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11465                         break;
11466
11467                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11468                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11469
11470                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11471                          * read on some older 5700/5701 bootcode.
11472                          */
11473                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11474                             ASIC_REV_5700 ||
11475                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11476                             ASIC_REV_5701)
11477                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11478
11479                         break;
11480
11481                 case SHASTA_EXT_LED_SHARED:
11482                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11483                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11484                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11485                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11486                                                  LED_CTRL_MODE_PHY_2);
11487                         break;
11488
11489                 case SHASTA_EXT_LED_MAC:
11490                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11491                         break;
11492
11493                 case SHASTA_EXT_LED_COMBO:
11494                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11495                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11496                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11497                                                  LED_CTRL_MODE_PHY_2);
11498                         break;
11499
11500                 }
11501
11502                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11503                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11504                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11505                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11506
11507                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11508                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11509
11510                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11511                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11512                         if ((tp->pdev->subsystem_vendor ==
11513                              PCI_VENDOR_ID_ARIMA) &&
11514                             (tp->pdev->subsystem_device == 0x205a ||
11515                              tp->pdev->subsystem_device == 0x2063))
11516                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11517                 } else {
11518                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11519                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11520                 }
11521
11522                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11523                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11524                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11525                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11526                 }
11527
11528                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11529                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11530                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11531
11532                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11533                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11534                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11535
11536                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11537                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11538                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11539
11540                 if (cfg2 & (1 << 17))
11541                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11542
11543                 /* serdes signal pre-emphasis in register 0x590 set by */
11544                 /* bootcode if bit 18 is set */
11545                 if (cfg2 & (1 << 18))
11546                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11547
11548                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11549                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11550                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11551                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11552
11553                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11554                         u32 cfg3;
11555
11556                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11557                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11558                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11559                 }
11560
11561                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11562                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11563                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11564                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11565                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11566                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11567         }
11568 done:
11569         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11570         device_set_wakeup_enable(&tp->pdev->dev,
11571                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11572 }
11573
11574 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11575 {
11576         int i;
11577         u32 val;
11578
11579         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11580         tw32(OTP_CTRL, cmd);
11581
11582         /* Wait for up to 1 ms for command to execute. */
11583         for (i = 0; i < 100; i++) {
11584                 val = tr32(OTP_STATUS);
11585                 if (val & OTP_STATUS_CMD_DONE)
11586                         break;
11587                 udelay(10);
11588         }
11589
11590         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11591 }
11592
11593 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11594  * configuration is a 32-bit value that straddles the alignment boundary.
11595  * We do two 32-bit reads and then shift and merge the results.
11596  */
11597 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11598 {
11599         u32 bhalf_otp, thalf_otp;
11600
11601         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11602
11603         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11604                 return 0;
11605
11606         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11607
11608         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11609                 return 0;
11610
11611         thalf_otp = tr32(OTP_READ_DATA);
11612
11613         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11614
11615         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11616                 return 0;
11617
11618         bhalf_otp = tr32(OTP_READ_DATA);
11619
11620         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11621 }
11622
11623 static int __devinit tg3_phy_probe(struct tg3 *tp)
11624 {
11625         u32 hw_phy_id_1, hw_phy_id_2;
11626         u32 hw_phy_id, hw_phy_id_masked;
11627         int err;
11628
11629         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11630                 return tg3_phy_init(tp);
11631
11632         /* Reading the PHY ID register can conflict with ASF
11633          * firmware access to the PHY hardware.
11634          */
11635         err = 0;
11636         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11637             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11638                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11639         } else {
11640                 /* Now read the physical PHY_ID from the chip and verify
11641                  * that it is sane.  If it doesn't look good, we fall back
11642                  * to either the hard-coded table based PHY_ID and failing
11643                  * that the value found in the eeprom area.
11644                  */
11645                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11646                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11647
11648                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11649                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11650                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11651
11652                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11653         }
11654
11655         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11656                 tp->phy_id = hw_phy_id;
11657                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11658                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11659                 else
11660                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11661         } else {
11662                 if (tp->phy_id != PHY_ID_INVALID) {
11663                         /* Do nothing, phy ID already set up in
11664                          * tg3_get_eeprom_hw_cfg().
11665                          */
11666                 } else {
11667                         struct subsys_tbl_ent *p;
11668
11669                         /* No eeprom signature?  Try the hardcoded
11670                          * subsys device table.
11671                          */
11672                         p = lookup_by_subsys(tp);
11673                         if (!p)
11674                                 return -ENODEV;
11675
11676                         tp->phy_id = p->phy_id;
11677                         if (!tp->phy_id ||
11678                             tp->phy_id == PHY_ID_BCM8002)
11679                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11680                 }
11681         }
11682
11683         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11684             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11685             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11686                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11687
11688                 tg3_readphy(tp, MII_BMSR, &bmsr);
11689                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11690                     (bmsr & BMSR_LSTATUS))
11691                         goto skip_phy_reset;
11692
11693                 err = tg3_phy_reset(tp);
11694                 if (err)
11695                         return err;
11696
11697                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11698                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11699                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11700                 tg3_ctrl = 0;
11701                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11702                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11703                                     MII_TG3_CTRL_ADV_1000_FULL);
11704                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11705                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11706                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11707                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11708                 }
11709
11710                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11711                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11712                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11713                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11714                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11715
11716                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11717                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11718
11719                         tg3_writephy(tp, MII_BMCR,
11720                                      BMCR_ANENABLE | BMCR_ANRESTART);
11721                 }
11722                 tg3_phy_set_wirespeed(tp);
11723
11724                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11725                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11726                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11727         }
11728
11729 skip_phy_reset:
11730         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11731                 err = tg3_init_5401phy_dsp(tp);
11732                 if (err)
11733                         return err;
11734         }
11735
11736         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11737                 err = tg3_init_5401phy_dsp(tp);
11738         }
11739
11740         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11741                 tp->link_config.advertising =
11742                         (ADVERTISED_1000baseT_Half |
11743                          ADVERTISED_1000baseT_Full |
11744                          ADVERTISED_Autoneg |
11745                          ADVERTISED_FIBRE);
11746         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11747                 tp->link_config.advertising &=
11748                         ~(ADVERTISED_1000baseT_Half |
11749                           ADVERTISED_1000baseT_Full);
11750
11751         return err;
11752 }
11753
11754 static void __devinit tg3_read_partno(struct tg3 *tp)
11755 {
11756         unsigned char vpd_data[256];   /* in little-endian format */
11757         unsigned int i;
11758         u32 magic;
11759
11760         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11761             tg3_nvram_read(tp, 0x0, &magic))
11762                 goto out_not_found;
11763
11764         if (magic == TG3_EEPROM_MAGIC) {
11765                 for (i = 0; i < 256; i += 4) {
11766                         u32 tmp;
11767
11768                         /* The data is in little-endian format in NVRAM.
11769                          * Use the big-endian read routines to preserve
11770                          * the byte order as it exists in NVRAM.
11771                          */
11772                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11773                                 goto out_not_found;
11774
11775                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11776                 }
11777         } else {
11778                 int vpd_cap;
11779
11780                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11781                 for (i = 0; i < 256; i += 4) {
11782                         u32 tmp, j = 0;
11783                         __le32 v;
11784                         u16 tmp16;
11785
11786                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11787                                               i);
11788                         while (j++ < 100) {
11789                                 pci_read_config_word(tp->pdev, vpd_cap +
11790                                                      PCI_VPD_ADDR, &tmp16);
11791                                 if (tmp16 & 0x8000)
11792                                         break;
11793                                 msleep(1);
11794                         }
11795                         if (!(tmp16 & 0x8000))
11796                                 goto out_not_found;
11797
11798                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11799                                               &tmp);
11800                         v = cpu_to_le32(tmp);
11801                         memcpy(&vpd_data[i], &v, sizeof(v));
11802                 }
11803         }
11804
11805         /* Now parse and find the part number. */
11806         for (i = 0; i < 254; ) {
11807                 unsigned char val = vpd_data[i];
11808                 unsigned int block_end;
11809
11810                 if (val == 0x82 || val == 0x91) {
11811                         i = (i + 3 +
11812                              (vpd_data[i + 1] +
11813                               (vpd_data[i + 2] << 8)));
11814                         continue;
11815                 }
11816
11817                 if (val != 0x90)
11818                         goto out_not_found;
11819
11820                 block_end = (i + 3 +
11821                              (vpd_data[i + 1] +
11822                               (vpd_data[i + 2] << 8)));
11823                 i += 3;
11824
11825                 if (block_end > 256)
11826                         goto out_not_found;
11827
11828                 while (i < (block_end - 2)) {
11829                         if (vpd_data[i + 0] == 'P' &&
11830                             vpd_data[i + 1] == 'N') {
11831                                 int partno_len = vpd_data[i + 2];
11832
11833                                 i += 3;
11834                                 if (partno_len > 24 || (partno_len + i) > 256)
11835                                         goto out_not_found;
11836
11837                                 memcpy(tp->board_part_number,
11838                                        &vpd_data[i], partno_len);
11839
11840                                 /* Success. */
11841                                 return;
11842                         }
11843                         i += 3 + vpd_data[i + 2];
11844                 }
11845
11846                 /* Part number not found. */
11847                 goto out_not_found;
11848         }
11849
11850 out_not_found:
11851         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11852                 strcpy(tp->board_part_number, "BCM95906");
11853         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11854                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11855                 strcpy(tp->board_part_number, "BCM57780");
11856         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11857                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11858                 strcpy(tp->board_part_number, "BCM57760");
11859         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11860                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11861                 strcpy(tp->board_part_number, "BCM57790");
11862         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11863                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11864                 strcpy(tp->board_part_number, "BCM57788");
11865         else
11866                 strcpy(tp->board_part_number, "none");
11867 }
11868
11869 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11870 {
11871         u32 val;
11872
11873         if (tg3_nvram_read(tp, offset, &val) ||
11874             (val & 0xfc000000) != 0x0c000000 ||
11875             tg3_nvram_read(tp, offset + 4, &val) ||
11876             val != 0)
11877                 return 0;
11878
11879         return 1;
11880 }
11881
11882 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11883 {
11884         u32 val, offset, start, ver_offset;
11885         int i;
11886         bool newver = false;
11887
11888         if (tg3_nvram_read(tp, 0xc, &offset) ||
11889             tg3_nvram_read(tp, 0x4, &start))
11890                 return;
11891
11892         offset = tg3_nvram_logical_addr(tp, offset);
11893
11894         if (tg3_nvram_read(tp, offset, &val))
11895                 return;
11896
11897         if ((val & 0xfc000000) == 0x0c000000) {
11898                 if (tg3_nvram_read(tp, offset + 4, &val))
11899                         return;
11900
11901                 if (val == 0)
11902                         newver = true;
11903         }
11904
11905         if (newver) {
11906                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11907                         return;
11908
11909                 offset = offset + ver_offset - start;
11910                 for (i = 0; i < 16; i += 4) {
11911                         __be32 v;
11912                         if (tg3_nvram_read_be32(tp, offset + i, &v))
11913                                 return;
11914
11915                         memcpy(tp->fw_ver + i, &v, sizeof(v));
11916                 }
11917         } else {
11918                 u32 major, minor;
11919
11920                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11921                         return;
11922
11923                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11924                         TG3_NVM_BCVER_MAJSFT;
11925                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11926                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11927         }
11928 }
11929
11930 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11931 {
11932         u32 val, major, minor;
11933
11934         /* Use native endian representation */
11935         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11936                 return;
11937
11938         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11939                 TG3_NVM_HWSB_CFG1_MAJSFT;
11940         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11941                 TG3_NVM_HWSB_CFG1_MINSFT;
11942
11943         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11944 }
11945
11946 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11947 {
11948         u32 offset, major, minor, build;
11949
11950         tp->fw_ver[0] = 's';
11951         tp->fw_ver[1] = 'b';
11952         tp->fw_ver[2] = '\0';
11953
11954         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11955                 return;
11956
11957         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11958         case TG3_EEPROM_SB_REVISION_0:
11959                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11960                 break;
11961         case TG3_EEPROM_SB_REVISION_2:
11962                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11963                 break;
11964         case TG3_EEPROM_SB_REVISION_3:
11965                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11966                 break;
11967         default:
11968                 return;
11969         }
11970
11971         if (tg3_nvram_read(tp, offset, &val))
11972                 return;
11973
11974         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11975                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11976         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11977                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11978         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11979
11980         if (minor > 99 || build > 26)
11981                 return;
11982
11983         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11984
11985         if (build > 0) {
11986                 tp->fw_ver[8] = 'a' + build - 1;
11987                 tp->fw_ver[9] = '\0';
11988         }
11989 }
11990
11991 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11992 {
11993         u32 val, offset, start;
11994         int i, vlen;
11995
11996         for (offset = TG3_NVM_DIR_START;
11997              offset < TG3_NVM_DIR_END;
11998              offset += TG3_NVM_DIRENT_SIZE) {
11999                 if (tg3_nvram_read(tp, offset, &val))
12000                         return;
12001
12002                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12003                         break;
12004         }
12005
12006         if (offset == TG3_NVM_DIR_END)
12007                 return;
12008
12009         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12010                 start = 0x08000000;
12011         else if (tg3_nvram_read(tp, offset - 4, &start))
12012                 return;
12013
12014         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12015             !tg3_fw_img_is_valid(tp, offset) ||
12016             tg3_nvram_read(tp, offset + 8, &val))
12017                 return;
12018
12019         offset += val - start;
12020
12021         vlen = strlen(tp->fw_ver);
12022
12023         tp->fw_ver[vlen++] = ',';
12024         tp->fw_ver[vlen++] = ' ';
12025
12026         for (i = 0; i < 4; i++) {
12027                 __be32 v;
12028                 if (tg3_nvram_read_be32(tp, offset, &v))
12029                         return;
12030
12031                 offset += sizeof(v);
12032
12033                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12034                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12035                         break;
12036                 }
12037
12038                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12039                 vlen += sizeof(v);
12040         }
12041 }
12042
12043 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12044 {
12045         int vlen;
12046         u32 apedata;
12047
12048         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12049             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12050                 return;
12051
12052         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12053         if (apedata != APE_SEG_SIG_MAGIC)
12054                 return;
12055
12056         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12057         if (!(apedata & APE_FW_STATUS_READY))
12058                 return;
12059
12060         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12061
12062         vlen = strlen(tp->fw_ver);
12063
12064         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12065                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12066                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12067                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12068                  (apedata & APE_FW_VERSION_BLDMSK));
12069 }
12070
12071 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12072 {
12073         u32 val;
12074
12075         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12076                 tp->fw_ver[0] = 's';
12077                 tp->fw_ver[1] = 'b';
12078                 tp->fw_ver[2] = '\0';
12079
12080                 return;
12081         }
12082
12083         if (tg3_nvram_read(tp, 0, &val))
12084                 return;
12085
12086         if (val == TG3_EEPROM_MAGIC)
12087                 tg3_read_bc_ver(tp);
12088         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12089                 tg3_read_sb_ver(tp, val);
12090         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12091                 tg3_read_hwsb_ver(tp);
12092         else
12093                 return;
12094
12095         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12096              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12097                 return;
12098
12099         tg3_read_mgmtfw_ver(tp);
12100
12101         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12102 }
12103
12104 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12105
12106 static int __devinit tg3_get_invariants(struct tg3 *tp)
12107 {
12108         static struct pci_device_id write_reorder_chipsets[] = {
12109                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12110                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12111                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12112                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12113                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12114                              PCI_DEVICE_ID_VIA_8385_0) },
12115                 { },
12116         };
12117         u32 misc_ctrl_reg;
12118         u32 pci_state_reg, grc_misc_cfg;
12119         u32 val;
12120         u16 pci_cmd;
12121         int err;
12122
12123         /* Force memory write invalidate off.  If we leave it on,
12124          * then on 5700_BX chips we have to enable a workaround.
12125          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12126          * to match the cacheline size.  The Broadcom driver have this
12127          * workaround but turns MWI off all the times so never uses
12128          * it.  This seems to suggest that the workaround is insufficient.
12129          */
12130         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12131         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12132         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12133
12134         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12135          * has the register indirect write enable bit set before
12136          * we try to access any of the MMIO registers.  It is also
12137          * critical that the PCI-X hw workaround situation is decided
12138          * before that as well.
12139          */
12140         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12141                               &misc_ctrl_reg);
12142
12143         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12144                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12145         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12146                 u32 prod_id_asic_rev;
12147
12148                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12149                                       &prod_id_asic_rev);
12150                 tp->pci_chip_rev_id = prod_id_asic_rev;
12151         }
12152
12153         /* Wrong chip ID in 5752 A0. This code can be removed later
12154          * as A0 is not in production.
12155          */
12156         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12157                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12158
12159         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12160          * we need to disable memory and use config. cycles
12161          * only to access all registers. The 5702/03 chips
12162          * can mistakenly decode the special cycles from the
12163          * ICH chipsets as memory write cycles, causing corruption
12164          * of register and memory space. Only certain ICH bridges
12165          * will drive special cycles with non-zero data during the
12166          * address phase which can fall within the 5703's address
12167          * range. This is not an ICH bug as the PCI spec allows
12168          * non-zero address during special cycles. However, only
12169          * these ICH bridges are known to drive non-zero addresses
12170          * during special cycles.
12171          *
12172          * Since special cycles do not cross PCI bridges, we only
12173          * enable this workaround if the 5703 is on the secondary
12174          * bus of these ICH bridges.
12175          */
12176         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12177             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12178                 static struct tg3_dev_id {
12179                         u32     vendor;
12180                         u32     device;
12181                         u32     rev;
12182                 } ich_chipsets[] = {
12183                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12184                           PCI_ANY_ID },
12185                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12186                           PCI_ANY_ID },
12187                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12188                           0xa },
12189                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12190                           PCI_ANY_ID },
12191                         { },
12192                 };
12193                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12194                 struct pci_dev *bridge = NULL;
12195
12196                 while (pci_id->vendor != 0) {
12197                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12198                                                 bridge);
12199                         if (!bridge) {
12200                                 pci_id++;
12201                                 continue;
12202                         }
12203                         if (pci_id->rev != PCI_ANY_ID) {
12204                                 if (bridge->revision > pci_id->rev)
12205                                         continue;
12206                         }
12207                         if (bridge->subordinate &&
12208                             (bridge->subordinate->number ==
12209                              tp->pdev->bus->number)) {
12210
12211                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12212                                 pci_dev_put(bridge);
12213                                 break;
12214                         }
12215                 }
12216         }
12217
12218         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12219                 static struct tg3_dev_id {
12220                         u32     vendor;
12221                         u32     device;
12222                 } bridge_chipsets[] = {
12223                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12224                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12225                         { },
12226                 };
12227                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12228                 struct pci_dev *bridge = NULL;
12229
12230                 while (pci_id->vendor != 0) {
12231                         bridge = pci_get_device(pci_id->vendor,
12232                                                 pci_id->device,
12233                                                 bridge);
12234                         if (!bridge) {
12235                                 pci_id++;
12236                                 continue;
12237                         }
12238                         if (bridge->subordinate &&
12239                             (bridge->subordinate->number <=
12240                              tp->pdev->bus->number) &&
12241                             (bridge->subordinate->subordinate >=
12242                              tp->pdev->bus->number)) {
12243                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12244                                 pci_dev_put(bridge);
12245                                 break;
12246                         }
12247                 }
12248         }
12249
12250         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12251          * DMA addresses > 40-bit. This bridge may have other additional
12252          * 57xx devices behind it in some 4-port NIC designs for example.
12253          * Any tg3 device found behind the bridge will also need the 40-bit
12254          * DMA workaround.
12255          */
12256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12257             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12258                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12259                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12260                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12261         }
12262         else {
12263                 struct pci_dev *bridge = NULL;
12264
12265                 do {
12266                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12267                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12268                                                 bridge);
12269                         if (bridge && bridge->subordinate &&
12270                             (bridge->subordinate->number <=
12271                              tp->pdev->bus->number) &&
12272                             (bridge->subordinate->subordinate >=
12273                              tp->pdev->bus->number)) {
12274                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12275                                 pci_dev_put(bridge);
12276                                 break;
12277                         }
12278                 } while (bridge);
12279         }
12280
12281         /* Initialize misc host control in PCI block. */
12282         tp->misc_host_ctrl |= (misc_ctrl_reg &
12283                                MISC_HOST_CTRL_CHIPREV);
12284         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12285                                tp->misc_host_ctrl);
12286
12287         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12288             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12289                 tp->pdev_peer = tg3_find_peer(tp);
12290
12291         /* Intentionally exclude ASIC_REV_5906 */
12292         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12293             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12294             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12295             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12296             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12297             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12298                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12299
12300         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12302             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12303             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12304             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12305                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12306
12307         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12308             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12309                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12310
12311         /* 5700 B0 chips do not support checksumming correctly due
12312          * to hardware bugs.
12313          */
12314         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12315                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12316         else {
12317                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12318                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12319                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12320                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12321         }
12322
12323         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12324                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12325                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12326                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12327                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12328                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12329                      tp->pdev_peer == tp->pdev))
12330                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12331
12332                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12333                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12334                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12335                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12336                 } else {
12337                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12338                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12339                                 ASIC_REV_5750 &&
12340                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12341                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12342                 }
12343         }
12344
12345         tp->irq_max = 1;
12346
12347         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12348              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12349                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12350
12351         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12352                               &pci_state_reg);
12353
12354         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12355         if (tp->pcie_cap != 0) {
12356                 u16 lnkctl;
12357
12358                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12359
12360                 pcie_set_readrq(tp->pdev, 4096);
12361
12362                 pci_read_config_word(tp->pdev,
12363                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12364                                      &lnkctl);
12365                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12366                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12367                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12368                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12369                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12370                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12371                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12372                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12373                 }
12374         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12375                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12376         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12377                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12378                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12379                 if (!tp->pcix_cap) {
12380                         printk(KERN_ERR PFX "Cannot find PCI-X "
12381                                             "capability, aborting.\n");
12382                         return -EIO;
12383                 }
12384
12385                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12386                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12387         }
12388
12389         /* If we have an AMD 762 or VIA K8T800 chipset, write
12390          * reordering to the mailbox registers done by the host
12391          * controller can cause major troubles.  We read back from
12392          * every mailbox register write to force the writes to be
12393          * posted to the chip in order.
12394          */
12395         if (pci_dev_present(write_reorder_chipsets) &&
12396             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12397                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12398
12399         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12400                              &tp->pci_cacheline_sz);
12401         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12402                              &tp->pci_lat_timer);
12403         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12404             tp->pci_lat_timer < 64) {
12405                 tp->pci_lat_timer = 64;
12406                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12407                                       tp->pci_lat_timer);
12408         }
12409
12410         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12411                 /* 5700 BX chips need to have their TX producer index
12412                  * mailboxes written twice to workaround a bug.
12413                  */
12414                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12415
12416                 /* If we are in PCI-X mode, enable register write workaround.
12417                  *
12418                  * The workaround is to use indirect register accesses
12419                  * for all chip writes not to mailbox registers.
12420                  */
12421                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12422                         u32 pm_reg;
12423
12424                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12425
12426                         /* The chip can have it's power management PCI config
12427                          * space registers clobbered due to this bug.
12428                          * So explicitly force the chip into D0 here.
12429                          */
12430                         pci_read_config_dword(tp->pdev,
12431                                               tp->pm_cap + PCI_PM_CTRL,
12432                                               &pm_reg);
12433                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12434                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12435                         pci_write_config_dword(tp->pdev,
12436                                                tp->pm_cap + PCI_PM_CTRL,
12437                                                pm_reg);
12438
12439                         /* Also, force SERR#/PERR# in PCI command. */
12440                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12441                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12442                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12443                 }
12444         }
12445
12446         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12447                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12448         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12449                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12450
12451         /* Chip-specific fixup from Broadcom driver */
12452         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12453             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12454                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12455                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12456         }
12457
12458         /* Default fast path register access methods */
12459         tp->read32 = tg3_read32;
12460         tp->write32 = tg3_write32;
12461         tp->read32_mbox = tg3_read32;
12462         tp->write32_mbox = tg3_write32;
12463         tp->write32_tx_mbox = tg3_write32;
12464         tp->write32_rx_mbox = tg3_write32;
12465
12466         /* Various workaround register access methods */
12467         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12468                 tp->write32 = tg3_write_indirect_reg32;
12469         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12470                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12471                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12472                 /*
12473                  * Back to back register writes can cause problems on these
12474                  * chips, the workaround is to read back all reg writes
12475                  * except those to mailbox regs.
12476                  *
12477                  * See tg3_write_indirect_reg32().
12478                  */
12479                 tp->write32 = tg3_write_flush_reg32;
12480         }
12481
12482
12483         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12484             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12485                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12486                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12487                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12488         }
12489
12490         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12491                 tp->read32 = tg3_read_indirect_reg32;
12492                 tp->write32 = tg3_write_indirect_reg32;
12493                 tp->read32_mbox = tg3_read_indirect_mbox;
12494                 tp->write32_mbox = tg3_write_indirect_mbox;
12495                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12496                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12497
12498                 iounmap(tp->regs);
12499                 tp->regs = NULL;
12500
12501                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12502                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12503                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12504         }
12505         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12506                 tp->read32_mbox = tg3_read32_mbox_5906;
12507                 tp->write32_mbox = tg3_write32_mbox_5906;
12508                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12509                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12510         }
12511
12512         if (tp->write32 == tg3_write_indirect_reg32 ||
12513             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12514              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12515               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12516                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12517
12518         /* Get eeprom hw config before calling tg3_set_power_state().
12519          * In particular, the TG3_FLG2_IS_NIC flag must be
12520          * determined before calling tg3_set_power_state() so that
12521          * we know whether or not to switch out of Vaux power.
12522          * When the flag is set, it means that GPIO1 is used for eeprom
12523          * write protect and also implies that it is a LOM where GPIOs
12524          * are not used to switch power.
12525          */
12526         tg3_get_eeprom_hw_cfg(tp);
12527
12528         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12529                 /* Allow reads and writes to the
12530                  * APE register and memory space.
12531                  */
12532                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12533                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12534                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12535                                        pci_state_reg);
12536         }
12537
12538         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12539             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12540             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12541             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12542                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12543
12544         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12545          * GPIO1 driven high will bring 5700's external PHY out of reset.
12546          * It is also used as eeprom write protect on LOMs.
12547          */
12548         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12549         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12550             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12551                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12552                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12553         /* Unused GPIO3 must be driven as output on 5752 because there
12554          * are no pull-up resistors on unused GPIO pins.
12555          */
12556         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12557                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12558
12559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12561                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12562
12563         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12564             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12565                 /* Turn off the debug UART. */
12566                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12567                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12568                         /* Keep VMain power. */
12569                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12570                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12571         }
12572
12573         /* Force the chip into D0. */
12574         err = tg3_set_power_state(tp, PCI_D0);
12575         if (err) {
12576                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12577                        pci_name(tp->pdev));
12578                 return err;
12579         }
12580
12581         /* Derive initial jumbo mode from MTU assigned in
12582          * ether_setup() via the alloc_etherdev() call
12583          */
12584         if (tp->dev->mtu > ETH_DATA_LEN &&
12585             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12586                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12587
12588         /* Determine WakeOnLan speed to use. */
12589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12590             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12591             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12592             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12593                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12594         } else {
12595                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12596         }
12597
12598         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12599                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12600
12601         /* A few boards don't want Ethernet@WireSpeed phy feature */
12602         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12603             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12604              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12605              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12606             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12607             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12608                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12609
12610         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12611             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12612                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12613         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12614                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12615
12616         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12617             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12618             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12619             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12620                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12621                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12622                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12623                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12624                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12625                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12626                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12627                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12628                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12629                 } else
12630                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12631         }
12632
12633         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12634             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12635                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12636                 if (tp->phy_otp == 0)
12637                         tp->phy_otp = TG3_OTP_DEFAULT;
12638         }
12639
12640         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12641                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12642         else
12643                 tp->mi_mode = MAC_MI_MODE_BASE;
12644
12645         tp->coalesce_mode = 0;
12646         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12647             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12648                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12649
12650         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12651             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12652                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12653
12654         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12655              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12656             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12657                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12658
12659         err = tg3_mdio_init(tp);
12660         if (err)
12661                 return err;
12662
12663         /* Initialize data/descriptor byte/word swapping. */
12664         val = tr32(GRC_MODE);
12665         val &= GRC_MODE_HOST_STACKUP;
12666         tw32(GRC_MODE, val | tp->grc_mode);
12667
12668         tg3_switch_clocks(tp);
12669
12670         /* Clear this out for sanity. */
12671         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12672
12673         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12674                               &pci_state_reg);
12675         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12676             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12677                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12678
12679                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12680                     chiprevid == CHIPREV_ID_5701_B0 ||
12681                     chiprevid == CHIPREV_ID_5701_B2 ||
12682                     chiprevid == CHIPREV_ID_5701_B5) {
12683                         void __iomem *sram_base;
12684
12685                         /* Write some dummy words into the SRAM status block
12686                          * area, see if it reads back correctly.  If the return
12687                          * value is bad, force enable the PCIX workaround.
12688                          */
12689                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12690
12691                         writel(0x00000000, sram_base);
12692                         writel(0x00000000, sram_base + 4);
12693                         writel(0xffffffff, sram_base + 4);
12694                         if (readl(sram_base) != 0x00000000)
12695                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12696                 }
12697         }
12698
12699         udelay(50);
12700         tg3_nvram_init(tp);
12701
12702         grc_misc_cfg = tr32(GRC_MISC_CFG);
12703         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12704
12705         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12706             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12707              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12708                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12709
12710         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12711             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12712                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12713         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12714                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12715                                       HOSTCC_MODE_CLRTICK_TXBD);
12716
12717                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12718                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12719                                        tp->misc_host_ctrl);
12720         }
12721
12722         /* Preserve the APE MAC_MODE bits */
12723         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12724                 tp->mac_mode = tr32(MAC_MODE) |
12725                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12726         else
12727                 tp->mac_mode = TG3_DEF_MAC_MODE;
12728
12729         /* these are limited to 10/100 only */
12730         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12731              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12732             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12733              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12734              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12735               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12736               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12737             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12738              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12739               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12740               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12741             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12742             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12743                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12744
12745         err = tg3_phy_probe(tp);
12746         if (err) {
12747                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12748                        pci_name(tp->pdev), err);
12749                 /* ... but do not return immediately ... */
12750                 tg3_mdio_fini(tp);
12751         }
12752
12753         tg3_read_partno(tp);
12754         tg3_read_fw_ver(tp);
12755
12756         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12757                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12758         } else {
12759                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12760                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12761                 else
12762                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12763         }
12764
12765         /* 5700 {AX,BX} chips have a broken status block link
12766          * change bit implementation, so we must use the
12767          * status register in those cases.
12768          */
12769         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12770                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12771         else
12772                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12773
12774         /* The led_ctrl is set during tg3_phy_probe, here we might
12775          * have to force the link status polling mechanism based
12776          * upon subsystem IDs.
12777          */
12778         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12779             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12780             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12781                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12782                                   TG3_FLAG_USE_LINKCHG_REG);
12783         }
12784
12785         /* For all SERDES we poll the MAC status register. */
12786         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12787                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12788         else
12789                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12790
12791         tp->rx_offset = NET_IP_ALIGN;
12792         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12793             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12794                 tp->rx_offset = 0;
12795
12796         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12797
12798         /* Increment the rx prod index on the rx std ring by at most
12799          * 8 for these chips to workaround hw errata.
12800          */
12801         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12802             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12803             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12804                 tp->rx_std_max_post = 8;
12805
12806         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12807                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12808                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12809
12810         return err;
12811 }
12812
12813 #ifdef CONFIG_SPARC
12814 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12815 {
12816         struct net_device *dev = tp->dev;
12817         struct pci_dev *pdev = tp->pdev;
12818         struct device_node *dp = pci_device_to_OF_node(pdev);
12819         const unsigned char *addr;
12820         int len;
12821
12822         addr = of_get_property(dp, "local-mac-address", &len);
12823         if (addr && len == 6) {
12824                 memcpy(dev->dev_addr, addr, 6);
12825                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12826                 return 0;
12827         }
12828         return -ENODEV;
12829 }
12830
12831 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12832 {
12833         struct net_device *dev = tp->dev;
12834
12835         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12836         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12837         return 0;
12838 }
12839 #endif
12840
12841 static int __devinit tg3_get_device_address(struct tg3 *tp)
12842 {
12843         struct net_device *dev = tp->dev;
12844         u32 hi, lo, mac_offset;
12845         int addr_ok = 0;
12846
12847 #ifdef CONFIG_SPARC
12848         if (!tg3_get_macaddr_sparc(tp))
12849                 return 0;
12850 #endif
12851
12852         mac_offset = 0x7c;
12853         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12854             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12855                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12856                         mac_offset = 0xcc;
12857                 if (tg3_nvram_lock(tp))
12858                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12859                 else
12860                         tg3_nvram_unlock(tp);
12861         }
12862         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12863                 mac_offset = 0x10;
12864
12865         /* First try to get it from MAC address mailbox. */
12866         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12867         if ((hi >> 16) == 0x484b) {
12868                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12869                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12870
12871                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12872                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12873                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12874                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12875                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12876
12877                 /* Some old bootcode may report a 0 MAC address in SRAM */
12878                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12879         }
12880         if (!addr_ok) {
12881                 /* Next, try NVRAM. */
12882                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12883                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12884                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12885                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12886                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12887                 }
12888                 /* Finally just fetch it out of the MAC control regs. */
12889                 else {
12890                         hi = tr32(MAC_ADDR_0_HIGH);
12891                         lo = tr32(MAC_ADDR_0_LOW);
12892
12893                         dev->dev_addr[5] = lo & 0xff;
12894                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12895                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12896                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12897                         dev->dev_addr[1] = hi & 0xff;
12898                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12899                 }
12900         }
12901
12902         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12903 #ifdef CONFIG_SPARC
12904                 if (!tg3_get_default_macaddr_sparc(tp))
12905                         return 0;
12906 #endif
12907                 return -EINVAL;
12908         }
12909         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12910         return 0;
12911 }
12912
12913 #define BOUNDARY_SINGLE_CACHELINE       1
12914 #define BOUNDARY_MULTI_CACHELINE        2
12915
12916 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12917 {
12918         int cacheline_size;
12919         u8 byte;
12920         int goal;
12921
12922         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12923         if (byte == 0)
12924                 cacheline_size = 1024;
12925         else
12926                 cacheline_size = (int) byte * 4;
12927
12928         /* On 5703 and later chips, the boundary bits have no
12929          * effect.
12930          */
12931         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12932             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12933             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12934                 goto out;
12935
12936 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12937         goal = BOUNDARY_MULTI_CACHELINE;
12938 #else
12939 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12940         goal = BOUNDARY_SINGLE_CACHELINE;
12941 #else
12942         goal = 0;
12943 #endif
12944 #endif
12945
12946         if (!goal)
12947                 goto out;
12948
12949         /* PCI controllers on most RISC systems tend to disconnect
12950          * when a device tries to burst across a cache-line boundary.
12951          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12952          *
12953          * Unfortunately, for PCI-E there are only limited
12954          * write-side controls for this, and thus for reads
12955          * we will still get the disconnects.  We'll also waste
12956          * these PCI cycles for both read and write for chips
12957          * other than 5700 and 5701 which do not implement the
12958          * boundary bits.
12959          */
12960         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12961             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12962                 switch (cacheline_size) {
12963                 case 16:
12964                 case 32:
12965                 case 64:
12966                 case 128:
12967                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12968                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12969                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12970                         } else {
12971                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12972                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12973                         }
12974                         break;
12975
12976                 case 256:
12977                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12978                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12979                         break;
12980
12981                 default:
12982                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12983                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12984                         break;
12985                 }
12986         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12987                 switch (cacheline_size) {
12988                 case 16:
12989                 case 32:
12990                 case 64:
12991                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12992                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12993                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12994                                 break;
12995                         }
12996                         /* fallthrough */
12997                 case 128:
12998                 default:
12999                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13000                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13001                         break;
13002                 }
13003         } else {
13004                 switch (cacheline_size) {
13005                 case 16:
13006                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13007                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13008                                         DMA_RWCTRL_WRITE_BNDRY_16);
13009                                 break;
13010                         }
13011                         /* fallthrough */
13012                 case 32:
13013                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13014                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13015                                         DMA_RWCTRL_WRITE_BNDRY_32);
13016                                 break;
13017                         }
13018                         /* fallthrough */
13019                 case 64:
13020                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13021                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13022                                         DMA_RWCTRL_WRITE_BNDRY_64);
13023                                 break;
13024                         }
13025                         /* fallthrough */
13026                 case 128:
13027                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13028                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13029                                         DMA_RWCTRL_WRITE_BNDRY_128);
13030                                 break;
13031                         }
13032                         /* fallthrough */
13033                 case 256:
13034                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13035                                 DMA_RWCTRL_WRITE_BNDRY_256);
13036                         break;
13037                 case 512:
13038                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13039                                 DMA_RWCTRL_WRITE_BNDRY_512);
13040                         break;
13041                 case 1024:
13042                 default:
13043                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13044                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13045                         break;
13046                 }
13047         }
13048
13049 out:
13050         return val;
13051 }
13052
13053 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13054 {
13055         struct tg3_internal_buffer_desc test_desc;
13056         u32 sram_dma_descs;
13057         int i, ret;
13058
13059         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13060
13061         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13062         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13063         tw32(RDMAC_STATUS, 0);
13064         tw32(WDMAC_STATUS, 0);
13065
13066         tw32(BUFMGR_MODE, 0);
13067         tw32(FTQ_RESET, 0);
13068
13069         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13070         test_desc.addr_lo = buf_dma & 0xffffffff;
13071         test_desc.nic_mbuf = 0x00002100;
13072         test_desc.len = size;
13073
13074         /*
13075          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13076          * the *second* time the tg3 driver was getting loaded after an
13077          * initial scan.
13078          *
13079          * Broadcom tells me:
13080          *   ...the DMA engine is connected to the GRC block and a DMA
13081          *   reset may affect the GRC block in some unpredictable way...
13082          *   The behavior of resets to individual blocks has not been tested.
13083          *
13084          * Broadcom noted the GRC reset will also reset all sub-components.
13085          */
13086         if (to_device) {
13087                 test_desc.cqid_sqid = (13 << 8) | 2;
13088
13089                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13090                 udelay(40);
13091         } else {
13092                 test_desc.cqid_sqid = (16 << 8) | 7;
13093
13094                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13095                 udelay(40);
13096         }
13097         test_desc.flags = 0x00000005;
13098
13099         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13100                 u32 val;
13101
13102                 val = *(((u32 *)&test_desc) + i);
13103                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13104                                        sram_dma_descs + (i * sizeof(u32)));
13105                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13106         }
13107         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13108
13109         if (to_device) {
13110                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13111         } else {
13112                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13113         }
13114
13115         ret = -ENODEV;
13116         for (i = 0; i < 40; i++) {
13117                 u32 val;
13118
13119                 if (to_device)
13120                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13121                 else
13122                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13123                 if ((val & 0xffff) == sram_dma_descs) {
13124                         ret = 0;
13125                         break;
13126                 }
13127
13128                 udelay(100);
13129         }
13130
13131         return ret;
13132 }
13133
13134 #define TEST_BUFFER_SIZE        0x2000
13135
13136 static int __devinit tg3_test_dma(struct tg3 *tp)
13137 {
13138         dma_addr_t buf_dma;
13139         u32 *buf, saved_dma_rwctrl;
13140         int ret;
13141
13142         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13143         if (!buf) {
13144                 ret = -ENOMEM;
13145                 goto out_nofree;
13146         }
13147
13148         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13149                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13150
13151         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13152
13153         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13154                 /* DMA read watermark not used on PCIE */
13155                 tp->dma_rwctrl |= 0x00180000;
13156         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13157                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13158                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13159                         tp->dma_rwctrl |= 0x003f0000;
13160                 else
13161                         tp->dma_rwctrl |= 0x003f000f;
13162         } else {
13163                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13164                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13165                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13166                         u32 read_water = 0x7;
13167
13168                         /* If the 5704 is behind the EPB bridge, we can
13169                          * do the less restrictive ONE_DMA workaround for
13170                          * better performance.
13171                          */
13172                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13173                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13174                                 tp->dma_rwctrl |= 0x8000;
13175                         else if (ccval == 0x6 || ccval == 0x7)
13176                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13177
13178                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13179                                 read_water = 4;
13180                         /* Set bit 23 to enable PCIX hw bug fix */
13181                         tp->dma_rwctrl |=
13182                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13183                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13184                                 (1 << 23);
13185                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13186                         /* 5780 always in PCIX mode */
13187                         tp->dma_rwctrl |= 0x00144000;
13188                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13189                         /* 5714 always in PCIX mode */
13190                         tp->dma_rwctrl |= 0x00148000;
13191                 } else {
13192                         tp->dma_rwctrl |= 0x001b000f;
13193                 }
13194         }
13195
13196         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13197             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13198                 tp->dma_rwctrl &= 0xfffffff0;
13199
13200         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13201             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13202                 /* Remove this if it causes problems for some boards. */
13203                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13204
13205                 /* On 5700/5701 chips, we need to set this bit.
13206                  * Otherwise the chip will issue cacheline transactions
13207                  * to streamable DMA memory with not all the byte
13208                  * enables turned on.  This is an error on several
13209                  * RISC PCI controllers, in particular sparc64.
13210                  *
13211                  * On 5703/5704 chips, this bit has been reassigned
13212                  * a different meaning.  In particular, it is used
13213                  * on those chips to enable a PCI-X workaround.
13214                  */
13215                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13216         }
13217
13218         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13219
13220 #if 0
13221         /* Unneeded, already done by tg3_get_invariants.  */
13222         tg3_switch_clocks(tp);
13223 #endif
13224
13225         ret = 0;
13226         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13227             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13228                 goto out;
13229
13230         /* It is best to perform DMA test with maximum write burst size
13231          * to expose the 5700/5701 write DMA bug.
13232          */
13233         saved_dma_rwctrl = tp->dma_rwctrl;
13234         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13235         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13236
13237         while (1) {
13238                 u32 *p = buf, i;
13239
13240                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13241                         p[i] = i;
13242
13243                 /* Send the buffer to the chip. */
13244                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13245                 if (ret) {
13246                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13247                         break;
13248                 }
13249
13250 #if 0
13251                 /* validate data reached card RAM correctly. */
13252                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13253                         u32 val;
13254                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13255                         if (le32_to_cpu(val) != p[i]) {
13256                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13257                                 /* ret = -ENODEV here? */
13258                         }
13259                         p[i] = 0;
13260                 }
13261 #endif
13262                 /* Now read it back. */
13263                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13264                 if (ret) {
13265                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13266
13267                         break;
13268                 }
13269
13270                 /* Verify it. */
13271                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13272                         if (p[i] == i)
13273                                 continue;
13274
13275                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13276                             DMA_RWCTRL_WRITE_BNDRY_16) {
13277                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13278                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13279                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13280                                 break;
13281                         } else {
13282                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13283                                 ret = -ENODEV;
13284                                 goto out;
13285                         }
13286                 }
13287
13288                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13289                         /* Success. */
13290                         ret = 0;
13291                         break;
13292                 }
13293         }
13294         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13295             DMA_RWCTRL_WRITE_BNDRY_16) {
13296                 static struct pci_device_id dma_wait_state_chipsets[] = {
13297                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13298                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13299                         { },
13300                 };
13301
13302                 /* DMA test passed without adjusting DMA boundary,
13303                  * now look for chipsets that are known to expose the
13304                  * DMA bug without failing the test.
13305                  */
13306                 if (pci_dev_present(dma_wait_state_chipsets)) {
13307                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13308                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13309                 }
13310                 else
13311                         /* Safe to use the calculated DMA boundary. */
13312                         tp->dma_rwctrl = saved_dma_rwctrl;
13313
13314                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13315         }
13316
13317 out:
13318         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13319 out_nofree:
13320         return ret;
13321 }
13322
13323 static void __devinit tg3_init_link_config(struct tg3 *tp)
13324 {
13325         tp->link_config.advertising =
13326                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13327                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13328                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13329                  ADVERTISED_Autoneg | ADVERTISED_MII);
13330         tp->link_config.speed = SPEED_INVALID;
13331         tp->link_config.duplex = DUPLEX_INVALID;
13332         tp->link_config.autoneg = AUTONEG_ENABLE;
13333         tp->link_config.active_speed = SPEED_INVALID;
13334         tp->link_config.active_duplex = DUPLEX_INVALID;
13335         tp->link_config.phy_is_low_power = 0;
13336         tp->link_config.orig_speed = SPEED_INVALID;
13337         tp->link_config.orig_duplex = DUPLEX_INVALID;
13338         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13339 }
13340
13341 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13342 {
13343         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13344                 tp->bufmgr_config.mbuf_read_dma_low_water =
13345                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13346                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13347                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13348                 tp->bufmgr_config.mbuf_high_water =
13349                         DEFAULT_MB_HIGH_WATER_5705;
13350                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13351                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13352                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13353                         tp->bufmgr_config.mbuf_high_water =
13354                                 DEFAULT_MB_HIGH_WATER_5906;
13355                 }
13356
13357                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13358                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13359                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13360                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13361                 tp->bufmgr_config.mbuf_high_water_jumbo =
13362                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13363         } else {
13364                 tp->bufmgr_config.mbuf_read_dma_low_water =
13365                         DEFAULT_MB_RDMA_LOW_WATER;
13366                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13367                         DEFAULT_MB_MACRX_LOW_WATER;
13368                 tp->bufmgr_config.mbuf_high_water =
13369                         DEFAULT_MB_HIGH_WATER;
13370
13371                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13372                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13373                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13374                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13375                 tp->bufmgr_config.mbuf_high_water_jumbo =
13376                         DEFAULT_MB_HIGH_WATER_JUMBO;
13377         }
13378
13379         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13380         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13381 }
13382
13383 static char * __devinit tg3_phy_string(struct tg3 *tp)
13384 {
13385         switch (tp->phy_id & PHY_ID_MASK) {
13386         case PHY_ID_BCM5400:    return "5400";
13387         case PHY_ID_BCM5401:    return "5401";
13388         case PHY_ID_BCM5411:    return "5411";
13389         case PHY_ID_BCM5701:    return "5701";
13390         case PHY_ID_BCM5703:    return "5703";
13391         case PHY_ID_BCM5704:    return "5704";
13392         case PHY_ID_BCM5705:    return "5705";
13393         case PHY_ID_BCM5750:    return "5750";
13394         case PHY_ID_BCM5752:    return "5752";
13395         case PHY_ID_BCM5714:    return "5714";
13396         case PHY_ID_BCM5780:    return "5780";
13397         case PHY_ID_BCM5755:    return "5755";
13398         case PHY_ID_BCM5787:    return "5787";
13399         case PHY_ID_BCM5784:    return "5784";
13400         case PHY_ID_BCM5756:    return "5722/5756";
13401         case PHY_ID_BCM5906:    return "5906";
13402         case PHY_ID_BCM5761:    return "5761";
13403         case PHY_ID_BCM8002:    return "8002/serdes";
13404         case 0:                 return "serdes";
13405         default:                return "unknown";
13406         }
13407 }
13408
13409 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13410 {
13411         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13412                 strcpy(str, "PCI Express");
13413                 return str;
13414         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13415                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13416
13417                 strcpy(str, "PCIX:");
13418
13419                 if ((clock_ctrl == 7) ||
13420                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13421                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13422                         strcat(str, "133MHz");
13423                 else if (clock_ctrl == 0)
13424                         strcat(str, "33MHz");
13425                 else if (clock_ctrl == 2)
13426                         strcat(str, "50MHz");
13427                 else if (clock_ctrl == 4)
13428                         strcat(str, "66MHz");
13429                 else if (clock_ctrl == 6)
13430                         strcat(str, "100MHz");
13431         } else {
13432                 strcpy(str, "PCI:");
13433                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13434                         strcat(str, "66MHz");
13435                 else
13436                         strcat(str, "33MHz");
13437         }
13438         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13439                 strcat(str, ":32-bit");
13440         else
13441                 strcat(str, ":64-bit");
13442         return str;
13443 }
13444
13445 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13446 {
13447         struct pci_dev *peer;
13448         unsigned int func, devnr = tp->pdev->devfn & ~7;
13449
13450         for (func = 0; func < 8; func++) {
13451                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13452                 if (peer && peer != tp->pdev)
13453                         break;
13454                 pci_dev_put(peer);
13455         }
13456         /* 5704 can be configured in single-port mode, set peer to
13457          * tp->pdev in that case.
13458          */
13459         if (!peer) {
13460                 peer = tp->pdev;
13461                 return peer;
13462         }
13463
13464         /*
13465          * We don't need to keep the refcount elevated; there's no way
13466          * to remove one half of this device without removing the other
13467          */
13468         pci_dev_put(peer);
13469
13470         return peer;
13471 }
13472
13473 static void __devinit tg3_init_coal(struct tg3 *tp)
13474 {
13475         struct ethtool_coalesce *ec = &tp->coal;
13476
13477         memset(ec, 0, sizeof(*ec));
13478         ec->cmd = ETHTOOL_GCOALESCE;
13479         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13480         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13481         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13482         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13483         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13484         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13485         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13486         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13487         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13488
13489         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13490                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13491                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13492                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13493                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13494                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13495         }
13496
13497         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13498                 ec->rx_coalesce_usecs_irq = 0;
13499                 ec->tx_coalesce_usecs_irq = 0;
13500                 ec->stats_block_coalesce_usecs = 0;
13501         }
13502 }
13503
13504 static const struct net_device_ops tg3_netdev_ops = {
13505         .ndo_open               = tg3_open,
13506         .ndo_stop               = tg3_close,
13507         .ndo_start_xmit         = tg3_start_xmit,
13508         .ndo_get_stats          = tg3_get_stats,
13509         .ndo_validate_addr      = eth_validate_addr,
13510         .ndo_set_multicast_list = tg3_set_rx_mode,
13511         .ndo_set_mac_address    = tg3_set_mac_addr,
13512         .ndo_do_ioctl           = tg3_ioctl,
13513         .ndo_tx_timeout         = tg3_tx_timeout,
13514         .ndo_change_mtu         = tg3_change_mtu,
13515 #if TG3_VLAN_TAG_USED
13516         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13517 #endif
13518 #ifdef CONFIG_NET_POLL_CONTROLLER
13519         .ndo_poll_controller    = tg3_poll_controller,
13520 #endif
13521 };
13522
13523 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13524         .ndo_open               = tg3_open,
13525         .ndo_stop               = tg3_close,
13526         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13527         .ndo_get_stats          = tg3_get_stats,
13528         .ndo_validate_addr      = eth_validate_addr,
13529         .ndo_set_multicast_list = tg3_set_rx_mode,
13530         .ndo_set_mac_address    = tg3_set_mac_addr,
13531         .ndo_do_ioctl           = tg3_ioctl,
13532         .ndo_tx_timeout         = tg3_tx_timeout,
13533         .ndo_change_mtu         = tg3_change_mtu,
13534 #if TG3_VLAN_TAG_USED
13535         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13536 #endif
13537 #ifdef CONFIG_NET_POLL_CONTROLLER
13538         .ndo_poll_controller    = tg3_poll_controller,
13539 #endif
13540 };
13541
13542 static int __devinit tg3_init_one(struct pci_dev *pdev,
13543                                   const struct pci_device_id *ent)
13544 {
13545         static int tg3_version_printed = 0;
13546         struct net_device *dev;
13547         struct tg3 *tp;
13548         int i, err, pm_cap;
13549         u32 sndmbx, rcvmbx, intmbx;
13550         char str[40];
13551         u64 dma_mask, persist_dma_mask;
13552
13553         if (tg3_version_printed++ == 0)
13554                 printk(KERN_INFO "%s", version);
13555
13556         err = pci_enable_device(pdev);
13557         if (err) {
13558                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13559                        "aborting.\n");
13560                 return err;
13561         }
13562
13563         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13564         if (err) {
13565                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13566                        "aborting.\n");
13567                 goto err_out_disable_pdev;
13568         }
13569
13570         pci_set_master(pdev);
13571
13572         /* Find power-management capability. */
13573         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13574         if (pm_cap == 0) {
13575                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13576                        "aborting.\n");
13577                 err = -EIO;
13578                 goto err_out_free_res;
13579         }
13580
13581         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13582         if (!dev) {
13583                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13584                 err = -ENOMEM;
13585                 goto err_out_free_res;
13586         }
13587
13588         SET_NETDEV_DEV(dev, &pdev->dev);
13589
13590 #if TG3_VLAN_TAG_USED
13591         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13592 #endif
13593
13594         tp = netdev_priv(dev);
13595         tp->pdev = pdev;
13596         tp->dev = dev;
13597         tp->pm_cap = pm_cap;
13598         tp->rx_mode = TG3_DEF_RX_MODE;
13599         tp->tx_mode = TG3_DEF_TX_MODE;
13600
13601         if (tg3_debug > 0)
13602                 tp->msg_enable = tg3_debug;
13603         else
13604                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13605
13606         /* The word/byte swap controls here control register access byte
13607          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13608          * setting below.
13609          */
13610         tp->misc_host_ctrl =
13611                 MISC_HOST_CTRL_MASK_PCI_INT |
13612                 MISC_HOST_CTRL_WORD_SWAP |
13613                 MISC_HOST_CTRL_INDIR_ACCESS |
13614                 MISC_HOST_CTRL_PCISTATE_RW;
13615
13616         /* The NONFRM (non-frame) byte/word swap controls take effect
13617          * on descriptor entries, anything which isn't packet data.
13618          *
13619          * The StrongARM chips on the board (one for tx, one for rx)
13620          * are running in big-endian mode.
13621          */
13622         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13623                         GRC_MODE_WSWAP_NONFRM_DATA);
13624 #ifdef __BIG_ENDIAN
13625         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13626 #endif
13627         spin_lock_init(&tp->lock);
13628         spin_lock_init(&tp->indirect_lock);
13629         INIT_WORK(&tp->reset_task, tg3_reset_task);
13630
13631         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13632         if (!tp->regs) {
13633                 printk(KERN_ERR PFX "Cannot map device registers, "
13634                        "aborting.\n");
13635                 err = -ENOMEM;
13636                 goto err_out_free_dev;
13637         }
13638
13639         tg3_init_link_config(tp);
13640
13641         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13642         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13643
13644         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13645         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13646         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13647         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13648                 struct tg3_napi *tnapi = &tp->napi[i];
13649
13650                 tnapi->tp = tp;
13651                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13652
13653                 tnapi->int_mbox = intmbx;
13654                 if (i < 4)
13655                         intmbx += 0x8;
13656                 else
13657                         intmbx += 0x4;
13658
13659                 tnapi->consmbox = rcvmbx;
13660                 tnapi->prodmbox = sndmbx;
13661
13662                 if (i)
13663                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13664                 else
13665                         tnapi->coal_now = HOSTCC_MODE_NOW;
13666
13667                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13668                         break;
13669
13670                 /*
13671                  * If we support MSIX, we'll be using RSS.  If we're using
13672                  * RSS, the first vector only handles link interrupts and the
13673                  * remaining vectors handle rx and tx interrupts.  Reuse the
13674                  * mailbox values for the next iteration.  The values we setup
13675                  * above are still useful for the single vectored mode.
13676                  */
13677                 if (!i)
13678                         continue;
13679
13680                 rcvmbx += 0x8;
13681
13682                 if (sndmbx & 0x4)
13683                         sndmbx -= 0x4;
13684                 else
13685                         sndmbx += 0xc;
13686         }
13687
13688         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13689         dev->ethtool_ops = &tg3_ethtool_ops;
13690         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13691         dev->irq = pdev->irq;
13692
13693         err = tg3_get_invariants(tp);
13694         if (err) {
13695                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13696                        "aborting.\n");
13697                 goto err_out_iounmap;
13698         }
13699
13700         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13701             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13702                 dev->netdev_ops = &tg3_netdev_ops;
13703         else
13704                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13705
13706
13707         /* The EPB bridge inside 5714, 5715, and 5780 and any
13708          * device behind the EPB cannot support DMA addresses > 40-bit.
13709          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13710          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13711          * do DMA address check in tg3_start_xmit().
13712          */
13713         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13714                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13715         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13716                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13717 #ifdef CONFIG_HIGHMEM
13718                 dma_mask = DMA_BIT_MASK(64);
13719 #endif
13720         } else
13721                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13722
13723         /* Configure DMA attributes. */
13724         if (dma_mask > DMA_BIT_MASK(32)) {
13725                 err = pci_set_dma_mask(pdev, dma_mask);
13726                 if (!err) {
13727                         dev->features |= NETIF_F_HIGHDMA;
13728                         err = pci_set_consistent_dma_mask(pdev,
13729                                                           persist_dma_mask);
13730                         if (err < 0) {
13731                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13732                                        "DMA for consistent allocations\n");
13733                                 goto err_out_iounmap;
13734                         }
13735                 }
13736         }
13737         if (err || dma_mask == DMA_BIT_MASK(32)) {
13738                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13739                 if (err) {
13740                         printk(KERN_ERR PFX "No usable DMA configuration, "
13741                                "aborting.\n");
13742                         goto err_out_iounmap;
13743                 }
13744         }
13745
13746         tg3_init_bufmgr_config(tp);
13747
13748         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13749                 tp->fw_needed = FIRMWARE_TG3;
13750
13751         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13752                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13753         }
13754         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13755             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13756             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13757             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13758             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13759                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13760         } else {
13761                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13762                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13763                         tp->fw_needed = FIRMWARE_TG3TSO5;
13764                 else
13765                         tp->fw_needed = FIRMWARE_TG3TSO;
13766         }
13767
13768         /* TSO is on by default on chips that support hardware TSO.
13769          * Firmware TSO on older chips gives lower performance, so it
13770          * is off by default, but can be enabled using ethtool.
13771          */
13772         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13773                 if (dev->features & NETIF_F_IP_CSUM)
13774                         dev->features |= NETIF_F_TSO;
13775                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13776                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13777                         dev->features |= NETIF_F_TSO6;
13778                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13779                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13780                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13781                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13782                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13783                         dev->features |= NETIF_F_TSO_ECN;
13784         }
13785
13786
13787         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13788             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13789             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13790                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13791                 tp->rx_pending = 63;
13792         }
13793
13794         err = tg3_get_device_address(tp);
13795         if (err) {
13796                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13797                        "aborting.\n");
13798                 goto err_out_fw;
13799         }
13800
13801         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13802                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13803                 if (!tp->aperegs) {
13804                         printk(KERN_ERR PFX "Cannot map APE registers, "
13805                                "aborting.\n");
13806                         err = -ENOMEM;
13807                         goto err_out_fw;
13808                 }
13809
13810                 tg3_ape_lock_init(tp);
13811
13812                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13813                         tg3_read_dash_ver(tp);
13814         }
13815
13816         /*
13817          * Reset chip in case UNDI or EFI driver did not shutdown
13818          * DMA self test will enable WDMAC and we'll see (spurious)
13819          * pending DMA on the PCI bus at that point.
13820          */
13821         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13822             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13823                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13824                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13825         }
13826
13827         err = tg3_test_dma(tp);
13828         if (err) {
13829                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13830                 goto err_out_apeunmap;
13831         }
13832
13833         /* flow control autonegotiation is default behavior */
13834         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13835         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13836
13837         tg3_init_coal(tp);
13838
13839         pci_set_drvdata(pdev, dev);
13840
13841         err = register_netdev(dev);
13842         if (err) {
13843                 printk(KERN_ERR PFX "Cannot register net device, "
13844                        "aborting.\n");
13845                 goto err_out_apeunmap;
13846         }
13847
13848         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13849                dev->name,
13850                tp->board_part_number,
13851                tp->pci_chip_rev_id,
13852                tg3_bus_string(tp, str),
13853                dev->dev_addr);
13854
13855         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13856                 printk(KERN_INFO
13857                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13858                        tp->dev->name,
13859                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13860                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13861         else
13862                 printk(KERN_INFO
13863                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13864                        tp->dev->name, tg3_phy_string(tp),
13865                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13866                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13867                          "10/100/1000Base-T")),
13868                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13869
13870         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13871                dev->name,
13872                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13873                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13874                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13875                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13876                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13877         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13878                dev->name, tp->dma_rwctrl,
13879                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13880                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13881
13882         return 0;
13883
13884 err_out_apeunmap:
13885         if (tp->aperegs) {
13886                 iounmap(tp->aperegs);
13887                 tp->aperegs = NULL;
13888         }
13889
13890 err_out_fw:
13891         if (tp->fw)
13892                 release_firmware(tp->fw);
13893
13894 err_out_iounmap:
13895         if (tp->regs) {
13896                 iounmap(tp->regs);
13897                 tp->regs = NULL;
13898         }
13899
13900 err_out_free_dev:
13901         free_netdev(dev);
13902
13903 err_out_free_res:
13904         pci_release_regions(pdev);
13905
13906 err_out_disable_pdev:
13907         pci_disable_device(pdev);
13908         pci_set_drvdata(pdev, NULL);
13909         return err;
13910 }
13911
13912 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13913 {
13914         struct net_device *dev = pci_get_drvdata(pdev);
13915
13916         if (dev) {
13917                 struct tg3 *tp = netdev_priv(dev);
13918
13919                 if (tp->fw)
13920                         release_firmware(tp->fw);
13921
13922                 flush_scheduled_work();
13923
13924                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13925                         tg3_phy_fini(tp);
13926                         tg3_mdio_fini(tp);
13927                 }
13928
13929                 unregister_netdev(dev);
13930                 if (tp->aperegs) {
13931                         iounmap(tp->aperegs);
13932                         tp->aperegs = NULL;
13933                 }
13934                 if (tp->regs) {
13935                         iounmap(tp->regs);
13936                         tp->regs = NULL;
13937                 }
13938                 free_netdev(dev);
13939                 pci_release_regions(pdev);
13940                 pci_disable_device(pdev);
13941                 pci_set_drvdata(pdev, NULL);
13942         }
13943 }
13944
13945 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13946 {
13947         struct net_device *dev = pci_get_drvdata(pdev);
13948         struct tg3 *tp = netdev_priv(dev);
13949         pci_power_t target_state;
13950         int err;
13951
13952         /* PCI register 4 needs to be saved whether netif_running() or not.
13953          * MSI address and data need to be saved if using MSI and
13954          * netif_running().
13955          */
13956         pci_save_state(pdev);
13957
13958         if (!netif_running(dev))
13959                 return 0;
13960
13961         flush_scheduled_work();
13962         tg3_phy_stop(tp);
13963         tg3_netif_stop(tp);
13964
13965         del_timer_sync(&tp->timer);
13966
13967         tg3_full_lock(tp, 1);
13968         tg3_disable_ints(tp);
13969         tg3_full_unlock(tp);
13970
13971         netif_device_detach(dev);
13972
13973         tg3_full_lock(tp, 0);
13974         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13975         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13976         tg3_full_unlock(tp);
13977
13978         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13979
13980         err = tg3_set_power_state(tp, target_state);
13981         if (err) {
13982                 int err2;
13983
13984                 tg3_full_lock(tp, 0);
13985
13986                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13987                 err2 = tg3_restart_hw(tp, 1);
13988                 if (err2)
13989                         goto out;
13990
13991                 tp->timer.expires = jiffies + tp->timer_offset;
13992                 add_timer(&tp->timer);
13993
13994                 netif_device_attach(dev);
13995                 tg3_netif_start(tp);
13996
13997 out:
13998                 tg3_full_unlock(tp);
13999
14000                 if (!err2)
14001                         tg3_phy_start(tp);
14002         }
14003
14004         return err;
14005 }
14006
14007 static int tg3_resume(struct pci_dev *pdev)
14008 {
14009         struct net_device *dev = pci_get_drvdata(pdev);
14010         struct tg3 *tp = netdev_priv(dev);
14011         int err;
14012
14013         pci_restore_state(tp->pdev);
14014
14015         if (!netif_running(dev))
14016                 return 0;
14017
14018         err = tg3_set_power_state(tp, PCI_D0);
14019         if (err)
14020                 return err;
14021
14022         netif_device_attach(dev);
14023
14024         tg3_full_lock(tp, 0);
14025
14026         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14027         err = tg3_restart_hw(tp, 1);
14028         if (err)
14029                 goto out;
14030
14031         tp->timer.expires = jiffies + tp->timer_offset;
14032         add_timer(&tp->timer);
14033
14034         tg3_netif_start(tp);
14035
14036 out:
14037         tg3_full_unlock(tp);
14038
14039         if (!err)
14040                 tg3_phy_start(tp);
14041
14042         return err;
14043 }
14044
14045 static struct pci_driver tg3_driver = {
14046         .name           = DRV_MODULE_NAME,
14047         .id_table       = tg3_pci_tbl,
14048         .probe          = tg3_init_one,
14049         .remove         = __devexit_p(tg3_remove_one),
14050         .suspend        = tg3_suspend,
14051         .resume         = tg3_resume
14052 };
14053
14054 static int __init tg3_init(void)
14055 {
14056         return pci_register_driver(&tg3_driver);
14057 }
14058
14059 static void __exit tg3_cleanup(void)
14060 {
14061         pci_unregister_driver(&tg3_driver);
14062 }
14063
14064 module_init(tg3_init);
14065 module_exit(tg3_cleanup);