drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #ifdef NETIF_F_TSO
  62 #define TG3_TSO_SUPPORT 1
  63 #else
  64 #define TG3_TSO_SUPPORT 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.70"
  72 #define DRV_MODULE_RELDATE      "December 1, 2006"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 /* number of ETHTOOL_GSTATS u64's */
 135 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 136
 137 #define TG3_NUM_TEST            6
 138
 139 static char version[] __devinitdata =
 140         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 141
 142 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 143 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 144 MODULE_LICENSE("GPL");
 145 MODULE_VERSION(DRV_MODULE_VERSION);
 146
 147 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 148 module_param(tg3_debug, int, 0);
 149 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 150
 151 static struct pci_device_id tg3_pci_tbl[] = {
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 212         {}
 213 };
 214
 215 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 216
 217 static const struct {
 218         const char string[ETH_GSTRING_LEN];
 219 } ethtool_stats_keys[TG3_NUM_STATS] = {
 220         { "rx_octets" },
 221         { "rx_fragments" },
 222         { "rx_ucast_packets" },
 223         { "rx_mcast_packets" },
 224         { "rx_bcast_packets" },
 225         { "rx_fcs_errors" },
 226         { "rx_align_errors" },
 227         { "rx_xon_pause_rcvd" },
 228         { "rx_xoff_pause_rcvd" },
 229         { "rx_mac_ctrl_rcvd" },
 230         { "rx_xoff_entered" },
 231         { "rx_frame_too_long_errors" },
 232         { "rx_jabbers" },
 233         { "rx_undersize_packets" },
 234         { "rx_in_length_errors" },
 235         { "rx_out_length_errors" },
 236         { "rx_64_or_less_octet_packets" },
 237         { "rx_65_to_127_octet_packets" },
 238         { "rx_128_to_255_octet_packets" },
 239         { "rx_256_to_511_octet_packets" },
 240         { "rx_512_to_1023_octet_packets" },
 241         { "rx_1024_to_1522_octet_packets" },
 242         { "rx_1523_to_2047_octet_packets" },
 243         { "rx_2048_to_4095_octet_packets" },
 244         { "rx_4096_to_8191_octet_packets" },
 245         { "rx_8192_to_9022_octet_packets" },
 246
 247         { "tx_octets" },
 248         { "tx_collisions" },
 249
 250         { "tx_xon_sent" },
 251         { "tx_xoff_sent" },
 252         { "tx_flow_control" },
 253         { "tx_mac_errors" },
 254         { "tx_single_collisions" },
 255         { "tx_mult_collisions" },
 256         { "tx_deferred" },
 257         { "tx_excessive_collisions" },
 258         { "tx_late_collisions" },
 259         { "tx_collide_2times" },
 260         { "tx_collide_3times" },
 261         { "tx_collide_4times" },
 262         { "tx_collide_5times" },
 263         { "tx_collide_6times" },
 264         { "tx_collide_7times" },
 265         { "tx_collide_8times" },
 266         { "tx_collide_9times" },
 267         { "tx_collide_10times" },
 268         { "tx_collide_11times" },
 269         { "tx_collide_12times" },
 270         { "tx_collide_13times" },
 271         { "tx_collide_14times" },
 272         { "tx_collide_15times" },
 273         { "tx_ucast_packets" },
 274         { "tx_mcast_packets" },
 275         { "tx_bcast_packets" },
 276         { "tx_carrier_sense_errors" },
 277         { "tx_discards" },
 278         { "tx_errors" },
 279
 280         { "dma_writeq_full" },
 281         { "dma_write_prioq_full" },
 282         { "rxbds_empty" },
 283         { "rx_discards" },
 284         { "rx_errors" },
 285         { "rx_threshold_hit" },
 286
 287         { "dma_readq_full" },
 288         { "dma_read_prioq_full" },
 289         { "tx_comp_queue_full" },
 290
 291         { "ring_set_send_prod_index" },
 292         { "ring_status_update" },
 293         { "nic_irqs" },
 294         { "nic_avoided_irqs" },
 295         { "nic_tx_threshold_hit" }
 296 };
 297
 298 static const struct {
 299         const char string[ETH_GSTRING_LEN];
 300 } ethtool_test_keys[TG3_NUM_TEST] = {
 301         { "nvram test     (online) " },
 302         { "link test      (online) " },
 303         { "register test  (offline)" },
 304         { "memory test    (offline)" },
 305         { "loopback test  (offline)" },
 306         { "interrupt test (offline)" },
 307 };
 308
 309 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 310 {
 311         writel(val, tp->regs + off);
 312 }
 313
 314 static u32 tg3_read32(struct tg3 *tp, u32 off)
 315 {
 316         return (readl(tp->regs + off));
 317 }
 318
 319 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 320 {
 321         unsigned long flags;
 322
 323         spin_lock_irqsave(&tp->indirect_lock, flags);
 324         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 325         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 326         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 327 }
 328
 329 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 330 {
 331         writel(val, tp->regs + off);
 332         readl(tp->regs + off);
 333 }
 334
 335 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 336 {
 337         unsigned long flags;
 338         u32 val;
 339
 340         spin_lock_irqsave(&tp->indirect_lock, flags);
 341         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 342         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 343         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 344         return val;
 345 }
 346
 347 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 348 {
 349         unsigned long flags;
 350
 351         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 352                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 353                                        TG3_64BIT_REG_LOW, val);
 354                 return;
 355         }
 356         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 357                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 358                                        TG3_64BIT_REG_LOW, val);
 359                 return;
 360         }
 361
 362         spin_lock_irqsave(&tp->indirect_lock, flags);
 363         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 364         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 365         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 366
 367         /* In indirect mode when disabling interrupts, we also need
 368          * to clear the interrupt bit in the GRC local ctrl register.
 369          */
 370         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 371             (val == 0x1)) {
 372                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 373                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 374         }
 375 }
 376
 377 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 378 {
 379         unsigned long flags;
 380         u32 val;
 381
 382         spin_lock_irqsave(&tp->indirect_lock, flags);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 384         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 385         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 386         return val;
 387 }
 388
 389 /* usec_wait specifies the wait time in usec when writing to certain registers
 390  * where it is unsafe to read back the register without some delay.
 391  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 392  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 393  */
 394 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 395 {
 396         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 397             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 398                 /* Non-posted methods */
 399                 tp->write32(tp, off, val);
 400         else {
 401                 /* Posted method */
 402                 tg3_write32(tp, off, val);
 403                 if (usec_wait)
 404                         udelay(usec_wait);
 405                 tp->read32(tp, off);
 406         }
 407         /* Wait again after the read for the posted method to guarantee that
 408          * the wait time is met.
 409          */
 410         if (usec_wait)
 411                 udelay(usec_wait);
 412 }
 413
 414 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 415 {
 416         tp->write32_mbox(tp, off, val);
 417         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 418             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 419                 tp->read32_mbox(tp, off);
 420 }
 421
 422 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 423 {
 424         void __iomem *mbox = tp->regs + off;
 425         writel(val, mbox);
 426         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 427                 writel(val, mbox);
 428         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 429                 readl(mbox);
 430 }
 431
 432 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 433 {
 434         return (readl(tp->regs + off + GRCMBOX_BASE));
 435 }
 436
 437 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 438 {
 439         writel(val, tp->regs + off + GRCMBOX_BASE);
 440 }
 441
 442 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 443 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 444 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 445 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 446 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 447
 448 #define tw32(reg,val)           tp->write32(tp, reg, val)
 449 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 450 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 451 #define tr32(reg)               tp->read32(tp, reg)
 452
 453 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 454 {
 455         unsigned long flags;
 456
 457         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 458             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 459                 return;
 460
 461         spin_lock_irqsave(&tp->indirect_lock, flags);
 462         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 464                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 465
 466                 /* Always leave this as zero. */
 467                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 468         } else {
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 470                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 471
 472                 /* Always leave this as zero. */
 473                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 474         }
 475         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 476 }
 477
 478 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 479 {
 480         unsigned long flags;
 481
 482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 483             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 484                 *val = 0;
 485                 return;
 486         }
 487
 488         spin_lock_irqsave(&tp->indirect_lock, flags);
 489         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 491                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 492
 493                 /* Always leave this as zero. */
 494                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 495         } else {
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 497                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 498
 499                 /* Always leave this as zero. */
 500                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 501         }
 502         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 503 }
 504
 505 static void tg3_disable_ints(struct tg3 *tp)
 506 {
 507         tw32(TG3PCI_MISC_HOST_CTRL,
 508              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 509         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 510 }
 511
 512 static inline void tg3_cond_int(struct tg3 *tp)
 513 {
 514         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 515             (tp->hw_status->status & SD_STATUS_UPDATED))
 516                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 517         else
 518                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 519                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 520 }
 521
 522 static void tg3_enable_ints(struct tg3 *tp)
 523 {
 524         tp->irq_sync = 0;
 525         wmb();
 526
 527         tw32(TG3PCI_MISC_HOST_CTRL,
 528              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 529         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 530                        (tp->last_tag << 24));
 531         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 532                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 533                                (tp->last_tag << 24));
 534         tg3_cond_int(tp);
 535 }
 536
 537 static inline unsigned int tg3_has_work(struct tg3 *tp)
 538 {
 539         struct tg3_hw_status *sblk = tp->hw_status;
 540         unsigned int work_exists = 0;
 541
 542         /* check for phy events */
 543         if (!(tp->tg3_flags &
 544               (TG3_FLAG_USE_LINKCHG_REG |
 545                TG3_FLAG_POLL_SERDES))) {
 546                 if (sblk->status & SD_STATUS_LINK_CHG)
 547                         work_exists = 1;
 548         }
 549         /* check for RX/TX work to do */
 550         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 551             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 552                 work_exists = 1;
 553
 554         return work_exists;
 555 }
 556
 557 /* tg3_restart_ints
 558  *  similar to tg3_enable_ints, but it accurately determines whether there
 559  *  is new work pending and can return without flushing the PIO write
 560  *  which reenables interrupts
 561  */
 562 static void tg3_restart_ints(struct tg3 *tp)
 563 {
 564         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 565                      tp->last_tag << 24);
 566         mmiowb();
 567
 568         /* When doing tagged status, this work check is unnecessary.
 569          * The last_tag we write above tells the chip which piece of
 570          * work we've completed.
 571          */
 572         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 573             tg3_has_work(tp))
 574                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 575                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 576 }
 577
 578 static inline void tg3_netif_stop(struct tg3 *tp)
 579 {
 580         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 581         netif_poll_disable(tp->dev);
 582         netif_tx_disable(tp->dev);
 583 }
 584
 585 static inline void tg3_netif_start(struct tg3 *tp)
 586 {
 587         netif_wake_queue(tp->dev);
 588         /* NOTE: unconditional netif_wake_queue is only appropriate
 589          * so long as all callers are assured to have free tx slots
 590          * (such as after tg3_init_hw)
 591          */
 592         netif_poll_enable(tp->dev);
 593         tp->hw_status->status |= SD_STATUS_UPDATED;
 594         tg3_enable_ints(tp);
 595 }
 596
 597 static void tg3_switch_clocks(struct tg3 *tp)
 598 {
 599         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 600         u32 orig_clock_ctrl;
 601
 602         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 603                 return;
 604
 605         orig_clock_ctrl = clock_ctrl;
 606         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 607                        CLOCK_CTRL_CLKRUN_OENABLE |
 608                        0x1f);
 609         tp->pci_clock_ctrl = clock_ctrl;
 610
 611         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 612                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 613                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 615                 }
 616         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl |
 619                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 620                             40);
 621                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 622                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 623                             40);
 624         }
 625         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 626 }
 627
 628 #define PHY_BUSY_LOOPS  5000
 629
 630 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 631 {
 632         u32 frame_val;
 633         unsigned int loops;
 634         int ret;
 635
 636         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 637                 tw32_f(MAC_MI_MODE,
 638                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 639                 udelay(80);
 640         }
 641
 642         *val = 0x0;
 643
 644         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 645                       MI_COM_PHY_ADDR_MASK);
 646         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 647                       MI_COM_REG_ADDR_MASK);
 648         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 649
 650         tw32_f(MAC_MI_COM, frame_val);
 651
 652         loops = PHY_BUSY_LOOPS;
 653         while (loops != 0) {
 654                 udelay(10);
 655                 frame_val = tr32(MAC_MI_COM);
 656
 657                 if ((frame_val & MI_COM_BUSY) == 0) {
 658                         udelay(5);
 659                         frame_val = tr32(MAC_MI_COM);
 660                         break;
 661                 }
 662                 loops -= 1;
 663         }
 664
 665         ret = -EBUSY;
 666         if (loops != 0) {
 667                 *val = frame_val & MI_COM_DATA_MASK;
 668                 ret = 0;
 669         }
 670
 671         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 672                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 673                 udelay(80);
 674         }
 675
 676         return ret;
 677 }
 678
 679 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 680 {
 681         u32 frame_val;
 682         unsigned int loops;
 683         int ret;
 684
 685         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 686             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 687                 return 0;
 688
 689         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 690                 tw32_f(MAC_MI_MODE,
 691                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 692                 udelay(80);
 693         }
 694
 695         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 696                       MI_COM_PHY_ADDR_MASK);
 697         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 698                       MI_COM_REG_ADDR_MASK);
 699         frame_val |= (val & MI_COM_DATA_MASK);
 700         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 701
 702         tw32_f(MAC_MI_COM, frame_val);
 703
 704         loops = PHY_BUSY_LOOPS;
 705         while (loops != 0) {
 706                 udelay(10);
 707                 frame_val = tr32(MAC_MI_COM);
 708                 if ((frame_val & MI_COM_BUSY) == 0) {
 709                         udelay(5);
 710                         frame_val = tr32(MAC_MI_COM);
 711                         break;
 712                 }
 713                 loops -= 1;
 714         }
 715
 716         ret = -EBUSY;
 717         if (loops != 0)
 718                 ret = 0;
 719
 720         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 721                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 722                 udelay(80);
 723         }
 724
 725         return ret;
 726 }
 727
 728 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 729 {
 730         u32 val;
 731
 732         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 733                 return;
 734
 735         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 736             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 737                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 738                              (val | (1 << 15) | (1 << 4)));
 739 }
 740
 741 static int tg3_bmcr_reset(struct tg3 *tp)
 742 {
 743         u32 phy_control;
 744         int limit, err;
 745
 746         /* OK, reset it, and poll the BMCR_RESET bit until it
 747          * clears or we time out.
 748          */
 749         phy_control = BMCR_RESET;
 750         err = tg3_writephy(tp, MII_BMCR, phy_control);
 751         if (err != 0)
 752                 return -EBUSY;
 753
 754         limit = 5000;
 755         while (limit--) {
 756                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 757                 if (err != 0)
 758                         return -EBUSY;
 759
 760                 if ((phy_control & BMCR_RESET) == 0) {
 761                         udelay(40);
 762                         break;
 763                 }
 764                 udelay(10);
 765         }
 766         if (limit <= 0)
 767                 return -EBUSY;
 768
 769         return 0;
 770 }
 771
 772 static int tg3_wait_macro_done(struct tg3 *tp)
 773 {
 774         int limit = 100;
 775
 776         while (limit--) {
 777                 u32 tmp32;
 778
 779                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 780                         if ((tmp32 & 0x1000) == 0)
 781                                 break;
 782                 }
 783         }
 784         if (limit <= 0)
 785                 return -EBUSY;
 786
 787         return 0;
 788 }
 789
 790 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 791 {
 792         static const u32 test_pat[4][6] = {
 793         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 794         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 795         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 796         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 797         };
 798         int chan;
 799
 800         for (chan = 0; chan < 4; chan++) {
 801                 int i;
 802
 803                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 804                              (chan * 0x2000) | 0x0200);
 805                 tg3_writephy(tp, 0x16, 0x0002);
 806
 807                 for (i = 0; i < 6; i++)
 808                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 809                                      test_pat[chan][i]);
 810
 811                 tg3_writephy(tp, 0x16, 0x0202);
 812                 if (tg3_wait_macro_done(tp)) {
 813                         *resetp = 1;
 814                         return -EBUSY;
 815                 }
 816
 817                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 818                              (chan * 0x2000) | 0x0200);
 819                 tg3_writephy(tp, 0x16, 0x0082);
 820                 if (tg3_wait_macro_done(tp)) {
 821                         *resetp = 1;
 822                         return -EBUSY;
 823                 }
 824
 825                 tg3_writephy(tp, 0x16, 0x0802);
 826                 if (tg3_wait_macro_done(tp)) {
 827                         *resetp = 1;
 828                         return -EBUSY;
 829                 }
 830
 831                 for (i = 0; i < 6; i += 2) {
 832                         u32 low, high;
 833
 834                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 835                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 836                             tg3_wait_macro_done(tp)) {
 837                                 *resetp = 1;
 838                                 return -EBUSY;
 839                         }
 840                         low &= 0x7fff;
 841                         high &= 0x000f;
 842                         if (low != test_pat[chan][i] ||
 843                             high != test_pat[chan][i+1]) {
 844                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 845                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 846                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 847
 848                                 return -EBUSY;
 849                         }
 850                 }
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 857 {
 858         int chan;
 859
 860         for (chan = 0; chan < 4; chan++) {
 861                 int i;
 862
 863                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 864                              (chan * 0x2000) | 0x0200);
 865                 tg3_writephy(tp, 0x16, 0x0002);
 866                 for (i = 0; i < 6; i++)
 867                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 868                 tg3_writephy(tp, 0x16, 0x0202);
 869                 if (tg3_wait_macro_done(tp))
 870                         return -EBUSY;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 877 {
 878         u32 reg32, phy9_orig;
 879         int retries, do_phy_reset, err;
 880
 881         retries = 10;
 882         do_phy_reset = 1;
 883         do {
 884                 if (do_phy_reset) {
 885                         err = tg3_bmcr_reset(tp);
 886                         if (err)
 887                                 return err;
 888                         do_phy_reset = 0;
 889                 }
 890
 891                 /* Disable transmitter and interrupt.  */
 892                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 893                         continue;
 894
 895                 reg32 |= 0x3000;
 896                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 897
 898                 /* Set full-duplex, 1000 mbps.  */
 899                 tg3_writephy(tp, MII_BMCR,
 900                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 901
 902                 /* Set to master mode.  */
 903                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 904                         continue;
 905
 906                 tg3_writephy(tp, MII_TG3_CTRL,
 907                              (MII_TG3_CTRL_AS_MASTER |
 908                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 909
 910                 /* Enable SM_DSP_CLOCK and 6dB.  */
 911                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 912
 913                 /* Block the PHY control access.  */
 914                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 915                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 916
 917                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 918                 if (!err)
 919                         break;
 920         } while (--retries);
 921
 922         err = tg3_phy_reset_chanpat(tp);
 923         if (err)
 924                 return err;
 925
 926         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 927         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 928
 929         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 930         tg3_writephy(tp, 0x16, 0x0000);
 931
 932         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 933             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 934                 /* Set Extended packet length bit for jumbo frames */
 935                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 936         }
 937         else {
 938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 939         }
 940
 941         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 942
 943         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 944                 reg32 &= ~0x3000;
 945                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 946         } else if (!err)
 947                 err = -EBUSY;
 948
 949         return err;
 950 }
 951
 952 static void tg3_link_report(struct tg3 *);
 953
 954 /* This will reset the tigon3 PHY if there is no valid
 955  * link unless the FORCE argument is non-zero.
 956  */
 957 static int tg3_phy_reset(struct tg3 *tp)
 958 {
 959         u32 phy_status;
 960         int err;
 961
 962         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 963         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 964         if (err != 0)
 965                 return -EBUSY;
 966
 967         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 968                 netif_carrier_off(tp->dev);
 969                 tg3_link_report(tp);
 970         }
 971
 972         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 975                 err = tg3_phy_reset_5703_4_5(tp);
 976                 if (err)
 977                         return err;
 978                 goto out;
 979         }
 980
 981         err = tg3_bmcr_reset(tp);
 982         if (err)
 983                 return err;
 984
 985 out:
 986         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 987                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 988                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 989                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 990                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 991                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 992                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 993         }
 994         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 995                 tg3_writephy(tp, 0x1c, 0x8d68);
 996                 tg3_writephy(tp, 0x1c, 0x8d68);
 997         }
 998         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1000                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1001                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1002                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1003                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1004                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1005                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1007         }
1008         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1010                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1011                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1013         }
1014         /* Set Extended packet length bit (bit 14) on all chips that */
1015         /* support jumbo frames */
1016         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1017                 /* Cannot do read-modify-write on 5401 */
1018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1019         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1020                 u32 phy_reg;
1021
1022                 /* Set bit 14 with read-modify-write to preserve other bits */
1023                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1024                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1025                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1026         }
1027
1028         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1029          * jumbo frames transmission.
1030          */
1031         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1032                 u32 phy_reg;
1033
1034                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1035                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1036                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1037         }
1038
1039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1040                 u32 phy_reg;
1041
1042                 /* adjust output voltage */
1043                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1044
1045                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1046                         u32 phy_reg2;
1047
1048                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1049                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1050                         /* Enable auto-MDIX */
1051                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1052                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1053                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1054                 }
1055         }
1056
1057         tg3_phy_set_wirespeed(tp);
1058         return 0;
1059 }
1060
1061 static void tg3_frob_aux_power(struct tg3 *tp)
1062 {
1063         struct tg3 *tp_peer = tp;
1064
1065         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1066                 return;
1067
1068         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1069             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1070                 struct net_device *dev_peer;
1071
1072                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1073                 /* remove_one() may have been run on the peer. */
1074                 if (!dev_peer)
1075                         tp_peer = tp;
1076                 else
1077                         tp_peer = netdev_priv(dev_peer);
1078         }
1079
1080         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1081             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1082             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1083             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1084                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1085                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1086                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1087                                     (GRC_LCLCTRL_GPIO_OE0 |
1088                                      GRC_LCLCTRL_GPIO_OE1 |
1089                                      GRC_LCLCTRL_GPIO_OE2 |
1090                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1091                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1092                                     100);
1093                 } else {
1094                         u32 no_gpio2;
1095                         u32 grc_local_ctrl = 0;
1096
1097                         if (tp_peer != tp &&
1098                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1099                                 return;
1100
1101                         /* Workaround to prevent overdrawing Amps. */
1102                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1103                             ASIC_REV_5714) {
1104                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1105                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1106                                             grc_local_ctrl, 100);
1107                         }
1108
1109                         /* On 5753 and variants, GPIO2 cannot be used. */
1110                         no_gpio2 = tp->nic_sram_data_cfg &
1111                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1112
1113                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1114                                          GRC_LCLCTRL_GPIO_OE1 |
1115                                          GRC_LCLCTRL_GPIO_OE2 |
1116                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1117                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1118                         if (no_gpio2) {
1119                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1120                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1121                         }
1122                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1123                                                     grc_local_ctrl, 100);
1124
1125                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1126
1127                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1128                                                     grc_local_ctrl, 100);
1129
1130                         if (!no_gpio2) {
1131                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1132                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1133                                             grc_local_ctrl, 100);
1134                         }
1135                 }
1136         } else {
1137                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1138                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1139                         if (tp_peer != tp &&
1140                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1141                                 return;
1142
1143                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1144                                     (GRC_LCLCTRL_GPIO_OE1 |
1145                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1146
1147                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1148                                     GRC_LCLCTRL_GPIO_OE1, 100);
1149
1150                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1151                                     (GRC_LCLCTRL_GPIO_OE1 |
1152                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1153                 }
1154         }
1155 }
1156
1157 static int tg3_setup_phy(struct tg3 *, int);
1158
1159 #define RESET_KIND_SHUTDOWN     0
1160 #define RESET_KIND_INIT         1
1161 #define RESET_KIND_SUSPEND      2
1162
1163 static void tg3_write_sig_post_reset(struct tg3 *, int);
1164 static int tg3_halt_cpu(struct tg3 *, u32);
1165 static int tg3_nvram_lock(struct tg3 *);
1166 static void tg3_nvram_unlock(struct tg3 *);
1167
1168 static void tg3_power_down_phy(struct tg3 *tp)
1169 {
1170         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1171                 return;
1172
1173         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1174                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1175                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1176                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1177         }
1178
1179         /* The PHY should not be powered down on some chips because
1180          * of bugs.
1181          */
1182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1183             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1184             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1185              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1186                 return;
1187         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1188 }
1189
1190 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1191 {
1192         u32 misc_host_ctrl;
1193         u16 power_control, power_caps;
1194         int pm = tp->pm_cap;
1195
1196         /* Make sure register accesses (indirect or otherwise)
1197          * will function correctly.
1198          */
1199         pci_write_config_dword(tp->pdev,
1200                                TG3PCI_MISC_HOST_CTRL,
1201                                tp->misc_host_ctrl);
1202
1203         pci_read_config_word(tp->pdev,
1204                              pm + PCI_PM_CTRL,
1205                              &power_control);
1206         power_control |= PCI_PM_CTRL_PME_STATUS;
1207         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1208         switch (state) {
1209         case PCI_D0:
1210                 power_control |= 0;
1211                 pci_write_config_word(tp->pdev,
1212                                       pm + PCI_PM_CTRL,
1213                                       power_control);
1214                 udelay(100);    /* Delay after power state change */
1215
1216                 /* Switch out of Vaux if it is a NIC */
1217                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1218                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1219
1220                 return 0;
1221
1222         case PCI_D1:
1223                 power_control |= 1;
1224                 break;
1225
1226         case PCI_D2:
1227                 power_control |= 2;
1228                 break;
1229
1230         case PCI_D3hot:
1231                 power_control |= 3;
1232                 break;
1233
1234         default:
1235                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1236                        "requested.\n",
1237                        tp->dev->name, state);
1238                 return -EINVAL;
1239         };
1240
1241         power_control |= PCI_PM_CTRL_PME_ENABLE;
1242
1243         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1244         tw32(TG3PCI_MISC_HOST_CTRL,
1245              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1246
1247         if (tp->link_config.phy_is_low_power == 0) {
1248                 tp->link_config.phy_is_low_power = 1;
1249                 tp->link_config.orig_speed = tp->link_config.speed;
1250                 tp->link_config.orig_duplex = tp->link_config.duplex;
1251                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1252         }
1253
1254         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1255                 tp->link_config.speed = SPEED_10;
1256                 tp->link_config.duplex = DUPLEX_HALF;
1257                 tp->link_config.autoneg = AUTONEG_ENABLE;
1258                 tg3_setup_phy(tp, 0);
1259         }
1260
1261         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1262                 u32 val;
1263
1264                 val = tr32(GRC_VCPU_EXT_CTRL);
1265                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1266         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1267                 int i;
1268                 u32 val;
1269
1270                 for (i = 0; i < 200; i++) {
1271                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1272                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1273                                 break;
1274                         msleep(1);
1275                 }
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1278                                              WOL_DRV_STATE_SHUTDOWN |
1279                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1280
1281         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1282
1283         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1284                 u32 mac_mode;
1285
1286                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1287                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1288                         udelay(40);
1289
1290                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1291                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1292                         else
1293                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1294
1295                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1296                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1297                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1298                 } else {
1299                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1300                 }
1301
1302                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1303                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1304
1305                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1306                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1307                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1308
1309                 tw32_f(MAC_MODE, mac_mode);
1310                 udelay(100);
1311
1312                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1313                 udelay(10);
1314         }
1315
1316         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1317             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1318              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1319                 u32 base_val;
1320
1321                 base_val = tp->pci_clock_ctrl;
1322                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1323                              CLOCK_CTRL_TXCLK_DISABLE);
1324
1325                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1326                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1327         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1328                 /* do nothing */
1329         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1330                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1331                 u32 newbits1, newbits2;
1332
1333                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1334                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1335                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1336                                     CLOCK_CTRL_TXCLK_DISABLE |
1337                                     CLOCK_CTRL_ALTCLK);
1338                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1339                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1340                         newbits1 = CLOCK_CTRL_625_CORE;
1341                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1342                 } else {
1343                         newbits1 = CLOCK_CTRL_ALTCLK;
1344                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1345                 }
1346
1347                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1348                             40);
1349
1350                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1351                             40);
1352
1353                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1354                         u32 newbits3;
1355
1356                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1357                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1358                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1359                                             CLOCK_CTRL_TXCLK_DISABLE |
1360                                             CLOCK_CTRL_44MHZ_CORE);
1361                         } else {
1362                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1363                         }
1364
1365                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1366                                     tp->pci_clock_ctrl | newbits3, 40);
1367                 }
1368         }
1369
1370         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1371             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1372                 tg3_power_down_phy(tp);
1373
1374         tg3_frob_aux_power(tp);
1375
1376         /* Workaround for unstable PLL clock */
1377         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1378             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1379                 u32 val = tr32(0x7d00);
1380
1381                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1382                 tw32(0x7d00, val);
1383                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1384                         int err;
1385
1386                         err = tg3_nvram_lock(tp);
1387                         tg3_halt_cpu(tp, RX_CPU_BASE);
1388                         if (!err)
1389                                 tg3_nvram_unlock(tp);
1390                 }
1391         }
1392
1393         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1394
1395         /* Finally, set the new power state. */
1396         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1397         udelay(100);    /* Delay after power state change */
1398
1399         return 0;
1400 }
1401
1402 static void tg3_link_report(struct tg3 *tp)
1403 {
1404         if (!netif_carrier_ok(tp->dev)) {
1405                 if (netif_msg_link(tp))
1406                         printk(KERN_INFO PFX "%s: Link is down.\n",
1407                                tp->dev->name);
1408         } else if (netif_msg_link(tp)) {
1409                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1410                        tp->dev->name,
1411                        (tp->link_config.active_speed == SPEED_1000 ?
1412                         1000 :
1413                         (tp->link_config.active_speed == SPEED_100 ?
1414                          100 : 10)),
1415                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1416                         "full" : "half"));
1417
1418                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1419                        "%s for RX.\n",
1420                        tp->dev->name,
1421                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1422                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1423         }
1424 }
1425
1426 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1427 {
1428         u32 new_tg3_flags = 0;
1429         u32 old_rx_mode = tp->rx_mode;
1430         u32 old_tx_mode = tp->tx_mode;
1431
1432         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1433
1434                 /* Convert 1000BaseX flow control bits to 1000BaseT
1435                  * bits before resolving flow control.
1436                  */
1437                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1438                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1439                                        ADVERTISE_PAUSE_ASYM);
1440                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1441
1442                         if (local_adv & ADVERTISE_1000XPAUSE)
1443                                 local_adv |= ADVERTISE_PAUSE_CAP;
1444                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1445                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1446                         if (remote_adv & LPA_1000XPAUSE)
1447                                 remote_adv |= LPA_PAUSE_CAP;
1448                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1449                                 remote_adv |= LPA_PAUSE_ASYM;
1450                 }
1451
1452                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1453                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1454                                 if (remote_adv & LPA_PAUSE_CAP)
1455                                         new_tg3_flags |=
1456                                                 (TG3_FLAG_RX_PAUSE |
1457                                                 TG3_FLAG_TX_PAUSE);
1458                                 else if (remote_adv & LPA_PAUSE_ASYM)
1459                                         new_tg3_flags |=
1460                                                 (TG3_FLAG_RX_PAUSE);
1461                         } else {
1462                                 if (remote_adv & LPA_PAUSE_CAP)
1463                                         new_tg3_flags |=
1464                                                 (TG3_FLAG_RX_PAUSE |
1465                                                 TG3_FLAG_TX_PAUSE);
1466                         }
1467                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1468                         if ((remote_adv & LPA_PAUSE_CAP) &&
1469                         (remote_adv & LPA_PAUSE_ASYM))
1470                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1471                 }
1472
1473                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1474                 tp->tg3_flags |= new_tg3_flags;
1475         } else {
1476                 new_tg3_flags = tp->tg3_flags;
1477         }
1478
1479         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1480                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1481         else
1482                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1483
1484         if (old_rx_mode != tp->rx_mode) {
1485                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1486         }
1487
1488         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1489                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1490         else
1491                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1492
1493         if (old_tx_mode != tp->tx_mode) {
1494                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1495         }
1496 }
1497
1498 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1499 {
1500         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1501         case MII_TG3_AUX_STAT_10HALF:
1502                 *speed = SPEED_10;
1503                 *duplex = DUPLEX_HALF;
1504                 break;
1505
1506         case MII_TG3_AUX_STAT_10FULL:
1507                 *speed = SPEED_10;
1508                 *duplex = DUPLEX_FULL;
1509                 break;
1510
1511         case MII_TG3_AUX_STAT_100HALF:
1512                 *speed = SPEED_100;
1513                 *duplex = DUPLEX_HALF;
1514                 break;
1515
1516         case MII_TG3_AUX_STAT_100FULL:
1517                 *speed = SPEED_100;
1518                 *duplex = DUPLEX_FULL;
1519                 break;
1520
1521         case MII_TG3_AUX_STAT_1000HALF:
1522                 *speed = SPEED_1000;
1523                 *duplex = DUPLEX_HALF;
1524                 break;
1525
1526         case MII_TG3_AUX_STAT_1000FULL:
1527                 *speed = SPEED_1000;
1528                 *duplex = DUPLEX_FULL;
1529                 break;
1530
1531         default:
1532                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1533                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1534                                  SPEED_10;
1535                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1536                                   DUPLEX_HALF;
1537                         break;
1538                 }
1539                 *speed = SPEED_INVALID;
1540                 *duplex = DUPLEX_INVALID;
1541                 break;
1542         };
1543 }
1544
1545 static void tg3_phy_copper_begin(struct tg3 *tp)
1546 {
1547         u32 new_adv;
1548         int i;
1549
1550         if (tp->link_config.phy_is_low_power) {
1551                 /* Entering low power mode.  Disable gigabit and
1552                  * 100baseT advertisements.
1553                  */
1554                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1555
1556                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1557                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1558                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1559                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1560
1561                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1562         } else if (tp->link_config.speed == SPEED_INVALID) {
1563                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1564                         tp->link_config.advertising &=
1565                                 ~(ADVERTISED_1000baseT_Half |
1566                                   ADVERTISED_1000baseT_Full);
1567
1568                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1569                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1570                         new_adv |= ADVERTISE_10HALF;
1571                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1572                         new_adv |= ADVERTISE_10FULL;
1573                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1574                         new_adv |= ADVERTISE_100HALF;
1575                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1576                         new_adv |= ADVERTISE_100FULL;
1577                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1578
1579                 if (tp->link_config.advertising &
1580                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1581                         new_adv = 0;
1582                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1583                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1584                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1585                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1586                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1587                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1588                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1589                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1590                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1591                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1592                 } else {
1593                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1594                 }
1595         } else {
1596                 /* Asking for a specific link mode. */
1597                 if (tp->link_config.speed == SPEED_1000) {
1598                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1599                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1600
1601                         if (tp->link_config.duplex == DUPLEX_FULL)
1602                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1603                         else
1604                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1605                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1606                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1607                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1608                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1609                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1610                 } else {
1611                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1612
1613                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1614                         if (tp->link_config.speed == SPEED_100) {
1615                                 if (tp->link_config.duplex == DUPLEX_FULL)
1616                                         new_adv |= ADVERTISE_100FULL;
1617                                 else
1618                                         new_adv |= ADVERTISE_100HALF;
1619                         } else {
1620                                 if (tp->link_config.duplex == DUPLEX_FULL)
1621                                         new_adv |= ADVERTISE_10FULL;
1622                                 else
1623                                         new_adv |= ADVERTISE_10HALF;
1624                         }
1625                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1626                 }
1627         }
1628
1629         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1630             tp->link_config.speed != SPEED_INVALID) {
1631                 u32 bmcr, orig_bmcr;
1632
1633                 tp->link_config.active_speed = tp->link_config.speed;
1634                 tp->link_config.active_duplex = tp->link_config.duplex;
1635
1636                 bmcr = 0;
1637                 switch (tp->link_config.speed) {
1638                 default:
1639                 case SPEED_10:
1640                         break;
1641
1642                 case SPEED_100:
1643                         bmcr |= BMCR_SPEED100;
1644                         break;
1645
1646                 case SPEED_1000:
1647                         bmcr |= TG3_BMCR_SPEED1000;
1648                         break;
1649                 };
1650
1651                 if (tp->link_config.duplex == DUPLEX_FULL)
1652                         bmcr |= BMCR_FULLDPLX;
1653
1654                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1655                     (bmcr != orig_bmcr)) {
1656                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1657                         for (i = 0; i < 1500; i++) {
1658                                 u32 tmp;
1659
1660                                 udelay(10);
1661                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1662                                     tg3_readphy(tp, MII_BMSR, &tmp))
1663                                         continue;
1664                                 if (!(tmp & BMSR_LSTATUS)) {
1665                                         udelay(40);
1666                                         break;
1667                                 }
1668                         }
1669                         tg3_writephy(tp, MII_BMCR, bmcr);
1670                         udelay(40);
1671                 }
1672         } else {
1673                 tg3_writephy(tp, MII_BMCR,
1674                              BMCR_ANENABLE | BMCR_ANRESTART);
1675         }
1676 }
1677
1678 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1679 {
1680         int err;
1681
1682         /* Turn off tap power management. */
1683         /* Set Extended packet length bit */
1684         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1685
1686         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1687         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1688
1689         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1690         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1691
1692         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1693         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1694
1695         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1696         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1697
1698         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1699         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1700
1701         udelay(40);
1702
1703         return err;
1704 }
1705
1706 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1707 {
1708         u32 adv_reg, all_mask = 0;
1709
1710         if (mask & ADVERTISED_10baseT_Half)
1711                 all_mask |= ADVERTISE_10HALF;
1712         if (mask & ADVERTISED_10baseT_Full)
1713                 all_mask |= ADVERTISE_10FULL;
1714         if (mask & ADVERTISED_100baseT_Half)
1715                 all_mask |= ADVERTISE_100HALF;
1716         if (mask & ADVERTISED_100baseT_Full)
1717                 all_mask |= ADVERTISE_100FULL;
1718
1719         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1720                 return 0;
1721
1722         if ((adv_reg & all_mask) != all_mask)
1723                 return 0;
1724         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1725                 u32 tg3_ctrl;
1726
1727                 all_mask = 0;
1728                 if (mask & ADVERTISED_1000baseT_Half)
1729                         all_mask |= ADVERTISE_1000HALF;
1730                 if (mask & ADVERTISED_1000baseT_Full)
1731                         all_mask |= ADVERTISE_1000FULL;
1732
1733                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1734                         return 0;
1735
1736                 if ((tg3_ctrl & all_mask) != all_mask)
1737                         return 0;
1738         }
1739         return 1;
1740 }
1741
1742 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1743 {
1744         int current_link_up;
1745         u32 bmsr, dummy;
1746         u16 current_speed;
1747         u8 current_duplex;
1748         int i, err;
1749
1750         tw32(MAC_EVENT, 0);
1751
1752         tw32_f(MAC_STATUS,
1753              (MAC_STATUS_SYNC_CHANGED |
1754               MAC_STATUS_CFG_CHANGED |
1755               MAC_STATUS_MI_COMPLETION |
1756               MAC_STATUS_LNKSTATE_CHANGED));
1757         udelay(40);
1758
1759         tp->mi_mode = MAC_MI_MODE_BASE;
1760         tw32_f(MAC_MI_MODE, tp->mi_mode);
1761         udelay(80);
1762
1763         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1764
1765         /* Some third-party PHYs need to be reset on link going
1766          * down.
1767          */
1768         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1769              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1770              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1771             netif_carrier_ok(tp->dev)) {
1772                 tg3_readphy(tp, MII_BMSR, &bmsr);
1773                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1774                     !(bmsr & BMSR_LSTATUS))
1775                         force_reset = 1;
1776         }
1777         if (force_reset)
1778                 tg3_phy_reset(tp);
1779
1780         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1781                 tg3_readphy(tp, MII_BMSR, &bmsr);
1782                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1783                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1784                         bmsr = 0;
1785
1786                 if (!(bmsr & BMSR_LSTATUS)) {
1787                         err = tg3_init_5401phy_dsp(tp);
1788                         if (err)
1789                                 return err;
1790
1791                         tg3_readphy(tp, MII_BMSR, &bmsr);
1792                         for (i = 0; i < 1000; i++) {
1793                                 udelay(10);
1794                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1795                                     (bmsr & BMSR_LSTATUS)) {
1796                                         udelay(40);
1797                                         break;
1798                                 }
1799                         }
1800
1801                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1802                             !(bmsr & BMSR_LSTATUS) &&
1803                             tp->link_config.active_speed == SPEED_1000) {
1804                                 err = tg3_phy_reset(tp);
1805                                 if (!err)
1806                                         err = tg3_init_5401phy_dsp(tp);
1807                                 if (err)
1808                                         return err;
1809                         }
1810                 }
1811         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1812                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1813                 /* 5701 {A0,B0} CRC bug workaround */
1814                 tg3_writephy(tp, 0x15, 0x0a75);
1815                 tg3_writephy(tp, 0x1c, 0x8c68);
1816                 tg3_writephy(tp, 0x1c, 0x8d68);
1817                 tg3_writephy(tp, 0x1c, 0x8c68);
1818         }
1819
1820         /* Clear pending interrupts... */
1821         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1822         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1823
1824         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1825                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1826         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1827                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1828
1829         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1830             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1831                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1832                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1833                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1834                 else
1835                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1836         }
1837
1838         current_link_up = 0;
1839         current_speed = SPEED_INVALID;
1840         current_duplex = DUPLEX_INVALID;
1841
1842         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1843                 u32 val;
1844
1845                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1846                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1847                 if (!(val & (1 << 10))) {
1848                         val |= (1 << 10);
1849                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1850                         goto relink;
1851                 }
1852         }
1853
1854         bmsr = 0;
1855         for (i = 0; i < 100; i++) {
1856                 tg3_readphy(tp, MII_BMSR, &bmsr);
1857                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1858                     (bmsr & BMSR_LSTATUS))
1859                         break;
1860                 udelay(40);
1861         }
1862
1863         if (bmsr & BMSR_LSTATUS) {
1864                 u32 aux_stat, bmcr;
1865
1866                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1867                 for (i = 0; i < 2000; i++) {
1868                         udelay(10);
1869                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1870                             aux_stat)
1871                                 break;
1872                 }
1873
1874                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1875                                              &current_speed,
1876                                              &current_duplex);
1877
1878                 bmcr = 0;
1879                 for (i = 0; i < 200; i++) {
1880                         tg3_readphy(tp, MII_BMCR, &bmcr);
1881                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1882                                 continue;
1883                         if (bmcr && bmcr != 0x7fff)
1884                                 break;
1885                         udelay(10);
1886                 }
1887
1888                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1889                         if (bmcr & BMCR_ANENABLE) {
1890                                 current_link_up = 1;
1891
1892                                 /* Force autoneg restart if we are exiting
1893                                  * low power mode.
1894                                  */
1895                                 if (!tg3_copper_is_advertising_all(tp,
1896                                                 tp->link_config.advertising))
1897                                         current_link_up = 0;
1898                         } else {
1899                                 current_link_up = 0;
1900                         }
1901                 } else {
1902                         if (!(bmcr & BMCR_ANENABLE) &&
1903                             tp->link_config.speed == current_speed &&
1904                             tp->link_config.duplex == current_duplex) {
1905                                 current_link_up = 1;
1906                         } else {
1907                                 current_link_up = 0;
1908                         }
1909                 }
1910
1911                 tp->link_config.active_speed = current_speed;
1912                 tp->link_config.active_duplex = current_duplex;
1913         }
1914
1915         if (current_link_up == 1 &&
1916             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1917             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1918                 u32 local_adv, remote_adv;
1919
1920                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1921                         local_adv = 0;
1922                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1923
1924                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1925                         remote_adv = 0;
1926
1927                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1928
1929                 /* If we are not advertising full pause capability,
1930                  * something is wrong.  Bring the link down and reconfigure.
1931                  */
1932                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1933                         current_link_up = 0;
1934                 } else {
1935                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1936                 }
1937         }
1938 relink:
1939         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1940                 u32 tmp;
1941
1942                 tg3_phy_copper_begin(tp);
1943
1944                 tg3_readphy(tp, MII_BMSR, &tmp);
1945                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1946                     (tmp & BMSR_LSTATUS))
1947                         current_link_up = 1;
1948         }
1949
1950         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1951         if (current_link_up == 1) {
1952                 if (tp->link_config.active_speed == SPEED_100 ||
1953                     tp->link_config.active_speed == SPEED_10)
1954                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1955                 else
1956                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1957         } else
1958                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1959
1960         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1961         if (tp->link_config.active_duplex == DUPLEX_HALF)
1962                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1963
1964         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1965         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1966                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1967                     (current_link_up == 1 &&
1968                      tp->link_config.active_speed == SPEED_10))
1969                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1970         } else {
1971                 if (current_link_up == 1)
1972                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1973         }
1974
1975         /* ??? Without this setting Netgear GA302T PHY does not
1976          * ??? send/receive packets...
1977          */
1978         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1979             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1980                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1981                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1982                 udelay(80);
1983         }
1984
1985         tw32_f(MAC_MODE, tp->mac_mode);
1986         udelay(40);
1987
1988         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1989                 /* Polled via timer. */
1990                 tw32_f(MAC_EVENT, 0);
1991         } else {
1992                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1993         }
1994         udelay(40);
1995
1996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1997             current_link_up == 1 &&
1998             tp->link_config.active_speed == SPEED_1000 &&
1999             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2000              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2001                 udelay(120);
2002                 tw32_f(MAC_STATUS,
2003                      (MAC_STATUS_SYNC_CHANGED |
2004                       MAC_STATUS_CFG_CHANGED));
2005                 udelay(40);
2006                 tg3_write_mem(tp,
2007                               NIC_SRAM_FIRMWARE_MBOX,
2008                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2009         }
2010
2011         if (current_link_up != netif_carrier_ok(tp->dev)) {
2012                 if (current_link_up)
2013                         netif_carrier_on(tp->dev);
2014                 else
2015                         netif_carrier_off(tp->dev);
2016                 tg3_link_report(tp);
2017         }
2018
2019         return 0;
2020 }
2021
2022 struct tg3_fiber_aneginfo {
2023         int state;
2024 #define ANEG_STATE_UNKNOWN              0
2025 #define ANEG_STATE_AN_ENABLE            1
2026 #define ANEG_STATE_RESTART_INIT         2
2027 #define ANEG_STATE_RESTART              3
2028 #define ANEG_STATE_DISABLE_LINK_OK      4
2029 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2030 #define ANEG_STATE_ABILITY_DETECT       6
2031 #define ANEG_STATE_ACK_DETECT_INIT      7
2032 #define ANEG_STATE_ACK_DETECT           8
2033 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2034 #define ANEG_STATE_COMPLETE_ACK         10
2035 #define ANEG_STATE_IDLE_DETECT_INIT     11
2036 #define ANEG_STATE_IDLE_DETECT          12
2037 #define ANEG_STATE_LINK_OK              13
2038 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2039 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2040
2041         u32 flags;
2042 #define MR_AN_ENABLE            0x00000001
2043 #define MR_RESTART_AN           0x00000002
2044 #define MR_AN_COMPLETE          0x00000004
2045 #define MR_PAGE_RX              0x00000008
2046 #define MR_NP_LOADED            0x00000010
2047 #define MR_TOGGLE_TX            0x00000020
2048 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2049 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2050 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2051 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2052 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2053 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2054 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2055 #define MR_TOGGLE_RX            0x00002000
2056 #define MR_NP_RX                0x00004000
2057
2058 #define MR_LINK_OK              0x80000000
2059
2060         unsigned long link_time, cur_time;
2061
2062         u32 ability_match_cfg;
2063         int ability_match_count;
2064
2065         char ability_match, idle_match, ack_match;
2066
2067         u32 txconfig, rxconfig;
2068 #define ANEG_CFG_NP             0x00000080
2069 #define ANEG_CFG_ACK            0x00000040
2070 #define ANEG_CFG_RF2            0x00000020
2071 #define ANEG_CFG_RF1            0x00000010
2072 #define ANEG_CFG_PS2            0x00000001
2073 #define ANEG_CFG_PS1            0x00008000
2074 #define ANEG_CFG_HD             0x00004000
2075 #define ANEG_CFG_FD             0x00002000
2076 #define ANEG_CFG_INVAL          0x00001f06
2077
2078 };
2079 #define ANEG_OK         0
2080 #define ANEG_DONE       1
2081 #define ANEG_TIMER_ENAB 2
2082 #define ANEG_FAILED     -1
2083
2084 #define ANEG_STATE_SETTLE_TIME  10000
2085
2086 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2087                                    struct tg3_fiber_aneginfo *ap)
2088 {
2089         unsigned long delta;
2090         u32 rx_cfg_reg;
2091         int ret;
2092
2093         if (ap->state == ANEG_STATE_UNKNOWN) {
2094                 ap->rxconfig = 0;
2095                 ap->link_time = 0;
2096                 ap->cur_time = 0;
2097                 ap->ability_match_cfg = 0;
2098                 ap->ability_match_count = 0;
2099                 ap->ability_match = 0;
2100                 ap->idle_match = 0;
2101                 ap->ack_match = 0;
2102         }
2103         ap->cur_time++;
2104
2105         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2106                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2107
2108                 if (rx_cfg_reg != ap->ability_match_cfg) {
2109                         ap->ability_match_cfg = rx_cfg_reg;
2110                         ap->ability_match = 0;
2111                         ap->ability_match_count = 0;
2112                 } else {
2113                         if (++ap->ability_match_count > 1) {
2114                                 ap->ability_match = 1;
2115                                 ap->ability_match_cfg = rx_cfg_reg;
2116                         }
2117                 }
2118                 if (rx_cfg_reg & ANEG_CFG_ACK)
2119                         ap->ack_match = 1;
2120                 else
2121                         ap->ack_match = 0;
2122
2123                 ap->idle_match = 0;
2124         } else {
2125                 ap->idle_match = 1;
2126                 ap->ability_match_cfg = 0;
2127                 ap->ability_match_count = 0;
2128                 ap->ability_match = 0;
2129                 ap->ack_match = 0;
2130
2131                 rx_cfg_reg = 0;
2132         }
2133
2134         ap->rxconfig = rx_cfg_reg;
2135         ret = ANEG_OK;
2136
2137         switch(ap->state) {
2138         case ANEG_STATE_UNKNOWN:
2139                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2140                         ap->state = ANEG_STATE_AN_ENABLE;
2141
2142                 /* fallthru */
2143         case ANEG_STATE_AN_ENABLE:
2144                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2145                 if (ap->flags & MR_AN_ENABLE) {
2146                         ap->link_time = 0;
2147                         ap->cur_time = 0;
2148                         ap->ability_match_cfg = 0;
2149                         ap->ability_match_count = 0;
2150                         ap->ability_match = 0;
2151                         ap->idle_match = 0;
2152                         ap->ack_match = 0;
2153
2154                         ap->state = ANEG_STATE_RESTART_INIT;
2155                 } else {
2156                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2157                 }
2158                 break;
2159
2160         case ANEG_STATE_RESTART_INIT:
2161                 ap->link_time = ap->cur_time;
2162                 ap->flags &= ~(MR_NP_LOADED);
2163                 ap->txconfig = 0;
2164                 tw32(MAC_TX_AUTO_NEG, 0);
2165                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2166                 tw32_f(MAC_MODE, tp->mac_mode);
2167                 udelay(40);
2168
2169                 ret = ANEG_TIMER_ENAB;
2170                 ap->state = ANEG_STATE_RESTART;
2171
2172                 /* fallthru */
2173         case ANEG_STATE_RESTART:
2174                 delta = ap->cur_time - ap->link_time;
2175                 if (delta > ANEG_STATE_SETTLE_TIME) {
2176                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2177                 } else {
2178                         ret = ANEG_TIMER_ENAB;
2179                 }
2180                 break;
2181
2182         case ANEG_STATE_DISABLE_LINK_OK:
2183                 ret = ANEG_DONE;
2184                 break;
2185
2186         case ANEG_STATE_ABILITY_DETECT_INIT:
2187                 ap->flags &= ~(MR_TOGGLE_TX);
2188                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2189                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2190                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2191                 tw32_f(MAC_MODE, tp->mac_mode);
2192                 udelay(40);
2193
2194                 ap->state = ANEG_STATE_ABILITY_DETECT;
2195                 break;
2196
2197         case ANEG_STATE_ABILITY_DETECT:
2198                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2199                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2200                 }
2201                 break;
2202
2203         case ANEG_STATE_ACK_DETECT_INIT:
2204                 ap->txconfig |= ANEG_CFG_ACK;
2205                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2206                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2207                 tw32_f(MAC_MODE, tp->mac_mode);
2208                 udelay(40);
2209
2210                 ap->state = ANEG_STATE_ACK_DETECT;
2211
2212                 /* fallthru */
2213         case ANEG_STATE_ACK_DETECT:
2214                 if (ap->ack_match != 0) {
2215                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2216                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2217                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2218                         } else {
2219                                 ap->state = ANEG_STATE_AN_ENABLE;
2220                         }
2221                 } else if (ap->ability_match != 0 &&
2222                            ap->rxconfig == 0) {
2223                         ap->state = ANEG_STATE_AN_ENABLE;
2224                 }
2225                 break;
2226
2227         case ANEG_STATE_COMPLETE_ACK_INIT:
2228                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2229                         ret = ANEG_FAILED;
2230                         break;
2231                 }
2232                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2233                                MR_LP_ADV_HALF_DUPLEX |
2234                                MR_LP_ADV_SYM_PAUSE |
2235                                MR_LP_ADV_ASYM_PAUSE |
2236                                MR_LP_ADV_REMOTE_FAULT1 |
2237                                MR_LP_ADV_REMOTE_FAULT2 |
2238                                MR_LP_ADV_NEXT_PAGE |
2239                                MR_TOGGLE_RX |
2240                                MR_NP_RX);
2241                 if (ap->rxconfig & ANEG_CFG_FD)
2242                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2243                 if (ap->rxconfig & ANEG_CFG_HD)
2244                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2245                 if (ap->rxconfig & ANEG_CFG_PS1)
2246                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2247                 if (ap->rxconfig & ANEG_CFG_PS2)
2248                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2249                 if (ap->rxconfig & ANEG_CFG_RF1)
2250                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2251                 if (ap->rxconfig & ANEG_CFG_RF2)
2252                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2253                 if (ap->rxconfig & ANEG_CFG_NP)
2254                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2255
2256                 ap->link_time = ap->cur_time;
2257
2258                 ap->flags ^= (MR_TOGGLE_TX);
2259                 if (ap->rxconfig & 0x0008)
2260                         ap->flags |= MR_TOGGLE_RX;
2261                 if (ap->rxconfig & ANEG_CFG_NP)
2262                         ap->flags |= MR_NP_RX;
2263                 ap->flags |= MR_PAGE_RX;
2264
2265                 ap->state = ANEG_STATE_COMPLETE_ACK;
2266                 ret = ANEG_TIMER_ENAB;
2267                 break;
2268
2269         case ANEG_STATE_COMPLETE_ACK:
2270                 if (ap->ability_match != 0 &&
2271                     ap->rxconfig == 0) {
2272                         ap->state = ANEG_STATE_AN_ENABLE;
2273                         break;
2274                 }
2275                 delta = ap->cur_time - ap->link_time;
2276                 if (delta > ANEG_STATE_SETTLE_TIME) {
2277                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2278                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2279                         } else {
2280                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2281                                     !(ap->flags & MR_NP_RX)) {
2282                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2283                                 } else {
2284                                         ret = ANEG_FAILED;
2285                                 }
2286                         }
2287                 }
2288                 break;
2289
2290         case ANEG_STATE_IDLE_DETECT_INIT:
2291                 ap->link_time = ap->cur_time;
2292                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2293                 tw32_f(MAC_MODE, tp->mac_mode);
2294                 udelay(40);
2295
2296                 ap->state = ANEG_STATE_IDLE_DETECT;
2297                 ret = ANEG_TIMER_ENAB;
2298                 break;
2299
2300         case ANEG_STATE_IDLE_DETECT:
2301                 if (ap->ability_match != 0 &&
2302                     ap->rxconfig == 0) {
2303                         ap->state = ANEG_STATE_AN_ENABLE;
2304                         break;
2305                 }
2306                 delta = ap->cur_time - ap->link_time;
2307                 if (delta > ANEG_STATE_SETTLE_TIME) {
2308                         /* XXX another gem from the Broadcom driver :( */
2309                         ap->state = ANEG_STATE_LINK_OK;
2310                 }
2311                 break;
2312
2313         case ANEG_STATE_LINK_OK:
2314                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2315                 ret = ANEG_DONE;
2316                 break;
2317
2318         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2319                 /* ??? unimplemented */
2320                 break;
2321
2322         case ANEG_STATE_NEXT_PAGE_WAIT:
2323                 /* ??? unimplemented */
2324                 break;
2325
2326         default:
2327                 ret = ANEG_FAILED;
2328                 break;
2329         };
2330
2331         return ret;
2332 }
2333
2334 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2335 {
2336         int res = 0;
2337         struct tg3_fiber_aneginfo aninfo;
2338         int status = ANEG_FAILED;
2339         unsigned int tick;
2340         u32 tmp;
2341
2342         tw32_f(MAC_TX_AUTO_NEG, 0);
2343
2344         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2345         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2346         udelay(40);
2347
2348         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2349         udelay(40);
2350
2351         memset(&aninfo, 0, sizeof(aninfo));
2352         aninfo.flags |= MR_AN_ENABLE;
2353         aninfo.state = ANEG_STATE_UNKNOWN;
2354         aninfo.cur_time = 0;
2355         tick = 0;
2356         while (++tick < 195000) {
2357                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2358                 if (status == ANEG_DONE || status == ANEG_FAILED)
2359                         break;
2360
2361                 udelay(1);
2362         }
2363
2364         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2365         tw32_f(MAC_MODE, tp->mac_mode);
2366         udelay(40);
2367
2368         *flags = aninfo.flags;
2369
2370         if (status == ANEG_DONE &&
2371             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2372                              MR_LP_ADV_FULL_DUPLEX)))
2373                 res = 1;
2374
2375         return res;
2376 }
2377
2378 static void tg3_init_bcm8002(struct tg3 *tp)
2379 {
2380         u32 mac_status = tr32(MAC_STATUS);
2381         int i;
2382
2383         /* Reset when initting first time or we have a link. */
2384         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2385             !(mac_status & MAC_STATUS_PCS_SYNCED))
2386                 return;
2387
2388         /* Set PLL lock range. */
2389         tg3_writephy(tp, 0x16, 0x8007);
2390
2391         /* SW reset */
2392         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2393
2394         /* Wait for reset to complete. */
2395         /* XXX schedule_timeout() ... */
2396         for (i = 0; i < 500; i++)
2397                 udelay(10);
2398
2399         /* Config mode; select PMA/Ch 1 regs. */
2400         tg3_writephy(tp, 0x10, 0x8411);
2401
2402         /* Enable auto-lock and comdet, select txclk for tx. */
2403         tg3_writephy(tp, 0x11, 0x0a10);
2404
2405         tg3_writephy(tp, 0x18, 0x00a0);
2406         tg3_writephy(tp, 0x16, 0x41ff);
2407
2408         /* Assert and deassert POR. */
2409         tg3_writephy(tp, 0x13, 0x0400);
2410         udelay(40);
2411         tg3_writephy(tp, 0x13, 0x0000);
2412
2413         tg3_writephy(tp, 0x11, 0x0a50);
2414         udelay(40);
2415         tg3_writephy(tp, 0x11, 0x0a10);
2416
2417         /* Wait for signal to stabilize */
2418         /* XXX schedule_timeout() ... */
2419         for (i = 0; i < 15000; i++)
2420                 udelay(10);
2421
2422         /* Deselect the channel register so we can read the PHYID
2423          * later.
2424          */
2425         tg3_writephy(tp, 0x10, 0x8011);
2426 }
2427
2428 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2429 {
2430         u32 sg_dig_ctrl, sg_dig_status;
2431         u32 serdes_cfg, expected_sg_dig_ctrl;
2432         int workaround, port_a;
2433         int current_link_up;
2434
2435         serdes_cfg = 0;
2436         expected_sg_dig_ctrl = 0;
2437         workaround = 0;
2438         port_a = 1;
2439         current_link_up = 0;
2440
2441         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2442             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2443                 workaround = 1;
2444                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2445                         port_a = 0;
2446
2447                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2448                 /* preserve bits 20-23 for voltage regulator */
2449                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2450         }
2451
2452         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2453
2454         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2455                 if (sg_dig_ctrl & (1 << 31)) {
2456                         if (workaround) {
2457                                 u32 val = serdes_cfg;
2458
2459                                 if (port_a)
2460                                         val |= 0xc010000;
2461                                 else
2462                                         val |= 0x4010000;
2463                                 tw32_f(MAC_SERDES_CFG, val);
2464                         }
2465                         tw32_f(SG_DIG_CTRL, 0x01388400);
2466                 }
2467                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2468                         tg3_setup_flow_control(tp, 0, 0);
2469                         current_link_up = 1;
2470                 }
2471                 goto out;
2472         }
2473
2474         /* Want auto-negotiation.  */
2475         expected_sg_dig_ctrl = 0x81388400;
2476
2477         /* Pause capability */
2478         expected_sg_dig_ctrl |= (1 << 11);
2479
2480         /* Asymettric pause */
2481         expected_sg_dig_ctrl |= (1 << 12);
2482
2483         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2484                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2485                     tp->serdes_counter &&
2486                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2487                                     MAC_STATUS_RCVD_CFG)) ==
2488                      MAC_STATUS_PCS_SYNCED)) {
2489                         tp->serdes_counter--;
2490                         current_link_up = 1;
2491                         goto out;
2492                 }
2493 restart_autoneg:
2494                 if (workaround)
2495                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2496                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2497                 udelay(5);
2498                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2499
2500                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2501                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2502         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2503                                  MAC_STATUS_SIGNAL_DET)) {
2504                 sg_dig_status = tr32(SG_DIG_STATUS);
2505                 mac_status = tr32(MAC_STATUS);
2506
2507                 if ((sg_dig_status & (1 << 1)) &&
2508                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2509                         u32 local_adv, remote_adv;
2510
2511                         local_adv = ADVERTISE_PAUSE_CAP;
2512                         remote_adv = 0;
2513                         if (sg_dig_status & (1 << 19))
2514                                 remote_adv |= LPA_PAUSE_CAP;
2515                         if (sg_dig_status & (1 << 20))
2516                                 remote_adv |= LPA_PAUSE_ASYM;
2517
2518                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2519                         current_link_up = 1;
2520                         tp->serdes_counter = 0;
2521                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2522                 } else if (!(sg_dig_status & (1 << 1))) {
2523                         if (tp->serdes_counter)
2524                                 tp->serdes_counter--;
2525                         else {
2526                                 if (workaround) {
2527                                         u32 val = serdes_cfg;
2528
2529                                         if (port_a)
2530                                                 val |= 0xc010000;
2531                                         else
2532                                                 val |= 0x4010000;
2533
2534                                         tw32_f(MAC_SERDES_CFG, val);
2535                                 }
2536
2537                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2538                                 udelay(40);
2539
2540                                 /* Link parallel detection - link is up */
2541                                 /* only if we have PCS_SYNC and not */
2542                                 /* receiving config code words */
2543                                 mac_status = tr32(MAC_STATUS);
2544                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2545                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2546                                         tg3_setup_flow_control(tp, 0, 0);
2547                                         current_link_up = 1;
2548                                         tp->tg3_flags2 |=
2549                                                 TG3_FLG2_PARALLEL_DETECT;
2550                                         tp->serdes_counter =
2551                                                 SERDES_PARALLEL_DET_TIMEOUT;
2552                                 } else
2553                                         goto restart_autoneg;
2554                         }
2555                 }
2556         } else {
2557                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2558                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2559         }
2560
2561 out:
2562         return current_link_up;
2563 }
2564
2565 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2566 {
2567         int current_link_up = 0;
2568
2569         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2570                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2571                 goto out;
2572         }
2573
2574         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2575                 u32 flags;
2576                 int i;
2577
2578                 if (fiber_autoneg(tp, &flags)) {
2579                         u32 local_adv, remote_adv;
2580
2581                         local_adv = ADVERTISE_PAUSE_CAP;
2582                         remote_adv = 0;
2583                         if (flags & MR_LP_ADV_SYM_PAUSE)
2584                                 remote_adv |= LPA_PAUSE_CAP;
2585                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2586                                 remote_adv |= LPA_PAUSE_ASYM;
2587
2588                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2589
2590                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2591                         current_link_up = 1;
2592                 }
2593                 for (i = 0; i < 30; i++) {
2594                         udelay(20);
2595                         tw32_f(MAC_STATUS,
2596                                (MAC_STATUS_SYNC_CHANGED |
2597                                 MAC_STATUS_CFG_CHANGED));
2598                         udelay(40);
2599                         if ((tr32(MAC_STATUS) &
2600                              (MAC_STATUS_SYNC_CHANGED |
2601                               MAC_STATUS_CFG_CHANGED)) == 0)
2602                                 break;
2603                 }
2604
2605                 mac_status = tr32(MAC_STATUS);
2606                 if (current_link_up == 0 &&
2607                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2608                     !(mac_status & MAC_STATUS_RCVD_CFG))
2609                         current_link_up = 1;
2610         } else {
2611                 /* Forcing 1000FD link up. */
2612                 current_link_up = 1;
2613                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2614
2615                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2616                 udelay(40);
2617         }
2618
2619 out:
2620         return current_link_up;
2621 }
2622
2623 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2624 {
2625         u32 orig_pause_cfg;
2626         u16 orig_active_speed;
2627         u8 orig_active_duplex;
2628         u32 mac_status;
2629         int current_link_up;
2630         int i;
2631
2632         orig_pause_cfg =
2633                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2634                                   TG3_FLAG_TX_PAUSE));
2635         orig_active_speed = tp->link_config.active_speed;
2636         orig_active_duplex = tp->link_config.active_duplex;
2637
2638         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2639             netif_carrier_ok(tp->dev) &&
2640             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2641                 mac_status = tr32(MAC_STATUS);
2642                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2643                                MAC_STATUS_SIGNAL_DET |
2644                                MAC_STATUS_CFG_CHANGED |
2645                                MAC_STATUS_RCVD_CFG);
2646                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2647                                    MAC_STATUS_SIGNAL_DET)) {
2648                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2649                                             MAC_STATUS_CFG_CHANGED));
2650                         return 0;
2651                 }
2652         }
2653
2654         tw32_f(MAC_TX_AUTO_NEG, 0);
2655
2656         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2657         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2658         tw32_f(MAC_MODE, tp->mac_mode);
2659         udelay(40);
2660
2661         if (tp->phy_id == PHY_ID_BCM8002)
2662                 tg3_init_bcm8002(tp);
2663
2664         /* Enable link change event even when serdes polling.  */
2665         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2666         udelay(40);
2667
2668         current_link_up = 0;
2669         mac_status = tr32(MAC_STATUS);
2670
2671         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2672                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2673         else
2674                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2675
2676         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2677         tw32_f(MAC_MODE, tp->mac_mode);
2678         udelay(40);
2679
2680         tp->hw_status->status =
2681                 (SD_STATUS_UPDATED |
2682                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2683
2684         for (i = 0; i < 100; i++) {
2685                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2686                                     MAC_STATUS_CFG_CHANGED));
2687                 udelay(5);
2688                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2689                                          MAC_STATUS_CFG_CHANGED |
2690                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2691                         break;
2692         }
2693
2694         mac_status = tr32(MAC_STATUS);
2695         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2696                 current_link_up = 0;
2697                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2698                     tp->serdes_counter == 0) {
2699                         tw32_f(MAC_MODE, (tp->mac_mode |
2700                                           MAC_MODE_SEND_CONFIGS));
2701                         udelay(1);
2702                         tw32_f(MAC_MODE, tp->mac_mode);
2703                 }
2704         }
2705
2706         if (current_link_up == 1) {
2707                 tp->link_config.active_speed = SPEED_1000;
2708                 tp->link_config.active_duplex = DUPLEX_FULL;
2709                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2710                                     LED_CTRL_LNKLED_OVERRIDE |
2711                                     LED_CTRL_1000MBPS_ON));
2712         } else {
2713                 tp->link_config.active_speed = SPEED_INVALID;
2714                 tp->link_config.active_duplex = DUPLEX_INVALID;
2715                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2716                                     LED_CTRL_LNKLED_OVERRIDE |
2717                                     LED_CTRL_TRAFFIC_OVERRIDE));
2718         }
2719
2720         if (current_link_up != netif_carrier_ok(tp->dev)) {
2721                 if (current_link_up)
2722                         netif_carrier_on(tp->dev);
2723                 else
2724                         netif_carrier_off(tp->dev);
2725                 tg3_link_report(tp);
2726         } else {
2727                 u32 now_pause_cfg =
2728                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2729                                          TG3_FLAG_TX_PAUSE);
2730                 if (orig_pause_cfg != now_pause_cfg ||
2731                     orig_active_speed != tp->link_config.active_speed ||
2732                     orig_active_duplex != tp->link_config.active_duplex)
2733                         tg3_link_report(tp);
2734         }
2735
2736         return 0;
2737 }
2738
2739 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2740 {
2741         int current_link_up, err = 0;
2742         u32 bmsr, bmcr;
2743         u16 current_speed;
2744         u8 current_duplex;
2745
2746         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2747         tw32_f(MAC_MODE, tp->mac_mode);
2748         udelay(40);
2749
2750         tw32(MAC_EVENT, 0);
2751
2752         tw32_f(MAC_STATUS,
2753              (MAC_STATUS_SYNC_CHANGED |
2754               MAC_STATUS_CFG_CHANGED |
2755               MAC_STATUS_MI_COMPLETION |
2756               MAC_STATUS_LNKSTATE_CHANGED));
2757         udelay(40);
2758
2759         if (force_reset)
2760                 tg3_phy_reset(tp);
2761
2762         current_link_up = 0;
2763         current_speed = SPEED_INVALID;
2764         current_duplex = DUPLEX_INVALID;
2765
2766         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2767         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2768         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2769                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2770                         bmsr |= BMSR_LSTATUS;
2771                 else
2772                         bmsr &= ~BMSR_LSTATUS;
2773         }
2774
2775         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2776
2777         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2778             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2779                 /* do nothing, just check for link up at the end */
2780         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2781                 u32 adv, new_adv;
2782
2783                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2784                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2785                                   ADVERTISE_1000XPAUSE |
2786                                   ADVERTISE_1000XPSE_ASYM |
2787                                   ADVERTISE_SLCT);
2788
2789                 /* Always advertise symmetric PAUSE just like copper */
2790                 new_adv |= ADVERTISE_1000XPAUSE;
2791
2792                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2793                         new_adv |= ADVERTISE_1000XHALF;
2794                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2795                         new_adv |= ADVERTISE_1000XFULL;
2796
2797                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2798                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2799                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2800                         tg3_writephy(tp, MII_BMCR, bmcr);
2801
2802                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2803                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2804                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2805
2806                         return err;
2807                 }
2808         } else {
2809                 u32 new_bmcr;
2810
2811                 bmcr &= ~BMCR_SPEED1000;
2812                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2813
2814                 if (tp->link_config.duplex == DUPLEX_FULL)
2815                         new_bmcr |= BMCR_FULLDPLX;
2816
2817                 if (new_bmcr != bmcr) {
2818                         /* BMCR_SPEED1000 is a reserved bit that needs
2819                          * to be set on write.
2820                          */
2821                         new_bmcr |= BMCR_SPEED1000;
2822
2823                         /* Force a linkdown */
2824                         if (netif_carrier_ok(tp->dev)) {
2825                                 u32 adv;
2826
2827                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2828                                 adv &= ~(ADVERTISE_1000XFULL |
2829                                          ADVERTISE_1000XHALF |
2830                                          ADVERTISE_SLCT);
2831                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2832                                 tg3_writephy(tp, MII_BMCR, bmcr |
2833                                                            BMCR_ANRESTART |
2834                                                            BMCR_ANENABLE);
2835                                 udelay(10);
2836                                 netif_carrier_off(tp->dev);
2837                         }
2838                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2839                         bmcr = new_bmcr;
2840                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2841                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2842                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2843                             ASIC_REV_5714) {
2844                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2845                                         bmsr |= BMSR_LSTATUS;
2846                                 else
2847                                         bmsr &= ~BMSR_LSTATUS;
2848                         }
2849                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2850                 }
2851         }
2852
2853         if (bmsr & BMSR_LSTATUS) {
2854                 current_speed = SPEED_1000;
2855                 current_link_up = 1;
2856                 if (bmcr & BMCR_FULLDPLX)
2857                         current_duplex = DUPLEX_FULL;
2858                 else
2859                         current_duplex = DUPLEX_HALF;
2860
2861                 if (bmcr & BMCR_ANENABLE) {
2862                         u32 local_adv, remote_adv, common;
2863
2864                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2865                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2866                         common = local_adv & remote_adv;
2867                         if (common & (ADVERTISE_1000XHALF |
2868                                       ADVERTISE_1000XFULL)) {
2869                                 if (common & ADVERTISE_1000XFULL)
2870                                         current_duplex = DUPLEX_FULL;
2871                                 else
2872                                         current_duplex = DUPLEX_HALF;
2873
2874                                 tg3_setup_flow_control(tp, local_adv,
2875                                                        remote_adv);
2876                         }
2877                         else
2878                                 current_link_up = 0;
2879                 }
2880         }
2881
2882         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2883         if (tp->link_config.active_duplex == DUPLEX_HALF)
2884                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2885
2886         tw32_f(MAC_MODE, tp->mac_mode);
2887         udelay(40);
2888
2889         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2890
2891         tp->link_config.active_speed = current_speed;
2892         tp->link_config.active_duplex = current_duplex;
2893
2894         if (current_link_up != netif_carrier_ok(tp->dev)) {
2895                 if (current_link_up)
2896                         netif_carrier_on(tp->dev);
2897                 else {
2898                         netif_carrier_off(tp->dev);
2899                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2900                 }
2901                 tg3_link_report(tp);
2902         }
2903         return err;
2904 }
2905
2906 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2907 {
2908         if (tp->serdes_counter) {
2909                 /* Give autoneg time to complete. */
2910                 tp->serdes_counter--;
2911                 return;
2912         }
2913         if (!netif_carrier_ok(tp->dev) &&
2914             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2915                 u32 bmcr;
2916
2917                 tg3_readphy(tp, MII_BMCR, &bmcr);
2918                 if (bmcr & BMCR_ANENABLE) {
2919                         u32 phy1, phy2;
2920
2921                         /* Select shadow register 0x1f */
2922                         tg3_writephy(tp, 0x1c, 0x7c00);
2923                         tg3_readphy(tp, 0x1c, &phy1);
2924
2925                         /* Select expansion interrupt status register */
2926                         tg3_writephy(tp, 0x17, 0x0f01);
2927                         tg3_readphy(tp, 0x15, &phy2);
2928                         tg3_readphy(tp, 0x15, &phy2);
2929
2930                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2931                                 /* We have signal detect and not receiving
2932                                  * config code words, link is up by parallel
2933                                  * detection.
2934                                  */
2935
2936                                 bmcr &= ~BMCR_ANENABLE;
2937                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2938                                 tg3_writephy(tp, MII_BMCR, bmcr);
2939                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2940                         }
2941                 }
2942         }
2943         else if (netif_carrier_ok(tp->dev) &&
2944                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2945                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2946                 u32 phy2;
2947
2948                 /* Select expansion interrupt status register */
2949                 tg3_writephy(tp, 0x17, 0x0f01);
2950                 tg3_readphy(tp, 0x15, &phy2);
2951                 if (phy2 & 0x20) {
2952                         u32 bmcr;
2953
2954                         /* Config code words received, turn on autoneg. */
2955                         tg3_readphy(tp, MII_BMCR, &bmcr);
2956                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2957
2958                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2959
2960                 }
2961         }
2962 }
2963
2964 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2965 {
2966         int err;
2967
2968         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2969                 err = tg3_setup_fiber_phy(tp, force_reset);
2970         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2971                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2972         } else {
2973                 err = tg3_setup_copper_phy(tp, force_reset);
2974         }
2975
2976         if (tp->link_config.active_speed == SPEED_1000 &&
2977             tp->link_config.active_duplex == DUPLEX_HALF)
2978                 tw32(MAC_TX_LENGTHS,
2979                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2980                       (6 << TX_LENGTHS_IPG_SHIFT) |
2981                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2982         else
2983                 tw32(MAC_TX_LENGTHS,
2984                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2985                       (6 << TX_LENGTHS_IPG_SHIFT) |
2986                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2987
2988         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2989                 if (netif_carrier_ok(tp->dev)) {
2990                         tw32(HOSTCC_STAT_COAL_TICKS,
2991                              tp->coal.stats_block_coalesce_usecs);
2992                 } else {
2993                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2994                 }
2995         }
2996
2997         return err;
2998 }
2999
3000 /* This is called whenever we suspect that the system chipset is re-
3001  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3002  * is bogus tx completions. We try to recover by setting the
3003  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3004  * in the workqueue.
3005  */
3006 static void tg3_tx_recover(struct tg3 *tp)
3007 {
3008         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3009                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3010
3011         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3012                "mapped I/O cycles to the network device, attempting to "
3013                "recover. Please report the problem to the driver maintainer "
3014                "and include system chipset information.\n", tp->dev->name);
3015
3016         spin_lock(&tp->lock);
3017         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3018         spin_unlock(&tp->lock);
3019 }
3020
3021 static inline u32 tg3_tx_avail(struct tg3 *tp)
3022 {
3023         smp_mb();
3024         return (tp->tx_pending -
3025                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3026 }
3027
3028 /* Tigon3 never reports partial packet sends.  So we do not
3029  * need special logic to handle SKBs that have not had all
3030  * of their frags sent yet, like SunGEM does.
3031  */
3032 static void tg3_tx(struct tg3 *tp)
3033 {
3034         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3035         u32 sw_idx = tp->tx_cons;
3036
3037         while (sw_idx != hw_idx) {
3038                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3039                 struct sk_buff *skb = ri->skb;
3040                 int i, tx_bug = 0;
3041
3042                 if (unlikely(skb == NULL)) {
3043                         tg3_tx_recover(tp);
3044                         return;
3045                 }
3046
3047                 pci_unmap_single(tp->pdev,
3048                                  pci_unmap_addr(ri, mapping),
3049                                  skb_headlen(skb),
3050                                  PCI_DMA_TODEVICE);
3051
3052                 ri->skb = NULL;
3053
3054                 sw_idx = NEXT_TX(sw_idx);
3055
3056                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3057                         ri = &tp->tx_buffers[sw_idx];
3058                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3059                                 tx_bug = 1;
3060
3061                         pci_unmap_page(tp->pdev,
3062                                        pci_unmap_addr(ri, mapping),
3063                                        skb_shinfo(skb)->frags[i].size,
3064                                        PCI_DMA_TODEVICE);
3065
3066                         sw_idx = NEXT_TX(sw_idx);
3067                 }
3068
3069                 dev_kfree_skb(skb);
3070
3071                 if (unlikely(tx_bug)) {
3072                         tg3_tx_recover(tp);
3073                         return;
3074                 }
3075         }
3076
3077         tp->tx_cons = sw_idx;
3078
3079         /* Need to make the tx_cons update visible to tg3_start_xmit()
3080          * before checking for netif_queue_stopped().  Without the
3081          * memory barrier, there is a small possibility that tg3_start_xmit()
3082          * will miss it and cause the queue to be stopped forever.
3083          */
3084         smp_mb();
3085
3086         if (unlikely(netif_queue_stopped(tp->dev) &&
3087                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3088                 netif_tx_lock(tp->dev);
3089                 if (netif_queue_stopped(tp->dev) &&
3090                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3091                         netif_wake_queue(tp->dev);
3092                 netif_tx_unlock(tp->dev);
3093         }
3094 }
3095
3096 /* Returns size of skb allocated or < 0 on error.
3097  *
3098  * We only need to fill in the address because the other members
3099  * of the RX descriptor are invariant, see tg3_init_rings.
3100  *
3101  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3102  * posting buffers we only dirty the first cache line of the RX
3103  * descriptor (containing the address).  Whereas for the RX status
3104  * buffers the cpu only reads the last cacheline of the RX descriptor
3105  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3106  */
3107 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3108                             int src_idx, u32 dest_idx_unmasked)
3109 {
3110         struct tg3_rx_buffer_desc *desc;
3111         struct ring_info *map, *src_map;
3112         struct sk_buff *skb;
3113         dma_addr_t mapping;
3114         int skb_size, dest_idx;
3115
3116         src_map = NULL;
3117         switch (opaque_key) {
3118         case RXD_OPAQUE_RING_STD:
3119                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3120                 desc = &tp->rx_std[dest_idx];
3121                 map = &tp->rx_std_buffers[dest_idx];
3122                 if (src_idx >= 0)
3123                         src_map = &tp->rx_std_buffers[src_idx];
3124                 skb_size = tp->rx_pkt_buf_sz;
3125                 break;
3126
3127         case RXD_OPAQUE_RING_JUMBO:
3128                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3129                 desc = &tp->rx_jumbo[dest_idx];
3130                 map = &tp->rx_jumbo_buffers[dest_idx];
3131                 if (src_idx >= 0)
3132                         src_map = &tp->rx_jumbo_buffers[src_idx];
3133                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3134                 break;
3135
3136         default:
3137                 return -EINVAL;
3138         };
3139
3140         /* Do not overwrite any of the map or rp information
3141          * until we are sure we can commit to a new buffer.
3142          *
3143          * Callers depend upon this behavior and assume that
3144          * we leave everything unchanged if we fail.
3145          */
3146         skb = netdev_alloc_skb(tp->dev, skb_size);
3147         if (skb == NULL)
3148                 return -ENOMEM;
3149
3150         skb_reserve(skb, tp->rx_offset);
3151
3152         mapping = pci_map_single(tp->pdev, skb->data,
3153                                  skb_size - tp->rx_offset,
3154                                  PCI_DMA_FROMDEVICE);
3155
3156         map->skb = skb;
3157         pci_unmap_addr_set(map, mapping, mapping);
3158
3159         if (src_map != NULL)
3160                 src_map->skb = NULL;
3161
3162         desc->addr_hi = ((u64)mapping >> 32);
3163         desc->addr_lo = ((u64)mapping & 0xffffffff);
3164
3165         return skb_size;
3166 }
3167
3168 /* We only need to move over in the address because the other
3169  * members of the RX descriptor are invariant.  See notes above
3170  * tg3_alloc_rx_skb for full details.
3171  */
3172 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3173                            int src_idx, u32 dest_idx_unmasked)
3174 {
3175         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3176         struct ring_info *src_map, *dest_map;
3177         int dest_idx;
3178
3179         switch (opaque_key) {
3180         case RXD_OPAQUE_RING_STD:
3181                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3182                 dest_desc = &tp->rx_std[dest_idx];
3183                 dest_map = &tp->rx_std_buffers[dest_idx];
3184                 src_desc = &tp->rx_std[src_idx];
3185                 src_map = &tp->rx_std_buffers[src_idx];
3186                 break;
3187
3188         case RXD_OPAQUE_RING_JUMBO:
3189                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3190                 dest_desc = &tp->rx_jumbo[dest_idx];
3191                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3192                 src_desc = &tp->rx_jumbo[src_idx];
3193                 src_map = &tp->rx_jumbo_buffers[src_idx];
3194                 break;
3195
3196         default:
3197                 return;
3198         };
3199
3200         dest_map->skb = src_map->skb;
3201         pci_unmap_addr_set(dest_map, mapping,
3202                            pci_unmap_addr(src_map, mapping));
3203         dest_desc->addr_hi = src_desc->addr_hi;
3204         dest_desc->addr_lo = src_desc->addr_lo;
3205
3206         src_map->skb = NULL;
3207 }
3208
3209 #if TG3_VLAN_TAG_USED
3210 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3211 {
3212         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3213 }
3214 #endif
3215
3216 /* The RX ring scheme is composed of multiple rings which post fresh
3217  * buffers to the chip, and one special ring the chip uses to report
3218  * status back to the host.
3219  *
3220  * The special ring reports the status of received packets to the
3221  * host.  The chip does not write into the original descriptor the
3222  * RX buffer was obtained from.  The chip simply takes the original
3223  * descriptor as provided by the host, updates the status and length
3224  * field, then writes this into the next status ring entry.
3225  *
3226  * Each ring the host uses to post buffers to the chip is described
3227  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3228  * it is first placed into the on-chip ram.  When the packet's length
3229  * is known, it walks down the TG3_BDINFO entries to select the ring.
3230  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3231  * which is within the range of the new packet's length is chosen.
3232  *
3233  * The "separate ring for rx status" scheme may sound queer, but it makes
3234  * sense from a cache coherency perspective.  If only the host writes
3235  * to the buffer post rings, and only the chip writes to the rx status
3236  * rings, then cache lines never move beyond shared-modified state.
3237  * If both the host and chip were to write into the same ring, cache line
3238  * eviction could occur since both entities want it in an exclusive state.
3239  */
3240 static int tg3_rx(struct tg3 *tp, int budget)
3241 {
3242         u32 work_mask, rx_std_posted = 0;
3243         u32 sw_idx = tp->rx_rcb_ptr;
3244         u16 hw_idx;
3245         int received;
3246
3247         hw_idx = tp->hw_status->idx[0].rx_producer;
3248         /*
3249          * We need to order the read of hw_idx and the read of
3250          * the opaque cookie.
3251          */
3252         rmb();
3253         work_mask = 0;
3254         received = 0;
3255         while (sw_idx != hw_idx && budget > 0) {
3256                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3257                 unsigned int len;
3258                 struct sk_buff *skb;
3259                 dma_addr_t dma_addr;
3260                 u32 opaque_key, desc_idx, *post_ptr;
3261
3262                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3263                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3264                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3265                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3266                                                   mapping);
3267                         skb = tp->rx_std_buffers[desc_idx].skb;
3268                         post_ptr = &tp->rx_std_ptr;
3269                         rx_std_posted++;
3270                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3271                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3272                                                   mapping);
3273                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3274                         post_ptr = &tp->rx_jumbo_ptr;
3275                 }
3276                 else {
3277                         goto next_pkt_nopost;
3278                 }
3279
3280                 work_mask |= opaque_key;
3281
3282                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3283                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3284                 drop_it:
3285                         tg3_recycle_rx(tp, opaque_key,
3286                                        desc_idx, *post_ptr);
3287                 drop_it_no_recycle:
3288                         /* Other statistics kept track of by card. */
3289                         tp->net_stats.rx_dropped++;
3290                         goto next_pkt;
3291                 }
3292
3293                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3294
3295                 if (len > RX_COPY_THRESHOLD
3296                         && tp->rx_offset == 2
3297                         /* rx_offset != 2 iff this is a 5701 card running
3298                          * in PCI-X mode [see tg3_get_invariants()] */
3299                 ) {
3300                         int skb_size;
3301
3302                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3303                                                     desc_idx, *post_ptr);
3304                         if (skb_size < 0)
3305                                 goto drop_it;
3306
3307                         pci_unmap_single(tp->pdev, dma_addr,
3308                                          skb_size - tp->rx_offset,
3309                                          PCI_DMA_FROMDEVICE);
3310
3311                         skb_put(skb, len);
3312                 } else {
3313                         struct sk_buff *copy_skb;
3314
3315                         tg3_recycle_rx(tp, opaque_key,
3316                                        desc_idx, *post_ptr);
3317
3318                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3319                         if (copy_skb == NULL)
3320                                 goto drop_it_no_recycle;
3321
3322                         skb_reserve(copy_skb, 2);
3323                         skb_put(copy_skb, len);
3324                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3325                         memcpy(copy_skb->data, skb->data, len);
3326                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3327
3328                         /* We'll reuse the original ring buffer. */
3329                         skb = copy_skb;
3330                 }
3331
3332                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3333                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3334                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3335                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3336                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3337                 else
3338                         skb->ip_summed = CHECKSUM_NONE;
3339
3340                 skb->protocol = eth_type_trans(skb, tp->dev);
3341 #if TG3_VLAN_TAG_USED
3342                 if (tp->vlgrp != NULL &&
3343                     desc->type_flags & RXD_FLAG_VLAN) {
3344                         tg3_vlan_rx(tp, skb,
3345                                     desc->err_vlan & RXD_VLAN_MASK);
3346                 } else
3347 #endif
3348                         netif_receive_skb(skb);
3349
3350                 tp->dev->last_rx = jiffies;
3351                 received++;
3352                 budget--;
3353
3354 next_pkt:
3355                 (*post_ptr)++;
3356
3357                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3358                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3359
3360                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3361                                      TG3_64BIT_REG_LOW, idx);
3362                         work_mask &= ~RXD_OPAQUE_RING_STD;
3363                         rx_std_posted = 0;
3364                 }
3365 next_pkt_nopost:
3366                 sw_idx++;
3367                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3368
3369                 /* Refresh hw_idx to see if there is new work */
3370                 if (sw_idx == hw_idx) {
3371                         hw_idx = tp->hw_status->idx[0].rx_producer;
3372                         rmb();
3373                 }
3374         }
3375
3376         /* ACK the status ring. */
3377         tp->rx_rcb_ptr = sw_idx;
3378         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3379
3380         /* Refill RX ring(s). */
3381         if (work_mask & RXD_OPAQUE_RING_STD) {
3382                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3383                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3384                              sw_idx);
3385         }
3386         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3387                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3388                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3389                              sw_idx);
3390         }
3391         mmiowb();
3392
3393         return received;
3394 }
3395
3396 static int tg3_poll(struct net_device *netdev, int *budget)
3397 {
3398         struct tg3 *tp = netdev_priv(netdev);
3399         struct tg3_hw_status *sblk = tp->hw_status;
3400         int done;
3401
3402         /* handle link change and other phy events */
3403         if (!(tp->tg3_flags &
3404               (TG3_FLAG_USE_LINKCHG_REG |
3405                TG3_FLAG_POLL_SERDES))) {
3406                 if (sblk->status & SD_STATUS_LINK_CHG) {
3407                         sblk->status = SD_STATUS_UPDATED |
3408                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3409                         spin_lock(&tp->lock);
3410                         tg3_setup_phy(tp, 0);
3411                         spin_unlock(&tp->lock);
3412                 }
3413         }
3414
3415         /* run TX completion thread */
3416         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3417                 tg3_tx(tp);
3418                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3419                         netif_rx_complete(netdev);
3420                         schedule_work(&tp->reset_task);
3421                         return 0;
3422                 }
3423         }
3424
3425         /* run RX thread, within the bounds set by NAPI.
3426          * All RX "locking" is done by ensuring outside
3427          * code synchronizes with dev->poll()
3428          */
3429         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3430                 int orig_budget = *budget;
3431                 int work_done;
3432
3433                 if (orig_budget > netdev->quota)
3434                         orig_budget = netdev->quota;
3435
3436                 work_done = tg3_rx(tp, orig_budget);
3437
3438                 *budget -= work_done;
3439                 netdev->quota -= work_done;
3440         }
3441
3442         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3443                 tp->last_tag = sblk->status_tag;
3444                 rmb();
3445         } else
3446                 sblk->status &= ~SD_STATUS_UPDATED;
3447
3448         /* if no more work, tell net stack and NIC we're done */
3449         done = !tg3_has_work(tp);
3450         if (done) {
3451                 netif_rx_complete(netdev);
3452                 tg3_restart_ints(tp);
3453         }
3454
3455         return (done ? 0 : 1);
3456 }
3457
3458 static void tg3_irq_quiesce(struct tg3 *tp)
3459 {
3460         BUG_ON(tp->irq_sync);
3461
3462         tp->irq_sync = 1;
3463         smp_mb();
3464
3465         synchronize_irq(tp->pdev->irq);
3466 }
3467
3468 static inline int tg3_irq_sync(struct tg3 *tp)
3469 {
3470         return tp->irq_sync;
3471 }
3472
3473 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3474  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3475  * with as well.  Most of the time, this is not necessary except when
3476  * shutting down the device.
3477  */
3478 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3479 {
3480         if (irq_sync)
3481                 tg3_irq_quiesce(tp);
3482         spin_lock_bh(&tp->lock);
3483 }
3484
3485 static inline void tg3_full_unlock(struct tg3 *tp)
3486 {
3487         spin_unlock_bh(&tp->lock);
3488 }
3489
3490 /* One-shot MSI handler - Chip automatically disables interrupt
3491  * after sending MSI so driver doesn't have to do it.
3492  */
3493 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3494 {
3495         struct net_device *dev = dev_id;
3496         struct tg3 *tp = netdev_priv(dev);
3497
3498         prefetch(tp->hw_status);
3499         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3500
3501         if (likely(!tg3_irq_sync(tp)))
3502                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3503
3504         return IRQ_HANDLED;
3505 }
3506
3507 /* MSI ISR - No need to check for interrupt sharing and no need to
3508  * flush status block and interrupt mailbox. PCI ordering rules
3509  * guarantee that MSI will arrive after the status block.
3510  */
3511 static irqreturn_t tg3_msi(int irq, void *dev_id)
3512 {
3513         struct net_device *dev = dev_id;
3514         struct tg3 *tp = netdev_priv(dev);
3515
3516         prefetch(tp->hw_status);
3517         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3518         /*
3519          * Writing any value to intr-mbox-0 clears PCI INTA# and
3520          * chip-internal interrupt pending events.
3521          * Writing non-zero to intr-mbox-0 additional tells the
3522          * NIC to stop sending us irqs, engaging "in-intr-handler"
3523          * event coalescing.
3524          */
3525         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3526         if (likely(!tg3_irq_sync(tp)))
3527                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3528
3529         return IRQ_RETVAL(1);
3530 }
3531
3532 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3533 {
3534         struct net_device *dev = dev_id;
3535         struct tg3 *tp = netdev_priv(dev);
3536         struct tg3_hw_status *sblk = tp->hw_status;
3537         unsigned int handled = 1;
3538
3539         /* In INTx mode, it is possible for the interrupt to arrive at
3540          * the CPU before the status block posted prior to the interrupt.
3541          * Reading the PCI State register will confirm whether the
3542          * interrupt is ours and will flush the status block.
3543          */
3544         if ((sblk->status & SD_STATUS_UPDATED) ||
3545             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3546                 /*
3547                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3548                  * chip-internal interrupt pending events.
3549                  * Writing non-zero to intr-mbox-0 additional tells the
3550                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3551                  * event coalescing.
3552                  */
3553                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3554                              0x00000001);
3555                 if (tg3_irq_sync(tp))
3556                         goto out;
3557                 sblk->status &= ~SD_STATUS_UPDATED;
3558                 if (likely(tg3_has_work(tp))) {
3559                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3560                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3561                 } else {
3562                         /* No work, shared interrupt perhaps?  re-enable
3563                          * interrupts, and flush that PCI write
3564                          */
3565                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3566                                 0x00000000);
3567                 }
3568         } else {        /* shared interrupt */
3569                 handled = 0;
3570         }
3571 out:
3572         return IRQ_RETVAL(handled);
3573 }
3574
3575 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3576 {
3577         struct net_device *dev = dev_id;
3578         struct tg3 *tp = netdev_priv(dev);
3579         struct tg3_hw_status *sblk = tp->hw_status;
3580         unsigned int handled = 1;
3581
3582         /* In INTx mode, it is possible for the interrupt to arrive at
3583          * the CPU before the status block posted prior to the interrupt.
3584          * Reading the PCI State register will confirm whether the
3585          * interrupt is ours and will flush the status block.
3586          */
3587         if ((sblk->status_tag != tp->last_tag) ||
3588             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3589                 /*
3590                  * writing any value to intr-mbox-0 clears PCI INTA# and
3591                  * chip-internal interrupt pending events.
3592                  * writing non-zero to intr-mbox-0 additional tells the
3593                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3594                  * event coalescing.
3595                  */
3596                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3597                              0x00000001);
3598                 if (tg3_irq_sync(tp))
3599                         goto out;
3600                 if (netif_rx_schedule_prep(dev)) {
3601                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3602                         /* Update last_tag to mark that this status has been
3603                          * seen. Because interrupt may be shared, we may be
3604                          * racing with tg3_poll(), so only update last_tag
3605                          * if tg3_poll() is not scheduled.
3606                          */
3607                         tp->last_tag = sblk->status_tag;
3608                         __netif_rx_schedule(dev);
3609                 }
3610         } else {        /* shared interrupt */
3611                 handled = 0;
3612         }
3613 out:
3614         return IRQ_RETVAL(handled);
3615 }
3616
3617 /* ISR for interrupt test */
3618 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3619 {
3620         struct net_device *dev = dev_id;
3621         struct tg3 *tp = netdev_priv(dev);
3622         struct tg3_hw_status *sblk = tp->hw_status;
3623
3624         if ((sblk->status & SD_STATUS_UPDATED) ||
3625             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3626                 tg3_disable_ints(tp);
3627                 return IRQ_RETVAL(1);
3628         }
3629         return IRQ_RETVAL(0);
3630 }
3631
3632 static int tg3_init_hw(struct tg3 *, int);
3633 static int tg3_halt(struct tg3 *, int, int);
3634
3635 /* Restart hardware after configuration changes, self-test, etc.
3636  * Invoked with tp->lock held.
3637  */
3638 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3639 {
3640         int err;
3641
3642         err = tg3_init_hw(tp, reset_phy);
3643         if (err) {
3644                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3645                        "aborting.\n", tp->dev->name);
3646                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3647                 tg3_full_unlock(tp);
3648                 del_timer_sync(&tp->timer);
3649                 tp->irq_sync = 0;
3650                 netif_poll_enable(tp->dev);
3651                 dev_close(tp->dev);
3652                 tg3_full_lock(tp, 0);
3653         }
3654         return err;
3655 }
3656
3657 #ifdef CONFIG_NET_POLL_CONTROLLER
3658 static void tg3_poll_controller(struct net_device *dev)
3659 {
3660         struct tg3 *tp = netdev_priv(dev);
3661
3662         tg3_interrupt(tp->pdev->irq, dev);
3663 }
3664 #endif
3665
3666 static void tg3_reset_task(struct work_struct *work)
3667 {
3668         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3669         unsigned int restart_timer;
3670
3671         tg3_full_lock(tp, 0);
3672         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3673
3674         if (!netif_running(tp->dev)) {
3675                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3676                 tg3_full_unlock(tp);
3677                 return;
3678         }
3679
3680         tg3_full_unlock(tp);
3681
3682         tg3_netif_stop(tp);
3683
3684         tg3_full_lock(tp, 1);
3685
3686         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3687         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3688
3689         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3690                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3691                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3692                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3693                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3694         }
3695
3696         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3697         if (tg3_init_hw(tp, 1))
3698                 goto out;
3699
3700         tg3_netif_start(tp);
3701
3702         if (restart_timer)
3703                 mod_timer(&tp->timer, jiffies + 1);
3704
3705 out:
3706         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3707
3708         tg3_full_unlock(tp);
3709 }
3710
3711 static void tg3_tx_timeout(struct net_device *dev)
3712 {
3713         struct tg3 *tp = netdev_priv(dev);
3714
3715         if (netif_msg_tx_err(tp))
3716                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3717                        dev->name);
3718
3719         schedule_work(&tp->reset_task);
3720 }
3721
3722 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3723 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3724 {
3725         u32 base = (u32) mapping & 0xffffffff;
3726
3727         return ((base > 0xffffdcc0) &&
3728                 (base + len + 8 < base));
3729 }
3730
3731 /* Test for DMA addresses > 40-bit */
3732 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3733                                           int len)
3734 {
3735 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3736         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3737                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3738         return 0;
3739 #else
3740         return 0;
3741 #endif
3742 }
3743
3744 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3745
3746 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3747 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3748                                        u32 last_plus_one, u32 *start,
3749                                        u32 base_flags, u32 mss)
3750 {
3751         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3752         dma_addr_t new_addr = 0;
3753         u32 entry = *start;
3754         int i, ret = 0;
3755
3756         if (!new_skb) {
3757                 ret = -1;
3758         } else {
3759                 /* New SKB is guaranteed to be linear. */
3760                 entry = *start;
3761                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3762                                           PCI_DMA_TODEVICE);
3763                 /* Make sure new skb does not cross any 4G boundaries.
3764                  * Drop the packet if it does.
3765                  */
3766                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3767                         ret = -1;
3768                         dev_kfree_skb(new_skb);
3769                         new_skb = NULL;
3770                 } else {
3771                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3772                                     base_flags, 1 | (mss << 1));
3773                         *start = NEXT_TX(entry);
3774                 }
3775         }
3776
3777         /* Now clean up the sw ring entries. */
3778         i = 0;
3779         while (entry != last_plus_one) {
3780                 int len;
3781
3782                 if (i == 0)
3783                         len = skb_headlen(skb);
3784                 else
3785                         len = skb_shinfo(skb)->frags[i-1].size;
3786                 pci_unmap_single(tp->pdev,
3787                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3788                                  len, PCI_DMA_TODEVICE);
3789                 if (i == 0) {
3790                         tp->tx_buffers[entry].skb = new_skb;
3791                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3792                 } else {
3793                         tp->tx_buffers[entry].skb = NULL;
3794                 }
3795                 entry = NEXT_TX(entry);
3796                 i++;
3797         }
3798
3799         dev_kfree_skb(skb);
3800
3801         return ret;
3802 }
3803
3804 static void tg3_set_txd(struct tg3 *tp, int entry,
3805                         dma_addr_t mapping, int len, u32 flags,
3806                         u32 mss_and_is_end)
3807 {
3808         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3809         int is_end = (mss_and_is_end & 0x1);
3810         u32 mss = (mss_and_is_end >> 1);
3811         u32 vlan_tag = 0;
3812
3813         if (is_end)
3814                 flags |= TXD_FLAG_END;
3815         if (flags & TXD_FLAG_VLAN) {
3816                 vlan_tag = flags >> 16;
3817                 flags &= 0xffff;
3818         }
3819         vlan_tag |= (mss << TXD_MSS_SHIFT);
3820
3821         txd->addr_hi = ((u64) mapping >> 32);
3822         txd->addr_lo = ((u64) mapping & 0xffffffff);
3823         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3824         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3825 }
3826
3827 /* hard_start_xmit for devices that don't have any bugs and
3828  * support TG3_FLG2_HW_TSO_2 only.
3829  */
3830 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3831 {
3832         struct tg3 *tp = netdev_priv(dev);
3833         dma_addr_t mapping;
3834         u32 len, entry, base_flags, mss;
3835
3836         len = skb_headlen(skb);
3837
3838         /* We are running in BH disabled context with netif_tx_lock
3839          * and TX reclaim runs via tp->poll inside of a software
3840          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3841          * no IRQ context deadlocks to worry about either.  Rejoice!
3842          */
3843         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3844                 if (!netif_queue_stopped(dev)) {
3845                         netif_stop_queue(dev);
3846
3847                         /* This is a hard error, log it. */
3848                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3849                                "queue awake!\n", dev->name);
3850                 }
3851                 return NETDEV_TX_BUSY;
3852         }
3853
3854         entry = tp->tx_prod;
3855         base_flags = 0;
3856 #if TG3_TSO_SUPPORT != 0
3857         mss = 0;
3858         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3859             (mss = skb_shinfo(skb)->gso_size) != 0) {
3860                 int tcp_opt_len, ip_tcp_len;
3861
3862                 if (skb_header_cloned(skb) &&
3863                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3864                         dev_kfree_skb(skb);
3865                         goto out_unlock;
3866                 }
3867
3868                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3869                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3870                 else {
3871                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3872                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3873                                      sizeof(struct tcphdr);
3874
3875                         skb->nh.iph->check = 0;
3876                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3877                                                      tcp_opt_len);
3878                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3879                 }
3880
3881                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3882                                TXD_FLAG_CPU_POST_DMA);
3883
3884                 skb->h.th->check = 0;
3885
3886         }
3887         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3888                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3889 #else
3890         mss = 0;
3891         if (skb->ip_summed == CHECKSUM_PARTIAL)
3892                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3893 #endif
3894 #if TG3_VLAN_TAG_USED
3895         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3896                 base_flags |= (TXD_FLAG_VLAN |
3897                                (vlan_tx_tag_get(skb) << 16));
3898 #endif
3899
3900         /* Queue skb data, a.k.a. the main skb fragment. */
3901         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3902
3903         tp->tx_buffers[entry].skb = skb;
3904         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3905
3906         tg3_set_txd(tp, entry, mapping, len, base_flags,
3907                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3908
3909         entry = NEXT_TX(entry);
3910
3911         /* Now loop through additional data fragments, and queue them. */
3912         if (skb_shinfo(skb)->nr_frags > 0) {
3913                 unsigned int i, last;
3914
3915                 last = skb_shinfo(skb)->nr_frags - 1;
3916                 for (i = 0; i <= last; i++) {
3917                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3918
3919                         len = frag->size;
3920                         mapping = pci_map_page(tp->pdev,
3921                                                frag->page,
3922                                                frag->page_offset,
3923                                                len, PCI_DMA_TODEVICE);
3924
3925                         tp->tx_buffers[entry].skb = NULL;
3926                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3927
3928                         tg3_set_txd(tp, entry, mapping, len,
3929                                     base_flags, (i == last) | (mss << 1));
3930
3931                         entry = NEXT_TX(entry);
3932                 }
3933         }
3934
3935         /* Packets are ready, update Tx producer idx local and on card. */
3936         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3937
3938         tp->tx_prod = entry;
3939         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3940                 netif_stop_queue(dev);
3941                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3942                         netif_wake_queue(tp->dev);
3943         }
3944
3945 out_unlock:
3946         mmiowb();
3947
3948         dev->trans_start = jiffies;
3949
3950         return NETDEV_TX_OK;
3951 }
3952
3953 #if TG3_TSO_SUPPORT != 0
3954 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3955
3956 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3957  * TSO header is greater than 80 bytes.
3958  */
3959 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3960 {
3961         struct sk_buff *segs, *nskb;
3962
3963         /* Estimate the number of fragments in the worst case */
3964         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3965                 netif_stop_queue(tp->dev);
3966                 return NETDEV_TX_BUSY;
3967         }
3968
3969         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3970         if (unlikely(IS_ERR(segs)))
3971                 goto tg3_tso_bug_end;
3972
3973         do {
3974                 nskb = segs;
3975                 segs = segs->next;
3976                 nskb->next = NULL;
3977                 tg3_start_xmit_dma_bug(nskb, tp->dev);
3978         } while (segs);
3979
3980 tg3_tso_bug_end:
3981         dev_kfree_skb(skb);
3982
3983         return NETDEV_TX_OK;
3984 }
3985 #endif
3986
3987 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3988  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3989  */
3990 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3991 {
3992         struct tg3 *tp = netdev_priv(dev);
3993         dma_addr_t mapping;
3994         u32 len, entry, base_flags, mss;
3995         int would_hit_hwbug;
3996
3997         len = skb_headlen(skb);
3998
3999         /* We are running in BH disabled context with netif_tx_lock
4000          * and TX reclaim runs via tp->poll inside of a software
4001          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4002          * no IRQ context deadlocks to worry about either.  Rejoice!
4003          */
4004         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4005                 if (!netif_queue_stopped(dev)) {
4006                         netif_stop_queue(dev);
4007
4008                         /* This is a hard error, log it. */
4009                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4010                                "queue awake!\n", dev->name);
4011                 }
4012                 return NETDEV_TX_BUSY;
4013         }
4014
4015         entry = tp->tx_prod;
4016         base_flags = 0;
4017         if (skb->ip_summed == CHECKSUM_PARTIAL)
4018                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4019 #if TG3_TSO_SUPPORT != 0
4020         mss = 0;
4021         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4022             (mss = skb_shinfo(skb)->gso_size) != 0) {
4023                 int tcp_opt_len, ip_tcp_len, hdr_len;
4024
4025                 if (skb_header_cloned(skb) &&
4026                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4027                         dev_kfree_skb(skb);
4028                         goto out_unlock;
4029                 }
4030
4031                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4032                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4033
4034                 hdr_len = ip_tcp_len + tcp_opt_len;
4035                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4036                              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4037                         return (tg3_tso_bug(tp, skb));
4038
4039                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4040                                TXD_FLAG_CPU_POST_DMA);
4041
4042                 skb->nh.iph->check = 0;
4043                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4044                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4045                         skb->h.th->check = 0;
4046                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4047                 }
4048                 else {
4049                         skb->h.th->check =
4050                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4051                                                    skb->nh.iph->daddr,
4052                                                    0, IPPROTO_TCP, 0);
4053                 }
4054
4055                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4056                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4057                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4058                                 int tsflags;
4059
4060                                 tsflags = ((skb->nh.iph->ihl - 5) +
4061                                            (tcp_opt_len >> 2));
4062                                 mss |= (tsflags << 11);
4063                         }
4064                 } else {
4065                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4066                                 int tsflags;
4067
4068                                 tsflags = ((skb->nh.iph->ihl - 5) +
4069                                            (tcp_opt_len >> 2));
4070                                 base_flags |= tsflags << 12;
4071                         }
4072                 }
4073         }
4074 #else
4075         mss = 0;
4076 #endif
4077 #if TG3_VLAN_TAG_USED
4078         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4079                 base_flags |= (TXD_FLAG_VLAN |
4080                                (vlan_tx_tag_get(skb) << 16));
4081 #endif
4082
4083         /* Queue skb data, a.k.a. the main skb fragment. */
4084         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4085
4086         tp->tx_buffers[entry].skb = skb;
4087         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4088
4089         would_hit_hwbug = 0;
4090
4091         if (tg3_4g_overflow_test(mapping, len))
4092                 would_hit_hwbug = 1;
4093
4094         tg3_set_txd(tp, entry, mapping, len, base_flags,
4095                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4096
4097         entry = NEXT_TX(entry);
4098
4099         /* Now loop through additional data fragments, and queue them. */
4100         if (skb_shinfo(skb)->nr_frags > 0) {
4101                 unsigned int i, last;
4102
4103                 last = skb_shinfo(skb)->nr_frags - 1;
4104                 for (i = 0; i <= last; i++) {
4105                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4106
4107                         len = frag->size;
4108                         mapping = pci_map_page(tp->pdev,
4109                                                frag->page,
4110                                                frag->page_offset,
4111                                                len, PCI_DMA_TODEVICE);
4112
4113                         tp->tx_buffers[entry].skb = NULL;
4114                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4115
4116                         if (tg3_4g_overflow_test(mapping, len))
4117                                 would_hit_hwbug = 1;
4118
4119                         if (tg3_40bit_overflow_test(tp, mapping, len))
4120                                 would_hit_hwbug = 1;
4121
4122                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4123                                 tg3_set_txd(tp, entry, mapping, len,
4124                                             base_flags, (i == last)|(mss << 1));
4125                         else
4126                                 tg3_set_txd(tp, entry, mapping, len,
4127                                             base_flags, (i == last));
4128
4129                         entry = NEXT_TX(entry);
4130                 }
4131         }
4132
4133         if (would_hit_hwbug) {
4134                 u32 last_plus_one = entry;
4135                 u32 start;
4136
4137                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4138                 start &= (TG3_TX_RING_SIZE - 1);
4139
4140                 /* If the workaround fails due to memory/mapping
4141                  * failure, silently drop this packet.
4142                  */
4143                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4144                                                 &start, base_flags, mss))
4145                         goto out_unlock;
4146
4147                 entry = start;
4148         }
4149
4150         /* Packets are ready, update Tx producer idx local and on card. */
4151         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4152
4153         tp->tx_prod = entry;
4154         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4155                 netif_stop_queue(dev);
4156                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4157                         netif_wake_queue(tp->dev);
4158         }
4159
4160 out_unlock:
4161         mmiowb();
4162
4163         dev->trans_start = jiffies;
4164
4165         return NETDEV_TX_OK;
4166 }
4167
4168 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4169                                int new_mtu)
4170 {
4171         dev->mtu = new_mtu;
4172
4173         if (new_mtu > ETH_DATA_LEN) {
4174                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4175                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4176                         ethtool_op_set_tso(dev, 0);
4177                 }
4178                 else
4179                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4180         } else {
4181                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4182                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4183                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4184         }
4185 }
4186
4187 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4188 {
4189         struct tg3 *tp = netdev_priv(dev);
4190         int err;
4191
4192         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4193                 return -EINVAL;
4194
4195         if (!netif_running(dev)) {
4196                 /* We'll just catch it later when the
4197                  * device is up'd.
4198                  */
4199                 tg3_set_mtu(dev, tp, new_mtu);
4200                 return 0;
4201         }
4202
4203         tg3_netif_stop(tp);
4204
4205         tg3_full_lock(tp, 1);
4206
4207         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4208
4209         tg3_set_mtu(dev, tp, new_mtu);
4210
4211         err = tg3_restart_hw(tp, 0);
4212
4213         if (!err)
4214                 tg3_netif_start(tp);
4215
4216         tg3_full_unlock(tp);
4217
4218         return err;
4219 }
4220
4221 /* Free up pending packets in all rx/tx rings.
4222  *
4223  * The chip has been shut down and the driver detached from
4224  * the networking, so no interrupts or new tx packets will
4225  * end up in the driver.  tp->{tx,}lock is not held and we are not
4226  * in an interrupt context and thus may sleep.
4227  */
4228 static void tg3_free_rings(struct tg3 *tp)
4229 {
4230         struct ring_info *rxp;
4231         int i;
4232
4233         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4234                 rxp = &tp->rx_std_buffers[i];
4235
4236                 if (rxp->skb == NULL)
4237                         continue;
4238                 pci_unmap_single(tp->pdev,
4239                                  pci_unmap_addr(rxp, mapping),
4240                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4241                                  PCI_DMA_FROMDEVICE);
4242                 dev_kfree_skb_any(rxp->skb);
4243                 rxp->skb = NULL;
4244         }
4245
4246         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4247                 rxp = &tp->rx_jumbo_buffers[i];
4248
4249                 if (rxp->skb == NULL)
4250                         continue;
4251                 pci_unmap_single(tp->pdev,
4252                                  pci_unmap_addr(rxp, mapping),
4253                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4254                                  PCI_DMA_FROMDEVICE);
4255                 dev_kfree_skb_any(rxp->skb);
4256                 rxp->skb = NULL;
4257         }
4258
4259         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4260                 struct tx_ring_info *txp;
4261                 struct sk_buff *skb;
4262                 int j;
4263
4264                 txp = &tp->tx_buffers[i];
4265                 skb = txp->skb;
4266
4267                 if (skb == NULL) {
4268                         i++;
4269                         continue;
4270                 }
4271
4272                 pci_unmap_single(tp->pdev,
4273                                  pci_unmap_addr(txp, mapping),
4274                                  skb_headlen(skb),
4275                                  PCI_DMA_TODEVICE);
4276                 txp->skb = NULL;
4277
4278                 i++;
4279
4280                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4281                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4282                         pci_unmap_page(tp->pdev,
4283                                        pci_unmap_addr(txp, mapping),
4284                                        skb_shinfo(skb)->frags[j].size,
4285                                        PCI_DMA_TODEVICE);
4286                         i++;
4287                 }
4288
4289                 dev_kfree_skb_any(skb);
4290         }
4291 }
4292
4293 /* Initialize tx/rx rings for packet processing.
4294  *
4295  * The chip has been shut down and the driver detached from
4296  * the networking, so no interrupts or new tx packets will
4297  * end up in the driver.  tp->{tx,}lock are held and thus
4298  * we may not sleep.
4299  */
4300 static int tg3_init_rings(struct tg3 *tp)
4301 {
4302         u32 i;
4303
4304         /* Free up all the SKBs. */
4305         tg3_free_rings(tp);
4306
4307         /* Zero out all descriptors. */
4308         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4309         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4310         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4311         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4312
4313         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4314         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4315             (tp->dev->mtu > ETH_DATA_LEN))
4316                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4317
4318         /* Initialize invariants of the rings, we only set this
4319          * stuff once.  This works because the card does not
4320          * write into the rx buffer posting rings.
4321          */
4322         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4323                 struct tg3_rx_buffer_desc *rxd;
4324
4325                 rxd = &tp->rx_std[i];
4326                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4327                         << RXD_LEN_SHIFT;
4328                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4329                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4330                                (i << RXD_OPAQUE_INDEX_SHIFT));
4331         }
4332
4333         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4334                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4335                         struct tg3_rx_buffer_desc *rxd;
4336
4337                         rxd = &tp->rx_jumbo[i];
4338                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4339                                 << RXD_LEN_SHIFT;
4340                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4341                                 RXD_FLAG_JUMBO;
4342                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4343                                (i << RXD_OPAQUE_INDEX_SHIFT));
4344                 }
4345         }
4346
4347         /* Now allocate fresh SKBs for each rx ring. */
4348         for (i = 0; i < tp->rx_pending; i++) {
4349                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4350                         printk(KERN_WARNING PFX
4351                                "%s: Using a smaller RX standard ring, "
4352                                "only %d out of %d buffers were allocated "
4353                                "successfully.\n",
4354                                tp->dev->name, i, tp->rx_pending);
4355                         if (i == 0)
4356                                 return -ENOMEM;
4357                         tp->rx_pending = i;
4358                         break;
4359                 }
4360         }
4361
4362         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4363                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4364                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4365                                              -1, i) < 0) {
4366                                 printk(KERN_WARNING PFX
4367                                        "%s: Using a smaller RX jumbo ring, "
4368                                        "only %d out of %d buffers were "
4369                                        "allocated successfully.\n",
4370                                        tp->dev->name, i, tp->rx_jumbo_pending);
4371                                 if (i == 0) {
4372                                         tg3_free_rings(tp);
4373                                         return -ENOMEM;
4374                                 }
4375                                 tp->rx_jumbo_pending = i;
4376                                 break;
4377                         }
4378                 }
4379         }
4380         return 0;
4381 }
4382
4383 /*
4384  * Must not be invoked with interrupt sources disabled and
4385  * the hardware shutdown down.
4386  */
4387 static void tg3_free_consistent(struct tg3 *tp)
4388 {
4389         kfree(tp->rx_std_buffers);
4390         tp->rx_std_buffers = NULL;
4391         if (tp->rx_std) {
4392                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4393                                     tp->rx_std, tp->rx_std_mapping);
4394                 tp->rx_std = NULL;
4395         }
4396         if (tp->rx_jumbo) {
4397                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4398                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4399                 tp->rx_jumbo = NULL;
4400         }
4401         if (tp->rx_rcb) {
4402                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4403                                     tp->rx_rcb, tp->rx_rcb_mapping);
4404                 tp->rx_rcb = NULL;
4405         }
4406         if (tp->tx_ring) {
4407                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4408                         tp->tx_ring, tp->tx_desc_mapping);
4409                 tp->tx_ring = NULL;
4410         }
4411         if (tp->hw_status) {
4412                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4413                                     tp->hw_status, tp->status_mapping);
4414                 tp->hw_status = NULL;
4415         }
4416         if (tp->hw_stats) {
4417                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4418                                     tp->hw_stats, tp->stats_mapping);
4419                 tp->hw_stats = NULL;
4420         }
4421 }
4422
4423 /*
4424  * Must not be invoked with interrupt sources disabled and
4425  * the hardware shutdown down.  Can sleep.
4426  */
4427 static int tg3_alloc_consistent(struct tg3 *tp)
4428 {
4429         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4430                                       (TG3_RX_RING_SIZE +
4431                                        TG3_RX_JUMBO_RING_SIZE)) +
4432                                      (sizeof(struct tx_ring_info) *
4433                                       TG3_TX_RING_SIZE),
4434                                      GFP_KERNEL);
4435         if (!tp->rx_std_buffers)
4436                 return -ENOMEM;
4437
4438         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4439         tp->tx_buffers = (struct tx_ring_info *)
4440                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4441
4442         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4443                                           &tp->rx_std_mapping);
4444         if (!tp->rx_std)
4445                 goto err_out;
4446
4447         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4448                                             &tp->rx_jumbo_mapping);
4449
4450         if (!tp->rx_jumbo)
4451                 goto err_out;
4452
4453         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4454                                           &tp->rx_rcb_mapping);
4455         if (!tp->rx_rcb)
4456                 goto err_out;
4457
4458         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4459                                            &tp->tx_desc_mapping);
4460         if (!tp->tx_ring)
4461                 goto err_out;
4462
4463         tp->hw_status = pci_alloc_consistent(tp->pdev,
4464                                              TG3_HW_STATUS_SIZE,
4465                                              &tp->status_mapping);
4466         if (!tp->hw_status)
4467                 goto err_out;
4468
4469         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4470                                             sizeof(struct tg3_hw_stats),
4471                                             &tp->stats_mapping);
4472         if (!tp->hw_stats)
4473                 goto err_out;
4474
4475         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4476         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4477
4478         return 0;
4479
4480 err_out:
4481         tg3_free_consistent(tp);
4482         return -ENOMEM;
4483 }
4484
4485 #define MAX_WAIT_CNT 1000
4486
4487 /* To stop a block, clear the enable bit and poll till it
4488  * clears.  tp->lock is held.
4489  */
4490 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4491 {
4492         unsigned int i;
4493         u32 val;
4494
4495         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4496                 switch (ofs) {
4497                 case RCVLSC_MODE:
4498                 case DMAC_MODE:
4499                 case MBFREE_MODE:
4500                 case BUFMGR_MODE:
4501                 case MEMARB_MODE:
4502                         /* We can't enable/disable these bits of the
4503                          * 5705/5750, just say success.
4504                          */
4505                         return 0;
4506
4507                 default:
4508                         break;
4509                 };
4510         }
4511
4512         val = tr32(ofs);
4513         val &= ~enable_bit;
4514         tw32_f(ofs, val);
4515
4516         for (i = 0; i < MAX_WAIT_CNT; i++) {
4517                 udelay(100);
4518                 val = tr32(ofs);
4519                 if ((val & enable_bit) == 0)
4520                         break;
4521         }
4522
4523         if (i == MAX_WAIT_CNT && !silent) {
4524                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4525                        "ofs=%lx enable_bit=%x\n",
4526                        ofs, enable_bit);
4527                 return -ENODEV;
4528         }
4529
4530         return 0;
4531 }
4532
4533 /* tp->lock is held. */
4534 static int tg3_abort_hw(struct tg3 *tp, int silent)
4535 {
4536         int i, err;
4537
4538         tg3_disable_ints(tp);
4539
4540         tp->rx_mode &= ~RX_MODE_ENABLE;
4541         tw32_f(MAC_RX_MODE, tp->rx_mode);
4542         udelay(10);
4543
4544         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4545         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4546         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4547         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4548         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4549         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4550
4551         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4552         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4553         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4554         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4555         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4556         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4557         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4558
4559         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4560         tw32_f(MAC_MODE, tp->mac_mode);
4561         udelay(40);
4562
4563         tp->tx_mode &= ~TX_MODE_ENABLE;
4564         tw32_f(MAC_TX_MODE, tp->tx_mode);
4565
4566         for (i = 0; i < MAX_WAIT_CNT; i++) {
4567                 udelay(100);
4568                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4569                         break;
4570         }
4571         if (i >= MAX_WAIT_CNT) {
4572                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4573                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4574                        tp->dev->name, tr32(MAC_TX_MODE));
4575                 err |= -ENODEV;
4576         }
4577
4578         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4579         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4580         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4581
4582         tw32(FTQ_RESET, 0xffffffff);
4583         tw32(FTQ_RESET, 0x00000000);
4584
4585         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4586         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4587
4588         if (tp->hw_status)
4589                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4590         if (tp->hw_stats)
4591                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4592
4593         return err;
4594 }
4595
4596 /* tp->lock is held. */
4597 static int tg3_nvram_lock(struct tg3 *tp)
4598 {
4599         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4600                 int i;
4601
4602                 if (tp->nvram_lock_cnt == 0) {
4603                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4604                         for (i = 0; i < 8000; i++) {
4605                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4606                                         break;
4607                                 udelay(20);
4608                         }
4609                         if (i == 8000) {
4610                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4611                                 return -ENODEV;
4612                         }
4613                 }
4614                 tp->nvram_lock_cnt++;
4615         }
4616         return 0;
4617 }
4618
4619 /* tp->lock is held. */
4620 static void tg3_nvram_unlock(struct tg3 *tp)
4621 {
4622         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4623                 if (tp->nvram_lock_cnt > 0)
4624                         tp->nvram_lock_cnt--;
4625                 if (tp->nvram_lock_cnt == 0)
4626                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4627         }
4628 }
4629
4630 /* tp->lock is held. */
4631 static void tg3_enable_nvram_access(struct tg3 *tp)
4632 {
4633         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4634             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4635                 u32 nvaccess = tr32(NVRAM_ACCESS);
4636
4637                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4638         }
4639 }
4640
4641 /* tp->lock is held. */
4642 static void tg3_disable_nvram_access(struct tg3 *tp)
4643 {
4644         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4645             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4646                 u32 nvaccess = tr32(NVRAM_ACCESS);
4647
4648                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4649         }
4650 }
4651
4652 /* tp->lock is held. */
4653 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4654 {
4655         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4656                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4657
4658         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4659                 switch (kind) {
4660                 case RESET_KIND_INIT:
4661                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4662                                       DRV_STATE_START);
4663                         break;
4664
4665                 case RESET_KIND_SHUTDOWN:
4666                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4667                                       DRV_STATE_UNLOAD);
4668                         break;
4669
4670                 case RESET_KIND_SUSPEND:
4671                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4672                                       DRV_STATE_SUSPEND);
4673                         break;
4674
4675                 default:
4676                         break;
4677                 };
4678         }
4679 }
4680
4681 /* tp->lock is held. */
4682 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4683 {
4684         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4685                 switch (kind) {
4686                 case RESET_KIND_INIT:
4687                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4688                                       DRV_STATE_START_DONE);
4689                         break;
4690
4691                 case RESET_KIND_SHUTDOWN:
4692                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4693                                       DRV_STATE_UNLOAD_DONE);
4694                         break;
4695
4696                 default:
4697                         break;
4698                 };
4699         }
4700 }
4701
4702 /* tp->lock is held. */
4703 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4704 {
4705         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4706                 switch (kind) {
4707                 case RESET_KIND_INIT:
4708                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4709                                       DRV_STATE_START);
4710                         break;
4711
4712                 case RESET_KIND_SHUTDOWN:
4713                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4714                                       DRV_STATE_UNLOAD);
4715                         break;
4716
4717                 case RESET_KIND_SUSPEND:
4718                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4719                                       DRV_STATE_SUSPEND);
4720                         break;
4721
4722                 default:
4723                         break;
4724                 };
4725         }
4726 }
4727
4728 static int tg3_poll_fw(struct tg3 *tp)
4729 {
4730         int i;
4731         u32 val;
4732
4733         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4734                 /* Wait up to 20ms for init done. */
4735                 for (i = 0; i < 200; i++) {
4736                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4737                                 return 0;
4738                         udelay(100);
4739                 }
4740                 return -ENODEV;
4741         }
4742
4743         /* Wait for firmware initialization to complete. */
4744         for (i = 0; i < 100000; i++) {
4745                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4746                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4747                         break;
4748                 udelay(10);
4749         }
4750
4751         /* Chip might not be fitted with firmware.  Some Sun onboard
4752          * parts are configured like that.  So don't signal the timeout
4753          * of the above loop as an error, but do report the lack of
4754          * running firmware once.
4755          */
4756         if (i >= 100000 &&
4757             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4758                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4759
4760                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4761                        tp->dev->name);
4762         }
4763
4764         return 0;
4765 }
4766
4767 static void tg3_stop_fw(struct tg3 *);
4768
4769 /* tp->lock is held. */
4770 static int tg3_chip_reset(struct tg3 *tp)
4771 {
4772         u32 val;
4773         void (*write_op)(struct tg3 *, u32, u32);
4774         int err;
4775
4776         tg3_nvram_lock(tp);
4777
4778         /* No matching tg3_nvram_unlock() after this because
4779          * chip reset below will undo the nvram lock.
4780          */
4781         tp->nvram_lock_cnt = 0;
4782
4783         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4784             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4785             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4786                 tw32(GRC_FASTBOOT_PC, 0);
4787
4788         /*
4789          * We must avoid the readl() that normally takes place.
4790          * It locks machines, causes machine checks, and other
4791          * fun things.  So, temporarily disable the 5701
4792          * hardware workaround, while we do the reset.
4793          */
4794         write_op = tp->write32;
4795         if (write_op == tg3_write_flush_reg32)
4796                 tp->write32 = tg3_write32;
4797
4798         /* do the reset */
4799         val = GRC_MISC_CFG_CORECLK_RESET;
4800
4801         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4802                 if (tr32(0x7e2c) == 0x60) {
4803                         tw32(0x7e2c, 0x20);
4804                 }
4805                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4806                         tw32(GRC_MISC_CFG, (1 << 29));
4807                         val |= (1 << 29);
4808                 }
4809         }
4810
4811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4812                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4813                 tw32(GRC_VCPU_EXT_CTRL,
4814                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4815         }
4816
4817         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4818                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4819         tw32(GRC_MISC_CFG, val);
4820
4821         /* restore 5701 hardware bug workaround write method */
4822         tp->write32 = write_op;
4823
4824         /* Unfortunately, we have to delay before the PCI read back.
4825          * Some 575X chips even will not respond to a PCI cfg access
4826          * when the reset command is given to the chip.
4827          *
4828          * How do these hardware designers expect things to work
4829          * properly if the PCI write is posted for a long period
4830          * of time?  It is always necessary to have some method by
4831          * which a register read back can occur to push the write
4832          * out which does the reset.
4833          *
4834          * For most tg3 variants the trick below was working.
4835          * Ho hum...
4836          */
4837         udelay(120);
4838
4839         /* Flush PCI posted writes.  The normal MMIO registers
4840          * are inaccessible at this time so this is the only
4841          * way to make this reliably (actually, this is no longer
4842          * the case, see above).  I tried to use indirect
4843          * register read/write but this upset some 5701 variants.
4844          */
4845         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4846
4847         udelay(120);
4848
4849         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4850                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4851                         int i;
4852                         u32 cfg_val;
4853
4854                         /* Wait for link training to complete.  */
4855                         for (i = 0; i < 5000; i++)
4856                                 udelay(100);
4857
4858                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4859                         pci_write_config_dword(tp->pdev, 0xc4,
4860                                                cfg_val | (1 << 15));
4861                 }
4862                 /* Set PCIE max payload size and clear error status.  */
4863                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4864         }
4865
4866         /* Re-enable indirect register accesses. */
4867         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4868                                tp->misc_host_ctrl);
4869
4870         /* Set MAX PCI retry to zero. */
4871         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4872         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4873             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4874                 val |= PCISTATE_RETRY_SAME_DMA;
4875         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4876
4877         pci_restore_state(tp->pdev);
4878
4879         /* Make sure PCI-X relaxed ordering bit is clear. */
4880         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4881         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4882         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4883
4884         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4885                 u32 val;
4886
4887                 /* Chip reset on 5780 will reset MSI enable bit,
4888                  * so need to restore it.
4889                  */
4890                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4891                         u16 ctrl;
4892
4893                         pci_read_config_word(tp->pdev,
4894                                              tp->msi_cap + PCI_MSI_FLAGS,
4895                                              &ctrl);
4896                         pci_write_config_word(tp->pdev,
4897                                               tp->msi_cap + PCI_MSI_FLAGS,
4898                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4899                         val = tr32(MSGINT_MODE);
4900                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4901                 }
4902
4903                 val = tr32(MEMARB_MODE);
4904                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4905
4906         } else
4907                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4908
4909         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4910                 tg3_stop_fw(tp);
4911                 tw32(0x5000, 0x400);
4912         }
4913
4914         tw32(GRC_MODE, tp->grc_mode);
4915
4916         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4917                 u32 val = tr32(0xc4);
4918
4919                 tw32(0xc4, val | (1 << 15));
4920         }
4921
4922         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4923             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4924                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4925                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4926                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4927                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4928         }
4929
4930         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4931                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4932                 tw32_f(MAC_MODE, tp->mac_mode);
4933         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4934                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4935                 tw32_f(MAC_MODE, tp->mac_mode);
4936         } else
4937                 tw32_f(MAC_MODE, 0);
4938         udelay(40);
4939
4940         err = tg3_poll_fw(tp);
4941         if (err)
4942                 return err;
4943
4944         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4945             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4946                 u32 val = tr32(0x7c00);
4947
4948                 tw32(0x7c00, val | (1 << 25));
4949         }
4950
4951         /* Reprobe ASF enable state.  */
4952         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4953         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4954         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4955         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4956                 u32 nic_cfg;
4957
4958                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4959                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4960                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4961                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4962                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4963                 }
4964         }
4965
4966         return 0;
4967 }
4968
4969 /* tp->lock is held. */
4970 static void tg3_stop_fw(struct tg3 *tp)
4971 {
4972         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4973                 u32 val;
4974                 int i;
4975
4976                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4977                 val = tr32(GRC_RX_CPU_EVENT);
4978                 val |= (1 << 14);
4979                 tw32(GRC_RX_CPU_EVENT, val);
4980
4981                 /* Wait for RX cpu to ACK the event.  */
4982                 for (i = 0; i < 100; i++) {
4983                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4984                                 break;
4985                         udelay(1);
4986                 }
4987         }
4988 }
4989
4990 /* tp->lock is held. */
4991 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4992 {
4993         int err;
4994
4995         tg3_stop_fw(tp);
4996
4997         tg3_write_sig_pre_reset(tp, kind);
4998
4999         tg3_abort_hw(tp, silent);
5000         err = tg3_chip_reset(tp);
5001
5002         tg3_write_sig_legacy(tp, kind);
5003         tg3_write_sig_post_reset(tp, kind);
5004
5005         if (err)
5006                 return err;
5007
5008         return 0;
5009 }
5010
5011 #define TG3_FW_RELEASE_MAJOR    0x0
5012 #define TG3_FW_RELASE_MINOR     0x0
5013 #define TG3_FW_RELEASE_FIX      0x0
5014 #define TG3_FW_START_ADDR       0x08000000
5015 #define TG3_FW_TEXT_ADDR        0x08000000
5016 #define TG3_FW_TEXT_LEN         0x9c0
5017 #define TG3_FW_RODATA_ADDR      0x080009c0
5018 #define TG3_FW_RODATA_LEN       0x60
5019 #define TG3_FW_DATA_ADDR        0x08000a40
5020 #define TG3_FW_DATA_LEN         0x20
5021 #define TG3_FW_SBSS_ADDR        0x08000a60
5022 #define TG3_FW_SBSS_LEN         0xc
5023 #define TG3_FW_BSS_ADDR         0x08000a70
5024 #define TG3_FW_BSS_LEN          0x10
5025
5026 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5027         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5028         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5029         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5030         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5031         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5032         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5033         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5034         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5035         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5036         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5037         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5038         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5039         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5040         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5041         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5042         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5043         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5044         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5045         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5046         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5047         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5048         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5049         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5050         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5051         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5052         0, 0, 0, 0, 0, 0,
5053         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5054         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5055         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5056         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5057         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5058         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5059         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5060         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5061         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5062         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5063         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5064         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5065         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5066         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5067         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5068         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5069         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5070         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5071         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5072         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5073         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5074         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5075         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5076         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5077         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5078         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5079         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5080         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5081         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5082         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5083         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5084         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5085         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5086         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5087         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5088         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5089         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5090         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5091         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5092         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5093         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5094         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5095         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5096         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5097         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5098         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5099         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5100         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5101         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5102         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5103         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5104         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5105         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5106         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5107         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5108         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5109         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5110         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5111         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5112         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5113         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5114         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5115         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5116         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5117         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5118 };
5119
5120 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5121         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5122         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5123         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5124         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5125         0x00000000
5126 };
5127
5128 #if 0 /* All zeros, don't eat up space with it. */
5129 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5130         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5131         0x00000000, 0x00000000, 0x00000000, 0x00000000
5132 };
5133 #endif
5134
5135 #define RX_CPU_SCRATCH_BASE     0x30000
5136 #define RX_CPU_SCRATCH_SIZE     0x04000
5137 #define TX_CPU_SCRATCH_BASE     0x34000
5138 #define TX_CPU_SCRATCH_SIZE     0x04000
5139
5140 /* tp->lock is held. */
5141 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5142 {
5143         int i;
5144
5145         BUG_ON(offset == TX_CPU_BASE &&
5146             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5147
5148         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5149                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5150
5151                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5152                 return 0;
5153         }
5154         if (offset == RX_CPU_BASE) {
5155                 for (i = 0; i < 10000; i++) {
5156                         tw32(offset + CPU_STATE, 0xffffffff);
5157                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5158                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5159                                 break;
5160                 }
5161
5162                 tw32(offset + CPU_STATE, 0xffffffff);
5163                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5164                 udelay(10);
5165         } else {
5166                 for (i = 0; i < 10000; i++) {
5167                         tw32(offset + CPU_STATE, 0xffffffff);
5168                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5169                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5170                                 break;
5171                 }
5172         }
5173
5174         if (i >= 10000) {
5175                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5176                        "and %s CPU\n",
5177                        tp->dev->name,
5178                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5179                 return -ENODEV;
5180         }
5181
5182         /* Clear firmware's nvram arbitration. */
5183         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5184                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5185         return 0;
5186 }
5187
5188 struct fw_info {
5189         unsigned int text_base;
5190         unsigned int text_len;
5191         const u32 *text_data;
5192         unsigned int rodata_base;
5193         unsigned int rodata_len;
5194         const u32 *rodata_data;
5195         unsigned int data_base;
5196         unsigned int data_len;
5197         const u32 *data_data;
5198 };
5199
5200 /* tp->lock is held. */
5201 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5202                                  int cpu_scratch_size, struct fw_info *info)
5203 {
5204         int err, lock_err, i;
5205         void (*write_op)(struct tg3 *, u32, u32);
5206
5207         if (cpu_base == TX_CPU_BASE &&
5208             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5209                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5210                        "TX cpu firmware on %s which is 5705.\n",
5211                        tp->dev->name);
5212                 return -EINVAL;
5213         }
5214
5215         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5216                 write_op = tg3_write_mem;
5217         else
5218                 write_op = tg3_write_indirect_reg32;
5219
5220         /* It is possible that bootcode is still loading at this point.
5221          * Get the nvram lock first before halting the cpu.
5222          */
5223         lock_err = tg3_nvram_lock(tp);
5224         err = tg3_halt_cpu(tp, cpu_base);
5225         if (!lock_err)
5226                 tg3_nvram_unlock(tp);
5227         if (err)
5228                 goto out;
5229
5230         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5231                 write_op(tp, cpu_scratch_base + i, 0);
5232         tw32(cpu_base + CPU_STATE, 0xffffffff);
5233         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5234         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5235                 write_op(tp, (cpu_scratch_base +
5236                               (info->text_base & 0xffff) +
5237                               (i * sizeof(u32))),
5238                          (info->text_data ?
5239                           info->text_data[i] : 0));
5240         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5241                 write_op(tp, (cpu_scratch_base +
5242                               (info->rodata_base & 0xffff) +
5243                               (i * sizeof(u32))),
5244                          (info->rodata_data ?
5245                           info->rodata_data[i] : 0));
5246         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5247                 write_op(tp, (cpu_scratch_base +
5248                               (info->data_base & 0xffff) +
5249                               (i * sizeof(u32))),
5250                          (info->data_data ?
5251                           info->data_data[i] : 0));
5252
5253         err = 0;
5254
5255 out:
5256         return err;
5257 }
5258
5259 /* tp->lock is held. */
5260 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5261 {
5262         struct fw_info info;
5263         int err, i;
5264
5265         info.text_base = TG3_FW_TEXT_ADDR;
5266         info.text_len = TG3_FW_TEXT_LEN;
5267         info.text_data = &tg3FwText[0];
5268         info.rodata_base = TG3_FW_RODATA_ADDR;
5269         info.rodata_len = TG3_FW_RODATA_LEN;
5270         info.rodata_data = &tg3FwRodata[0];
5271         info.data_base = TG3_FW_DATA_ADDR;
5272         info.data_len = TG3_FW_DATA_LEN;
5273         info.data_data = NULL;
5274
5275         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5276                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5277                                     &info);
5278         if (err)
5279                 return err;
5280
5281         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5282                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5283                                     &info);
5284         if (err)
5285                 return err;
5286
5287         /* Now startup only the RX cpu. */
5288         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5289         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5290
5291         for (i = 0; i < 5; i++) {
5292                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5293                         break;
5294                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5295                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5296                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5297                 udelay(1000);
5298         }
5299         if (i >= 5) {
5300                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5301                        "to set RX CPU PC, is %08x should be %08x\n",
5302                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5303                        TG3_FW_TEXT_ADDR);
5304                 return -ENODEV;
5305         }
5306         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5307         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5308
5309         return 0;
5310 }
5311
5312 #if TG3_TSO_SUPPORT != 0
5313
5314 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5315 #define TG3_TSO_FW_RELASE_MINOR         0x6
5316 #define TG3_TSO_FW_RELEASE_FIX          0x0
5317 #define TG3_TSO_FW_START_ADDR           0x08000000
5318 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5319 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5320 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5321 #define TG3_TSO_FW_RODATA_LEN           0x60
5322 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5323 #define TG3_TSO_FW_DATA_LEN             0x30
5324 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5325 #define TG3_TSO_FW_SBSS_LEN             0x2c
5326 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5327 #define TG3_TSO_FW_BSS_LEN              0x894
5328
5329 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5330         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5331         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5332         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5333         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5334         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5335         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5336         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5337         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5338         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5339         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5340         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5341         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5342         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5343         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5344         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5345         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5346         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5347         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5348         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5349         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5350         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5351         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5352         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5353         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5354         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5355         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5356         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5357         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5358         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5359         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5360         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5361         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5362         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5363         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5364         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5365         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5366         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5367         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5368         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5369         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5370         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5371         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5372         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5373         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5374         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5375         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5376         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5377         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5378         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5379         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5380         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5381         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5382         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5383         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5384         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5385         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5386         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5387         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5388         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5389         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5390         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5391         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5392         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5393         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5394         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5395         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5396         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5397         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5398         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5399         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5400         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5401         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5402         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5403         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5404         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5405         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5406         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5407         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5408         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5409         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5410         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5411         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5412         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5413         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5414         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5415         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5416         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5417         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5418         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5419         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5420         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5421         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5422         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5423         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5424         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5425         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5426         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5427         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5428         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5429         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5430         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5431         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5432         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5433         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5434         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5435         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5436         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5437         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5438         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5439         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5440         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5441         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5442         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5443         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5444         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5445         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5446         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5447         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5448         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5449         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5450         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5451         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5452         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5453         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5454         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5455         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5456         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5457         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5458         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5459         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5460         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5461         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5462         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5463         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5464         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5465         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5466         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5467         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5468         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5469         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5470         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5471         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5472         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5473         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5474         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5475         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5476         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5477         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5478         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5479         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5480         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5481         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5482         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5483         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5484         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5485         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5486         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5487         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5488         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5489         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5490         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5491         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5492         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5493         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5494         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5495         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5496         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5497         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5498         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5499         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5500         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5501         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5502         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5503         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5504         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5505         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5506         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5507         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5508         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5509         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5510         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5511         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5512         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5513         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5514         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5515         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5516         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5517         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5518         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5519         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5520         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5521         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5522         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5523         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5524         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5525         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5526         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5527         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5528         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5529         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5530         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5531         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5532         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5533         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5534         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5535         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5536         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5537         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5538         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5539         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5540         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5541         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5542         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5543         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5544         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5545         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5546         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5547         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5548         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5549         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5550         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5551         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5552         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5553         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5554         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5555         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5556         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5557         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5558         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5559         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5560         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5561         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5562         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5563         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5564         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5565         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5566         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5567         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5568         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5569         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5570         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5571         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5572         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5573         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5574         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5575         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5576         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5577         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5578         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5579         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5580         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5581         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5582         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5583         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5584         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5585         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5586         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5587         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5588         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5589         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5590         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5591         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5592         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5593         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5594         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5595         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5596         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5597         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5598         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5599         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5600         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5601         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5602         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5603         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5604         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5605         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5606         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5607         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5608         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5609         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5610         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5611         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5612         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5613         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5614 };
5615
5616 static const u32 tg3TsoFwRodata[] = {
5617         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5618         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5619         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5620         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5621         0x00000000,
5622 };
5623
5624 static const u32 tg3TsoFwData[] = {
5625         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5626         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5627         0x00000000,
5628 };
5629
5630 /* 5705 needs a special version of the TSO firmware.  */
5631 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5632 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5633 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5634 #define TG3_TSO5_FW_START_ADDR          0x00010000
5635 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5636 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5637 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5638 #define TG3_TSO5_FW_RODATA_LEN          0x50
5639 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5640 #define TG3_TSO5_FW_DATA_LEN            0x20
5641 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5642 #define TG3_TSO5_FW_SBSS_LEN            0x28
5643 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5644 #define TG3_TSO5_FW_BSS_LEN             0x88
5645
5646 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5647         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5648         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5649         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5650         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5651         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5652         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5653         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5654         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5655         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5656         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5657         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5658         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5659         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5660         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5661         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5662         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5663         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5664         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5665         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5666         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5667         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5668         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5669         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5670         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5671         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5672         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5673         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5674         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5675         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5676         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5677         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5678         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5679         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5680         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5681         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5682         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5683         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5684         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5685         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5686         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5687         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5688         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5689         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5690         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5691         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5692         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5693         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5694         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5695         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5696         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5697         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5698         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5699         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5700         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5701         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5702         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5703         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5704         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5705         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5706         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5707         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5708         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5709         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5710         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5711         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5712         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5713         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5714         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5715         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5716         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5717         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5718         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5719         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5720         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5721         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5722         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5723         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5724         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5725         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5726         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5727         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5728         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5729         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5730         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5731         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5732         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5733         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5734         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5735         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5736         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5737         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5738         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5739         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5740         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5741         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5742         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5743         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5744         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5745         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5746         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5747         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5748         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5749         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5750         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5751         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5752         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5753         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5754         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5755         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5756         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5757         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5758         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5759         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5760         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5761         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5762         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5763         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5764         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5765         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5766         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5767         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5768         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5769         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5770         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5771         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5772         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5773         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5774         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5775         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5776         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5777         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5778         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5779         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5780         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5781         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5782         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5783         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5784         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5785         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5786         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5787         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5788         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5789         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5790         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5791         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5792         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5793         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5794         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5795         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5796         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5797         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5798         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5799         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5800         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5801         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5802         0x00000000, 0x00000000, 0x00000000,
5803 };
5804
5805 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5806         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5807         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5808         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5809         0x00000000, 0x00000000, 0x00000000,
5810 };
5811
5812 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5813         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5814         0x00000000, 0x00000000, 0x00000000,
5815 };
5816
5817 /* tp->lock is held. */
5818 static int tg3_load_tso_firmware(struct tg3 *tp)
5819 {
5820         struct fw_info info;
5821         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5822         int err, i;
5823
5824         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5825                 return 0;
5826
5827         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5828                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5829                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5830                 info.text_data = &tg3Tso5FwText[0];
5831                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5832                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5833                 info.rodata_data = &tg3Tso5FwRodata[0];
5834                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5835                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5836                 info.data_data = &tg3Tso5FwData[0];
5837                 cpu_base = RX_CPU_BASE;
5838                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5839                 cpu_scratch_size = (info.text_len +
5840                                     info.rodata_len +
5841                                     info.data_len +
5842                                     TG3_TSO5_FW_SBSS_LEN +
5843                                     TG3_TSO5_FW_BSS_LEN);
5844         } else {
5845                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5846                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5847                 info.text_data = &tg3TsoFwText[0];
5848                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5849                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5850                 info.rodata_data = &tg3TsoFwRodata[0];
5851                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5852                 info.data_len = TG3_TSO_FW_DATA_LEN;
5853                 info.data_data = &tg3TsoFwData[0];
5854                 cpu_base = TX_CPU_BASE;
5855                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5856                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5857         }
5858
5859         err = tg3_load_firmware_cpu(tp, cpu_base,
5860                                     cpu_scratch_base, cpu_scratch_size,
5861                                     &info);
5862         if (err)
5863                 return err;
5864
5865         /* Now startup the cpu. */
5866         tw32(cpu_base + CPU_STATE, 0xffffffff);
5867         tw32_f(cpu_base + CPU_PC,    info.text_base);
5868
5869         for (i = 0; i < 5; i++) {
5870                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5871                         break;
5872                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5873                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5874                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5875                 udelay(1000);
5876         }
5877         if (i >= 5) {
5878                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5879                        "to set CPU PC, is %08x should be %08x\n",
5880                        tp->dev->name, tr32(cpu_base + CPU_PC),
5881                        info.text_base);
5882                 return -ENODEV;
5883         }
5884         tw32(cpu_base + CPU_STATE, 0xffffffff);
5885         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5886         return 0;
5887 }
5888
5889 #endif /* TG3_TSO_SUPPORT != 0 */
5890
5891 /* tp->lock is held. */
5892 static void __tg3_set_mac_addr(struct tg3 *tp)
5893 {
5894         u32 addr_high, addr_low;
5895         int i;
5896
5897         addr_high = ((tp->dev->dev_addr[0] << 8) |
5898                      tp->dev->dev_addr[1]);
5899         addr_low = ((tp->dev->dev_addr[2] << 24) |
5900                     (tp->dev->dev_addr[3] << 16) |
5901                     (tp->dev->dev_addr[4] <<  8) |
5902                     (tp->dev->dev_addr[5] <<  0));
5903         for (i = 0; i < 4; i++) {
5904                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5905                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5906         }
5907
5908         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5909             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5910                 for (i = 0; i < 12; i++) {
5911                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5912                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5913                 }
5914         }
5915
5916         addr_high = (tp->dev->dev_addr[0] +
5917                      tp->dev->dev_addr[1] +
5918                      tp->dev->dev_addr[2] +
5919                      tp->dev->dev_addr[3] +
5920                      tp->dev->dev_addr[4] +
5921                      tp->dev->dev_addr[5]) &
5922                 TX_BACKOFF_SEED_MASK;
5923         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5924 }
5925
5926 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5927 {
5928         struct tg3 *tp = netdev_priv(dev);
5929         struct sockaddr *addr = p;
5930         int err = 0;
5931
5932         if (!is_valid_ether_addr(addr->sa_data))
5933                 return -EINVAL;
5934
5935         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5936
5937         if (!netif_running(dev))
5938                 return 0;
5939
5940         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5941                 /* Reset chip so that ASF can re-init any MAC addresses it
5942                  * needs.
5943                  */
5944                 tg3_netif_stop(tp);
5945                 tg3_full_lock(tp, 1);
5946
5947                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5948                 err = tg3_restart_hw(tp, 0);
5949                 if (!err)
5950                         tg3_netif_start(tp);
5951                 tg3_full_unlock(tp);
5952         } else {
5953                 spin_lock_bh(&tp->lock);
5954                 __tg3_set_mac_addr(tp);
5955                 spin_unlock_bh(&tp->lock);
5956         }
5957
5958         return err;
5959 }
5960
5961 /* tp->lock is held. */
5962 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5963                            dma_addr_t mapping, u32 maxlen_flags,
5964                            u32 nic_addr)
5965 {
5966         tg3_write_mem(tp,
5967                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5968                       ((u64) mapping >> 32));
5969         tg3_write_mem(tp,
5970                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5971                       ((u64) mapping & 0xffffffff));
5972         tg3_write_mem(tp,
5973                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5974                        maxlen_flags);
5975
5976         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5977                 tg3_write_mem(tp,
5978                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5979                               nic_addr);
5980 }
5981
5982 static void __tg3_set_rx_mode(struct net_device *);
5983 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5984 {
5985         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5986         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5987         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5988         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5989         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5990                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5991                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5992         }
5993         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5994         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5995         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5996                 u32 val = ec->stats_block_coalesce_usecs;
5997
5998                 if (!netif_carrier_ok(tp->dev))
5999                         val = 0;
6000
6001                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6002         }
6003 }
6004
6005 /* tp->lock is held. */
6006 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6007 {
6008         u32 val, rdmac_mode;
6009         int i, err, limit;
6010
6011         tg3_disable_ints(tp);
6012
6013         tg3_stop_fw(tp);
6014
6015         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6016
6017         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6018                 tg3_abort_hw(tp, 1);
6019         }
6020
6021         if (reset_phy)
6022                 tg3_phy_reset(tp);
6023
6024         err = tg3_chip_reset(tp);
6025         if (err)
6026                 return err;
6027
6028         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6029
6030         /* This works around an issue with Athlon chipsets on
6031          * B3 tigon3 silicon.  This bit has no effect on any
6032          * other revision.  But do not set this on PCI Express
6033          * chips.
6034          */
6035         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6036                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6037         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6038
6039         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6040             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6041                 val = tr32(TG3PCI_PCISTATE);
6042                 val |= PCISTATE_RETRY_SAME_DMA;
6043                 tw32(TG3PCI_PCISTATE, val);
6044         }
6045
6046         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6047                 /* Enable some hw fixes.  */
6048                 val = tr32(TG3PCI_MSI_DATA);
6049                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6050                 tw32(TG3PCI_MSI_DATA, val);
6051         }
6052
6053         /* Descriptor ring init may make accesses to the
6054          * NIC SRAM area to setup the TX descriptors, so we
6055          * can only do this after the hardware has been
6056          * successfully reset.
6057          */
6058         err = tg3_init_rings(tp);
6059         if (err)
6060                 return err;
6061
6062         /* This value is determined during the probe time DMA
6063          * engine test, tg3_test_dma.
6064          */
6065         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6066
6067         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6068                           GRC_MODE_4X_NIC_SEND_RINGS |
6069                           GRC_MODE_NO_TX_PHDR_CSUM |
6070                           GRC_MODE_NO_RX_PHDR_CSUM);
6071         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6072
6073         /* Pseudo-header checksum is done by hardware logic and not
6074          * the offload processers, so make the chip do the pseudo-
6075          * header checksums on receive.  For transmit it is more
6076          * convenient to do the pseudo-header checksum in software
6077          * as Linux does that on transmit for us in all cases.
6078          */
6079         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6080
6081         tw32(GRC_MODE,
6082              tp->grc_mode |
6083              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6084
6085         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6086         val = tr32(GRC_MISC_CFG);
6087         val &= ~0xff;
6088         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6089         tw32(GRC_MISC_CFG, val);
6090
6091         /* Initialize MBUF/DESC pool. */
6092         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6093                 /* Do nothing.  */
6094         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6095                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6096                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6097                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6098                 else
6099                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6100                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6101                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6102         }
6103 #if TG3_TSO_SUPPORT != 0
6104         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6105                 int fw_len;
6106
6107                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6108                           TG3_TSO5_FW_RODATA_LEN +
6109                           TG3_TSO5_FW_DATA_LEN +
6110                           TG3_TSO5_FW_SBSS_LEN +
6111                           TG3_TSO5_FW_BSS_LEN);
6112                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6113                 tw32(BUFMGR_MB_POOL_ADDR,
6114                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6115                 tw32(BUFMGR_MB_POOL_SIZE,
6116                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6117         }
6118 #endif
6119
6120         if (tp->dev->mtu <= ETH_DATA_LEN) {
6121                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6122                      tp->bufmgr_config.mbuf_read_dma_low_water);
6123                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6124                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6125                 tw32(BUFMGR_MB_HIGH_WATER,
6126                      tp->bufmgr_config.mbuf_high_water);
6127         } else {
6128                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6129                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6130                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6131                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6132                 tw32(BUFMGR_MB_HIGH_WATER,
6133                      tp->bufmgr_config.mbuf_high_water_jumbo);
6134         }
6135         tw32(BUFMGR_DMA_LOW_WATER,
6136              tp->bufmgr_config.dma_low_water);
6137         tw32(BUFMGR_DMA_HIGH_WATER,
6138              tp->bufmgr_config.dma_high_water);
6139
6140         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6141         for (i = 0; i < 2000; i++) {
6142                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6143                         break;
6144                 udelay(10);
6145         }
6146         if (i >= 2000) {
6147                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6148                        tp->dev->name);
6149                 return -ENODEV;
6150         }
6151
6152         /* Setup replenish threshold. */
6153         val = tp->rx_pending / 8;
6154         if (val == 0)
6155                 val = 1;
6156         else if (val > tp->rx_std_max_post)
6157                 val = tp->rx_std_max_post;
6158         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6159                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6160                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6161
6162                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6163                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6164         }
6165
6166         tw32(RCVBDI_STD_THRESH, val);
6167
6168         /* Initialize TG3_BDINFO's at:
6169          *  RCVDBDI_STD_BD:     standard eth size rx ring
6170          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6171          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6172          *
6173          * like so:
6174          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6175          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6176          *                              ring attribute flags
6177          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6178          *
6179          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6180          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6181          *
6182          * The size of each ring is fixed in the firmware, but the location is
6183          * configurable.
6184          */
6185         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6186              ((u64) tp->rx_std_mapping >> 32));
6187         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6188              ((u64) tp->rx_std_mapping & 0xffffffff));
6189         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6190              NIC_SRAM_RX_BUFFER_DESC);
6191
6192         /* Don't even try to program the JUMBO/MINI buffer descriptor
6193          * configs on 5705.
6194          */
6195         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6196                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6197                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6198         } else {
6199                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6200                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6201
6202                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6203                      BDINFO_FLAGS_DISABLED);
6204
6205                 /* Setup replenish threshold. */
6206                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6207
6208                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6209                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6210                              ((u64) tp->rx_jumbo_mapping >> 32));
6211                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6212                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6213                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6214                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6215                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6216                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6217                 } else {
6218                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6219                              BDINFO_FLAGS_DISABLED);
6220                 }
6221
6222         }
6223
6224         /* There is only one send ring on 5705/5750, no need to explicitly
6225          * disable the others.
6226          */
6227         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6228                 /* Clear out send RCB ring in SRAM. */
6229                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6230                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6231                                       BDINFO_FLAGS_DISABLED);
6232         }
6233
6234         tp->tx_prod = 0;
6235         tp->tx_cons = 0;
6236         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6237         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6238
6239         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6240                        tp->tx_desc_mapping,
6241                        (TG3_TX_RING_SIZE <<
6242                         BDINFO_FLAGS_MAXLEN_SHIFT),
6243                        NIC_SRAM_TX_BUFFER_DESC);
6244
6245         /* There is only one receive return ring on 5705/5750, no need
6246          * to explicitly disable the others.
6247          */
6248         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6249                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6250                      i += TG3_BDINFO_SIZE) {
6251                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6252                                       BDINFO_FLAGS_DISABLED);
6253                 }
6254         }
6255
6256         tp->rx_rcb_ptr = 0;
6257         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6258
6259         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6260                        tp->rx_rcb_mapping,
6261                        (TG3_RX_RCB_RING_SIZE(tp) <<
6262                         BDINFO_FLAGS_MAXLEN_SHIFT),
6263                        0);
6264
6265         tp->rx_std_ptr = tp->rx_pending;
6266         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6267                      tp->rx_std_ptr);
6268
6269         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6270                                                 tp->rx_jumbo_pending : 0;
6271         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6272                      tp->rx_jumbo_ptr);
6273
6274         /* Initialize MAC address and backoff seed. */
6275         __tg3_set_mac_addr(tp);
6276
6277         /* MTU + ethernet header + FCS + optional VLAN tag */
6278         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6279
6280         /* The slot time is changed by tg3_setup_phy if we
6281          * run at gigabit with half duplex.
6282          */
6283         tw32(MAC_TX_LENGTHS,
6284              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6285              (6 << TX_LENGTHS_IPG_SHIFT) |
6286              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6287
6288         /* Receive rules. */
6289         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6290         tw32(RCVLPC_CONFIG, 0x0181);
6291
6292         /* Calculate RDMAC_MODE setting early, we need it to determine
6293          * the RCVLPC_STATE_ENABLE mask.
6294          */
6295         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6296                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6297                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6298                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6299                       RDMAC_MODE_LNGREAD_ENAB);
6300         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6301                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6302
6303         /* If statement applies to 5705 and 5750 PCI devices only */
6304         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6305              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6306             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6307                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6308                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6309                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6310                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6311                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6312                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6313                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6314                 }
6315         }
6316
6317         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6318                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6319
6320 #if TG3_TSO_SUPPORT != 0
6321         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6322                 rdmac_mode |= (1 << 27);
6323 #endif
6324
6325         /* Receive/send statistics. */
6326         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6327                 val = tr32(RCVLPC_STATS_ENABLE);
6328                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6329                 tw32(RCVLPC_STATS_ENABLE, val);
6330         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6331                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6332                 val = tr32(RCVLPC_STATS_ENABLE);
6333                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6334                 tw32(RCVLPC_STATS_ENABLE, val);
6335         } else {
6336                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6337         }
6338         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6339         tw32(SNDDATAI_STATSENAB, 0xffffff);
6340         tw32(SNDDATAI_STATSCTRL,
6341              (SNDDATAI_SCTRL_ENABLE |
6342               SNDDATAI_SCTRL_FASTUPD));
6343
6344         /* Setup host coalescing engine. */
6345         tw32(HOSTCC_MODE, 0);
6346         for (i = 0; i < 2000; i++) {
6347                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6348                         break;
6349                 udelay(10);
6350         }
6351
6352         __tg3_set_coalesce(tp, &tp->coal);
6353
6354         /* set status block DMA address */
6355         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6356              ((u64) tp->status_mapping >> 32));
6357         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6358              ((u64) tp->status_mapping & 0xffffffff));
6359
6360         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6361                 /* Status/statistics block address.  See tg3_timer,
6362                  * the tg3_periodic_fetch_stats call there, and
6363                  * tg3_get_stats to see how this works for 5705/5750 chips.
6364                  */
6365                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6366                      ((u64) tp->stats_mapping >> 32));
6367                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6368                      ((u64) tp->stats_mapping & 0xffffffff));
6369                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6370                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6371         }
6372
6373         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6374
6375         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6376         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6377         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6378                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6379
6380         /* Clear statistics/status block in chip, and status block in ram. */
6381         for (i = NIC_SRAM_STATS_BLK;
6382              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6383              i += sizeof(u32)) {
6384                 tg3_write_mem(tp, i, 0);
6385                 udelay(40);
6386         }
6387         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6388
6389         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6390                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6391                 /* reset to prevent losing 1st rx packet intermittently */
6392                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6393                 udelay(10);
6394         }
6395
6396         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6397                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6398         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6399         udelay(40);
6400
6401         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6402          * If TG3_FLG2_IS_NIC is zero, we should read the
6403          * register to preserve the GPIO settings for LOMs. The GPIOs,
6404          * whether used as inputs or outputs, are set by boot code after
6405          * reset.
6406          */
6407         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6408                 u32 gpio_mask;
6409
6410                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6411                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6412                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6413
6414                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6415                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6416                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6417
6418                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6419                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6420
6421                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6422
6423                 /* GPIO1 must be driven high for eeprom write protect */
6424                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6425                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6426                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6427         }
6428         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6429         udelay(100);
6430
6431         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6432         tp->last_tag = 0;
6433
6434         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6435                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6436                 udelay(40);
6437         }
6438
6439         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6440                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6441                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6442                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6443                WDMAC_MODE_LNGREAD_ENAB);
6444
6445         /* If statement applies to 5705 and 5750 PCI devices only */
6446         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6447              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6448             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6449                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6450                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6451                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6452                         /* nothing */
6453                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6454                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6455                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6456                         val |= WDMAC_MODE_RX_ACCEL;
6457                 }
6458         }
6459
6460         /* Enable host coalescing bug fix */
6461         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6462             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6463                 val |= (1 << 29);
6464
6465         tw32_f(WDMAC_MODE, val);
6466         udelay(40);
6467
6468         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6469                 val = tr32(TG3PCI_X_CAPS);
6470                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6471                         val &= ~PCIX_CAPS_BURST_MASK;
6472                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6473                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6474                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6475                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6476                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6477                                 val |= (tp->split_mode_max_reqs <<
6478                                         PCIX_CAPS_SPLIT_SHIFT);
6479                 }
6480                 tw32(TG3PCI_X_CAPS, val);
6481         }
6482
6483         tw32_f(RDMAC_MODE, rdmac_mode);
6484         udelay(40);
6485
6486         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6487         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6488                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6489         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6490         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6491         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6492         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6493         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6494 #if TG3_TSO_SUPPORT != 0
6495         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6496                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6497 #endif
6498         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6499         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6500
6501         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6502                 err = tg3_load_5701_a0_firmware_fix(tp);
6503                 if (err)
6504                         return err;
6505         }
6506
6507 #if TG3_TSO_SUPPORT != 0
6508         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6509                 err = tg3_load_tso_firmware(tp);
6510                 if (err)
6511                         return err;
6512         }
6513 #endif
6514
6515         tp->tx_mode = TX_MODE_ENABLE;
6516         tw32_f(MAC_TX_MODE, tp->tx_mode);
6517         udelay(100);
6518
6519         tp->rx_mode = RX_MODE_ENABLE;
6520         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6521                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6522
6523         tw32_f(MAC_RX_MODE, tp->rx_mode);
6524         udelay(10);
6525
6526         if (tp->link_config.phy_is_low_power) {
6527                 tp->link_config.phy_is_low_power = 0;
6528                 tp->link_config.speed = tp->link_config.orig_speed;
6529                 tp->link_config.duplex = tp->link_config.orig_duplex;
6530                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6531         }
6532
6533         tp->mi_mode = MAC_MI_MODE_BASE;
6534         tw32_f(MAC_MI_MODE, tp->mi_mode);
6535         udelay(80);
6536
6537         tw32(MAC_LED_CTRL, tp->led_ctrl);
6538
6539         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6540         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6541                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6542                 udelay(10);
6543         }
6544         tw32_f(MAC_RX_MODE, tp->rx_mode);
6545         udelay(10);
6546
6547         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6548                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6549                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6550                         /* Set drive transmission level to 1.2V  */
6551                         /* only if the signal pre-emphasis bit is not set  */
6552                         val = tr32(MAC_SERDES_CFG);
6553                         val &= 0xfffff000;
6554                         val |= 0x880;
6555                         tw32(MAC_SERDES_CFG, val);
6556                 }
6557                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6558                         tw32(MAC_SERDES_CFG, 0x616000);
6559         }
6560
6561         /* Prevent chip from dropping frames when flow control
6562          * is enabled.
6563          */
6564         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6565
6566         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6567             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6568                 /* Use hardware link auto-negotiation */
6569                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6570         }
6571
6572         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6573             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6574                 u32 tmp;
6575
6576                 tmp = tr32(SERDES_RX_CTRL);
6577                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6578                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6579                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6580                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6581         }
6582
6583         err = tg3_setup_phy(tp, 0);
6584         if (err)
6585                 return err;
6586
6587         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6588             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6589                 u32 tmp;
6590
6591                 /* Clear CRC stats. */
6592                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6593                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6594                         tg3_readphy(tp, 0x14, &tmp);
6595                 }
6596         }
6597
6598         __tg3_set_rx_mode(tp->dev);
6599
6600         /* Initialize receive rules. */
6601         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6602         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6603         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6604         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6605
6606         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6607             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6608                 limit = 8;
6609         else
6610                 limit = 16;
6611         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6612                 limit -= 4;
6613         switch (limit) {
6614         case 16:
6615                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6616         case 15:
6617                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6618         case 14:
6619                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6620         case 13:
6621                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6622         case 12:
6623                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6624         case 11:
6625                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6626         case 10:
6627                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6628         case 9:
6629                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6630         case 8:
6631                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6632         case 7:
6633                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6634         case 6:
6635                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6636         case 5:
6637                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6638         case 4:
6639                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6640         case 3:
6641                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6642         case 2:
6643         case 1:
6644
6645         default:
6646                 break;
6647         };
6648
6649         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6650
6651         return 0;
6652 }
6653
6654 /* Called at device open time to get the chip ready for
6655  * packet processing.  Invoked with tp->lock held.
6656  */
6657 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6658 {
6659         int err;
6660
6661         /* Force the chip into D0. */
6662         err = tg3_set_power_state(tp, PCI_D0);
6663         if (err)
6664                 goto out;
6665
6666         tg3_switch_clocks(tp);
6667
6668         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6669
6670         err = tg3_reset_hw(tp, reset_phy);
6671
6672 out:
6673         return err;
6674 }
6675
6676 #define TG3_STAT_ADD32(PSTAT, REG) \
6677 do {    u32 __val = tr32(REG); \
6678         (PSTAT)->low += __val; \
6679         if ((PSTAT)->low < __val) \
6680                 (PSTAT)->high += 1; \
6681 } while (0)
6682
6683 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6684 {
6685         struct tg3_hw_stats *sp = tp->hw_stats;
6686
6687         if (!netif_carrier_ok(tp->dev))
6688                 return;
6689
6690         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6691         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6692         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6693         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6694         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6695         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6696         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6697         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6698         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6699         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6700         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6701         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6702         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6703
6704         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6705         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6706         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6707         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6708         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6709         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6710         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6711         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6712         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6713         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6714         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6715         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6716         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6717         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6718
6719         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6720         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6721         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6722 }
6723
6724 static void tg3_timer(unsigned long __opaque)
6725 {
6726         struct tg3 *tp = (struct tg3 *) __opaque;
6727
6728         if (tp->irq_sync)
6729                 goto restart_timer;
6730
6731         spin_lock(&tp->lock);
6732
6733         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6734                 /* All of this garbage is because when using non-tagged
6735                  * IRQ status the mailbox/status_block protocol the chip
6736                  * uses with the cpu is race prone.
6737                  */
6738                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6739                         tw32(GRC_LOCAL_CTRL,
6740                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6741                 } else {
6742                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6743                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6744                 }
6745
6746                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6747                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6748                         spin_unlock(&tp->lock);
6749                         schedule_work(&tp->reset_task);
6750                         return;
6751                 }
6752         }
6753
6754         /* This part only runs once per second. */
6755         if (!--tp->timer_counter) {
6756                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6757                         tg3_periodic_fetch_stats(tp);
6758
6759                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6760                         u32 mac_stat;
6761                         int phy_event;
6762
6763                         mac_stat = tr32(MAC_STATUS);
6764
6765                         phy_event = 0;
6766                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6767                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6768                                         phy_event = 1;
6769                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6770                                 phy_event = 1;
6771
6772                         if (phy_event)
6773                                 tg3_setup_phy(tp, 0);
6774                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6775                         u32 mac_stat = tr32(MAC_STATUS);
6776                         int need_setup = 0;
6777
6778                         if (netif_carrier_ok(tp->dev) &&
6779                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6780                                 need_setup = 1;
6781                         }
6782                         if (! netif_carrier_ok(tp->dev) &&
6783                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6784                                          MAC_STATUS_SIGNAL_DET))) {
6785                                 need_setup = 1;
6786                         }
6787                         if (need_setup) {
6788                                 if (!tp->serdes_counter) {
6789                                         tw32_f(MAC_MODE,
6790                                              (tp->mac_mode &
6791                                               ~MAC_MODE_PORT_MODE_MASK));
6792                                         udelay(40);
6793                                         tw32_f(MAC_MODE, tp->mac_mode);
6794                                         udelay(40);
6795                                 }
6796                                 tg3_setup_phy(tp, 0);
6797                         }
6798                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6799                         tg3_serdes_parallel_detect(tp);
6800
6801                 tp->timer_counter = tp->timer_multiplier;
6802         }
6803
6804         /* Heartbeat is only sent once every 2 seconds.
6805          *
6806          * The heartbeat is to tell the ASF firmware that the host
6807          * driver is still alive.  In the event that the OS crashes,
6808          * ASF needs to reset the hardware to free up the FIFO space
6809          * that may be filled with rx packets destined for the host.
6810          * If the FIFO is full, ASF will no longer function properly.
6811          *
6812          * Unintended resets have been reported on real time kernels
6813          * where the timer doesn't run on time.  Netpoll will also have
6814          * same problem.
6815          *
6816          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6817          * to check the ring condition when the heartbeat is expiring
6818          * before doing the reset.  This will prevent most unintended
6819          * resets.
6820          */
6821         if (!--tp->asf_counter) {
6822                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6823                         u32 val;
6824
6825                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6826                                       FWCMD_NICDRV_ALIVE3);
6827                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6828                         /* 5 seconds timeout */
6829                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6830                         val = tr32(GRC_RX_CPU_EVENT);
6831                         val |= (1 << 14);
6832                         tw32(GRC_RX_CPU_EVENT, val);
6833                 }
6834                 tp->asf_counter = tp->asf_multiplier;
6835         }
6836
6837         spin_unlock(&tp->lock);
6838
6839 restart_timer:
6840         tp->timer.expires = jiffies + tp->timer_offset;
6841         add_timer(&tp->timer);
6842 }
6843
6844 static int tg3_request_irq(struct tg3 *tp)
6845 {
6846         irq_handler_t fn;
6847         unsigned long flags;
6848         struct net_device *dev = tp->dev;
6849
6850         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6851                 fn = tg3_msi;
6852                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6853                         fn = tg3_msi_1shot;
6854                 flags = IRQF_SAMPLE_RANDOM;
6855         } else {
6856                 fn = tg3_interrupt;
6857                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6858                         fn = tg3_interrupt_tagged;
6859                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6860         }
6861         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6862 }
6863
6864 static int tg3_test_interrupt(struct tg3 *tp)
6865 {
6866         struct net_device *dev = tp->dev;
6867         int err, i, intr_ok = 0;
6868
6869         if (!netif_running(dev))
6870                 return -ENODEV;
6871
6872         tg3_disable_ints(tp);
6873
6874         free_irq(tp->pdev->irq, dev);
6875
6876         err = request_irq(tp->pdev->irq, tg3_test_isr,
6877                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6878         if (err)
6879                 return err;
6880
6881         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6882         tg3_enable_ints(tp);
6883
6884         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6885                HOSTCC_MODE_NOW);
6886
6887         for (i = 0; i < 5; i++) {
6888                 u32 int_mbox, misc_host_ctrl;
6889
6890                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6891                                         TG3_64BIT_REG_LOW);
6892                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6893
6894                 if ((int_mbox != 0) ||
6895                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6896                         intr_ok = 1;
6897                         break;
6898                 }
6899
6900                 msleep(10);
6901         }
6902
6903         tg3_disable_ints(tp);
6904
6905         free_irq(tp->pdev->irq, dev);
6906
6907         err = tg3_request_irq(tp);
6908
6909         if (err)
6910                 return err;
6911
6912         if (intr_ok)
6913                 return 0;
6914
6915         return -EIO;
6916 }
6917
6918 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6919  * successfully restored
6920  */
6921 static int tg3_test_msi(struct tg3 *tp)
6922 {
6923         struct net_device *dev = tp->dev;
6924         int err;
6925         u16 pci_cmd;
6926
6927         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6928                 return 0;
6929
6930         /* Turn off SERR reporting in case MSI terminates with Master
6931          * Abort.
6932          */
6933         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6934         pci_write_config_word(tp->pdev, PCI_COMMAND,
6935                               pci_cmd & ~PCI_COMMAND_SERR);
6936
6937         err = tg3_test_interrupt(tp);
6938
6939         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6940
6941         if (!err)
6942                 return 0;
6943
6944         /* other failures */
6945         if (err != -EIO)
6946                 return err;
6947
6948         /* MSI test failed, go back to INTx mode */
6949         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6950                "switching to INTx mode. Please report this failure to "
6951                "the PCI maintainer and include system chipset information.\n",
6952                        tp->dev->name);
6953
6954         free_irq(tp->pdev->irq, dev);
6955         pci_disable_msi(tp->pdev);
6956
6957         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6958
6959         err = tg3_request_irq(tp);
6960         if (err)
6961                 return err;
6962
6963         /* Need to reset the chip because the MSI cycle may have terminated
6964          * with Master Abort.
6965          */
6966         tg3_full_lock(tp, 1);
6967
6968         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6969         err = tg3_init_hw(tp, 1);
6970
6971         tg3_full_unlock(tp);
6972
6973         if (err)
6974                 free_irq(tp->pdev->irq, dev);
6975
6976         return err;
6977 }
6978
6979 static int tg3_open(struct net_device *dev)
6980 {
6981         struct tg3 *tp = netdev_priv(dev);
6982         int err;
6983
6984         netif_carrier_off(tp->dev);
6985
6986         tg3_full_lock(tp, 0);
6987
6988         err = tg3_set_power_state(tp, PCI_D0);
6989         if (err) {
6990                 tg3_full_unlock(tp);
6991                 return err;
6992         }
6993
6994         tg3_disable_ints(tp);
6995         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6996
6997         tg3_full_unlock(tp);
6998
6999         /* The placement of this call is tied
7000          * to the setup and use of Host TX descriptors.
7001          */
7002         err = tg3_alloc_consistent(tp);
7003         if (err)
7004                 return err;
7005
7006         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7007             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7008             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7009             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7010               (tp->pdev_peer == tp->pdev))) {
7011                 /* All MSI supporting chips should support tagged
7012                  * status.  Assert that this is the case.
7013                  */
7014                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7015                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7016                                "Not using MSI.\n", tp->dev->name);
7017                 } else if (pci_enable_msi(tp->pdev) == 0) {
7018                         u32 msi_mode;
7019
7020                         msi_mode = tr32(MSGINT_MODE);
7021                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7022                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7023                 }
7024         }
7025         err = tg3_request_irq(tp);
7026
7027         if (err) {
7028                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7029                         pci_disable_msi(tp->pdev);
7030                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7031                 }
7032                 tg3_free_consistent(tp);
7033                 return err;
7034         }
7035
7036         tg3_full_lock(tp, 0);
7037
7038         err = tg3_init_hw(tp, 1);
7039         if (err) {
7040                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7041                 tg3_free_rings(tp);
7042         } else {
7043                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7044                         tp->timer_offset = HZ;
7045                 else
7046                         tp->timer_offset = HZ / 10;
7047
7048                 BUG_ON(tp->timer_offset > HZ);
7049                 tp->timer_counter = tp->timer_multiplier =
7050                         (HZ / tp->timer_offset);
7051                 tp->asf_counter = tp->asf_multiplier =
7052                         ((HZ / tp->timer_offset) * 2);
7053
7054                 init_timer(&tp->timer);
7055                 tp->timer.expires = jiffies + tp->timer_offset;
7056                 tp->timer.data = (unsigned long) tp;
7057                 tp->timer.function = tg3_timer;
7058         }
7059
7060         tg3_full_unlock(tp);
7061
7062         if (err) {
7063                 free_irq(tp->pdev->irq, dev);
7064                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7065                         pci_disable_msi(tp->pdev);
7066                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7067                 }
7068                 tg3_free_consistent(tp);
7069                 return err;
7070         }
7071
7072         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7073                 err = tg3_test_msi(tp);
7074
7075                 if (err) {
7076                         tg3_full_lock(tp, 0);
7077
7078                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7079                                 pci_disable_msi(tp->pdev);
7080                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7081                         }
7082                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7083                         tg3_free_rings(tp);
7084                         tg3_free_consistent(tp);
7085
7086                         tg3_full_unlock(tp);
7087
7088                         return err;
7089                 }
7090
7091                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7092                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7093                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7094
7095                                 tw32(PCIE_TRANSACTION_CFG,
7096                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7097                         }
7098                 }
7099         }
7100
7101         tg3_full_lock(tp, 0);
7102
7103         add_timer(&tp->timer);
7104         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7105         tg3_enable_ints(tp);
7106
7107         tg3_full_unlock(tp);
7108
7109         netif_start_queue(dev);
7110
7111         return 0;
7112 }
7113
7114 #if 0
7115 /*static*/ void tg3_dump_state(struct tg3 *tp)
7116 {
7117         u32 val32, val32_2, val32_3, val32_4, val32_5;
7118         u16 val16;
7119         int i;
7120
7121         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7122         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7123         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7124                val16, val32);
7125
7126         /* MAC block */
7127         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7128                tr32(MAC_MODE), tr32(MAC_STATUS));
7129         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7130                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7131         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7132                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7133         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7134                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7135
7136         /* Send data initiator control block */
7137         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7138                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7139         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7140                tr32(SNDDATAI_STATSCTRL));
7141
7142         /* Send data completion control block */
7143         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7144
7145         /* Send BD ring selector block */
7146         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7147                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7148
7149         /* Send BD initiator control block */
7150         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7151                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7152
7153         /* Send BD completion control block */
7154         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7155
7156         /* Receive list placement control block */
7157         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7158                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7159         printk("       RCVLPC_STATSCTRL[%08x]\n",
7160                tr32(RCVLPC_STATSCTRL));
7161
7162         /* Receive data and receive BD initiator control block */
7163         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7164                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7165
7166         /* Receive data completion control block */
7167         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7168                tr32(RCVDCC_MODE));
7169
7170         /* Receive BD initiator control block */
7171         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7172                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7173
7174         /* Receive BD completion control block */
7175         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7176                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7177
7178         /* Receive list selector control block */
7179         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7180                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7181
7182         /* Mbuf cluster free block */
7183         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7184                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7185
7186         /* Host coalescing control block */
7187         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7188                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7189         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7190                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7191                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7192         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7193                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7194                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7195         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7196                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7197         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7198                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7199
7200         /* Memory arbiter control block */
7201         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7202                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7203
7204         /* Buffer manager control block */
7205         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7206                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7207         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7208                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7209         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7210                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7211                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7212                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7213
7214         /* Read DMA control block */
7215         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7216                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7217
7218         /* Write DMA control block */
7219         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7220                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7221
7222         /* DMA completion block */
7223         printk("DEBUG: DMAC_MODE[%08x]\n",
7224                tr32(DMAC_MODE));
7225
7226         /* GRC block */
7227         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7228                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7229         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7230                tr32(GRC_LOCAL_CTRL));
7231
7232         /* TG3_BDINFOs */
7233         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7234                tr32(RCVDBDI_JUMBO_BD + 0x0),
7235                tr32(RCVDBDI_JUMBO_BD + 0x4),
7236                tr32(RCVDBDI_JUMBO_BD + 0x8),
7237                tr32(RCVDBDI_JUMBO_BD + 0xc));
7238         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7239                tr32(RCVDBDI_STD_BD + 0x0),
7240                tr32(RCVDBDI_STD_BD + 0x4),
7241                tr32(RCVDBDI_STD_BD + 0x8),
7242                tr32(RCVDBDI_STD_BD + 0xc));
7243         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7244                tr32(RCVDBDI_MINI_BD + 0x0),
7245                tr32(RCVDBDI_MINI_BD + 0x4),
7246                tr32(RCVDBDI_MINI_BD + 0x8),
7247                tr32(RCVDBDI_MINI_BD + 0xc));
7248
7249         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7250         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7251         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7252         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7253         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7254                val32, val32_2, val32_3, val32_4);
7255
7256         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7257         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7258         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7259         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7260         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7261                val32, val32_2, val32_3, val32_4);
7262
7263         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7264         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7265         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7266         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7267         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7268         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7269                val32, val32_2, val32_3, val32_4, val32_5);
7270
7271         /* SW status block */
7272         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7273                tp->hw_status->status,
7274                tp->hw_status->status_tag,
7275                tp->hw_status->rx_jumbo_consumer,
7276                tp->hw_status->rx_consumer,
7277                tp->hw_status->rx_mini_consumer,
7278                tp->hw_status->idx[0].rx_producer,
7279                tp->hw_status->idx[0].tx_consumer);
7280
7281         /* SW statistics block */
7282         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7283                ((u32 *)tp->hw_stats)[0],
7284                ((u32 *)tp->hw_stats)[1],
7285                ((u32 *)tp->hw_stats)[2],
7286                ((u32 *)tp->hw_stats)[3]);
7287
7288         /* Mailboxes */
7289         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7290                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7291                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7292                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7293                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7294
7295         /* NIC side send descriptors. */
7296         for (i = 0; i < 6; i++) {
7297                 unsigned long txd;
7298
7299                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7300                         + (i * sizeof(struct tg3_tx_buffer_desc));
7301                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7302                        i,
7303                        readl(txd + 0x0), readl(txd + 0x4),
7304                        readl(txd + 0x8), readl(txd + 0xc));
7305         }
7306
7307         /* NIC side RX descriptors. */
7308         for (i = 0; i < 6; i++) {
7309                 unsigned long rxd;
7310
7311                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7312                         + (i * sizeof(struct tg3_rx_buffer_desc));
7313                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7314                        i,
7315                        readl(rxd + 0x0), readl(rxd + 0x4),
7316                        readl(rxd + 0x8), readl(rxd + 0xc));
7317                 rxd += (4 * sizeof(u32));
7318                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7319                        i,
7320                        readl(rxd + 0x0), readl(rxd + 0x4),
7321                        readl(rxd + 0x8), readl(rxd + 0xc));
7322         }
7323
7324         for (i = 0; i < 6; i++) {
7325                 unsigned long rxd;
7326
7327                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7328                         + (i * sizeof(struct tg3_rx_buffer_desc));
7329                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7330                        i,
7331                        readl(rxd + 0x0), readl(rxd + 0x4),
7332                        readl(rxd + 0x8), readl(rxd + 0xc));
7333                 rxd += (4 * sizeof(u32));
7334                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7335                        i,
7336                        readl(rxd + 0x0), readl(rxd + 0x4),
7337                        readl(rxd + 0x8), readl(rxd + 0xc));
7338         }
7339 }
7340 #endif
7341
7342 static struct net_device_stats *tg3_get_stats(struct net_device *);
7343 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7344
7345 static int tg3_close(struct net_device *dev)
7346 {
7347         struct tg3 *tp = netdev_priv(dev);
7348
7349         /* Calling flush_scheduled_work() may deadlock because
7350          * linkwatch_event() may be on the workqueue and it will try to get
7351          * the rtnl_lock which we are holding.
7352          */
7353         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7354                 msleep(1);
7355
7356         netif_stop_queue(dev);
7357
7358         del_timer_sync(&tp->timer);
7359
7360         tg3_full_lock(tp, 1);
7361 #if 0
7362         tg3_dump_state(tp);
7363 #endif
7364
7365         tg3_disable_ints(tp);
7366
7367         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7368         tg3_free_rings(tp);
7369         tp->tg3_flags &=
7370                 ~(TG3_FLAG_INIT_COMPLETE |
7371                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7372
7373         tg3_full_unlock(tp);
7374
7375         free_irq(tp->pdev->irq, dev);
7376         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7377                 pci_disable_msi(tp->pdev);
7378                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7379         }
7380
7381         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7382                sizeof(tp->net_stats_prev));
7383         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7384                sizeof(tp->estats_prev));
7385
7386         tg3_free_consistent(tp);
7387
7388         tg3_set_power_state(tp, PCI_D3hot);
7389
7390         netif_carrier_off(tp->dev);
7391
7392         return 0;
7393 }
7394
7395 static inline unsigned long get_stat64(tg3_stat64_t *val)
7396 {
7397         unsigned long ret;
7398
7399 #if (BITS_PER_LONG == 32)
7400         ret = val->low;
7401 #else
7402         ret = ((u64)val->high << 32) | ((u64)val->low);
7403 #endif
7404         return ret;
7405 }
7406
7407 static unsigned long calc_crc_errors(struct tg3 *tp)
7408 {
7409         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7410
7411         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7412             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7413              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7414                 u32 val;
7415
7416                 spin_lock_bh(&tp->lock);
7417                 if (!tg3_readphy(tp, 0x1e, &val)) {
7418                         tg3_writephy(tp, 0x1e, val | 0x8000);
7419                         tg3_readphy(tp, 0x14, &val);
7420                 } else
7421                         val = 0;
7422                 spin_unlock_bh(&tp->lock);
7423
7424                 tp->phy_crc_errors += val;
7425
7426                 return tp->phy_crc_errors;
7427         }
7428
7429         return get_stat64(&hw_stats->rx_fcs_errors);
7430 }
7431
7432 #define ESTAT_ADD(member) \
7433         estats->member =        old_estats->member + \
7434                                 get_stat64(&hw_stats->member)
7435
7436 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7437 {
7438         struct tg3_ethtool_stats *estats = &tp->estats;
7439         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7440         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7441
7442         if (!hw_stats)
7443                 return old_estats;
7444
7445         ESTAT_ADD(rx_octets);
7446         ESTAT_ADD(rx_fragments);
7447         ESTAT_ADD(rx_ucast_packets);
7448         ESTAT_ADD(rx_mcast_packets);
7449         ESTAT_ADD(rx_bcast_packets);
7450         ESTAT_ADD(rx_fcs_errors);
7451         ESTAT_ADD(rx_align_errors);
7452         ESTAT_ADD(rx_xon_pause_rcvd);
7453         ESTAT_ADD(rx_xoff_pause_rcvd);
7454         ESTAT_ADD(rx_mac_ctrl_rcvd);
7455         ESTAT_ADD(rx_xoff_entered);
7456         ESTAT_ADD(rx_frame_too_long_errors);
7457         ESTAT_ADD(rx_jabbers);
7458         ESTAT_ADD(rx_undersize_packets);
7459         ESTAT_ADD(rx_in_length_errors);
7460         ESTAT_ADD(rx_out_length_errors);
7461         ESTAT_ADD(rx_64_or_less_octet_packets);
7462         ESTAT_ADD(rx_65_to_127_octet_packets);
7463         ESTAT_ADD(rx_128_to_255_octet_packets);
7464         ESTAT_ADD(rx_256_to_511_octet_packets);
7465         ESTAT_ADD(rx_512_to_1023_octet_packets);
7466         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7467         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7468         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7469         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7470         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7471
7472         ESTAT_ADD(tx_octets);
7473         ESTAT_ADD(tx_collisions);
7474         ESTAT_ADD(tx_xon_sent);
7475         ESTAT_ADD(tx_xoff_sent);
7476         ESTAT_ADD(tx_flow_control);
7477         ESTAT_ADD(tx_mac_errors);
7478         ESTAT_ADD(tx_single_collisions);
7479         ESTAT_ADD(tx_mult_collisions);
7480         ESTAT_ADD(tx_deferred);
7481         ESTAT_ADD(tx_excessive_collisions);
7482         ESTAT_ADD(tx_late_collisions);
7483         ESTAT_ADD(tx_collide_2times);
7484         ESTAT_ADD(tx_collide_3times);
7485         ESTAT_ADD(tx_collide_4times);
7486         ESTAT_ADD(tx_collide_5times);
7487         ESTAT_ADD(tx_collide_6times);
7488         ESTAT_ADD(tx_collide_7times);
7489         ESTAT_ADD(tx_collide_8times);
7490         ESTAT_ADD(tx_collide_9times);
7491         ESTAT_ADD(tx_collide_10times);
7492         ESTAT_ADD(tx_collide_11times);
7493         ESTAT_ADD(tx_collide_12times);
7494         ESTAT_ADD(tx_collide_13times);
7495         ESTAT_ADD(tx_collide_14times);
7496         ESTAT_ADD(tx_collide_15times);
7497         ESTAT_ADD(tx_ucast_packets);
7498         ESTAT_ADD(tx_mcast_packets);
7499         ESTAT_ADD(tx_bcast_packets);
7500         ESTAT_ADD(tx_carrier_sense_errors);
7501         ESTAT_ADD(tx_discards);
7502         ESTAT_ADD(tx_errors);
7503
7504         ESTAT_ADD(dma_writeq_full);
7505         ESTAT_ADD(dma_write_prioq_full);
7506         ESTAT_ADD(rxbds_empty);
7507         ESTAT_ADD(rx_discards);
7508         ESTAT_ADD(rx_errors);
7509         ESTAT_ADD(rx_threshold_hit);
7510
7511         ESTAT_ADD(dma_readq_full);
7512         ESTAT_ADD(dma_read_prioq_full);
7513         ESTAT_ADD(tx_comp_queue_full);
7514
7515         ESTAT_ADD(ring_set_send_prod_index);
7516         ESTAT_ADD(ring_status_update);
7517         ESTAT_ADD(nic_irqs);
7518         ESTAT_ADD(nic_avoided_irqs);
7519         ESTAT_ADD(nic_tx_threshold_hit);
7520
7521         return estats;
7522 }
7523
7524 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7525 {
7526         struct tg3 *tp = netdev_priv(dev);
7527         struct net_device_stats *stats = &tp->net_stats;
7528         struct net_device_stats *old_stats = &tp->net_stats_prev;
7529         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7530
7531         if (!hw_stats)
7532                 return old_stats;
7533
7534         stats->rx_packets = old_stats->rx_packets +
7535                 get_stat64(&hw_stats->rx_ucast_packets) +
7536                 get_stat64(&hw_stats->rx_mcast_packets) +
7537                 get_stat64(&hw_stats->rx_bcast_packets);
7538
7539         stats->tx_packets = old_stats->tx_packets +
7540                 get_stat64(&hw_stats->tx_ucast_packets) +
7541                 get_stat64(&hw_stats->tx_mcast_packets) +
7542                 get_stat64(&hw_stats->tx_bcast_packets);
7543
7544         stats->rx_bytes = old_stats->rx_bytes +
7545                 get_stat64(&hw_stats->rx_octets);
7546         stats->tx_bytes = old_stats->tx_bytes +
7547                 get_stat64(&hw_stats->tx_octets);
7548
7549         stats->rx_errors = old_stats->rx_errors +
7550                 get_stat64(&hw_stats->rx_errors);
7551         stats->tx_errors = old_stats->tx_errors +
7552                 get_stat64(&hw_stats->tx_errors) +
7553                 get_stat64(&hw_stats->tx_mac_errors) +
7554                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7555                 get_stat64(&hw_stats->tx_discards);
7556
7557         stats->multicast = old_stats->multicast +
7558                 get_stat64(&hw_stats->rx_mcast_packets);
7559         stats->collisions = old_stats->collisions +
7560                 get_stat64(&hw_stats->tx_collisions);
7561
7562         stats->rx_length_errors = old_stats->rx_length_errors +
7563                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7564                 get_stat64(&hw_stats->rx_undersize_packets);
7565
7566         stats->rx_over_errors = old_stats->rx_over_errors +
7567                 get_stat64(&hw_stats->rxbds_empty);
7568         stats->rx_frame_errors = old_stats->rx_frame_errors +
7569                 get_stat64(&hw_stats->rx_align_errors);
7570         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7571                 get_stat64(&hw_stats->tx_discards);
7572         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7573                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7574
7575         stats->rx_crc_errors = old_stats->rx_crc_errors +
7576                 calc_crc_errors(tp);
7577
7578         stats->rx_missed_errors = old_stats->rx_missed_errors +
7579                 get_stat64(&hw_stats->rx_discards);
7580
7581         return stats;
7582 }
7583
7584 static inline u32 calc_crc(unsigned char *buf, int len)
7585 {
7586         u32 reg;
7587         u32 tmp;
7588         int j, k;
7589
7590         reg = 0xffffffff;
7591
7592         for (j = 0; j < len; j++) {
7593                 reg ^= buf[j];
7594
7595                 for (k = 0; k < 8; k++) {
7596                         tmp = reg & 0x01;
7597
7598                         reg >>= 1;
7599
7600                         if (tmp) {
7601                                 reg ^= 0xedb88320;
7602                         }
7603                 }
7604         }
7605
7606         return ~reg;
7607 }
7608
7609 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7610 {
7611         /* accept or reject all multicast frames */
7612         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7613         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7614         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7615         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7616 }
7617
7618 static void __tg3_set_rx_mode(struct net_device *dev)
7619 {
7620         struct tg3 *tp = netdev_priv(dev);
7621         u32 rx_mode;
7622
7623         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7624                                   RX_MODE_KEEP_VLAN_TAG);
7625
7626         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7627          * flag clear.
7628          */
7629 #if TG3_VLAN_TAG_USED
7630         if (!tp->vlgrp &&
7631             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7632                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7633 #else
7634         /* By definition, VLAN is disabled always in this
7635          * case.
7636          */
7637         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7638                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7639 #endif
7640
7641         if (dev->flags & IFF_PROMISC) {
7642                 /* Promiscuous mode. */
7643                 rx_mode |= RX_MODE_PROMISC;
7644         } else if (dev->flags & IFF_ALLMULTI) {
7645                 /* Accept all multicast. */
7646                 tg3_set_multi (tp, 1);
7647         } else if (dev->mc_count < 1) {
7648                 /* Reject all multicast. */
7649                 tg3_set_multi (tp, 0);
7650         } else {
7651                 /* Accept one or more multicast(s). */
7652                 struct dev_mc_list *mclist;
7653                 unsigned int i;
7654                 u32 mc_filter[4] = { 0, };
7655                 u32 regidx;
7656                 u32 bit;
7657                 u32 crc;
7658
7659                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7660                      i++, mclist = mclist->next) {
7661
7662                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7663                         bit = ~crc & 0x7f;
7664                         regidx = (bit & 0x60) >> 5;
7665                         bit &= 0x1f;
7666                         mc_filter[regidx] |= (1 << bit);
7667                 }
7668
7669                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7670                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7671                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7672                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7673         }
7674
7675         if (rx_mode != tp->rx_mode) {
7676                 tp->rx_mode = rx_mode;
7677                 tw32_f(MAC_RX_MODE, rx_mode);
7678                 udelay(10);
7679         }
7680 }
7681
7682 static void tg3_set_rx_mode(struct net_device *dev)
7683 {
7684         struct tg3 *tp = netdev_priv(dev);
7685
7686         if (!netif_running(dev))
7687                 return;
7688
7689         tg3_full_lock(tp, 0);
7690         __tg3_set_rx_mode(dev);
7691         tg3_full_unlock(tp);
7692 }
7693
7694 #define TG3_REGDUMP_LEN         (32 * 1024)
7695
7696 static int tg3_get_regs_len(struct net_device *dev)
7697 {
7698         return TG3_REGDUMP_LEN;
7699 }
7700
7701 static void tg3_get_regs(struct net_device *dev,
7702                 struct ethtool_regs *regs, void *_p)
7703 {
7704         u32 *p = _p;
7705         struct tg3 *tp = netdev_priv(dev);
7706         u8 *orig_p = _p;
7707         int i;
7708
7709         regs->version = 0;
7710
7711         memset(p, 0, TG3_REGDUMP_LEN);
7712
7713         if (tp->link_config.phy_is_low_power)
7714                 return;
7715
7716         tg3_full_lock(tp, 0);
7717
7718 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7719 #define GET_REG32_LOOP(base,len)                \
7720 do {    p = (u32 *)(orig_p + (base));           \
7721         for (i = 0; i < len; i += 4)            \
7722                 __GET_REG32((base) + i);        \
7723 } while (0)
7724 #define GET_REG32_1(reg)                        \
7725 do {    p = (u32 *)(orig_p + (reg));            \
7726         __GET_REG32((reg));                     \
7727 } while (0)
7728
7729         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7730         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7731         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7732         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7733         GET_REG32_1(SNDDATAC_MODE);
7734         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7735         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7736         GET_REG32_1(SNDBDC_MODE);
7737         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7738         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7739         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7740         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7741         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7742         GET_REG32_1(RCVDCC_MODE);
7743         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7744         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7745         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7746         GET_REG32_1(MBFREE_MODE);
7747         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7748         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7749         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7750         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7751         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7752         GET_REG32_1(RX_CPU_MODE);
7753         GET_REG32_1(RX_CPU_STATE);
7754         GET_REG32_1(RX_CPU_PGMCTR);
7755         GET_REG32_1(RX_CPU_HWBKPT);
7756         GET_REG32_1(TX_CPU_MODE);
7757         GET_REG32_1(TX_CPU_STATE);
7758         GET_REG32_1(TX_CPU_PGMCTR);
7759         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7760         GET_REG32_LOOP(FTQ_RESET, 0x120);
7761         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7762         GET_REG32_1(DMAC_MODE);
7763         GET_REG32_LOOP(GRC_MODE, 0x4c);
7764         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7765                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7766
7767 #undef __GET_REG32
7768 #undef GET_REG32_LOOP
7769 #undef GET_REG32_1
7770
7771         tg3_full_unlock(tp);
7772 }
7773
7774 static int tg3_get_eeprom_len(struct net_device *dev)
7775 {
7776         struct tg3 *tp = netdev_priv(dev);
7777
7778         return tp->nvram_size;
7779 }
7780
7781 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7782 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7783
7784 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7785 {
7786         struct tg3 *tp = netdev_priv(dev);
7787         int ret;
7788         u8  *pd;
7789         u32 i, offset, len, val, b_offset, b_count;
7790
7791         if (tp->link_config.phy_is_low_power)
7792                 return -EAGAIN;
7793
7794         offset = eeprom->offset;
7795         len = eeprom->len;
7796         eeprom->len = 0;
7797
7798         eeprom->magic = TG3_EEPROM_MAGIC;
7799
7800         if (offset & 3) {
7801                 /* adjustments to start on required 4 byte boundary */
7802                 b_offset = offset & 3;
7803                 b_count = 4 - b_offset;
7804                 if (b_count > len) {
7805                         /* i.e. offset=1 len=2 */
7806                         b_count = len;
7807                 }
7808                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7809                 if (ret)
7810                         return ret;
7811                 val = cpu_to_le32(val);
7812                 memcpy(data, ((char*)&val) + b_offset, b_count);
7813                 len -= b_count;
7814                 offset += b_count;
7815                 eeprom->len += b_count;
7816         }
7817
7818         /* read bytes upto the last 4 byte boundary */
7819         pd = &data[eeprom->len];
7820         for (i = 0; i < (len - (len & 3)); i += 4) {
7821                 ret = tg3_nvram_read(tp, offset + i, &val);
7822                 if (ret) {
7823                         eeprom->len += i;
7824                         return ret;
7825                 }
7826                 val = cpu_to_le32(val);
7827                 memcpy(pd + i, &val, 4);
7828         }
7829         eeprom->len += i;
7830
7831         if (len & 3) {
7832                 /* read last bytes not ending on 4 byte boundary */
7833                 pd = &data[eeprom->len];
7834                 b_count = len & 3;
7835                 b_offset = offset + len - b_count;
7836                 ret = tg3_nvram_read(tp, b_offset, &val);
7837                 if (ret)
7838                         return ret;
7839                 val = cpu_to_le32(val);
7840                 memcpy(pd, ((char*)&val), b_count);
7841                 eeprom->len += b_count;
7842         }
7843         return 0;
7844 }
7845
7846 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7847
7848 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7849 {
7850         struct tg3 *tp = netdev_priv(dev);
7851         int ret;
7852         u32 offset, len, b_offset, odd_len, start, end;
7853         u8 *buf;
7854
7855         if (tp->link_config.phy_is_low_power)
7856                 return -EAGAIN;
7857
7858         if (eeprom->magic != TG3_EEPROM_MAGIC)
7859                 return -EINVAL;
7860
7861         offset = eeprom->offset;
7862         len = eeprom->len;
7863
7864         if ((b_offset = (offset & 3))) {
7865                 /* adjustments to start on required 4 byte boundary */
7866                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7867                 if (ret)
7868                         return ret;
7869                 start = cpu_to_le32(start);
7870                 len += b_offset;
7871                 offset &= ~3;
7872                 if (len < 4)
7873                         len = 4;
7874         }
7875
7876         odd_len = 0;
7877         if (len & 3) {
7878                 /* adjustments to end on required 4 byte boundary */
7879                 odd_len = 1;
7880                 len = (len + 3) & ~3;
7881                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7882                 if (ret)
7883                         return ret;
7884                 end = cpu_to_le32(end);
7885         }
7886
7887         buf = data;
7888         if (b_offset || odd_len) {
7889                 buf = kmalloc(len, GFP_KERNEL);
7890                 if (buf == 0)
7891                         return -ENOMEM;
7892                 if (b_offset)
7893                         memcpy(buf, &start, 4);
7894                 if (odd_len)
7895                         memcpy(buf+len-4, &end, 4);
7896                 memcpy(buf + b_offset, data, eeprom->len);
7897         }
7898
7899         ret = tg3_nvram_write_block(tp, offset, len, buf);
7900
7901         if (buf != data)
7902                 kfree(buf);
7903
7904         return ret;
7905 }
7906
7907 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7908 {
7909         struct tg3 *tp = netdev_priv(dev);
7910
7911         cmd->supported = (SUPPORTED_Autoneg);
7912
7913         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7914                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7915                                    SUPPORTED_1000baseT_Full);
7916
7917         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7918                 cmd->supported |= (SUPPORTED_100baseT_Half |
7919                                   SUPPORTED_100baseT_Full |
7920                                   SUPPORTED_10baseT_Half |
7921                                   SUPPORTED_10baseT_Full |
7922                                   SUPPORTED_MII);
7923                 cmd->port = PORT_TP;
7924         } else {
7925                 cmd->supported |= SUPPORTED_FIBRE;
7926                 cmd->port = PORT_FIBRE;
7927         }
7928
7929         cmd->advertising = tp->link_config.advertising;
7930         if (netif_running(dev)) {
7931                 cmd->speed = tp->link_config.active_speed;
7932                 cmd->duplex = tp->link_config.active_duplex;
7933         }
7934         cmd->phy_address = PHY_ADDR;
7935         cmd->transceiver = 0;
7936         cmd->autoneg = tp->link_config.autoneg;
7937         cmd->maxtxpkt = 0;
7938         cmd->maxrxpkt = 0;
7939         return 0;
7940 }
7941
7942 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7943 {
7944         struct tg3 *tp = netdev_priv(dev);
7945
7946         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7947                 /* These are the only valid advertisement bits allowed.  */
7948                 if (cmd->autoneg == AUTONEG_ENABLE &&
7949                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7950                                           ADVERTISED_1000baseT_Full |
7951                                           ADVERTISED_Autoneg |
7952                                           ADVERTISED_FIBRE)))
7953                         return -EINVAL;
7954                 /* Fiber can only do SPEED_1000.  */
7955                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7956                          (cmd->speed != SPEED_1000))
7957                         return -EINVAL;
7958         /* Copper cannot force SPEED_1000.  */
7959         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7960                    (cmd->speed == SPEED_1000))
7961                 return -EINVAL;
7962         else if ((cmd->speed == SPEED_1000) &&
7963                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7964                 return -EINVAL;
7965
7966         tg3_full_lock(tp, 0);
7967
7968         tp->link_config.autoneg = cmd->autoneg;
7969         if (cmd->autoneg == AUTONEG_ENABLE) {
7970                 tp->link_config.advertising = cmd->advertising;
7971                 tp->link_config.speed = SPEED_INVALID;
7972                 tp->link_config.duplex = DUPLEX_INVALID;
7973         } else {
7974                 tp->link_config.advertising = 0;
7975                 tp->link_config.speed = cmd->speed;
7976                 tp->link_config.duplex = cmd->duplex;
7977         }
7978
7979         tp->link_config.orig_speed = tp->link_config.speed;
7980         tp->link_config.orig_duplex = tp->link_config.duplex;
7981         tp->link_config.orig_autoneg = tp->link_config.autoneg;
7982
7983         if (netif_running(dev))
7984                 tg3_setup_phy(tp, 1);
7985
7986         tg3_full_unlock(tp);
7987
7988         return 0;
7989 }
7990
7991 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7992 {
7993         struct tg3 *tp = netdev_priv(dev);
7994
7995         strcpy(info->driver, DRV_MODULE_NAME);
7996         strcpy(info->version, DRV_MODULE_VERSION);
7997         strcpy(info->fw_version, tp->fw_ver);
7998         strcpy(info->bus_info, pci_name(tp->pdev));
7999 }
8000
8001 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8002 {
8003         struct tg3 *tp = netdev_priv(dev);
8004
8005         wol->supported = WAKE_MAGIC;
8006         wol->wolopts = 0;
8007         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8008                 wol->wolopts = WAKE_MAGIC;
8009         memset(&wol->sopass, 0, sizeof(wol->sopass));
8010 }
8011
8012 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8013 {
8014         struct tg3 *tp = netdev_priv(dev);
8015
8016         if (wol->wolopts & ~WAKE_MAGIC)
8017                 return -EINVAL;
8018         if ((wol->wolopts & WAKE_MAGIC) &&
8019             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8020             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8021                 return -EINVAL;
8022
8023         spin_lock_bh(&tp->lock);
8024         if (wol->wolopts & WAKE_MAGIC)
8025                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8026         else
8027                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8028         spin_unlock_bh(&tp->lock);
8029
8030         return 0;
8031 }
8032
8033 static u32 tg3_get_msglevel(struct net_device *dev)
8034 {
8035         struct tg3 *tp = netdev_priv(dev);
8036         return tp->msg_enable;
8037 }
8038
8039 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8040 {
8041         struct tg3 *tp = netdev_priv(dev);
8042         tp->msg_enable = value;
8043 }
8044
8045 #if TG3_TSO_SUPPORT != 0
8046 static int tg3_set_tso(struct net_device *dev, u32 value)
8047 {
8048         struct tg3 *tp = netdev_priv(dev);
8049
8050         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8051                 if (value)
8052                         return -EINVAL;
8053                 return 0;
8054         }
8055         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8056             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8057                 if (value)
8058                         dev->features |= NETIF_F_TSO6;
8059                 else
8060                         dev->features &= ~NETIF_F_TSO6;
8061         }
8062         return ethtool_op_set_tso(dev, value);
8063 }
8064 #endif
8065
8066 static int tg3_nway_reset(struct net_device *dev)
8067 {
8068         struct tg3 *tp = netdev_priv(dev);
8069         u32 bmcr;
8070         int r;
8071
8072         if (!netif_running(dev))
8073                 return -EAGAIN;
8074
8075         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8076                 return -EINVAL;
8077
8078         spin_lock_bh(&tp->lock);
8079         r = -EINVAL;
8080         tg3_readphy(tp, MII_BMCR, &bmcr);
8081         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8082             ((bmcr & BMCR_ANENABLE) ||
8083              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8084                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8085                                            BMCR_ANENABLE);
8086                 r = 0;
8087         }
8088         spin_unlock_bh(&tp->lock);
8089
8090         return r;
8091 }
8092
8093 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8094 {
8095         struct tg3 *tp = netdev_priv(dev);
8096
8097         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8098         ering->rx_mini_max_pending = 0;
8099         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8100                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8101         else
8102                 ering->rx_jumbo_max_pending = 0;
8103
8104         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8105
8106         ering->rx_pending = tp->rx_pending;
8107         ering->rx_mini_pending = 0;
8108         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8109                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8110         else
8111                 ering->rx_jumbo_pending = 0;
8112
8113         ering->tx_pending = tp->tx_pending;
8114 }
8115
8116 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8117 {
8118         struct tg3 *tp = netdev_priv(dev);
8119         int irq_sync = 0, err = 0;
8120
8121         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8122             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8123             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8124             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8125             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8126              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8127                 return -EINVAL;
8128
8129         if (netif_running(dev)) {
8130                 tg3_netif_stop(tp);
8131                 irq_sync = 1;
8132         }
8133
8134         tg3_full_lock(tp, irq_sync);
8135
8136         tp->rx_pending = ering->rx_pending;
8137
8138         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8139             tp->rx_pending > 63)
8140                 tp->rx_pending = 63;
8141         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8142         tp->tx_pending = ering->tx_pending;
8143
8144         if (netif_running(dev)) {
8145                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8146                 err = tg3_restart_hw(tp, 1);
8147                 if (!err)
8148                         tg3_netif_start(tp);
8149         }
8150
8151         tg3_full_unlock(tp);
8152
8153         return err;
8154 }
8155
8156 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8157 {
8158         struct tg3 *tp = netdev_priv(dev);
8159
8160         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8161         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8162         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8163 }
8164
8165 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8166 {
8167         struct tg3 *tp = netdev_priv(dev);
8168         int irq_sync = 0, err = 0;
8169
8170         if (netif_running(dev)) {
8171                 tg3_netif_stop(tp);
8172                 irq_sync = 1;
8173         }
8174
8175         tg3_full_lock(tp, irq_sync);
8176
8177         if (epause->autoneg)
8178                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8179         else
8180                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8181         if (epause->rx_pause)
8182                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8183         else
8184                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8185         if (epause->tx_pause)
8186                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8187         else
8188                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8189
8190         if (netif_running(dev)) {
8191                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8192                 err = tg3_restart_hw(tp, 1);
8193                 if (!err)
8194                         tg3_netif_start(tp);
8195         }
8196
8197         tg3_full_unlock(tp);
8198
8199         return err;
8200 }
8201
8202 static u32 tg3_get_rx_csum(struct net_device *dev)
8203 {
8204         struct tg3 *tp = netdev_priv(dev);
8205         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8206 }
8207
8208 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8209 {
8210         struct tg3 *tp = netdev_priv(dev);
8211
8212         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8213                 if (data != 0)
8214                         return -EINVAL;
8215                 return 0;
8216         }
8217
8218         spin_lock_bh(&tp->lock);
8219         if (data)
8220                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8221         else
8222                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8223         spin_unlock_bh(&tp->lock);
8224
8225         return 0;
8226 }
8227
8228 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8229 {
8230         struct tg3 *tp = netdev_priv(dev);
8231
8232         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8233                 if (data != 0)
8234                         return -EINVAL;
8235                 return 0;
8236         }
8237
8238         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8239             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8240                 ethtool_op_set_tx_hw_csum(dev, data);
8241         else
8242                 ethtool_op_set_tx_csum(dev, data);
8243
8244         return 0;
8245 }
8246
8247 static int tg3_get_stats_count (struct net_device *dev)
8248 {
8249         return TG3_NUM_STATS;
8250 }
8251
8252 static int tg3_get_test_count (struct net_device *dev)
8253 {
8254         return TG3_NUM_TEST;
8255 }
8256
8257 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8258 {
8259         switch (stringset) {
8260         case ETH_SS_STATS:
8261                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8262                 break;
8263         case ETH_SS_TEST:
8264                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8265                 break;
8266         default:
8267                 WARN_ON(1);     /* we need a WARN() */
8268                 break;
8269         }
8270 }
8271
8272 static int tg3_phys_id(struct net_device *dev, u32 data)
8273 {
8274         struct tg3 *tp = netdev_priv(dev);
8275         int i;
8276
8277         if (!netif_running(tp->dev))
8278                 return -EAGAIN;
8279
8280         if (data == 0)
8281                 data = 2;
8282
8283         for (i = 0; i < (data * 2); i++) {
8284                 if ((i % 2) == 0)
8285                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8286                                            LED_CTRL_1000MBPS_ON |
8287                                            LED_CTRL_100MBPS_ON |
8288                                            LED_CTRL_10MBPS_ON |
8289                                            LED_CTRL_TRAFFIC_OVERRIDE |
8290                                            LED_CTRL_TRAFFIC_BLINK |
8291                                            LED_CTRL_TRAFFIC_LED);
8292
8293                 else
8294                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8295                                            LED_CTRL_TRAFFIC_OVERRIDE);
8296
8297                 if (msleep_interruptible(500))
8298                         break;
8299         }
8300         tw32(MAC_LED_CTRL, tp->led_ctrl);
8301         return 0;
8302 }
8303
8304 static void tg3_get_ethtool_stats (struct net_device *dev,
8305                                    struct ethtool_stats *estats, u64 *tmp_stats)
8306 {
8307         struct tg3 *tp = netdev_priv(dev);
8308         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8309 }
8310
8311 #define NVRAM_TEST_SIZE 0x100
8312 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8313 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8314 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8315
8316 static int tg3_test_nvram(struct tg3 *tp)
8317 {
8318         u32 *buf, csum, magic;
8319         int i, j, err = 0, size;
8320
8321         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8322                 return -EIO;
8323
8324         if (magic == TG3_EEPROM_MAGIC)
8325                 size = NVRAM_TEST_SIZE;
8326         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8327                 if ((magic & 0xe00000) == 0x200000)
8328                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8329                 else
8330                         return 0;
8331         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8332                 size = NVRAM_SELFBOOT_HW_SIZE;
8333         else
8334                 return -EIO;
8335
8336         buf = kmalloc(size, GFP_KERNEL);
8337         if (buf == NULL)
8338                 return -ENOMEM;
8339
8340         err = -EIO;
8341         for (i = 0, j = 0; i < size; i += 4, j++) {
8342                 u32 val;
8343
8344                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8345                         break;
8346                 buf[j] = cpu_to_le32(val);
8347         }
8348         if (i < size)
8349                 goto out;
8350
8351         /* Selfboot format */
8352         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8353             TG3_EEPROM_MAGIC_FW) {
8354                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8355
8356                 for (i = 0; i < size; i++)
8357                         csum8 += buf8[i];
8358
8359                 if (csum8 == 0) {
8360                         err = 0;
8361                         goto out;
8362                 }
8363
8364                 err = -EIO;
8365                 goto out;
8366         }
8367
8368         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8369             TG3_EEPROM_MAGIC_HW) {
8370                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8371                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8372                 u8 *buf8 = (u8 *) buf;
8373                 int j, k;
8374
8375                 /* Separate the parity bits and the data bytes.  */
8376                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8377                         if ((i == 0) || (i == 8)) {
8378                                 int l;
8379                                 u8 msk;
8380
8381                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8382                                         parity[k++] = buf8[i] & msk;
8383                                 i++;
8384                         }
8385                         else if (i == 16) {
8386                                 int l;
8387                                 u8 msk;
8388
8389                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8390                                         parity[k++] = buf8[i] & msk;
8391                                 i++;
8392
8393                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8394                                         parity[k++] = buf8[i] & msk;
8395                                 i++;
8396                         }
8397                         data[j++] = buf8[i];
8398                 }
8399
8400                 err = -EIO;
8401                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8402                         u8 hw8 = hweight8(data[i]);
8403
8404                         if ((hw8 & 0x1) && parity[i])
8405                                 goto out;
8406                         else if (!(hw8 & 0x1) && !parity[i])
8407                                 goto out;
8408                 }
8409                 err = 0;
8410                 goto out;
8411         }
8412
8413         /* Bootstrap checksum at offset 0x10 */
8414         csum = calc_crc((unsigned char *) buf, 0x10);
8415         if(csum != cpu_to_le32(buf[0x10/4]))
8416                 goto out;
8417
8418         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8419         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8420         if (csum != cpu_to_le32(buf[0xfc/4]))
8421                  goto out;
8422
8423         err = 0;
8424
8425 out:
8426         kfree(buf);
8427         return err;
8428 }
8429
8430 #define TG3_SERDES_TIMEOUT_SEC  2
8431 #define TG3_COPPER_TIMEOUT_SEC  6
8432
8433 static int tg3_test_link(struct tg3 *tp)
8434 {
8435         int i, max;
8436
8437         if (!netif_running(tp->dev))
8438                 return -ENODEV;
8439
8440         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8441                 max = TG3_SERDES_TIMEOUT_SEC;
8442         else
8443                 max = TG3_COPPER_TIMEOUT_SEC;
8444
8445         for (i = 0; i < max; i++) {
8446                 if (netif_carrier_ok(tp->dev))
8447                         return 0;
8448
8449                 if (msleep_interruptible(1000))
8450                         break;
8451         }
8452
8453         return -EIO;
8454 }
8455
8456 /* Only test the commonly used registers */
8457 static int tg3_test_registers(struct tg3 *tp)
8458 {
8459         int i, is_5705, is_5750;
8460         u32 offset, read_mask, write_mask, val, save_val, read_val;
8461         static struct {
8462                 u16 offset;
8463                 u16 flags;
8464 #define TG3_FL_5705     0x1
8465 #define TG3_FL_NOT_5705 0x2
8466 #define TG3_FL_NOT_5788 0x4
8467 #define TG3_FL_NOT_5750 0x8
8468                 u32 read_mask;
8469                 u32 write_mask;
8470         } reg_tbl[] = {
8471                 /* MAC Control Registers */
8472                 { MAC_MODE, TG3_FL_NOT_5705,
8473                         0x00000000, 0x00ef6f8c },
8474                 { MAC_MODE, TG3_FL_5705,
8475                         0x00000000, 0x01ef6b8c },
8476                 { MAC_STATUS, TG3_FL_NOT_5705,
8477                         0x03800107, 0x00000000 },
8478                 { MAC_STATUS, TG3_FL_5705,
8479                         0x03800100, 0x00000000 },
8480                 { MAC_ADDR_0_HIGH, 0x0000,
8481                         0x00000000, 0x0000ffff },
8482                 { MAC_ADDR_0_LOW, 0x0000,
8483                         0x00000000, 0xffffffff },
8484                 { MAC_RX_MTU_SIZE, 0x0000,
8485                         0x00000000, 0x0000ffff },
8486                 { MAC_TX_MODE, 0x0000,
8487                         0x00000000, 0x00000070 },
8488                 { MAC_TX_LENGTHS, 0x0000,
8489                         0x00000000, 0x00003fff },
8490                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8491                         0x00000000, 0x000007fc },
8492                 { MAC_RX_MODE, TG3_FL_5705,
8493                         0x00000000, 0x000007dc },
8494                 { MAC_HASH_REG_0, 0x0000,
8495                         0x00000000, 0xffffffff },
8496                 { MAC_HASH_REG_1, 0x0000,
8497                         0x00000000, 0xffffffff },
8498                 { MAC_HASH_REG_2, 0x0000,
8499                         0x00000000, 0xffffffff },
8500                 { MAC_HASH_REG_3, 0x0000,
8501                         0x00000000, 0xffffffff },
8502
8503                 /* Receive Data and Receive BD Initiator Control Registers. */
8504                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8505                         0x00000000, 0xffffffff },
8506                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8507                         0x00000000, 0xffffffff },
8508                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8509                         0x00000000, 0x00000003 },
8510                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8511                         0x00000000, 0xffffffff },
8512                 { RCVDBDI_STD_BD+0, 0x0000,
8513                         0x00000000, 0xffffffff },
8514                 { RCVDBDI_STD_BD+4, 0x0000,
8515                         0x00000000, 0xffffffff },
8516                 { RCVDBDI_STD_BD+8, 0x0000,
8517                         0x00000000, 0xffff0002 },
8518                 { RCVDBDI_STD_BD+0xc, 0x0000,
8519                         0x00000000, 0xffffffff },
8520
8521                 /* Receive BD Initiator Control Registers. */
8522                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8523                         0x00000000, 0xffffffff },
8524                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8525                         0x00000000, 0x000003ff },
8526                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8527                         0x00000000, 0xffffffff },
8528
8529                 /* Host Coalescing Control Registers. */
8530                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8531                         0x00000000, 0x00000004 },
8532                 { HOSTCC_MODE, TG3_FL_5705,
8533                         0x00000000, 0x000000f6 },
8534                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8535                         0x00000000, 0xffffffff },
8536                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8537                         0x00000000, 0x000003ff },
8538                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8539                         0x00000000, 0xffffffff },
8540                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8541                         0x00000000, 0x000003ff },
8542                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8543                         0x00000000, 0xffffffff },
8544                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8545                         0x00000000, 0x000000ff },
8546                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8547                         0x00000000, 0xffffffff },
8548                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8549                         0x00000000, 0x000000ff },
8550                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8551                         0x00000000, 0xffffffff },
8552                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8553                         0x00000000, 0xffffffff },
8554                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8555                         0x00000000, 0xffffffff },
8556                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8557                         0x00000000, 0x000000ff },
8558                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8559                         0x00000000, 0xffffffff },
8560                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8561                         0x00000000, 0x000000ff },
8562                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8563                         0x00000000, 0xffffffff },
8564                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8565                         0x00000000, 0xffffffff },
8566                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8567                         0x00000000, 0xffffffff },
8568                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8569                         0x00000000, 0xffffffff },
8570                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8571                         0x00000000, 0xffffffff },
8572                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8573                         0xffffffff, 0x00000000 },
8574                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8575                         0xffffffff, 0x00000000 },
8576
8577                 /* Buffer Manager Control Registers. */
8578                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8579                         0x00000000, 0x007fff80 },
8580                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8581                         0x00000000, 0x007fffff },
8582                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8583                         0x00000000, 0x0000003f },
8584                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8585                         0x00000000, 0x000001ff },
8586                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8587                         0x00000000, 0x000001ff },
8588                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8589                         0xffffffff, 0x00000000 },
8590                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8591                         0xffffffff, 0x00000000 },
8592
8593                 /* Mailbox Registers */
8594                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8595                         0x00000000, 0x000001ff },
8596                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8597                         0x00000000, 0x000001ff },
8598                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8599                         0x00000000, 0x000007ff },
8600                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8601                         0x00000000, 0x000001ff },
8602
8603                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8604         };
8605
8606         is_5705 = is_5750 = 0;
8607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8608                 is_5705 = 1;
8609                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8610                         is_5750 = 1;
8611         }
8612
8613         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8614                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8615                         continue;
8616
8617                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8618                         continue;
8619
8620                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8621                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8622                         continue;
8623
8624                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8625                         continue;
8626
8627                 offset = (u32) reg_tbl[i].offset;
8628                 read_mask = reg_tbl[i].read_mask;
8629                 write_mask = reg_tbl[i].write_mask;
8630
8631                 /* Save the original register content */
8632                 save_val = tr32(offset);
8633
8634                 /* Determine the read-only value. */
8635                 read_val = save_val & read_mask;
8636
8637                 /* Write zero to the register, then make sure the read-only bits
8638                  * are not changed and the read/write bits are all zeros.
8639                  */
8640                 tw32(offset, 0);
8641
8642                 val = tr32(offset);
8643
8644                 /* Test the read-only and read/write bits. */
8645                 if (((val & read_mask) != read_val) || (val & write_mask))
8646                         goto out;
8647
8648                 /* Write ones to all the bits defined by RdMask and WrMask, then
8649                  * make sure the read-only bits are not changed and the
8650                  * read/write bits are all ones.
8651                  */
8652                 tw32(offset, read_mask | write_mask);
8653
8654                 val = tr32(offset);
8655
8656                 /* Test the read-only bits. */
8657                 if ((val & read_mask) != read_val)
8658                         goto out;
8659
8660                 /* Test the read/write bits. */
8661                 if ((val & write_mask) != write_mask)
8662                         goto out;
8663
8664                 tw32(offset, save_val);
8665         }
8666
8667         return 0;
8668
8669 out:
8670         if (netif_msg_hw(tp))
8671                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8672                        offset);
8673         tw32(offset, save_val);
8674         return -EIO;
8675 }
8676
8677 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8678 {
8679         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8680         int i;
8681         u32 j;
8682
8683         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8684                 for (j = 0; j < len; j += 4) {
8685                         u32 val;
8686
8687                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8688                         tg3_read_mem(tp, offset + j, &val);
8689                         if (val != test_pattern[i])
8690                                 return -EIO;
8691                 }
8692         }
8693         return 0;
8694 }
8695
8696 static int tg3_test_memory(struct tg3 *tp)
8697 {
8698         static struct mem_entry {
8699                 u32 offset;
8700                 u32 len;
8701         } mem_tbl_570x[] = {
8702                 { 0x00000000, 0x00b50},
8703                 { 0x00002000, 0x1c000},
8704                 { 0xffffffff, 0x00000}
8705         }, mem_tbl_5705[] = {
8706                 { 0x00000100, 0x0000c},
8707                 { 0x00000200, 0x00008},
8708                 { 0x00004000, 0x00800},
8709                 { 0x00006000, 0x01000},
8710                 { 0x00008000, 0x02000},
8711                 { 0x00010000, 0x0e000},
8712                 { 0xffffffff, 0x00000}
8713         }, mem_tbl_5755[] = {
8714                 { 0x00000200, 0x00008},
8715                 { 0x00004000, 0x00800},
8716                 { 0x00006000, 0x00800},
8717                 { 0x00008000, 0x02000},
8718                 { 0x00010000, 0x0c000},
8719                 { 0xffffffff, 0x00000}
8720         }, mem_tbl_5906[] = {
8721                 { 0x00000200, 0x00008},
8722                 { 0x00004000, 0x00400},
8723                 { 0x00006000, 0x00400},
8724                 { 0x00008000, 0x01000},
8725                 { 0x00010000, 0x01000},
8726                 { 0xffffffff, 0x00000}
8727         };
8728         struct mem_entry *mem_tbl;
8729         int err = 0;
8730         int i;
8731
8732         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8733                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8734                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8735                         mem_tbl = mem_tbl_5755;
8736                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8737                         mem_tbl = mem_tbl_5906;
8738                 else
8739                         mem_tbl = mem_tbl_5705;
8740         } else
8741                 mem_tbl = mem_tbl_570x;
8742
8743         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8744                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8745                     mem_tbl[i].len)) != 0)
8746                         break;
8747         }
8748
8749         return err;
8750 }
8751
8752 #define TG3_MAC_LOOPBACK        0
8753 #define TG3_PHY_LOOPBACK        1
8754
8755 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8756 {
8757         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8758         u32 desc_idx;
8759         struct sk_buff *skb, *rx_skb;
8760         u8 *tx_data;
8761         dma_addr_t map;
8762         int num_pkts, tx_len, rx_len, i, err;
8763         struct tg3_rx_buffer_desc *desc;
8764
8765         if (loopback_mode == TG3_MAC_LOOPBACK) {
8766                 /* HW errata - mac loopback fails in some cases on 5780.
8767                  * Normal traffic and PHY loopback are not affected by
8768                  * errata.
8769                  */
8770                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8771                         return 0;
8772
8773                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8774                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8775                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8776                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8777                 else
8778                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8779                 tw32(MAC_MODE, mac_mode);
8780         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8781                 u32 val;
8782
8783                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8784                         u32 phytest;
8785
8786                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8787                                 u32 phy;
8788
8789                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8790                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8791                                 if (!tg3_readphy(tp, 0x1b, &phy))
8792                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8793                                 if (!tg3_readphy(tp, 0x10, &phy))
8794                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8795                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8796                         }
8797                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8798                 } else
8799                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8800
8801                 tg3_writephy(tp, MII_BMCR, val);
8802                 udelay(40);
8803
8804                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8805                            MAC_MODE_LINK_POLARITY;
8806                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8807                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8808                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8809                 } else
8810                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8811
8812                 /* reset to prevent losing 1st rx packet intermittently */
8813                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8814                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8815                         udelay(10);
8816                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8817                 }
8818                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8819                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8820                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8821                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8822                 }
8823                 tw32(MAC_MODE, mac_mode);
8824         }
8825         else
8826                 return -EINVAL;
8827
8828         err = -EIO;
8829
8830         tx_len = 1514;
8831         skb = netdev_alloc_skb(tp->dev, tx_len);
8832         if (!skb)
8833                 return -ENOMEM;
8834
8835         tx_data = skb_put(skb, tx_len);
8836         memcpy(tx_data, tp->dev->dev_addr, 6);
8837         memset(tx_data + 6, 0x0, 8);
8838
8839         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8840
8841         for (i = 14; i < tx_len; i++)
8842                 tx_data[i] = (u8) (i & 0xff);
8843
8844         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8845
8846         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8847              HOSTCC_MODE_NOW);
8848
8849         udelay(10);
8850
8851         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8852
8853         num_pkts = 0;
8854
8855         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8856
8857         tp->tx_prod++;
8858         num_pkts++;
8859
8860         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8861                      tp->tx_prod);
8862         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8863
8864         udelay(10);
8865
8866         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8867         for (i = 0; i < 25; i++) {
8868                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8869                        HOSTCC_MODE_NOW);
8870
8871                 udelay(10);
8872
8873                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8874                 rx_idx = tp->hw_status->idx[0].rx_producer;
8875                 if ((tx_idx == tp->tx_prod) &&
8876                     (rx_idx == (rx_start_idx + num_pkts)))
8877                         break;
8878         }
8879
8880         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8881         dev_kfree_skb(skb);
8882
8883         if (tx_idx != tp->tx_prod)
8884                 goto out;
8885
8886         if (rx_idx != rx_start_idx + num_pkts)
8887                 goto out;
8888
8889         desc = &tp->rx_rcb[rx_start_idx];
8890         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8891         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8892         if (opaque_key != RXD_OPAQUE_RING_STD)
8893                 goto out;
8894
8895         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8896             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8897                 goto out;
8898
8899         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8900         if (rx_len != tx_len)
8901                 goto out;
8902
8903         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8904
8905         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8906         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8907
8908         for (i = 14; i < tx_len; i++) {
8909                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8910                         goto out;
8911         }
8912         err = 0;
8913
8914         /* tg3_free_rings will unmap and free the rx_skb */
8915 out:
8916         return err;
8917 }
8918
8919 #define TG3_MAC_LOOPBACK_FAILED         1
8920 #define TG3_PHY_LOOPBACK_FAILED         2
8921 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8922                                          TG3_PHY_LOOPBACK_FAILED)
8923
8924 static int tg3_test_loopback(struct tg3 *tp)
8925 {
8926         int err = 0;
8927
8928         if (!netif_running(tp->dev))
8929                 return TG3_LOOPBACK_FAILED;
8930
8931         err = tg3_reset_hw(tp, 1);
8932         if (err)
8933                 return TG3_LOOPBACK_FAILED;
8934
8935         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8936                 err |= TG3_MAC_LOOPBACK_FAILED;
8937         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8938                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8939                         err |= TG3_PHY_LOOPBACK_FAILED;
8940         }
8941
8942         return err;
8943 }
8944
8945 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8946                           u64 *data)
8947 {
8948         struct tg3 *tp = netdev_priv(dev);
8949
8950         if (tp->link_config.phy_is_low_power)
8951                 tg3_set_power_state(tp, PCI_D0);
8952
8953         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8954
8955         if (tg3_test_nvram(tp) != 0) {
8956                 etest->flags |= ETH_TEST_FL_FAILED;
8957                 data[0] = 1;
8958         }
8959         if (tg3_test_link(tp) != 0) {
8960                 etest->flags |= ETH_TEST_FL_FAILED;
8961                 data[1] = 1;
8962         }
8963         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8964                 int err, irq_sync = 0;
8965
8966                 if (netif_running(dev)) {
8967                         tg3_netif_stop(tp);
8968                         irq_sync = 1;
8969                 }
8970
8971                 tg3_full_lock(tp, irq_sync);
8972
8973                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8974                 err = tg3_nvram_lock(tp);
8975                 tg3_halt_cpu(tp, RX_CPU_BASE);
8976                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8977                         tg3_halt_cpu(tp, TX_CPU_BASE);
8978                 if (!err)
8979                         tg3_nvram_unlock(tp);
8980
8981                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8982                         tg3_phy_reset(tp);
8983
8984                 if (tg3_test_registers(tp) != 0) {
8985                         etest->flags |= ETH_TEST_FL_FAILED;
8986                         data[2] = 1;
8987                 }
8988                 if (tg3_test_memory(tp) != 0) {
8989                         etest->flags |= ETH_TEST_FL_FAILED;
8990                         data[3] = 1;
8991                 }
8992                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8993                         etest->flags |= ETH_TEST_FL_FAILED;
8994
8995                 tg3_full_unlock(tp);
8996
8997                 if (tg3_test_interrupt(tp) != 0) {
8998                         etest->flags |= ETH_TEST_FL_FAILED;
8999                         data[5] = 1;
9000                 }
9001
9002                 tg3_full_lock(tp, 0);
9003
9004                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9005                 if (netif_running(dev)) {
9006                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9007                         if (!tg3_restart_hw(tp, 1))
9008                                 tg3_netif_start(tp);
9009                 }
9010
9011                 tg3_full_unlock(tp);
9012         }
9013         if (tp->link_config.phy_is_low_power)
9014                 tg3_set_power_state(tp, PCI_D3hot);
9015
9016 }
9017
9018 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9019 {
9020         struct mii_ioctl_data *data = if_mii(ifr);
9021         struct tg3 *tp = netdev_priv(dev);
9022         int err;
9023
9024         switch(cmd) {
9025         case SIOCGMIIPHY:
9026                 data->phy_id = PHY_ADDR;
9027
9028                 /* fallthru */
9029         case SIOCGMIIREG: {
9030                 u32 mii_regval;
9031
9032                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9033                         break;                  /* We have no PHY */
9034
9035                 if (tp->link_config.phy_is_low_power)
9036                         return -EAGAIN;
9037
9038                 spin_lock_bh(&tp->lock);
9039                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9040                 spin_unlock_bh(&tp->lock);
9041
9042                 data->val_out = mii_regval;
9043
9044                 return err;
9045         }
9046
9047         case SIOCSMIIREG:
9048                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9049                         break;                  /* We have no PHY */
9050
9051                 if (!capable(CAP_NET_ADMIN))
9052                         return -EPERM;
9053
9054                 if (tp->link_config.phy_is_low_power)
9055                         return -EAGAIN;
9056
9057                 spin_lock_bh(&tp->lock);
9058                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9059                 spin_unlock_bh(&tp->lock);
9060
9061                 return err;
9062
9063         default:
9064                 /* do nothing */
9065                 break;
9066         }
9067         return -EOPNOTSUPP;
9068 }
9069
9070 #if TG3_VLAN_TAG_USED
9071 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9072 {
9073         struct tg3 *tp = netdev_priv(dev);
9074
9075         if (netif_running(dev))
9076                 tg3_netif_stop(tp);
9077
9078         tg3_full_lock(tp, 0);
9079
9080         tp->vlgrp = grp;
9081
9082         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9083         __tg3_set_rx_mode(dev);
9084
9085         tg3_full_unlock(tp);
9086
9087         if (netif_running(dev))
9088                 tg3_netif_start(tp);
9089 }
9090
9091 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9092 {
9093         struct tg3 *tp = netdev_priv(dev);
9094
9095         if (netif_running(dev))
9096                 tg3_netif_stop(tp);
9097
9098         tg3_full_lock(tp, 0);
9099         if (tp->vlgrp)
9100                 tp->vlgrp->vlan_devices[vid] = NULL;
9101         tg3_full_unlock(tp);
9102
9103         if (netif_running(dev))
9104                 tg3_netif_start(tp);
9105 }
9106 #endif
9107
9108 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9109 {
9110         struct tg3 *tp = netdev_priv(dev);
9111
9112         memcpy(ec, &tp->coal, sizeof(*ec));
9113         return 0;
9114 }
9115
9116 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9117 {
9118         struct tg3 *tp = netdev_priv(dev);
9119         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9120         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9121
9122         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9123                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9124                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9125                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9126                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9127         }
9128
9129         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9130             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9131             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9132             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9133             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9134             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9135             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9136             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9137             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9138             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9139                 return -EINVAL;
9140
9141         /* No rx interrupts will be generated if both are zero */
9142         if ((ec->rx_coalesce_usecs == 0) &&
9143             (ec->rx_max_coalesced_frames == 0))
9144                 return -EINVAL;
9145
9146         /* No tx interrupts will be generated if both are zero */
9147         if ((ec->tx_coalesce_usecs == 0) &&
9148             (ec->tx_max_coalesced_frames == 0))
9149                 return -EINVAL;
9150
9151         /* Only copy relevant parameters, ignore all others. */
9152         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9153         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9154         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9155         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9156         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9157         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9158         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9159         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9160         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9161
9162         if (netif_running(dev)) {
9163                 tg3_full_lock(tp, 0);
9164                 __tg3_set_coalesce(tp, &tp->coal);
9165                 tg3_full_unlock(tp);
9166         }
9167         return 0;
9168 }
9169
9170 static const struct ethtool_ops tg3_ethtool_ops = {
9171         .get_settings           = tg3_get_settings,
9172         .set_settings           = tg3_set_settings,
9173         .get_drvinfo            = tg3_get_drvinfo,
9174         .get_regs_len           = tg3_get_regs_len,
9175         .get_regs               = tg3_get_regs,
9176         .get_wol                = tg3_get_wol,
9177         .set_wol                = tg3_set_wol,
9178         .get_msglevel           = tg3_get_msglevel,
9179         .set_msglevel           = tg3_set_msglevel,
9180         .nway_reset             = tg3_nway_reset,
9181         .get_link               = ethtool_op_get_link,
9182         .get_eeprom_len         = tg3_get_eeprom_len,
9183         .get_eeprom             = tg3_get_eeprom,
9184         .set_eeprom             = tg3_set_eeprom,
9185         .get_ringparam          = tg3_get_ringparam,
9186         .set_ringparam          = tg3_set_ringparam,
9187         .get_pauseparam         = tg3_get_pauseparam,
9188         .set_pauseparam         = tg3_set_pauseparam,
9189         .get_rx_csum            = tg3_get_rx_csum,
9190         .set_rx_csum            = tg3_set_rx_csum,
9191         .get_tx_csum            = ethtool_op_get_tx_csum,
9192         .set_tx_csum            = tg3_set_tx_csum,
9193         .get_sg                 = ethtool_op_get_sg,
9194         .set_sg                 = ethtool_op_set_sg,
9195 #if TG3_TSO_SUPPORT != 0
9196         .get_tso                = ethtool_op_get_tso,
9197         .set_tso                = tg3_set_tso,
9198 #endif
9199         .self_test_count        = tg3_get_test_count,
9200         .self_test              = tg3_self_test,
9201         .get_strings            = tg3_get_strings,
9202         .phys_id                = tg3_phys_id,
9203         .get_stats_count        = tg3_get_stats_count,
9204         .get_ethtool_stats      = tg3_get_ethtool_stats,
9205         .get_coalesce           = tg3_get_coalesce,
9206         .set_coalesce           = tg3_set_coalesce,
9207         .get_perm_addr          = ethtool_op_get_perm_addr,
9208 };
9209
9210 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9211 {
9212         u32 cursize, val, magic;
9213
9214         tp->nvram_size = EEPROM_CHIP_SIZE;
9215
9216         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9217                 return;
9218
9219         if ((magic != TG3_EEPROM_MAGIC) &&
9220             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9221             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9222                 return;
9223
9224         /*
9225          * Size the chip by reading offsets at increasing powers of two.
9226          * When we encounter our validation signature, we know the addressing
9227          * has wrapped around, and thus have our chip size.
9228          */
9229         cursize = 0x10;
9230
9231         while (cursize < tp->nvram_size) {
9232                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9233                         return;
9234
9235                 if (val == magic)
9236                         break;
9237
9238                 cursize <<= 1;
9239         }
9240
9241         tp->nvram_size = cursize;
9242 }
9243
9244 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9245 {
9246         u32 val;
9247
9248         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9249                 return;
9250
9251         /* Selfboot format */
9252         if (val != TG3_EEPROM_MAGIC) {
9253                 tg3_get_eeprom_size(tp);
9254                 return;
9255         }
9256
9257         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9258                 if (val != 0) {
9259                         tp->nvram_size = (val >> 16) * 1024;
9260                         return;
9261                 }
9262         }
9263         tp->nvram_size = 0x20000;
9264 }
9265
9266 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9267 {
9268         u32 nvcfg1;
9269
9270         nvcfg1 = tr32(NVRAM_CFG1);
9271         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9272                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9273         }
9274         else {
9275                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9276                 tw32(NVRAM_CFG1, nvcfg1);
9277         }
9278
9279         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9280             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9281                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9282                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9283                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9284                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9285                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9286                                 break;
9287                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9288                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9289                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9290                                 break;
9291                         case FLASH_VENDOR_ATMEL_EEPROM:
9292                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9293                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9294                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9295                                 break;
9296                         case FLASH_VENDOR_ST:
9297                                 tp->nvram_jedecnum = JEDEC_ST;
9298                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9299                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9300                                 break;
9301                         case FLASH_VENDOR_SAIFUN:
9302                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9303                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9304                                 break;
9305                         case FLASH_VENDOR_SST_SMALL:
9306                         case FLASH_VENDOR_SST_LARGE:
9307                                 tp->nvram_jedecnum = JEDEC_SST;
9308                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9309                                 break;
9310                 }
9311         }
9312         else {
9313                 tp->nvram_jedecnum = JEDEC_ATMEL;
9314                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9315                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9316         }
9317 }
9318
9319 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9320 {
9321         u32 nvcfg1;
9322
9323         nvcfg1 = tr32(NVRAM_CFG1);
9324
9325         /* NVRAM protection for TPM */
9326         if (nvcfg1 & (1 << 27))
9327                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9328
9329         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9330                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9331                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9332                         tp->nvram_jedecnum = JEDEC_ATMEL;
9333                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9334                         break;
9335                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9336                         tp->nvram_jedecnum = JEDEC_ATMEL;
9337                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9338                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9339                         break;
9340                 case FLASH_5752VENDOR_ST_M45PE10:
9341                 case FLASH_5752VENDOR_ST_M45PE20:
9342                 case FLASH_5752VENDOR_ST_M45PE40:
9343                         tp->nvram_jedecnum = JEDEC_ST;
9344                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9345                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9346                         break;
9347         }
9348
9349         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9350                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9351                         case FLASH_5752PAGE_SIZE_256:
9352                                 tp->nvram_pagesize = 256;
9353                                 break;
9354                         case FLASH_5752PAGE_SIZE_512:
9355                                 tp->nvram_pagesize = 512;
9356                                 break;
9357                         case FLASH_5752PAGE_SIZE_1K:
9358                                 tp->nvram_pagesize = 1024;
9359                                 break;
9360                         case FLASH_5752PAGE_SIZE_2K:
9361                                 tp->nvram_pagesize = 2048;
9362                                 break;
9363                         case FLASH_5752PAGE_SIZE_4K:
9364                                 tp->nvram_pagesize = 4096;
9365                                 break;
9366                         case FLASH_5752PAGE_SIZE_264:
9367                                 tp->nvram_pagesize = 264;
9368                                 break;
9369                 }
9370         }
9371         else {
9372                 /* For eeprom, set pagesize to maximum eeprom size */
9373                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9374
9375                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9376                 tw32(NVRAM_CFG1, nvcfg1);
9377         }
9378 }
9379
9380 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9381 {
9382         u32 nvcfg1;
9383
9384         nvcfg1 = tr32(NVRAM_CFG1);
9385
9386         /* NVRAM protection for TPM */
9387         if (nvcfg1 & (1 << 27))
9388                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9389
9390         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9391                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9392                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9393                         tp->nvram_jedecnum = JEDEC_ATMEL;
9394                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9395                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9396
9397                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9398                         tw32(NVRAM_CFG1, nvcfg1);
9399                         break;
9400                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9401                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9402                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9403                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9404                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9405                         tp->nvram_jedecnum = JEDEC_ATMEL;
9406                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9407                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9408                         tp->nvram_pagesize = 264;
9409                         break;
9410                 case FLASH_5752VENDOR_ST_M45PE10:
9411                 case FLASH_5752VENDOR_ST_M45PE20:
9412                 case FLASH_5752VENDOR_ST_M45PE40:
9413                         tp->nvram_jedecnum = JEDEC_ST;
9414                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9415                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9416                         tp->nvram_pagesize = 256;
9417                         break;
9418         }
9419 }
9420
9421 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9422 {
9423         u32 nvcfg1;
9424
9425         nvcfg1 = tr32(NVRAM_CFG1);
9426
9427         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9428                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9429                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9430                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9431                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9432                         tp->nvram_jedecnum = JEDEC_ATMEL;
9433                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9434                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9435
9436                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9437                         tw32(NVRAM_CFG1, nvcfg1);
9438                         break;
9439                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9440                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9441                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9442                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9443                         tp->nvram_jedecnum = JEDEC_ATMEL;
9444                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9445                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9446                         tp->nvram_pagesize = 264;
9447                         break;
9448                 case FLASH_5752VENDOR_ST_M45PE10:
9449                 case FLASH_5752VENDOR_ST_M45PE20:
9450                 case FLASH_5752VENDOR_ST_M45PE40:
9451                         tp->nvram_jedecnum = JEDEC_ST;
9452                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9453                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9454                         tp->nvram_pagesize = 256;
9455                         break;
9456         }
9457 }
9458
9459 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9460 {
9461         tp->nvram_jedecnum = JEDEC_ATMEL;
9462         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9463         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9464 }
9465
9466 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9467 static void __devinit tg3_nvram_init(struct tg3 *tp)
9468 {
9469         tw32_f(GRC_EEPROM_ADDR,
9470              (EEPROM_ADDR_FSM_RESET |
9471               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9472                EEPROM_ADDR_CLKPERD_SHIFT)));
9473
9474         msleep(1);
9475
9476         /* Enable seeprom accesses. */
9477         tw32_f(GRC_LOCAL_CTRL,
9478              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9479         udelay(100);
9480
9481         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9482             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9483                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9484
9485                 if (tg3_nvram_lock(tp)) {
9486                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9487                                "tg3_nvram_init failed.\n", tp->dev->name);
9488                         return;
9489                 }
9490                 tg3_enable_nvram_access(tp);
9491
9492                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9493                         tg3_get_5752_nvram_info(tp);
9494                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9495                         tg3_get_5755_nvram_info(tp);
9496                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9497                         tg3_get_5787_nvram_info(tp);
9498                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9499                         tg3_get_5906_nvram_info(tp);
9500                 else
9501                         tg3_get_nvram_info(tp);
9502
9503                 tg3_get_nvram_size(tp);
9504
9505                 tg3_disable_nvram_access(tp);
9506                 tg3_nvram_unlock(tp);
9507
9508         } else {
9509                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9510
9511                 tg3_get_eeprom_size(tp);
9512         }
9513 }
9514
9515 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9516                                         u32 offset, u32 *val)
9517 {
9518         u32 tmp;
9519         int i;
9520
9521         if (offset > EEPROM_ADDR_ADDR_MASK ||
9522             (offset % 4) != 0)
9523                 return -EINVAL;
9524
9525         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9526                                         EEPROM_ADDR_DEVID_MASK |
9527                                         EEPROM_ADDR_READ);
9528         tw32(GRC_EEPROM_ADDR,
9529              tmp |
9530              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9531              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9532               EEPROM_ADDR_ADDR_MASK) |
9533              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9534
9535         for (i = 0; i < 1000; i++) {
9536                 tmp = tr32(GRC_EEPROM_ADDR);
9537
9538                 if (tmp & EEPROM_ADDR_COMPLETE)
9539                         break;
9540                 msleep(1);
9541         }
9542         if (!(tmp & EEPROM_ADDR_COMPLETE))
9543                 return -EBUSY;
9544
9545         *val = tr32(GRC_EEPROM_DATA);
9546         return 0;
9547 }
9548
9549 #define NVRAM_CMD_TIMEOUT 10000
9550
9551 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9552 {
9553         int i;
9554
9555         tw32(NVRAM_CMD, nvram_cmd);
9556         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9557                 udelay(10);
9558                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9559                         udelay(10);
9560                         break;
9561                 }
9562         }
9563         if (i == NVRAM_CMD_TIMEOUT) {
9564                 return -EBUSY;
9565         }
9566         return 0;
9567 }
9568
9569 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9570 {
9571         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9572             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9573             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9574             (tp->nvram_jedecnum == JEDEC_ATMEL))
9575
9576                 addr = ((addr / tp->nvram_pagesize) <<
9577                         ATMEL_AT45DB0X1B_PAGE_POS) +
9578                        (addr % tp->nvram_pagesize);
9579
9580         return addr;
9581 }
9582
9583 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9584 {
9585         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9586             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9587             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9588             (tp->nvram_jedecnum == JEDEC_ATMEL))
9589
9590                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9591                         tp->nvram_pagesize) +
9592                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9593
9594         return addr;
9595 }
9596
9597 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9598 {
9599         int ret;
9600
9601         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9602                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9603
9604         offset = tg3_nvram_phys_addr(tp, offset);
9605
9606         if (offset > NVRAM_ADDR_MSK)
9607                 return -EINVAL;
9608
9609         ret = tg3_nvram_lock(tp);
9610         if (ret)
9611                 return ret;
9612
9613         tg3_enable_nvram_access(tp);
9614
9615         tw32(NVRAM_ADDR, offset);
9616         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9617                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9618
9619         if (ret == 0)
9620                 *val = swab32(tr32(NVRAM_RDDATA));
9621
9622         tg3_disable_nvram_access(tp);
9623
9624         tg3_nvram_unlock(tp);
9625
9626         return ret;
9627 }
9628
9629 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9630 {
9631         int err;
9632         u32 tmp;
9633
9634         err = tg3_nvram_read(tp, offset, &tmp);
9635         *val = swab32(tmp);
9636         return err;
9637 }
9638
9639 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9640                                     u32 offset, u32 len, u8 *buf)
9641 {
9642         int i, j, rc = 0;
9643         u32 val;
9644
9645         for (i = 0; i < len; i += 4) {
9646                 u32 addr, data;
9647
9648                 addr = offset + i;
9649
9650                 memcpy(&data, buf + i, 4);
9651
9652                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9653
9654                 val = tr32(GRC_EEPROM_ADDR);
9655                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9656
9657                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9658                         EEPROM_ADDR_READ);
9659                 tw32(GRC_EEPROM_ADDR, val |
9660                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9661                         (addr & EEPROM_ADDR_ADDR_MASK) |
9662                         EEPROM_ADDR_START |
9663                         EEPROM_ADDR_WRITE);
9664
9665                 for (j = 0; j < 1000; j++) {
9666                         val = tr32(GRC_EEPROM_ADDR);
9667
9668                         if (val & EEPROM_ADDR_COMPLETE)
9669                                 break;
9670                         msleep(1);
9671                 }
9672                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9673                         rc = -EBUSY;
9674                         break;
9675                 }
9676         }
9677
9678         return rc;
9679 }
9680
9681 /* offset and length are dword aligned */
9682 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9683                 u8 *buf)
9684 {
9685         int ret = 0;
9686         u32 pagesize = tp->nvram_pagesize;
9687         u32 pagemask = pagesize - 1;
9688         u32 nvram_cmd;
9689         u8 *tmp;
9690
9691         tmp = kmalloc(pagesize, GFP_KERNEL);
9692         if (tmp == NULL)
9693                 return -ENOMEM;
9694
9695         while (len) {
9696                 int j;
9697                 u32 phy_addr, page_off, size;
9698
9699                 phy_addr = offset & ~pagemask;
9700
9701                 for (j = 0; j < pagesize; j += 4) {
9702                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9703                                                 (u32 *) (tmp + j))))
9704                                 break;
9705                 }
9706                 if (ret)
9707                         break;
9708
9709                 page_off = offset & pagemask;
9710                 size = pagesize;
9711                 if (len < size)
9712                         size = len;
9713
9714                 len -= size;
9715
9716                 memcpy(tmp + page_off, buf, size);
9717
9718                 offset = offset + (pagesize - page_off);
9719
9720                 tg3_enable_nvram_access(tp);
9721
9722                 /*
9723                  * Before we can erase the flash page, we need
9724                  * to issue a special "write enable" command.
9725                  */
9726                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9727
9728                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9729                         break;
9730
9731                 /* Erase the target page */
9732                 tw32(NVRAM_ADDR, phy_addr);
9733
9734                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9735                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9736
9737                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9738                         break;
9739
9740                 /* Issue another write enable to start the write. */
9741                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9742
9743                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9744                         break;
9745
9746                 for (j = 0; j < pagesize; j += 4) {
9747                         u32 data;
9748
9749                         data = *((u32 *) (tmp + j));
9750                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9751
9752                         tw32(NVRAM_ADDR, phy_addr + j);
9753
9754                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9755                                 NVRAM_CMD_WR;
9756
9757                         if (j == 0)
9758                                 nvram_cmd |= NVRAM_CMD_FIRST;
9759                         else if (j == (pagesize - 4))
9760                                 nvram_cmd |= NVRAM_CMD_LAST;
9761
9762                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9763                                 break;
9764                 }
9765                 if (ret)
9766                         break;
9767         }
9768
9769         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9770         tg3_nvram_exec_cmd(tp, nvram_cmd);
9771
9772         kfree(tmp);
9773
9774         return ret;
9775 }
9776
9777 /* offset and length are dword aligned */
9778 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9779                 u8 *buf)
9780 {
9781         int i, ret = 0;
9782
9783         for (i = 0; i < len; i += 4, offset += 4) {
9784                 u32 data, page_off, phy_addr, nvram_cmd;
9785
9786                 memcpy(&data, buf + i, 4);
9787                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9788
9789                 page_off = offset % tp->nvram_pagesize;
9790
9791                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9792
9793                 tw32(NVRAM_ADDR, phy_addr);
9794
9795                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9796
9797                 if ((page_off == 0) || (i == 0))
9798                         nvram_cmd |= NVRAM_CMD_FIRST;
9799                 if (page_off == (tp->nvram_pagesize - 4))
9800                         nvram_cmd |= NVRAM_CMD_LAST;
9801
9802                 if (i == (len - 4))
9803                         nvram_cmd |= NVRAM_CMD_LAST;
9804
9805                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9806                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9807                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9808                     (tp->nvram_jedecnum == JEDEC_ST) &&
9809                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9810
9811                         if ((ret = tg3_nvram_exec_cmd(tp,
9812                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9813                                 NVRAM_CMD_DONE)))
9814
9815                                 break;
9816                 }
9817                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9818                         /* We always do complete word writes to eeprom. */
9819                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9820                 }
9821
9822                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9823                         break;
9824         }
9825         return ret;
9826 }
9827
9828 /* offset and length are dword aligned */
9829 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9830 {
9831         int ret;
9832
9833         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9834                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9835                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9836                 udelay(40);
9837         }
9838
9839         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9840                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9841         }
9842         else {
9843                 u32 grc_mode;
9844
9845                 ret = tg3_nvram_lock(tp);
9846                 if (ret)
9847                         return ret;
9848
9849                 tg3_enable_nvram_access(tp);
9850                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9851                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9852                         tw32(NVRAM_WRITE1, 0x406);
9853
9854                 grc_mode = tr32(GRC_MODE);
9855                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9856
9857                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9858                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9859
9860                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9861                                 buf);
9862                 }
9863                 else {
9864                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9865                                 buf);
9866                 }
9867
9868                 grc_mode = tr32(GRC_MODE);
9869                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9870
9871                 tg3_disable_nvram_access(tp);
9872                 tg3_nvram_unlock(tp);
9873         }
9874
9875         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9876                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9877                 udelay(40);
9878         }
9879
9880         return ret;
9881 }
9882
9883 struct subsys_tbl_ent {
9884         u16 subsys_vendor, subsys_devid;
9885         u32 phy_id;
9886 };
9887
9888 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9889         /* Broadcom boards. */
9890         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9891         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9892         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9893         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9894         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9895         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9896         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9897         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9898         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9899         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9900         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9901
9902         /* 3com boards. */
9903         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9904         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9905         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9906         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9907         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9908
9909         /* DELL boards. */
9910         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9911         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9912         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9913         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9914
9915         /* Compaq boards. */
9916         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9917         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9918         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9919         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9920         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9921
9922         /* IBM boards. */
9923         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9924 };
9925
9926 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9927 {
9928         int i;
9929
9930         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9931                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9932                      tp->pdev->subsystem_vendor) &&
9933                     (subsys_id_to_phy_id[i].subsys_devid ==
9934                      tp->pdev->subsystem_device))
9935                         return &subsys_id_to_phy_id[i];
9936         }
9937         return NULL;
9938 }
9939
9940 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9941 {
9942         u32 val;
9943         u16 pmcsr;
9944
9945         /* On some early chips the SRAM cannot be accessed in D3hot state,
9946          * so need make sure we're in D0.
9947          */
9948         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9949         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9950         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9951         msleep(1);
9952
9953         /* Make sure register accesses (indirect or otherwise)
9954          * will function correctly.
9955          */
9956         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9957                                tp->misc_host_ctrl);
9958
9959         /* The memory arbiter has to be enabled in order for SRAM accesses
9960          * to succeed.  Normally on powerup the tg3 chip firmware will make
9961          * sure it is enabled, but other entities such as system netboot
9962          * code might disable it.
9963          */
9964         val = tr32(MEMARB_MODE);
9965         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9966
9967         tp->phy_id = PHY_ID_INVALID;
9968         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9969
9970         /* Assume an onboard device by default.  */
9971         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9972
9973         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9974                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
9975                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9976                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9977                 }
9978                 return;
9979         }
9980
9981         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9982         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9983                 u32 nic_cfg, led_cfg;
9984                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9985                 int eeprom_phy_serdes = 0;
9986
9987                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9988                 tp->nic_sram_data_cfg = nic_cfg;
9989
9990                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9991                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9992                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9993                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9994                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9995                     (ver > 0) && (ver < 0x100))
9996                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9997
9998                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9999                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10000                         eeprom_phy_serdes = 1;
10001
10002                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10003                 if (nic_phy_id != 0) {
10004                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10005                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10006
10007                         eeprom_phy_id  = (id1 >> 16) << 10;
10008                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10009                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10010                 } else
10011                         eeprom_phy_id = 0;
10012
10013                 tp->phy_id = eeprom_phy_id;
10014                 if (eeprom_phy_serdes) {
10015                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10016                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10017                         else
10018                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10019                 }
10020
10021                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10022                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10023                                     SHASTA_EXT_LED_MODE_MASK);
10024                 else
10025                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10026
10027                 switch (led_cfg) {
10028                 default:
10029                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10030                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10031                         break;
10032
10033                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10034                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10035                         break;
10036
10037                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10038                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10039
10040                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10041                          * read on some older 5700/5701 bootcode.
10042                          */
10043                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10044                             ASIC_REV_5700 ||
10045                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10046                             ASIC_REV_5701)
10047                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10048
10049                         break;
10050
10051                 case SHASTA_EXT_LED_SHARED:
10052                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10053                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10054                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10055                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10056                                                  LED_CTRL_MODE_PHY_2);
10057                         break;
10058
10059                 case SHASTA_EXT_LED_MAC:
10060                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10061                         break;
10062
10063                 case SHASTA_EXT_LED_COMBO:
10064                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10065                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10066                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10067                                                  LED_CTRL_MODE_PHY_2);
10068                         break;
10069
10070                 };
10071
10072                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10073                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10074                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10075                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10076
10077                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10078                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10079                         if ((tp->pdev->subsystem_vendor ==
10080                              PCI_VENDOR_ID_ARIMA) &&
10081                             (tp->pdev->subsystem_device == 0x205a ||
10082                              tp->pdev->subsystem_device == 0x2063))
10083                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10084                 } else {
10085                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10086                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10087                 }
10088
10089                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10090                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10091                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10092                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10093                 }
10094                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10095                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10096
10097                 if (cfg2 & (1 << 17))
10098                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10099
10100                 /* serdes signal pre-emphasis in register 0x590 set by */
10101                 /* bootcode if bit 18 is set */
10102                 if (cfg2 & (1 << 18))
10103                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10104         }
10105 }
10106
10107 static int __devinit tg3_phy_probe(struct tg3 *tp)
10108 {
10109         u32 hw_phy_id_1, hw_phy_id_2;
10110         u32 hw_phy_id, hw_phy_id_masked;
10111         int err;
10112
10113         /* Reading the PHY ID register can conflict with ASF
10114          * firwmare access to the PHY hardware.
10115          */
10116         err = 0;
10117         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10118                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10119         } else {
10120                 /* Now read the physical PHY_ID from the chip and verify
10121                  * that it is sane.  If it doesn't look good, we fall back
10122                  * to either the hard-coded table based PHY_ID and failing
10123                  * that the value found in the eeprom area.
10124                  */
10125                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10126                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10127
10128                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10129                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10130                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10131
10132                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10133         }
10134
10135         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10136                 tp->phy_id = hw_phy_id;
10137                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10138                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10139                 else
10140                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10141         } else {
10142                 if (tp->phy_id != PHY_ID_INVALID) {
10143                         /* Do nothing, phy ID already set up in
10144                          * tg3_get_eeprom_hw_cfg().
10145                          */
10146                 } else {
10147                         struct subsys_tbl_ent *p;
10148
10149                         /* No eeprom signature?  Try the hardcoded
10150                          * subsys device table.
10151                          */
10152                         p = lookup_by_subsys(tp);
10153                         if (!p)
10154                                 return -ENODEV;
10155
10156                         tp->phy_id = p->phy_id;
10157                         if (!tp->phy_id ||
10158                             tp->phy_id == PHY_ID_BCM8002)
10159                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10160                 }
10161         }
10162
10163         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10164             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10165                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10166
10167                 tg3_readphy(tp, MII_BMSR, &bmsr);
10168                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10169                     (bmsr & BMSR_LSTATUS))
10170                         goto skip_phy_reset;
10171
10172                 err = tg3_phy_reset(tp);
10173                 if (err)
10174                         return err;
10175
10176                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10177                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10178                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10179                 tg3_ctrl = 0;
10180                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10181                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10182                                     MII_TG3_CTRL_ADV_1000_FULL);
10183                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10184                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10185                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10186                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10187                 }
10188
10189                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10190                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10191                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10192                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10193                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10194
10195                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10196                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10197
10198                         tg3_writephy(tp, MII_BMCR,
10199                                      BMCR_ANENABLE | BMCR_ANRESTART);
10200                 }
10201                 tg3_phy_set_wirespeed(tp);
10202
10203                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10204                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10205                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10206         }
10207
10208 skip_phy_reset:
10209         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10210                 err = tg3_init_5401phy_dsp(tp);
10211                 if (err)
10212                         return err;
10213         }
10214
10215         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10216                 err = tg3_init_5401phy_dsp(tp);
10217         }
10218
10219         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10220                 tp->link_config.advertising =
10221                         (ADVERTISED_1000baseT_Half |
10222                          ADVERTISED_1000baseT_Full |
10223                          ADVERTISED_Autoneg |
10224                          ADVERTISED_FIBRE);
10225         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10226                 tp->link_config.advertising &=
10227                         ~(ADVERTISED_1000baseT_Half |
10228                           ADVERTISED_1000baseT_Full);
10229
10230         return err;
10231 }
10232
10233 static void __devinit tg3_read_partno(struct tg3 *tp)
10234 {
10235         unsigned char vpd_data[256];
10236         unsigned int i;
10237         u32 magic;
10238
10239         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10240                 goto out_not_found;
10241
10242         if (magic == TG3_EEPROM_MAGIC) {
10243                 for (i = 0; i < 256; i += 4) {
10244                         u32 tmp;
10245
10246                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10247                                 goto out_not_found;
10248
10249                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10250                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10251                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10252                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10253                 }
10254         } else {
10255                 int vpd_cap;
10256
10257                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10258                 for (i = 0; i < 256; i += 4) {
10259                         u32 tmp, j = 0;
10260                         u16 tmp16;
10261
10262                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10263                                               i);
10264                         while (j++ < 100) {
10265                                 pci_read_config_word(tp->pdev, vpd_cap +
10266                                                      PCI_VPD_ADDR, &tmp16);
10267                                 if (tmp16 & 0x8000)
10268                                         break;
10269                                 msleep(1);
10270                         }
10271                         if (!(tmp16 & 0x8000))
10272                                 goto out_not_found;
10273
10274                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10275                                               &tmp);
10276                         tmp = cpu_to_le32(tmp);
10277                         memcpy(&vpd_data[i], &tmp, 4);
10278                 }
10279         }
10280
10281         /* Now parse and find the part number. */
10282         for (i = 0; i < 254; ) {
10283                 unsigned char val = vpd_data[i];
10284                 unsigned int block_end;
10285
10286                 if (val == 0x82 || val == 0x91) {
10287                         i = (i + 3 +
10288                              (vpd_data[i + 1] +
10289                               (vpd_data[i + 2] << 8)));
10290                         continue;
10291                 }
10292
10293                 if (val != 0x90)
10294                         goto out_not_found;
10295
10296                 block_end = (i + 3 +
10297                              (vpd_data[i + 1] +
10298                               (vpd_data[i + 2] << 8)));
10299                 i += 3;
10300
10301                 if (block_end > 256)
10302                         goto out_not_found;
10303
10304                 while (i < (block_end - 2)) {
10305                         if (vpd_data[i + 0] == 'P' &&
10306                             vpd_data[i + 1] == 'N') {
10307                                 int partno_len = vpd_data[i + 2];
10308
10309                                 i += 3;
10310                                 if (partno_len > 24 || (partno_len + i) > 256)
10311                                         goto out_not_found;
10312
10313                                 memcpy(tp->board_part_number,
10314                                        &vpd_data[i], partno_len);
10315
10316                                 /* Success. */
10317                                 return;
10318                         }
10319                         i += 3 + vpd_data[i + 2];
10320                 }
10321
10322                 /* Part number not found. */
10323                 goto out_not_found;
10324         }
10325
10326 out_not_found:
10327         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10328                 strcpy(tp->board_part_number, "BCM95906");
10329         else
10330                 strcpy(tp->board_part_number, "none");
10331 }
10332
10333 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10334 {
10335         u32 val, offset, start;
10336
10337         if (tg3_nvram_read_swab(tp, 0, &val))
10338                 return;
10339
10340         if (val != TG3_EEPROM_MAGIC)
10341                 return;
10342
10343         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10344             tg3_nvram_read_swab(tp, 0x4, &start))
10345                 return;
10346
10347         offset = tg3_nvram_logical_addr(tp, offset);
10348         if (tg3_nvram_read_swab(tp, offset, &val))
10349                 return;
10350
10351         if ((val & 0xfc000000) == 0x0c000000) {
10352                 u32 ver_offset, addr;
10353                 int i;
10354
10355                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10356                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10357                         return;
10358
10359                 if (val != 0)
10360                         return;
10361
10362                 addr = offset + ver_offset - start;
10363                 for (i = 0; i < 16; i += 4) {
10364                         if (tg3_nvram_read(tp, addr + i, &val))
10365                                 return;
10366
10367                         val = cpu_to_le32(val);
10368                         memcpy(tp->fw_ver + i, &val, 4);
10369                 }
10370         }
10371 }
10372
10373 static int __devinit tg3_get_invariants(struct tg3 *tp)
10374 {
10375         static struct pci_device_id write_reorder_chipsets[] = {
10376                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10377                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10378                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10379                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10380                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10381                              PCI_DEVICE_ID_VIA_8385_0) },
10382                 { },
10383         };
10384         u32 misc_ctrl_reg;
10385         u32 cacheline_sz_reg;
10386         u32 pci_state_reg, grc_misc_cfg;
10387         u32 val;
10388         u16 pci_cmd;
10389         int err, pcie_cap;
10390
10391         /* Force memory write invalidate off.  If we leave it on,
10392          * then on 5700_BX chips we have to enable a workaround.
10393          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10394          * to match the cacheline size.  The Broadcom driver have this
10395          * workaround but turns MWI off all the times so never uses
10396          * it.  This seems to suggest that the workaround is insufficient.
10397          */
10398         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10399         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10400         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10401
10402         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10403          * has the register indirect write enable bit set before
10404          * we try to access any of the MMIO registers.  It is also
10405          * critical that the PCI-X hw workaround situation is decided
10406          * before that as well.
10407          */
10408         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10409                               &misc_ctrl_reg);
10410
10411         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10412                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10413
10414         /* Wrong chip ID in 5752 A0. This code can be removed later
10415          * as A0 is not in production.
10416          */
10417         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10418                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10419
10420         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10421          * we need to disable memory and use config. cycles
10422          * only to access all registers. The 5702/03 chips
10423          * can mistakenly decode the special cycles from the
10424          * ICH chipsets as memory write cycles, causing corruption
10425          * of register and memory space. Only certain ICH bridges
10426          * will drive special cycles with non-zero data during the
10427          * address phase which can fall within the 5703's address
10428          * range. This is not an ICH bug as the PCI spec allows
10429          * non-zero address during special cycles. However, only
10430          * these ICH bridges are known to drive non-zero addresses
10431          * during special cycles.
10432          *
10433          * Since special cycles do not cross PCI bridges, we only
10434          * enable this workaround if the 5703 is on the secondary
10435          * bus of these ICH bridges.
10436          */
10437         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10438             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10439                 static struct tg3_dev_id {
10440                         u32     vendor;
10441                         u32     device;
10442                         u32     rev;
10443                 } ich_chipsets[] = {
10444                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10445                           PCI_ANY_ID },
10446                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10447                           PCI_ANY_ID },
10448                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10449                           0xa },
10450                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10451                           PCI_ANY_ID },
10452                         { },
10453                 };
10454                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10455                 struct pci_dev *bridge = NULL;
10456
10457                 while (pci_id->vendor != 0) {
10458                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10459                                                 bridge);
10460                         if (!bridge) {
10461                                 pci_id++;
10462                                 continue;
10463                         }
10464                         if (pci_id->rev != PCI_ANY_ID) {
10465                                 u8 rev;
10466
10467                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10468                                                      &rev);
10469                                 if (rev > pci_id->rev)
10470                                         continue;
10471                         }
10472                         if (bridge->subordinate &&
10473                             (bridge->subordinate->number ==
10474                              tp->pdev->bus->number)) {
10475
10476                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10477                                 pci_dev_put(bridge);
10478                                 break;
10479                         }
10480                 }
10481         }
10482
10483         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10484          * DMA addresses > 40-bit. This bridge may have other additional
10485          * 57xx devices behind it in some 4-port NIC designs for example.
10486          * Any tg3 device found behind the bridge will also need the 40-bit
10487          * DMA workaround.
10488          */
10489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10490             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10491                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10492                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10493                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10494         }
10495         else {
10496                 struct pci_dev *bridge = NULL;
10497
10498                 do {
10499                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10500                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10501                                                 bridge);
10502                         if (bridge && bridge->subordinate &&
10503                             (bridge->subordinate->number <=
10504                              tp->pdev->bus->number) &&
10505                             (bridge->subordinate->subordinate >=
10506                              tp->pdev->bus->number)) {
10507                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10508                                 pci_dev_put(bridge);
10509                                 break;
10510                         }
10511                 } while (bridge);
10512         }
10513
10514         /* Initialize misc host control in PCI block. */
10515         tp->misc_host_ctrl |= (misc_ctrl_reg &
10516                                MISC_HOST_CTRL_CHIPREV);
10517         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10518                                tp->misc_host_ctrl);
10519
10520         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10521                               &cacheline_sz_reg);
10522
10523         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10524         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10525         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10526         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10527
10528         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10529             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10530             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10531             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10532             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10533             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10534                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10535
10536         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10537             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10538                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10539
10540         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10541                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10542                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10543                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10544                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10545                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10546                 } else {
10547                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10548                                           TG3_FLG2_HW_TSO_1_BUG;
10549                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10550                                 ASIC_REV_5750 &&
10551                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10552                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10553                 }
10554         }
10555
10556         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10557             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10558             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10559             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10560             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10561             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10562                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10563
10564         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10565         if (pcie_cap != 0) {
10566                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10567                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10568                         u16 lnkctl;
10569
10570                         pci_read_config_word(tp->pdev,
10571                                              pcie_cap + PCI_EXP_LNKCTL,
10572                                              &lnkctl);
10573                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10574                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10575                 }
10576         }
10577
10578         /* If we have an AMD 762 or VIA K8T800 chipset, write
10579          * reordering to the mailbox registers done by the host
10580          * controller can cause major troubles.  We read back from
10581          * every mailbox register write to force the writes to be
10582          * posted to the chip in order.
10583          */
10584         if (pci_dev_present(write_reorder_chipsets) &&
10585             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10586                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10587
10588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10589             tp->pci_lat_timer < 64) {
10590                 tp->pci_lat_timer = 64;
10591
10592                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10593                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10594                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10595                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10596
10597                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10598                                        cacheline_sz_reg);
10599         }
10600
10601         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10602                               &pci_state_reg);
10603
10604         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10605                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10606
10607                 /* If this is a 5700 BX chipset, and we are in PCI-X
10608                  * mode, enable register write workaround.
10609                  *
10610                  * The workaround is to use indirect register accesses
10611                  * for all chip writes not to mailbox registers.
10612                  */
10613                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10614                         u32 pm_reg;
10615                         u16 pci_cmd;
10616
10617                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10618
10619                         /* The chip can have it's power management PCI config
10620                          * space registers clobbered due to this bug.
10621                          * So explicitly force the chip into D0 here.
10622                          */
10623                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10624                                               &pm_reg);
10625                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10626                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10627                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10628                                                pm_reg);
10629
10630                         /* Also, force SERR#/PERR# in PCI command. */
10631                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10632                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10633                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10634                 }
10635         }
10636
10637         /* 5700 BX chips need to have their TX producer index mailboxes
10638          * written twice to workaround a bug.
10639          */
10640         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10641                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10642
10643         /* Back to back register writes can cause problems on this chip,
10644          * the workaround is to read back all reg writes except those to
10645          * mailbox regs.  See tg3_write_indirect_reg32().
10646          *
10647          * PCI Express 5750_A0 rev chips need this workaround too.
10648          */
10649         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10650             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10651              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10652                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10653
10654         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10655                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10656         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10657                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10658
10659         /* Chip-specific fixup from Broadcom driver */
10660         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10661             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10662                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10663                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10664         }
10665
10666         /* Default fast path register access methods */
10667         tp->read32 = tg3_read32;
10668         tp->write32 = tg3_write32;
10669         tp->read32_mbox = tg3_read32;
10670         tp->write32_mbox = tg3_write32;
10671         tp->write32_tx_mbox = tg3_write32;
10672         tp->write32_rx_mbox = tg3_write32;
10673
10674         /* Various workaround register access methods */
10675         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10676                 tp->write32 = tg3_write_indirect_reg32;
10677         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10678                 tp->write32 = tg3_write_flush_reg32;
10679
10680         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10681             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10682                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10683                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10684                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10685         }
10686
10687         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10688                 tp->read32 = tg3_read_indirect_reg32;
10689                 tp->write32 = tg3_write_indirect_reg32;
10690                 tp->read32_mbox = tg3_read_indirect_mbox;
10691                 tp->write32_mbox = tg3_write_indirect_mbox;
10692                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10693                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10694
10695                 iounmap(tp->regs);
10696                 tp->regs = NULL;
10697
10698                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10699                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10700                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10701         }
10702         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10703                 tp->read32_mbox = tg3_read32_mbox_5906;
10704                 tp->write32_mbox = tg3_write32_mbox_5906;
10705                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10706                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10707         }
10708
10709         if (tp->write32 == tg3_write_indirect_reg32 ||
10710             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10711              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10712               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10713                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10714
10715         /* Get eeprom hw config before calling tg3_set_power_state().
10716          * In particular, the TG3_FLG2_IS_NIC flag must be
10717          * determined before calling tg3_set_power_state() so that
10718          * we know whether or not to switch out of Vaux power.
10719          * When the flag is set, it means that GPIO1 is used for eeprom
10720          * write protect and also implies that it is a LOM where GPIOs
10721          * are not used to switch power.
10722          */
10723         tg3_get_eeprom_hw_cfg(tp);
10724
10725         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10726          * GPIO1 driven high will bring 5700's external PHY out of reset.
10727          * It is also used as eeprom write protect on LOMs.
10728          */
10729         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10730         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10731             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10732                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10733                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10734         /* Unused GPIO3 must be driven as output on 5752 because there
10735          * are no pull-up resistors on unused GPIO pins.
10736          */
10737         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10738                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10739
10740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10741                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10742
10743         /* Force the chip into D0. */
10744         err = tg3_set_power_state(tp, PCI_D0);
10745         if (err) {
10746                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10747                        pci_name(tp->pdev));
10748                 return err;
10749         }
10750
10751         /* 5700 B0 chips do not support checksumming correctly due
10752          * to hardware bugs.
10753          */
10754         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10755                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10756
10757         /* Derive initial jumbo mode from MTU assigned in
10758          * ether_setup() via the alloc_etherdev() call
10759          */
10760         if (tp->dev->mtu > ETH_DATA_LEN &&
10761             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10762                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10763
10764         /* Determine WakeOnLan speed to use. */
10765         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10766             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10767             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10768             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10769                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10770         } else {
10771                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10772         }
10773
10774         /* A few boards don't want Ethernet@WireSpeed phy feature */
10775         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10776             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10777              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10778              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10779             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10780             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10781                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10782
10783         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10784             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10785                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10786         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10787                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10788
10789         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10790                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10791                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10792                         tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10793                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10794                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10795         }
10796
10797         tp->coalesce_mode = 0;
10798         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10799             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10800                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10801
10802         /* Initialize MAC MI mode, polling disabled. */
10803         tw32_f(MAC_MI_MODE, tp->mi_mode);
10804         udelay(80);
10805
10806         /* Initialize data/descriptor byte/word swapping. */
10807         val = tr32(GRC_MODE);
10808         val &= GRC_MODE_HOST_STACKUP;
10809         tw32(GRC_MODE, val | tp->grc_mode);
10810
10811         tg3_switch_clocks(tp);
10812
10813         /* Clear this out for sanity. */
10814         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10815
10816         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10817                               &pci_state_reg);
10818         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10819             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10820                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10821
10822                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10823                     chiprevid == CHIPREV_ID_5701_B0 ||
10824                     chiprevid == CHIPREV_ID_5701_B2 ||
10825                     chiprevid == CHIPREV_ID_5701_B5) {
10826                         void __iomem *sram_base;
10827
10828                         /* Write some dummy words into the SRAM status block
10829                          * area, see if it reads back correctly.  If the return
10830                          * value is bad, force enable the PCIX workaround.
10831                          */
10832                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10833
10834                         writel(0x00000000, sram_base);
10835                         writel(0x00000000, sram_base + 4);
10836                         writel(0xffffffff, sram_base + 4);
10837                         if (readl(sram_base) != 0x00000000)
10838                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10839                 }
10840         }
10841
10842         udelay(50);
10843         tg3_nvram_init(tp);
10844
10845         grc_misc_cfg = tr32(GRC_MISC_CFG);
10846         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10847
10848         /* Broadcom's driver says that CIOBE multisplit has a bug */
10849 #if 0
10850         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10851             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10852                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10853                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10854         }
10855 #endif
10856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10857             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10858              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10859                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10860
10861         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10862             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10863                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10864         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10865                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10866                                       HOSTCC_MODE_CLRTICK_TXBD);
10867
10868                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10869                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10870                                        tp->misc_host_ctrl);
10871         }
10872
10873         /* these are limited to 10/100 only */
10874         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10875              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10876             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10877              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10878              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10879               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10880               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10881             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10882              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10883               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10884               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10885             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10886                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10887
10888         err = tg3_phy_probe(tp);
10889         if (err) {
10890                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10891                        pci_name(tp->pdev), err);
10892                 /* ... but do not return immediately ... */
10893         }
10894
10895         tg3_read_partno(tp);
10896         tg3_read_fw_ver(tp);
10897
10898         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10899                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10900         } else {
10901                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10902                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10903                 else
10904                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10905         }
10906
10907         /* 5700 {AX,BX} chips have a broken status block link
10908          * change bit implementation, so we must use the
10909          * status register in those cases.
10910          */
10911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10912                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10913         else
10914                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10915
10916         /* The led_ctrl is set during tg3_phy_probe, here we might
10917          * have to force the link status polling mechanism based
10918          * upon subsystem IDs.
10919          */
10920         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10921             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10922                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10923                                   TG3_FLAG_USE_LINKCHG_REG);
10924         }
10925
10926         /* For all SERDES we poll the MAC status register. */
10927         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10928                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10929         else
10930                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10931
10932         /* All chips before 5787 can get confused if TX buffers
10933          * straddle the 4GB address boundary in some cases.
10934          */
10935         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10936             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10937             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10938                 tp->dev->hard_start_xmit = tg3_start_xmit;
10939         else
10940                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10941
10942         tp->rx_offset = 2;
10943         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10944             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10945                 tp->rx_offset = 0;
10946
10947         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10948
10949         /* Increment the rx prod index on the rx std ring by at most
10950          * 8 for these chips to workaround hw errata.
10951          */
10952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10953             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10954             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10955                 tp->rx_std_max_post = 8;
10956
10957         /* By default, disable wake-on-lan.  User can change this
10958          * using ETHTOOL_SWOL.
10959          */
10960         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10961
10962         return err;
10963 }
10964
10965 #ifdef CONFIG_SPARC64
10966 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10967 {
10968         struct net_device *dev = tp->dev;
10969         struct pci_dev *pdev = tp->pdev;
10970         struct pcidev_cookie *pcp = pdev->sysdata;
10971
10972         if (pcp != NULL) {
10973                 unsigned char *addr;
10974                 int len;
10975
10976                 addr = of_get_property(pcp->prom_node, "local-mac-address",
10977                                         &len);
10978                 if (addr && len == 6) {
10979                         memcpy(dev->dev_addr, addr, 6);
10980                         memcpy(dev->perm_addr, dev->dev_addr, 6);
10981                         return 0;
10982                 }
10983         }
10984         return -ENODEV;
10985 }
10986
10987 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10988 {
10989         struct net_device *dev = tp->dev;
10990
10991         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10992         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10993         return 0;
10994 }
10995 #endif
10996
10997 static int __devinit tg3_get_device_address(struct tg3 *tp)
10998 {
10999         struct net_device *dev = tp->dev;
11000         u32 hi, lo, mac_offset;
11001         int addr_ok = 0;
11002
11003 #ifdef CONFIG_SPARC64
11004         if (!tg3_get_macaddr_sparc(tp))
11005                 return 0;
11006 #endif
11007
11008         mac_offset = 0x7c;
11009         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11010             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11011                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11012                         mac_offset = 0xcc;
11013                 if (tg3_nvram_lock(tp))
11014                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11015                 else
11016                         tg3_nvram_unlock(tp);
11017         }
11018         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11019                 mac_offset = 0x10;
11020
11021         /* First try to get it from MAC address mailbox. */
11022         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11023         if ((hi >> 16) == 0x484b) {
11024                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11025                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11026
11027                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11028                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11029                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11030                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11031                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11032
11033                 /* Some old bootcode may report a 0 MAC address in SRAM */
11034                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11035         }
11036         if (!addr_ok) {
11037                 /* Next, try NVRAM. */
11038                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11039                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11040                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11041                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11042                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11043                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11044                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11045                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11046                 }
11047                 /* Finally just fetch it out of the MAC control regs. */
11048                 else {
11049                         hi = tr32(MAC_ADDR_0_HIGH);
11050                         lo = tr32(MAC_ADDR_0_LOW);
11051
11052                         dev->dev_addr[5] = lo & 0xff;
11053                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11054                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11055                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11056                         dev->dev_addr[1] = hi & 0xff;
11057                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11058                 }
11059         }
11060
11061         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11062 #ifdef CONFIG_SPARC64
11063                 if (!tg3_get_default_macaddr_sparc(tp))
11064                         return 0;
11065 #endif
11066                 return -EINVAL;
11067         }
11068         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11069         return 0;
11070 }
11071
11072 #define BOUNDARY_SINGLE_CACHELINE       1
11073 #define BOUNDARY_MULTI_CACHELINE        2
11074
11075 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11076 {
11077         int cacheline_size;
11078         u8 byte;
11079         int goal;
11080
11081         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11082         if (byte == 0)
11083                 cacheline_size = 1024;
11084         else
11085                 cacheline_size = (int) byte * 4;
11086
11087         /* On 5703 and later chips, the boundary bits have no
11088          * effect.
11089          */
11090         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11091             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11092             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11093                 goto out;
11094
11095 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11096         goal = BOUNDARY_MULTI_CACHELINE;
11097 #else
11098 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11099         goal = BOUNDARY_SINGLE_CACHELINE;
11100 #else
11101         goal = 0;
11102 #endif
11103 #endif
11104
11105         if (!goal)
11106                 goto out;
11107
11108         /* PCI controllers on most RISC systems tend to disconnect
11109          * when a device tries to burst across a cache-line boundary.
11110          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11111          *
11112          * Unfortunately, for PCI-E there are only limited
11113          * write-side controls for this, and thus for reads
11114          * we will still get the disconnects.  We'll also waste
11115          * these PCI cycles for both read and write for chips
11116          * other than 5700 and 5701 which do not implement the
11117          * boundary bits.
11118          */
11119         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11120             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11121                 switch (cacheline_size) {
11122                 case 16:
11123                 case 32:
11124                 case 64:
11125                 case 128:
11126                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11127                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11128                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11129                         } else {
11130                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11131                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11132                         }
11133                         break;
11134
11135                 case 256:
11136                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11137                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11138                         break;
11139
11140                 default:
11141                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11142                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11143                         break;
11144                 };
11145         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11146                 switch (cacheline_size) {
11147                 case 16:
11148                 case 32:
11149                 case 64:
11150                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11151                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11152                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11153                                 break;
11154                         }
11155                         /* fallthrough */
11156                 case 128:
11157                 default:
11158                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11159                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11160                         break;
11161                 };
11162         } else {
11163                 switch (cacheline_size) {
11164                 case 16:
11165                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11166                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11167                                         DMA_RWCTRL_WRITE_BNDRY_16);
11168                                 break;
11169                         }
11170                         /* fallthrough */
11171                 case 32:
11172                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11173                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11174                                         DMA_RWCTRL_WRITE_BNDRY_32);
11175                                 break;
11176                         }
11177                         /* fallthrough */
11178                 case 64:
11179                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11180                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11181                                         DMA_RWCTRL_WRITE_BNDRY_64);
11182                                 break;
11183                         }
11184                         /* fallthrough */
11185                 case 128:
11186                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11187                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11188                                         DMA_RWCTRL_WRITE_BNDRY_128);
11189                                 break;
11190                         }
11191                         /* fallthrough */
11192                 case 256:
11193                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11194                                 DMA_RWCTRL_WRITE_BNDRY_256);
11195                         break;
11196                 case 512:
11197                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11198                                 DMA_RWCTRL_WRITE_BNDRY_512);
11199                         break;
11200                 case 1024:
11201                 default:
11202                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11203                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11204                         break;
11205                 };
11206         }
11207
11208 out:
11209         return val;
11210 }
11211
11212 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11213 {
11214         struct tg3_internal_buffer_desc test_desc;
11215         u32 sram_dma_descs;
11216         int i, ret;
11217
11218         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11219
11220         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11221         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11222         tw32(RDMAC_STATUS, 0);
11223         tw32(WDMAC_STATUS, 0);
11224
11225         tw32(BUFMGR_MODE, 0);
11226         tw32(FTQ_RESET, 0);
11227
11228         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11229         test_desc.addr_lo = buf_dma & 0xffffffff;
11230         test_desc.nic_mbuf = 0x00002100;
11231         test_desc.len = size;
11232
11233         /*
11234          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11235          * the *second* time the tg3 driver was getting loaded after an
11236          * initial scan.
11237          *
11238          * Broadcom tells me:
11239          *   ...the DMA engine is connected to the GRC block and a DMA
11240          *   reset may affect the GRC block in some unpredictable way...
11241          *   The behavior of resets to individual blocks has not been tested.
11242          *
11243          * Broadcom noted the GRC reset will also reset all sub-components.
11244          */
11245         if (to_device) {
11246                 test_desc.cqid_sqid = (13 << 8) | 2;
11247
11248                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11249                 udelay(40);
11250         } else {
11251                 test_desc.cqid_sqid = (16 << 8) | 7;
11252
11253                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11254                 udelay(40);
11255         }
11256         test_desc.flags = 0x00000005;
11257
11258         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11259                 u32 val;
11260
11261                 val = *(((u32 *)&test_desc) + i);
11262                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11263                                        sram_dma_descs + (i * sizeof(u32)));
11264                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11265         }
11266         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11267
11268         if (to_device) {
11269                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11270         } else {
11271                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11272         }
11273
11274         ret = -ENODEV;
11275         for (i = 0; i < 40; i++) {
11276                 u32 val;
11277
11278                 if (to_device)
11279                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11280                 else
11281                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11282                 if ((val & 0xffff) == sram_dma_descs) {
11283                         ret = 0;
11284                         break;
11285                 }
11286
11287                 udelay(100);
11288         }
11289
11290         return ret;
11291 }
11292
11293 #define TEST_BUFFER_SIZE        0x2000
11294
11295 static int __devinit tg3_test_dma(struct tg3 *tp)
11296 {
11297         dma_addr_t buf_dma;
11298         u32 *buf, saved_dma_rwctrl;
11299         int ret;
11300
11301         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11302         if (!buf) {
11303                 ret = -ENOMEM;
11304                 goto out_nofree;
11305         }
11306
11307         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11308                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11309
11310         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11311
11312         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11313                 /* DMA read watermark not used on PCIE */
11314                 tp->dma_rwctrl |= 0x00180000;
11315         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11316                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11317                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11318                         tp->dma_rwctrl |= 0x003f0000;
11319                 else
11320                         tp->dma_rwctrl |= 0x003f000f;
11321         } else {
11322                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11323                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11324                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11325
11326                         /* If the 5704 is behind the EPB bridge, we can
11327                          * do the less restrictive ONE_DMA workaround for
11328                          * better performance.
11329                          */
11330                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11331                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11332                                 tp->dma_rwctrl |= 0x8000;
11333                         else if (ccval == 0x6 || ccval == 0x7)
11334                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11335
11336                         /* Set bit 23 to enable PCIX hw bug fix */
11337                         tp->dma_rwctrl |= 0x009f0000;
11338                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11339                         /* 5780 always in PCIX mode */
11340                         tp->dma_rwctrl |= 0x00144000;
11341                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11342                         /* 5714 always in PCIX mode */
11343                         tp->dma_rwctrl |= 0x00148000;
11344                 } else {
11345                         tp->dma_rwctrl |= 0x001b000f;
11346                 }
11347         }
11348
11349         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11350             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11351                 tp->dma_rwctrl &= 0xfffffff0;
11352
11353         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11354             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11355                 /* Remove this if it causes problems for some boards. */
11356                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11357
11358                 /* On 5700/5701 chips, we need to set this bit.
11359                  * Otherwise the chip will issue cacheline transactions
11360                  * to streamable DMA memory with not all the byte
11361                  * enables turned on.  This is an error on several
11362                  * RISC PCI controllers, in particular sparc64.
11363                  *
11364                  * On 5703/5704 chips, this bit has been reassigned
11365                  * a different meaning.  In particular, it is used
11366                  * on those chips to enable a PCI-X workaround.
11367                  */
11368                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11369         }
11370
11371         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11372
11373 #if 0
11374         /* Unneeded, already done by tg3_get_invariants.  */
11375         tg3_switch_clocks(tp);
11376 #endif
11377
11378         ret = 0;
11379         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11380             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11381                 goto out;
11382
11383         /* It is best to perform DMA test with maximum write burst size
11384          * to expose the 5700/5701 write DMA bug.
11385          */
11386         saved_dma_rwctrl = tp->dma_rwctrl;
11387         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11388         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11389
11390         while (1) {
11391                 u32 *p = buf, i;
11392
11393                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11394                         p[i] = i;
11395
11396                 /* Send the buffer to the chip. */
11397                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11398                 if (ret) {
11399                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11400                         break;
11401                 }
11402
11403 #if 0
11404                 /* validate data reached card RAM correctly. */
11405                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11406                         u32 val;
11407                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11408                         if (le32_to_cpu(val) != p[i]) {
11409                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11410                                 /* ret = -ENODEV here? */
11411                         }
11412                         p[i] = 0;
11413                 }
11414 #endif
11415                 /* Now read it back. */
11416                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11417                 if (ret) {
11418                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11419
11420                         break;
11421                 }
11422
11423                 /* Verify it. */
11424                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11425                         if (p[i] == i)
11426                                 continue;
11427
11428                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11429                             DMA_RWCTRL_WRITE_BNDRY_16) {
11430                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11431                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11432                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11433                                 break;
11434                         } else {
11435                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11436                                 ret = -ENODEV;
11437                                 goto out;
11438                         }
11439                 }
11440
11441                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11442                         /* Success. */
11443                         ret = 0;
11444                         break;
11445                 }
11446         }
11447         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11448             DMA_RWCTRL_WRITE_BNDRY_16) {
11449                 static struct pci_device_id dma_wait_state_chipsets[] = {
11450                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11451                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11452                         { },
11453                 };
11454
11455                 /* DMA test passed without adjusting DMA boundary,
11456                  * now look for chipsets that are known to expose the
11457                  * DMA bug without failing the test.
11458                  */
11459                 if (pci_dev_present(dma_wait_state_chipsets)) {
11460                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11461                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11462                 }
11463                 else
11464                         /* Safe to use the calculated DMA boundary. */
11465                         tp->dma_rwctrl = saved_dma_rwctrl;
11466
11467                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11468         }
11469
11470 out:
11471         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11472 out_nofree:
11473         return ret;
11474 }
11475
11476 static void __devinit tg3_init_link_config(struct tg3 *tp)
11477 {
11478         tp->link_config.advertising =
11479                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11480                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11481                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11482                  ADVERTISED_Autoneg | ADVERTISED_MII);
11483         tp->link_config.speed = SPEED_INVALID;
11484         tp->link_config.duplex = DUPLEX_INVALID;
11485         tp->link_config.autoneg = AUTONEG_ENABLE;
11486         tp->link_config.active_speed = SPEED_INVALID;
11487         tp->link_config.active_duplex = DUPLEX_INVALID;
11488         tp->link_config.phy_is_low_power = 0;
11489         tp->link_config.orig_speed = SPEED_INVALID;
11490         tp->link_config.orig_duplex = DUPLEX_INVALID;
11491         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11492 }
11493
11494 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11495 {
11496         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11497                 tp->bufmgr_config.mbuf_read_dma_low_water =
11498                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11499                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11500                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11501                 tp->bufmgr_config.mbuf_high_water =
11502                         DEFAULT_MB_HIGH_WATER_5705;
11503                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11504                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11505                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11506                         tp->bufmgr_config.mbuf_high_water =
11507                                 DEFAULT_MB_HIGH_WATER_5906;
11508                 }
11509
11510                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11511                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11512                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11513                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11514                 tp->bufmgr_config.mbuf_high_water_jumbo =
11515                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11516         } else {
11517                 tp->bufmgr_config.mbuf_read_dma_low_water =
11518                         DEFAULT_MB_RDMA_LOW_WATER;
11519                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11520                         DEFAULT_MB_MACRX_LOW_WATER;
11521                 tp->bufmgr_config.mbuf_high_water =
11522                         DEFAULT_MB_HIGH_WATER;
11523
11524                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11525                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11526                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11527                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11528                 tp->bufmgr_config.mbuf_high_water_jumbo =
11529                         DEFAULT_MB_HIGH_WATER_JUMBO;
11530         }
11531
11532         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11533         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11534 }
11535
11536 static char * __devinit tg3_phy_string(struct tg3 *tp)
11537 {
11538         switch (tp->phy_id & PHY_ID_MASK) {
11539         case PHY_ID_BCM5400:    return "5400";
11540         case PHY_ID_BCM5401:    return "5401";
11541         case PHY_ID_BCM5411:    return "5411";
11542         case PHY_ID_BCM5701:    return "5701";
11543         case PHY_ID_BCM5703:    return "5703";
11544         case PHY_ID_BCM5704:    return "5704";
11545         case PHY_ID_BCM5705:    return "5705";
11546         case PHY_ID_BCM5750:    return "5750";
11547         case PHY_ID_BCM5752:    return "5752";
11548         case PHY_ID_BCM5714:    return "5714";
11549         case PHY_ID_BCM5780:    return "5780";
11550         case PHY_ID_BCM5755:    return "5755";
11551         case PHY_ID_BCM5787:    return "5787";
11552         case PHY_ID_BCM5756:    return "5722/5756";
11553         case PHY_ID_BCM5906:    return "5906";
11554         case PHY_ID_BCM8002:    return "8002/serdes";
11555         case 0:                 return "serdes";
11556         default:                return "unknown";
11557         };
11558 }
11559
11560 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11561 {
11562         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11563                 strcpy(str, "PCI Express");
11564                 return str;
11565         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11566                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11567
11568                 strcpy(str, "PCIX:");
11569
11570                 if ((clock_ctrl == 7) ||
11571                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11572                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11573                         strcat(str, "133MHz");
11574                 else if (clock_ctrl == 0)
11575                         strcat(str, "33MHz");
11576                 else if (clock_ctrl == 2)
11577                         strcat(str, "50MHz");
11578                 else if (clock_ctrl == 4)
11579                         strcat(str, "66MHz");
11580                 else if (clock_ctrl == 6)
11581                         strcat(str, "100MHz");
11582         } else {
11583                 strcpy(str, "PCI:");
11584                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11585                         strcat(str, "66MHz");
11586                 else
11587                         strcat(str, "33MHz");
11588         }
11589         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11590                 strcat(str, ":32-bit");
11591         else
11592                 strcat(str, ":64-bit");
11593         return str;
11594 }
11595
11596 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11597 {
11598         struct pci_dev *peer;
11599         unsigned int func, devnr = tp->pdev->devfn & ~7;
11600
11601         for (func = 0; func < 8; func++) {
11602                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11603                 if (peer && peer != tp->pdev)
11604                         break;
11605                 pci_dev_put(peer);
11606         }
11607         /* 5704 can be configured in single-port mode, set peer to
11608          * tp->pdev in that case.
11609          */
11610         if (!peer) {
11611                 peer = tp->pdev;
11612                 return peer;
11613         }
11614
11615         /*
11616          * We don't need to keep the refcount elevated; there's no way
11617          * to remove one half of this device without removing the other
11618          */
11619         pci_dev_put(peer);
11620
11621         return peer;
11622 }
11623
11624 static void __devinit tg3_init_coal(struct tg3 *tp)
11625 {
11626         struct ethtool_coalesce *ec = &tp->coal;
11627
11628         memset(ec, 0, sizeof(*ec));
11629         ec->cmd = ETHTOOL_GCOALESCE;
11630         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11631         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11632         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11633         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11634         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11635         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11636         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11637         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11638         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11639
11640         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11641                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11642                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11643                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11644                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11645                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11646         }
11647
11648         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11649                 ec->rx_coalesce_usecs_irq = 0;
11650                 ec->tx_coalesce_usecs_irq = 0;
11651                 ec->stats_block_coalesce_usecs = 0;
11652         }
11653 }
11654
11655 static int __devinit tg3_init_one(struct pci_dev *pdev,
11656                                   const struct pci_device_id *ent)
11657 {
11658         static int tg3_version_printed = 0;
11659         unsigned long tg3reg_base, tg3reg_len;
11660         struct net_device *dev;
11661         struct tg3 *tp;
11662         int i, err, pm_cap;
11663         char str[40];
11664         u64 dma_mask, persist_dma_mask;
11665
11666         if (tg3_version_printed++ == 0)
11667                 printk(KERN_INFO "%s", version);
11668
11669         err = pci_enable_device(pdev);
11670         if (err) {
11671                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11672                        "aborting.\n");
11673                 return err;
11674         }
11675
11676         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11677                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11678                        "base address, aborting.\n");
11679                 err = -ENODEV;
11680                 goto err_out_disable_pdev;
11681         }
11682
11683         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11684         if (err) {
11685                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11686                        "aborting.\n");
11687                 goto err_out_disable_pdev;
11688         }
11689
11690         pci_set_master(pdev);
11691
11692         /* Find power-management capability. */
11693         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11694         if (pm_cap == 0) {
11695                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11696                        "aborting.\n");
11697                 err = -EIO;
11698                 goto err_out_free_res;
11699         }
11700
11701         tg3reg_base = pci_resource_start(pdev, 0);
11702         tg3reg_len = pci_resource_len(pdev, 0);
11703
11704         dev = alloc_etherdev(sizeof(*tp));
11705         if (!dev) {
11706                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11707                 err = -ENOMEM;
11708                 goto err_out_free_res;
11709         }
11710
11711         SET_MODULE_OWNER(dev);
11712         SET_NETDEV_DEV(dev, &pdev->dev);
11713
11714 #if TG3_VLAN_TAG_USED
11715         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11716         dev->vlan_rx_register = tg3_vlan_rx_register;
11717         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11718 #endif
11719
11720         tp = netdev_priv(dev);
11721         tp->pdev = pdev;
11722         tp->dev = dev;
11723         tp->pm_cap = pm_cap;
11724         tp->mac_mode = TG3_DEF_MAC_MODE;
11725         tp->rx_mode = TG3_DEF_RX_MODE;
11726         tp->tx_mode = TG3_DEF_TX_MODE;
11727         tp->mi_mode = MAC_MI_MODE_BASE;
11728         if (tg3_debug > 0)
11729                 tp->msg_enable = tg3_debug;
11730         else
11731                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11732
11733         /* The word/byte swap controls here control register access byte
11734          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11735          * setting below.
11736          */
11737         tp->misc_host_ctrl =
11738                 MISC_HOST_CTRL_MASK_PCI_INT |
11739                 MISC_HOST_CTRL_WORD_SWAP |
11740                 MISC_HOST_CTRL_INDIR_ACCESS |
11741                 MISC_HOST_CTRL_PCISTATE_RW;
11742
11743         /* The NONFRM (non-frame) byte/word swap controls take effect
11744          * on descriptor entries, anything which isn't packet data.
11745          *
11746          * The StrongARM chips on the board (one for tx, one for rx)
11747          * are running in big-endian mode.
11748          */
11749         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11750                         GRC_MODE_WSWAP_NONFRM_DATA);
11751 #ifdef __BIG_ENDIAN
11752         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11753 #endif
11754         spin_lock_init(&tp->lock);
11755         spin_lock_init(&tp->indirect_lock);
11756         INIT_WORK(&tp->reset_task, tg3_reset_task);
11757
11758         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11759         if (tp->regs == 0UL) {
11760                 printk(KERN_ERR PFX "Cannot map device registers, "
11761                        "aborting.\n");
11762                 err = -ENOMEM;
11763                 goto err_out_free_dev;
11764         }
11765
11766         tg3_init_link_config(tp);
11767
11768         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11769         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11770         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11771
11772         dev->open = tg3_open;
11773         dev->stop = tg3_close;
11774         dev->get_stats = tg3_get_stats;
11775         dev->set_multicast_list = tg3_set_rx_mode;
11776         dev->set_mac_address = tg3_set_mac_addr;
11777         dev->do_ioctl = tg3_ioctl;
11778         dev->tx_timeout = tg3_tx_timeout;
11779         dev->poll = tg3_poll;
11780         dev->ethtool_ops = &tg3_ethtool_ops;
11781         dev->weight = 64;
11782         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11783         dev->change_mtu = tg3_change_mtu;
11784         dev->irq = pdev->irq;
11785 #ifdef CONFIG_NET_POLL_CONTROLLER
11786         dev->poll_controller = tg3_poll_controller;
11787 #endif
11788
11789         err = tg3_get_invariants(tp);
11790         if (err) {
11791                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11792                        "aborting.\n");
11793                 goto err_out_iounmap;
11794         }
11795
11796         /* The EPB bridge inside 5714, 5715, and 5780 and any
11797          * device behind the EPB cannot support DMA addresses > 40-bit.
11798          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11799          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11800          * do DMA address check in tg3_start_xmit().
11801          */
11802         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11803                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11804         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11805                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11806 #ifdef CONFIG_HIGHMEM
11807                 dma_mask = DMA_64BIT_MASK;
11808 #endif
11809         } else
11810                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11811
11812         /* Configure DMA attributes. */
11813         if (dma_mask > DMA_32BIT_MASK) {
11814                 err = pci_set_dma_mask(pdev, dma_mask);
11815                 if (!err) {
11816                         dev->features |= NETIF_F_HIGHDMA;
11817                         err = pci_set_consistent_dma_mask(pdev,
11818                                                           persist_dma_mask);
11819                         if (err < 0) {
11820                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11821                                        "DMA for consistent allocations\n");
11822                                 goto err_out_iounmap;
11823                         }
11824                 }
11825         }
11826         if (err || dma_mask == DMA_32BIT_MASK) {
11827                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11828                 if (err) {
11829                         printk(KERN_ERR PFX "No usable DMA configuration, "
11830                                "aborting.\n");
11831                         goto err_out_iounmap;
11832                 }
11833         }
11834
11835         tg3_init_bufmgr_config(tp);
11836
11837 #if TG3_TSO_SUPPORT != 0
11838         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11839                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11840         }
11841         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11842             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11843             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11844             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11845             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11846                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11847         } else {
11848                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11849         }
11850
11851         /* TSO is on by default on chips that support hardware TSO.
11852          * Firmware TSO on older chips gives lower performance, so it
11853          * is off by default, but can be enabled using ethtool.
11854          */
11855         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11856                 dev->features |= NETIF_F_TSO;
11857                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11858                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11859                         dev->features |= NETIF_F_TSO6;
11860         }
11861
11862 #endif
11863
11864         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11865             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11866             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11867                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11868                 tp->rx_pending = 63;
11869         }
11870
11871         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11872             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11873                 tp->pdev_peer = tg3_find_peer(tp);
11874
11875         err = tg3_get_device_address(tp);
11876         if (err) {
11877                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11878                        "aborting.\n");
11879                 goto err_out_iounmap;
11880         }
11881
11882         /*
11883          * Reset chip in case UNDI or EFI driver did not shutdown
11884          * DMA self test will enable WDMAC and we'll see (spurious)
11885          * pending DMA on the PCI bus at that point.
11886          */
11887         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11888             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11889                 pci_save_state(tp->pdev);
11890                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11891                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11892         }
11893
11894         err = tg3_test_dma(tp);
11895         if (err) {
11896                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11897                 goto err_out_iounmap;
11898         }
11899
11900         /* Tigon3 can do ipv4 only... and some chips have buggy
11901          * checksumming.
11902          */
11903         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11904                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11905                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11906                         dev->features |= NETIF_F_HW_CSUM;
11907                 else
11908                         dev->features |= NETIF_F_IP_CSUM;
11909                 dev->features |= NETIF_F_SG;
11910                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11911         } else
11912                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11913
11914         /* flow control autonegotiation is default behavior */
11915         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11916
11917         tg3_init_coal(tp);
11918
11919         /* Now that we have fully setup the chip, save away a snapshot
11920          * of the PCI config space.  We need to restore this after
11921          * GRC_MISC_CFG core clock resets and some resume events.
11922          */
11923         pci_save_state(tp->pdev);
11924
11925         pci_set_drvdata(pdev, dev);
11926
11927         err = register_netdev(dev);
11928         if (err) {
11929                 printk(KERN_ERR PFX "Cannot register net device, "
11930                        "aborting.\n");
11931                 goto err_out_iounmap;
11932         }
11933
11934         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11935                dev->name,
11936                tp->board_part_number,
11937                tp->pci_chip_rev_id,
11938                tg3_phy_string(tp),
11939                tg3_bus_string(tp, str),
11940                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11941                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11942                  "10/100/1000Base-T")));
11943
11944         for (i = 0; i < 6; i++)
11945                 printk("%2.2x%c", dev->dev_addr[i],
11946                        i == 5 ? '\n' : ':');
11947
11948         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11949                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11950                "TSOcap[%d] \n",
11951                dev->name,
11952                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11953                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11954                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11955                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11956                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11957                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11958                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11959         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11960                dev->name, tp->dma_rwctrl,
11961                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11962                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11963
11964         return 0;
11965
11966 err_out_iounmap:
11967         if (tp->regs) {
11968                 iounmap(tp->regs);
11969                 tp->regs = NULL;
11970         }
11971
11972 err_out_free_dev:
11973         free_netdev(dev);
11974
11975 err_out_free_res:
11976         pci_release_regions(pdev);
11977
11978 err_out_disable_pdev:
11979         pci_disable_device(pdev);
11980         pci_set_drvdata(pdev, NULL);
11981         return err;
11982 }
11983
11984 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11985 {
11986         struct net_device *dev = pci_get_drvdata(pdev);
11987
11988         if (dev) {
11989                 struct tg3 *tp = netdev_priv(dev);
11990
11991                 flush_scheduled_work();
11992                 unregister_netdev(dev);
11993                 if (tp->regs) {
11994                         iounmap(tp->regs);
11995                         tp->regs = NULL;
11996                 }
11997                 free_netdev(dev);
11998                 pci_release_regions(pdev);
11999                 pci_disable_device(pdev);
12000                 pci_set_drvdata(pdev, NULL);
12001         }
12002 }
12003
12004 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12005 {
12006         struct net_device *dev = pci_get_drvdata(pdev);
12007         struct tg3 *tp = netdev_priv(dev);
12008         int err;
12009
12010         if (!netif_running(dev))
12011                 return 0;
12012
12013         flush_scheduled_work();
12014         tg3_netif_stop(tp);
12015
12016         del_timer_sync(&tp->timer);
12017
12018         tg3_full_lock(tp, 1);
12019         tg3_disable_ints(tp);
12020         tg3_full_unlock(tp);
12021
12022         netif_device_detach(dev);
12023
12024         tg3_full_lock(tp, 0);
12025         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12026         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12027         tg3_full_unlock(tp);
12028
12029         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12030         if (err) {
12031                 tg3_full_lock(tp, 0);
12032
12033                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12034                 if (tg3_restart_hw(tp, 1))
12035                         goto out;
12036
12037                 tp->timer.expires = jiffies + tp->timer_offset;
12038                 add_timer(&tp->timer);
12039
12040                 netif_device_attach(dev);
12041                 tg3_netif_start(tp);
12042
12043 out:
12044                 tg3_full_unlock(tp);
12045         }
12046
12047         return err;
12048 }
12049
12050 static int tg3_resume(struct pci_dev *pdev)
12051 {
12052         struct net_device *dev = pci_get_drvdata(pdev);
12053         struct tg3 *tp = netdev_priv(dev);
12054         int err;
12055
12056         if (!netif_running(dev))
12057                 return 0;
12058
12059         pci_restore_state(tp->pdev);
12060
12061         err = tg3_set_power_state(tp, PCI_D0);
12062         if (err)
12063                 return err;
12064
12065         netif_device_attach(dev);
12066
12067         tg3_full_lock(tp, 0);
12068
12069         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12070         err = tg3_restart_hw(tp, 1);
12071         if (err)
12072                 goto out;
12073
12074         tp->timer.expires = jiffies + tp->timer_offset;
12075         add_timer(&tp->timer);
12076
12077         tg3_netif_start(tp);
12078
12079 out:
12080         tg3_full_unlock(tp);
12081
12082         return err;
12083 }
12084
12085 static struct pci_driver tg3_driver = {
12086         .name           = DRV_MODULE_NAME,
12087         .id_table       = tg3_pci_tbl,
12088         .probe          = tg3_init_one,
12089         .remove         = __devexit_p(tg3_remove_one),
12090         .suspend        = tg3_suspend,
12091         .resume         = tg3_resume
12092 };
12093
12094 static int __init tg3_init(void)
12095 {
12096         return pci_register_driver(&tg3_driver);
12097 }
12098
12099 static void __exit tg3_cleanup(void)
12100 {
12101         pci_unregister_driver(&tg3_driver);
12102 }
12103
12104 module_init(tg3_init);
12105 module_exit(tg3_cleanup);