drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/ip.h>
  38 #include <linux/tcp.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <net/checksum.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC64
  51 #include <asm/idprom.h>
  52 #include <asm/oplib.h>
  53 #include <asm/pbm.h>
  54 #endif
  55
  56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  57 #define TG3_VLAN_TAG_USED 1
  58 #else
  59 #define TG3_VLAN_TAG_USED 0
  60 #endif
  61
  62 #ifdef NETIF_F_TSO
  63 #define TG3_TSO_SUPPORT 1
  64 #else
  65 #define TG3_TSO_SUPPORT 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define PFX DRV_MODULE_NAME     ": "
  72 #define DRV_MODULE_VERSION      "3.56"
  73 #define DRV_MODULE_RELDATE      "Apr 1, 2006"
  74
  75 #define TG3_DEF_MAC_MODE        0
  76 #define TG3_DEF_RX_MODE         0
  77 #define TG3_DEF_TX_MODE         0
  78 #define TG3_DEF_MSG_ENABLE        \
  79         (NETIF_MSG_DRV          | \
  80          NETIF_MSG_PROBE        | \
  81          NETIF_MSG_LINK         | \
  82          NETIF_MSG_TIMER        | \
  83          NETIF_MSG_IFDOWN       | \
  84          NETIF_MSG_IFUP         | \
  85          NETIF_MSG_RX_ERR       | \
  86          NETIF_MSG_TX_ERR)
  87
  88 /* length of time before we decide the hardware is borked,
  89  * and dev->tx_timeout() should be called to fix the problem
  90  */
  91 #define TG3_TX_TIMEOUT                  (5 * HZ)
  92
  93 /* hardware minimum and maximum for a single frame's data payload */
  94 #define TG3_MIN_MTU                     60
  95 #define TG3_MAX_MTU(tp) \
  96         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  97
  98 /* These numbers seem to be hard coded in the NIC firmware somehow.
  99  * You can't change the ring sizes, but you can change where you place
 100  * them in the NIC onboard memory.
 101  */
 102 #define TG3_RX_RING_SIZE                512
 103 #define TG3_DEF_RX_RING_PENDING         200
 104 #define TG3_RX_JUMBO_RING_SIZE          256
 105 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                    TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define TX_BUFFS_AVAIL(TP)                                              \
 128         ((TP)->tx_pending -                                             \
 129          (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
 130 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 131
 132 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 133 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 134
 135 /* minimum number of free TX descriptors required to wake up TX process */
 136 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 137
 138 /* number of ETHTOOL_GSTATS u64's */
 139 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 140
 141 #define TG3_NUM_TEST            6
 142
 143 static char version[] __devinitdata =
 144         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 145
 146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 148 MODULE_LICENSE("GPL");
 149 MODULE_VERSION(DRV_MODULE_VERSION);
 150
 151 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 152 module_param(tg3_debug, int, 0);
 153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 154
 155 static struct pci_device_id tg3_pci_tbl[] = {
 156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754,
 225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 226         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
 227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 228         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
 229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 230         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
 231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 232         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
 233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 234         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
 235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 236         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
 237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 238         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S,
 239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 240         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
 241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 242         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S,
 243           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 244         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
 245           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 246         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
 247           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 248         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 249           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 250         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 251           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 252         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 253           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 254         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 255           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 256         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 257           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 258         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 259           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 260         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 261           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 262         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 263           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 264         { 0, }
 265 };
 266
 267 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 268
 269 static struct {
 270         const char string[ETH_GSTRING_LEN];
 271 } ethtool_stats_keys[TG3_NUM_STATS] = {
 272         { "rx_octets" },
 273         { "rx_fragments" },
 274         { "rx_ucast_packets" },
 275         { "rx_mcast_packets" },
 276         { "rx_bcast_packets" },
 277         { "rx_fcs_errors" },
 278         { "rx_align_errors" },
 279         { "rx_xon_pause_rcvd" },
 280         { "rx_xoff_pause_rcvd" },
 281         { "rx_mac_ctrl_rcvd" },
 282         { "rx_xoff_entered" },
 283         { "rx_frame_too_long_errors" },
 284         { "rx_jabbers" },
 285         { "rx_undersize_packets" },
 286         { "rx_in_length_errors" },
 287         { "rx_out_length_errors" },
 288         { "rx_64_or_less_octet_packets" },
 289         { "rx_65_to_127_octet_packets" },
 290         { "rx_128_to_255_octet_packets" },
 291         { "rx_256_to_511_octet_packets" },
 292         { "rx_512_to_1023_octet_packets" },
 293         { "rx_1024_to_1522_octet_packets" },
 294         { "rx_1523_to_2047_octet_packets" },
 295         { "rx_2048_to_4095_octet_packets" },
 296         { "rx_4096_to_8191_octet_packets" },
 297         { "rx_8192_to_9022_octet_packets" },
 298
 299         { "tx_octets" },
 300         { "tx_collisions" },
 301
 302         { "tx_xon_sent" },
 303         { "tx_xoff_sent" },
 304         { "tx_flow_control" },
 305         { "tx_mac_errors" },
 306         { "tx_single_collisions" },
 307         { "tx_mult_collisions" },
 308         { "tx_deferred" },
 309         { "tx_excessive_collisions" },
 310         { "tx_late_collisions" },
 311         { "tx_collide_2times" },
 312         { "tx_collide_3times" },
 313         { "tx_collide_4times" },
 314         { "tx_collide_5times" },
 315         { "tx_collide_6times" },
 316         { "tx_collide_7times" },
 317         { "tx_collide_8times" },
 318         { "tx_collide_9times" },
 319         { "tx_collide_10times" },
 320         { "tx_collide_11times" },
 321         { "tx_collide_12times" },
 322         { "tx_collide_13times" },
 323         { "tx_collide_14times" },
 324         { "tx_collide_15times" },
 325         { "tx_ucast_packets" },
 326         { "tx_mcast_packets" },
 327         { "tx_bcast_packets" },
 328         { "tx_carrier_sense_errors" },
 329         { "tx_discards" },
 330         { "tx_errors" },
 331
 332         { "dma_writeq_full" },
 333         { "dma_write_prioq_full" },
 334         { "rxbds_empty" },
 335         { "rx_discards" },
 336         { "rx_errors" },
 337         { "rx_threshold_hit" },
 338
 339         { "dma_readq_full" },
 340         { "dma_read_prioq_full" },
 341         { "tx_comp_queue_full" },
 342
 343         { "ring_set_send_prod_index" },
 344         { "ring_status_update" },
 345         { "nic_irqs" },
 346         { "nic_avoided_irqs" },
 347         { "nic_tx_threshold_hit" }
 348 };
 349
 350 static struct {
 351         const char string[ETH_GSTRING_LEN];
 352 } ethtool_test_keys[TG3_NUM_TEST] = {
 353         { "nvram test     (online) " },
 354         { "link test      (online) " },
 355         { "register test  (offline)" },
 356         { "memory test    (offline)" },
 357         { "loopback test  (offline)" },
 358         { "interrupt test (offline)" },
 359 };
 360
 361 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->regs + off);
 364 }
 365
 366 static u32 tg3_read32(struct tg3 *tp, u32 off)
 367 {
 368         return (readl(tp->regs + off));
 369 }
 370
 371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         unsigned long flags;
 374
 375         spin_lock_irqsave(&tp->indirect_lock, flags);
 376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 379 }
 380
 381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384         readl(tp->regs + off);
 385 }
 386
 387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 388 {
 389         unsigned long flags;
 390         u32 val;
 391
 392         spin_lock_irqsave(&tp->indirect_lock, flags);
 393         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 394         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 395         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 396         return val;
 397 }
 398
 399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 405                                        TG3_64BIT_REG_LOW, val);
 406                 return;
 407         }
 408         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 409                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 410                                        TG3_64BIT_REG_LOW, val);
 411                 return;
 412         }
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418
 419         /* In indirect mode when disabling interrupts, we also need
 420          * to clear the interrupt bit in the GRC local ctrl register.
 421          */
 422         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 423             (val == 0x1)) {
 424                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 425                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 426         }
 427 }
 428
 429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 430 {
 431         unsigned long flags;
 432         u32 val;
 433
 434         spin_lock_irqsave(&tp->indirect_lock, flags);
 435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 436         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 438         return val;
 439 }
 440
 441 /* usec_wait specifies the wait time in usec when writing to certain registers
 442  * where it is unsafe to read back the register without some delay.
 443  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 444  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 445  */
 446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 447 {
 448         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 449             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 450                 /* Non-posted methods */
 451                 tp->write32(tp, off, val);
 452         else {
 453                 /* Posted method */
 454                 tg3_write32(tp, off, val);
 455                 if (usec_wait)
 456                         udelay(usec_wait);
 457                 tp->read32(tp, off);
 458         }
 459         /* Wait again after the read for the posted method to guarantee that
 460          * the wait time is met.
 461          */
 462         if (usec_wait)
 463                 udelay(usec_wait);
 464 }
 465
 466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 467 {
 468         tp->write32_mbox(tp, off, val);
 469         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 470             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 471                 tp->read32_mbox(tp, off);
 472 }
 473
 474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 475 {
 476         void __iomem *mbox = tp->regs + off;
 477         writel(val, mbox);
 478         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 479                 writel(val, mbox);
 480         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 481                 readl(mbox);
 482 }
 483
 484 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 485 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 486 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 487 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 488 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 489
 490 #define tw32(reg,val)           tp->write32(tp, reg, val)
 491 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 492 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 493 #define tr32(reg)               tp->read32(tp, reg)
 494
 495 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         unsigned long flags;
 498
 499         spin_lock_irqsave(&tp->indirect_lock, flags);
 500         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 501                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         } else {
 507                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 508                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 509
 510                 /* Always leave this as zero. */
 511                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 512         }
 513         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 514 }
 515
 516 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 517 {
 518         unsigned long flags;
 519
 520         spin_lock_irqsave(&tp->indirect_lock, flags);
 521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 524
 525                 /* Always leave this as zero. */
 526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 527         } else {
 528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 530
 531                 /* Always leave this as zero. */
 532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 533         }
 534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 535 }
 536
 537 static void tg3_disable_ints(struct tg3 *tp)
 538 {
 539         tw32(TG3PCI_MISC_HOST_CTRL,
 540              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 541         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 542 }
 543
 544 static inline void tg3_cond_int(struct tg3 *tp)
 545 {
 546         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 547             (tp->hw_status->status & SD_STATUS_UPDATED))
 548                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 549 }
 550
 551 static void tg3_enable_ints(struct tg3 *tp)
 552 {
 553         tp->irq_sync = 0;
 554         wmb();
 555
 556         tw32(TG3PCI_MISC_HOST_CTRL,
 557              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 558         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 559                        (tp->last_tag << 24));
 560         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 561                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 562                                (tp->last_tag << 24));
 563         tg3_cond_int(tp);
 564 }
 565
 566 static inline unsigned int tg3_has_work(struct tg3 *tp)
 567 {
 568         struct tg3_hw_status *sblk = tp->hw_status;
 569         unsigned int work_exists = 0;
 570
 571         /* check for phy events */
 572         if (!(tp->tg3_flags &
 573               (TG3_FLAG_USE_LINKCHG_REG |
 574                TG3_FLAG_POLL_SERDES))) {
 575                 if (sblk->status & SD_STATUS_LINK_CHG)
 576                         work_exists = 1;
 577         }
 578         /* check for RX/TX work to do */
 579         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 580             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 581                 work_exists = 1;
 582
 583         return work_exists;
 584 }
 585
 586 /* tg3_restart_ints
 587  *  similar to tg3_enable_ints, but it accurately determines whether there
 588  *  is new work pending and can return without flushing the PIO write
 589  *  which reenables interrupts
 590  */
 591 static void tg3_restart_ints(struct tg3 *tp)
 592 {
 593         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 594                      tp->last_tag << 24);
 595         mmiowb();
 596
 597         /* When doing tagged status, this work check is unnecessary.
 598          * The last_tag we write above tells the chip which piece of
 599          * work we've completed.
 600          */
 601         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 602             tg3_has_work(tp))
 603                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 604                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 605 }
 606
 607 static inline void tg3_netif_stop(struct tg3 *tp)
 608 {
 609         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 610         netif_poll_disable(tp->dev);
 611         netif_tx_disable(tp->dev);
 612 }
 613
 614 static inline void tg3_netif_start(struct tg3 *tp)
 615 {
 616         netif_wake_queue(tp->dev);
 617         /* NOTE: unconditional netif_wake_queue is only appropriate
 618          * so long as all callers are assured to have free tx slots
 619          * (such as after tg3_init_hw)
 620          */
 621         netif_poll_enable(tp->dev);
 622         tp->hw_status->status |= SD_STATUS_UPDATED;
 623         tg3_enable_ints(tp);
 624 }
 625
 626 static void tg3_switch_clocks(struct tg3 *tp)
 627 {
 628         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 629         u32 orig_clock_ctrl;
 630
 631         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 632                 return;
 633
 634         orig_clock_ctrl = clock_ctrl;
 635         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 636                        CLOCK_CTRL_CLKRUN_OENABLE |
 637                        0x1f);
 638         tp->pci_clock_ctrl = clock_ctrl;
 639
 640         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 641                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 642                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 643                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 644                 }
 645         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 646                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 647                             clock_ctrl |
 648                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 649                             40);
 650                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 651                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 652                             40);
 653         }
 654         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 655 }
 656
 657 #define PHY_BUSY_LOOPS  5000
 658
 659 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 660 {
 661         u32 frame_val;
 662         unsigned int loops;
 663         int ret;
 664
 665         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 666                 tw32_f(MAC_MI_MODE,
 667                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 668                 udelay(80);
 669         }
 670
 671         *val = 0x0;
 672
 673         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 674                       MI_COM_PHY_ADDR_MASK);
 675         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 676                       MI_COM_REG_ADDR_MASK);
 677         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 678
 679         tw32_f(MAC_MI_COM, frame_val);
 680
 681         loops = PHY_BUSY_LOOPS;
 682         while (loops != 0) {
 683                 udelay(10);
 684                 frame_val = tr32(MAC_MI_COM);
 685
 686                 if ((frame_val & MI_COM_BUSY) == 0) {
 687                         udelay(5);
 688                         frame_val = tr32(MAC_MI_COM);
 689                         break;
 690                 }
 691                 loops -= 1;
 692         }
 693
 694         ret = -EBUSY;
 695         if (loops != 0) {
 696                 *val = frame_val & MI_COM_DATA_MASK;
 697                 ret = 0;
 698         }
 699
 700         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 701                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 702                 udelay(80);
 703         }
 704
 705         return ret;
 706 }
 707
 708 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 709 {
 710         u32 frame_val;
 711         unsigned int loops;
 712         int ret;
 713
 714         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 715                 tw32_f(MAC_MI_MODE,
 716                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 717                 udelay(80);
 718         }
 719
 720         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 721                       MI_COM_PHY_ADDR_MASK);
 722         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 723                       MI_COM_REG_ADDR_MASK);
 724         frame_val |= (val & MI_COM_DATA_MASK);
 725         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 726
 727         tw32_f(MAC_MI_COM, frame_val);
 728
 729         loops = PHY_BUSY_LOOPS;
 730         while (loops != 0) {
 731                 udelay(10);
 732                 frame_val = tr32(MAC_MI_COM);
 733                 if ((frame_val & MI_COM_BUSY) == 0) {
 734                         udelay(5);
 735                         frame_val = tr32(MAC_MI_COM);
 736                         break;
 737                 }
 738                 loops -= 1;
 739         }
 740
 741         ret = -EBUSY;
 742         if (loops != 0)
 743                 ret = 0;
 744
 745         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 746                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 747                 udelay(80);
 748         }
 749
 750         return ret;
 751 }
 752
 753 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 754 {
 755         u32 val;
 756
 757         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 758                 return;
 759
 760         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 761             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 762                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 763                              (val | (1 << 15) | (1 << 4)));
 764 }
 765
 766 static int tg3_bmcr_reset(struct tg3 *tp)
 767 {
 768         u32 phy_control;
 769         int limit, err;
 770
 771         /* OK, reset it, and poll the BMCR_RESET bit until it
 772          * clears or we time out.
 773          */
 774         phy_control = BMCR_RESET;
 775         err = tg3_writephy(tp, MII_BMCR, phy_control);
 776         if (err != 0)
 777                 return -EBUSY;
 778
 779         limit = 5000;
 780         while (limit--) {
 781                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 782                 if (err != 0)
 783                         return -EBUSY;
 784
 785                 if ((phy_control & BMCR_RESET) == 0) {
 786                         udelay(40);
 787                         break;
 788                 }
 789                 udelay(10);
 790         }
 791         if (limit <= 0)
 792                 return -EBUSY;
 793
 794         return 0;
 795 }
 796
 797 static int tg3_wait_macro_done(struct tg3 *tp)
 798 {
 799         int limit = 100;
 800
 801         while (limit--) {
 802                 u32 tmp32;
 803
 804                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 805                         if ((tmp32 & 0x1000) == 0)
 806                                 break;
 807                 }
 808         }
 809         if (limit <= 0)
 810                 return -EBUSY;
 811
 812         return 0;
 813 }
 814
 815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 816 {
 817         static const u32 test_pat[4][6] = {
 818         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 819         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 820         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 821         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 822         };
 823         int chan;
 824
 825         for (chan = 0; chan < 4; chan++) {
 826                 int i;
 827
 828                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 829                              (chan * 0x2000) | 0x0200);
 830                 tg3_writephy(tp, 0x16, 0x0002);
 831
 832                 for (i = 0; i < 6; i++)
 833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 834                                      test_pat[chan][i]);
 835
 836                 tg3_writephy(tp, 0x16, 0x0202);
 837                 if (tg3_wait_macro_done(tp)) {
 838                         *resetp = 1;
 839                         return -EBUSY;
 840                 }
 841
 842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 843                              (chan * 0x2000) | 0x0200);
 844                 tg3_writephy(tp, 0x16, 0x0082);
 845                 if (tg3_wait_macro_done(tp)) {
 846                         *resetp = 1;
 847                         return -EBUSY;
 848                 }
 849
 850                 tg3_writephy(tp, 0x16, 0x0802);
 851                 if (tg3_wait_macro_done(tp)) {
 852                         *resetp = 1;
 853                         return -EBUSY;
 854                 }
 855
 856                 for (i = 0; i < 6; i += 2) {
 857                         u32 low, high;
 858
 859                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 860                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 861                             tg3_wait_macro_done(tp)) {
 862                                 *resetp = 1;
 863                                 return -EBUSY;
 864                         }
 865                         low &= 0x7fff;
 866                         high &= 0x000f;
 867                         if (low != test_pat[chan][i] ||
 868                             high != test_pat[chan][i+1]) {
 869                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 870                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 871                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 872
 873                                 return -EBUSY;
 874                         }
 875                 }
 876         }
 877
 878         return 0;
 879 }
 880
 881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 882 {
 883         int chan;
 884
 885         for (chan = 0; chan < 4; chan++) {
 886                 int i;
 887
 888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 889                              (chan * 0x2000) | 0x0200);
 890                 tg3_writephy(tp, 0x16, 0x0002);
 891                 for (i = 0; i < 6; i++)
 892                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 893                 tg3_writephy(tp, 0x16, 0x0202);
 894                 if (tg3_wait_macro_done(tp))
 895                         return -EBUSY;
 896         }
 897
 898         return 0;
 899 }
 900
 901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 902 {
 903         u32 reg32, phy9_orig;
 904         int retries, do_phy_reset, err;
 905
 906         retries = 10;
 907         do_phy_reset = 1;
 908         do {
 909                 if (do_phy_reset) {
 910                         err = tg3_bmcr_reset(tp);
 911                         if (err)
 912                                 return err;
 913                         do_phy_reset = 0;
 914                 }
 915
 916                 /* Disable transmitter and interrupt.  */
 917                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 918                         continue;
 919
 920                 reg32 |= 0x3000;
 921                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 922
 923                 /* Set full-duplex, 1000 mbps.  */
 924                 tg3_writephy(tp, MII_BMCR,
 925                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 926
 927                 /* Set to master mode.  */
 928                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 929                         continue;
 930
 931                 tg3_writephy(tp, MII_TG3_CTRL,
 932                              (MII_TG3_CTRL_AS_MASTER |
 933                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 934
 935                 /* Enable SM_DSP_CLOCK and 6dB.  */
 936                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 937
 938                 /* Block the PHY control access.  */
 939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 941
 942                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 943                 if (!err)
 944                         break;
 945         } while (--retries);
 946
 947         err = tg3_phy_reset_chanpat(tp);
 948         if (err)
 949                 return err;
 950
 951         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 952         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 953
 954         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 955         tg3_writephy(tp, 0x16, 0x0000);
 956
 957         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 958             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 959                 /* Set Extended packet length bit for jumbo frames */
 960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 961         }
 962         else {
 963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 964         }
 965
 966         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 967
 968         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 969                 reg32 &= ~0x3000;
 970                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 971         } else if (!err)
 972                 err = -EBUSY;
 973
 974         return err;
 975 }
 976
 977 static void tg3_link_report(struct tg3 *);
 978
 979 /* This will reset the tigon3 PHY if there is no valid
 980  * link unless the FORCE argument is non-zero.
 981  */
 982 static int tg3_phy_reset(struct tg3 *tp)
 983 {
 984         u32 phy_status;
 985         int err;
 986
 987         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 988         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 989         if (err != 0)
 990                 return -EBUSY;
 991
 992         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 993                 netif_carrier_off(tp->dev);
 994                 tg3_link_report(tp);
 995         }
 996
 997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1000                 err = tg3_phy_reset_5703_4_5(tp);
1001                 if (err)
1002                         return err;
1003                 goto out;
1004         }
1005
1006         err = tg3_bmcr_reset(tp);
1007         if (err)
1008                 return err;
1009
1010 out:
1011         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1014                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1015                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1016                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1017                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1018         }
1019         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1020                 tg3_writephy(tp, 0x1c, 0x8d68);
1021                 tg3_writephy(tp, 0x1c, 0x8d68);
1022         }
1023         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1024                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1025                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1026                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1027                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1028                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1029                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1030                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1031                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1032         }
1033         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1034                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1035                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1036                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1037                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1038         }
1039         /* Set Extended packet length bit (bit 14) on all chips that */
1040         /* support jumbo frames */
1041         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1042                 /* Cannot do read-modify-write on 5401 */
1043                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1044         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1045                 u32 phy_reg;
1046
1047                 /* Set bit 14 with read-modify-write to preserve other bits */
1048                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1049                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1050                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1051         }
1052
1053         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1054          * jumbo frames transmission.
1055          */
1056         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1057                 u32 phy_reg;
1058
1059                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1060                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1061                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1062         }
1063
1064         tg3_phy_set_wirespeed(tp);
1065         return 0;
1066 }
1067
1068 static void tg3_frob_aux_power(struct tg3 *tp)
1069 {
1070         struct tg3 *tp_peer = tp;
1071
1072         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1073                 return;
1074
1075         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1076             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1077                 struct net_device *dev_peer;
1078
1079                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1080                 /* remove_one() may have been run on the peer. */
1081                 if (!dev_peer)
1082                         tp_peer = tp;
1083                 else
1084                         tp_peer = netdev_priv(dev_peer);
1085         }
1086
1087         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1088             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1089             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1090             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1091                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1092                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1093                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1094                                     (GRC_LCLCTRL_GPIO_OE0 |
1095                                      GRC_LCLCTRL_GPIO_OE1 |
1096                                      GRC_LCLCTRL_GPIO_OE2 |
1097                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1098                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1099                                     100);
1100                 } else {
1101                         u32 no_gpio2;
1102                         u32 grc_local_ctrl = 0;
1103
1104                         if (tp_peer != tp &&
1105                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1106                                 return;
1107
1108                         /* Workaround to prevent overdrawing Amps. */
1109                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1110                             ASIC_REV_5714) {
1111                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1112                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1113                                             grc_local_ctrl, 100);
1114                         }
1115
1116                         /* On 5753 and variants, GPIO2 cannot be used. */
1117                         no_gpio2 = tp->nic_sram_data_cfg &
1118                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1119
1120                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1121                                          GRC_LCLCTRL_GPIO_OE1 |
1122                                          GRC_LCLCTRL_GPIO_OE2 |
1123                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1124                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1125                         if (no_gpio2) {
1126                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1127                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1128                         }
1129                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1130                                                     grc_local_ctrl, 100);
1131
1132                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1133
1134                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1135                                                     grc_local_ctrl, 100);
1136
1137                         if (!no_gpio2) {
1138                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1139                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140                                             grc_local_ctrl, 100);
1141                         }
1142                 }
1143         } else {
1144                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1145                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1146                         if (tp_peer != tp &&
1147                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1148                                 return;
1149
1150                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1151                                     (GRC_LCLCTRL_GPIO_OE1 |
1152                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1153
1154                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1155                                     GRC_LCLCTRL_GPIO_OE1, 100);
1156
1157                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1158                                     (GRC_LCLCTRL_GPIO_OE1 |
1159                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1160                 }
1161         }
1162 }
1163
1164 static int tg3_setup_phy(struct tg3 *, int);
1165
1166 #define RESET_KIND_SHUTDOWN     0
1167 #define RESET_KIND_INIT         1
1168 #define RESET_KIND_SUSPEND      2
1169
1170 static void tg3_write_sig_post_reset(struct tg3 *, int);
1171 static int tg3_halt_cpu(struct tg3 *, u32);
1172 static int tg3_nvram_lock(struct tg3 *);
1173 static void tg3_nvram_unlock(struct tg3 *);
1174
1175 static void tg3_power_down_phy(struct tg3 *tp)
1176 {
1177         /* The PHY should not be powered down on some chips because
1178          * of bugs.
1179          */
1180         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1181             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1182             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1183              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1184                 return;
1185         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1186 }
1187
1188 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1189 {
1190         u32 misc_host_ctrl;
1191         u16 power_control, power_caps;
1192         int pm = tp->pm_cap;
1193
1194         /* Make sure register accesses (indirect or otherwise)
1195          * will function correctly.
1196          */
1197         pci_write_config_dword(tp->pdev,
1198                                TG3PCI_MISC_HOST_CTRL,
1199                                tp->misc_host_ctrl);
1200
1201         pci_read_config_word(tp->pdev,
1202                              pm + PCI_PM_CTRL,
1203                              &power_control);
1204         power_control |= PCI_PM_CTRL_PME_STATUS;
1205         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1206         switch (state) {
1207         case PCI_D0:
1208                 power_control |= 0;
1209                 pci_write_config_word(tp->pdev,
1210                                       pm + PCI_PM_CTRL,
1211                                       power_control);
1212                 udelay(100);    /* Delay after power state change */
1213
1214                 /* Switch out of Vaux if it is not a LOM */
1215                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1216                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1217
1218                 return 0;
1219
1220         case PCI_D1:
1221                 power_control |= 1;
1222                 break;
1223
1224         case PCI_D2:
1225                 power_control |= 2;
1226                 break;
1227
1228         case PCI_D3hot:
1229                 power_control |= 3;
1230                 break;
1231
1232         default:
1233                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1234                        "requested.\n",
1235                        tp->dev->name, state);
1236                 return -EINVAL;
1237         };
1238
1239         power_control |= PCI_PM_CTRL_PME_ENABLE;
1240
1241         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1242         tw32(TG3PCI_MISC_HOST_CTRL,
1243              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1244
1245         if (tp->link_config.phy_is_low_power == 0) {
1246                 tp->link_config.phy_is_low_power = 1;
1247                 tp->link_config.orig_speed = tp->link_config.speed;
1248                 tp->link_config.orig_duplex = tp->link_config.duplex;
1249                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1250         }
1251
1252         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1253                 tp->link_config.speed = SPEED_10;
1254                 tp->link_config.duplex = DUPLEX_HALF;
1255                 tp->link_config.autoneg = AUTONEG_ENABLE;
1256                 tg3_setup_phy(tp, 0);
1257         }
1258
1259         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1260                 int i;
1261                 u32 val;
1262
1263                 for (i = 0; i < 200; i++) {
1264                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1265                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1266                                 break;
1267                         msleep(1);
1268                 }
1269         }
1270         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1271                                              WOL_DRV_STATE_SHUTDOWN |
1272                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1273
1274         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1275
1276         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1277                 u32 mac_mode;
1278
1279                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1280                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1281                         udelay(40);
1282
1283                         mac_mode = MAC_MODE_PORT_MODE_MII;
1284
1285                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1286                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1287                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1288                 } else {
1289                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1290                 }
1291
1292                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1293                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1294
1295                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1296                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1297                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1298
1299                 tw32_f(MAC_MODE, mac_mode);
1300                 udelay(100);
1301
1302                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1303                 udelay(10);
1304         }
1305
1306         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1307             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1308              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1309                 u32 base_val;
1310
1311                 base_val = tp->pci_clock_ctrl;
1312                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1313                              CLOCK_CTRL_TXCLK_DISABLE);
1314
1315                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1316                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1317         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1318                 /* do nothing */
1319         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1320                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1321                 u32 newbits1, newbits2;
1322
1323                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1324                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1325                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1326                                     CLOCK_CTRL_TXCLK_DISABLE |
1327                                     CLOCK_CTRL_ALTCLK);
1328                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1329                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1330                         newbits1 = CLOCK_CTRL_625_CORE;
1331                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1332                 } else {
1333                         newbits1 = CLOCK_CTRL_ALTCLK;
1334                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1335                 }
1336
1337                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1338                             40);
1339
1340                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1341                             40);
1342
1343                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1344                         u32 newbits3;
1345
1346                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1347                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1348                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1349                                             CLOCK_CTRL_TXCLK_DISABLE |
1350                                             CLOCK_CTRL_44MHZ_CORE);
1351                         } else {
1352                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1353                         }
1354
1355                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1356                                     tp->pci_clock_ctrl | newbits3, 40);
1357                 }
1358         }
1359
1360         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1361             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1362                 /* Turn off the PHY */
1363                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1364                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1365                                      MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1366                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1367                         tg3_power_down_phy(tp);
1368                 }
1369         }
1370
1371         tg3_frob_aux_power(tp);
1372
1373         /* Workaround for unstable PLL clock */
1374         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1375             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1376                 u32 val = tr32(0x7d00);
1377
1378                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1379                 tw32(0x7d00, val);
1380                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1381                         int err;
1382
1383                         err = tg3_nvram_lock(tp);
1384                         tg3_halt_cpu(tp, RX_CPU_BASE);
1385                         if (!err)
1386                                 tg3_nvram_unlock(tp);
1387                 }
1388         }
1389
1390         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1391
1392         /* Finally, set the new power state. */
1393         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1394         udelay(100);    /* Delay after power state change */
1395
1396         return 0;
1397 }
1398
1399 static void tg3_link_report(struct tg3 *tp)
1400 {
1401         if (!netif_carrier_ok(tp->dev)) {
1402                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1403         } else {
1404                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1405                        tp->dev->name,
1406                        (tp->link_config.active_speed == SPEED_1000 ?
1407                         1000 :
1408                         (tp->link_config.active_speed == SPEED_100 ?
1409                          100 : 10)),
1410                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1411                         "full" : "half"));
1412
1413                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1414                        "%s for RX.\n",
1415                        tp->dev->name,
1416                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1417                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1418         }
1419 }
1420
1421 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1422 {
1423         u32 new_tg3_flags = 0;
1424         u32 old_rx_mode = tp->rx_mode;
1425         u32 old_tx_mode = tp->tx_mode;
1426
1427         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1428
1429                 /* Convert 1000BaseX flow control bits to 1000BaseT
1430                  * bits before resolving flow control.
1431                  */
1432                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1433                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1434                                        ADVERTISE_PAUSE_ASYM);
1435                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1436
1437                         if (local_adv & ADVERTISE_1000XPAUSE)
1438                                 local_adv |= ADVERTISE_PAUSE_CAP;
1439                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1440                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1441                         if (remote_adv & LPA_1000XPAUSE)
1442                                 remote_adv |= LPA_PAUSE_CAP;
1443                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1444                                 remote_adv |= LPA_PAUSE_ASYM;
1445                 }
1446
1447                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1448                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1449                                 if (remote_adv & LPA_PAUSE_CAP)
1450                                         new_tg3_flags |=
1451                                                 (TG3_FLAG_RX_PAUSE |
1452                                                 TG3_FLAG_TX_PAUSE);
1453                                 else if (remote_adv & LPA_PAUSE_ASYM)
1454                                         new_tg3_flags |=
1455                                                 (TG3_FLAG_RX_PAUSE);
1456                         } else {
1457                                 if (remote_adv & LPA_PAUSE_CAP)
1458                                         new_tg3_flags |=
1459                                                 (TG3_FLAG_RX_PAUSE |
1460                                                 TG3_FLAG_TX_PAUSE);
1461                         }
1462                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1463                         if ((remote_adv & LPA_PAUSE_CAP) &&
1464                         (remote_adv & LPA_PAUSE_ASYM))
1465                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1466                 }
1467
1468                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1469                 tp->tg3_flags |= new_tg3_flags;
1470         } else {
1471                 new_tg3_flags = tp->tg3_flags;
1472         }
1473
1474         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1475                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1476         else
1477                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1478
1479         if (old_rx_mode != tp->rx_mode) {
1480                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1481         }
1482
1483         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1484                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1485         else
1486                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1487
1488         if (old_tx_mode != tp->tx_mode) {
1489                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1490         }
1491 }
1492
1493 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1494 {
1495         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1496         case MII_TG3_AUX_STAT_10HALF:
1497                 *speed = SPEED_10;
1498                 *duplex = DUPLEX_HALF;
1499                 break;
1500
1501         case MII_TG3_AUX_STAT_10FULL:
1502                 *speed = SPEED_10;
1503                 *duplex = DUPLEX_FULL;
1504                 break;
1505
1506         case MII_TG3_AUX_STAT_100HALF:
1507                 *speed = SPEED_100;
1508                 *duplex = DUPLEX_HALF;
1509                 break;
1510
1511         case MII_TG3_AUX_STAT_100FULL:
1512                 *speed = SPEED_100;
1513                 *duplex = DUPLEX_FULL;
1514                 break;
1515
1516         case MII_TG3_AUX_STAT_1000HALF:
1517                 *speed = SPEED_1000;
1518                 *duplex = DUPLEX_HALF;
1519                 break;
1520
1521         case MII_TG3_AUX_STAT_1000FULL:
1522                 *speed = SPEED_1000;
1523                 *duplex = DUPLEX_FULL;
1524                 break;
1525
1526         default:
1527                 *speed = SPEED_INVALID;
1528                 *duplex = DUPLEX_INVALID;
1529                 break;
1530         };
1531 }
1532
1533 static void tg3_phy_copper_begin(struct tg3 *tp)
1534 {
1535         u32 new_adv;
1536         int i;
1537
1538         if (tp->link_config.phy_is_low_power) {
1539                 /* Entering low power mode.  Disable gigabit and
1540                  * 100baseT advertisements.
1541                  */
1542                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1543
1544                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1545                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1546                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1547                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1548
1549                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1550         } else if (tp->link_config.speed == SPEED_INVALID) {
1551                 tp->link_config.advertising =
1552                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1553                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1554                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1555                          ADVERTISED_Autoneg | ADVERTISED_MII);
1556
1557                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1558                         tp->link_config.advertising &=
1559                                 ~(ADVERTISED_1000baseT_Half |
1560                                   ADVERTISED_1000baseT_Full);
1561
1562                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1563                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1564                         new_adv |= ADVERTISE_10HALF;
1565                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1566                         new_adv |= ADVERTISE_10FULL;
1567                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1568                         new_adv |= ADVERTISE_100HALF;
1569                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1570                         new_adv |= ADVERTISE_100FULL;
1571                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1572
1573                 if (tp->link_config.advertising &
1574                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1575                         new_adv = 0;
1576                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1577                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1578                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1579                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1580                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1581                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1582                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1583                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1584                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1585                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1586                 } else {
1587                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1588                 }
1589         } else {
1590                 /* Asking for a specific link mode. */
1591                 if (tp->link_config.speed == SPEED_1000) {
1592                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1593                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1594
1595                         if (tp->link_config.duplex == DUPLEX_FULL)
1596                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1597                         else
1598                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1599                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1600                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1601                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1602                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1603                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1604                 } else {
1605                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1606
1607                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1608                         if (tp->link_config.speed == SPEED_100) {
1609                                 if (tp->link_config.duplex == DUPLEX_FULL)
1610                                         new_adv |= ADVERTISE_100FULL;
1611                                 else
1612                                         new_adv |= ADVERTISE_100HALF;
1613                         } else {
1614                                 if (tp->link_config.duplex == DUPLEX_FULL)
1615                                         new_adv |= ADVERTISE_10FULL;
1616                                 else
1617                                         new_adv |= ADVERTISE_10HALF;
1618                         }
1619                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1620                 }
1621         }
1622
1623         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1624             tp->link_config.speed != SPEED_INVALID) {
1625                 u32 bmcr, orig_bmcr;
1626
1627                 tp->link_config.active_speed = tp->link_config.speed;
1628                 tp->link_config.active_duplex = tp->link_config.duplex;
1629
1630                 bmcr = 0;
1631                 switch (tp->link_config.speed) {
1632                 default:
1633                 case SPEED_10:
1634                         break;
1635
1636                 case SPEED_100:
1637                         bmcr |= BMCR_SPEED100;
1638                         break;
1639
1640                 case SPEED_1000:
1641                         bmcr |= TG3_BMCR_SPEED1000;
1642                         break;
1643                 };
1644
1645                 if (tp->link_config.duplex == DUPLEX_FULL)
1646                         bmcr |= BMCR_FULLDPLX;
1647
1648                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1649                     (bmcr != orig_bmcr)) {
1650                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1651                         for (i = 0; i < 1500; i++) {
1652                                 u32 tmp;
1653
1654                                 udelay(10);
1655                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1656                                     tg3_readphy(tp, MII_BMSR, &tmp))
1657                                         continue;
1658                                 if (!(tmp & BMSR_LSTATUS)) {
1659                                         udelay(40);
1660                                         break;
1661                                 }
1662                         }
1663                         tg3_writephy(tp, MII_BMCR, bmcr);
1664                         udelay(40);
1665                 }
1666         } else {
1667                 tg3_writephy(tp, MII_BMCR,
1668                              BMCR_ANENABLE | BMCR_ANRESTART);
1669         }
1670 }
1671
1672 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1673 {
1674         int err;
1675
1676         /* Turn off tap power management. */
1677         /* Set Extended packet length bit */
1678         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1679
1680         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1681         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1682
1683         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1684         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1685
1686         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1687         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1688
1689         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1690         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1691
1692         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1693         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1694
1695         udelay(40);
1696
1697         return err;
1698 }
1699
1700 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1701 {
1702         u32 adv_reg, all_mask;
1703
1704         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1705                 return 0;
1706
1707         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1708                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1709         if ((adv_reg & all_mask) != all_mask)
1710                 return 0;
1711         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1712                 u32 tg3_ctrl;
1713
1714                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1715                         return 0;
1716
1717                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1718                             MII_TG3_CTRL_ADV_1000_FULL);
1719                 if ((tg3_ctrl & all_mask) != all_mask)
1720                         return 0;
1721         }
1722         return 1;
1723 }
1724
1725 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1726 {
1727         int current_link_up;
1728         u32 bmsr, dummy;
1729         u16 current_speed;
1730         u8 current_duplex;
1731         int i, err;
1732
1733         tw32(MAC_EVENT, 0);
1734
1735         tw32_f(MAC_STATUS,
1736              (MAC_STATUS_SYNC_CHANGED |
1737               MAC_STATUS_CFG_CHANGED |
1738               MAC_STATUS_MI_COMPLETION |
1739               MAC_STATUS_LNKSTATE_CHANGED));
1740         udelay(40);
1741
1742         tp->mi_mode = MAC_MI_MODE_BASE;
1743         tw32_f(MAC_MI_MODE, tp->mi_mode);
1744         udelay(80);
1745
1746         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1747
1748         /* Some third-party PHYs need to be reset on link going
1749          * down.
1750          */
1751         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1752              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1753              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1754             netif_carrier_ok(tp->dev)) {
1755                 tg3_readphy(tp, MII_BMSR, &bmsr);
1756                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1757                     !(bmsr & BMSR_LSTATUS))
1758                         force_reset = 1;
1759         }
1760         if (force_reset)
1761                 tg3_phy_reset(tp);
1762
1763         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1764                 tg3_readphy(tp, MII_BMSR, &bmsr);
1765                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1766                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1767                         bmsr = 0;
1768
1769                 if (!(bmsr & BMSR_LSTATUS)) {
1770                         err = tg3_init_5401phy_dsp(tp);
1771                         if (err)
1772                                 return err;
1773
1774                         tg3_readphy(tp, MII_BMSR, &bmsr);
1775                         for (i = 0; i < 1000; i++) {
1776                                 udelay(10);
1777                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1778                                     (bmsr & BMSR_LSTATUS)) {
1779                                         udelay(40);
1780                                         break;
1781                                 }
1782                         }
1783
1784                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1785                             !(bmsr & BMSR_LSTATUS) &&
1786                             tp->link_config.active_speed == SPEED_1000) {
1787                                 err = tg3_phy_reset(tp);
1788                                 if (!err)
1789                                         err = tg3_init_5401phy_dsp(tp);
1790                                 if (err)
1791                                         return err;
1792                         }
1793                 }
1794         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1795                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1796                 /* 5701 {A0,B0} CRC bug workaround */
1797                 tg3_writephy(tp, 0x15, 0x0a75);
1798                 tg3_writephy(tp, 0x1c, 0x8c68);
1799                 tg3_writephy(tp, 0x1c, 0x8d68);
1800                 tg3_writephy(tp, 0x1c, 0x8c68);
1801         }
1802
1803         /* Clear pending interrupts... */
1804         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1805         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1806
1807         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1808                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1809         else
1810                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1811
1812         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1813             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1814                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1815                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1816                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1817                 else
1818                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1819         }
1820
1821         current_link_up = 0;
1822         current_speed = SPEED_INVALID;
1823         current_duplex = DUPLEX_INVALID;
1824
1825         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1826                 u32 val;
1827
1828                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1829                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1830                 if (!(val & (1 << 10))) {
1831                         val |= (1 << 10);
1832                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1833                         goto relink;
1834                 }
1835         }
1836
1837         bmsr = 0;
1838         for (i = 0; i < 100; i++) {
1839                 tg3_readphy(tp, MII_BMSR, &bmsr);
1840                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1841                     (bmsr & BMSR_LSTATUS))
1842                         break;
1843                 udelay(40);
1844         }
1845
1846         if (bmsr & BMSR_LSTATUS) {
1847                 u32 aux_stat, bmcr;
1848
1849                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1850                 for (i = 0; i < 2000; i++) {
1851                         udelay(10);
1852                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1853                             aux_stat)
1854                                 break;
1855                 }
1856
1857                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1858                                              &current_speed,
1859                                              &current_duplex);
1860
1861                 bmcr = 0;
1862                 for (i = 0; i < 200; i++) {
1863                         tg3_readphy(tp, MII_BMCR, &bmcr);
1864                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1865                                 continue;
1866                         if (bmcr && bmcr != 0x7fff)
1867                                 break;
1868                         udelay(10);
1869                 }
1870
1871                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1872                         if (bmcr & BMCR_ANENABLE) {
1873                                 current_link_up = 1;
1874
1875                                 /* Force autoneg restart if we are exiting
1876                                  * low power mode.
1877                                  */
1878                                 if (!tg3_copper_is_advertising_all(tp))
1879                                         current_link_up = 0;
1880                         } else {
1881                                 current_link_up = 0;
1882                         }
1883                 } else {
1884                         if (!(bmcr & BMCR_ANENABLE) &&
1885                             tp->link_config.speed == current_speed &&
1886                             tp->link_config.duplex == current_duplex) {
1887                                 current_link_up = 1;
1888                         } else {
1889                                 current_link_up = 0;
1890                         }
1891                 }
1892
1893                 tp->link_config.active_speed = current_speed;
1894                 tp->link_config.active_duplex = current_duplex;
1895         }
1896
1897         if (current_link_up == 1 &&
1898             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1899             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1900                 u32 local_adv, remote_adv;
1901
1902                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1903                         local_adv = 0;
1904                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1905
1906                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1907                         remote_adv = 0;
1908
1909                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1910
1911                 /* If we are not advertising full pause capability,
1912                  * something is wrong.  Bring the link down and reconfigure.
1913                  */
1914                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1915                         current_link_up = 0;
1916                 } else {
1917                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1918                 }
1919         }
1920 relink:
1921         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1922                 u32 tmp;
1923
1924                 tg3_phy_copper_begin(tp);
1925
1926                 tg3_readphy(tp, MII_BMSR, &tmp);
1927                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1928                     (tmp & BMSR_LSTATUS))
1929                         current_link_up = 1;
1930         }
1931
1932         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1933         if (current_link_up == 1) {
1934                 if (tp->link_config.active_speed == SPEED_100 ||
1935                     tp->link_config.active_speed == SPEED_10)
1936                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1937                 else
1938                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1939         } else
1940                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1941
1942         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1943         if (tp->link_config.active_duplex == DUPLEX_HALF)
1944                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1945
1946         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1947         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1948                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1949                     (current_link_up == 1 &&
1950                      tp->link_config.active_speed == SPEED_10))
1951                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1952         } else {
1953                 if (current_link_up == 1)
1954                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1955         }
1956
1957         /* ??? Without this setting Netgear GA302T PHY does not
1958          * ??? send/receive packets...
1959          */
1960         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1961             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1962                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1963                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1964                 udelay(80);
1965         }
1966
1967         tw32_f(MAC_MODE, tp->mac_mode);
1968         udelay(40);
1969
1970         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1971                 /* Polled via timer. */
1972                 tw32_f(MAC_EVENT, 0);
1973         } else {
1974                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1975         }
1976         udelay(40);
1977
1978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1979             current_link_up == 1 &&
1980             tp->link_config.active_speed == SPEED_1000 &&
1981             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1982              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1983                 udelay(120);
1984                 tw32_f(MAC_STATUS,
1985                      (MAC_STATUS_SYNC_CHANGED |
1986                       MAC_STATUS_CFG_CHANGED));
1987                 udelay(40);
1988                 tg3_write_mem(tp,
1989                               NIC_SRAM_FIRMWARE_MBOX,
1990                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1991         }
1992
1993         if (current_link_up != netif_carrier_ok(tp->dev)) {
1994                 if (current_link_up)
1995                         netif_carrier_on(tp->dev);
1996                 else
1997                         netif_carrier_off(tp->dev);
1998                 tg3_link_report(tp);
1999         }
2000
2001         return 0;
2002 }
2003
2004 struct tg3_fiber_aneginfo {
2005         int state;
2006 #define ANEG_STATE_UNKNOWN              0
2007 #define ANEG_STATE_AN_ENABLE            1
2008 #define ANEG_STATE_RESTART_INIT         2
2009 #define ANEG_STATE_RESTART              3
2010 #define ANEG_STATE_DISABLE_LINK_OK      4
2011 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2012 #define ANEG_STATE_ABILITY_DETECT       6
2013 #define ANEG_STATE_ACK_DETECT_INIT      7
2014 #define ANEG_STATE_ACK_DETECT           8
2015 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2016 #define ANEG_STATE_COMPLETE_ACK         10
2017 #define ANEG_STATE_IDLE_DETECT_INIT     11
2018 #define ANEG_STATE_IDLE_DETECT          12
2019 #define ANEG_STATE_LINK_OK              13
2020 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2021 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2022
2023         u32 flags;
2024 #define MR_AN_ENABLE            0x00000001
2025 #define MR_RESTART_AN           0x00000002
2026 #define MR_AN_COMPLETE          0x00000004
2027 #define MR_PAGE_RX              0x00000008
2028 #define MR_NP_LOADED            0x00000010
2029 #define MR_TOGGLE_TX            0x00000020
2030 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2031 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2032 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2033 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2034 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2035 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2036 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2037 #define MR_TOGGLE_RX            0x00002000
2038 #define MR_NP_RX                0x00004000
2039
2040 #define MR_LINK_OK              0x80000000
2041
2042         unsigned long link_time, cur_time;
2043
2044         u32 ability_match_cfg;
2045         int ability_match_count;
2046
2047         char ability_match, idle_match, ack_match;
2048
2049         u32 txconfig, rxconfig;
2050 #define ANEG_CFG_NP             0x00000080
2051 #define ANEG_CFG_ACK            0x00000040
2052 #define ANEG_CFG_RF2            0x00000020
2053 #define ANEG_CFG_RF1            0x00000010
2054 #define ANEG_CFG_PS2            0x00000001
2055 #define ANEG_CFG_PS1            0x00008000
2056 #define ANEG_CFG_HD             0x00004000
2057 #define ANEG_CFG_FD             0x00002000
2058 #define ANEG_CFG_INVAL          0x00001f06
2059
2060 };
2061 #define ANEG_OK         0
2062 #define ANEG_DONE       1
2063 #define ANEG_TIMER_ENAB 2
2064 #define ANEG_FAILED     -1
2065
2066 #define ANEG_STATE_SETTLE_TIME  10000
2067
2068 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2069                                    struct tg3_fiber_aneginfo *ap)
2070 {
2071         unsigned long delta;
2072         u32 rx_cfg_reg;
2073         int ret;
2074
2075         if (ap->state == ANEG_STATE_UNKNOWN) {
2076                 ap->rxconfig = 0;
2077                 ap->link_time = 0;
2078                 ap->cur_time = 0;
2079                 ap->ability_match_cfg = 0;
2080                 ap->ability_match_count = 0;
2081                 ap->ability_match = 0;
2082                 ap->idle_match = 0;
2083                 ap->ack_match = 0;
2084         }
2085         ap->cur_time++;
2086
2087         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2088                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2089
2090                 if (rx_cfg_reg != ap->ability_match_cfg) {
2091                         ap->ability_match_cfg = rx_cfg_reg;
2092                         ap->ability_match = 0;
2093                         ap->ability_match_count = 0;
2094                 } else {
2095                         if (++ap->ability_match_count > 1) {
2096                                 ap->ability_match = 1;
2097                                 ap->ability_match_cfg = rx_cfg_reg;
2098                         }
2099                 }
2100                 if (rx_cfg_reg & ANEG_CFG_ACK)
2101                         ap->ack_match = 1;
2102                 else
2103                         ap->ack_match = 0;
2104
2105                 ap->idle_match = 0;
2106         } else {
2107                 ap->idle_match = 1;
2108                 ap->ability_match_cfg = 0;
2109                 ap->ability_match_count = 0;
2110                 ap->ability_match = 0;
2111                 ap->ack_match = 0;
2112
2113                 rx_cfg_reg = 0;
2114         }
2115
2116         ap->rxconfig = rx_cfg_reg;
2117         ret = ANEG_OK;
2118
2119         switch(ap->state) {
2120         case ANEG_STATE_UNKNOWN:
2121                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2122                         ap->state = ANEG_STATE_AN_ENABLE;
2123
2124                 /* fallthru */
2125         case ANEG_STATE_AN_ENABLE:
2126                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2127                 if (ap->flags & MR_AN_ENABLE) {
2128                         ap->link_time = 0;
2129                         ap->cur_time = 0;
2130                         ap->ability_match_cfg = 0;
2131                         ap->ability_match_count = 0;
2132                         ap->ability_match = 0;
2133                         ap->idle_match = 0;
2134                         ap->ack_match = 0;
2135
2136                         ap->state = ANEG_STATE_RESTART_INIT;
2137                 } else {
2138                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2139                 }
2140                 break;
2141
2142         case ANEG_STATE_RESTART_INIT:
2143                 ap->link_time = ap->cur_time;
2144                 ap->flags &= ~(MR_NP_LOADED);
2145                 ap->txconfig = 0;
2146                 tw32(MAC_TX_AUTO_NEG, 0);
2147                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2148                 tw32_f(MAC_MODE, tp->mac_mode);
2149                 udelay(40);
2150
2151                 ret = ANEG_TIMER_ENAB;
2152                 ap->state = ANEG_STATE_RESTART;
2153
2154                 /* fallthru */
2155         case ANEG_STATE_RESTART:
2156                 delta = ap->cur_time - ap->link_time;
2157                 if (delta > ANEG_STATE_SETTLE_TIME) {
2158                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2159                 } else {
2160                         ret = ANEG_TIMER_ENAB;
2161                 }
2162                 break;
2163
2164         case ANEG_STATE_DISABLE_LINK_OK:
2165                 ret = ANEG_DONE;
2166                 break;
2167
2168         case ANEG_STATE_ABILITY_DETECT_INIT:
2169                 ap->flags &= ~(MR_TOGGLE_TX);
2170                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2171                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2172                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2173                 tw32_f(MAC_MODE, tp->mac_mode);
2174                 udelay(40);
2175
2176                 ap->state = ANEG_STATE_ABILITY_DETECT;
2177                 break;
2178
2179         case ANEG_STATE_ABILITY_DETECT:
2180                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2181                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2182                 }
2183                 break;
2184
2185         case ANEG_STATE_ACK_DETECT_INIT:
2186                 ap->txconfig |= ANEG_CFG_ACK;
2187                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2188                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2189                 tw32_f(MAC_MODE, tp->mac_mode);
2190                 udelay(40);
2191
2192                 ap->state = ANEG_STATE_ACK_DETECT;
2193
2194                 /* fallthru */
2195         case ANEG_STATE_ACK_DETECT:
2196                 if (ap->ack_match != 0) {
2197                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2198                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2199                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2200                         } else {
2201                                 ap->state = ANEG_STATE_AN_ENABLE;
2202                         }
2203                 } else if (ap->ability_match != 0 &&
2204                            ap->rxconfig == 0) {
2205                         ap->state = ANEG_STATE_AN_ENABLE;
2206                 }
2207                 break;
2208
2209         case ANEG_STATE_COMPLETE_ACK_INIT:
2210                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2211                         ret = ANEG_FAILED;
2212                         break;
2213                 }
2214                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2215                                MR_LP_ADV_HALF_DUPLEX |
2216                                MR_LP_ADV_SYM_PAUSE |
2217                                MR_LP_ADV_ASYM_PAUSE |
2218                                MR_LP_ADV_REMOTE_FAULT1 |
2219                                MR_LP_ADV_REMOTE_FAULT2 |
2220                                MR_LP_ADV_NEXT_PAGE |
2221                                MR_TOGGLE_RX |
2222                                MR_NP_RX);
2223                 if (ap->rxconfig & ANEG_CFG_FD)
2224                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2225                 if (ap->rxconfig & ANEG_CFG_HD)
2226                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2227                 if (ap->rxconfig & ANEG_CFG_PS1)
2228                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2229                 if (ap->rxconfig & ANEG_CFG_PS2)
2230                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2231                 if (ap->rxconfig & ANEG_CFG_RF1)
2232                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2233                 if (ap->rxconfig & ANEG_CFG_RF2)
2234                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2235                 if (ap->rxconfig & ANEG_CFG_NP)
2236                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2237
2238                 ap->link_time = ap->cur_time;
2239
2240                 ap->flags ^= (MR_TOGGLE_TX);
2241                 if (ap->rxconfig & 0x0008)
2242                         ap->flags |= MR_TOGGLE_RX;
2243                 if (ap->rxconfig & ANEG_CFG_NP)
2244                         ap->flags |= MR_NP_RX;
2245                 ap->flags |= MR_PAGE_RX;
2246
2247                 ap->state = ANEG_STATE_COMPLETE_ACK;
2248                 ret = ANEG_TIMER_ENAB;
2249                 break;
2250
2251         case ANEG_STATE_COMPLETE_ACK:
2252                 if (ap->ability_match != 0 &&
2253                     ap->rxconfig == 0) {
2254                         ap->state = ANEG_STATE_AN_ENABLE;
2255                         break;
2256                 }
2257                 delta = ap->cur_time - ap->link_time;
2258                 if (delta > ANEG_STATE_SETTLE_TIME) {
2259                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2260                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2261                         } else {
2262                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2263                                     !(ap->flags & MR_NP_RX)) {
2264                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2265                                 } else {
2266                                         ret = ANEG_FAILED;
2267                                 }
2268                         }
2269                 }
2270                 break;
2271
2272         case ANEG_STATE_IDLE_DETECT_INIT:
2273                 ap->link_time = ap->cur_time;
2274                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2275                 tw32_f(MAC_MODE, tp->mac_mode);
2276                 udelay(40);
2277
2278                 ap->state = ANEG_STATE_IDLE_DETECT;
2279                 ret = ANEG_TIMER_ENAB;
2280                 break;
2281
2282         case ANEG_STATE_IDLE_DETECT:
2283                 if (ap->ability_match != 0 &&
2284                     ap->rxconfig == 0) {
2285                         ap->state = ANEG_STATE_AN_ENABLE;
2286                         break;
2287                 }
2288                 delta = ap->cur_time - ap->link_time;
2289                 if (delta > ANEG_STATE_SETTLE_TIME) {
2290                         /* XXX another gem from the Broadcom driver :( */
2291                         ap->state = ANEG_STATE_LINK_OK;
2292                 }
2293                 break;
2294
2295         case ANEG_STATE_LINK_OK:
2296                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2297                 ret = ANEG_DONE;
2298                 break;
2299
2300         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2301                 /* ??? unimplemented */
2302                 break;
2303
2304         case ANEG_STATE_NEXT_PAGE_WAIT:
2305                 /* ??? unimplemented */
2306                 break;
2307
2308         default:
2309                 ret = ANEG_FAILED;
2310                 break;
2311         };
2312
2313         return ret;
2314 }
2315
2316 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2317 {
2318         int res = 0;
2319         struct tg3_fiber_aneginfo aninfo;
2320         int status = ANEG_FAILED;
2321         unsigned int tick;
2322         u32 tmp;
2323
2324         tw32_f(MAC_TX_AUTO_NEG, 0);
2325
2326         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2327         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2328         udelay(40);
2329
2330         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2331         udelay(40);
2332
2333         memset(&aninfo, 0, sizeof(aninfo));
2334         aninfo.flags |= MR_AN_ENABLE;
2335         aninfo.state = ANEG_STATE_UNKNOWN;
2336         aninfo.cur_time = 0;
2337         tick = 0;
2338         while (++tick < 195000) {
2339                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2340                 if (status == ANEG_DONE || status == ANEG_FAILED)
2341                         break;
2342
2343                 udelay(1);
2344         }
2345
2346         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2347         tw32_f(MAC_MODE, tp->mac_mode);
2348         udelay(40);
2349
2350         *flags = aninfo.flags;
2351
2352         if (status == ANEG_DONE &&
2353             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2354                              MR_LP_ADV_FULL_DUPLEX)))
2355                 res = 1;
2356
2357         return res;
2358 }
2359
2360 static void tg3_init_bcm8002(struct tg3 *tp)
2361 {
2362         u32 mac_status = tr32(MAC_STATUS);
2363         int i;
2364
2365         /* Reset when initting first time or we have a link. */
2366         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2367             !(mac_status & MAC_STATUS_PCS_SYNCED))
2368                 return;
2369
2370         /* Set PLL lock range. */
2371         tg3_writephy(tp, 0x16, 0x8007);
2372
2373         /* SW reset */
2374         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2375
2376         /* Wait for reset to complete. */
2377         /* XXX schedule_timeout() ... */
2378         for (i = 0; i < 500; i++)
2379                 udelay(10);
2380
2381         /* Config mode; select PMA/Ch 1 regs. */
2382         tg3_writephy(tp, 0x10, 0x8411);
2383
2384         /* Enable auto-lock and comdet, select txclk for tx. */
2385         tg3_writephy(tp, 0x11, 0x0a10);
2386
2387         tg3_writephy(tp, 0x18, 0x00a0);
2388         tg3_writephy(tp, 0x16, 0x41ff);
2389
2390         /* Assert and deassert POR. */
2391         tg3_writephy(tp, 0x13, 0x0400);
2392         udelay(40);
2393         tg3_writephy(tp, 0x13, 0x0000);
2394
2395         tg3_writephy(tp, 0x11, 0x0a50);
2396         udelay(40);
2397         tg3_writephy(tp, 0x11, 0x0a10);
2398
2399         /* Wait for signal to stabilize */
2400         /* XXX schedule_timeout() ... */
2401         for (i = 0; i < 15000; i++)
2402                 udelay(10);
2403
2404         /* Deselect the channel register so we can read the PHYID
2405          * later.
2406          */
2407         tg3_writephy(tp, 0x10, 0x8011);
2408 }
2409
2410 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2411 {
2412         u32 sg_dig_ctrl, sg_dig_status;
2413         u32 serdes_cfg, expected_sg_dig_ctrl;
2414         int workaround, port_a;
2415         int current_link_up;
2416
2417         serdes_cfg = 0;
2418         expected_sg_dig_ctrl = 0;
2419         workaround = 0;
2420         port_a = 1;
2421         current_link_up = 0;
2422
2423         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2424             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2425                 workaround = 1;
2426                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2427                         port_a = 0;
2428
2429                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2430                 /* preserve bits 20-23 for voltage regulator */
2431                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2432         }
2433
2434         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2435
2436         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2437                 if (sg_dig_ctrl & (1 << 31)) {
2438                         if (workaround) {
2439                                 u32 val = serdes_cfg;
2440
2441                                 if (port_a)
2442                                         val |= 0xc010000;
2443                                 else
2444                                         val |= 0x4010000;
2445                                 tw32_f(MAC_SERDES_CFG, val);
2446                         }
2447                         tw32_f(SG_DIG_CTRL, 0x01388400);
2448                 }
2449                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2450                         tg3_setup_flow_control(tp, 0, 0);
2451                         current_link_up = 1;
2452                 }
2453                 goto out;
2454         }
2455
2456         /* Want auto-negotiation.  */
2457         expected_sg_dig_ctrl = 0x81388400;
2458
2459         /* Pause capability */
2460         expected_sg_dig_ctrl |= (1 << 11);
2461
2462         /* Asymettric pause */
2463         expected_sg_dig_ctrl |= (1 << 12);
2464
2465         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2466                 if (workaround)
2467                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2468                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2469                 udelay(5);
2470                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2471
2472                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2473         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2474                                  MAC_STATUS_SIGNAL_DET)) {
2475                 int i;
2476
2477                 /* Giver time to negotiate (~200ms) */
2478                 for (i = 0; i < 40000; i++) {
2479                         sg_dig_status = tr32(SG_DIG_STATUS);
2480                         if (sg_dig_status & (0x3))
2481                                 break;
2482                         udelay(5);
2483                 }
2484                 mac_status = tr32(MAC_STATUS);
2485
2486                 if ((sg_dig_status & (1 << 1)) &&
2487                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2488                         u32 local_adv, remote_adv;
2489
2490                         local_adv = ADVERTISE_PAUSE_CAP;
2491                         remote_adv = 0;
2492                         if (sg_dig_status & (1 << 19))
2493                                 remote_adv |= LPA_PAUSE_CAP;
2494                         if (sg_dig_status & (1 << 20))
2495                                 remote_adv |= LPA_PAUSE_ASYM;
2496
2497                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2498                         current_link_up = 1;
2499                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2500                 } else if (!(sg_dig_status & (1 << 1))) {
2501                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2502                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2503                         else {
2504                                 if (workaround) {
2505                                         u32 val = serdes_cfg;
2506
2507                                         if (port_a)
2508                                                 val |= 0xc010000;
2509                                         else
2510                                                 val |= 0x4010000;
2511
2512                                         tw32_f(MAC_SERDES_CFG, val);
2513                                 }
2514
2515                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2516                                 udelay(40);
2517
2518                                 /* Link parallel detection - link is up */
2519                                 /* only if we have PCS_SYNC and not */
2520                                 /* receiving config code words */
2521                                 mac_status = tr32(MAC_STATUS);
2522                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2523                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2524                                         tg3_setup_flow_control(tp, 0, 0);
2525                                         current_link_up = 1;
2526                                 }
2527                         }
2528                 }
2529         }
2530
2531 out:
2532         return current_link_up;
2533 }
2534
2535 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2536 {
2537         int current_link_up = 0;
2538
2539         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2540                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2541                 goto out;
2542         }
2543
2544         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2545                 u32 flags;
2546                 int i;
2547
2548                 if (fiber_autoneg(tp, &flags)) {
2549                         u32 local_adv, remote_adv;
2550
2551                         local_adv = ADVERTISE_PAUSE_CAP;
2552                         remote_adv = 0;
2553                         if (flags & MR_LP_ADV_SYM_PAUSE)
2554                                 remote_adv |= LPA_PAUSE_CAP;
2555                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2556                                 remote_adv |= LPA_PAUSE_ASYM;
2557
2558                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2559
2560                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2561                         current_link_up = 1;
2562                 }
2563                 for (i = 0; i < 30; i++) {
2564                         udelay(20);
2565                         tw32_f(MAC_STATUS,
2566                                (MAC_STATUS_SYNC_CHANGED |
2567                                 MAC_STATUS_CFG_CHANGED));
2568                         udelay(40);
2569                         if ((tr32(MAC_STATUS) &
2570                              (MAC_STATUS_SYNC_CHANGED |
2571                               MAC_STATUS_CFG_CHANGED)) == 0)
2572                                 break;
2573                 }
2574
2575                 mac_status = tr32(MAC_STATUS);
2576                 if (current_link_up == 0 &&
2577                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2578                     !(mac_status & MAC_STATUS_RCVD_CFG))
2579                         current_link_up = 1;
2580         } else {
2581                 /* Forcing 1000FD link up. */
2582                 current_link_up = 1;
2583                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2584
2585                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2586                 udelay(40);
2587         }
2588
2589 out:
2590         return current_link_up;
2591 }
2592
2593 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2594 {
2595         u32 orig_pause_cfg;
2596         u16 orig_active_speed;
2597         u8 orig_active_duplex;
2598         u32 mac_status;
2599         int current_link_up;
2600         int i;
2601
2602         orig_pause_cfg =
2603                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2604                                   TG3_FLAG_TX_PAUSE));
2605         orig_active_speed = tp->link_config.active_speed;
2606         orig_active_duplex = tp->link_config.active_duplex;
2607
2608         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2609             netif_carrier_ok(tp->dev) &&
2610             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2611                 mac_status = tr32(MAC_STATUS);
2612                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2613                                MAC_STATUS_SIGNAL_DET |
2614                                MAC_STATUS_CFG_CHANGED |
2615                                MAC_STATUS_RCVD_CFG);
2616                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2617                                    MAC_STATUS_SIGNAL_DET)) {
2618                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2619                                             MAC_STATUS_CFG_CHANGED));
2620                         return 0;
2621                 }
2622         }
2623
2624         tw32_f(MAC_TX_AUTO_NEG, 0);
2625
2626         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2627         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2628         tw32_f(MAC_MODE, tp->mac_mode);
2629         udelay(40);
2630
2631         if (tp->phy_id == PHY_ID_BCM8002)
2632                 tg3_init_bcm8002(tp);
2633
2634         /* Enable link change event even when serdes polling.  */
2635         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2636         udelay(40);
2637
2638         current_link_up = 0;
2639         mac_status = tr32(MAC_STATUS);
2640
2641         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2642                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2643         else
2644                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2645
2646         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2647         tw32_f(MAC_MODE, tp->mac_mode);
2648         udelay(40);
2649
2650         tp->hw_status->status =
2651                 (SD_STATUS_UPDATED |
2652                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2653
2654         for (i = 0; i < 100; i++) {
2655                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2656                                     MAC_STATUS_CFG_CHANGED));
2657                 udelay(5);
2658                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2659                                          MAC_STATUS_CFG_CHANGED)) == 0)
2660                         break;
2661         }
2662
2663         mac_status = tr32(MAC_STATUS);
2664         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2665                 current_link_up = 0;
2666                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2667                         tw32_f(MAC_MODE, (tp->mac_mode |
2668                                           MAC_MODE_SEND_CONFIGS));
2669                         udelay(1);
2670                         tw32_f(MAC_MODE, tp->mac_mode);
2671                 }
2672         }
2673
2674         if (current_link_up == 1) {
2675                 tp->link_config.active_speed = SPEED_1000;
2676                 tp->link_config.active_duplex = DUPLEX_FULL;
2677                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2678                                     LED_CTRL_LNKLED_OVERRIDE |
2679                                     LED_CTRL_1000MBPS_ON));
2680         } else {
2681                 tp->link_config.active_speed = SPEED_INVALID;
2682                 tp->link_config.active_duplex = DUPLEX_INVALID;
2683                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2684                                     LED_CTRL_LNKLED_OVERRIDE |
2685                                     LED_CTRL_TRAFFIC_OVERRIDE));
2686         }
2687
2688         if (current_link_up != netif_carrier_ok(tp->dev)) {
2689                 if (current_link_up)
2690                         netif_carrier_on(tp->dev);
2691                 else
2692                         netif_carrier_off(tp->dev);
2693                 tg3_link_report(tp);
2694         } else {
2695                 u32 now_pause_cfg =
2696                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2697                                          TG3_FLAG_TX_PAUSE);
2698                 if (orig_pause_cfg != now_pause_cfg ||
2699                     orig_active_speed != tp->link_config.active_speed ||
2700                     orig_active_duplex != tp->link_config.active_duplex)
2701                         tg3_link_report(tp);
2702         }
2703
2704         return 0;
2705 }
2706
2707 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2708 {
2709         int current_link_up, err = 0;
2710         u32 bmsr, bmcr;
2711         u16 current_speed;
2712         u8 current_duplex;
2713
2714         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2715         tw32_f(MAC_MODE, tp->mac_mode);
2716         udelay(40);
2717
2718         tw32(MAC_EVENT, 0);
2719
2720         tw32_f(MAC_STATUS,
2721              (MAC_STATUS_SYNC_CHANGED |
2722               MAC_STATUS_CFG_CHANGED |
2723               MAC_STATUS_MI_COMPLETION |
2724               MAC_STATUS_LNKSTATE_CHANGED));
2725         udelay(40);
2726
2727         if (force_reset)
2728                 tg3_phy_reset(tp);
2729
2730         current_link_up = 0;
2731         current_speed = SPEED_INVALID;
2732         current_duplex = DUPLEX_INVALID;
2733
2734         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2735         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2736         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2737                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2738                         bmsr |= BMSR_LSTATUS;
2739                 else
2740                         bmsr &= ~BMSR_LSTATUS;
2741         }
2742
2743         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2744
2745         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2746             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2747                 /* do nothing, just check for link up at the end */
2748         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2749                 u32 adv, new_adv;
2750
2751                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2752                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2753                                   ADVERTISE_1000XPAUSE |
2754                                   ADVERTISE_1000XPSE_ASYM |
2755                                   ADVERTISE_SLCT);
2756
2757                 /* Always advertise symmetric PAUSE just like copper */
2758                 new_adv |= ADVERTISE_1000XPAUSE;
2759
2760                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2761                         new_adv |= ADVERTISE_1000XHALF;
2762                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2763                         new_adv |= ADVERTISE_1000XFULL;
2764
2765                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2766                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2767                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2768                         tg3_writephy(tp, MII_BMCR, bmcr);
2769
2770                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2771                         tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2772                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2773
2774                         return err;
2775                 }
2776         } else {
2777                 u32 new_bmcr;
2778
2779                 bmcr &= ~BMCR_SPEED1000;
2780                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2781
2782                 if (tp->link_config.duplex == DUPLEX_FULL)
2783                         new_bmcr |= BMCR_FULLDPLX;
2784
2785                 if (new_bmcr != bmcr) {
2786                         /* BMCR_SPEED1000 is a reserved bit that needs
2787                          * to be set on write.
2788                          */
2789                         new_bmcr |= BMCR_SPEED1000;
2790
2791                         /* Force a linkdown */
2792                         if (netif_carrier_ok(tp->dev)) {
2793                                 u32 adv;
2794
2795                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2796                                 adv &= ~(ADVERTISE_1000XFULL |
2797                                          ADVERTISE_1000XHALF |
2798                                          ADVERTISE_SLCT);
2799                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2800                                 tg3_writephy(tp, MII_BMCR, bmcr |
2801                                                            BMCR_ANRESTART |
2802                                                            BMCR_ANENABLE);
2803                                 udelay(10);
2804                                 netif_carrier_off(tp->dev);
2805                         }
2806                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2807                         bmcr = new_bmcr;
2808                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2809                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2810                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2811                             ASIC_REV_5714) {
2812                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2813                                         bmsr |= BMSR_LSTATUS;
2814                                 else
2815                                         bmsr &= ~BMSR_LSTATUS;
2816                         }
2817                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2818                 }
2819         }
2820
2821         if (bmsr & BMSR_LSTATUS) {
2822                 current_speed = SPEED_1000;
2823                 current_link_up = 1;
2824                 if (bmcr & BMCR_FULLDPLX)
2825                         current_duplex = DUPLEX_FULL;
2826                 else
2827                         current_duplex = DUPLEX_HALF;
2828
2829                 if (bmcr & BMCR_ANENABLE) {
2830                         u32 local_adv, remote_adv, common;
2831
2832                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2833                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2834                         common = local_adv & remote_adv;
2835                         if (common & (ADVERTISE_1000XHALF |
2836                                       ADVERTISE_1000XFULL)) {
2837                                 if (common & ADVERTISE_1000XFULL)
2838                                         current_duplex = DUPLEX_FULL;
2839                                 else
2840                                         current_duplex = DUPLEX_HALF;
2841
2842                                 tg3_setup_flow_control(tp, local_adv,
2843                                                        remote_adv);
2844                         }
2845                         else
2846                                 current_link_up = 0;
2847                 }
2848         }
2849
2850         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2851         if (tp->link_config.active_duplex == DUPLEX_HALF)
2852                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2853
2854         tw32_f(MAC_MODE, tp->mac_mode);
2855         udelay(40);
2856
2857         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2858
2859         tp->link_config.active_speed = current_speed;
2860         tp->link_config.active_duplex = current_duplex;
2861
2862         if (current_link_up != netif_carrier_ok(tp->dev)) {
2863                 if (current_link_up)
2864                         netif_carrier_on(tp->dev);
2865                 else {
2866                         netif_carrier_off(tp->dev);
2867                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2868                 }
2869                 tg3_link_report(tp);
2870         }
2871         return err;
2872 }
2873
2874 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2875 {
2876         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2877                 /* Give autoneg time to complete. */
2878                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2879                 return;
2880         }
2881         if (!netif_carrier_ok(tp->dev) &&
2882             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2883                 u32 bmcr;
2884
2885                 tg3_readphy(tp, MII_BMCR, &bmcr);
2886                 if (bmcr & BMCR_ANENABLE) {
2887                         u32 phy1, phy2;
2888
2889                         /* Select shadow register 0x1f */
2890                         tg3_writephy(tp, 0x1c, 0x7c00);
2891                         tg3_readphy(tp, 0x1c, &phy1);
2892
2893                         /* Select expansion interrupt status register */
2894                         tg3_writephy(tp, 0x17, 0x0f01);
2895                         tg3_readphy(tp, 0x15, &phy2);
2896                         tg3_readphy(tp, 0x15, &phy2);
2897
2898                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2899                                 /* We have signal detect and not receiving
2900                                  * config code words, link is up by parallel
2901                                  * detection.
2902                                  */
2903
2904                                 bmcr &= ~BMCR_ANENABLE;
2905                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2906                                 tg3_writephy(tp, MII_BMCR, bmcr);
2907                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2908                         }
2909                 }
2910         }
2911         else if (netif_carrier_ok(tp->dev) &&
2912                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2913                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2914                 u32 phy2;
2915
2916                 /* Select expansion interrupt status register */
2917                 tg3_writephy(tp, 0x17, 0x0f01);
2918                 tg3_readphy(tp, 0x15, &phy2);
2919                 if (phy2 & 0x20) {
2920                         u32 bmcr;
2921
2922                         /* Config code words received, turn on autoneg. */
2923                         tg3_readphy(tp, MII_BMCR, &bmcr);
2924                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2925
2926                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2927
2928                 }
2929         }
2930 }
2931
2932 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2933 {
2934         int err;
2935
2936         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2937                 err = tg3_setup_fiber_phy(tp, force_reset);
2938         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2939                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2940         } else {
2941                 err = tg3_setup_copper_phy(tp, force_reset);
2942         }
2943
2944         if (tp->link_config.active_speed == SPEED_1000 &&
2945             tp->link_config.active_duplex == DUPLEX_HALF)
2946                 tw32(MAC_TX_LENGTHS,
2947                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2948                       (6 << TX_LENGTHS_IPG_SHIFT) |
2949                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2950         else
2951                 tw32(MAC_TX_LENGTHS,
2952                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2953                       (6 << TX_LENGTHS_IPG_SHIFT) |
2954                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2955
2956         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2957                 if (netif_carrier_ok(tp->dev)) {
2958                         tw32(HOSTCC_STAT_COAL_TICKS,
2959                              tp->coal.stats_block_coalesce_usecs);
2960                 } else {
2961                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2962                 }
2963         }
2964
2965         return err;
2966 }
2967
2968 /* Tigon3 never reports partial packet sends.  So we do not
2969  * need special logic to handle SKBs that have not had all
2970  * of their frags sent yet, like SunGEM does.
2971  */
2972 static void tg3_tx(struct tg3 *tp)
2973 {
2974         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2975         u32 sw_idx = tp->tx_cons;
2976
2977         while (sw_idx != hw_idx) {
2978                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2979                 struct sk_buff *skb = ri->skb;
2980                 int i;
2981
2982                 BUG_ON(skb == NULL);
2983                 pci_unmap_single(tp->pdev,
2984                                  pci_unmap_addr(ri, mapping),
2985                                  skb_headlen(skb),
2986                                  PCI_DMA_TODEVICE);
2987
2988                 ri->skb = NULL;
2989
2990                 sw_idx = NEXT_TX(sw_idx);
2991
2992                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2993                         BUG_ON(sw_idx == hw_idx);
2994
2995                         ri = &tp->tx_buffers[sw_idx];
2996                         BUG_ON(ri->skb != NULL);
2997
2998                         pci_unmap_page(tp->pdev,
2999                                        pci_unmap_addr(ri, mapping),
3000                                        skb_shinfo(skb)->frags[i].size,
3001                                        PCI_DMA_TODEVICE);
3002
3003                         sw_idx = NEXT_TX(sw_idx);
3004                 }
3005
3006                 dev_kfree_skb(skb);
3007         }
3008
3009         tp->tx_cons = sw_idx;
3010
3011         if (unlikely(netif_queue_stopped(tp->dev))) {
3012                 spin_lock(&tp->tx_lock);
3013                 if (netif_queue_stopped(tp->dev) &&
3014                     (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
3015                         netif_wake_queue(tp->dev);
3016                 spin_unlock(&tp->tx_lock);
3017         }
3018 }
3019
3020 /* Returns size of skb allocated or < 0 on error.
3021  *
3022  * We only need to fill in the address because the other members
3023  * of the RX descriptor are invariant, see tg3_init_rings.
3024  *
3025  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3026  * posting buffers we only dirty the first cache line of the RX
3027  * descriptor (containing the address).  Whereas for the RX status
3028  * buffers the cpu only reads the last cacheline of the RX descriptor
3029  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3030  */
3031 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3032                             int src_idx, u32 dest_idx_unmasked)
3033 {
3034         struct tg3_rx_buffer_desc *desc;
3035         struct ring_info *map, *src_map;
3036         struct sk_buff *skb;
3037         dma_addr_t mapping;
3038         int skb_size, dest_idx;
3039
3040         src_map = NULL;
3041         switch (opaque_key) {
3042         case RXD_OPAQUE_RING_STD:
3043                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3044                 desc = &tp->rx_std[dest_idx];
3045                 map = &tp->rx_std_buffers[dest_idx];
3046                 if (src_idx >= 0)
3047                         src_map = &tp->rx_std_buffers[src_idx];
3048                 skb_size = tp->rx_pkt_buf_sz;
3049                 break;
3050
3051         case RXD_OPAQUE_RING_JUMBO:
3052                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3053                 desc = &tp->rx_jumbo[dest_idx];
3054                 map = &tp->rx_jumbo_buffers[dest_idx];
3055                 if (src_idx >= 0)
3056                         src_map = &tp->rx_jumbo_buffers[src_idx];
3057                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3058                 break;
3059
3060         default:
3061                 return -EINVAL;
3062         };
3063
3064         /* Do not overwrite any of the map or rp information
3065          * until we are sure we can commit to a new buffer.
3066          *
3067          * Callers depend upon this behavior and assume that
3068          * we leave everything unchanged if we fail.
3069          */
3070         skb = dev_alloc_skb(skb_size);
3071         if (skb == NULL)
3072                 return -ENOMEM;
3073
3074         skb->dev = tp->dev;
3075         skb_reserve(skb, tp->rx_offset);
3076
3077         mapping = pci_map_single(tp->pdev, skb->data,
3078                                  skb_size - tp->rx_offset,
3079                                  PCI_DMA_FROMDEVICE);
3080
3081         map->skb = skb;
3082         pci_unmap_addr_set(map, mapping, mapping);
3083
3084         if (src_map != NULL)
3085                 src_map->skb = NULL;
3086
3087         desc->addr_hi = ((u64)mapping >> 32);
3088         desc->addr_lo = ((u64)mapping & 0xffffffff);
3089
3090         return skb_size;
3091 }
3092
3093 /* We only need to move over in the address because the other
3094  * members of the RX descriptor are invariant.  See notes above
3095  * tg3_alloc_rx_skb for full details.
3096  */
3097 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3098                            int src_idx, u32 dest_idx_unmasked)
3099 {
3100         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3101         struct ring_info *src_map, *dest_map;
3102         int dest_idx;
3103
3104         switch (opaque_key) {
3105         case RXD_OPAQUE_RING_STD:
3106                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3107                 dest_desc = &tp->rx_std[dest_idx];
3108                 dest_map = &tp->rx_std_buffers[dest_idx];
3109                 src_desc = &tp->rx_std[src_idx];
3110                 src_map = &tp->rx_std_buffers[src_idx];
3111                 break;
3112
3113         case RXD_OPAQUE_RING_JUMBO:
3114                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3115                 dest_desc = &tp->rx_jumbo[dest_idx];
3116                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3117                 src_desc = &tp->rx_jumbo[src_idx];
3118                 src_map = &tp->rx_jumbo_buffers[src_idx];
3119                 break;
3120
3121         default:
3122                 return;
3123         };
3124
3125         dest_map->skb = src_map->skb;
3126         pci_unmap_addr_set(dest_map, mapping,
3127                            pci_unmap_addr(src_map, mapping));
3128         dest_desc->addr_hi = src_desc->addr_hi;
3129         dest_desc->addr_lo = src_desc->addr_lo;
3130
3131         src_map->skb = NULL;
3132 }
3133
3134 #if TG3_VLAN_TAG_USED
3135 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3136 {
3137         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3138 }
3139 #endif
3140
3141 /* The RX ring scheme is composed of multiple rings which post fresh
3142  * buffers to the chip, and one special ring the chip uses to report
3143  * status back to the host.
3144  *
3145  * The special ring reports the status of received packets to the
3146  * host.  The chip does not write into the original descriptor the
3147  * RX buffer was obtained from.  The chip simply takes the original
3148  * descriptor as provided by the host, updates the status and length
3149  * field, then writes this into the next status ring entry.
3150  *
3151  * Each ring the host uses to post buffers to the chip is described
3152  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3153  * it is first placed into the on-chip ram.  When the packet's length
3154  * is known, it walks down the TG3_BDINFO entries to select the ring.
3155  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3156  * which is within the range of the new packet's length is chosen.
3157  *
3158  * The "separate ring for rx status" scheme may sound queer, but it makes
3159  * sense from a cache coherency perspective.  If only the host writes
3160  * to the buffer post rings, and only the chip writes to the rx status
3161  * rings, then cache lines never move beyond shared-modified state.
3162  * If both the host and chip were to write into the same ring, cache line
3163  * eviction could occur since both entities want it in an exclusive state.
3164  */
3165 static int tg3_rx(struct tg3 *tp, int budget)
3166 {
3167         u32 work_mask;
3168         u32 sw_idx = tp->rx_rcb_ptr;
3169         u16 hw_idx;
3170         int received;
3171
3172         hw_idx = tp->hw_status->idx[0].rx_producer;
3173         /*
3174          * We need to order the read of hw_idx and the read of
3175          * the opaque cookie.
3176          */
3177         rmb();
3178         work_mask = 0;
3179         received = 0;
3180         while (sw_idx != hw_idx && budget > 0) {
3181                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3182                 unsigned int len;
3183                 struct sk_buff *skb;
3184                 dma_addr_t dma_addr;
3185                 u32 opaque_key, desc_idx, *post_ptr;
3186
3187                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3188                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3189                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3190                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3191                                                   mapping);
3192                         skb = tp->rx_std_buffers[desc_idx].skb;
3193                         post_ptr = &tp->rx_std_ptr;
3194                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3195                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3196                                                   mapping);
3197                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3198                         post_ptr = &tp->rx_jumbo_ptr;
3199                 }
3200                 else {
3201                         goto next_pkt_nopost;
3202                 }
3203
3204                 work_mask |= opaque_key;
3205
3206                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3207                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3208                 drop_it:
3209                         tg3_recycle_rx(tp, opaque_key,
3210                                        desc_idx, *post_ptr);
3211                 drop_it_no_recycle:
3212                         /* Other statistics kept track of by card. */
3213                         tp->net_stats.rx_dropped++;
3214                         goto next_pkt;
3215                 }
3216
3217                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3218
3219                 if (len > RX_COPY_THRESHOLD
3220                         && tp->rx_offset == 2
3221                         /* rx_offset != 2 iff this is a 5701 card running
3222                          * in PCI-X mode [see tg3_get_invariants()] */
3223                 ) {
3224                         int skb_size;
3225
3226                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3227                                                     desc_idx, *post_ptr);
3228                         if (skb_size < 0)
3229                                 goto drop_it;
3230
3231                         pci_unmap_single(tp->pdev, dma_addr,
3232                                          skb_size - tp->rx_offset,
3233                                          PCI_DMA_FROMDEVICE);
3234
3235                         skb_put(skb, len);
3236                 } else {
3237                         struct sk_buff *copy_skb;
3238
3239                         tg3_recycle_rx(tp, opaque_key,
3240                                        desc_idx, *post_ptr);
3241
3242                         copy_skb = dev_alloc_skb(len + 2);
3243                         if (copy_skb == NULL)
3244                                 goto drop_it_no_recycle;
3245
3246                         copy_skb->dev = tp->dev;
3247                         skb_reserve(copy_skb, 2);
3248                         skb_put(copy_skb, len);
3249                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3250                         memcpy(copy_skb->data, skb->data, len);
3251                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3252
3253                         /* We'll reuse the original ring buffer. */
3254                         skb = copy_skb;
3255                 }
3256
3257                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3258                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3259                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3260                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3261                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3262                 else
3263                         skb->ip_summed = CHECKSUM_NONE;
3264
3265                 skb->protocol = eth_type_trans(skb, tp->dev);
3266 #if TG3_VLAN_TAG_USED
3267                 if (tp->vlgrp != NULL &&
3268                     desc->type_flags & RXD_FLAG_VLAN) {
3269                         tg3_vlan_rx(tp, skb,
3270                                     desc->err_vlan & RXD_VLAN_MASK);
3271                 } else
3272 #endif
3273                         netif_receive_skb(skb);
3274
3275                 tp->dev->last_rx = jiffies;
3276                 received++;
3277                 budget--;
3278
3279 next_pkt:
3280                 (*post_ptr)++;
3281 next_pkt_nopost:
3282                 sw_idx++;
3283                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3284
3285                 /* Refresh hw_idx to see if there is new work */
3286                 if (sw_idx == hw_idx) {
3287                         hw_idx = tp->hw_status->idx[0].rx_producer;
3288                         rmb();
3289                 }
3290         }
3291
3292         /* ACK the status ring. */
3293         tp->rx_rcb_ptr = sw_idx;
3294         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3295
3296         /* Refill RX ring(s). */
3297         if (work_mask & RXD_OPAQUE_RING_STD) {
3298                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3299                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3300                              sw_idx);
3301         }
3302         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3303                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3304                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3305                              sw_idx);
3306         }
3307         mmiowb();
3308
3309         return received;
3310 }
3311
3312 static int tg3_poll(struct net_device *netdev, int *budget)
3313 {
3314         struct tg3 *tp = netdev_priv(netdev);
3315         struct tg3_hw_status *sblk = tp->hw_status;
3316         int done;
3317
3318         /* handle link change and other phy events */
3319         if (!(tp->tg3_flags &
3320               (TG3_FLAG_USE_LINKCHG_REG |
3321                TG3_FLAG_POLL_SERDES))) {
3322                 if (sblk->status & SD_STATUS_LINK_CHG) {
3323                         sblk->status = SD_STATUS_UPDATED |
3324                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3325                         spin_lock(&tp->lock);
3326                         tg3_setup_phy(tp, 0);
3327                         spin_unlock(&tp->lock);
3328                 }
3329         }
3330
3331         /* run TX completion thread */
3332         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3333                 tg3_tx(tp);
3334         }
3335
3336         /* run RX thread, within the bounds set by NAPI.
3337          * All RX "locking" is done by ensuring outside
3338          * code synchronizes with dev->poll()
3339          */
3340         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3341                 int orig_budget = *budget;
3342                 int work_done;
3343
3344                 if (orig_budget > netdev->quota)
3345                         orig_budget = netdev->quota;
3346
3347                 work_done = tg3_rx(tp, orig_budget);
3348
3349                 *budget -= work_done;
3350                 netdev->quota -= work_done;
3351         }
3352
3353         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3354                 tp->last_tag = sblk->status_tag;
3355                 rmb();
3356         } else
3357                 sblk->status &= ~SD_STATUS_UPDATED;
3358
3359         /* if no more work, tell net stack and NIC we're done */
3360         done = !tg3_has_work(tp);
3361         if (done) {
3362                 netif_rx_complete(netdev);
3363                 tg3_restart_ints(tp);
3364         }
3365
3366         return (done ? 0 : 1);
3367 }
3368
3369 static void tg3_irq_quiesce(struct tg3 *tp)
3370 {
3371         BUG_ON(tp->irq_sync);
3372
3373         tp->irq_sync = 1;
3374         smp_mb();
3375
3376         synchronize_irq(tp->pdev->irq);
3377 }
3378
3379 static inline int tg3_irq_sync(struct tg3 *tp)
3380 {
3381         return tp->irq_sync;
3382 }
3383
3384 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3385  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3386  * with as well.  Most of the time, this is not necessary except when
3387  * shutting down the device.
3388  */
3389 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3390 {
3391         if (irq_sync)
3392                 tg3_irq_quiesce(tp);
3393         spin_lock_bh(&tp->lock);
3394         spin_lock(&tp->tx_lock);
3395 }
3396
3397 static inline void tg3_full_unlock(struct tg3 *tp)
3398 {
3399         spin_unlock(&tp->tx_lock);
3400         spin_unlock_bh(&tp->lock);
3401 }
3402
3403 /* One-shot MSI handler - Chip automatically disables interrupt
3404  * after sending MSI so driver doesn't have to do it.
3405  */
3406 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
3407 {
3408         struct net_device *dev = dev_id;
3409         struct tg3 *tp = netdev_priv(dev);
3410
3411         prefetch(tp->hw_status);
3412         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3413
3414         if (likely(!tg3_irq_sync(tp)))
3415                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3416
3417         return IRQ_HANDLED;
3418 }
3419
3420 /* MSI ISR - No need to check for interrupt sharing and no need to
3421  * flush status block and interrupt mailbox. PCI ordering rules
3422  * guarantee that MSI will arrive after the status block.
3423  */
3424 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3425 {
3426         struct net_device *dev = dev_id;
3427         struct tg3 *tp = netdev_priv(dev);
3428
3429         prefetch(tp->hw_status);
3430         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3431         /*
3432          * Writing any value to intr-mbox-0 clears PCI INTA# and
3433          * chip-internal interrupt pending events.
3434          * Writing non-zero to intr-mbox-0 additional tells the
3435          * NIC to stop sending us irqs, engaging "in-intr-handler"
3436          * event coalescing.
3437          */
3438         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3439         if (likely(!tg3_irq_sync(tp)))
3440                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3441
3442         return IRQ_RETVAL(1);
3443 }
3444
3445 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3446 {
3447         struct net_device *dev = dev_id;
3448         struct tg3 *tp = netdev_priv(dev);
3449         struct tg3_hw_status *sblk = tp->hw_status;
3450         unsigned int handled = 1;
3451
3452         /* In INTx mode, it is possible for the interrupt to arrive at
3453          * the CPU before the status block posted prior to the interrupt.
3454          * Reading the PCI State register will confirm whether the
3455          * interrupt is ours and will flush the status block.
3456          */
3457         if ((sblk->status & SD_STATUS_UPDATED) ||
3458             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3459                 /*
3460                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3461                  * chip-internal interrupt pending events.
3462                  * Writing non-zero to intr-mbox-0 additional tells the
3463                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3464                  * event coalescing.
3465                  */
3466                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3467                              0x00000001);
3468                 if (tg3_irq_sync(tp))
3469                         goto out;
3470                 sblk->status &= ~SD_STATUS_UPDATED;
3471                 if (likely(tg3_has_work(tp))) {
3472                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3473                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3474                 } else {
3475                         /* No work, shared interrupt perhaps?  re-enable
3476                          * interrupts, and flush that PCI write
3477                          */
3478                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3479                                 0x00000000);
3480                 }
3481         } else {        /* shared interrupt */
3482                 handled = 0;
3483         }
3484 out:
3485         return IRQ_RETVAL(handled);
3486 }
3487
3488 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3489 {
3490         struct net_device *dev = dev_id;
3491         struct tg3 *tp = netdev_priv(dev);
3492         struct tg3_hw_status *sblk = tp->hw_status;
3493         unsigned int handled = 1;
3494
3495         /* In INTx mode, it is possible for the interrupt to arrive at
3496          * the CPU before the status block posted prior to the interrupt.
3497          * Reading the PCI State register will confirm whether the
3498          * interrupt is ours and will flush the status block.
3499          */
3500         if ((sblk->status_tag != tp->last_tag) ||
3501             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3502                 /*
3503                  * writing any value to intr-mbox-0 clears PCI INTA# and
3504                  * chip-internal interrupt pending events.
3505                  * writing non-zero to intr-mbox-0 additional tells the
3506                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3507                  * event coalescing.
3508                  */
3509                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3510                              0x00000001);
3511                 if (tg3_irq_sync(tp))
3512                         goto out;
3513                 if (netif_rx_schedule_prep(dev)) {
3514                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3515                         /* Update last_tag to mark that this status has been
3516                          * seen. Because interrupt may be shared, we may be
3517                          * racing with tg3_poll(), so only update last_tag
3518                          * if tg3_poll() is not scheduled.
3519                          */
3520                         tp->last_tag = sblk->status_tag;
3521                         __netif_rx_schedule(dev);
3522                 }
3523         } else {        /* shared interrupt */
3524                 handled = 0;
3525         }
3526 out:
3527         return IRQ_RETVAL(handled);
3528 }
3529
3530 /* ISR for interrupt test */
3531 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3532                 struct pt_regs *regs)
3533 {
3534         struct net_device *dev = dev_id;
3535         struct tg3 *tp = netdev_priv(dev);
3536         struct tg3_hw_status *sblk = tp->hw_status;
3537
3538         if ((sblk->status & SD_STATUS_UPDATED) ||
3539             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3540                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3541                              0x00000001);
3542                 return IRQ_RETVAL(1);
3543         }
3544         return IRQ_RETVAL(0);
3545 }
3546
3547 static int tg3_init_hw(struct tg3 *);
3548 static int tg3_halt(struct tg3 *, int, int);
3549
3550 #ifdef CONFIG_NET_POLL_CONTROLLER
3551 static void tg3_poll_controller(struct net_device *dev)
3552 {
3553         struct tg3 *tp = netdev_priv(dev);
3554
3555         tg3_interrupt(tp->pdev->irq, dev, NULL);
3556 }
3557 #endif
3558
3559 static void tg3_reset_task(void *_data)
3560 {
3561         struct tg3 *tp = _data;
3562         unsigned int restart_timer;
3563
3564         tg3_full_lock(tp, 0);
3565         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3566
3567         if (!netif_running(tp->dev)) {
3568                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3569                 tg3_full_unlock(tp);
3570                 return;
3571         }
3572
3573         tg3_full_unlock(tp);
3574
3575         tg3_netif_stop(tp);
3576
3577         tg3_full_lock(tp, 1);
3578
3579         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3580         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3581
3582         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3583         tg3_init_hw(tp);
3584
3585         tg3_netif_start(tp);
3586
3587         if (restart_timer)
3588                 mod_timer(&tp->timer, jiffies + 1);
3589
3590         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3591
3592         tg3_full_unlock(tp);
3593 }
3594
3595 static void tg3_tx_timeout(struct net_device *dev)
3596 {
3597         struct tg3 *tp = netdev_priv(dev);
3598
3599         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3600                dev->name);
3601
3602         schedule_work(&tp->reset_task);
3603 }
3604
3605 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3606 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3607 {
3608         u32 base = (u32) mapping & 0xffffffff;
3609
3610         return ((base > 0xffffdcc0) &&
3611                 (base + len + 8 < base));
3612 }
3613
3614 /* Test for DMA addresses > 40-bit */
3615 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3616                                           int len)
3617 {
3618 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3619         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3620                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3621         return 0;
3622 #else
3623         return 0;
3624 #endif
3625 }
3626
3627 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3628
3629 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3630 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3631                                        u32 last_plus_one, u32 *start,
3632                                        u32 base_flags, u32 mss)
3633 {
3634         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3635         dma_addr_t new_addr = 0;
3636         u32 entry = *start;
3637         int i, ret = 0;
3638
3639         if (!new_skb) {
3640                 ret = -1;
3641         } else {
3642                 /* New SKB is guaranteed to be linear. */
3643                 entry = *start;
3644                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3645                                           PCI_DMA_TODEVICE);
3646                 /* Make sure new skb does not cross any 4G boundaries.
3647                  * Drop the packet if it does.
3648                  */
3649                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3650                         ret = -1;
3651                         dev_kfree_skb(new_skb);
3652                         new_skb = NULL;
3653                 } else {
3654                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3655                                     base_flags, 1 | (mss << 1));
3656                         *start = NEXT_TX(entry);
3657                 }
3658         }
3659
3660         /* Now clean up the sw ring entries. */
3661         i = 0;
3662         while (entry != last_plus_one) {
3663                 int len;
3664
3665                 if (i == 0)
3666                         len = skb_headlen(skb);
3667                 else
3668                         len = skb_shinfo(skb)->frags[i-1].size;
3669                 pci_unmap_single(tp->pdev,
3670                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3671                                  len, PCI_DMA_TODEVICE);
3672                 if (i == 0) {
3673                         tp->tx_buffers[entry].skb = new_skb;
3674                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3675                 } else {
3676                         tp->tx_buffers[entry].skb = NULL;
3677                 }
3678                 entry = NEXT_TX(entry);
3679                 i++;
3680         }
3681
3682         dev_kfree_skb(skb);
3683
3684         return ret;
3685 }
3686
3687 static void tg3_set_txd(struct tg3 *tp, int entry,
3688                         dma_addr_t mapping, int len, u32 flags,
3689                         u32 mss_and_is_end)
3690 {
3691         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3692         int is_end = (mss_and_is_end & 0x1);
3693         u32 mss = (mss_and_is_end >> 1);
3694         u32 vlan_tag = 0;
3695
3696         if (is_end)
3697                 flags |= TXD_FLAG_END;
3698         if (flags & TXD_FLAG_VLAN) {
3699                 vlan_tag = flags >> 16;
3700                 flags &= 0xffff;
3701         }
3702         vlan_tag |= (mss << TXD_MSS_SHIFT);
3703
3704         txd->addr_hi = ((u64) mapping >> 32);
3705         txd->addr_lo = ((u64) mapping & 0xffffffff);
3706         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3707         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3708 }
3709
3710 /* hard_start_xmit for devices that don't have any bugs and
3711  * support TG3_FLG2_HW_TSO_2 only.
3712  */
3713 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3714 {
3715         struct tg3 *tp = netdev_priv(dev);
3716         dma_addr_t mapping;
3717         u32 len, entry, base_flags, mss;
3718
3719         len = skb_headlen(skb);
3720
3721         /* No BH disabling for tx_lock here.  We are running in BH disabled
3722          * context and TX reclaim runs via tp->poll inside of a software
3723          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3724          * no IRQ context deadlocks to worry about either.  Rejoice!
3725          */
3726         if (!spin_trylock(&tp->tx_lock))
3727                 return NETDEV_TX_LOCKED;
3728
3729         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3730                 if (!netif_queue_stopped(dev)) {
3731                         netif_stop_queue(dev);
3732
3733                         /* This is a hard error, log it. */
3734                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3735                                "queue awake!\n", dev->name);
3736                 }
3737                 spin_unlock(&tp->tx_lock);
3738                 return NETDEV_TX_BUSY;
3739         }
3740
3741         entry = tp->tx_prod;
3742         base_flags = 0;
3743 #if TG3_TSO_SUPPORT != 0
3744         mss = 0;
3745         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3746             (mss = skb_shinfo(skb)->tso_size) != 0) {
3747                 int tcp_opt_len, ip_tcp_len;
3748
3749                 if (skb_header_cloned(skb) &&
3750                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3751                         dev_kfree_skb(skb);
3752                         goto out_unlock;
3753                 }
3754
3755                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3756                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3757
3758                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3759                                TXD_FLAG_CPU_POST_DMA);
3760
3761                 skb->nh.iph->check = 0;
3762                 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3763
3764                 skb->h.th->check = 0;
3765
3766                 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3767         }
3768         else if (skb->ip_summed == CHECKSUM_HW)
3769                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3770 #else
3771         mss = 0;
3772         if (skb->ip_summed == CHECKSUM_HW)
3773                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3774 #endif
3775 #if TG3_VLAN_TAG_USED
3776         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3777                 base_flags |= (TXD_FLAG_VLAN |
3778                                (vlan_tx_tag_get(skb) << 16));
3779 #endif
3780
3781         /* Queue skb data, a.k.a. the main skb fragment. */
3782         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3783
3784         tp->tx_buffers[entry].skb = skb;
3785         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3786
3787         tg3_set_txd(tp, entry, mapping, len, base_flags,
3788                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3789
3790         entry = NEXT_TX(entry);
3791
3792         /* Now loop through additional data fragments, and queue them. */
3793         if (skb_shinfo(skb)->nr_frags > 0) {
3794                 unsigned int i, last;
3795
3796                 last = skb_shinfo(skb)->nr_frags - 1;
3797                 for (i = 0; i <= last; i++) {
3798                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3799
3800                         len = frag->size;
3801                         mapping = pci_map_page(tp->pdev,
3802                                                frag->page,
3803                                                frag->page_offset,
3804                                                len, PCI_DMA_TODEVICE);
3805
3806                         tp->tx_buffers[entry].skb = NULL;
3807                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3808
3809                         tg3_set_txd(tp, entry, mapping, len,
3810                                     base_flags, (i == last) | (mss << 1));
3811
3812                         entry = NEXT_TX(entry);
3813                 }
3814         }
3815
3816         /* Packets are ready, update Tx producer idx local and on card. */
3817         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3818
3819         tp->tx_prod = entry;
3820         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
3821                 netif_stop_queue(dev);
3822                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3823                         netif_wake_queue(tp->dev);
3824         }
3825
3826 out_unlock:
3827         mmiowb();
3828         spin_unlock(&tp->tx_lock);
3829
3830         dev->trans_start = jiffies;
3831
3832         return NETDEV_TX_OK;
3833 }
3834
3835 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3836  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3837  */
3838 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3839 {
3840         struct tg3 *tp = netdev_priv(dev);
3841         dma_addr_t mapping;
3842         u32 len, entry, base_flags, mss;
3843         int would_hit_hwbug;
3844
3845         len = skb_headlen(skb);
3846
3847         /* No BH disabling for tx_lock here.  We are running in BH disabled
3848          * context and TX reclaim runs via tp->poll inside of a software
3849          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3850          * no IRQ context deadlocks to worry about either.  Rejoice!
3851          */
3852         if (!spin_trylock(&tp->tx_lock))
3853                 return NETDEV_TX_LOCKED;
3854
3855         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3856                 if (!netif_queue_stopped(dev)) {
3857                         netif_stop_queue(dev);
3858
3859                         /* This is a hard error, log it. */
3860                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3861                                "queue awake!\n", dev->name);
3862                 }
3863                 spin_unlock(&tp->tx_lock);
3864                 return NETDEV_TX_BUSY;
3865         }
3866
3867         entry = tp->tx_prod;
3868         base_flags = 0;
3869         if (skb->ip_summed == CHECKSUM_HW)
3870                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3871 #if TG3_TSO_SUPPORT != 0
3872         mss = 0;
3873         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3874             (mss = skb_shinfo(skb)->tso_size) != 0) {
3875                 int tcp_opt_len, ip_tcp_len;
3876
3877                 if (skb_header_cloned(skb) &&
3878                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3879                         dev_kfree_skb(skb);
3880                         goto out_unlock;
3881                 }
3882
3883                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3884                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3885
3886                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3887                                TXD_FLAG_CPU_POST_DMA);
3888
3889                 skb->nh.iph->check = 0;
3890                 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3891                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3892                         skb->h.th->check = 0;
3893                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3894                 }
3895                 else {
3896                         skb->h.th->check =
3897                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3898                                                    skb->nh.iph->daddr,
3899                                                    0, IPPROTO_TCP, 0);
3900                 }
3901
3902                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3903                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3904                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3905                                 int tsflags;
3906
3907                                 tsflags = ((skb->nh.iph->ihl - 5) +
3908                                            (tcp_opt_len >> 2));
3909                                 mss |= (tsflags << 11);
3910                         }
3911                 } else {
3912                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3913                                 int tsflags;
3914
3915                                 tsflags = ((skb->nh.iph->ihl - 5) +
3916                                            (tcp_opt_len >> 2));
3917                                 base_flags |= tsflags << 12;
3918                         }
3919                 }
3920         }
3921 #else
3922         mss = 0;
3923 #endif
3924 #if TG3_VLAN_TAG_USED
3925         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3926                 base_flags |= (TXD_FLAG_VLAN |
3927                                (vlan_tx_tag_get(skb) << 16));
3928 #endif
3929
3930         /* Queue skb data, a.k.a. the main skb fragment. */
3931         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3932
3933         tp->tx_buffers[entry].skb = skb;
3934         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3935
3936         would_hit_hwbug = 0;
3937
3938         if (tg3_4g_overflow_test(mapping, len))
3939                 would_hit_hwbug = 1;
3940
3941         tg3_set_txd(tp, entry, mapping, len, base_flags,
3942                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3943
3944         entry = NEXT_TX(entry);
3945
3946         /* Now loop through additional data fragments, and queue them. */
3947         if (skb_shinfo(skb)->nr_frags > 0) {
3948                 unsigned int i, last;
3949
3950                 last = skb_shinfo(skb)->nr_frags - 1;
3951                 for (i = 0; i <= last; i++) {
3952                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3953
3954                         len = frag->size;
3955                         mapping = pci_map_page(tp->pdev,
3956                                                frag->page,
3957                                                frag->page_offset,
3958                                                len, PCI_DMA_TODEVICE);
3959
3960                         tp->tx_buffers[entry].skb = NULL;
3961                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3962
3963                         if (tg3_4g_overflow_test(mapping, len))
3964                                 would_hit_hwbug = 1;
3965
3966                         if (tg3_40bit_overflow_test(tp, mapping, len))
3967                                 would_hit_hwbug = 1;
3968
3969                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3970                                 tg3_set_txd(tp, entry, mapping, len,
3971                                             base_flags, (i == last)|(mss << 1));
3972                         else
3973                                 tg3_set_txd(tp, entry, mapping, len,
3974                                             base_flags, (i == last));
3975
3976                         entry = NEXT_TX(entry);
3977                 }
3978         }
3979
3980         if (would_hit_hwbug) {
3981                 u32 last_plus_one = entry;
3982                 u32 start;
3983
3984                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3985                 start &= (TG3_TX_RING_SIZE - 1);
3986
3987                 /* If the workaround fails due to memory/mapping
3988                  * failure, silently drop this packet.
3989                  */
3990                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
3991                                                 &start, base_flags, mss))
3992                         goto out_unlock;
3993
3994                 entry = start;
3995         }
3996
3997         /* Packets are ready, update Tx producer idx local and on card. */
3998         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3999
4000         tp->tx_prod = entry;
4001         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
4002                 netif_stop_queue(dev);
4003                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
4004                         netif_wake_queue(tp->dev);
4005         }
4006
4007 out_unlock:
4008         mmiowb();
4009         spin_unlock(&tp->tx_lock);
4010
4011         dev->trans_start = jiffies;
4012
4013         return NETDEV_TX_OK;
4014 }
4015
4016 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4017                                int new_mtu)
4018 {
4019         dev->mtu = new_mtu;
4020
4021         if (new_mtu > ETH_DATA_LEN) {
4022                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4023                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4024                         ethtool_op_set_tso(dev, 0);
4025                 }
4026                 else
4027                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4028         } else {
4029                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4030                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4031                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4032         }
4033 }
4034
4035 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4036 {
4037         struct tg3 *tp = netdev_priv(dev);
4038
4039         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4040                 return -EINVAL;
4041
4042         if (!netif_running(dev)) {
4043                 /* We'll just catch it later when the
4044                  * device is up'd.
4045                  */
4046                 tg3_set_mtu(dev, tp, new_mtu);
4047                 return 0;
4048         }
4049
4050         tg3_netif_stop(tp);
4051
4052         tg3_full_lock(tp, 1);
4053
4054         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4055
4056         tg3_set_mtu(dev, tp, new_mtu);
4057
4058         tg3_init_hw(tp);
4059
4060         tg3_netif_start(tp);
4061
4062         tg3_full_unlock(tp);
4063
4064         return 0;
4065 }
4066
4067 /* Free up pending packets in all rx/tx rings.
4068  *
4069  * The chip has been shut down and the driver detached from
4070  * the networking, so no interrupts or new tx packets will
4071  * end up in the driver.  tp->{tx,}lock is not held and we are not
4072  * in an interrupt context and thus may sleep.
4073  */
4074 static void tg3_free_rings(struct tg3 *tp)
4075 {
4076         struct ring_info *rxp;
4077         int i;
4078
4079         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4080                 rxp = &tp->rx_std_buffers[i];
4081
4082                 if (rxp->skb == NULL)
4083                         continue;
4084                 pci_unmap_single(tp->pdev,
4085                                  pci_unmap_addr(rxp, mapping),
4086                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4087                                  PCI_DMA_FROMDEVICE);
4088                 dev_kfree_skb_any(rxp->skb);
4089                 rxp->skb = NULL;
4090         }
4091
4092         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4093                 rxp = &tp->rx_jumbo_buffers[i];
4094
4095                 if (rxp->skb == NULL)
4096                         continue;
4097                 pci_unmap_single(tp->pdev,
4098                                  pci_unmap_addr(rxp, mapping),
4099                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4100                                  PCI_DMA_FROMDEVICE);
4101                 dev_kfree_skb_any(rxp->skb);
4102                 rxp->skb = NULL;
4103         }
4104
4105         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4106                 struct tx_ring_info *txp;
4107                 struct sk_buff *skb;
4108                 int j;
4109
4110                 txp = &tp->tx_buffers[i];
4111                 skb = txp->skb;
4112
4113                 if (skb == NULL) {
4114                         i++;
4115                         continue;
4116                 }
4117
4118                 pci_unmap_single(tp->pdev,
4119                                  pci_unmap_addr(txp, mapping),
4120                                  skb_headlen(skb),
4121                                  PCI_DMA_TODEVICE);
4122                 txp->skb = NULL;
4123
4124                 i++;
4125
4126                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4127                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4128                         pci_unmap_page(tp->pdev,
4129                                        pci_unmap_addr(txp, mapping),
4130                                        skb_shinfo(skb)->frags[j].size,
4131                                        PCI_DMA_TODEVICE);
4132                         i++;
4133                 }
4134
4135                 dev_kfree_skb_any(skb);
4136         }
4137 }
4138
4139 /* Initialize tx/rx rings for packet processing.
4140  *
4141  * The chip has been shut down and the driver detached from
4142  * the networking, so no interrupts or new tx packets will
4143  * end up in the driver.  tp->{tx,}lock are held and thus
4144  * we may not sleep.
4145  */
4146 static void tg3_init_rings(struct tg3 *tp)
4147 {
4148         u32 i;
4149
4150         /* Free up all the SKBs. */
4151         tg3_free_rings(tp);
4152
4153         /* Zero out all descriptors. */
4154         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4155         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4156         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4157         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4158
4159         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4160         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4161             (tp->dev->mtu > ETH_DATA_LEN))
4162                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4163
4164         /* Initialize invariants of the rings, we only set this
4165          * stuff once.  This works because the card does not
4166          * write into the rx buffer posting rings.
4167          */
4168         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4169                 struct tg3_rx_buffer_desc *rxd;
4170
4171                 rxd = &tp->rx_std[i];
4172                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4173                         << RXD_LEN_SHIFT;
4174                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4175                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4176                                (i << RXD_OPAQUE_INDEX_SHIFT));
4177         }
4178
4179         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4180                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4181                         struct tg3_rx_buffer_desc *rxd;
4182
4183                         rxd = &tp->rx_jumbo[i];
4184                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4185                                 << RXD_LEN_SHIFT;
4186                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4187                                 RXD_FLAG_JUMBO;
4188                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4189                                (i << RXD_OPAQUE_INDEX_SHIFT));
4190                 }
4191         }
4192
4193         /* Now allocate fresh SKBs for each rx ring. */
4194         for (i = 0; i < tp->rx_pending; i++) {
4195                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
4196                                      -1, i) < 0)
4197                         break;
4198         }
4199
4200         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4201                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4202                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4203                                              -1, i) < 0)
4204                                 break;
4205                 }
4206         }
4207 }
4208
4209 /*
4210  * Must not be invoked with interrupt sources disabled and
4211  * the hardware shutdown down.
4212  */
4213 static void tg3_free_consistent(struct tg3 *tp)
4214 {
4215         kfree(tp->rx_std_buffers);
4216         tp->rx_std_buffers = NULL;
4217         if (tp->rx_std) {
4218                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4219                                     tp->rx_std, tp->rx_std_mapping);
4220                 tp->rx_std = NULL;
4221         }
4222         if (tp->rx_jumbo) {
4223                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4224                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4225                 tp->rx_jumbo = NULL;
4226         }
4227         if (tp->rx_rcb) {
4228                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4229                                     tp->rx_rcb, tp->rx_rcb_mapping);
4230                 tp->rx_rcb = NULL;
4231         }
4232         if (tp->tx_ring) {
4233                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4234                         tp->tx_ring, tp->tx_desc_mapping);
4235                 tp->tx_ring = NULL;
4236         }
4237         if (tp->hw_status) {
4238                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4239                                     tp->hw_status, tp->status_mapping);
4240                 tp->hw_status = NULL;
4241         }
4242         if (tp->hw_stats) {
4243                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4244                                     tp->hw_stats, tp->stats_mapping);
4245                 tp->hw_stats = NULL;
4246         }
4247 }
4248
4249 /*
4250  * Must not be invoked with interrupt sources disabled and
4251  * the hardware shutdown down.  Can sleep.
4252  */
4253 static int tg3_alloc_consistent(struct tg3 *tp)
4254 {
4255         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4256                                       (TG3_RX_RING_SIZE +
4257                                        TG3_RX_JUMBO_RING_SIZE)) +
4258                                      (sizeof(struct tx_ring_info) *
4259                                       TG3_TX_RING_SIZE),
4260                                      GFP_KERNEL);
4261         if (!tp->rx_std_buffers)
4262                 return -ENOMEM;
4263
4264         memset(tp->rx_std_buffers, 0,
4265                (sizeof(struct ring_info) *
4266                 (TG3_RX_RING_SIZE +
4267                  TG3_RX_JUMBO_RING_SIZE)) +
4268                (sizeof(struct tx_ring_info) *
4269                 TG3_TX_RING_SIZE));
4270
4271         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4272         tp->tx_buffers = (struct tx_ring_info *)
4273                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4274
4275         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4276                                           &tp->rx_std_mapping);
4277         if (!tp->rx_std)
4278                 goto err_out;
4279
4280         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4281                                             &tp->rx_jumbo_mapping);
4282
4283         if (!tp->rx_jumbo)
4284                 goto err_out;
4285
4286         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4287                                           &tp->rx_rcb_mapping);
4288         if (!tp->rx_rcb)
4289                 goto err_out;
4290
4291         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4292                                            &tp->tx_desc_mapping);
4293         if (!tp->tx_ring)
4294                 goto err_out;
4295
4296         tp->hw_status = pci_alloc_consistent(tp->pdev,
4297                                              TG3_HW_STATUS_SIZE,
4298                                              &tp->status_mapping);
4299         if (!tp->hw_status)
4300                 goto err_out;
4301
4302         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4303                                             sizeof(struct tg3_hw_stats),
4304                                             &tp->stats_mapping);
4305         if (!tp->hw_stats)
4306                 goto err_out;
4307
4308         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4309         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4310
4311         return 0;
4312
4313 err_out:
4314         tg3_free_consistent(tp);
4315         return -ENOMEM;
4316 }
4317
4318 #define MAX_WAIT_CNT 1000
4319
4320 /* To stop a block, clear the enable bit and poll till it
4321  * clears.  tp->lock is held.
4322  */
4323 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4324 {
4325         unsigned int i;
4326         u32 val;
4327
4328         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4329                 switch (ofs) {
4330                 case RCVLSC_MODE:
4331                 case DMAC_MODE:
4332                 case MBFREE_MODE:
4333                 case BUFMGR_MODE:
4334                 case MEMARB_MODE:
4335                         /* We can't enable/disable these bits of the
4336                          * 5705/5750, just say success.
4337                          */
4338                         return 0;
4339
4340                 default:
4341                         break;
4342                 };
4343         }
4344
4345         val = tr32(ofs);
4346         val &= ~enable_bit;
4347         tw32_f(ofs, val);
4348
4349         for (i = 0; i < MAX_WAIT_CNT; i++) {
4350                 udelay(100);
4351                 val = tr32(ofs);
4352                 if ((val & enable_bit) == 0)
4353                         break;
4354         }
4355
4356         if (i == MAX_WAIT_CNT && !silent) {
4357                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4358                        "ofs=%lx enable_bit=%x\n",
4359                        ofs, enable_bit);
4360                 return -ENODEV;
4361         }
4362
4363         return 0;
4364 }
4365
4366 /* tp->lock is held. */
4367 static int tg3_abort_hw(struct tg3 *tp, int silent)
4368 {
4369         int i, err;
4370
4371         tg3_disable_ints(tp);
4372
4373         tp->rx_mode &= ~RX_MODE_ENABLE;
4374         tw32_f(MAC_RX_MODE, tp->rx_mode);
4375         udelay(10);
4376
4377         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4378         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4379         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4380         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4381         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4382         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4383
4384         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4385         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4386         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4387         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4388         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4389         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4390         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4391
4392         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4393         tw32_f(MAC_MODE, tp->mac_mode);
4394         udelay(40);
4395
4396         tp->tx_mode &= ~TX_MODE_ENABLE;
4397         tw32_f(MAC_TX_MODE, tp->tx_mode);
4398
4399         for (i = 0; i < MAX_WAIT_CNT; i++) {
4400                 udelay(100);
4401                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4402                         break;
4403         }
4404         if (i >= MAX_WAIT_CNT) {
4405                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4406                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4407                        tp->dev->name, tr32(MAC_TX_MODE));
4408                 err |= -ENODEV;
4409         }
4410
4411         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4412         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4413         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4414
4415         tw32(FTQ_RESET, 0xffffffff);
4416         tw32(FTQ_RESET, 0x00000000);
4417
4418         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4419         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4420
4421         if (tp->hw_status)
4422                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4423         if (tp->hw_stats)
4424                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4425
4426         return err;
4427 }
4428
4429 /* tp->lock is held. */
4430 static int tg3_nvram_lock(struct tg3 *tp)
4431 {
4432         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4433                 int i;
4434
4435                 if (tp->nvram_lock_cnt == 0) {
4436                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4437                         for (i = 0; i < 8000; i++) {
4438                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4439                                         break;
4440                                 udelay(20);
4441                         }
4442                         if (i == 8000) {
4443                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4444                                 return -ENODEV;
4445                         }
4446                 }
4447                 tp->nvram_lock_cnt++;
4448         }
4449         return 0;
4450 }
4451
4452 /* tp->lock is held. */
4453 static void tg3_nvram_unlock(struct tg3 *tp)
4454 {
4455         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4456                 if (tp->nvram_lock_cnt > 0)
4457                         tp->nvram_lock_cnt--;
4458                 if (tp->nvram_lock_cnt == 0)
4459                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4460         }
4461 }
4462
4463 /* tp->lock is held. */
4464 static void tg3_enable_nvram_access(struct tg3 *tp)
4465 {
4466         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4467             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4468                 u32 nvaccess = tr32(NVRAM_ACCESS);
4469
4470                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4471         }
4472 }
4473
4474 /* tp->lock is held. */
4475 static void tg3_disable_nvram_access(struct tg3 *tp)
4476 {
4477         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4478             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4479                 u32 nvaccess = tr32(NVRAM_ACCESS);
4480
4481                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4482         }
4483 }
4484
4485 /* tp->lock is held. */
4486 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4487 {
4488         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4489                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4490                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4491
4492         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4493                 switch (kind) {
4494                 case RESET_KIND_INIT:
4495                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4496                                       DRV_STATE_START);
4497                         break;
4498
4499                 case RESET_KIND_SHUTDOWN:
4500                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4501                                       DRV_STATE_UNLOAD);
4502                         break;
4503
4504                 case RESET_KIND_SUSPEND:
4505                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4506                                       DRV_STATE_SUSPEND);
4507                         break;
4508
4509                 default:
4510                         break;
4511                 };
4512         }
4513 }
4514
4515 /* tp->lock is held. */
4516 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4517 {
4518         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4519                 switch (kind) {
4520                 case RESET_KIND_INIT:
4521                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4522                                       DRV_STATE_START_DONE);
4523                         break;
4524
4525                 case RESET_KIND_SHUTDOWN:
4526                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4527                                       DRV_STATE_UNLOAD_DONE);
4528                         break;
4529
4530                 default:
4531                         break;
4532                 };
4533         }
4534 }
4535
4536 /* tp->lock is held. */
4537 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4538 {
4539         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4540                 switch (kind) {
4541                 case RESET_KIND_INIT:
4542                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4543                                       DRV_STATE_START);
4544                         break;
4545
4546                 case RESET_KIND_SHUTDOWN:
4547                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4548                                       DRV_STATE_UNLOAD);
4549                         break;
4550
4551                 case RESET_KIND_SUSPEND:
4552                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4553                                       DRV_STATE_SUSPEND);
4554                         break;
4555
4556                 default:
4557                         break;
4558                 };
4559         }
4560 }
4561
4562 static void tg3_stop_fw(struct tg3 *);
4563
4564 /* tp->lock is held. */
4565 static int tg3_chip_reset(struct tg3 *tp)
4566 {
4567         u32 val;
4568         void (*write_op)(struct tg3 *, u32, u32);
4569         int i;
4570
4571         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4572                 tg3_nvram_lock(tp);
4573                 /* No matching tg3_nvram_unlock() after this because
4574                  * chip reset below will undo the nvram lock.
4575                  */
4576                 tp->nvram_lock_cnt = 0;
4577         }
4578
4579         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4580             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4581             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4582                 tw32(GRC_FASTBOOT_PC, 0);
4583
4584         /*
4585          * We must avoid the readl() that normally takes place.
4586          * It locks machines, causes machine checks, and other
4587          * fun things.  So, temporarily disable the 5701
4588          * hardware workaround, while we do the reset.
4589          */
4590         write_op = tp->write32;
4591         if (write_op == tg3_write_flush_reg32)
4592                 tp->write32 = tg3_write32;
4593
4594         /* do the reset */
4595         val = GRC_MISC_CFG_CORECLK_RESET;
4596
4597         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4598                 if (tr32(0x7e2c) == 0x60) {
4599                         tw32(0x7e2c, 0x20);
4600                 }
4601                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4602                         tw32(GRC_MISC_CFG, (1 << 29));
4603                         val |= (1 << 29);
4604                 }
4605         }
4606
4607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4608                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4609         tw32(GRC_MISC_CFG, val);
4610
4611         /* restore 5701 hardware bug workaround write method */
4612         tp->write32 = write_op;
4613
4614         /* Unfortunately, we have to delay before the PCI read back.
4615          * Some 575X chips even will not respond to a PCI cfg access
4616          * when the reset command is given to the chip.
4617          *
4618          * How do these hardware designers expect things to work
4619          * properly if the PCI write is posted for a long period
4620          * of time?  It is always necessary to have some method by
4621          * which a register read back can occur to push the write
4622          * out which does the reset.
4623          *
4624          * For most tg3 variants the trick below was working.
4625          * Ho hum...
4626          */
4627         udelay(120);
4628
4629         /* Flush PCI posted writes.  The normal MMIO registers
4630          * are inaccessible at this time so this is the only
4631          * way to make this reliably (actually, this is no longer
4632          * the case, see above).  I tried to use indirect
4633          * register read/write but this upset some 5701 variants.
4634          */
4635         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4636
4637         udelay(120);
4638
4639         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4640                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4641                         int i;
4642                         u32 cfg_val;
4643
4644                         /* Wait for link training to complete.  */
4645                         for (i = 0; i < 5000; i++)
4646                                 udelay(100);
4647
4648                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4649                         pci_write_config_dword(tp->pdev, 0xc4,
4650                                                cfg_val | (1 << 15));
4651                 }
4652                 /* Set PCIE max payload size and clear error status.  */
4653                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4654         }
4655
4656         /* Re-enable indirect register accesses. */
4657         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4658                                tp->misc_host_ctrl);
4659
4660         /* Set MAX PCI retry to zero. */
4661         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4662         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4663             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4664                 val |= PCISTATE_RETRY_SAME_DMA;
4665         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4666
4667         pci_restore_state(tp->pdev);
4668
4669         /* Make sure PCI-X relaxed ordering bit is clear. */
4670         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4671         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4672         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4673
4674         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4675                 u32 val;
4676
4677                 /* Chip reset on 5780 will reset MSI enable bit,
4678                  * so need to restore it.
4679                  */
4680                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4681                         u16 ctrl;
4682
4683                         pci_read_config_word(tp->pdev,
4684                                              tp->msi_cap + PCI_MSI_FLAGS,
4685                                              &ctrl);
4686                         pci_write_config_word(tp->pdev,
4687                                               tp->msi_cap + PCI_MSI_FLAGS,
4688                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4689                         val = tr32(MSGINT_MODE);
4690                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4691                 }
4692
4693                 val = tr32(MEMARB_MODE);
4694                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4695
4696         } else
4697                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4698
4699         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4700                 tg3_stop_fw(tp);
4701                 tw32(0x5000, 0x400);
4702         }
4703
4704         tw32(GRC_MODE, tp->grc_mode);
4705
4706         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4707                 u32 val = tr32(0xc4);
4708
4709                 tw32(0xc4, val | (1 << 15));
4710         }
4711
4712         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4713             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4714                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4715                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4716                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4717                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4718         }
4719
4720         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4721                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4722                 tw32_f(MAC_MODE, tp->mac_mode);
4723         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4724                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4725                 tw32_f(MAC_MODE, tp->mac_mode);
4726         } else
4727                 tw32_f(MAC_MODE, 0);
4728         udelay(40);
4729
4730         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4731                 /* Wait for firmware initialization to complete. */
4732                 for (i = 0; i < 100000; i++) {
4733                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4734                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4735                                 break;
4736                         udelay(10);
4737                 }
4738                 if (i >= 100000) {
4739                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4740                                "firmware will not restart magic=%08x\n",
4741                                tp->dev->name, val);
4742                         return -ENODEV;
4743                 }
4744         }
4745
4746         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4747             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4748                 u32 val = tr32(0x7c00);
4749
4750                 tw32(0x7c00, val | (1 << 25));
4751         }
4752
4753         /* Reprobe ASF enable state.  */
4754         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4755         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4756         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4757         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4758                 u32 nic_cfg;
4759
4760                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4761                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4762                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4763                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4764                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4765                 }
4766         }
4767
4768         return 0;
4769 }
4770
4771 /* tp->lock is held. */
4772 static void tg3_stop_fw(struct tg3 *tp)
4773 {
4774         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4775                 u32 val;
4776                 int i;
4777
4778                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4779                 val = tr32(GRC_RX_CPU_EVENT);
4780                 val |= (1 << 14);
4781                 tw32(GRC_RX_CPU_EVENT, val);
4782
4783                 /* Wait for RX cpu to ACK the event.  */
4784                 for (i = 0; i < 100; i++) {
4785                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4786                                 break;
4787                         udelay(1);
4788                 }
4789         }
4790 }
4791
4792 /* tp->lock is held. */
4793 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4794 {
4795         int err;
4796
4797         tg3_stop_fw(tp);
4798
4799         tg3_write_sig_pre_reset(tp, kind);
4800
4801         tg3_abort_hw(tp, silent);
4802         err = tg3_chip_reset(tp);
4803
4804         tg3_write_sig_legacy(tp, kind);
4805         tg3_write_sig_post_reset(tp, kind);
4806
4807         if (err)
4808                 return err;
4809
4810         return 0;
4811 }
4812
4813 #define TG3_FW_RELEASE_MAJOR    0x0
4814 #define TG3_FW_RELASE_MINOR     0x0
4815 #define TG3_FW_RELEASE_FIX      0x0
4816 #define TG3_FW_START_ADDR       0x08000000
4817 #define TG3_FW_TEXT_ADDR        0x08000000
4818 #define TG3_FW_TEXT_LEN         0x9c0
4819 #define TG3_FW_RODATA_ADDR      0x080009c0
4820 #define TG3_FW_RODATA_LEN       0x60
4821 #define TG3_FW_DATA_ADDR        0x08000a40
4822 #define TG3_FW_DATA_LEN         0x20
4823 #define TG3_FW_SBSS_ADDR        0x08000a60
4824 #define TG3_FW_SBSS_LEN         0xc
4825 #define TG3_FW_BSS_ADDR         0x08000a70
4826 #define TG3_FW_BSS_LEN          0x10
4827
4828 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4829         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4830         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4831         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4832         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4833         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4834         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4835         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4836         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4837         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4838         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4839         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4840         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4841         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4842         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4843         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4844         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4845         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4846         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4847         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4848         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4849         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4850         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4851         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4852         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4853         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4854         0, 0, 0, 0, 0, 0,
4855         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4856         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4857         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4858         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4859         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4860         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4861         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4862         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4863         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4864         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4865         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4866         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4867         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4868         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4869         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4870         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4871         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4872         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4873         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4874         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4875         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4876         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4877         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4878         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4879         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4880         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4881         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4882         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4883         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4884         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4885         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4886         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4887         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4888         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4889         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4890         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4891         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4892         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4893         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4894         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4895         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4896         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4897         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4898         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4899         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4900         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4901         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4902         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4903         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4904         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4905         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4906         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4907         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4908         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4909         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4910         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4911         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4912         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4913         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4914         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4915         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4916         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4917         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4918         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4919         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4920 };
4921
4922 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4923         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4924         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4925         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4926         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4927         0x00000000
4928 };
4929
4930 #if 0 /* All zeros, don't eat up space with it. */
4931 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4932         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4933         0x00000000, 0x00000000, 0x00000000, 0x00000000
4934 };
4935 #endif
4936
4937 #define RX_CPU_SCRATCH_BASE     0x30000
4938 #define RX_CPU_SCRATCH_SIZE     0x04000
4939 #define TX_CPU_SCRATCH_BASE     0x34000
4940 #define TX_CPU_SCRATCH_SIZE     0x04000
4941
4942 /* tp->lock is held. */
4943 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4944 {
4945         int i;
4946
4947         BUG_ON(offset == TX_CPU_BASE &&
4948             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
4949
4950         if (offset == RX_CPU_BASE) {
4951                 for (i = 0; i < 10000; i++) {
4952                         tw32(offset + CPU_STATE, 0xffffffff);
4953                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4954                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4955                                 break;
4956                 }
4957
4958                 tw32(offset + CPU_STATE, 0xffffffff);
4959                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4960                 udelay(10);
4961         } else {
4962                 for (i = 0; i < 10000; i++) {
4963                         tw32(offset + CPU_STATE, 0xffffffff);
4964                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4965                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4966                                 break;
4967                 }
4968         }
4969
4970         if (i >= 10000) {
4971                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4972                        "and %s CPU\n",
4973                        tp->dev->name,
4974                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4975                 return -ENODEV;
4976         }
4977
4978         /* Clear firmware's nvram arbitration. */
4979         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4980                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
4981         return 0;
4982 }
4983
4984 struct fw_info {
4985         unsigned int text_base;
4986         unsigned int text_len;
4987         u32 *text_data;
4988         unsigned int rodata_base;
4989         unsigned int rodata_len;
4990         u32 *rodata_data;
4991         unsigned int data_base;
4992         unsigned int data_len;
4993         u32 *data_data;
4994 };
4995
4996 /* tp->lock is held. */
4997 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4998                                  int cpu_scratch_size, struct fw_info *info)
4999 {
5000         int err, lock_err, i;
5001         void (*write_op)(struct tg3 *, u32, u32);
5002
5003         if (cpu_base == TX_CPU_BASE &&
5004             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5005                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5006                        "TX cpu firmware on %s which is 5705.\n",
5007                        tp->dev->name);
5008                 return -EINVAL;
5009         }
5010
5011         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5012                 write_op = tg3_write_mem;
5013         else
5014                 write_op = tg3_write_indirect_reg32;
5015
5016         /* It is possible that bootcode is still loading at this point.
5017          * Get the nvram lock first before halting the cpu.
5018          */
5019         lock_err = tg3_nvram_lock(tp);
5020         err = tg3_halt_cpu(tp, cpu_base);
5021         if (!lock_err)
5022                 tg3_nvram_unlock(tp);
5023         if (err)
5024                 goto out;
5025
5026         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5027                 write_op(tp, cpu_scratch_base + i, 0);
5028         tw32(cpu_base + CPU_STATE, 0xffffffff);
5029         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5030         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5031                 write_op(tp, (cpu_scratch_base +
5032                               (info->text_base & 0xffff) +
5033                               (i * sizeof(u32))),
5034                          (info->text_data ?
5035                           info->text_data[i] : 0));
5036         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5037                 write_op(tp, (cpu_scratch_base +
5038                               (info->rodata_base & 0xffff) +
5039                               (i * sizeof(u32))),
5040                          (info->rodata_data ?
5041                           info->rodata_data[i] : 0));
5042         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5043                 write_op(tp, (cpu_scratch_base +
5044                               (info->data_base & 0xffff) +
5045                               (i * sizeof(u32))),
5046                          (info->data_data ?
5047                           info->data_data[i] : 0));
5048
5049         err = 0;
5050
5051 out:
5052         return err;
5053 }
5054
5055 /* tp->lock is held. */
5056 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5057 {
5058         struct fw_info info;
5059         int err, i;
5060
5061         info.text_base = TG3_FW_TEXT_ADDR;
5062         info.text_len = TG3_FW_TEXT_LEN;
5063         info.text_data = &tg3FwText[0];
5064         info.rodata_base = TG3_FW_RODATA_ADDR;
5065         info.rodata_len = TG3_FW_RODATA_LEN;
5066         info.rodata_data = &tg3FwRodata[0];
5067         info.data_base = TG3_FW_DATA_ADDR;
5068         info.data_len = TG3_FW_DATA_LEN;
5069         info.data_data = NULL;
5070
5071         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5072                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5073                                     &info);
5074         if (err)
5075                 return err;
5076
5077         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5078                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5079                                     &info);
5080         if (err)
5081                 return err;
5082
5083         /* Now startup only the RX cpu. */
5084         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5085         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5086
5087         for (i = 0; i < 5; i++) {
5088                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5089                         break;
5090                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5091                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5092                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5093                 udelay(1000);
5094         }
5095         if (i >= 5) {
5096                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5097                        "to set RX CPU PC, is %08x should be %08x\n",
5098                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5099                        TG3_FW_TEXT_ADDR);
5100                 return -ENODEV;
5101         }
5102         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5103         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5104
5105         return 0;
5106 }
5107
5108 #if TG3_TSO_SUPPORT != 0
5109
5110 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5111 #define TG3_TSO_FW_RELASE_MINOR         0x6
5112 #define TG3_TSO_FW_RELEASE_FIX          0x0
5113 #define TG3_TSO_FW_START_ADDR           0x08000000
5114 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5115 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5116 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5117 #define TG3_TSO_FW_RODATA_LEN           0x60
5118 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5119 #define TG3_TSO_FW_DATA_LEN             0x30
5120 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5121 #define TG3_TSO_FW_SBSS_LEN             0x2c
5122 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5123 #define TG3_TSO_FW_BSS_LEN              0x894
5124
5125 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5126         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5127         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5128         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5129         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5130         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5131         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5132         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5133         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5134         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5135         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5136         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5137         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5138         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5139         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5140         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5141         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5142         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5143         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5144         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5145         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5146         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5147         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5148         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5149         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5150         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5151         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5152         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5153         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5154         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5155         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5156         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5157         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5158         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5159         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5160         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5161         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5162         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5163         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5164         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5165         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5166         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5167         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5168         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5169         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5170         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5171         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5172         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5173         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5174         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5175         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5176         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5177         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5178         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5179         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5180         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5181         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5182         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5183         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5184         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5185         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5186         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5187         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5188         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5189         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5190         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5191         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5192         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5193         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5194         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5195         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5196         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5197         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5198         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5199         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5200         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5201         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5202         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5203         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5204         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5205         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5206         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5207         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5208         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5209         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5210         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5211         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5212         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5213         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5214         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5215         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5216         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5217         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5218         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5219         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5220         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5221         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5222         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5223         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5224         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5225         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5226         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5227         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5228         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5229         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5230         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5231         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5232         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5233         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5234         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5235         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5236         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5237         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5238         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5239         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5240         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5241         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5242         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5243         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5244         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5245         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5246         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5247         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5248         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5249         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5250         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5251         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5252         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5253         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5254         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5255         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5256         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5257         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5258         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5259         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5260         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5261         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5262         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5263         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5264         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5265         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5266         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5267         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5268         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5269         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5270         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5271         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5272         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5273         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5274         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5275         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5276         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5277         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5278         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5279         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5280         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5281         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5282         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5283         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5284         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5285         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5286         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5287         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5288         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5289         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5290         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5291         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5292         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5293         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5294         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5295         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5296         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5297         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5298         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5299         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5300         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5301         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5302         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5303         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5304         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5305         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5306         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5307         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5308         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5309         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5310         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5311         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5312         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5313         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5314         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5315         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5316         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5317         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5318         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5319         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5320         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5321         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5322         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5323         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5324         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5325         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5326         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5327         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5328         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5329         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5330         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5331         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5332         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5333         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5334         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5335         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5336         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5337         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5338         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5339         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5340         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5341         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5342         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5343         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5344         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5345         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5346         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5347         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5348         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5349         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5350         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5351         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5352         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5353         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5354         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5355         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5356         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5357         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5358         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5359         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5360         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5361         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5362         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5363         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5364         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5365         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5366         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5367         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5368         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5369         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5370         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5371         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5372         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5373         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5374         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5375         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5376         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5377         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5378         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5379         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5380         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5381         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5382         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5383         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5384         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5385         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5386         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5387         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5388         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5389         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5390         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5391         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5392         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5393         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5394         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5395         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5396         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5397         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5398         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5399         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5400         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5401         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5402         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5403         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5404         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5405         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5406         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5407         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5408         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5409         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5410 };
5411
5412 static u32 tg3TsoFwRodata[] = {
5413         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5414         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5415         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5416         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5417         0x00000000,
5418 };
5419
5420 static u32 tg3TsoFwData[] = {
5421         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5422         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5423         0x00000000,
5424 };
5425
5426 /* 5705 needs a special version of the TSO firmware.  */
5427 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5428 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5429 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5430 #define TG3_TSO5_FW_START_ADDR          0x00010000
5431 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5432 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5433 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5434 #define TG3_TSO5_FW_RODATA_LEN          0x50
5435 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5436 #define TG3_TSO5_FW_DATA_LEN            0x20
5437 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5438 #define TG3_TSO5_FW_SBSS_LEN            0x28
5439 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5440 #define TG3_TSO5_FW_BSS_LEN             0x88
5441
5442 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5443         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5444         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5445         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5446         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5447         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5448         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5449         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5450         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5451         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5452         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5453         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5454         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5455         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5456         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5457         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5458         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5459         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5460         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5461         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5462         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5463         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5464         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5465         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5466         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5467         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5468         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5469         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5470         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5471         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5472         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5473         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5474         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5475         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5476         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5477         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5478         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5479         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5480         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5481         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5482         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5483         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5484         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5485         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5486         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5487         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5488         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5489         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5490         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5491         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5492         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5493         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5494         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5495         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5496         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5497         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5498         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5499         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5500         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5501         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5502         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5503         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5504         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5505         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5506         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5507         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5508         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5509         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5510         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5511         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5512         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5513         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5514         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5515         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5516         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5517         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5518         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5519         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5520         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5521         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5522         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5523         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5524         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5525         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5526         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5527         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5528         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5529         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5530         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5531         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5532         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5533         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5534         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5535         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5536         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5537         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5538         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5539         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5540         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5541         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5542         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5543         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5544         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5545         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5546         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5547         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5548         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5549         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5550         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5551         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5552         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5553         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5554         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5555         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5556         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5557         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5558         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5559         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5560         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5561         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5562         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5563         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5564         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5565         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5566         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5567         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5568         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5569         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5570         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5571         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5572         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5573         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5574         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5575         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5576         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5577         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5578         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5579         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5580         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5581         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5582         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5583         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5584         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5585         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5586         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5587         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5588         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5589         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5590         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5591         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5592         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5593         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5594         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5595         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5596         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5597         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5598         0x00000000, 0x00000000, 0x00000000,
5599 };
5600
5601 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5602         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5603         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5604         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5605         0x00000000, 0x00000000, 0x00000000,
5606 };
5607
5608 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5609         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5610         0x00000000, 0x00000000, 0x00000000,
5611 };
5612
5613 /* tp->lock is held. */
5614 static int tg3_load_tso_firmware(struct tg3 *tp)
5615 {
5616         struct fw_info info;
5617         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5618         int err, i;
5619
5620         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5621                 return 0;
5622
5623         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5624                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5625                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5626                 info.text_data = &tg3Tso5FwText[0];
5627                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5628                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5629                 info.rodata_data = &tg3Tso5FwRodata[0];
5630                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5631                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5632                 info.data_data = &tg3Tso5FwData[0];
5633                 cpu_base = RX_CPU_BASE;
5634                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5635                 cpu_scratch_size = (info.text_len +
5636                                     info.rodata_len +
5637                                     info.data_len +
5638                                     TG3_TSO5_FW_SBSS_LEN +
5639                                     TG3_TSO5_FW_BSS_LEN);
5640         } else {
5641                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5642                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5643                 info.text_data = &tg3TsoFwText[0];
5644                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5645                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5646                 info.rodata_data = &tg3TsoFwRodata[0];
5647                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5648                 info.data_len = TG3_TSO_FW_DATA_LEN;
5649                 info.data_data = &tg3TsoFwData[0];
5650                 cpu_base = TX_CPU_BASE;
5651                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5652                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5653         }
5654
5655         err = tg3_load_firmware_cpu(tp, cpu_base,
5656                                     cpu_scratch_base, cpu_scratch_size,
5657                                     &info);
5658         if (err)
5659                 return err;
5660
5661         /* Now startup the cpu. */
5662         tw32(cpu_base + CPU_STATE, 0xffffffff);
5663         tw32_f(cpu_base + CPU_PC,    info.text_base);
5664
5665         for (i = 0; i < 5; i++) {
5666                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5667                         break;
5668                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5669                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5670                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5671                 udelay(1000);
5672         }
5673         if (i >= 5) {
5674                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5675                        "to set CPU PC, is %08x should be %08x\n",
5676                        tp->dev->name, tr32(cpu_base + CPU_PC),
5677                        info.text_base);
5678                 return -ENODEV;
5679         }
5680         tw32(cpu_base + CPU_STATE, 0xffffffff);
5681         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5682         return 0;
5683 }
5684
5685 #endif /* TG3_TSO_SUPPORT != 0 */
5686
5687 /* tp->lock is held. */
5688 static void __tg3_set_mac_addr(struct tg3 *tp)
5689 {
5690         u32 addr_high, addr_low;
5691         int i;
5692
5693         addr_high = ((tp->dev->dev_addr[0] << 8) |
5694                      tp->dev->dev_addr[1]);
5695         addr_low = ((tp->dev->dev_addr[2] << 24) |
5696                     (tp->dev->dev_addr[3] << 16) |
5697                     (tp->dev->dev_addr[4] <<  8) |
5698                     (tp->dev->dev_addr[5] <<  0));
5699         for (i = 0; i < 4; i++) {
5700                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5701                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5702         }
5703
5704         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5705             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5706                 for (i = 0; i < 12; i++) {
5707                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5708                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5709                 }
5710         }
5711
5712         addr_high = (tp->dev->dev_addr[0] +
5713                      tp->dev->dev_addr[1] +
5714                      tp->dev->dev_addr[2] +
5715                      tp->dev->dev_addr[3] +
5716                      tp->dev->dev_addr[4] +
5717                      tp->dev->dev_addr[5]) &
5718                 TX_BACKOFF_SEED_MASK;
5719         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5720 }
5721
5722 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5723 {
5724         struct tg3 *tp = netdev_priv(dev);
5725         struct sockaddr *addr = p;
5726
5727         if (!is_valid_ether_addr(addr->sa_data))
5728                 return -EINVAL;
5729
5730         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5731
5732         if (!netif_running(dev))
5733                 return 0;
5734
5735         spin_lock_bh(&tp->lock);
5736         __tg3_set_mac_addr(tp);
5737         spin_unlock_bh(&tp->lock);
5738
5739         return 0;
5740 }
5741
5742 /* tp->lock is held. */
5743 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5744                            dma_addr_t mapping, u32 maxlen_flags,
5745                            u32 nic_addr)
5746 {
5747         tg3_write_mem(tp,
5748                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5749                       ((u64) mapping >> 32));
5750         tg3_write_mem(tp,
5751                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5752                       ((u64) mapping & 0xffffffff));
5753         tg3_write_mem(tp,
5754                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5755                        maxlen_flags);
5756
5757         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5758                 tg3_write_mem(tp,
5759                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5760                               nic_addr);
5761 }
5762
5763 static void __tg3_set_rx_mode(struct net_device *);
5764 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5765 {
5766         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5767         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5768         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5769         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5770         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5771                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5772                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5773         }
5774         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5775         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5776         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5777                 u32 val = ec->stats_block_coalesce_usecs;
5778
5779                 if (!netif_carrier_ok(tp->dev))
5780                         val = 0;
5781
5782                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5783         }
5784 }
5785
5786 /* tp->lock is held. */
5787 static int tg3_reset_hw(struct tg3 *tp)
5788 {
5789         u32 val, rdmac_mode;
5790         int i, err, limit;
5791
5792         tg3_disable_ints(tp);
5793
5794         tg3_stop_fw(tp);
5795
5796         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5797
5798         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5799                 tg3_abort_hw(tp, 1);
5800         }
5801
5802         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
5803                 tg3_phy_reset(tp);
5804
5805         err = tg3_chip_reset(tp);
5806         if (err)
5807                 return err;
5808
5809         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5810
5811         /* This works around an issue with Athlon chipsets on
5812          * B3 tigon3 silicon.  This bit has no effect on any
5813          * other revision.  But do not set this on PCI Express
5814          * chips.
5815          */
5816         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5817                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5818         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5819
5820         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5821             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5822                 val = tr32(TG3PCI_PCISTATE);
5823                 val |= PCISTATE_RETRY_SAME_DMA;
5824                 tw32(TG3PCI_PCISTATE, val);
5825         }
5826
5827         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5828                 /* Enable some hw fixes.  */
5829                 val = tr32(TG3PCI_MSI_DATA);
5830                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5831                 tw32(TG3PCI_MSI_DATA, val);
5832         }
5833
5834         /* Descriptor ring init may make accesses to the
5835          * NIC SRAM area to setup the TX descriptors, so we
5836          * can only do this after the hardware has been
5837          * successfully reset.
5838          */
5839         tg3_init_rings(tp);
5840
5841         /* This value is determined during the probe time DMA
5842          * engine test, tg3_test_dma.
5843          */
5844         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5845
5846         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5847                           GRC_MODE_4X_NIC_SEND_RINGS |
5848                           GRC_MODE_NO_TX_PHDR_CSUM |
5849                           GRC_MODE_NO_RX_PHDR_CSUM);
5850         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5851
5852         /* Pseudo-header checksum is done by hardware logic and not
5853          * the offload processers, so make the chip do the pseudo-
5854          * header checksums on receive.  For transmit it is more
5855          * convenient to do the pseudo-header checksum in software
5856          * as Linux does that on transmit for us in all cases.
5857          */
5858         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5859
5860         tw32(GRC_MODE,
5861              tp->grc_mode |
5862              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5863
5864         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5865         val = tr32(GRC_MISC_CFG);
5866         val &= ~0xff;
5867         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5868         tw32(GRC_MISC_CFG, val);
5869
5870         /* Initialize MBUF/DESC pool. */
5871         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5872                 /* Do nothing.  */
5873         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5874                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5875                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5876                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5877                 else
5878                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5879                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5880                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5881         }
5882 #if TG3_TSO_SUPPORT != 0
5883         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5884                 int fw_len;
5885
5886                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5887                           TG3_TSO5_FW_RODATA_LEN +
5888                           TG3_TSO5_FW_DATA_LEN +
5889                           TG3_TSO5_FW_SBSS_LEN +
5890                           TG3_TSO5_FW_BSS_LEN);
5891                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5892                 tw32(BUFMGR_MB_POOL_ADDR,
5893                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5894                 tw32(BUFMGR_MB_POOL_SIZE,
5895                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5896         }
5897 #endif
5898
5899         if (tp->dev->mtu <= ETH_DATA_LEN) {
5900                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5901                      tp->bufmgr_config.mbuf_read_dma_low_water);
5902                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5903                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5904                 tw32(BUFMGR_MB_HIGH_WATER,
5905                      tp->bufmgr_config.mbuf_high_water);
5906         } else {
5907                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5908                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5909                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5910                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5911                 tw32(BUFMGR_MB_HIGH_WATER,
5912                      tp->bufmgr_config.mbuf_high_water_jumbo);
5913         }
5914         tw32(BUFMGR_DMA_LOW_WATER,
5915              tp->bufmgr_config.dma_low_water);
5916         tw32(BUFMGR_DMA_HIGH_WATER,
5917              tp->bufmgr_config.dma_high_water);
5918
5919         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5920         for (i = 0; i < 2000; i++) {
5921                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5922                         break;
5923                 udelay(10);
5924         }
5925         if (i >= 2000) {
5926                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5927                        tp->dev->name);
5928                 return -ENODEV;
5929         }
5930
5931         /* Setup replenish threshold. */
5932         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5933
5934         /* Initialize TG3_BDINFO's at:
5935          *  RCVDBDI_STD_BD:     standard eth size rx ring
5936          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5937          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5938          *
5939          * like so:
5940          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5941          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5942          *                              ring attribute flags
5943          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5944          *
5945          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5946          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5947          *
5948          * The size of each ring is fixed in the firmware, but the location is
5949          * configurable.
5950          */
5951         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5952              ((u64) tp->rx_std_mapping >> 32));
5953         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5954              ((u64) tp->rx_std_mapping & 0xffffffff));
5955         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5956              NIC_SRAM_RX_BUFFER_DESC);
5957
5958         /* Don't even try to program the JUMBO/MINI buffer descriptor
5959          * configs on 5705.
5960          */
5961         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5962                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5963                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5964         } else {
5965                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5966                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5967
5968                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5969                      BDINFO_FLAGS_DISABLED);
5970
5971                 /* Setup replenish threshold. */
5972                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5973
5974                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5975                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5976                              ((u64) tp->rx_jumbo_mapping >> 32));
5977                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5978                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5979                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5980                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5981                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5982                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5983                 } else {
5984                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5985                              BDINFO_FLAGS_DISABLED);
5986                 }
5987
5988         }
5989
5990         /* There is only one send ring on 5705/5750, no need to explicitly
5991          * disable the others.
5992          */
5993         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5994                 /* Clear out send RCB ring in SRAM. */
5995                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5996                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5997                                       BDINFO_FLAGS_DISABLED);
5998         }
5999
6000         tp->tx_prod = 0;
6001         tp->tx_cons = 0;
6002         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6003         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6004
6005         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6006                        tp->tx_desc_mapping,
6007                        (TG3_TX_RING_SIZE <<
6008                         BDINFO_FLAGS_MAXLEN_SHIFT),
6009                        NIC_SRAM_TX_BUFFER_DESC);
6010
6011         /* There is only one receive return ring on 5705/5750, no need
6012          * to explicitly disable the others.
6013          */
6014         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6015                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6016                      i += TG3_BDINFO_SIZE) {
6017                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6018                                       BDINFO_FLAGS_DISABLED);
6019                 }
6020         }
6021
6022         tp->rx_rcb_ptr = 0;
6023         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6024
6025         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6026                        tp->rx_rcb_mapping,
6027                        (TG3_RX_RCB_RING_SIZE(tp) <<
6028                         BDINFO_FLAGS_MAXLEN_SHIFT),
6029                        0);
6030
6031         tp->rx_std_ptr = tp->rx_pending;
6032         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6033                      tp->rx_std_ptr);
6034
6035         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6036                                                 tp->rx_jumbo_pending : 0;
6037         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6038                      tp->rx_jumbo_ptr);
6039
6040         /* Initialize MAC address and backoff seed. */
6041         __tg3_set_mac_addr(tp);
6042
6043         /* MTU + ethernet header + FCS + optional VLAN tag */
6044         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6045
6046         /* The slot time is changed by tg3_setup_phy if we
6047          * run at gigabit with half duplex.
6048          */
6049         tw32(MAC_TX_LENGTHS,
6050              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6051              (6 << TX_LENGTHS_IPG_SHIFT) |
6052              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6053
6054         /* Receive rules. */
6055         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6056         tw32(RCVLPC_CONFIG, 0x0181);
6057
6058         /* Calculate RDMAC_MODE setting early, we need it to determine
6059          * the RCVLPC_STATE_ENABLE mask.
6060          */
6061         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6062                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6063                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6064                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6065                       RDMAC_MODE_LNGREAD_ENAB);
6066         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6067                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6068
6069         /* If statement applies to 5705 and 5750 PCI devices only */
6070         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6071              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6072             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6073                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6074                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6075                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6076                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6077                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6078                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6079                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6080                 }
6081         }
6082
6083         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6084                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6085
6086 #if TG3_TSO_SUPPORT != 0
6087         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6088                 rdmac_mode |= (1 << 27);
6089 #endif
6090
6091         /* Receive/send statistics. */
6092         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6093             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6094                 val = tr32(RCVLPC_STATS_ENABLE);
6095                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6096                 tw32(RCVLPC_STATS_ENABLE, val);
6097         } else {
6098                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6099         }
6100         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6101         tw32(SNDDATAI_STATSENAB, 0xffffff);
6102         tw32(SNDDATAI_STATSCTRL,
6103              (SNDDATAI_SCTRL_ENABLE |
6104               SNDDATAI_SCTRL_FASTUPD));
6105
6106         /* Setup host coalescing engine. */
6107         tw32(HOSTCC_MODE, 0);
6108         for (i = 0; i < 2000; i++) {
6109                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6110                         break;
6111                 udelay(10);
6112         }
6113
6114         __tg3_set_coalesce(tp, &tp->coal);
6115
6116         /* set status block DMA address */
6117         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6118              ((u64) tp->status_mapping >> 32));
6119         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6120              ((u64) tp->status_mapping & 0xffffffff));
6121
6122         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6123                 /* Status/statistics block address.  See tg3_timer,
6124                  * the tg3_periodic_fetch_stats call there, and
6125                  * tg3_get_stats to see how this works for 5705/5750 chips.
6126                  */
6127                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6128                      ((u64) tp->stats_mapping >> 32));
6129                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6130                      ((u64) tp->stats_mapping & 0xffffffff));
6131                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6132                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6133         }
6134
6135         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6136
6137         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6138         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6139         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6140                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6141
6142         /* Clear statistics/status block in chip, and status block in ram. */
6143         for (i = NIC_SRAM_STATS_BLK;
6144              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6145              i += sizeof(u32)) {
6146                 tg3_write_mem(tp, i, 0);
6147                 udelay(40);
6148         }
6149         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6150
6151         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6152                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6153                 /* reset to prevent losing 1st rx packet intermittently */
6154                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6155                 udelay(10);
6156         }
6157
6158         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6159                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6160         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6161         udelay(40);
6162
6163         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6164          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
6165          * register to preserve the GPIO settings for LOMs. The GPIOs,
6166          * whether used as inputs or outputs, are set by boot code after
6167          * reset.
6168          */
6169         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6170                 u32 gpio_mask;
6171
6172                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
6173                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
6174
6175                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6176                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6177                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6178
6179                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6180                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6181
6182                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6183
6184                 /* GPIO1 must be driven high for eeprom write protect */
6185                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6186                                        GRC_LCLCTRL_GPIO_OUTPUT1);
6187         }
6188         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6189         udelay(100);
6190
6191         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6192         tp->last_tag = 0;
6193
6194         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6195                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6196                 udelay(40);
6197         }
6198
6199         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6200                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6201                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6202                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6203                WDMAC_MODE_LNGREAD_ENAB);
6204
6205         /* If statement applies to 5705 and 5750 PCI devices only */
6206         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6207              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6208             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6209                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6210                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6211                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6212                         /* nothing */
6213                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6214                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6215                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6216                         val |= WDMAC_MODE_RX_ACCEL;
6217                 }
6218         }
6219
6220         /* Enable host coalescing bug fix */
6221         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6222             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6223                 val |= (1 << 29);
6224
6225         tw32_f(WDMAC_MODE, val);
6226         udelay(40);
6227
6228         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6229                 val = tr32(TG3PCI_X_CAPS);
6230                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6231                         val &= ~PCIX_CAPS_BURST_MASK;
6232                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6233                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6234                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6235                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6236                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6237                                 val |= (tp->split_mode_max_reqs <<
6238                                         PCIX_CAPS_SPLIT_SHIFT);
6239                 }
6240                 tw32(TG3PCI_X_CAPS, val);
6241         }
6242
6243         tw32_f(RDMAC_MODE, rdmac_mode);
6244         udelay(40);
6245
6246         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6247         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6248                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6249         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6250         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6251         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6252         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6253         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6254 #if TG3_TSO_SUPPORT != 0
6255         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6256                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6257 #endif
6258         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6259         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6260
6261         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6262                 err = tg3_load_5701_a0_firmware_fix(tp);
6263                 if (err)
6264                         return err;
6265         }
6266
6267 #if TG3_TSO_SUPPORT != 0
6268         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6269                 err = tg3_load_tso_firmware(tp);
6270                 if (err)
6271                         return err;
6272         }
6273 #endif
6274
6275         tp->tx_mode = TX_MODE_ENABLE;
6276         tw32_f(MAC_TX_MODE, tp->tx_mode);
6277         udelay(100);
6278
6279         tp->rx_mode = RX_MODE_ENABLE;
6280         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6281                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6282
6283         tw32_f(MAC_RX_MODE, tp->rx_mode);
6284         udelay(10);
6285
6286         if (tp->link_config.phy_is_low_power) {
6287                 tp->link_config.phy_is_low_power = 0;
6288                 tp->link_config.speed = tp->link_config.orig_speed;
6289                 tp->link_config.duplex = tp->link_config.orig_duplex;
6290                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6291         }
6292
6293         tp->mi_mode = MAC_MI_MODE_BASE;
6294         tw32_f(MAC_MI_MODE, tp->mi_mode);
6295         udelay(80);
6296
6297         tw32(MAC_LED_CTRL, tp->led_ctrl);
6298
6299         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6300         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6301                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6302                 udelay(10);
6303         }
6304         tw32_f(MAC_RX_MODE, tp->rx_mode);
6305         udelay(10);
6306
6307         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6308                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6309                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6310                         /* Set drive transmission level to 1.2V  */
6311                         /* only if the signal pre-emphasis bit is not set  */
6312                         val = tr32(MAC_SERDES_CFG);
6313                         val &= 0xfffff000;
6314                         val |= 0x880;
6315                         tw32(MAC_SERDES_CFG, val);
6316                 }
6317                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6318                         tw32(MAC_SERDES_CFG, 0x616000);
6319         }
6320
6321         /* Prevent chip from dropping frames when flow control
6322          * is enabled.
6323          */
6324         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6325
6326         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6327             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6328                 /* Use hardware link auto-negotiation */
6329                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6330         }
6331
6332         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6333             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6334                 u32 tmp;
6335
6336                 tmp = tr32(SERDES_RX_CTRL);
6337                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6338                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6339                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6340                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6341         }
6342
6343         err = tg3_setup_phy(tp, 1);
6344         if (err)
6345                 return err;
6346
6347         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6348                 u32 tmp;
6349
6350                 /* Clear CRC stats. */
6351                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6352                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6353                         tg3_readphy(tp, 0x14, &tmp);
6354                 }
6355         }
6356
6357         __tg3_set_rx_mode(tp->dev);
6358
6359         /* Initialize receive rules. */
6360         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6361         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6362         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6363         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6364
6365         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6366             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6367                 limit = 8;
6368         else
6369                 limit = 16;
6370         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6371                 limit -= 4;
6372         switch (limit) {
6373         case 16:
6374                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6375         case 15:
6376                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6377         case 14:
6378                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6379         case 13:
6380                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6381         case 12:
6382                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6383         case 11:
6384                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6385         case 10:
6386                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6387         case 9:
6388                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6389         case 8:
6390                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6391         case 7:
6392                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6393         case 6:
6394                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6395         case 5:
6396                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6397         case 4:
6398                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6399         case 3:
6400                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6401         case 2:
6402         case 1:
6403
6404         default:
6405                 break;
6406         };
6407
6408         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6409
6410         return 0;
6411 }
6412
6413 /* Called at device open time to get the chip ready for
6414  * packet processing.  Invoked with tp->lock held.
6415  */
6416 static int tg3_init_hw(struct tg3 *tp)
6417 {
6418         int err;
6419
6420         /* Force the chip into D0. */
6421         err = tg3_set_power_state(tp, PCI_D0);
6422         if (err)
6423                 goto out;
6424
6425         tg3_switch_clocks(tp);
6426
6427         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6428
6429         err = tg3_reset_hw(tp);
6430
6431 out:
6432         return err;
6433 }
6434
6435 #define TG3_STAT_ADD32(PSTAT, REG) \
6436 do {    u32 __val = tr32(REG); \
6437         (PSTAT)->low += __val; \
6438         if ((PSTAT)->low < __val) \
6439                 (PSTAT)->high += 1; \
6440 } while (0)
6441
6442 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6443 {
6444         struct tg3_hw_stats *sp = tp->hw_stats;
6445
6446         if (!netif_carrier_ok(tp->dev))
6447                 return;
6448
6449         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6450         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6451         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6452         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6453         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6454         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6455         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6456         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6457         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6458         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6459         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6460         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6461         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6462
6463         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6464         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6465         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6466         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6467         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6468         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6469         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6470         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6471         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6472         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6473         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6474         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6475         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6476         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6477 }
6478
6479 static void tg3_timer(unsigned long __opaque)
6480 {
6481         struct tg3 *tp = (struct tg3 *) __opaque;
6482
6483         if (tp->irq_sync)
6484                 goto restart_timer;
6485
6486         spin_lock(&tp->lock);
6487
6488         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6489                 /* All of this garbage is because when using non-tagged
6490                  * IRQ status the mailbox/status_block protocol the chip
6491                  * uses with the cpu is race prone.
6492                  */
6493                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6494                         tw32(GRC_LOCAL_CTRL,
6495                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6496                 } else {
6497                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6498                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6499                 }
6500
6501                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6502                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6503                         spin_unlock(&tp->lock);
6504                         schedule_work(&tp->reset_task);
6505                         return;
6506                 }
6507         }
6508
6509         /* This part only runs once per second. */
6510         if (!--tp->timer_counter) {
6511                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6512                         tg3_periodic_fetch_stats(tp);
6513
6514                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6515                         u32 mac_stat;
6516                         int phy_event;
6517
6518                         mac_stat = tr32(MAC_STATUS);
6519
6520                         phy_event = 0;
6521                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6522                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6523                                         phy_event = 1;
6524                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6525                                 phy_event = 1;
6526
6527                         if (phy_event)
6528                                 tg3_setup_phy(tp, 0);
6529                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6530                         u32 mac_stat = tr32(MAC_STATUS);
6531                         int need_setup = 0;
6532
6533                         if (netif_carrier_ok(tp->dev) &&
6534                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6535                                 need_setup = 1;
6536                         }
6537                         if (! netif_carrier_ok(tp->dev) &&
6538                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6539                                          MAC_STATUS_SIGNAL_DET))) {
6540                                 need_setup = 1;
6541                         }
6542                         if (need_setup) {
6543                                 tw32_f(MAC_MODE,
6544                                      (tp->mac_mode &
6545                                       ~MAC_MODE_PORT_MODE_MASK));
6546                                 udelay(40);
6547                                 tw32_f(MAC_MODE, tp->mac_mode);
6548                                 udelay(40);
6549                                 tg3_setup_phy(tp, 0);
6550                         }
6551                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6552                         tg3_serdes_parallel_detect(tp);
6553
6554                 tp->timer_counter = tp->timer_multiplier;
6555         }
6556
6557         /* Heartbeat is only sent once every 2 seconds.  */
6558         if (!--tp->asf_counter) {
6559                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6560                         u32 val;
6561
6562                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6563                                       FWCMD_NICDRV_ALIVE2);
6564                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6565                         /* 5 seconds timeout */
6566                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6567                         val = tr32(GRC_RX_CPU_EVENT);
6568                         val |= (1 << 14);
6569                         tw32(GRC_RX_CPU_EVENT, val);
6570                 }
6571                 tp->asf_counter = tp->asf_multiplier;
6572         }
6573
6574         spin_unlock(&tp->lock);
6575
6576 restart_timer:
6577         tp->timer.expires = jiffies + tp->timer_offset;
6578         add_timer(&tp->timer);
6579 }
6580
6581 static int tg3_request_irq(struct tg3 *tp)
6582 {
6583         irqreturn_t (*fn)(int, void *, struct pt_regs *);
6584         unsigned long flags;
6585         struct net_device *dev = tp->dev;
6586
6587         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6588                 fn = tg3_msi;
6589                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6590                         fn = tg3_msi_1shot;
6591                 flags = SA_SAMPLE_RANDOM;
6592         } else {
6593                 fn = tg3_interrupt;
6594                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6595                         fn = tg3_interrupt_tagged;
6596                 flags = SA_SHIRQ | SA_SAMPLE_RANDOM;
6597         }
6598         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6599 }
6600
6601 static int tg3_test_interrupt(struct tg3 *tp)
6602 {
6603         struct net_device *dev = tp->dev;
6604         int err, i;
6605         u32 int_mbox = 0;
6606
6607         if (!netif_running(dev))
6608                 return -ENODEV;
6609
6610         tg3_disable_ints(tp);
6611
6612         free_irq(tp->pdev->irq, dev);
6613
6614         err = request_irq(tp->pdev->irq, tg3_test_isr,
6615                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6616         if (err)
6617                 return err;
6618
6619         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6620         tg3_enable_ints(tp);
6621
6622         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6623                HOSTCC_MODE_NOW);
6624
6625         for (i = 0; i < 5; i++) {
6626                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6627                                         TG3_64BIT_REG_LOW);
6628                 if (int_mbox != 0)
6629                         break;
6630                 msleep(10);
6631         }
6632
6633         tg3_disable_ints(tp);
6634
6635         free_irq(tp->pdev->irq, dev);
6636
6637         err = tg3_request_irq(tp);
6638
6639         if (err)
6640                 return err;
6641
6642         if (int_mbox != 0)
6643                 return 0;
6644
6645         return -EIO;
6646 }
6647
6648 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6649  * successfully restored
6650  */
6651 static int tg3_test_msi(struct tg3 *tp)
6652 {
6653         struct net_device *dev = tp->dev;
6654         int err;
6655         u16 pci_cmd;
6656
6657         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6658                 return 0;
6659
6660         /* Turn off SERR reporting in case MSI terminates with Master
6661          * Abort.
6662          */
6663         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6664         pci_write_config_word(tp->pdev, PCI_COMMAND,
6665                               pci_cmd & ~PCI_COMMAND_SERR);
6666
6667         err = tg3_test_interrupt(tp);
6668
6669         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6670
6671         if (!err)
6672                 return 0;
6673
6674         /* other failures */
6675         if (err != -EIO)
6676                 return err;
6677
6678         /* MSI test failed, go back to INTx mode */
6679         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6680                "switching to INTx mode. Please report this failure to "
6681                "the PCI maintainer and include system chipset information.\n",
6682                        tp->dev->name);
6683
6684         free_irq(tp->pdev->irq, dev);
6685         pci_disable_msi(tp->pdev);
6686
6687         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6688
6689         err = tg3_request_irq(tp);
6690         if (err)
6691                 return err;
6692
6693         /* Need to reset the chip because the MSI cycle may have terminated
6694          * with Master Abort.
6695          */
6696         tg3_full_lock(tp, 1);
6697
6698         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6699         err = tg3_init_hw(tp);
6700
6701         tg3_full_unlock(tp);
6702
6703         if (err)
6704                 free_irq(tp->pdev->irq, dev);
6705
6706         return err;
6707 }
6708
6709 static int tg3_open(struct net_device *dev)
6710 {
6711         struct tg3 *tp = netdev_priv(dev);
6712         int err;
6713
6714         tg3_full_lock(tp, 0);
6715
6716         err = tg3_set_power_state(tp, PCI_D0);
6717         if (err)
6718                 return err;
6719
6720         tg3_disable_ints(tp);
6721         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6722
6723         tg3_full_unlock(tp);
6724
6725         /* The placement of this call is tied
6726          * to the setup and use of Host TX descriptors.
6727          */
6728         err = tg3_alloc_consistent(tp);
6729         if (err)
6730                 return err;
6731
6732         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6733             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6734             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
6735             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
6736               (tp->pdev_peer == tp->pdev))) {
6737                 /* All MSI supporting chips should support tagged
6738                  * status.  Assert that this is the case.
6739                  */
6740                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6741                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6742                                "Not using MSI.\n", tp->dev->name);
6743                 } else if (pci_enable_msi(tp->pdev) == 0) {
6744                         u32 msi_mode;
6745
6746                         msi_mode = tr32(MSGINT_MODE);
6747                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6748                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6749                 }
6750         }
6751         err = tg3_request_irq(tp);
6752
6753         if (err) {
6754                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6755                         pci_disable_msi(tp->pdev);
6756                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6757                 }
6758                 tg3_free_consistent(tp);
6759                 return err;
6760         }
6761
6762         tg3_full_lock(tp, 0);
6763
6764         err = tg3_init_hw(tp);
6765         if (err) {
6766                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6767                 tg3_free_rings(tp);
6768         } else {
6769                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6770                         tp->timer_offset = HZ;
6771                 else
6772                         tp->timer_offset = HZ / 10;
6773
6774                 BUG_ON(tp->timer_offset > HZ);
6775                 tp->timer_counter = tp->timer_multiplier =
6776                         (HZ / tp->timer_offset);
6777                 tp->asf_counter = tp->asf_multiplier =
6778                         ((HZ / tp->timer_offset) * 2);
6779
6780                 init_timer(&tp->timer);
6781                 tp->timer.expires = jiffies + tp->timer_offset;
6782                 tp->timer.data = (unsigned long) tp;
6783                 tp->timer.function = tg3_timer;
6784         }
6785
6786         tg3_full_unlock(tp);
6787
6788         if (err) {
6789                 free_irq(tp->pdev->irq, dev);
6790                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6791                         pci_disable_msi(tp->pdev);
6792                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6793                 }
6794                 tg3_free_consistent(tp);
6795                 return err;
6796         }
6797
6798         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6799                 err = tg3_test_msi(tp);
6800
6801                 if (err) {
6802                         tg3_full_lock(tp, 0);
6803
6804                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6805                                 pci_disable_msi(tp->pdev);
6806                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6807                         }
6808                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6809                         tg3_free_rings(tp);
6810                         tg3_free_consistent(tp);
6811
6812                         tg3_full_unlock(tp);
6813
6814                         return err;
6815                 }
6816
6817                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6818                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
6819                                 u32 val = tr32(0x7c04);
6820
6821                                 tw32(0x7c04, val | (1 << 29));
6822                         }
6823                 }
6824         }
6825
6826         tg3_full_lock(tp, 0);
6827
6828         add_timer(&tp->timer);
6829         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6830         tg3_enable_ints(tp);
6831
6832         tg3_full_unlock(tp);
6833
6834         netif_start_queue(dev);
6835
6836         return 0;
6837 }
6838
6839 #if 0
6840 /*static*/ void tg3_dump_state(struct tg3 *tp)
6841 {
6842         u32 val32, val32_2, val32_3, val32_4, val32_5;
6843         u16 val16;
6844         int i;
6845
6846         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6847         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6848         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6849                val16, val32);
6850
6851         /* MAC block */
6852         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6853                tr32(MAC_MODE), tr32(MAC_STATUS));
6854         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6855                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6856         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6857                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6858         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6859                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6860
6861         /* Send data initiator control block */
6862         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6863                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6864         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6865                tr32(SNDDATAI_STATSCTRL));
6866
6867         /* Send data completion control block */
6868         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6869
6870         /* Send BD ring selector block */
6871         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6872                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6873
6874         /* Send BD initiator control block */
6875         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6876                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6877
6878         /* Send BD completion control block */
6879         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6880
6881         /* Receive list placement control block */
6882         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6883                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6884         printk("       RCVLPC_STATSCTRL[%08x]\n",
6885                tr32(RCVLPC_STATSCTRL));
6886
6887         /* Receive data and receive BD initiator control block */
6888         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6889                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6890
6891         /* Receive data completion control block */
6892         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6893                tr32(RCVDCC_MODE));
6894
6895         /* Receive BD initiator control block */
6896         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6897                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6898
6899         /* Receive BD completion control block */
6900         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6901                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6902
6903         /* Receive list selector control block */
6904         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6905                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6906
6907         /* Mbuf cluster free block */
6908         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6909                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6910
6911         /* Host coalescing control block */
6912         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6913                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6914         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6915                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6916                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6917         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6918                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6919                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6920         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6921                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6922         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6923                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6924
6925         /* Memory arbiter control block */
6926         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6927                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6928
6929         /* Buffer manager control block */
6930         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6931                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6932         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6933                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6934         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6935                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6936                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6937                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6938
6939         /* Read DMA control block */
6940         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6941                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6942
6943         /* Write DMA control block */
6944         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6945                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6946
6947         /* DMA completion block */
6948         printk("DEBUG: DMAC_MODE[%08x]\n",
6949                tr32(DMAC_MODE));
6950
6951         /* GRC block */
6952         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6953                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6954         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6955                tr32(GRC_LOCAL_CTRL));
6956
6957         /* TG3_BDINFOs */
6958         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6959                tr32(RCVDBDI_JUMBO_BD + 0x0),
6960                tr32(RCVDBDI_JUMBO_BD + 0x4),
6961                tr32(RCVDBDI_JUMBO_BD + 0x8),
6962                tr32(RCVDBDI_JUMBO_BD + 0xc));
6963         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6964                tr32(RCVDBDI_STD_BD + 0x0),
6965                tr32(RCVDBDI_STD_BD + 0x4),
6966                tr32(RCVDBDI_STD_BD + 0x8),
6967                tr32(RCVDBDI_STD_BD + 0xc));
6968         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6969                tr32(RCVDBDI_MINI_BD + 0x0),
6970                tr32(RCVDBDI_MINI_BD + 0x4),
6971                tr32(RCVDBDI_MINI_BD + 0x8),
6972                tr32(RCVDBDI_MINI_BD + 0xc));
6973
6974         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6975         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6976         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6977         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6978         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6979                val32, val32_2, val32_3, val32_4);
6980
6981         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6982         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6983         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6984         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6985         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6986                val32, val32_2, val32_3, val32_4);
6987
6988         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6989         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6990         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6991         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6992         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6993         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6994                val32, val32_2, val32_3, val32_4, val32_5);
6995
6996         /* SW status block */
6997         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6998                tp->hw_status->status,
6999                tp->hw_status->status_tag,
7000                tp->hw_status->rx_jumbo_consumer,
7001                tp->hw_status->rx_consumer,
7002                tp->hw_status->rx_mini_consumer,
7003                tp->hw_status->idx[0].rx_producer,
7004                tp->hw_status->idx[0].tx_consumer);
7005
7006         /* SW statistics block */
7007         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7008                ((u32 *)tp->hw_stats)[0],
7009                ((u32 *)tp->hw_stats)[1],
7010                ((u32 *)tp->hw_stats)[2],
7011                ((u32 *)tp->hw_stats)[3]);
7012
7013         /* Mailboxes */
7014         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7015                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7016                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7017                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7018                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7019
7020         /* NIC side send descriptors. */
7021         for (i = 0; i < 6; i++) {
7022                 unsigned long txd;
7023
7024                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7025                         + (i * sizeof(struct tg3_tx_buffer_desc));
7026                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7027                        i,
7028                        readl(txd + 0x0), readl(txd + 0x4),
7029                        readl(txd + 0x8), readl(txd + 0xc));
7030         }
7031
7032         /* NIC side RX descriptors. */
7033         for (i = 0; i < 6; i++) {
7034                 unsigned long rxd;
7035
7036                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7037                         + (i * sizeof(struct tg3_rx_buffer_desc));
7038                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7039                        i,
7040                        readl(rxd + 0x0), readl(rxd + 0x4),
7041                        readl(rxd + 0x8), readl(rxd + 0xc));
7042                 rxd += (4 * sizeof(u32));
7043                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7044                        i,
7045                        readl(rxd + 0x0), readl(rxd + 0x4),
7046                        readl(rxd + 0x8), readl(rxd + 0xc));
7047         }
7048
7049         for (i = 0; i < 6; i++) {
7050                 unsigned long rxd;
7051
7052                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7053                         + (i * sizeof(struct tg3_rx_buffer_desc));
7054                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7055                        i,
7056                        readl(rxd + 0x0), readl(rxd + 0x4),
7057                        readl(rxd + 0x8), readl(rxd + 0xc));
7058                 rxd += (4 * sizeof(u32));
7059                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7060                        i,
7061                        readl(rxd + 0x0), readl(rxd + 0x4),
7062                        readl(rxd + 0x8), readl(rxd + 0xc));
7063         }
7064 }
7065 #endif
7066
7067 static struct net_device_stats *tg3_get_stats(struct net_device *);
7068 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7069
7070 static int tg3_close(struct net_device *dev)
7071 {
7072         struct tg3 *tp = netdev_priv(dev);
7073
7074         /* Calling flush_scheduled_work() may deadlock because
7075          * linkwatch_event() may be on the workqueue and it will try to get
7076          * the rtnl_lock which we are holding.
7077          */
7078         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7079                 msleep(1);
7080
7081         netif_stop_queue(dev);
7082
7083         del_timer_sync(&tp->timer);
7084
7085         tg3_full_lock(tp, 1);
7086 #if 0
7087         tg3_dump_state(tp);
7088 #endif
7089
7090         tg3_disable_ints(tp);
7091
7092         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7093         tg3_free_rings(tp);
7094         tp->tg3_flags &=
7095                 ~(TG3_FLAG_INIT_COMPLETE |
7096                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7097
7098         tg3_full_unlock(tp);
7099
7100         free_irq(tp->pdev->irq, dev);
7101         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7102                 pci_disable_msi(tp->pdev);
7103                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7104         }
7105
7106         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7107                sizeof(tp->net_stats_prev));
7108         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7109                sizeof(tp->estats_prev));
7110
7111         tg3_free_consistent(tp);
7112
7113         tg3_set_power_state(tp, PCI_D3hot);
7114
7115         netif_carrier_off(tp->dev);
7116
7117         return 0;
7118 }
7119
7120 static inline unsigned long get_stat64(tg3_stat64_t *val)
7121 {
7122         unsigned long ret;
7123
7124 #if (BITS_PER_LONG == 32)
7125         ret = val->low;
7126 #else
7127         ret = ((u64)val->high << 32) | ((u64)val->low);
7128 #endif
7129         return ret;
7130 }
7131
7132 static unsigned long calc_crc_errors(struct tg3 *tp)
7133 {
7134         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7135
7136         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7137             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7138              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7139                 u32 val;
7140
7141                 spin_lock_bh(&tp->lock);
7142                 if (!tg3_readphy(tp, 0x1e, &val)) {
7143                         tg3_writephy(tp, 0x1e, val | 0x8000);
7144                         tg3_readphy(tp, 0x14, &val);
7145                 } else
7146                         val = 0;
7147                 spin_unlock_bh(&tp->lock);
7148
7149                 tp->phy_crc_errors += val;
7150
7151                 return tp->phy_crc_errors;
7152         }
7153
7154         return get_stat64(&hw_stats->rx_fcs_errors);
7155 }
7156
7157 #define ESTAT_ADD(member) \
7158         estats->member =        old_estats->member + \
7159                                 get_stat64(&hw_stats->member)
7160
7161 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7162 {
7163         struct tg3_ethtool_stats *estats = &tp->estats;
7164         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7165         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7166
7167         if (!hw_stats)
7168                 return old_estats;
7169
7170         ESTAT_ADD(rx_octets);
7171         ESTAT_ADD(rx_fragments);
7172         ESTAT_ADD(rx_ucast_packets);
7173         ESTAT_ADD(rx_mcast_packets);
7174         ESTAT_ADD(rx_bcast_packets);
7175         ESTAT_ADD(rx_fcs_errors);
7176         ESTAT_ADD(rx_align_errors);
7177         ESTAT_ADD(rx_xon_pause_rcvd);
7178         ESTAT_ADD(rx_xoff_pause_rcvd);
7179         ESTAT_ADD(rx_mac_ctrl_rcvd);
7180         ESTAT_ADD(rx_xoff_entered);
7181         ESTAT_ADD(rx_frame_too_long_errors);
7182         ESTAT_ADD(rx_jabbers);
7183         ESTAT_ADD(rx_undersize_packets);
7184         ESTAT_ADD(rx_in_length_errors);
7185         ESTAT_ADD(rx_out_length_errors);
7186         ESTAT_ADD(rx_64_or_less_octet_packets);
7187         ESTAT_ADD(rx_65_to_127_octet_packets);
7188         ESTAT_ADD(rx_128_to_255_octet_packets);
7189         ESTAT_ADD(rx_256_to_511_octet_packets);
7190         ESTAT_ADD(rx_512_to_1023_octet_packets);
7191         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7192         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7193         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7194         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7195         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7196
7197         ESTAT_ADD(tx_octets);
7198         ESTAT_ADD(tx_collisions);
7199         ESTAT_ADD(tx_xon_sent);
7200         ESTAT_ADD(tx_xoff_sent);
7201         ESTAT_ADD(tx_flow_control);
7202         ESTAT_ADD(tx_mac_errors);
7203         ESTAT_ADD(tx_single_collisions);
7204         ESTAT_ADD(tx_mult_collisions);
7205         ESTAT_ADD(tx_deferred);
7206         ESTAT_ADD(tx_excessive_collisions);
7207         ESTAT_ADD(tx_late_collisions);
7208         ESTAT_ADD(tx_collide_2times);
7209         ESTAT_ADD(tx_collide_3times);
7210         ESTAT_ADD(tx_collide_4times);
7211         ESTAT_ADD(tx_collide_5times);
7212         ESTAT_ADD(tx_collide_6times);
7213         ESTAT_ADD(tx_collide_7times);
7214         ESTAT_ADD(tx_collide_8times);
7215         ESTAT_ADD(tx_collide_9times);
7216         ESTAT_ADD(tx_collide_10times);
7217         ESTAT_ADD(tx_collide_11times);
7218         ESTAT_ADD(tx_collide_12times);
7219         ESTAT_ADD(tx_collide_13times);
7220         ESTAT_ADD(tx_collide_14times);
7221         ESTAT_ADD(tx_collide_15times);
7222         ESTAT_ADD(tx_ucast_packets);
7223         ESTAT_ADD(tx_mcast_packets);
7224         ESTAT_ADD(tx_bcast_packets);
7225         ESTAT_ADD(tx_carrier_sense_errors);
7226         ESTAT_ADD(tx_discards);
7227         ESTAT_ADD(tx_errors);
7228
7229         ESTAT_ADD(dma_writeq_full);
7230         ESTAT_ADD(dma_write_prioq_full);
7231         ESTAT_ADD(rxbds_empty);
7232         ESTAT_ADD(rx_discards);
7233         ESTAT_ADD(rx_errors);
7234         ESTAT_ADD(rx_threshold_hit);
7235
7236         ESTAT_ADD(dma_readq_full);
7237         ESTAT_ADD(dma_read_prioq_full);
7238         ESTAT_ADD(tx_comp_queue_full);
7239
7240         ESTAT_ADD(ring_set_send_prod_index);
7241         ESTAT_ADD(ring_status_update);
7242         ESTAT_ADD(nic_irqs);
7243         ESTAT_ADD(nic_avoided_irqs);
7244         ESTAT_ADD(nic_tx_threshold_hit);
7245
7246         return estats;
7247 }
7248
7249 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7250 {
7251         struct tg3 *tp = netdev_priv(dev);
7252         struct net_device_stats *stats = &tp->net_stats;
7253         struct net_device_stats *old_stats = &tp->net_stats_prev;
7254         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7255
7256         if (!hw_stats)
7257                 return old_stats;
7258
7259         stats->rx_packets = old_stats->rx_packets +
7260                 get_stat64(&hw_stats->rx_ucast_packets) +
7261                 get_stat64(&hw_stats->rx_mcast_packets) +
7262                 get_stat64(&hw_stats->rx_bcast_packets);
7263
7264         stats->tx_packets = old_stats->tx_packets +
7265                 get_stat64(&hw_stats->tx_ucast_packets) +
7266                 get_stat64(&hw_stats->tx_mcast_packets) +
7267                 get_stat64(&hw_stats->tx_bcast_packets);
7268
7269         stats->rx_bytes = old_stats->rx_bytes +
7270                 get_stat64(&hw_stats->rx_octets);
7271         stats->tx_bytes = old_stats->tx_bytes +
7272                 get_stat64(&hw_stats->tx_octets);
7273
7274         stats->rx_errors = old_stats->rx_errors +
7275                 get_stat64(&hw_stats->rx_errors);
7276         stats->tx_errors = old_stats->tx_errors +
7277                 get_stat64(&hw_stats->tx_errors) +
7278                 get_stat64(&hw_stats->tx_mac_errors) +
7279                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7280                 get_stat64(&hw_stats->tx_discards);
7281
7282         stats->multicast = old_stats->multicast +
7283                 get_stat64(&hw_stats->rx_mcast_packets);
7284         stats->collisions = old_stats->collisions +
7285                 get_stat64(&hw_stats->tx_collisions);
7286
7287         stats->rx_length_errors = old_stats->rx_length_errors +
7288                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7289                 get_stat64(&hw_stats->rx_undersize_packets);
7290
7291         stats->rx_over_errors = old_stats->rx_over_errors +
7292                 get_stat64(&hw_stats->rxbds_empty);
7293         stats->rx_frame_errors = old_stats->rx_frame_errors +
7294                 get_stat64(&hw_stats->rx_align_errors);
7295         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7296                 get_stat64(&hw_stats->tx_discards);
7297         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7298                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7299
7300         stats->rx_crc_errors = old_stats->rx_crc_errors +
7301                 calc_crc_errors(tp);
7302
7303         stats->rx_missed_errors = old_stats->rx_missed_errors +
7304                 get_stat64(&hw_stats->rx_discards);
7305
7306         return stats;
7307 }
7308
7309 static inline u32 calc_crc(unsigned char *buf, int len)
7310 {
7311         u32 reg;
7312         u32 tmp;
7313         int j, k;
7314
7315         reg = 0xffffffff;
7316
7317         for (j = 0; j < len; j++) {
7318                 reg ^= buf[j];
7319
7320                 for (k = 0; k < 8; k++) {
7321                         tmp = reg & 0x01;
7322
7323                         reg >>= 1;
7324
7325                         if (tmp) {
7326                                 reg ^= 0xedb88320;
7327                         }
7328                 }
7329         }
7330
7331         return ~reg;
7332 }
7333
7334 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7335 {
7336         /* accept or reject all multicast frames */
7337         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7338         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7339         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7340         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7341 }
7342
7343 static void __tg3_set_rx_mode(struct net_device *dev)
7344 {
7345         struct tg3 *tp = netdev_priv(dev);
7346         u32 rx_mode;
7347
7348         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7349                                   RX_MODE_KEEP_VLAN_TAG);
7350
7351         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7352          * flag clear.
7353          */
7354 #if TG3_VLAN_TAG_USED
7355         if (!tp->vlgrp &&
7356             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7357                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7358 #else
7359         /* By definition, VLAN is disabled always in this
7360          * case.
7361          */
7362         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7363                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7364 #endif
7365
7366         if (dev->flags & IFF_PROMISC) {
7367                 /* Promiscuous mode. */
7368                 rx_mode |= RX_MODE_PROMISC;
7369         } else if (dev->flags & IFF_ALLMULTI) {
7370                 /* Accept all multicast. */
7371                 tg3_set_multi (tp, 1);
7372         } else if (dev->mc_count < 1) {
7373                 /* Reject all multicast. */
7374                 tg3_set_multi (tp, 0);
7375         } else {
7376                 /* Accept one or more multicast(s). */
7377                 struct dev_mc_list *mclist;
7378                 unsigned int i;
7379                 u32 mc_filter[4] = { 0, };
7380                 u32 regidx;
7381                 u32 bit;
7382                 u32 crc;
7383
7384                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7385                      i++, mclist = mclist->next) {
7386
7387                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7388                         bit = ~crc & 0x7f;
7389                         regidx = (bit & 0x60) >> 5;
7390                         bit &= 0x1f;
7391                         mc_filter[regidx] |= (1 << bit);
7392                 }
7393
7394                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7395                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7396                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7397                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7398         }
7399
7400         if (rx_mode != tp->rx_mode) {
7401                 tp->rx_mode = rx_mode;
7402                 tw32_f(MAC_RX_MODE, rx_mode);
7403                 udelay(10);
7404         }
7405 }
7406
7407 static void tg3_set_rx_mode(struct net_device *dev)
7408 {
7409         struct tg3 *tp = netdev_priv(dev);
7410
7411         if (!netif_running(dev))
7412                 return;
7413
7414         tg3_full_lock(tp, 0);
7415         __tg3_set_rx_mode(dev);
7416         tg3_full_unlock(tp);
7417 }
7418
7419 #define TG3_REGDUMP_LEN         (32 * 1024)
7420
7421 static int tg3_get_regs_len(struct net_device *dev)
7422 {
7423         return TG3_REGDUMP_LEN;
7424 }
7425
7426 static void tg3_get_regs(struct net_device *dev,
7427                 struct ethtool_regs *regs, void *_p)
7428 {
7429         u32 *p = _p;
7430         struct tg3 *tp = netdev_priv(dev);
7431         u8 *orig_p = _p;
7432         int i;
7433
7434         regs->version = 0;
7435
7436         memset(p, 0, TG3_REGDUMP_LEN);
7437
7438         if (tp->link_config.phy_is_low_power)
7439                 return;
7440
7441         tg3_full_lock(tp, 0);
7442
7443 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7444 #define GET_REG32_LOOP(base,len)                \
7445 do {    p = (u32 *)(orig_p + (base));           \
7446         for (i = 0; i < len; i += 4)            \
7447                 __GET_REG32((base) + i);        \
7448 } while (0)
7449 #define GET_REG32_1(reg)                        \
7450 do {    p = (u32 *)(orig_p + (reg));            \
7451         __GET_REG32((reg));                     \
7452 } while (0)
7453
7454         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7455         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7456         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7457         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7458         GET_REG32_1(SNDDATAC_MODE);
7459         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7460         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7461         GET_REG32_1(SNDBDC_MODE);
7462         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7463         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7464         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7465         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7466         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7467         GET_REG32_1(RCVDCC_MODE);
7468         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7469         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7470         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7471         GET_REG32_1(MBFREE_MODE);
7472         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7473         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7474         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7475         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7476         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7477         GET_REG32_1(RX_CPU_MODE);
7478         GET_REG32_1(RX_CPU_STATE);
7479         GET_REG32_1(RX_CPU_PGMCTR);
7480         GET_REG32_1(RX_CPU_HWBKPT);
7481         GET_REG32_1(TX_CPU_MODE);
7482         GET_REG32_1(TX_CPU_STATE);
7483         GET_REG32_1(TX_CPU_PGMCTR);
7484         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7485         GET_REG32_LOOP(FTQ_RESET, 0x120);
7486         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7487         GET_REG32_1(DMAC_MODE);
7488         GET_REG32_LOOP(GRC_MODE, 0x4c);
7489         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7490                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7491
7492 #undef __GET_REG32
7493 #undef GET_REG32_LOOP
7494 #undef GET_REG32_1
7495
7496         tg3_full_unlock(tp);
7497 }
7498
7499 static int tg3_get_eeprom_len(struct net_device *dev)
7500 {
7501         struct tg3 *tp = netdev_priv(dev);
7502
7503         return tp->nvram_size;
7504 }
7505
7506 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7507 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7508
7509 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7510 {
7511         struct tg3 *tp = netdev_priv(dev);
7512         int ret;
7513         u8  *pd;
7514         u32 i, offset, len, val, b_offset, b_count;
7515
7516         if (tp->link_config.phy_is_low_power)
7517                 return -EAGAIN;
7518
7519         offset = eeprom->offset;
7520         len = eeprom->len;
7521         eeprom->len = 0;
7522
7523         eeprom->magic = TG3_EEPROM_MAGIC;
7524
7525         if (offset & 3) {
7526                 /* adjustments to start on required 4 byte boundary */
7527                 b_offset = offset & 3;
7528                 b_count = 4 - b_offset;
7529                 if (b_count > len) {
7530                         /* i.e. offset=1 len=2 */
7531                         b_count = len;
7532                 }
7533                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7534                 if (ret)
7535                         return ret;
7536                 val = cpu_to_le32(val);
7537                 memcpy(data, ((char*)&val) + b_offset, b_count);
7538                 len -= b_count;
7539                 offset += b_count;
7540                 eeprom->len += b_count;
7541         }
7542
7543         /* read bytes upto the last 4 byte boundary */
7544         pd = &data[eeprom->len];
7545         for (i = 0; i < (len - (len & 3)); i += 4) {
7546                 ret = tg3_nvram_read(tp, offset + i, &val);
7547                 if (ret) {
7548                         eeprom->len += i;
7549                         return ret;
7550                 }
7551                 val = cpu_to_le32(val);
7552                 memcpy(pd + i, &val, 4);
7553         }
7554         eeprom->len += i;
7555
7556         if (len & 3) {
7557                 /* read last bytes not ending on 4 byte boundary */
7558                 pd = &data[eeprom->len];
7559                 b_count = len & 3;
7560                 b_offset = offset + len - b_count;
7561                 ret = tg3_nvram_read(tp, b_offset, &val);
7562                 if (ret)
7563                         return ret;
7564                 val = cpu_to_le32(val);
7565                 memcpy(pd, ((char*)&val), b_count);
7566                 eeprom->len += b_count;
7567         }
7568         return 0;
7569 }
7570
7571 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7572
7573 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7574 {
7575         struct tg3 *tp = netdev_priv(dev);
7576         int ret;
7577         u32 offset, len, b_offset, odd_len, start, end;
7578         u8 *buf;
7579
7580         if (tp->link_config.phy_is_low_power)
7581                 return -EAGAIN;
7582
7583         if (eeprom->magic != TG3_EEPROM_MAGIC)
7584                 return -EINVAL;
7585
7586         offset = eeprom->offset;
7587         len = eeprom->len;
7588
7589         if ((b_offset = (offset & 3))) {
7590                 /* adjustments to start on required 4 byte boundary */
7591                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7592                 if (ret)
7593                         return ret;
7594                 start = cpu_to_le32(start);
7595                 len += b_offset;
7596                 offset &= ~3;
7597                 if (len < 4)
7598                         len = 4;
7599         }
7600
7601         odd_len = 0;
7602         if (len & 3) {
7603                 /* adjustments to end on required 4 byte boundary */
7604                 odd_len = 1;
7605                 len = (len + 3) & ~3;
7606                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7607                 if (ret)
7608                         return ret;
7609                 end = cpu_to_le32(end);
7610         }
7611
7612         buf = data;
7613         if (b_offset || odd_len) {
7614                 buf = kmalloc(len, GFP_KERNEL);
7615                 if (buf == 0)
7616                         return -ENOMEM;
7617                 if (b_offset)
7618                         memcpy(buf, &start, 4);
7619                 if (odd_len)
7620                         memcpy(buf+len-4, &end, 4);
7621                 memcpy(buf + b_offset, data, eeprom->len);
7622         }
7623
7624         ret = tg3_nvram_write_block(tp, offset, len, buf);
7625
7626         if (buf != data)
7627                 kfree(buf);
7628
7629         return ret;
7630 }
7631
7632 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7633 {
7634         struct tg3 *tp = netdev_priv(dev);
7635
7636         cmd->supported = (SUPPORTED_Autoneg);
7637
7638         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7639                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7640                                    SUPPORTED_1000baseT_Full);
7641
7642         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
7643                 cmd->supported |= (SUPPORTED_100baseT_Half |
7644                                   SUPPORTED_100baseT_Full |
7645                                   SUPPORTED_10baseT_Half |
7646                                   SUPPORTED_10baseT_Full |
7647                                   SUPPORTED_MII);
7648         else
7649                 cmd->supported |= SUPPORTED_FIBRE;
7650
7651         cmd->advertising = tp->link_config.advertising;
7652         if (netif_running(dev)) {
7653                 cmd->speed = tp->link_config.active_speed;
7654                 cmd->duplex = tp->link_config.active_duplex;
7655         }
7656         cmd->port = 0;
7657         cmd->phy_address = PHY_ADDR;
7658         cmd->transceiver = 0;
7659         cmd->autoneg = tp->link_config.autoneg;
7660         cmd->maxtxpkt = 0;
7661         cmd->maxrxpkt = 0;
7662         return 0;
7663 }
7664
7665 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7666 {
7667         struct tg3 *tp = netdev_priv(dev);
7668
7669         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7670                 /* These are the only valid advertisement bits allowed.  */
7671                 if (cmd->autoneg == AUTONEG_ENABLE &&
7672                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7673                                           ADVERTISED_1000baseT_Full |
7674                                           ADVERTISED_Autoneg |
7675                                           ADVERTISED_FIBRE)))
7676                         return -EINVAL;
7677                 /* Fiber can only do SPEED_1000.  */
7678                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7679                          (cmd->speed != SPEED_1000))
7680                         return -EINVAL;
7681         /* Copper cannot force SPEED_1000.  */
7682         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7683                    (cmd->speed == SPEED_1000))
7684                 return -EINVAL;
7685         else if ((cmd->speed == SPEED_1000) &&
7686                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7687                 return -EINVAL;
7688
7689         tg3_full_lock(tp, 0);
7690
7691         tp->link_config.autoneg = cmd->autoneg;
7692         if (cmd->autoneg == AUTONEG_ENABLE) {
7693                 tp->link_config.advertising = cmd->advertising;
7694                 tp->link_config.speed = SPEED_INVALID;
7695                 tp->link_config.duplex = DUPLEX_INVALID;
7696         } else {
7697                 tp->link_config.advertising = 0;
7698                 tp->link_config.speed = cmd->speed;
7699                 tp->link_config.duplex = cmd->duplex;
7700         }
7701
7702         if (netif_running(dev))
7703                 tg3_setup_phy(tp, 1);
7704
7705         tg3_full_unlock(tp);
7706
7707         return 0;
7708 }
7709
7710 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7711 {
7712         struct tg3 *tp = netdev_priv(dev);
7713
7714         strcpy(info->driver, DRV_MODULE_NAME);
7715         strcpy(info->version, DRV_MODULE_VERSION);
7716         strcpy(info->fw_version, tp->fw_ver);
7717         strcpy(info->bus_info, pci_name(tp->pdev));
7718 }
7719
7720 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7721 {
7722         struct tg3 *tp = netdev_priv(dev);
7723
7724         wol->supported = WAKE_MAGIC;
7725         wol->wolopts = 0;
7726         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7727                 wol->wolopts = WAKE_MAGIC;
7728         memset(&wol->sopass, 0, sizeof(wol->sopass));
7729 }
7730
7731 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7732 {
7733         struct tg3 *tp = netdev_priv(dev);
7734
7735         if (wol->wolopts & ~WAKE_MAGIC)
7736                 return -EINVAL;
7737         if ((wol->wolopts & WAKE_MAGIC) &&
7738             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7739             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7740                 return -EINVAL;
7741
7742         spin_lock_bh(&tp->lock);
7743         if (wol->wolopts & WAKE_MAGIC)
7744                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7745         else
7746                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7747         spin_unlock_bh(&tp->lock);
7748
7749         return 0;
7750 }
7751
7752 static u32 tg3_get_msglevel(struct net_device *dev)
7753 {
7754         struct tg3 *tp = netdev_priv(dev);
7755         return tp->msg_enable;
7756 }
7757
7758 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7759 {
7760         struct tg3 *tp = netdev_priv(dev);
7761         tp->msg_enable = value;
7762 }
7763
7764 #if TG3_TSO_SUPPORT != 0
7765 static int tg3_set_tso(struct net_device *dev, u32 value)
7766 {
7767         struct tg3 *tp = netdev_priv(dev);
7768
7769         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7770                 if (value)
7771                         return -EINVAL;
7772                 return 0;
7773         }
7774         return ethtool_op_set_tso(dev, value);
7775 }
7776 #endif
7777
7778 static int tg3_nway_reset(struct net_device *dev)
7779 {
7780         struct tg3 *tp = netdev_priv(dev);
7781         u32 bmcr;
7782         int r;
7783
7784         if (!netif_running(dev))
7785                 return -EAGAIN;
7786
7787         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7788                 return -EINVAL;
7789
7790         spin_lock_bh(&tp->lock);
7791         r = -EINVAL;
7792         tg3_readphy(tp, MII_BMCR, &bmcr);
7793         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7794             ((bmcr & BMCR_ANENABLE) ||
7795              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7796                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7797                                            BMCR_ANENABLE);
7798                 r = 0;
7799         }
7800         spin_unlock_bh(&tp->lock);
7801
7802         return r;
7803 }
7804
7805 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7806 {
7807         struct tg3 *tp = netdev_priv(dev);
7808
7809         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7810         ering->rx_mini_max_pending = 0;
7811         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7812                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7813         else
7814                 ering->rx_jumbo_max_pending = 0;
7815
7816         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
7817
7818         ering->rx_pending = tp->rx_pending;
7819         ering->rx_mini_pending = 0;
7820         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7821                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7822         else
7823                 ering->rx_jumbo_pending = 0;
7824
7825         ering->tx_pending = tp->tx_pending;
7826 }
7827
7828 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7829 {
7830         struct tg3 *tp = netdev_priv(dev);
7831         int irq_sync = 0;
7832
7833         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7834             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7835             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7836                 return -EINVAL;
7837
7838         if (netif_running(dev)) {
7839                 tg3_netif_stop(tp);
7840                 irq_sync = 1;
7841         }
7842
7843         tg3_full_lock(tp, irq_sync);
7844
7845         tp->rx_pending = ering->rx_pending;
7846
7847         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7848             tp->rx_pending > 63)
7849                 tp->rx_pending = 63;
7850         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7851         tp->tx_pending = ering->tx_pending;
7852
7853         if (netif_running(dev)) {
7854                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7855                 tg3_init_hw(tp);
7856                 tg3_netif_start(tp);
7857         }
7858
7859         tg3_full_unlock(tp);
7860
7861         return 0;
7862 }
7863
7864 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7865 {
7866         struct tg3 *tp = netdev_priv(dev);
7867
7868         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7869         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7870         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7871 }
7872
7873 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7874 {
7875         struct tg3 *tp = netdev_priv(dev);
7876         int irq_sync = 0;
7877
7878         if (netif_running(dev)) {
7879                 tg3_netif_stop(tp);
7880                 irq_sync = 1;
7881         }
7882
7883         tg3_full_lock(tp, irq_sync);
7884
7885         if (epause->autoneg)
7886                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7887         else
7888                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7889         if (epause->rx_pause)
7890                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7891         else
7892                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7893         if (epause->tx_pause)
7894                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7895         else
7896                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7897
7898         if (netif_running(dev)) {
7899                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7900                 tg3_init_hw(tp);
7901                 tg3_netif_start(tp);
7902         }
7903
7904         tg3_full_unlock(tp);
7905
7906         return 0;
7907 }
7908
7909 static u32 tg3_get_rx_csum(struct net_device *dev)
7910 {
7911         struct tg3 *tp = netdev_priv(dev);
7912         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7913 }
7914
7915 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7916 {
7917         struct tg3 *tp = netdev_priv(dev);
7918
7919         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7920                 if (data != 0)
7921                         return -EINVAL;
7922                 return 0;
7923         }
7924
7925         spin_lock_bh(&tp->lock);
7926         if (data)
7927                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7928         else
7929                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7930         spin_unlock_bh(&tp->lock);
7931
7932         return 0;
7933 }
7934
7935 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7936 {
7937         struct tg3 *tp = netdev_priv(dev);
7938
7939         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7940                 if (data != 0)
7941                         return -EINVAL;
7942                 return 0;
7943         }
7944
7945         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7946             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
7947                 ethtool_op_set_tx_hw_csum(dev, data);
7948         else
7949                 ethtool_op_set_tx_csum(dev, data);
7950
7951         return 0;
7952 }
7953
7954 static int tg3_get_stats_count (struct net_device *dev)
7955 {
7956         return TG3_NUM_STATS;
7957 }
7958
7959 static int tg3_get_test_count (struct net_device *dev)
7960 {
7961         return TG3_NUM_TEST;
7962 }
7963
7964 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7965 {
7966         switch (stringset) {
7967         case ETH_SS_STATS:
7968                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7969                 break;
7970         case ETH_SS_TEST:
7971                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7972                 break;
7973         default:
7974                 WARN_ON(1);     /* we need a WARN() */
7975                 break;
7976         }
7977 }
7978
7979 static int tg3_phys_id(struct net_device *dev, u32 data)
7980 {
7981         struct tg3 *tp = netdev_priv(dev);
7982         int i;
7983
7984         if (!netif_running(tp->dev))
7985                 return -EAGAIN;
7986
7987         if (data == 0)
7988                 data = 2;
7989
7990         for (i = 0; i < (data * 2); i++) {
7991                 if ((i % 2) == 0)
7992                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7993                                            LED_CTRL_1000MBPS_ON |
7994                                            LED_CTRL_100MBPS_ON |
7995                                            LED_CTRL_10MBPS_ON |
7996                                            LED_CTRL_TRAFFIC_OVERRIDE |
7997                                            LED_CTRL_TRAFFIC_BLINK |
7998                                            LED_CTRL_TRAFFIC_LED);
7999
8000                 else
8001                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8002                                            LED_CTRL_TRAFFIC_OVERRIDE);
8003
8004                 if (msleep_interruptible(500))
8005                         break;
8006         }
8007         tw32(MAC_LED_CTRL, tp->led_ctrl);
8008         return 0;
8009 }
8010
8011 static void tg3_get_ethtool_stats (struct net_device *dev,
8012                                    struct ethtool_stats *estats, u64 *tmp_stats)
8013 {
8014         struct tg3 *tp = netdev_priv(dev);
8015         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8016 }
8017
8018 #define NVRAM_TEST_SIZE 0x100
8019 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8020
8021 static int tg3_test_nvram(struct tg3 *tp)
8022 {
8023         u32 *buf, csum, magic;
8024         int i, j, err = 0, size;
8025
8026         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8027                 return -EIO;
8028
8029         if (magic == TG3_EEPROM_MAGIC)
8030                 size = NVRAM_TEST_SIZE;
8031         else if ((magic & 0xff000000) == 0xa5000000) {
8032                 if ((magic & 0xe00000) == 0x200000)
8033                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8034                 else
8035                         return 0;
8036         } else
8037                 return -EIO;
8038
8039         buf = kmalloc(size, GFP_KERNEL);
8040         if (buf == NULL)
8041                 return -ENOMEM;
8042
8043         err = -EIO;
8044         for (i = 0, j = 0; i < size; i += 4, j++) {
8045                 u32 val;
8046
8047                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8048                         break;
8049                 buf[j] = cpu_to_le32(val);
8050         }
8051         if (i < size)
8052                 goto out;
8053
8054         /* Selfboot format */
8055         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
8056                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8057
8058                 for (i = 0; i < size; i++)
8059                         csum8 += buf8[i];
8060
8061                 if (csum8 == 0) {
8062                         err = 0;
8063                         goto out;
8064                 }
8065
8066                 err = -EIO;
8067                 goto out;
8068         }
8069
8070         /* Bootstrap checksum at offset 0x10 */
8071         csum = calc_crc((unsigned char *) buf, 0x10);
8072         if(csum != cpu_to_le32(buf[0x10/4]))
8073                 goto out;
8074
8075         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8076         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8077         if (csum != cpu_to_le32(buf[0xfc/4]))
8078                  goto out;
8079
8080         err = 0;
8081
8082 out:
8083         kfree(buf);
8084         return err;
8085 }
8086
8087 #define TG3_SERDES_TIMEOUT_SEC  2
8088 #define TG3_COPPER_TIMEOUT_SEC  6
8089
8090 static int tg3_test_link(struct tg3 *tp)
8091 {
8092         int i, max;
8093
8094         if (!netif_running(tp->dev))
8095                 return -ENODEV;
8096
8097         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8098                 max = TG3_SERDES_TIMEOUT_SEC;
8099         else
8100                 max = TG3_COPPER_TIMEOUT_SEC;
8101
8102         for (i = 0; i < max; i++) {
8103                 if (netif_carrier_ok(tp->dev))
8104                         return 0;
8105
8106                 if (msleep_interruptible(1000))
8107                         break;
8108         }
8109
8110         return -EIO;
8111 }
8112
8113 /* Only test the commonly used registers */
8114 static int tg3_test_registers(struct tg3 *tp)
8115 {
8116         int i, is_5705;
8117         u32 offset, read_mask, write_mask, val, save_val, read_val;
8118         static struct {
8119                 u16 offset;
8120                 u16 flags;
8121 #define TG3_FL_5705     0x1
8122 #define TG3_FL_NOT_5705 0x2
8123 #define TG3_FL_NOT_5788 0x4
8124                 u32 read_mask;
8125                 u32 write_mask;
8126         } reg_tbl[] = {
8127                 /* MAC Control Registers */
8128                 { MAC_MODE, TG3_FL_NOT_5705,
8129                         0x00000000, 0x00ef6f8c },
8130                 { MAC_MODE, TG3_FL_5705,
8131                         0x00000000, 0x01ef6b8c },
8132                 { MAC_STATUS, TG3_FL_NOT_5705,
8133                         0x03800107, 0x00000000 },
8134                 { MAC_STATUS, TG3_FL_5705,
8135                         0x03800100, 0x00000000 },
8136                 { MAC_ADDR_0_HIGH, 0x0000,
8137                         0x00000000, 0x0000ffff },
8138                 { MAC_ADDR_0_LOW, 0x0000,
8139                         0x00000000, 0xffffffff },
8140                 { MAC_RX_MTU_SIZE, 0x0000,
8141                         0x00000000, 0x0000ffff },
8142                 { MAC_TX_MODE, 0x0000,
8143                         0x00000000, 0x00000070 },
8144                 { MAC_TX_LENGTHS, 0x0000,
8145                         0x00000000, 0x00003fff },
8146                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8147                         0x00000000, 0x000007fc },
8148                 { MAC_RX_MODE, TG3_FL_5705,
8149                         0x00000000, 0x000007dc },
8150                 { MAC_HASH_REG_0, 0x0000,
8151                         0x00000000, 0xffffffff },
8152                 { MAC_HASH_REG_1, 0x0000,
8153                         0x00000000, 0xffffffff },
8154                 { MAC_HASH_REG_2, 0x0000,
8155                         0x00000000, 0xffffffff },
8156                 { MAC_HASH_REG_3, 0x0000,
8157                         0x00000000, 0xffffffff },
8158
8159                 /* Receive Data and Receive BD Initiator Control Registers. */
8160                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8161                         0x00000000, 0xffffffff },
8162                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8163                         0x00000000, 0xffffffff },
8164                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8165                         0x00000000, 0x00000003 },
8166                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8167                         0x00000000, 0xffffffff },
8168                 { RCVDBDI_STD_BD+0, 0x0000,
8169                         0x00000000, 0xffffffff },
8170                 { RCVDBDI_STD_BD+4, 0x0000,
8171                         0x00000000, 0xffffffff },
8172                 { RCVDBDI_STD_BD+8, 0x0000,
8173                         0x00000000, 0xffff0002 },
8174                 { RCVDBDI_STD_BD+0xc, 0x0000,
8175                         0x00000000, 0xffffffff },
8176
8177                 /* Receive BD Initiator Control Registers. */
8178                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8179                         0x00000000, 0xffffffff },
8180                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8181                         0x00000000, 0x000003ff },
8182                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8183                         0x00000000, 0xffffffff },
8184
8185                 /* Host Coalescing Control Registers. */
8186                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8187                         0x00000000, 0x00000004 },
8188                 { HOSTCC_MODE, TG3_FL_5705,
8189                         0x00000000, 0x000000f6 },
8190                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8191                         0x00000000, 0xffffffff },
8192                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8193                         0x00000000, 0x000003ff },
8194                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8195                         0x00000000, 0xffffffff },
8196                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8197                         0x00000000, 0x000003ff },
8198                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8199                         0x00000000, 0xffffffff },
8200                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8201                         0x00000000, 0x000000ff },
8202                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8203                         0x00000000, 0xffffffff },
8204                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8205                         0x00000000, 0x000000ff },
8206                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8207                         0x00000000, 0xffffffff },
8208                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8209                         0x00000000, 0xffffffff },
8210                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8211                         0x00000000, 0xffffffff },
8212                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8213                         0x00000000, 0x000000ff },
8214                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8215                         0x00000000, 0xffffffff },
8216                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8217                         0x00000000, 0x000000ff },
8218                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8219                         0x00000000, 0xffffffff },
8220                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8221                         0x00000000, 0xffffffff },
8222                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8223                         0x00000000, 0xffffffff },
8224                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8225                         0x00000000, 0xffffffff },
8226                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8227                         0x00000000, 0xffffffff },
8228                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8229                         0xffffffff, 0x00000000 },
8230                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8231                         0xffffffff, 0x00000000 },
8232
8233                 /* Buffer Manager Control Registers. */
8234                 { BUFMGR_MB_POOL_ADDR, 0x0000,
8235                         0x00000000, 0x007fff80 },
8236                 { BUFMGR_MB_POOL_SIZE, 0x0000,
8237                         0x00000000, 0x007fffff },
8238                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8239                         0x00000000, 0x0000003f },
8240                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8241                         0x00000000, 0x000001ff },
8242                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8243                         0x00000000, 0x000001ff },
8244                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8245                         0xffffffff, 0x00000000 },
8246                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8247                         0xffffffff, 0x00000000 },
8248
8249                 /* Mailbox Registers */
8250                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8251                         0x00000000, 0x000001ff },
8252                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8253                         0x00000000, 0x000001ff },
8254                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8255                         0x00000000, 0x000007ff },
8256                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8257                         0x00000000, 0x000001ff },
8258
8259                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8260         };
8261
8262         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8263                 is_5705 = 1;
8264         else
8265                 is_5705 = 0;
8266
8267         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8268                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8269                         continue;
8270
8271                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8272                         continue;
8273
8274                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8275                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8276                         continue;
8277
8278                 offset = (u32) reg_tbl[i].offset;
8279                 read_mask = reg_tbl[i].read_mask;
8280                 write_mask = reg_tbl[i].write_mask;
8281
8282                 /* Save the original register content */
8283                 save_val = tr32(offset);
8284
8285                 /* Determine the read-only value. */
8286                 read_val = save_val & read_mask;
8287
8288                 /* Write zero to the register, then make sure the read-only bits
8289                  * are not changed and the read/write bits are all zeros.
8290                  */
8291                 tw32(offset, 0);
8292
8293                 val = tr32(offset);
8294
8295                 /* Test the read-only and read/write bits. */
8296                 if (((val & read_mask) != read_val) || (val & write_mask))
8297                         goto out;
8298
8299                 /* Write ones to all the bits defined by RdMask and WrMask, then
8300                  * make sure the read-only bits are not changed and the
8301                  * read/write bits are all ones.
8302                  */
8303                 tw32(offset, read_mask | write_mask);
8304
8305                 val = tr32(offset);
8306
8307                 /* Test the read-only bits. */
8308                 if ((val & read_mask) != read_val)
8309                         goto out;
8310
8311                 /* Test the read/write bits. */
8312                 if ((val & write_mask) != write_mask)
8313                         goto out;
8314
8315                 tw32(offset, save_val);
8316         }
8317
8318         return 0;
8319
8320 out:
8321         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8322         tw32(offset, save_val);
8323         return -EIO;
8324 }
8325
8326 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8327 {
8328         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8329         int i;
8330         u32 j;
8331
8332         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8333                 for (j = 0; j < len; j += 4) {
8334                         u32 val;
8335
8336                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8337                         tg3_read_mem(tp, offset + j, &val);
8338                         if (val != test_pattern[i])
8339                                 return -EIO;
8340                 }
8341         }
8342         return 0;
8343 }
8344
8345 static int tg3_test_memory(struct tg3 *tp)
8346 {
8347         static struct mem_entry {
8348                 u32 offset;
8349                 u32 len;
8350         } mem_tbl_570x[] = {
8351                 { 0x00000000, 0x00b50},
8352                 { 0x00002000, 0x1c000},
8353                 { 0xffffffff, 0x00000}
8354         }, mem_tbl_5705[] = {
8355                 { 0x00000100, 0x0000c},
8356                 { 0x00000200, 0x00008},
8357                 { 0x00004000, 0x00800},
8358                 { 0x00006000, 0x01000},
8359                 { 0x00008000, 0x02000},
8360                 { 0x00010000, 0x0e000},
8361                 { 0xffffffff, 0x00000}
8362         }, mem_tbl_5755[] = {
8363                 { 0x00000200, 0x00008},
8364                 { 0x00004000, 0x00800},
8365                 { 0x00006000, 0x00800},
8366                 { 0x00008000, 0x02000},
8367                 { 0x00010000, 0x0c000},
8368                 { 0xffffffff, 0x00000}
8369         };
8370         struct mem_entry *mem_tbl;
8371         int err = 0;
8372         int i;
8373
8374         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8375                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8376                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8377                         mem_tbl = mem_tbl_5755;
8378                 else
8379                         mem_tbl = mem_tbl_5705;
8380         } else
8381                 mem_tbl = mem_tbl_570x;
8382
8383         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8384                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8385                     mem_tbl[i].len)) != 0)
8386                         break;
8387         }
8388
8389         return err;
8390 }
8391
8392 #define TG3_MAC_LOOPBACK        0
8393 #define TG3_PHY_LOOPBACK        1
8394
8395 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8396 {
8397         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8398         u32 desc_idx;
8399         struct sk_buff *skb, *rx_skb;
8400         u8 *tx_data;
8401         dma_addr_t map;
8402         int num_pkts, tx_len, rx_len, i, err;
8403         struct tg3_rx_buffer_desc *desc;
8404
8405         if (loopback_mode == TG3_MAC_LOOPBACK) {
8406                 /* HW errata - mac loopback fails in some cases on 5780.
8407                  * Normal traffic and PHY loopback are not affected by
8408                  * errata.
8409                  */
8410                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8411                         return 0;
8412
8413                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8414                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8415                            MAC_MODE_PORT_MODE_GMII;
8416                 tw32(MAC_MODE, mac_mode);
8417         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8418                 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8419                                            BMCR_SPEED1000);
8420                 udelay(40);
8421                 /* reset to prevent losing 1st rx packet intermittently */
8422                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8423                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8424                         udelay(10);
8425                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8426                 }
8427                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8428                            MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8429                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8430                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8431                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8432                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8433                 }
8434                 tw32(MAC_MODE, mac_mode);
8435         }
8436         else
8437                 return -EINVAL;
8438
8439         err = -EIO;
8440
8441         tx_len = 1514;
8442         skb = dev_alloc_skb(tx_len);
8443         tx_data = skb_put(skb, tx_len);
8444         memcpy(tx_data, tp->dev->dev_addr, 6);
8445         memset(tx_data + 6, 0x0, 8);
8446
8447         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8448
8449         for (i = 14; i < tx_len; i++)
8450                 tx_data[i] = (u8) (i & 0xff);
8451
8452         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8453
8454         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8455              HOSTCC_MODE_NOW);
8456
8457         udelay(10);
8458
8459         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8460
8461         num_pkts = 0;
8462
8463         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8464
8465         tp->tx_prod++;
8466         num_pkts++;
8467
8468         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8469                      tp->tx_prod);
8470         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8471
8472         udelay(10);
8473
8474         for (i = 0; i < 10; i++) {
8475                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8476                        HOSTCC_MODE_NOW);
8477
8478                 udelay(10);
8479
8480                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8481                 rx_idx = tp->hw_status->idx[0].rx_producer;
8482                 if ((tx_idx == tp->tx_prod) &&
8483                     (rx_idx == (rx_start_idx + num_pkts)))
8484                         break;
8485         }
8486
8487         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8488         dev_kfree_skb(skb);
8489
8490         if (tx_idx != tp->tx_prod)
8491                 goto out;
8492
8493         if (rx_idx != rx_start_idx + num_pkts)
8494                 goto out;
8495
8496         desc = &tp->rx_rcb[rx_start_idx];
8497         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8498         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8499         if (opaque_key != RXD_OPAQUE_RING_STD)
8500                 goto out;
8501
8502         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8503             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8504                 goto out;
8505
8506         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8507         if (rx_len != tx_len)
8508                 goto out;
8509
8510         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8511
8512         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8513         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8514
8515         for (i = 14; i < tx_len; i++) {
8516                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8517                         goto out;
8518         }
8519         err = 0;
8520
8521         /* tg3_free_rings will unmap and free the rx_skb */
8522 out:
8523         return err;
8524 }
8525
8526 #define TG3_MAC_LOOPBACK_FAILED         1
8527 #define TG3_PHY_LOOPBACK_FAILED         2
8528 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8529                                          TG3_PHY_LOOPBACK_FAILED)
8530
8531 static int tg3_test_loopback(struct tg3 *tp)
8532 {
8533         int err = 0;
8534
8535         if (!netif_running(tp->dev))
8536                 return TG3_LOOPBACK_FAILED;
8537
8538         tg3_reset_hw(tp);
8539
8540         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8541                 err |= TG3_MAC_LOOPBACK_FAILED;
8542         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8543                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8544                         err |= TG3_PHY_LOOPBACK_FAILED;
8545         }
8546
8547         return err;
8548 }
8549
8550 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8551                           u64 *data)
8552 {
8553         struct tg3 *tp = netdev_priv(dev);
8554
8555         if (tp->link_config.phy_is_low_power)
8556                 tg3_set_power_state(tp, PCI_D0);
8557
8558         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8559
8560         if (tg3_test_nvram(tp) != 0) {
8561                 etest->flags |= ETH_TEST_FL_FAILED;
8562                 data[0] = 1;
8563         }
8564         if (tg3_test_link(tp) != 0) {
8565                 etest->flags |= ETH_TEST_FL_FAILED;
8566                 data[1] = 1;
8567         }
8568         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8569                 int err, irq_sync = 0;
8570
8571                 if (netif_running(dev)) {
8572                         tg3_netif_stop(tp);
8573                         irq_sync = 1;
8574                 }
8575
8576                 tg3_full_lock(tp, irq_sync);
8577
8578                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8579                 err = tg3_nvram_lock(tp);
8580                 tg3_halt_cpu(tp, RX_CPU_BASE);
8581                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8582                         tg3_halt_cpu(tp, TX_CPU_BASE);
8583                 if (!err)
8584                         tg3_nvram_unlock(tp);
8585
8586                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8587                         tg3_phy_reset(tp);
8588
8589                 if (tg3_test_registers(tp) != 0) {
8590                         etest->flags |= ETH_TEST_FL_FAILED;
8591                         data[2] = 1;
8592                 }
8593                 if (tg3_test_memory(tp) != 0) {
8594                         etest->flags |= ETH_TEST_FL_FAILED;
8595                         data[3] = 1;
8596                 }
8597                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8598                         etest->flags |= ETH_TEST_FL_FAILED;
8599
8600                 tg3_full_unlock(tp);
8601
8602                 if (tg3_test_interrupt(tp) != 0) {
8603                         etest->flags |= ETH_TEST_FL_FAILED;
8604                         data[5] = 1;
8605                 }
8606
8607                 tg3_full_lock(tp, 0);
8608
8609                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8610                 if (netif_running(dev)) {
8611                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8612                         tg3_init_hw(tp);
8613                         tg3_netif_start(tp);
8614                 }
8615
8616                 tg3_full_unlock(tp);
8617         }
8618         if (tp->link_config.phy_is_low_power)
8619                 tg3_set_power_state(tp, PCI_D3hot);
8620
8621 }
8622
8623 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8624 {
8625         struct mii_ioctl_data *data = if_mii(ifr);
8626         struct tg3 *tp = netdev_priv(dev);
8627         int err;
8628
8629         switch(cmd) {
8630         case SIOCGMIIPHY:
8631                 data->phy_id = PHY_ADDR;
8632
8633                 /* fallthru */
8634         case SIOCGMIIREG: {
8635                 u32 mii_regval;
8636
8637                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8638                         break;                  /* We have no PHY */
8639
8640                 if (tp->link_config.phy_is_low_power)
8641                         return -EAGAIN;
8642
8643                 spin_lock_bh(&tp->lock);
8644                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8645                 spin_unlock_bh(&tp->lock);
8646
8647                 data->val_out = mii_regval;
8648
8649                 return err;
8650         }
8651
8652         case SIOCSMIIREG:
8653                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8654                         break;                  /* We have no PHY */
8655
8656                 if (!capable(CAP_NET_ADMIN))
8657                         return -EPERM;
8658
8659                 if (tp->link_config.phy_is_low_power)
8660                         return -EAGAIN;
8661
8662                 spin_lock_bh(&tp->lock);
8663                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8664                 spin_unlock_bh(&tp->lock);
8665
8666                 return err;
8667
8668         default:
8669                 /* do nothing */
8670                 break;
8671         }
8672         return -EOPNOTSUPP;
8673 }
8674
8675 #if TG3_VLAN_TAG_USED
8676 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8677 {
8678         struct tg3 *tp = netdev_priv(dev);
8679
8680         tg3_full_lock(tp, 0);
8681
8682         tp->vlgrp = grp;
8683
8684         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8685         __tg3_set_rx_mode(dev);
8686
8687         tg3_full_unlock(tp);
8688 }
8689
8690 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8691 {
8692         struct tg3 *tp = netdev_priv(dev);
8693
8694         tg3_full_lock(tp, 0);
8695         if (tp->vlgrp)
8696                 tp->vlgrp->vlan_devices[vid] = NULL;
8697         tg3_full_unlock(tp);
8698 }
8699 #endif
8700
8701 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8702 {
8703         struct tg3 *tp = netdev_priv(dev);
8704
8705         memcpy(ec, &tp->coal, sizeof(*ec));
8706         return 0;
8707 }
8708
8709 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8710 {
8711         struct tg3 *tp = netdev_priv(dev);
8712         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8713         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8714
8715         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8716                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8717                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8718                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8719                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8720         }
8721
8722         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8723             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8724             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8725             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8726             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8727             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8728             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8729             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8730             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8731             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8732                 return -EINVAL;
8733
8734         /* No rx interrupts will be generated if both are zero */
8735         if ((ec->rx_coalesce_usecs == 0) &&
8736             (ec->rx_max_coalesced_frames == 0))
8737                 return -EINVAL;
8738
8739         /* No tx interrupts will be generated if both are zero */
8740         if ((ec->tx_coalesce_usecs == 0) &&
8741             (ec->tx_max_coalesced_frames == 0))
8742                 return -EINVAL;
8743
8744         /* Only copy relevant parameters, ignore all others. */
8745         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8746         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8747         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8748         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8749         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8750         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8751         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8752         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8753         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8754
8755         if (netif_running(dev)) {
8756                 tg3_full_lock(tp, 0);
8757                 __tg3_set_coalesce(tp, &tp->coal);
8758                 tg3_full_unlock(tp);
8759         }
8760         return 0;
8761 }
8762
8763 static struct ethtool_ops tg3_ethtool_ops = {
8764         .get_settings           = tg3_get_settings,
8765         .set_settings           = tg3_set_settings,
8766         .get_drvinfo            = tg3_get_drvinfo,
8767         .get_regs_len           = tg3_get_regs_len,
8768         .get_regs               = tg3_get_regs,
8769         .get_wol                = tg3_get_wol,
8770         .set_wol                = tg3_set_wol,
8771         .get_msglevel           = tg3_get_msglevel,
8772         .set_msglevel           = tg3_set_msglevel,
8773         .nway_reset             = tg3_nway_reset,
8774         .get_link               = ethtool_op_get_link,
8775         .get_eeprom_len         = tg3_get_eeprom_len,
8776         .get_eeprom             = tg3_get_eeprom,
8777         .set_eeprom             = tg3_set_eeprom,
8778         .get_ringparam          = tg3_get_ringparam,
8779         .set_ringparam          = tg3_set_ringparam,
8780         .get_pauseparam         = tg3_get_pauseparam,
8781         .set_pauseparam         = tg3_set_pauseparam,
8782         .get_rx_csum            = tg3_get_rx_csum,
8783         .set_rx_csum            = tg3_set_rx_csum,
8784         .get_tx_csum            = ethtool_op_get_tx_csum,
8785         .set_tx_csum            = tg3_set_tx_csum,
8786         .get_sg                 = ethtool_op_get_sg,
8787         .set_sg                 = ethtool_op_set_sg,
8788 #if TG3_TSO_SUPPORT != 0
8789         .get_tso                = ethtool_op_get_tso,
8790         .set_tso                = tg3_set_tso,
8791 #endif
8792         .self_test_count        = tg3_get_test_count,
8793         .self_test              = tg3_self_test,
8794         .get_strings            = tg3_get_strings,
8795         .phys_id                = tg3_phys_id,
8796         .get_stats_count        = tg3_get_stats_count,
8797         .get_ethtool_stats      = tg3_get_ethtool_stats,
8798         .get_coalesce           = tg3_get_coalesce,
8799         .set_coalesce           = tg3_set_coalesce,
8800         .get_perm_addr          = ethtool_op_get_perm_addr,
8801 };
8802
8803 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8804 {
8805         u32 cursize, val, magic;
8806
8807         tp->nvram_size = EEPROM_CHIP_SIZE;
8808
8809         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8810                 return;
8811
8812         if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
8813                 return;
8814
8815         /*
8816          * Size the chip by reading offsets at increasing powers of two.
8817          * When we encounter our validation signature, we know the addressing
8818          * has wrapped around, and thus have our chip size.
8819          */
8820         cursize = 0x10;
8821
8822         while (cursize < tp->nvram_size) {
8823                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
8824                         return;
8825
8826                 if (val == magic)
8827                         break;
8828
8829                 cursize <<= 1;
8830         }
8831
8832         tp->nvram_size = cursize;
8833 }
8834
8835 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8836 {
8837         u32 val;
8838
8839         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
8840                 return;
8841
8842         /* Selfboot format */
8843         if (val != TG3_EEPROM_MAGIC) {
8844                 tg3_get_eeprom_size(tp);
8845                 return;
8846         }
8847
8848         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8849                 if (val != 0) {
8850                         tp->nvram_size = (val >> 16) * 1024;
8851                         return;
8852                 }
8853         }
8854         tp->nvram_size = 0x20000;
8855 }
8856
8857 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8858 {
8859         u32 nvcfg1;
8860
8861         nvcfg1 = tr32(NVRAM_CFG1);
8862         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8863                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8864         }
8865         else {
8866                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8867                 tw32(NVRAM_CFG1, nvcfg1);
8868         }
8869
8870         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8871             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8872                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8873                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8874                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8875                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8876                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8877                                 break;
8878                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8879                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8880                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8881                                 break;
8882                         case FLASH_VENDOR_ATMEL_EEPROM:
8883                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8884                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8885                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8886                                 break;
8887                         case FLASH_VENDOR_ST:
8888                                 tp->nvram_jedecnum = JEDEC_ST;
8889                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8890                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8891                                 break;
8892                         case FLASH_VENDOR_SAIFUN:
8893                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
8894                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8895                                 break;
8896                         case FLASH_VENDOR_SST_SMALL:
8897                         case FLASH_VENDOR_SST_LARGE:
8898                                 tp->nvram_jedecnum = JEDEC_SST;
8899                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8900                                 break;
8901                 }
8902         }
8903         else {
8904                 tp->nvram_jedecnum = JEDEC_ATMEL;
8905                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8906                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8907         }
8908 }
8909
8910 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8911 {
8912         u32 nvcfg1;
8913
8914         nvcfg1 = tr32(NVRAM_CFG1);
8915
8916         /* NVRAM protection for TPM */
8917         if (nvcfg1 & (1 << 27))
8918                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8919
8920         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8921                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8922                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8923                         tp->nvram_jedecnum = JEDEC_ATMEL;
8924                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8925                         break;
8926                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8927                         tp->nvram_jedecnum = JEDEC_ATMEL;
8928                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8929                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8930                         break;
8931                 case FLASH_5752VENDOR_ST_M45PE10:
8932                 case FLASH_5752VENDOR_ST_M45PE20:
8933                 case FLASH_5752VENDOR_ST_M45PE40:
8934                         tp->nvram_jedecnum = JEDEC_ST;
8935                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8936                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8937                         break;
8938         }
8939
8940         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8941                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8942                         case FLASH_5752PAGE_SIZE_256:
8943                                 tp->nvram_pagesize = 256;
8944                                 break;
8945                         case FLASH_5752PAGE_SIZE_512:
8946                                 tp->nvram_pagesize = 512;
8947                                 break;
8948                         case FLASH_5752PAGE_SIZE_1K:
8949                                 tp->nvram_pagesize = 1024;
8950                                 break;
8951                         case FLASH_5752PAGE_SIZE_2K:
8952                                 tp->nvram_pagesize = 2048;
8953                                 break;
8954                         case FLASH_5752PAGE_SIZE_4K:
8955                                 tp->nvram_pagesize = 4096;
8956                                 break;
8957                         case FLASH_5752PAGE_SIZE_264:
8958                                 tp->nvram_pagesize = 264;
8959                                 break;
8960                 }
8961         }
8962         else {
8963                 /* For eeprom, set pagesize to maximum eeprom size */
8964                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8965
8966                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8967                 tw32(NVRAM_CFG1, nvcfg1);
8968         }
8969 }
8970
8971 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
8972 {
8973         u32 nvcfg1;
8974
8975         nvcfg1 = tr32(NVRAM_CFG1);
8976
8977         /* NVRAM protection for TPM */
8978         if (nvcfg1 & (1 << 27))
8979                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8980
8981         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8982                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
8983                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
8984                         tp->nvram_jedecnum = JEDEC_ATMEL;
8985                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8986                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8987
8988                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8989                         tw32(NVRAM_CFG1, nvcfg1);
8990                         break;
8991                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8992                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
8993                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
8994                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
8995                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
8996                         tp->nvram_jedecnum = JEDEC_ATMEL;
8997                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8998                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8999                         tp->nvram_pagesize = 264;
9000                         break;
9001                 case FLASH_5752VENDOR_ST_M45PE10:
9002                 case FLASH_5752VENDOR_ST_M45PE20:
9003                 case FLASH_5752VENDOR_ST_M45PE40:
9004                         tp->nvram_jedecnum = JEDEC_ST;
9005                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9006                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9007                         tp->nvram_pagesize = 256;
9008                         break;
9009         }
9010 }
9011
9012 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9013 {
9014         u32 nvcfg1;
9015
9016         nvcfg1 = tr32(NVRAM_CFG1);
9017
9018         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9019                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9020                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9021                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9022                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9023                         tp->nvram_jedecnum = JEDEC_ATMEL;
9024                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9025                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9026
9027                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9028                         tw32(NVRAM_CFG1, nvcfg1);
9029                         break;
9030                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9031                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9032                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9033                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9034                         tp->nvram_jedecnum = JEDEC_ATMEL;
9035                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9036                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9037                         tp->nvram_pagesize = 264;
9038                         break;
9039                 case FLASH_5752VENDOR_ST_M45PE10:
9040                 case FLASH_5752VENDOR_ST_M45PE20:
9041                 case FLASH_5752VENDOR_ST_M45PE40:
9042                         tp->nvram_jedecnum = JEDEC_ST;
9043                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9044                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9045                         tp->nvram_pagesize = 256;
9046                         break;
9047         }
9048 }
9049
9050 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9051 static void __devinit tg3_nvram_init(struct tg3 *tp)
9052 {
9053         int j;
9054
9055         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
9056                 return;
9057
9058         tw32_f(GRC_EEPROM_ADDR,
9059              (EEPROM_ADDR_FSM_RESET |
9060               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9061                EEPROM_ADDR_CLKPERD_SHIFT)));
9062
9063         /* XXX schedule_timeout() ... */
9064         for (j = 0; j < 100; j++)
9065                 udelay(10);
9066
9067         /* Enable seeprom accesses. */
9068         tw32_f(GRC_LOCAL_CTRL,
9069              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9070         udelay(100);
9071
9072         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9073             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9074                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9075
9076                 if (tg3_nvram_lock(tp)) {
9077                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9078                                "tg3_nvram_init failed.\n", tp->dev->name);
9079                         return;
9080                 }
9081                 tg3_enable_nvram_access(tp);
9082
9083                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9084                         tg3_get_5752_nvram_info(tp);
9085                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9086                         tg3_get_5755_nvram_info(tp);
9087                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9088                         tg3_get_5787_nvram_info(tp);
9089                 else
9090                         tg3_get_nvram_info(tp);
9091
9092                 tg3_get_nvram_size(tp);
9093
9094                 tg3_disable_nvram_access(tp);
9095                 tg3_nvram_unlock(tp);
9096
9097         } else {
9098                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9099
9100                 tg3_get_eeprom_size(tp);
9101         }
9102 }
9103
9104 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9105                                         u32 offset, u32 *val)
9106 {
9107         u32 tmp;
9108         int i;
9109
9110         if (offset > EEPROM_ADDR_ADDR_MASK ||
9111             (offset % 4) != 0)
9112                 return -EINVAL;
9113
9114         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9115                                         EEPROM_ADDR_DEVID_MASK |
9116                                         EEPROM_ADDR_READ);
9117         tw32(GRC_EEPROM_ADDR,
9118              tmp |
9119              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9120              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9121               EEPROM_ADDR_ADDR_MASK) |
9122              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9123
9124         for (i = 0; i < 10000; i++) {
9125                 tmp = tr32(GRC_EEPROM_ADDR);
9126
9127                 if (tmp & EEPROM_ADDR_COMPLETE)
9128                         break;
9129                 udelay(100);
9130         }
9131         if (!(tmp & EEPROM_ADDR_COMPLETE))
9132                 return -EBUSY;
9133
9134         *val = tr32(GRC_EEPROM_DATA);
9135         return 0;
9136 }
9137
9138 #define NVRAM_CMD_TIMEOUT 10000
9139
9140 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9141 {
9142         int i;
9143
9144         tw32(NVRAM_CMD, nvram_cmd);
9145         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9146                 udelay(10);
9147                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9148                         udelay(10);
9149                         break;
9150                 }
9151         }
9152         if (i == NVRAM_CMD_TIMEOUT) {
9153                 return -EBUSY;
9154         }
9155         return 0;
9156 }
9157
9158 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9159 {
9160         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9161             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9162             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9163             (tp->nvram_jedecnum == JEDEC_ATMEL))
9164
9165                 addr = ((addr / tp->nvram_pagesize) <<
9166                         ATMEL_AT45DB0X1B_PAGE_POS) +
9167                        (addr % tp->nvram_pagesize);
9168
9169         return addr;
9170 }
9171
9172 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9173 {
9174         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9175             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9176             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9177             (tp->nvram_jedecnum == JEDEC_ATMEL))
9178
9179                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9180                         tp->nvram_pagesize) +
9181                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9182
9183         return addr;
9184 }
9185
9186 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9187 {
9188         int ret;
9189
9190         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9191                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
9192                 return -EINVAL;
9193         }
9194
9195         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9196                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9197
9198         offset = tg3_nvram_phys_addr(tp, offset);
9199
9200         if (offset > NVRAM_ADDR_MSK)
9201                 return -EINVAL;
9202
9203         ret = tg3_nvram_lock(tp);
9204         if (ret)
9205                 return ret;
9206
9207         tg3_enable_nvram_access(tp);
9208
9209         tw32(NVRAM_ADDR, offset);
9210         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9211                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9212
9213         if (ret == 0)
9214                 *val = swab32(tr32(NVRAM_RDDATA));
9215
9216         tg3_disable_nvram_access(tp);
9217
9218         tg3_nvram_unlock(tp);
9219
9220         return ret;
9221 }
9222
9223 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9224 {
9225         int err;
9226         u32 tmp;
9227
9228         err = tg3_nvram_read(tp, offset, &tmp);
9229         *val = swab32(tmp);
9230         return err;
9231 }
9232
9233 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9234                                     u32 offset, u32 len, u8 *buf)
9235 {
9236         int i, j, rc = 0;
9237         u32 val;
9238
9239         for (i = 0; i < len; i += 4) {
9240                 u32 addr, data;
9241
9242                 addr = offset + i;
9243
9244                 memcpy(&data, buf + i, 4);
9245
9246                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9247
9248                 val = tr32(GRC_EEPROM_ADDR);
9249                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9250
9251                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9252                         EEPROM_ADDR_READ);
9253                 tw32(GRC_EEPROM_ADDR, val |
9254                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9255                         (addr & EEPROM_ADDR_ADDR_MASK) |
9256                         EEPROM_ADDR_START |
9257                         EEPROM_ADDR_WRITE);
9258
9259                 for (j = 0; j < 10000; j++) {
9260                         val = tr32(GRC_EEPROM_ADDR);
9261
9262                         if (val & EEPROM_ADDR_COMPLETE)
9263                                 break;
9264                         udelay(100);
9265                 }
9266                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9267                         rc = -EBUSY;
9268                         break;
9269                 }
9270         }
9271
9272         return rc;
9273 }
9274
9275 /* offset and length are dword aligned */
9276 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9277                 u8 *buf)
9278 {
9279         int ret = 0;
9280         u32 pagesize = tp->nvram_pagesize;
9281         u32 pagemask = pagesize - 1;
9282         u32 nvram_cmd;
9283         u8 *tmp;
9284
9285         tmp = kmalloc(pagesize, GFP_KERNEL);
9286         if (tmp == NULL)
9287                 return -ENOMEM;
9288
9289         while (len) {
9290                 int j;
9291                 u32 phy_addr, page_off, size;
9292
9293                 phy_addr = offset & ~pagemask;
9294
9295                 for (j = 0; j < pagesize; j += 4) {
9296                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9297                                                 (u32 *) (tmp + j))))
9298                                 break;
9299                 }
9300                 if (ret)
9301                         break;
9302
9303                 page_off = offset & pagemask;
9304                 size = pagesize;
9305                 if (len < size)
9306                         size = len;
9307
9308                 len -= size;
9309
9310                 memcpy(tmp + page_off, buf, size);
9311
9312                 offset = offset + (pagesize - page_off);
9313
9314                 tg3_enable_nvram_access(tp);
9315
9316                 /*
9317                  * Before we can erase the flash page, we need
9318                  * to issue a special "write enable" command.
9319                  */
9320                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9321
9322                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9323                         break;
9324
9325                 /* Erase the target page */
9326                 tw32(NVRAM_ADDR, phy_addr);
9327
9328                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9329                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9330
9331                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9332                         break;
9333
9334                 /* Issue another write enable to start the write. */
9335                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9336
9337                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9338                         break;
9339
9340                 for (j = 0; j < pagesize; j += 4) {
9341                         u32 data;
9342
9343                         data = *((u32 *) (tmp + j));
9344                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9345
9346                         tw32(NVRAM_ADDR, phy_addr + j);
9347
9348                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9349                                 NVRAM_CMD_WR;
9350
9351                         if (j == 0)
9352                                 nvram_cmd |= NVRAM_CMD_FIRST;
9353                         else if (j == (pagesize - 4))
9354                                 nvram_cmd |= NVRAM_CMD_LAST;
9355
9356                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9357                                 break;
9358                 }
9359                 if (ret)
9360                         break;
9361         }
9362
9363         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9364         tg3_nvram_exec_cmd(tp, nvram_cmd);
9365
9366         kfree(tmp);
9367
9368         return ret;
9369 }
9370
9371 /* offset and length are dword aligned */
9372 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9373                 u8 *buf)
9374 {
9375         int i, ret = 0;
9376
9377         for (i = 0; i < len; i += 4, offset += 4) {
9378                 u32 data, page_off, phy_addr, nvram_cmd;
9379
9380                 memcpy(&data, buf + i, 4);
9381                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9382
9383                 page_off = offset % tp->nvram_pagesize;
9384
9385                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9386
9387                 tw32(NVRAM_ADDR, phy_addr);
9388
9389                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9390
9391                 if ((page_off == 0) || (i == 0))
9392                         nvram_cmd |= NVRAM_CMD_FIRST;
9393                 else if (page_off == (tp->nvram_pagesize - 4))
9394                         nvram_cmd |= NVRAM_CMD_LAST;
9395
9396                 if (i == (len - 4))
9397                         nvram_cmd |= NVRAM_CMD_LAST;
9398
9399                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9400                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9401                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9402                     (tp->nvram_jedecnum == JEDEC_ST) &&
9403                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9404
9405                         if ((ret = tg3_nvram_exec_cmd(tp,
9406                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9407                                 NVRAM_CMD_DONE)))
9408
9409                                 break;
9410                 }
9411                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9412                         /* We always do complete word writes to eeprom. */
9413                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9414                 }
9415
9416                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9417                         break;
9418         }
9419         return ret;
9420 }
9421
9422 /* offset and length are dword aligned */
9423 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9424 {
9425         int ret;
9426
9427         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9428                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
9429                 return -EINVAL;
9430         }
9431
9432         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9433                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9434                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9435                 udelay(40);
9436         }
9437
9438         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9439                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9440         }
9441         else {
9442                 u32 grc_mode;
9443
9444                 ret = tg3_nvram_lock(tp);
9445                 if (ret)
9446                         return ret;
9447
9448                 tg3_enable_nvram_access(tp);
9449                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9450                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9451                         tw32(NVRAM_WRITE1, 0x406);
9452
9453                 grc_mode = tr32(GRC_MODE);
9454                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9455
9456                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9457                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9458
9459                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9460                                 buf);
9461                 }
9462                 else {
9463                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9464                                 buf);
9465                 }
9466
9467                 grc_mode = tr32(GRC_MODE);
9468                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9469
9470                 tg3_disable_nvram_access(tp);
9471                 tg3_nvram_unlock(tp);
9472         }
9473
9474         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9475                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9476                 udelay(40);
9477         }
9478
9479         return ret;
9480 }
9481
9482 struct subsys_tbl_ent {
9483         u16 subsys_vendor, subsys_devid;
9484         u32 phy_id;
9485 };
9486
9487 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9488         /* Broadcom boards. */
9489         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9490         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9491         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9492         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9493         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9494         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9495         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9496         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9497         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9498         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9499         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9500
9501         /* 3com boards. */
9502         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9503         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9504         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9505         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9506         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9507
9508         /* DELL boards. */
9509         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9510         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9511         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9512         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9513
9514         /* Compaq boards. */
9515         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9516         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9517         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9518         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9519         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9520
9521         /* IBM boards. */
9522         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9523 };
9524
9525 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9526 {
9527         int i;
9528
9529         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9530                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9531                      tp->pdev->subsystem_vendor) &&
9532                     (subsys_id_to_phy_id[i].subsys_devid ==
9533                      tp->pdev->subsystem_device))
9534                         return &subsys_id_to_phy_id[i];
9535         }
9536         return NULL;
9537 }
9538
9539 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9540 {
9541         u32 val;
9542         u16 pmcsr;
9543
9544         /* On some early chips the SRAM cannot be accessed in D3hot state,
9545          * so need make sure we're in D0.
9546          */
9547         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9548         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9549         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9550         msleep(1);
9551
9552         /* Make sure register accesses (indirect or otherwise)
9553          * will function correctly.
9554          */
9555         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9556                                tp->misc_host_ctrl);
9557
9558         tp->phy_id = PHY_ID_INVALID;
9559         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9560
9561         /* Do not even try poking around in here on Sun parts.  */
9562         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9563                 /* All SUN chips are built-in LOMs. */
9564                 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9565                 return;
9566         }
9567
9568         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9569         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9570                 u32 nic_cfg, led_cfg;
9571                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9572                 int eeprom_phy_serdes = 0;
9573
9574                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9575                 tp->nic_sram_data_cfg = nic_cfg;
9576
9577                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9578                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9579                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9580                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9581                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9582                     (ver > 0) && (ver < 0x100))
9583                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9584
9585                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9586                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9587                         eeprom_phy_serdes = 1;
9588
9589                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9590                 if (nic_phy_id != 0) {
9591                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9592                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9593
9594                         eeprom_phy_id  = (id1 >> 16) << 10;
9595                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
9596                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
9597                 } else
9598                         eeprom_phy_id = 0;
9599
9600                 tp->phy_id = eeprom_phy_id;
9601                 if (eeprom_phy_serdes) {
9602                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9603                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9604                         else
9605                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9606                 }
9607
9608                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9609                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9610                                     SHASTA_EXT_LED_MODE_MASK);
9611                 else
9612                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9613
9614                 switch (led_cfg) {
9615                 default:
9616                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9617                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9618                         break;
9619
9620                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9621                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9622                         break;
9623
9624                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9625                         tp->led_ctrl = LED_CTRL_MODE_MAC;
9626
9627                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9628                          * read on some older 5700/5701 bootcode.
9629                          */
9630                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9631                             ASIC_REV_5700 ||
9632                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
9633                             ASIC_REV_5701)
9634                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9635
9636                         break;
9637
9638                 case SHASTA_EXT_LED_SHARED:
9639                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
9640                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9641                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9642                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9643                                                  LED_CTRL_MODE_PHY_2);
9644                         break;
9645
9646                 case SHASTA_EXT_LED_MAC:
9647                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9648                         break;
9649
9650                 case SHASTA_EXT_LED_COMBO:
9651                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
9652                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9653                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9654                                                  LED_CTRL_MODE_PHY_2);
9655                         break;
9656
9657                 };
9658
9659                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9660                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9661                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9662                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9663
9664                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9665                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9666
9667                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9668                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9669                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9670                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9671                 }
9672                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9673                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9674
9675                 if (cfg2 & (1 << 17))
9676                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9677
9678                 /* serdes signal pre-emphasis in register 0x590 set by */
9679                 /* bootcode if bit 18 is set */
9680                 if (cfg2 & (1 << 18))
9681                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9682         }
9683 }
9684
9685 static int __devinit tg3_phy_probe(struct tg3 *tp)
9686 {
9687         u32 hw_phy_id_1, hw_phy_id_2;
9688         u32 hw_phy_id, hw_phy_id_masked;
9689         int err;
9690
9691         /* Reading the PHY ID register can conflict with ASF
9692          * firwmare access to the PHY hardware.
9693          */
9694         err = 0;
9695         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9696                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9697         } else {
9698                 /* Now read the physical PHY_ID from the chip and verify
9699                  * that it is sane.  If it doesn't look good, we fall back
9700                  * to either the hard-coded table based PHY_ID and failing
9701                  * that the value found in the eeprom area.
9702                  */
9703                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9704                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9705
9706                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
9707                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9708                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
9709
9710                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9711         }
9712
9713         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9714                 tp->phy_id = hw_phy_id;
9715                 if (hw_phy_id_masked == PHY_ID_BCM8002)
9716                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9717                 else
9718                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9719         } else {
9720                 if (tp->phy_id != PHY_ID_INVALID) {
9721                         /* Do nothing, phy ID already set up in
9722                          * tg3_get_eeprom_hw_cfg().
9723                          */
9724                 } else {
9725                         struct subsys_tbl_ent *p;
9726
9727                         /* No eeprom signature?  Try the hardcoded
9728                          * subsys device table.
9729                          */
9730                         p = lookup_by_subsys(tp);
9731                         if (!p)
9732                                 return -ENODEV;
9733
9734                         tp->phy_id = p->phy_id;
9735                         if (!tp->phy_id ||
9736                             tp->phy_id == PHY_ID_BCM8002)
9737                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9738                 }
9739         }
9740
9741         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9742             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9743                 u32 bmsr, adv_reg, tg3_ctrl;
9744
9745                 tg3_readphy(tp, MII_BMSR, &bmsr);
9746                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9747                     (bmsr & BMSR_LSTATUS))
9748                         goto skip_phy_reset;
9749
9750                 err = tg3_phy_reset(tp);
9751                 if (err)
9752                         return err;
9753
9754                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9755                            ADVERTISE_100HALF | ADVERTISE_100FULL |
9756                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9757                 tg3_ctrl = 0;
9758                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9759                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9760                                     MII_TG3_CTRL_ADV_1000_FULL);
9761                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9762                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9763                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9764                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
9765                 }
9766
9767                 if (!tg3_copper_is_advertising_all(tp)) {
9768                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9769
9770                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9771                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9772
9773                         tg3_writephy(tp, MII_BMCR,
9774                                      BMCR_ANENABLE | BMCR_ANRESTART);
9775                 }
9776                 tg3_phy_set_wirespeed(tp);
9777
9778                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9779                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9780                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9781         }
9782
9783 skip_phy_reset:
9784         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9785                 err = tg3_init_5401phy_dsp(tp);
9786                 if (err)
9787                         return err;
9788         }
9789
9790         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9791                 err = tg3_init_5401phy_dsp(tp);
9792         }
9793
9794         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9795                 tp->link_config.advertising =
9796                         (ADVERTISED_1000baseT_Half |
9797                          ADVERTISED_1000baseT_Full |
9798                          ADVERTISED_Autoneg |
9799                          ADVERTISED_FIBRE);
9800         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9801                 tp->link_config.advertising &=
9802                         ~(ADVERTISED_1000baseT_Half |
9803                           ADVERTISED_1000baseT_Full);
9804
9805         return err;
9806 }
9807
9808 static void __devinit tg3_read_partno(struct tg3 *tp)
9809 {
9810         unsigned char vpd_data[256];
9811         int i;
9812         u32 magic;
9813
9814         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9815                 /* Sun decided not to put the necessary bits in the
9816                  * NVRAM of their onboard tg3 parts :(
9817                  */
9818                 strcpy(tp->board_part_number, "Sun 570X");
9819                 return;
9820         }
9821
9822         if (tg3_nvram_read_swab(tp, 0x0, &magic))
9823                 return;
9824
9825         if (magic == TG3_EEPROM_MAGIC) {
9826                 for (i = 0; i < 256; i += 4) {
9827                         u32 tmp;
9828
9829                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9830                                 goto out_not_found;
9831
9832                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
9833                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
9834                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9835                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9836                 }
9837         } else {
9838                 int vpd_cap;
9839
9840                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
9841                 for (i = 0; i < 256; i += 4) {
9842                         u32 tmp, j = 0;
9843                         u16 tmp16;
9844
9845                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
9846                                               i);
9847                         while (j++ < 100) {
9848                                 pci_read_config_word(tp->pdev, vpd_cap +
9849                                                      PCI_VPD_ADDR, &tmp16);
9850                                 if (tmp16 & 0x8000)
9851                                         break;
9852                                 msleep(1);
9853                         }
9854                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
9855                                               &tmp);
9856                         tmp = cpu_to_le32(tmp);
9857                         memcpy(&vpd_data[i], &tmp, 4);
9858                 }
9859         }
9860
9861         /* Now parse and find the part number. */
9862         for (i = 0; i < 256; ) {
9863                 unsigned char val = vpd_data[i];
9864                 int block_end;
9865
9866                 if (val == 0x82 || val == 0x91) {
9867                         i = (i + 3 +
9868                              (vpd_data[i + 1] +
9869                               (vpd_data[i + 2] << 8)));
9870                         continue;
9871                 }
9872
9873                 if (val != 0x90)
9874                         goto out_not_found;
9875
9876                 block_end = (i + 3 +
9877                              (vpd_data[i + 1] +
9878                               (vpd_data[i + 2] << 8)));
9879                 i += 3;
9880                 while (i < block_end) {
9881                         if (vpd_data[i + 0] == 'P' &&
9882                             vpd_data[i + 1] == 'N') {
9883                                 int partno_len = vpd_data[i + 2];
9884
9885                                 if (partno_len > 24)
9886                                         goto out_not_found;
9887
9888                                 memcpy(tp->board_part_number,
9889                                        &vpd_data[i + 3],
9890                                        partno_len);
9891
9892                                 /* Success. */
9893                                 return;
9894                         }
9895                 }
9896
9897                 /* Part number not found. */
9898                 goto out_not_found;
9899         }
9900
9901 out_not_found:
9902         strcpy(tp->board_part_number, "none");
9903 }
9904
9905 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
9906 {
9907         u32 val, offset, start;
9908
9909         if (tg3_nvram_read_swab(tp, 0, &val))
9910                 return;
9911
9912         if (val != TG3_EEPROM_MAGIC)
9913                 return;
9914
9915         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
9916             tg3_nvram_read_swab(tp, 0x4, &start))
9917                 return;
9918
9919         offset = tg3_nvram_logical_addr(tp, offset);
9920         if (tg3_nvram_read_swab(tp, offset, &val))
9921                 return;
9922
9923         if ((val & 0xfc000000) == 0x0c000000) {
9924                 u32 ver_offset, addr;
9925                 int i;
9926
9927                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
9928                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
9929                         return;
9930
9931                 if (val != 0)
9932                         return;
9933
9934                 addr = offset + ver_offset - start;
9935                 for (i = 0; i < 16; i += 4) {
9936                         if (tg3_nvram_read(tp, addr + i, &val))
9937                                 return;
9938
9939                         val = cpu_to_le32(val);
9940                         memcpy(tp->fw_ver + i, &val, 4);
9941                 }
9942         }
9943 }
9944
9945 #ifdef CONFIG_SPARC64
9946 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9947 {
9948         struct pci_dev *pdev = tp->pdev;
9949         struct pcidev_cookie *pcp = pdev->sysdata;
9950
9951         if (pcp != NULL) {
9952                 int node = pcp->prom_node;
9953                 u32 venid;
9954                 int err;
9955
9956                 err = prom_getproperty(node, "subsystem-vendor-id",
9957                                        (char *) &venid, sizeof(venid));
9958                 if (err == 0 || err == -1)
9959                         return 0;
9960                 if (venid == PCI_VENDOR_ID_SUN)
9961                         return 1;
9962
9963                 /* TG3 chips onboard the SunBlade-2500 don't have the
9964                  * subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
9965                  * are distinguishable from non-Sun variants by being
9966                  * named "network" by the firmware.  Non-Sun cards will
9967                  * show up as being named "ethernet".
9968                  */
9969                 if (!strcmp(pcp->prom_name, "network"))
9970                         return 1;
9971         }
9972         return 0;
9973 }
9974 #endif
9975
9976 static int __devinit tg3_get_invariants(struct tg3 *tp)
9977 {
9978         static struct pci_device_id write_reorder_chipsets[] = {
9979                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9980                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9981                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9982                              PCI_DEVICE_ID_VIA_8385_0) },
9983                 { },
9984         };
9985         u32 misc_ctrl_reg;
9986         u32 cacheline_sz_reg;
9987         u32 pci_state_reg, grc_misc_cfg;
9988         u32 val;
9989         u16 pci_cmd;
9990         int err;
9991
9992 #ifdef CONFIG_SPARC64
9993         if (tg3_is_sun_570X(tp))
9994                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9995 #endif
9996
9997         /* Force memory write invalidate off.  If we leave it on,
9998          * then on 5700_BX chips we have to enable a workaround.
9999          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10000          * to match the cacheline size.  The Broadcom driver have this
10001          * workaround but turns MWI off all the times so never uses
10002          * it.  This seems to suggest that the workaround is insufficient.
10003          */
10004         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10005         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10006         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10007
10008         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10009          * has the register indirect write enable bit set before
10010          * we try to access any of the MMIO registers.  It is also
10011          * critical that the PCI-X hw workaround situation is decided
10012          * before that as well.
10013          */
10014         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10015                               &misc_ctrl_reg);
10016
10017         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10018                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10019
10020         /* Wrong chip ID in 5752 A0. This code can be removed later
10021          * as A0 is not in production.
10022          */
10023         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10024                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10025
10026         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10027          * we need to disable memory and use config. cycles
10028          * only to access all registers. The 5702/03 chips
10029          * can mistakenly decode the special cycles from the
10030          * ICH chipsets as memory write cycles, causing corruption
10031          * of register and memory space. Only certain ICH bridges
10032          * will drive special cycles with non-zero data during the
10033          * address phase which can fall within the 5703's address
10034          * range. This is not an ICH bug as the PCI spec allows
10035          * non-zero address during special cycles. However, only
10036          * these ICH bridges are known to drive non-zero addresses
10037          * during special cycles.
10038          *
10039          * Since special cycles do not cross PCI bridges, we only
10040          * enable this workaround if the 5703 is on the secondary
10041          * bus of these ICH bridges.
10042          */
10043         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10044             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10045                 static struct tg3_dev_id {
10046                         u32     vendor;
10047                         u32     device;
10048                         u32     rev;
10049                 } ich_chipsets[] = {
10050                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10051                           PCI_ANY_ID },
10052                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10053                           PCI_ANY_ID },
10054                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10055                           0xa },
10056                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10057                           PCI_ANY_ID },
10058                         { },
10059                 };
10060                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10061                 struct pci_dev *bridge = NULL;
10062
10063                 while (pci_id->vendor != 0) {
10064                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10065                                                 bridge);
10066                         if (!bridge) {
10067                                 pci_id++;
10068                                 continue;
10069                         }
10070                         if (pci_id->rev != PCI_ANY_ID) {
10071                                 u8 rev;
10072
10073                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10074                                                      &rev);
10075                                 if (rev > pci_id->rev)
10076                                         continue;
10077                         }
10078                         if (bridge->subordinate &&
10079                             (bridge->subordinate->number ==
10080                              tp->pdev->bus->number)) {
10081
10082                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10083                                 pci_dev_put(bridge);
10084                                 break;
10085                         }
10086                 }
10087         }
10088
10089         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10090          * DMA addresses > 40-bit. This bridge may have other additional
10091          * 57xx devices behind it in some 4-port NIC designs for example.
10092          * Any tg3 device found behind the bridge will also need the 40-bit
10093          * DMA workaround.
10094          */
10095         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10096             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10097                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10098                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10099                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10100         }
10101         else {
10102                 struct pci_dev *bridge = NULL;
10103
10104                 do {
10105                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10106                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10107                                                 bridge);
10108                         if (bridge && bridge->subordinate &&
10109                             (bridge->subordinate->number <=
10110                              tp->pdev->bus->number) &&
10111                             (bridge->subordinate->subordinate >=
10112                              tp->pdev->bus->number)) {
10113                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10114                                 pci_dev_put(bridge);
10115                                 break;
10116                         }
10117                 } while (bridge);
10118         }
10119
10120         /* Initialize misc host control in PCI block. */
10121         tp->misc_host_ctrl |= (misc_ctrl_reg &
10122                                MISC_HOST_CTRL_CHIPREV);
10123         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10124                                tp->misc_host_ctrl);
10125
10126         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10127                               &cacheline_sz_reg);
10128
10129         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10130         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10131         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10132         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10133
10134         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10135             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10136             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10137             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10138             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10139                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10140
10141         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10142             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10143                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10144
10145         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10146                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10147                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10148                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10149                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10150                 } else
10151                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1;
10152         }
10153
10154         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10155             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10156             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10157             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10158             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
10159                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10160
10161         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10162                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10163
10164         /* If we have an AMD 762 or VIA K8T800 chipset, write
10165          * reordering to the mailbox registers done by the host
10166          * controller can cause major troubles.  We read back from
10167          * every mailbox register write to force the writes to be
10168          * posted to the chip in order.
10169          */
10170         if (pci_dev_present(write_reorder_chipsets) &&
10171             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10172                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10173
10174         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10175             tp->pci_lat_timer < 64) {
10176                 tp->pci_lat_timer = 64;
10177
10178                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10179                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10180                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10181                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10182
10183                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10184                                        cacheline_sz_reg);
10185         }
10186
10187         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10188                               &pci_state_reg);
10189
10190         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10191                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10192
10193                 /* If this is a 5700 BX chipset, and we are in PCI-X
10194                  * mode, enable register write workaround.
10195                  *
10196                  * The workaround is to use indirect register accesses
10197                  * for all chip writes not to mailbox registers.
10198                  */
10199                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10200                         u32 pm_reg;
10201                         u16 pci_cmd;
10202
10203                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10204
10205                         /* The chip can have it's power management PCI config
10206                          * space registers clobbered due to this bug.
10207                          * So explicitly force the chip into D0 here.
10208                          */
10209                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10210                                               &pm_reg);
10211                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10212                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10213                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10214                                                pm_reg);
10215
10216                         /* Also, force SERR#/PERR# in PCI command. */
10217                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10218                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10219                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10220                 }
10221         }
10222
10223         /* 5700 BX chips need to have their TX producer index mailboxes
10224          * written twice to workaround a bug.
10225          */
10226         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10227                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10228
10229         /* Back to back register writes can cause problems on this chip,
10230          * the workaround is to read back all reg writes except those to
10231          * mailbox regs.  See tg3_write_indirect_reg32().
10232          *
10233          * PCI Express 5750_A0 rev chips need this workaround too.
10234          */
10235         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10236             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10237              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10238                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10239
10240         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10241                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10242         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10243                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10244
10245         /* Chip-specific fixup from Broadcom driver */
10246         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10247             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10248                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10249                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10250         }
10251
10252         /* Default fast path register access methods */
10253         tp->read32 = tg3_read32;
10254         tp->write32 = tg3_write32;
10255         tp->read32_mbox = tg3_read32;
10256         tp->write32_mbox = tg3_write32;
10257         tp->write32_tx_mbox = tg3_write32;
10258         tp->write32_rx_mbox = tg3_write32;
10259
10260         /* Various workaround register access methods */
10261         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10262                 tp->write32 = tg3_write_indirect_reg32;
10263         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10264                 tp->write32 = tg3_write_flush_reg32;
10265
10266         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10267             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10268                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10269                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10270                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10271         }
10272
10273         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10274                 tp->read32 = tg3_read_indirect_reg32;
10275                 tp->write32 = tg3_write_indirect_reg32;
10276                 tp->read32_mbox = tg3_read_indirect_mbox;
10277                 tp->write32_mbox = tg3_write_indirect_mbox;
10278                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10279                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10280
10281                 iounmap(tp->regs);
10282                 tp->regs = NULL;
10283
10284                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10285                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10286                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10287         }
10288
10289         if (tp->write32 == tg3_write_indirect_reg32 ||
10290             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10291              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10292               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) ||
10293             (tp->tg3_flags2 & TG3_FLG2_SUN_570X))
10294                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10295
10296         /* Get eeprom hw config before calling tg3_set_power_state().
10297          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10298          * determined before calling tg3_set_power_state() so that
10299          * we know whether or not to switch out of Vaux power.
10300          * When the flag is set, it means that GPIO1 is used for eeprom
10301          * write protect and also implies that it is a LOM where GPIOs
10302          * are not used to switch power.
10303          */
10304         tg3_get_eeprom_hw_cfg(tp);
10305
10306         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10307          * GPIO1 driven high will bring 5700's external PHY out of reset.
10308          * It is also used as eeprom write protect on LOMs.
10309          */
10310         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10311         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10312             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10313                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10314                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10315         /* Unused GPIO3 must be driven as output on 5752 because there
10316          * are no pull-up resistors on unused GPIO pins.
10317          */
10318         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10319                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10320
10321         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10322                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10323
10324         /* Force the chip into D0. */
10325         err = tg3_set_power_state(tp, PCI_D0);
10326         if (err) {
10327                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10328                        pci_name(tp->pdev));
10329                 return err;
10330         }
10331
10332         /* 5700 B0 chips do not support checksumming correctly due
10333          * to hardware bugs.
10334          */
10335         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10336                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10337
10338         /* Derive initial jumbo mode from MTU assigned in
10339          * ether_setup() via the alloc_etherdev() call
10340          */
10341         if (tp->dev->mtu > ETH_DATA_LEN &&
10342             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10343                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10344
10345         /* Determine WakeOnLan speed to use. */
10346         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10347             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10348             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10349             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10350                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10351         } else {
10352                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10353         }
10354
10355         /* A few boards don't want Ethernet@WireSpeed phy feature */
10356         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10357             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10358              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10359              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10360             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10361                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10362
10363         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10364             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10365                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10366         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10367                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10368
10369         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10370                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10371                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10372                         tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10373                 else
10374                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10375         }
10376
10377         tp->coalesce_mode = 0;
10378         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10379             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10380                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10381
10382         /* Initialize MAC MI mode, polling disabled. */
10383         tw32_f(MAC_MI_MODE, tp->mi_mode);
10384         udelay(80);
10385
10386         /* Initialize data/descriptor byte/word swapping. */
10387         val = tr32(GRC_MODE);
10388         val &= GRC_MODE_HOST_STACKUP;
10389         tw32(GRC_MODE, val | tp->grc_mode);
10390
10391         tg3_switch_clocks(tp);
10392
10393         /* Clear this out for sanity. */
10394         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10395
10396         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10397                               &pci_state_reg);
10398         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10399             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10400                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10401
10402                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10403                     chiprevid == CHIPREV_ID_5701_B0 ||
10404                     chiprevid == CHIPREV_ID_5701_B2 ||
10405                     chiprevid == CHIPREV_ID_5701_B5) {
10406                         void __iomem *sram_base;
10407
10408                         /* Write some dummy words into the SRAM status block
10409                          * area, see if it reads back correctly.  If the return
10410                          * value is bad, force enable the PCIX workaround.
10411                          */
10412                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10413
10414                         writel(0x00000000, sram_base);
10415                         writel(0x00000000, sram_base + 4);
10416                         writel(0xffffffff, sram_base + 4);
10417                         if (readl(sram_base) != 0x00000000)
10418                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10419                 }
10420         }
10421
10422         udelay(50);
10423         tg3_nvram_init(tp);
10424
10425         grc_misc_cfg = tr32(GRC_MISC_CFG);
10426         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10427
10428         /* Broadcom's driver says that CIOBE multisplit has a bug */
10429 #if 0
10430         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10431             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10432                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10433                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10434         }
10435 #endif
10436         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10437             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10438              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10439                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10440
10441         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10442             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10443                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10444         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10445                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10446                                       HOSTCC_MODE_CLRTICK_TXBD);
10447
10448                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10449                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10450                                        tp->misc_host_ctrl);
10451         }
10452
10453         /* these are limited to 10/100 only */
10454         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10455              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10456             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10457              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10458              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10459               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10460               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10461             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10462              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10463               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
10464                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10465
10466         err = tg3_phy_probe(tp);
10467         if (err) {
10468                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10469                        pci_name(tp->pdev), err);
10470                 /* ... but do not return immediately ... */
10471         }
10472
10473         tg3_read_partno(tp);
10474         tg3_read_fw_ver(tp);
10475
10476         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10477                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10478         } else {
10479                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10480                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10481                 else
10482                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10483         }
10484
10485         /* 5700 {AX,BX} chips have a broken status block link
10486          * change bit implementation, so we must use the
10487          * status register in those cases.
10488          */
10489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10490                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10491         else
10492                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10493
10494         /* The led_ctrl is set during tg3_phy_probe, here we might
10495          * have to force the link status polling mechanism based
10496          * upon subsystem IDs.
10497          */
10498         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10499             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10500                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10501                                   TG3_FLAG_USE_LINKCHG_REG);
10502         }
10503
10504         /* For all SERDES we poll the MAC status register. */
10505         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10506                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10507         else
10508                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10509
10510         /* All chips before 5787 can get confused if TX buffers
10511          * straddle the 4GB address boundary in some cases.
10512          */
10513         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10514             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10515                 tp->dev->hard_start_xmit = tg3_start_xmit;
10516         else
10517                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10518
10519         tp->rx_offset = 2;
10520         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10521             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10522                 tp->rx_offset = 0;
10523
10524         /* By default, disable wake-on-lan.  User can change this
10525          * using ETHTOOL_SWOL.
10526          */
10527         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10528
10529         return err;
10530 }
10531
10532 #ifdef CONFIG_SPARC64
10533 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10534 {
10535         struct net_device *dev = tp->dev;
10536         struct pci_dev *pdev = tp->pdev;
10537         struct pcidev_cookie *pcp = pdev->sysdata;
10538
10539         if (pcp != NULL) {
10540                 int node = pcp->prom_node;
10541
10542                 if (prom_getproplen(node, "local-mac-address") == 6) {
10543                         prom_getproperty(node, "local-mac-address",
10544                                          dev->dev_addr, 6);
10545                         memcpy(dev->perm_addr, dev->dev_addr, 6);
10546                         return 0;
10547                 }
10548         }
10549         return -ENODEV;
10550 }
10551
10552 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10553 {
10554         struct net_device *dev = tp->dev;
10555
10556         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10557         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10558         return 0;
10559 }
10560 #endif
10561
10562 static int __devinit tg3_get_device_address(struct tg3 *tp)
10563 {
10564         struct net_device *dev = tp->dev;
10565         u32 hi, lo, mac_offset;
10566         int addr_ok = 0;
10567
10568 #ifdef CONFIG_SPARC64
10569         if (!tg3_get_macaddr_sparc(tp))
10570                 return 0;
10571 #endif
10572
10573         mac_offset = 0x7c;
10574         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10575              !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
10576             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10577                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10578                         mac_offset = 0xcc;
10579                 if (tg3_nvram_lock(tp))
10580                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
10581                 else
10582                         tg3_nvram_unlock(tp);
10583         }
10584
10585         /* First try to get it from MAC address mailbox. */
10586         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
10587         if ((hi >> 16) == 0x484b) {
10588                 dev->dev_addr[0] = (hi >>  8) & 0xff;
10589                 dev->dev_addr[1] = (hi >>  0) & 0xff;
10590
10591                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
10592                 dev->dev_addr[2] = (lo >> 24) & 0xff;
10593                 dev->dev_addr[3] = (lo >> 16) & 0xff;
10594                 dev->dev_addr[4] = (lo >>  8) & 0xff;
10595                 dev->dev_addr[5] = (lo >>  0) & 0xff;
10596
10597                 /* Some old bootcode may report a 0 MAC address in SRAM */
10598                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
10599         }
10600         if (!addr_ok) {
10601                 /* Next, try NVRAM. */
10602                 if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
10603                     !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10604                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
10605                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
10606                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
10607                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
10608                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
10609                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
10610                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
10611                 }
10612                 /* Finally just fetch it out of the MAC control regs. */
10613                 else {
10614                         hi = tr32(MAC_ADDR_0_HIGH);
10615                         lo = tr32(MAC_ADDR_0_LOW);
10616
10617                         dev->dev_addr[5] = lo & 0xff;
10618                         dev->dev_addr[4] = (lo >> 8) & 0xff;
10619                         dev->dev_addr[3] = (lo >> 16) & 0xff;
10620                         dev->dev_addr[2] = (lo >> 24) & 0xff;
10621                         dev->dev_addr[1] = hi & 0xff;
10622                         dev->dev_addr[0] = (hi >> 8) & 0xff;
10623                 }
10624         }
10625
10626         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
10627 #ifdef CONFIG_SPARC64
10628                 if (!tg3_get_default_macaddr_sparc(tp))
10629                         return 0;
10630 #endif
10631                 return -EINVAL;
10632         }
10633         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
10634         return 0;
10635 }
10636
10637 #define BOUNDARY_SINGLE_CACHELINE       1
10638 #define BOUNDARY_MULTI_CACHELINE        2
10639
10640 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
10641 {
10642         int cacheline_size;
10643         u8 byte;
10644         int goal;
10645
10646         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
10647         if (byte == 0)
10648                 cacheline_size = 1024;
10649         else
10650                 cacheline_size = (int) byte * 4;
10651
10652         /* On 5703 and later chips, the boundary bits have no
10653          * effect.
10654          */
10655         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10656             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
10657             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10658                 goto out;
10659
10660 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
10661         goal = BOUNDARY_MULTI_CACHELINE;
10662 #else
10663 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10664         goal = BOUNDARY_SINGLE_CACHELINE;
10665 #else
10666         goal = 0;
10667 #endif
10668 #endif
10669
10670         if (!goal)
10671                 goto out;
10672
10673         /* PCI controllers on most RISC systems tend to disconnect
10674          * when a device tries to burst across a cache-line boundary.
10675          * Therefore, letting tg3 do so just wastes PCI bandwidth.
10676          *
10677          * Unfortunately, for PCI-E there are only limited
10678          * write-side controls for this, and thus for reads
10679          * we will still get the disconnects.  We'll also waste
10680          * these PCI cycles for both read and write for chips
10681          * other than 5700 and 5701 which do not implement the
10682          * boundary bits.
10683          */
10684         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10685             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10686                 switch (cacheline_size) {
10687                 case 16:
10688                 case 32:
10689                 case 64:
10690                 case 128:
10691                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10692                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10693                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10694                         } else {
10695                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10696                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10697                         }
10698                         break;
10699
10700                 case 256:
10701                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10702                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10703                         break;
10704
10705                 default:
10706                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10707                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10708                         break;
10709                 };
10710         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10711                 switch (cacheline_size) {
10712                 case 16:
10713                 case 32:
10714                 case 64:
10715                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10716                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10717                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10718                                 break;
10719                         }
10720                         /* fallthrough */
10721                 case 128:
10722                 default:
10723                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10724                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10725                         break;
10726                 };
10727         } else {
10728                 switch (cacheline_size) {
10729                 case 16:
10730                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10731                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10732                                         DMA_RWCTRL_WRITE_BNDRY_16);
10733                                 break;
10734                         }
10735                         /* fallthrough */
10736                 case 32:
10737                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10738                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10739                                         DMA_RWCTRL_WRITE_BNDRY_32);
10740                                 break;
10741                         }
10742                         /* fallthrough */
10743                 case 64:
10744                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10745                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10746                                         DMA_RWCTRL_WRITE_BNDRY_64);
10747                                 break;
10748                         }
10749                         /* fallthrough */
10750                 case 128:
10751                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10752                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10753                                         DMA_RWCTRL_WRITE_BNDRY_128);
10754                                 break;
10755                         }
10756                         /* fallthrough */
10757                 case 256:
10758                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
10759                                 DMA_RWCTRL_WRITE_BNDRY_256);
10760                         break;
10761                 case 512:
10762                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
10763                                 DMA_RWCTRL_WRITE_BNDRY_512);
10764                         break;
10765                 case 1024:
10766                 default:
10767                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10768                                 DMA_RWCTRL_WRITE_BNDRY_1024);
10769                         break;
10770                 };
10771         }
10772
10773 out:
10774         return val;
10775 }
10776
10777 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10778 {
10779         struct tg3_internal_buffer_desc test_desc;
10780         u32 sram_dma_descs;
10781         int i, ret;
10782
10783         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10784
10785         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10786         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10787         tw32(RDMAC_STATUS, 0);
10788         tw32(WDMAC_STATUS, 0);
10789
10790         tw32(BUFMGR_MODE, 0);
10791         tw32(FTQ_RESET, 0);
10792
10793         test_desc.addr_hi = ((u64) buf_dma) >> 32;
10794         test_desc.addr_lo = buf_dma & 0xffffffff;
10795         test_desc.nic_mbuf = 0x00002100;
10796         test_desc.len = size;
10797
10798         /*
10799          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10800          * the *second* time the tg3 driver was getting loaded after an
10801          * initial scan.
10802          *
10803          * Broadcom tells me:
10804          *   ...the DMA engine is connected to the GRC block and a DMA
10805          *   reset may affect the GRC block in some unpredictable way...
10806          *   The behavior of resets to individual blocks has not been tested.
10807          *
10808          * Broadcom noted the GRC reset will also reset all sub-components.
10809          */
10810         if (to_device) {
10811                 test_desc.cqid_sqid = (13 << 8) | 2;
10812
10813                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10814                 udelay(40);
10815         } else {
10816                 test_desc.cqid_sqid = (16 << 8) | 7;
10817
10818                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10819                 udelay(40);
10820         }
10821         test_desc.flags = 0x00000005;
10822
10823         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10824                 u32 val;
10825
10826                 val = *(((u32 *)&test_desc) + i);
10827                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10828                                        sram_dma_descs + (i * sizeof(u32)));
10829                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10830         }
10831         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10832
10833         if (to_device) {
10834                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10835         } else {
10836                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10837         }
10838
10839         ret = -ENODEV;
10840         for (i = 0; i < 40; i++) {
10841                 u32 val;
10842
10843                 if (to_device)
10844                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10845                 else
10846                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10847                 if ((val & 0xffff) == sram_dma_descs) {
10848                         ret = 0;
10849                         break;
10850                 }
10851
10852                 udelay(100);
10853         }
10854
10855         return ret;
10856 }
10857
10858 #define TEST_BUFFER_SIZE        0x2000
10859
10860 static int __devinit tg3_test_dma(struct tg3 *tp)
10861 {
10862         dma_addr_t buf_dma;
10863         u32 *buf, saved_dma_rwctrl;
10864         int ret;
10865
10866         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10867         if (!buf) {
10868                 ret = -ENOMEM;
10869                 goto out_nofree;
10870         }
10871
10872         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10873                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10874
10875         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10876
10877         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10878                 /* DMA read watermark not used on PCIE */
10879                 tp->dma_rwctrl |= 0x00180000;
10880         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10881                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10882                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10883                         tp->dma_rwctrl |= 0x003f0000;
10884                 else
10885                         tp->dma_rwctrl |= 0x003f000f;
10886         } else {
10887                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10888                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10889                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10890
10891                         /* If the 5704 is behind the EPB bridge, we can
10892                          * do the less restrictive ONE_DMA workaround for
10893                          * better performance.
10894                          */
10895                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
10896                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10897                                 tp->dma_rwctrl |= 0x8000;
10898                         else if (ccval == 0x6 || ccval == 0x7)
10899                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10900
10901                         /* Set bit 23 to enable PCIX hw bug fix */
10902                         tp->dma_rwctrl |= 0x009f0000;
10903                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10904                         /* 5780 always in PCIX mode */
10905                         tp->dma_rwctrl |= 0x00144000;
10906                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10907                         /* 5714 always in PCIX mode */
10908                         tp->dma_rwctrl |= 0x00148000;
10909                 } else {
10910                         tp->dma_rwctrl |= 0x001b000f;
10911                 }
10912         }
10913
10914         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10915             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10916                 tp->dma_rwctrl &= 0xfffffff0;
10917
10918         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10919             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10920                 /* Remove this if it causes problems for some boards. */
10921                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10922
10923                 /* On 5700/5701 chips, we need to set this bit.
10924                  * Otherwise the chip will issue cacheline transactions
10925                  * to streamable DMA memory with not all the byte
10926                  * enables turned on.  This is an error on several
10927                  * RISC PCI controllers, in particular sparc64.
10928                  *
10929                  * On 5703/5704 chips, this bit has been reassigned
10930                  * a different meaning.  In particular, it is used
10931                  * on those chips to enable a PCI-X workaround.
10932                  */
10933                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10934         }
10935
10936         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10937
10938 #if 0
10939         /* Unneeded, already done by tg3_get_invariants.  */
10940         tg3_switch_clocks(tp);
10941 #endif
10942
10943         ret = 0;
10944         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10945             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10946                 goto out;
10947
10948         /* It is best to perform DMA test with maximum write burst size
10949          * to expose the 5700/5701 write DMA bug.
10950          */
10951         saved_dma_rwctrl = tp->dma_rwctrl;
10952         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10953         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10954
10955         while (1) {
10956                 u32 *p = buf, i;
10957
10958                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10959                         p[i] = i;
10960
10961                 /* Send the buffer to the chip. */
10962                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10963                 if (ret) {
10964                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10965                         break;
10966                 }
10967
10968 #if 0
10969                 /* validate data reached card RAM correctly. */
10970                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10971                         u32 val;
10972                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
10973                         if (le32_to_cpu(val) != p[i]) {
10974                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
10975                                 /* ret = -ENODEV here? */
10976                         }
10977                         p[i] = 0;
10978                 }
10979 #endif
10980                 /* Now read it back. */
10981                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10982                 if (ret) {
10983                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10984
10985                         break;
10986                 }
10987
10988                 /* Verify it. */
10989                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10990                         if (p[i] == i)
10991                                 continue;
10992
10993                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10994                             DMA_RWCTRL_WRITE_BNDRY_16) {
10995                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10996                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10997                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10998                                 break;
10999                         } else {
11000                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11001                                 ret = -ENODEV;
11002                                 goto out;
11003                         }
11004                 }
11005
11006                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11007                         /* Success. */
11008                         ret = 0;
11009                         break;
11010                 }
11011         }
11012         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11013             DMA_RWCTRL_WRITE_BNDRY_16) {
11014                 static struct pci_device_id dma_wait_state_chipsets[] = {
11015                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11016                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11017                         { },
11018                 };
11019
11020                 /* DMA test passed without adjusting DMA boundary,
11021                  * now look for chipsets that are known to expose the
11022                  * DMA bug without failing the test.
11023                  */
11024                 if (pci_dev_present(dma_wait_state_chipsets)) {
11025                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11026                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11027                 }
11028                 else
11029                         /* Safe to use the calculated DMA boundary. */
11030                         tp->dma_rwctrl = saved_dma_rwctrl;
11031
11032                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11033         }
11034
11035 out:
11036         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11037 out_nofree:
11038         return ret;
11039 }
11040
11041 static void __devinit tg3_init_link_config(struct tg3 *tp)
11042 {
11043         tp->link_config.advertising =
11044                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11045                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11046                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11047                  ADVERTISED_Autoneg | ADVERTISED_MII);
11048         tp->link_config.speed = SPEED_INVALID;
11049         tp->link_config.duplex = DUPLEX_INVALID;
11050         tp->link_config.autoneg = AUTONEG_ENABLE;
11051         tp->link_config.active_speed = SPEED_INVALID;
11052         tp->link_config.active_duplex = DUPLEX_INVALID;
11053         tp->link_config.phy_is_low_power = 0;
11054         tp->link_config.orig_speed = SPEED_INVALID;
11055         tp->link_config.orig_duplex = DUPLEX_INVALID;
11056         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11057 }
11058
11059 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11060 {
11061         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11062                 tp->bufmgr_config.mbuf_read_dma_low_water =
11063                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11064                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11065                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11066                 tp->bufmgr_config.mbuf_high_water =
11067                         DEFAULT_MB_HIGH_WATER_5705;
11068
11069                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11070                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11071                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11072                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11073                 tp->bufmgr_config.mbuf_high_water_jumbo =
11074                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11075         } else {
11076                 tp->bufmgr_config.mbuf_read_dma_low_water =
11077                         DEFAULT_MB_RDMA_LOW_WATER;
11078                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11079                         DEFAULT_MB_MACRX_LOW_WATER;
11080                 tp->bufmgr_config.mbuf_high_water =
11081                         DEFAULT_MB_HIGH_WATER;
11082
11083                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11084                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11085                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11086                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11087                 tp->bufmgr_config.mbuf_high_water_jumbo =
11088                         DEFAULT_MB_HIGH_WATER_JUMBO;
11089         }
11090
11091         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11092         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11093 }
11094
11095 static char * __devinit tg3_phy_string(struct tg3 *tp)
11096 {
11097         switch (tp->phy_id & PHY_ID_MASK) {
11098         case PHY_ID_BCM5400:    return "5400";
11099         case PHY_ID_BCM5401:    return "5401";
11100         case PHY_ID_BCM5411:    return "5411";
11101         case PHY_ID_BCM5701:    return "5701";
11102         case PHY_ID_BCM5703:    return "5703";
11103         case PHY_ID_BCM5704:    return "5704";
11104         case PHY_ID_BCM5705:    return "5705";
11105         case PHY_ID_BCM5750:    return "5750";
11106         case PHY_ID_BCM5752:    return "5752";
11107         case PHY_ID_BCM5714:    return "5714";
11108         case PHY_ID_BCM5780:    return "5780";
11109         case PHY_ID_BCM5755:    return "5755";
11110         case PHY_ID_BCM5787:    return "5787";
11111         case PHY_ID_BCM8002:    return "8002/serdes";
11112         case 0:                 return "serdes";
11113         default:                return "unknown";
11114         };
11115 }
11116
11117 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11118 {
11119         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11120                 strcpy(str, "PCI Express");
11121                 return str;
11122         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11123                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11124
11125                 strcpy(str, "PCIX:");
11126
11127                 if ((clock_ctrl == 7) ||
11128                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11129                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11130                         strcat(str, "133MHz");
11131                 else if (clock_ctrl == 0)
11132                         strcat(str, "33MHz");
11133                 else if (clock_ctrl == 2)
11134                         strcat(str, "50MHz");
11135                 else if (clock_ctrl == 4)
11136                         strcat(str, "66MHz");
11137                 else if (clock_ctrl == 6)
11138                         strcat(str, "100MHz");
11139         } else {
11140                 strcpy(str, "PCI:");
11141                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11142                         strcat(str, "66MHz");
11143                 else
11144                         strcat(str, "33MHz");
11145         }
11146         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11147                 strcat(str, ":32-bit");
11148         else
11149                 strcat(str, ":64-bit");
11150         return str;
11151 }
11152
11153 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11154 {
11155         struct pci_dev *peer;
11156         unsigned int func, devnr = tp->pdev->devfn & ~7;
11157
11158         for (func = 0; func < 8; func++) {
11159                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11160                 if (peer && peer != tp->pdev)
11161                         break;
11162                 pci_dev_put(peer);
11163         }
11164         /* 5704 can be configured in single-port mode, set peer to
11165          * tp->pdev in that case.
11166          */
11167         if (!peer) {
11168                 peer = tp->pdev;
11169                 return peer;
11170         }
11171
11172         /*
11173          * We don't need to keep the refcount elevated; there's no way
11174          * to remove one half of this device without removing the other
11175          */
11176         pci_dev_put(peer);
11177
11178         return peer;
11179 }
11180
11181 static void __devinit tg3_init_coal(struct tg3 *tp)
11182 {
11183         struct ethtool_coalesce *ec = &tp->coal;
11184
11185         memset(ec, 0, sizeof(*ec));
11186         ec->cmd = ETHTOOL_GCOALESCE;
11187         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11188         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11189         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11190         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11191         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11192         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11193         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11194         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11195         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11196
11197         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11198                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11199                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11200                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11201                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11202                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11203         }
11204
11205         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11206                 ec->rx_coalesce_usecs_irq = 0;
11207                 ec->tx_coalesce_usecs_irq = 0;
11208                 ec->stats_block_coalesce_usecs = 0;
11209         }
11210 }
11211
11212 static int __devinit tg3_init_one(struct pci_dev *pdev,
11213                                   const struct pci_device_id *ent)
11214 {
11215         static int tg3_version_printed = 0;
11216         unsigned long tg3reg_base, tg3reg_len;
11217         struct net_device *dev;
11218         struct tg3 *tp;
11219         int i, err, pm_cap;
11220         char str[40];
11221         u64 dma_mask, persist_dma_mask;
11222
11223         if (tg3_version_printed++ == 0)
11224                 printk(KERN_INFO "%s", version);
11225
11226         err = pci_enable_device(pdev);
11227         if (err) {
11228                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11229                        "aborting.\n");
11230                 return err;
11231         }
11232
11233         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11234                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11235                        "base address, aborting.\n");
11236                 err = -ENODEV;
11237                 goto err_out_disable_pdev;
11238         }
11239
11240         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11241         if (err) {
11242                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11243                        "aborting.\n");
11244                 goto err_out_disable_pdev;
11245         }
11246
11247         pci_set_master(pdev);
11248
11249         /* Find power-management capability. */
11250         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11251         if (pm_cap == 0) {
11252                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11253                        "aborting.\n");
11254                 err = -EIO;
11255                 goto err_out_free_res;
11256         }
11257
11258         tg3reg_base = pci_resource_start(pdev, 0);
11259         tg3reg_len = pci_resource_len(pdev, 0);
11260
11261         dev = alloc_etherdev(sizeof(*tp));
11262         if (!dev) {
11263                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11264                 err = -ENOMEM;
11265                 goto err_out_free_res;
11266         }
11267
11268         SET_MODULE_OWNER(dev);
11269         SET_NETDEV_DEV(dev, &pdev->dev);
11270
11271         dev->features |= NETIF_F_LLTX;
11272 #if TG3_VLAN_TAG_USED
11273         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11274         dev->vlan_rx_register = tg3_vlan_rx_register;
11275         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11276 #endif
11277
11278         tp = netdev_priv(dev);
11279         tp->pdev = pdev;
11280         tp->dev = dev;
11281         tp->pm_cap = pm_cap;
11282         tp->mac_mode = TG3_DEF_MAC_MODE;
11283         tp->rx_mode = TG3_DEF_RX_MODE;
11284         tp->tx_mode = TG3_DEF_TX_MODE;
11285         tp->mi_mode = MAC_MI_MODE_BASE;
11286         if (tg3_debug > 0)
11287                 tp->msg_enable = tg3_debug;
11288         else
11289                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11290
11291         /* The word/byte swap controls here control register access byte
11292          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11293          * setting below.
11294          */
11295         tp->misc_host_ctrl =
11296                 MISC_HOST_CTRL_MASK_PCI_INT |
11297                 MISC_HOST_CTRL_WORD_SWAP |
11298                 MISC_HOST_CTRL_INDIR_ACCESS |
11299                 MISC_HOST_CTRL_PCISTATE_RW;
11300
11301         /* The NONFRM (non-frame) byte/word swap controls take effect
11302          * on descriptor entries, anything which isn't packet data.
11303          *
11304          * The StrongARM chips on the board (one for tx, one for rx)
11305          * are running in big-endian mode.
11306          */
11307         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11308                         GRC_MODE_WSWAP_NONFRM_DATA);
11309 #ifdef __BIG_ENDIAN
11310         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11311 #endif
11312         spin_lock_init(&tp->lock);
11313         spin_lock_init(&tp->tx_lock);
11314         spin_lock_init(&tp->indirect_lock);
11315         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11316
11317         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11318         if (tp->regs == 0UL) {
11319                 printk(KERN_ERR PFX "Cannot map device registers, "
11320                        "aborting.\n");
11321                 err = -ENOMEM;
11322                 goto err_out_free_dev;
11323         }
11324
11325         tg3_init_link_config(tp);
11326
11327         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11328         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11329         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11330
11331         dev->open = tg3_open;
11332         dev->stop = tg3_close;
11333         dev->get_stats = tg3_get_stats;
11334         dev->set_multicast_list = tg3_set_rx_mode;
11335         dev->set_mac_address = tg3_set_mac_addr;
11336         dev->do_ioctl = tg3_ioctl;
11337         dev->tx_timeout = tg3_tx_timeout;
11338         dev->poll = tg3_poll;
11339         dev->ethtool_ops = &tg3_ethtool_ops;
11340         dev->weight = 64;
11341         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11342         dev->change_mtu = tg3_change_mtu;
11343         dev->irq = pdev->irq;
11344 #ifdef CONFIG_NET_POLL_CONTROLLER
11345         dev->poll_controller = tg3_poll_controller;
11346 #endif
11347
11348         err = tg3_get_invariants(tp);
11349         if (err) {
11350                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11351                        "aborting.\n");
11352                 goto err_out_iounmap;
11353         }
11354
11355         /* The EPB bridge inside 5714, 5715, and 5780 and any
11356          * device behind the EPB cannot support DMA addresses > 40-bit.
11357          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11358          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11359          * do DMA address check in tg3_start_xmit().
11360          */
11361         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11362                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11363         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11364                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11365 #ifdef CONFIG_HIGHMEM
11366                 dma_mask = DMA_64BIT_MASK;
11367 #endif
11368         } else
11369                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11370
11371         /* Configure DMA attributes. */
11372         if (dma_mask > DMA_32BIT_MASK) {
11373                 err = pci_set_dma_mask(pdev, dma_mask);
11374                 if (!err) {
11375                         dev->features |= NETIF_F_HIGHDMA;
11376                         err = pci_set_consistent_dma_mask(pdev,
11377                                                           persist_dma_mask);
11378                         if (err < 0) {
11379                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11380                                        "DMA for consistent allocations\n");
11381                                 goto err_out_iounmap;
11382                         }
11383                 }
11384         }
11385         if (err || dma_mask == DMA_32BIT_MASK) {
11386                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11387                 if (err) {
11388                         printk(KERN_ERR PFX "No usable DMA configuration, "
11389                                "aborting.\n");
11390                         goto err_out_iounmap;
11391                 }
11392         }
11393
11394         tg3_init_bufmgr_config(tp);
11395
11396 #if TG3_TSO_SUPPORT != 0
11397         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11398                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11399         }
11400         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11401             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11402             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11403             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11404                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11405         } else {
11406                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11407         }
11408
11409         /* TSO is on by default on chips that support hardware TSO.
11410          * Firmware TSO on older chips gives lower performance, so it
11411          * is off by default, but can be enabled using ethtool.
11412          */
11413         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
11414                 dev->features |= NETIF_F_TSO;
11415
11416 #endif
11417
11418         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11419             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11420             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11421                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11422                 tp->rx_pending = 63;
11423         }
11424
11425         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11426             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11427                 tp->pdev_peer = tg3_find_peer(tp);
11428
11429         err = tg3_get_device_address(tp);
11430         if (err) {
11431                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11432                        "aborting.\n");
11433                 goto err_out_iounmap;
11434         }
11435
11436         /*
11437          * Reset chip in case UNDI or EFI driver did not shutdown
11438          * DMA self test will enable WDMAC and we'll see (spurious)
11439          * pending DMA on the PCI bus at that point.
11440          */
11441         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11442             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11443                 pci_save_state(tp->pdev);
11444                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11445                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11446         }
11447
11448         err = tg3_test_dma(tp);
11449         if (err) {
11450                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11451                 goto err_out_iounmap;
11452         }
11453
11454         /* Tigon3 can do ipv4 only... and some chips have buggy
11455          * checksumming.
11456          */
11457         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11458                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11459                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11460                         dev->features |= NETIF_F_HW_CSUM;
11461                 else
11462                         dev->features |= NETIF_F_IP_CSUM;
11463                 dev->features |= NETIF_F_SG;
11464                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11465         } else
11466                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11467
11468         /* flow control autonegotiation is default behavior */
11469         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11470
11471         tg3_init_coal(tp);
11472
11473         /* Now that we have fully setup the chip, save away a snapshot
11474          * of the PCI config space.  We need to restore this after
11475          * GRC_MISC_CFG core clock resets and some resume events.
11476          */
11477         pci_save_state(tp->pdev);
11478
11479         err = register_netdev(dev);
11480         if (err) {
11481                 printk(KERN_ERR PFX "Cannot register net device, "
11482                        "aborting.\n");
11483                 goto err_out_iounmap;
11484         }
11485
11486         pci_set_drvdata(pdev, dev);
11487
11488         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11489                dev->name,
11490                tp->board_part_number,
11491                tp->pci_chip_rev_id,
11492                tg3_phy_string(tp),
11493                tg3_bus_string(tp, str),
11494                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11495
11496         for (i = 0; i < 6; i++)
11497                 printk("%2.2x%c", dev->dev_addr[i],
11498                        i == 5 ? '\n' : ':');
11499
11500         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11501                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11502                "TSOcap[%d] \n",
11503                dev->name,
11504                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11505                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11506                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11507                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11508                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11509                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11510                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11511         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11512                dev->name, tp->dma_rwctrl,
11513                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11514                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11515
11516         netif_carrier_off(tp->dev);
11517
11518         return 0;
11519
11520 err_out_iounmap:
11521         if (tp->regs) {
11522                 iounmap(tp->regs);
11523                 tp->regs = NULL;
11524         }
11525
11526 err_out_free_dev:
11527         free_netdev(dev);
11528
11529 err_out_free_res:
11530         pci_release_regions(pdev);
11531
11532 err_out_disable_pdev:
11533         pci_disable_device(pdev);
11534         pci_set_drvdata(pdev, NULL);
11535         return err;
11536 }
11537
11538 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11539 {
11540         struct net_device *dev = pci_get_drvdata(pdev);
11541
11542         if (dev) {
11543                 struct tg3 *tp = netdev_priv(dev);
11544
11545                 flush_scheduled_work();
11546                 unregister_netdev(dev);
11547                 if (tp->regs) {
11548                         iounmap(tp->regs);
11549                         tp->regs = NULL;
11550                 }
11551                 free_netdev(dev);
11552                 pci_release_regions(pdev);
11553                 pci_disable_device(pdev);
11554                 pci_set_drvdata(pdev, NULL);
11555         }
11556 }
11557
11558 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11559 {
11560         struct net_device *dev = pci_get_drvdata(pdev);
11561         struct tg3 *tp = netdev_priv(dev);
11562         int err;
11563
11564         if (!netif_running(dev))
11565                 return 0;
11566
11567         flush_scheduled_work();
11568         tg3_netif_stop(tp);
11569
11570         del_timer_sync(&tp->timer);
11571
11572         tg3_full_lock(tp, 1);
11573         tg3_disable_ints(tp);
11574         tg3_full_unlock(tp);
11575
11576         netif_device_detach(dev);
11577
11578         tg3_full_lock(tp, 0);
11579         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11580         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
11581         tg3_full_unlock(tp);
11582
11583         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
11584         if (err) {
11585                 tg3_full_lock(tp, 0);
11586
11587                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11588                 tg3_init_hw(tp);
11589
11590                 tp->timer.expires = jiffies + tp->timer_offset;
11591                 add_timer(&tp->timer);
11592
11593                 netif_device_attach(dev);
11594                 tg3_netif_start(tp);
11595
11596                 tg3_full_unlock(tp);
11597         }
11598
11599         return err;
11600 }
11601
11602 static int tg3_resume(struct pci_dev *pdev)
11603 {
11604         struct net_device *dev = pci_get_drvdata(pdev);
11605         struct tg3 *tp = netdev_priv(dev);
11606         int err;
11607
11608         if (!netif_running(dev))
11609                 return 0;
11610
11611         pci_restore_state(tp->pdev);
11612
11613         err = tg3_set_power_state(tp, PCI_D0);
11614         if (err)
11615                 return err;
11616
11617         netif_device_attach(dev);
11618
11619         tg3_full_lock(tp, 0);
11620
11621         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11622         tg3_init_hw(tp);
11623
11624         tp->timer.expires = jiffies + tp->timer_offset;
11625         add_timer(&tp->timer);
11626
11627         tg3_netif_start(tp);
11628
11629         tg3_full_unlock(tp);
11630
11631         return 0;
11632 }
11633
11634 static struct pci_driver tg3_driver = {
11635         .name           = DRV_MODULE_NAME,
11636         .id_table       = tg3_pci_tbl,
11637         .probe          = tg3_init_one,
11638         .remove         = __devexit_p(tg3_remove_one),
11639         .suspend        = tg3_suspend,
11640         .resume         = tg3_resume
11641 };
11642
11643 static int __init tg3_init(void)
11644 {
11645         return pci_module_init(&tg3_driver);
11646 }
11647
11648 static void __exit tg3_cleanup(void)
11649 {
11650         pci_unregister_driver(&tg3_driver);
11651 }
11652
11653 module_init(tg3_init);
11654 module_exit(tg3_cleanup);