drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.97"
  72 #define DRV_MODULE_RELDATE      "December 10, 2008"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 #define TG3_RAW_IP_ALIGN 2
 135
 136 /* number of ETHTOOL_GSTATS u64's */
 137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 138
 139 #define TG3_NUM_TEST            6
 140
 141 #define FIRMWARE_TG3            "tigon/tg3.bin"
 142 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 143 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 144
 145 static char version[] __devinitdata =
 146         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 147
 148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 150 MODULE_LICENSE("GPL");
 151 MODULE_VERSION(DRV_MODULE_VERSION);
 152 MODULE_FIRMWARE(FIRMWARE_TG3);
 153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 155
 156
 157 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 158 module_param(tg3_debug, int, 0);
 159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 160
 161 static struct pci_device_id tg3_pci_tbl[] = {
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 234         {}
 235 };
 236
 237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 238
 239 static const struct {
 240         const char string[ETH_GSTRING_LEN];
 241 } ethtool_stats_keys[TG3_NUM_STATS] = {
 242         { "rx_octets" },
 243         { "rx_fragments" },
 244         { "rx_ucast_packets" },
 245         { "rx_mcast_packets" },
 246         { "rx_bcast_packets" },
 247         { "rx_fcs_errors" },
 248         { "rx_align_errors" },
 249         { "rx_xon_pause_rcvd" },
 250         { "rx_xoff_pause_rcvd" },
 251         { "rx_mac_ctrl_rcvd" },
 252         { "rx_xoff_entered" },
 253         { "rx_frame_too_long_errors" },
 254         { "rx_jabbers" },
 255         { "rx_undersize_packets" },
 256         { "rx_in_length_errors" },
 257         { "rx_out_length_errors" },
 258         { "rx_64_or_less_octet_packets" },
 259         { "rx_65_to_127_octet_packets" },
 260         { "rx_128_to_255_octet_packets" },
 261         { "rx_256_to_511_octet_packets" },
 262         { "rx_512_to_1023_octet_packets" },
 263         { "rx_1024_to_1522_octet_packets" },
 264         { "rx_1523_to_2047_octet_packets" },
 265         { "rx_2048_to_4095_octet_packets" },
 266         { "rx_4096_to_8191_octet_packets" },
 267         { "rx_8192_to_9022_octet_packets" },
 268
 269         { "tx_octets" },
 270         { "tx_collisions" },
 271
 272         { "tx_xon_sent" },
 273         { "tx_xoff_sent" },
 274         { "tx_flow_control" },
 275         { "tx_mac_errors" },
 276         { "tx_single_collisions" },
 277         { "tx_mult_collisions" },
 278         { "tx_deferred" },
 279         { "tx_excessive_collisions" },
 280         { "tx_late_collisions" },
 281         { "tx_collide_2times" },
 282         { "tx_collide_3times" },
 283         { "tx_collide_4times" },
 284         { "tx_collide_5times" },
 285         { "tx_collide_6times" },
 286         { "tx_collide_7times" },
 287         { "tx_collide_8times" },
 288         { "tx_collide_9times" },
 289         { "tx_collide_10times" },
 290         { "tx_collide_11times" },
 291         { "tx_collide_12times" },
 292         { "tx_collide_13times" },
 293         { "tx_collide_14times" },
 294         { "tx_collide_15times" },
 295         { "tx_ucast_packets" },
 296         { "tx_mcast_packets" },
 297         { "tx_bcast_packets" },
 298         { "tx_carrier_sense_errors" },
 299         { "tx_discards" },
 300         { "tx_errors" },
 301
 302         { "dma_writeq_full" },
 303         { "dma_write_prioq_full" },
 304         { "rxbds_empty" },
 305         { "rx_discards" },
 306         { "rx_errors" },
 307         { "rx_threshold_hit" },
 308
 309         { "dma_readq_full" },
 310         { "dma_read_prioq_full" },
 311         { "tx_comp_queue_full" },
 312
 313         { "ring_set_send_prod_index" },
 314         { "ring_status_update" },
 315         { "nic_irqs" },
 316         { "nic_avoided_irqs" },
 317         { "nic_tx_threshold_hit" }
 318 };
 319
 320 static const struct {
 321         const char string[ETH_GSTRING_LEN];
 322 } ethtool_test_keys[TG3_NUM_TEST] = {
 323         { "nvram test     (online) " },
 324         { "link test      (online) " },
 325         { "register test  (offline)" },
 326         { "memory test    (offline)" },
 327         { "loopback test  (offline)" },
 328         { "interrupt test (offline)" },
 329 };
 330
 331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 332 {
 333         writel(val, tp->regs + off);
 334 }
 335
 336 static u32 tg3_read32(struct tg3 *tp, u32 off)
 337 {
 338         return (readl(tp->regs + off));
 339 }
 340
 341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         writel(val, tp->aperegs + off);
 344 }
 345
 346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 347 {
 348         return (readl(tp->aperegs + off));
 349 }
 350
 351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         unsigned long flags;
 354
 355         spin_lock_irqsave(&tp->indirect_lock, flags);
 356         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 357         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 358         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 359 }
 360
 361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->regs + off);
 364         readl(tp->regs + off);
 365 }
 366
 367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 368 {
 369         unsigned long flags;
 370         u32 val;
 371
 372         spin_lock_irqsave(&tp->indirect_lock, flags);
 373         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 374         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 375         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 376         return val;
 377 }
 378
 379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         unsigned long flags;
 382
 383         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 384                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 385                                        TG3_64BIT_REG_LOW, val);
 386                 return;
 387         }
 388         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 389                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 390                                        TG3_64BIT_REG_LOW, val);
 391                 return;
 392         }
 393
 394         spin_lock_irqsave(&tp->indirect_lock, flags);
 395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 396         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 398
 399         /* In indirect mode when disabling interrupts, we also need
 400          * to clear the interrupt bit in the GRC local ctrl register.
 401          */
 402         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 403             (val == 0x1)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 405                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 406         }
 407 }
 408
 409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 410 {
 411         unsigned long flags;
 412         u32 val;
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418         return val;
 419 }
 420
 421 /* usec_wait specifies the wait time in usec when writing to certain registers
 422  * where it is unsafe to read back the register without some delay.
 423  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 424  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 425  */
 426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 427 {
 428         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 429             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 430                 /* Non-posted methods */
 431                 tp->write32(tp, off, val);
 432         else {
 433                 /* Posted method */
 434                 tg3_write32(tp, off, val);
 435                 if (usec_wait)
 436                         udelay(usec_wait);
 437                 tp->read32(tp, off);
 438         }
 439         /* Wait again after the read for the posted method to guarantee that
 440          * the wait time is met.
 441          */
 442         if (usec_wait)
 443                 udelay(usec_wait);
 444 }
 445
 446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 447 {
 448         tp->write32_mbox(tp, off, val);
 449         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 450             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 451                 tp->read32_mbox(tp, off);
 452 }
 453
 454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 455 {
 456         void __iomem *mbox = tp->regs + off;
 457         writel(val, mbox);
 458         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 459                 writel(val, mbox);
 460         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 461                 readl(mbox);
 462 }
 463
 464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 465 {
 466         return (readl(tp->regs + off + GRCMBOX_BASE));
 467 }
 468
 469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 470 {
 471         writel(val, tp->regs + off + GRCMBOX_BASE);
 472 }
 473
 474 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 475 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 476 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 477 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 478 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 479
 480 #define tw32(reg,val)           tp->write32(tp, reg, val)
 481 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 483 #define tr32(reg)               tp->read32(tp, reg)
 484
 485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 486 {
 487         unsigned long flags;
 488
 489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 490             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 491                 return;
 492
 493         spin_lock_irqsave(&tp->indirect_lock, flags);
 494         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 495                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 496                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 497
 498                 /* Always leave this as zero. */
 499                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 500         } else {
 501                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         }
 507         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 508 }
 509
 510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 511 {
 512         unsigned long flags;
 513
 514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 515             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 516                 *val = 0;
 517                 return;
 518         }
 519
 520         spin_lock_irqsave(&tp->indirect_lock, flags);
 521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 524
 525                 /* Always leave this as zero. */
 526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 527         } else {
 528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 530
 531                 /* Always leave this as zero. */
 532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 533         }
 534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 535 }
 536
 537 static void tg3_ape_lock_init(struct tg3 *tp)
 538 {
 539         int i;
 540
 541         /* Make sure the driver hasn't any stale locks. */
 542         for (i = 0; i < 8; i++)
 543                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 544                                 APE_LOCK_GRANT_DRIVER);
 545 }
 546
 547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 548 {
 549         int i, off;
 550         int ret = 0;
 551         u32 status;
 552
 553         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 554                 return 0;
 555
 556         switch (locknum) {
 557                 case TG3_APE_LOCK_GRC:
 558                 case TG3_APE_LOCK_MEM:
 559                         break;
 560                 default:
 561                         return -EINVAL;
 562         }
 563
 564         off = 4 * locknum;
 565
 566         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 567
 568         /* Wait for up to 1 millisecond to acquire lock. */
 569         for (i = 0; i < 100; i++) {
 570                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 571                 if (status == APE_LOCK_GRANT_DRIVER)
 572                         break;
 573                 udelay(10);
 574         }
 575
 576         if (status != APE_LOCK_GRANT_DRIVER) {
 577                 /* Revoke the lock request. */
 578                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 579                                 APE_LOCK_GRANT_DRIVER);
 580
 581                 ret = -EBUSY;
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 588 {
 589         int off;
 590
 591         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 592                 return;
 593
 594         switch (locknum) {
 595                 case TG3_APE_LOCK_GRC:
 596                 case TG3_APE_LOCK_MEM:
 597                         break;
 598                 default:
 599                         return;
 600         }
 601
 602         off = 4 * locknum;
 603         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 604 }
 605
 606 static void tg3_disable_ints(struct tg3 *tp)
 607 {
 608         tw32(TG3PCI_MISC_HOST_CTRL,
 609              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 611 }
 612
 613 static inline void tg3_cond_int(struct tg3 *tp)
 614 {
 615         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 616             (tp->hw_status->status & SD_STATUS_UPDATED))
 617                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 618         else
 619                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 620                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 621 }
 622
 623 static void tg3_enable_ints(struct tg3 *tp)
 624 {
 625         tp->irq_sync = 0;
 626         wmb();
 627
 628         tw32(TG3PCI_MISC_HOST_CTRL,
 629              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 630         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 631                        (tp->last_tag << 24));
 632         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 633                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 634                                (tp->last_tag << 24));
 635         tg3_cond_int(tp);
 636 }
 637
 638 static inline unsigned int tg3_has_work(struct tg3 *tp)
 639 {
 640         struct tg3_hw_status *sblk = tp->hw_status;
 641         unsigned int work_exists = 0;
 642
 643         /* check for phy events */
 644         if (!(tp->tg3_flags &
 645               (TG3_FLAG_USE_LINKCHG_REG |
 646                TG3_FLAG_POLL_SERDES))) {
 647                 if (sblk->status & SD_STATUS_LINK_CHG)
 648                         work_exists = 1;
 649         }
 650         /* check for RX/TX work to do */
 651         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 652             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 653                 work_exists = 1;
 654
 655         return work_exists;
 656 }
 657
 658 /* tg3_restart_ints
 659  *  similar to tg3_enable_ints, but it accurately determines whether there
 660  *  is new work pending and can return without flushing the PIO write
 661  *  which reenables interrupts
 662  */
 663 static void tg3_restart_ints(struct tg3 *tp)
 664 {
 665         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 666                      tp->last_tag << 24);
 667         mmiowb();
 668
 669         /* When doing tagged status, this work check is unnecessary.
 670          * The last_tag we write above tells the chip which piece of
 671          * work we've completed.
 672          */
 673         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 674             tg3_has_work(tp))
 675                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 676                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 677 }
 678
 679 static inline void tg3_netif_stop(struct tg3 *tp)
 680 {
 681         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 682         napi_disable(&tp->napi);
 683         netif_tx_disable(tp->dev);
 684 }
 685
 686 static inline void tg3_netif_start(struct tg3 *tp)
 687 {
 688         netif_wake_queue(tp->dev);
 689         /* NOTE: unconditional netif_wake_queue is only appropriate
 690          * so long as all callers are assured to have free tx slots
 691          * (such as after tg3_init_hw)
 692          */
 693         napi_enable(&tp->napi);
 694         tp->hw_status->status |= SD_STATUS_UPDATED;
 695         tg3_enable_ints(tp);
 696 }
 697
 698 static void tg3_switch_clocks(struct tg3 *tp)
 699 {
 700         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 701         u32 orig_clock_ctrl;
 702
 703         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 704             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 705                 return;
 706
 707         orig_clock_ctrl = clock_ctrl;
 708         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 709                        CLOCK_CTRL_CLKRUN_OENABLE |
 710                        0x1f);
 711         tp->pci_clock_ctrl = clock_ctrl;
 712
 713         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 714                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 715                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 716                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 717                 }
 718         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 719                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 720                             clock_ctrl |
 721                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 722                             40);
 723                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 724                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 725                             40);
 726         }
 727         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 728 }
 729
 730 #define PHY_BUSY_LOOPS  5000
 731
 732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 733 {
 734         u32 frame_val;
 735         unsigned int loops;
 736         int ret;
 737
 738         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 739                 tw32_f(MAC_MI_MODE,
 740                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 741                 udelay(80);
 742         }
 743
 744         *val = 0x0;
 745
 746         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 747                       MI_COM_PHY_ADDR_MASK);
 748         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 749                       MI_COM_REG_ADDR_MASK);
 750         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 751
 752         tw32_f(MAC_MI_COM, frame_val);
 753
 754         loops = PHY_BUSY_LOOPS;
 755         while (loops != 0) {
 756                 udelay(10);
 757                 frame_val = tr32(MAC_MI_COM);
 758
 759                 if ((frame_val & MI_COM_BUSY) == 0) {
 760                         udelay(5);
 761                         frame_val = tr32(MAC_MI_COM);
 762                         break;
 763                 }
 764                 loops -= 1;
 765         }
 766
 767         ret = -EBUSY;
 768         if (loops != 0) {
 769                 *val = frame_val & MI_COM_DATA_MASK;
 770                 ret = 0;
 771         }
 772
 773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 774                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 775                 udelay(80);
 776         }
 777
 778         return ret;
 779 }
 780
 781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 782 {
 783         u32 frame_val;
 784         unsigned int loops;
 785         int ret;
 786
 787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 788             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 789                 return 0;
 790
 791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 792                 tw32_f(MAC_MI_MODE,
 793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 794                 udelay(80);
 795         }
 796
 797         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 798                       MI_COM_PHY_ADDR_MASK);
 799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 800                       MI_COM_REG_ADDR_MASK);
 801         frame_val |= (val & MI_COM_DATA_MASK);
 802         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 803
 804         tw32_f(MAC_MI_COM, frame_val);
 805
 806         loops = PHY_BUSY_LOOPS;
 807         while (loops != 0) {
 808                 udelay(10);
 809                 frame_val = tr32(MAC_MI_COM);
 810                 if ((frame_val & MI_COM_BUSY) == 0) {
 811                         udelay(5);
 812                         frame_val = tr32(MAC_MI_COM);
 813                         break;
 814                 }
 815                 loops -= 1;
 816         }
 817
 818         ret = -EBUSY;
 819         if (loops != 0)
 820                 ret = 0;
 821
 822         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 823                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 824                 udelay(80);
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int tg3_bmcr_reset(struct tg3 *tp)
 831 {
 832         u32 phy_control;
 833         int limit, err;
 834
 835         /* OK, reset it, and poll the BMCR_RESET bit until it
 836          * clears or we time out.
 837          */
 838         phy_control = BMCR_RESET;
 839         err = tg3_writephy(tp, MII_BMCR, phy_control);
 840         if (err != 0)
 841                 return -EBUSY;
 842
 843         limit = 5000;
 844         while (limit--) {
 845                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 846                 if (err != 0)
 847                         return -EBUSY;
 848
 849                 if ((phy_control & BMCR_RESET) == 0) {
 850                         udelay(40);
 851                         break;
 852                 }
 853                 udelay(10);
 854         }
 855         if (limit < 0)
 856                 return -EBUSY;
 857
 858         return 0;
 859 }
 860
 861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 862 {
 863         struct tg3 *tp = bp->priv;
 864         u32 val;
 865
 866         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 867                 return -EAGAIN;
 868
 869         if (tg3_readphy(tp, reg, &val))
 870                 return -EIO;
 871
 872         return val;
 873 }
 874
 875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 876 {
 877         struct tg3 *tp = bp->priv;
 878
 879         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 880                 return -EAGAIN;
 881
 882         if (tg3_writephy(tp, reg, val))
 883                 return -EIO;
 884
 885         return 0;
 886 }
 887
 888 static int tg3_mdio_reset(struct mii_bus *bp)
 889 {
 890         return 0;
 891 }
 892
 893 static void tg3_mdio_config_5785(struct tg3 *tp)
 894 {
 895         u32 val;
 896         struct phy_device *phydev;
 897
 898         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 899         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 900         case TG3_PHY_ID_BCM50610:
 901                 val = MAC_PHYCFG2_50610_LED_MODES;
 902                 break;
 903         case TG3_PHY_ID_BCMAC131:
 904                 val = MAC_PHYCFG2_AC131_LED_MODES;
 905                 break;
 906         case TG3_PHY_ID_RTL8211C:
 907                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 908                 break;
 909         case TG3_PHY_ID_RTL8201E:
 910                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 911                 break;
 912         default:
 913                 return;
 914         }
 915
 916         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 917                 tw32(MAC_PHYCFG2, val);
 918
 919                 val = tr32(MAC_PHYCFG1);
 920                 val &= ~MAC_PHYCFG1_RGMII_INT;
 921                 tw32(MAC_PHYCFG1, val);
 922
 923                 return;
 924         }
 925
 926         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 927                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 928                        MAC_PHYCFG2_FMODE_MASK_MASK |
 929                        MAC_PHYCFG2_GMODE_MASK_MASK |
 930                        MAC_PHYCFG2_ACT_MASK_MASK   |
 931                        MAC_PHYCFG2_QUAL_MASK_MASK |
 932                        MAC_PHYCFG2_INBAND_ENABLE;
 933
 934         tw32(MAC_PHYCFG2, val);
 935
 936         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
 937                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
 938         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 939                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 940                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 941                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 942                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 943         }
 944         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
 945
 946         val = tr32(MAC_EXT_RGMII_MODE);
 947         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 948                  MAC_RGMII_MODE_RX_QUALITY |
 949                  MAC_RGMII_MODE_RX_ACTIVITY |
 950                  MAC_RGMII_MODE_RX_ENG_DET |
 951                  MAC_RGMII_MODE_TX_ENABLE |
 952                  MAC_RGMII_MODE_TX_LOWPWR |
 953                  MAC_RGMII_MODE_TX_RESET);
 954         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 955                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 956                         val |= MAC_RGMII_MODE_RX_INT_B |
 957                                MAC_RGMII_MODE_RX_QUALITY |
 958                                MAC_RGMII_MODE_RX_ACTIVITY |
 959                                MAC_RGMII_MODE_RX_ENG_DET;
 960                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 961                         val |= MAC_RGMII_MODE_TX_ENABLE |
 962                                MAC_RGMII_MODE_TX_LOWPWR |
 963                                MAC_RGMII_MODE_TX_RESET;
 964         }
 965         tw32(MAC_EXT_RGMII_MODE, val);
 966 }
 967
 968 static void tg3_mdio_start(struct tg3 *tp)
 969 {
 970         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 971                 mutex_lock(&tp->mdio_bus->mdio_lock);
 972                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 973                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 974         }
 975
 976         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 977         tw32_f(MAC_MI_MODE, tp->mi_mode);
 978         udelay(80);
 979
 980         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
 981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
 982                 tg3_mdio_config_5785(tp);
 983 }
 984
 985 static void tg3_mdio_stop(struct tg3 *tp)
 986 {
 987         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 988                 mutex_lock(&tp->mdio_bus->mdio_lock);
 989                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 990                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 991         }
 992 }
 993
 994 static int tg3_mdio_init(struct tg3 *tp)
 995 {
 996         int i;
 997         u32 reg;
 998         struct phy_device *phydev;
 999
1000         tg3_mdio_start(tp);
1001
1002         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004                 return 0;
1005
1006         tp->mdio_bus = mdiobus_alloc();
1007         if (tp->mdio_bus == NULL)
1008                 return -ENOMEM;
1009
1010         tp->mdio_bus->name     = "tg3 mdio bus";
1011         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013         tp->mdio_bus->priv     = tp;
1014         tp->mdio_bus->parent   = &tp->pdev->dev;
1015         tp->mdio_bus->read     = &tg3_mdio_read;
1016         tp->mdio_bus->write    = &tg3_mdio_write;
1017         tp->mdio_bus->reset    = &tg3_mdio_reset;
1018         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1020
1021         for (i = 0; i < PHY_MAX_ADDR; i++)
1022                 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024         /* The bus registration will look for all the PHYs on the mdio bus.
1025          * Unfortunately, it does not ensure the PHY is powered up before
1026          * accessing the PHY ID registers.  A chip reset is the
1027          * quickest way to bring the device back to an operational state..
1028          */
1029         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030                 tg3_bmcr_reset(tp);
1031
1032         i = mdiobus_register(tp->mdio_bus);
1033         if (i) {
1034                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035                         tp->dev->name, i);
1036                 mdiobus_free(tp->mdio_bus);
1037                 return i;
1038         }
1039
1040         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042         if (!phydev || !phydev->drv) {
1043                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044                 mdiobus_unregister(tp->mdio_bus);
1045                 mdiobus_free(tp->mdio_bus);
1046                 return -ENODEV;
1047         }
1048
1049         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050         case TG3_PHY_ID_BCM57780:
1051                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052                 break;
1053         case TG3_PHY_ID_BCM50610:
1054                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060                 /* fallthru */
1061         case TG3_PHY_ID_RTL8211C:
1062                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063                 break;
1064         case TG3_PHY_ID_RTL8201E:
1065         case TG3_PHY_ID_BCMAC131:
1066                 phydev->interface = PHY_INTERFACE_MODE_MII;
1067                 break;
1068         }
1069
1070         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073                 tg3_mdio_config_5785(tp);
1074
1075         return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082                 mdiobus_unregister(tp->mdio_bus);
1083                 mdiobus_free(tp->mdio_bus);
1084                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085         }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091         u32 val;
1092
1093         val = tr32(GRC_RX_CPU_EVENT);
1094         val |= GRC_RX_CPU_DRIVER_EVENT;
1095         tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097         tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105         int i;
1106         unsigned int delay_cnt;
1107         long time_remain;
1108
1109         /* If enough time has passed, no wait is necessary. */
1110         time_remain = (long)(tp->last_event_jiffies + 1 +
1111                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112                       (long)jiffies;
1113         if (time_remain < 0)
1114                 return;
1115
1116         /* Check if we can shorten the wait time. */
1117         delay_cnt = jiffies_to_usecs(time_remain);
1118         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120         delay_cnt = (delay_cnt >> 3) + 1;
1121
1122         for (i = 0; i < delay_cnt; i++) {
1123                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124                         break;
1125                 udelay(8);
1126         }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132         u32 reg;
1133         u32 val;
1134
1135         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1137                 return;
1138
1139         tg3_wait_for_event_ack(tp);
1140
1141         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145         val = 0;
1146         if (!tg3_readphy(tp, MII_BMCR, &reg))
1147                 val = reg << 16;
1148         if (!tg3_readphy(tp, MII_BMSR, &reg))
1149                 val |= (reg & 0xffff);
1150         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152         val = 0;
1153         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154                 val = reg << 16;
1155         if (!tg3_readphy(tp, MII_LPA, &reg))
1156                 val |= (reg & 0xffff);
1157         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159         val = 0;
1160         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162                         val = reg << 16;
1163                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164                         val |= (reg & 0xffff);
1165         }
1166         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169                 val = reg << 16;
1170         else
1171                 val = 0;
1172         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174         tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179         if (!netif_carrier_ok(tp->dev)) {
1180                 if (netif_msg_link(tp))
1181                         printk(KERN_INFO PFX "%s: Link is down.\n",
1182                                tp->dev->name);
1183                 tg3_ump_link_report(tp);
1184         } else if (netif_msg_link(tp)) {
1185                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186                        tp->dev->name,
1187                        (tp->link_config.active_speed == SPEED_1000 ?
1188                         1000 :
1189                         (tp->link_config.active_speed == SPEED_100 ?
1190                          100 : 10)),
1191                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1192                         "full" : "half"));
1193
1194                 printk(KERN_INFO PFX
1195                        "%s: Flow control is %s for TX and %s for RX.\n",
1196                        tp->dev->name,
1197                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198                        "on" : "off",
1199                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200                        "on" : "off");
1201                 tg3_ump_link_report(tp);
1202         }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207         u16 miireg;
1208
1209         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210                 miireg = ADVERTISE_PAUSE_CAP;
1211         else if (flow_ctrl & FLOW_CTRL_TX)
1212                 miireg = ADVERTISE_PAUSE_ASYM;
1213         else if (flow_ctrl & FLOW_CTRL_RX)
1214                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215         else
1216                 miireg = 0;
1217
1218         return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223         u16 miireg;
1224
1225         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226                 miireg = ADVERTISE_1000XPAUSE;
1227         else if (flow_ctrl & FLOW_CTRL_TX)
1228                 miireg = ADVERTISE_1000XPSE_ASYM;
1229         else if (flow_ctrl & FLOW_CTRL_RX)
1230                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231         else
1232                 miireg = 0;
1233
1234         return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239         u8 cap = 0;
1240
1241         if (lcladv & ADVERTISE_1000XPAUSE) {
1242                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243                         if (rmtadv & LPA_1000XPAUSE)
1244                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246                                 cap = FLOW_CTRL_RX;
1247                 } else {
1248                         if (rmtadv & LPA_1000XPAUSE)
1249                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250                 }
1251         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253                         cap = FLOW_CTRL_TX;
1254         }
1255
1256         return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261         u8 autoneg;
1262         u8 flowctrl = 0;
1263         u32 old_rx_mode = tp->rx_mode;
1264         u32 old_tx_mode = tp->tx_mode;
1265
1266         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268         else
1269                 autoneg = tp->link_config.autoneg;
1270
1271         if (autoneg == AUTONEG_ENABLE &&
1272             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275                 else
1276                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277         } else
1278                 flowctrl = tp->link_config.flowctrl;
1279
1280         tp->link_config.active_flowctrl = flowctrl;
1281
1282         if (flowctrl & FLOW_CTRL_RX)
1283                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284         else
1285                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287         if (old_rx_mode != tp->rx_mode)
1288                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290         if (flowctrl & FLOW_CTRL_TX)
1291                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292         else
1293                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295         if (old_tx_mode != tp->tx_mode)
1296                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301         u8 oldflowctrl, linkmesg = 0;
1302         u32 mac_mode, lcl_adv, rmt_adv;
1303         struct tg3 *tp = netdev_priv(dev);
1304         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306         spin_lock(&tp->lock);
1307
1308         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309                                     MAC_MODE_HALF_DUPLEX);
1310
1311         oldflowctrl = tp->link_config.active_flowctrl;
1312
1313         if (phydev->link) {
1314                 lcl_adv = 0;
1315                 rmt_adv = 0;
1316
1317                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1319                 else
1320                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322                 if (phydev->duplex == DUPLEX_HALF)
1323                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1324                 else {
1325                         lcl_adv = tg3_advert_flowctrl_1000T(
1326                                   tp->link_config.flowctrl);
1327
1328                         if (phydev->pause)
1329                                 rmt_adv = LPA_PAUSE_CAP;
1330                         if (phydev->asym_pause)
1331                                 rmt_adv |= LPA_PAUSE_ASYM;
1332                 }
1333
1334                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335         } else
1336                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338         if (mac_mode != tp->mac_mode) {
1339                 tp->mac_mode = mac_mode;
1340                 tw32_f(MAC_MODE, tp->mac_mode);
1341                 udelay(40);
1342         }
1343
1344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345                 if (phydev->speed == SPEED_10)
1346                         tw32(MAC_MI_STAT,
1347                              MAC_MI_STAT_10MBPS_MODE |
1348                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349                 else
1350                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351         }
1352
1353         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354                 tw32(MAC_TX_LENGTHS,
1355                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356                       (6 << TX_LENGTHS_IPG_SHIFT) |
1357                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358         else
1359                 tw32(MAC_TX_LENGTHS,
1360                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361                       (6 << TX_LENGTHS_IPG_SHIFT) |
1362                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366             phydev->speed != tp->link_config.active_speed ||
1367             phydev->duplex != tp->link_config.active_duplex ||
1368             oldflowctrl != tp->link_config.active_flowctrl)
1369             linkmesg = 1;
1370
1371         tp->link_config.active_speed = phydev->speed;
1372         tp->link_config.active_duplex = phydev->duplex;
1373
1374         spin_unlock(&tp->lock);
1375
1376         if (linkmesg)
1377                 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382         struct phy_device *phydev;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385                 return 0;
1386
1387         /* Bring the PHY back to a known state. */
1388         tg3_bmcr_reset(tp);
1389
1390         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392         /* Attach the MAC to the PHY. */
1393         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394                              phydev->dev_flags, phydev->interface);
1395         if (IS_ERR(phydev)) {
1396                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397                 return PTR_ERR(phydev);
1398         }
1399
1400         /* Mask with MAC supported features. */
1401         switch (phydev->interface) {
1402         case PHY_INTERFACE_MODE_GMII:
1403         case PHY_INTERFACE_MODE_RGMII:
1404                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405                         phydev->supported &= (PHY_GBIT_FEATURES |
1406                                               SUPPORTED_Pause |
1407                                               SUPPORTED_Asym_Pause);
1408                         break;
1409                 }
1410                 /* fallthru */
1411         case PHY_INTERFACE_MODE_MII:
1412                 phydev->supported &= (PHY_BASIC_FEATURES |
1413                                       SUPPORTED_Pause |
1414                                       SUPPORTED_Asym_Pause);
1415                 break;
1416         default:
1417                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418                 return -EINVAL;
1419         }
1420
1421         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423         phydev->advertising = phydev->supported;
1424
1425         return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430         struct phy_device *phydev;
1431
1432         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433                 return;
1434
1435         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437         if (tp->link_config.phy_is_low_power) {
1438                 tp->link_config.phy_is_low_power = 0;
1439                 phydev->speed = tp->link_config.orig_speed;
1440                 phydev->duplex = tp->link_config.orig_duplex;
1441                 phydev->autoneg = tp->link_config.orig_autoneg;
1442                 phydev->advertising = tp->link_config.orig_advertising;
1443         }
1444
1445         phy_start(phydev);
1446
1447         phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453                 return;
1454
1455         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463         }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474         u32 reg;
1475
1476         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1478                 return;
1479
1480         reg = MII_TG3_MISC_SHDW_WREN |
1481               MII_TG3_MISC_SHDW_SCR5_SEL |
1482               MII_TG3_MISC_SHDW_SCR5_LPED |
1483               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484               MII_TG3_MISC_SHDW_SCR5_SDTL |
1485               MII_TG3_MISC_SHDW_SCR5_C125OE;
1486         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492         reg = MII_TG3_MISC_SHDW_WREN |
1493               MII_TG3_MISC_SHDW_APD_SEL |
1494               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495         if (enable)
1496                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499 }
1500
1501 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502 {
1503         u32 phy;
1504
1505         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507                 return;
1508
1509         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510                 u32 ephy;
1511
1512                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1515                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516                                 if (enable)
1517                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518                                 else
1519                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521                         }
1522                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523                 }
1524         } else {
1525                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1527                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529                         if (enable)
1530                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531                         else
1532                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1534                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535                 }
1536         }
1537 }
1538
1539 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540 {
1541         u32 val;
1542
1543         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544                 return;
1545
1546         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549                              (val | (1 << 15) | (1 << 4)));
1550 }
1551
1552 static void tg3_phy_apply_otp(struct tg3 *tp)
1553 {
1554         u32 otp, phy;
1555
1556         if (!tp->phy_otp)
1557                 return;
1558
1559         otp = tp->phy_otp;
1560
1561         /* Enable SM_DSP clock and tx 6dB coding. */
1562         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564               MII_TG3_AUXCTL_ACTL_TX_6DB;
1565         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589         /* Turn off SM_DSP clock. */
1590         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591               MII_TG3_AUXCTL_ACTL_TX_6DB;
1592         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593 }
1594
1595 static int tg3_wait_macro_done(struct tg3 *tp)
1596 {
1597         int limit = 100;
1598
1599         while (limit--) {
1600                 u32 tmp32;
1601
1602                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603                         if ((tmp32 & 0x1000) == 0)
1604                                 break;
1605                 }
1606         }
1607         if (limit < 0)
1608                 return -EBUSY;
1609
1610         return 0;
1611 }
1612
1613 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614 {
1615         static const u32 test_pat[4][6] = {
1616         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620         };
1621         int chan;
1622
1623         for (chan = 0; chan < 4; chan++) {
1624                 int i;
1625
1626                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627                              (chan * 0x2000) | 0x0200);
1628                 tg3_writephy(tp, 0x16, 0x0002);
1629
1630                 for (i = 0; i < 6; i++)
1631                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632                                      test_pat[chan][i]);
1633
1634                 tg3_writephy(tp, 0x16, 0x0202);
1635                 if (tg3_wait_macro_done(tp)) {
1636                         *resetp = 1;
1637                         return -EBUSY;
1638                 }
1639
1640                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641                              (chan * 0x2000) | 0x0200);
1642                 tg3_writephy(tp, 0x16, 0x0082);
1643                 if (tg3_wait_macro_done(tp)) {
1644                         *resetp = 1;
1645                         return -EBUSY;
1646                 }
1647
1648                 tg3_writephy(tp, 0x16, 0x0802);
1649                 if (tg3_wait_macro_done(tp)) {
1650                         *resetp = 1;
1651                         return -EBUSY;
1652                 }
1653
1654                 for (i = 0; i < 6; i += 2) {
1655                         u32 low, high;
1656
1657                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659                             tg3_wait_macro_done(tp)) {
1660                                 *resetp = 1;
1661                                 return -EBUSY;
1662                         }
1663                         low &= 0x7fff;
1664                         high &= 0x000f;
1665                         if (low != test_pat[chan][i] ||
1666                             high != test_pat[chan][i+1]) {
1667                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671                                 return -EBUSY;
1672                         }
1673                 }
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680 {
1681         int chan;
1682
1683         for (chan = 0; chan < 4; chan++) {
1684                 int i;
1685
1686                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687                              (chan * 0x2000) | 0x0200);
1688                 tg3_writephy(tp, 0x16, 0x0002);
1689                 for (i = 0; i < 6; i++)
1690                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691                 tg3_writephy(tp, 0x16, 0x0202);
1692                 if (tg3_wait_macro_done(tp))
1693                         return -EBUSY;
1694         }
1695
1696         return 0;
1697 }
1698
1699 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700 {
1701         u32 reg32, phy9_orig;
1702         int retries, do_phy_reset, err;
1703
1704         retries = 10;
1705         do_phy_reset = 1;
1706         do {
1707                 if (do_phy_reset) {
1708                         err = tg3_bmcr_reset(tp);
1709                         if (err)
1710                                 return err;
1711                         do_phy_reset = 0;
1712                 }
1713
1714                 /* Disable transmitter and interrupt.  */
1715                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716                         continue;
1717
1718                 reg32 |= 0x3000;
1719                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721                 /* Set full-duplex, 1000 mbps.  */
1722                 tg3_writephy(tp, MII_BMCR,
1723                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725                 /* Set to master mode.  */
1726                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727                         continue;
1728
1729                 tg3_writephy(tp, MII_TG3_CTRL,
1730                              (MII_TG3_CTRL_AS_MASTER |
1731                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733                 /* Enable SM_DSP_CLOCK and 6dB.  */
1734                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736                 /* Block the PHY control access.  */
1737                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741                 if (!err)
1742                         break;
1743         } while (--retries);
1744
1745         err = tg3_phy_reset_chanpat(tp);
1746         if (err)
1747                 return err;
1748
1749         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753         tg3_writephy(tp, 0x16, 0x0000);
1754
1755         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757                 /* Set Extended packet length bit for jumbo frames */
1758                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759         }
1760         else {
1761                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762         }
1763
1764         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767                 reg32 &= ~0x3000;
1768                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769         } else if (!err)
1770                 err = -EBUSY;
1771
1772         return err;
1773 }
1774
1775 /* This will reset the tigon3 PHY if there is no valid
1776  * link unless the FORCE argument is non-zero.
1777  */
1778 static int tg3_phy_reset(struct tg3 *tp)
1779 {
1780         u32 cpmuctrl;
1781         u32 phy_status;
1782         int err;
1783
1784         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785                 u32 val;
1786
1787                 val = tr32(GRC_MISC_CFG);
1788                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789                 udelay(40);
1790         }
1791         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1792         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793         if (err != 0)
1794                 return -EBUSY;
1795
1796         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797                 netif_carrier_off(tp->dev);
1798                 tg3_link_report(tp);
1799         }
1800
1801         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804                 err = tg3_phy_reset_5703_4_5(tp);
1805                 if (err)
1806                         return err;
1807                 goto out;
1808         }
1809
1810         cpmuctrl = 0;
1811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815                         tw32(TG3_CPMU_CTRL,
1816                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817         }
1818
1819         err = tg3_bmcr_reset(tp);
1820         if (err)
1821                 return err;
1822
1823         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824                 u32 phy;
1825
1826                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830         }
1831
1832         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1834                 u32 val;
1835
1836                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1839                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840                         udelay(40);
1841                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842                 }
1843         }
1844
1845         tg3_phy_apply_otp(tp);
1846
1847         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848                 tg3_phy_toggle_apd(tp, true);
1849         else
1850                 tg3_phy_toggle_apd(tp, false);
1851
1852 out:
1853         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860         }
1861         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862                 tg3_writephy(tp, 0x1c, 0x8d68);
1863                 tg3_writephy(tp, 0x1c, 0x8d68);
1864         }
1865         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874         }
1875         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1878                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880                         tg3_writephy(tp, MII_TG3_TEST1,
1881                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1882                 } else
1883                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1884                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885         }
1886         /* Set Extended packet length bit (bit 14) on all chips that */
1887         /* support jumbo frames */
1888         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889                 /* Cannot do read-modify-write on 5401 */
1890                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1891         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1892                 u32 phy_reg;
1893
1894                 /* Set bit 14 with read-modify-write to preserve other bits */
1895                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898         }
1899
1900         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901          * jumbo frames transmission.
1902          */
1903         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1904                 u32 phy_reg;
1905
1906                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909         }
1910
1911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1912                 /* adjust output voltage */
1913                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1914         }
1915
1916         tg3_phy_toggle_automdix(tp, 1);
1917         tg3_phy_set_wirespeed(tp);
1918         return 0;
1919 }
1920
1921 static void tg3_frob_aux_power(struct tg3 *tp)
1922 {
1923         struct tg3 *tp_peer = tp;
1924
1925         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1926                 return;
1927
1928         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930                 struct net_device *dev_peer;
1931
1932                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1933                 /* remove_one() may have been run on the peer. */
1934                 if (!dev_peer)
1935                         tp_peer = tp;
1936                 else
1937                         tp_peer = netdev_priv(dev_peer);
1938         }
1939
1940         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1941             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1944                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1946                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947                                     (GRC_LCLCTRL_GPIO_OE0 |
1948                                      GRC_LCLCTRL_GPIO_OE1 |
1949                                      GRC_LCLCTRL_GPIO_OE2 |
1950                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1951                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1952                                     100);
1953                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1954                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1956                                              GRC_LCLCTRL_GPIO_OE1 |
1957                                              GRC_LCLCTRL_GPIO_OE2 |
1958                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1959                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1960                                              tp->grc_local_ctrl;
1961                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1962
1963                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1964                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1965
1966                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1967                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1968                 } else {
1969                         u32 no_gpio2;
1970                         u32 grc_local_ctrl = 0;
1971
1972                         if (tp_peer != tp &&
1973                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1974                                 return;
1975
1976                         /* Workaround to prevent overdrawing Amps. */
1977                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1978                             ASIC_REV_5714) {
1979                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1980                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1981                                             grc_local_ctrl, 100);
1982                         }
1983
1984                         /* On 5753 and variants, GPIO2 cannot be used. */
1985                         no_gpio2 = tp->nic_sram_data_cfg &
1986                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1987
1988                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1989                                          GRC_LCLCTRL_GPIO_OE1 |
1990                                          GRC_LCLCTRL_GPIO_OE2 |
1991                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1992                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1993                         if (no_gpio2) {
1994                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1995                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1996                         }
1997                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1998                                                     grc_local_ctrl, 100);
1999
2000                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2001
2002                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2003                                                     grc_local_ctrl, 100);
2004
2005                         if (!no_gpio2) {
2006                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2007                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2008                                             grc_local_ctrl, 100);
2009                         }
2010                 }
2011         } else {
2012                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2013                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2014                         if (tp_peer != tp &&
2015                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2016                                 return;
2017
2018                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019                                     (GRC_LCLCTRL_GPIO_OE1 |
2020                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2021
2022                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2023                                     GRC_LCLCTRL_GPIO_OE1, 100);
2024
2025                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026                                     (GRC_LCLCTRL_GPIO_OE1 |
2027                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2028                 }
2029         }
2030 }
2031
2032 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2033 {
2034         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2035                 return 1;
2036         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2037                 if (speed != SPEED_10)
2038                         return 1;
2039         } else if (speed == SPEED_10)
2040                 return 1;
2041
2042         return 0;
2043 }
2044
2045 static int tg3_setup_phy(struct tg3 *, int);
2046
2047 #define RESET_KIND_SHUTDOWN     0
2048 #define RESET_KIND_INIT         1
2049 #define RESET_KIND_SUSPEND      2
2050
2051 static void tg3_write_sig_post_reset(struct tg3 *, int);
2052 static int tg3_halt_cpu(struct tg3 *, u32);
2053
2054 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2055 {
2056         u32 val;
2057
2058         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2059                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2060                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2061                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2062
2063                         sg_dig_ctrl |=
2064                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2065                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2066                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2067                 }
2068                 return;
2069         }
2070
2071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2072                 tg3_bmcr_reset(tp);
2073                 val = tr32(GRC_MISC_CFG);
2074                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2075                 udelay(40);
2076                 return;
2077         } else if (do_low_power) {
2078                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2079                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2080
2081                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2082                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2083                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2084                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2085                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2086         }
2087
2088         /* The PHY should not be powered down on some chips because
2089          * of bugs.
2090          */
2091         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2092             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2093             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2094              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2095                 return;
2096
2097         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2098             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2099                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2100                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2101                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2102                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2103         }
2104
2105         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2106 }
2107
2108 /* tp->lock is held. */
2109 static int tg3_nvram_lock(struct tg3 *tp)
2110 {
2111         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2112                 int i;
2113
2114                 if (tp->nvram_lock_cnt == 0) {
2115                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2116                         for (i = 0; i < 8000; i++) {
2117                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2118                                         break;
2119                                 udelay(20);
2120                         }
2121                         if (i == 8000) {
2122                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2123                                 return -ENODEV;
2124                         }
2125                 }
2126                 tp->nvram_lock_cnt++;
2127         }
2128         return 0;
2129 }
2130
2131 /* tp->lock is held. */
2132 static void tg3_nvram_unlock(struct tg3 *tp)
2133 {
2134         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2135                 if (tp->nvram_lock_cnt > 0)
2136                         tp->nvram_lock_cnt--;
2137                 if (tp->nvram_lock_cnt == 0)
2138                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2139         }
2140 }
2141
2142 /* tp->lock is held. */
2143 static void tg3_enable_nvram_access(struct tg3 *tp)
2144 {
2145         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2146             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2147                 u32 nvaccess = tr32(NVRAM_ACCESS);
2148
2149                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2150         }
2151 }
2152
2153 /* tp->lock is held. */
2154 static void tg3_disable_nvram_access(struct tg3 *tp)
2155 {
2156         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2157             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2158                 u32 nvaccess = tr32(NVRAM_ACCESS);
2159
2160                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2161         }
2162 }
2163
2164 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2165                                         u32 offset, u32 *val)
2166 {
2167         u32 tmp;
2168         int i;
2169
2170         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2171                 return -EINVAL;
2172
2173         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2174                                         EEPROM_ADDR_DEVID_MASK |
2175                                         EEPROM_ADDR_READ);
2176         tw32(GRC_EEPROM_ADDR,
2177              tmp |
2178              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2179              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2180               EEPROM_ADDR_ADDR_MASK) |
2181              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2182
2183         for (i = 0; i < 1000; i++) {
2184                 tmp = tr32(GRC_EEPROM_ADDR);
2185
2186                 if (tmp & EEPROM_ADDR_COMPLETE)
2187                         break;
2188                 msleep(1);
2189         }
2190         if (!(tmp & EEPROM_ADDR_COMPLETE))
2191                 return -EBUSY;
2192
2193         *val = tr32(GRC_EEPROM_DATA);
2194         return 0;
2195 }
2196
2197 #define NVRAM_CMD_TIMEOUT 10000
2198
2199 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2200 {
2201         int i;
2202
2203         tw32(NVRAM_CMD, nvram_cmd);
2204         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2205                 udelay(10);
2206                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2207                         udelay(10);
2208                         break;
2209                 }
2210         }
2211
2212         if (i == NVRAM_CMD_TIMEOUT)
2213                 return -EBUSY;
2214
2215         return 0;
2216 }
2217
2218 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2219 {
2220         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2221             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2222             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2223            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2224             (tp->nvram_jedecnum == JEDEC_ATMEL))
2225
2226                 addr = ((addr / tp->nvram_pagesize) <<
2227                         ATMEL_AT45DB0X1B_PAGE_POS) +
2228                        (addr % tp->nvram_pagesize);
2229
2230         return addr;
2231 }
2232
2233 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2234 {
2235         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2236             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2237             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2238            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2239             (tp->nvram_jedecnum == JEDEC_ATMEL))
2240
2241                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2242                         tp->nvram_pagesize) +
2243                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2244
2245         return addr;
2246 }
2247
2248 /* NOTE: Data read in from NVRAM is byteswapped according to
2249  * the byteswapping settings for all other register accesses.
2250  * tg3 devices are BE devices, so on a BE machine, the data
2251  * returned will be exactly as it is seen in NVRAM.  On a LE
2252  * machine, the 32-bit value will be byteswapped.
2253  */
2254 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2255 {
2256         int ret;
2257
2258         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2259                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2260
2261         offset = tg3_nvram_phys_addr(tp, offset);
2262
2263         if (offset > NVRAM_ADDR_MSK)
2264                 return -EINVAL;
2265
2266         ret = tg3_nvram_lock(tp);
2267         if (ret)
2268                 return ret;
2269
2270         tg3_enable_nvram_access(tp);
2271
2272         tw32(NVRAM_ADDR, offset);
2273         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2274                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2275
2276         if (ret == 0)
2277                 *val = tr32(NVRAM_RDDATA);
2278
2279         tg3_disable_nvram_access(tp);
2280
2281         tg3_nvram_unlock(tp);
2282
2283         return ret;
2284 }
2285
2286 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
2287 {
2288         int err;
2289         u32 tmp;
2290
2291         err = tg3_nvram_read(tp, offset, &tmp);
2292         *val = swab32(tmp);
2293         return err;
2294 }
2295
2296 /* Ensures NVRAM data is in bytestream format. */
2297 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2298 {
2299         u32 v;
2300         int res = tg3_nvram_read(tp, offset, &v);
2301         if (!res)
2302                 *val = cpu_to_be32(v);
2303         return res;
2304 }
2305
2306 /* tp->lock is held. */
2307 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2308 {
2309         u32 addr_high, addr_low;
2310         int i;
2311
2312         addr_high = ((tp->dev->dev_addr[0] << 8) |
2313                      tp->dev->dev_addr[1]);
2314         addr_low = ((tp->dev->dev_addr[2] << 24) |
2315                     (tp->dev->dev_addr[3] << 16) |
2316                     (tp->dev->dev_addr[4] <<  8) |
2317                     (tp->dev->dev_addr[5] <<  0));
2318         for (i = 0; i < 4; i++) {
2319                 if (i == 1 && skip_mac_1)
2320                         continue;
2321                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2322                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2323         }
2324
2325         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2326             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2327                 for (i = 0; i < 12; i++) {
2328                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2329                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2330                 }
2331         }
2332
2333         addr_high = (tp->dev->dev_addr[0] +
2334                      tp->dev->dev_addr[1] +
2335                      tp->dev->dev_addr[2] +
2336                      tp->dev->dev_addr[3] +
2337                      tp->dev->dev_addr[4] +
2338                      tp->dev->dev_addr[5]) &
2339                 TX_BACKOFF_SEED_MASK;
2340         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2341 }
2342
2343 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2344 {
2345         u32 misc_host_ctrl;
2346         bool device_should_wake, do_low_power;
2347
2348         /* Make sure register accesses (indirect or otherwise)
2349          * will function correctly.
2350          */
2351         pci_write_config_dword(tp->pdev,
2352                                TG3PCI_MISC_HOST_CTRL,
2353                                tp->misc_host_ctrl);
2354
2355         switch (state) {
2356         case PCI_D0:
2357                 pci_enable_wake(tp->pdev, state, false);
2358                 pci_set_power_state(tp->pdev, PCI_D0);
2359
2360                 /* Switch out of Vaux if it is a NIC */
2361                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2362                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2363
2364                 return 0;
2365
2366         case PCI_D1:
2367         case PCI_D2:
2368         case PCI_D3hot:
2369                 break;
2370
2371         default:
2372                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2373                         tp->dev->name, state);
2374                 return -EINVAL;
2375         }
2376
2377         /* Restore the CLKREQ setting. */
2378         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2379                 u16 lnkctl;
2380
2381                 pci_read_config_word(tp->pdev,
2382                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2383                                      &lnkctl);
2384                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2385                 pci_write_config_word(tp->pdev,
2386                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2387                                       lnkctl);
2388         }
2389
2390         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2391         tw32(TG3PCI_MISC_HOST_CTRL,
2392              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2393
2394         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2395                              device_may_wakeup(&tp->pdev->dev) &&
2396                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2397
2398         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2399                 do_low_power = false;
2400                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2401                     !tp->link_config.phy_is_low_power) {
2402                         struct phy_device *phydev;
2403                         u32 phyid, advertising;
2404
2405                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2406
2407                         tp->link_config.phy_is_low_power = 1;
2408
2409                         tp->link_config.orig_speed = phydev->speed;
2410                         tp->link_config.orig_duplex = phydev->duplex;
2411                         tp->link_config.orig_autoneg = phydev->autoneg;
2412                         tp->link_config.orig_advertising = phydev->advertising;
2413
2414                         advertising = ADVERTISED_TP |
2415                                       ADVERTISED_Pause |
2416                                       ADVERTISED_Autoneg |
2417                                       ADVERTISED_10baseT_Half;
2418
2419                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2420                             device_should_wake) {
2421                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2422                                         advertising |=
2423                                                 ADVERTISED_100baseT_Half |
2424                                                 ADVERTISED_100baseT_Full |
2425                                                 ADVERTISED_10baseT_Full;
2426                                 else
2427                                         advertising |= ADVERTISED_10baseT_Full;
2428                         }
2429
2430                         phydev->advertising = advertising;
2431
2432                         phy_start_aneg(phydev);
2433
2434                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2435                         if (phyid != TG3_PHY_ID_BCMAC131) {
2436                                 phyid &= TG3_PHY_OUI_MASK;
2437                                 if (phyid == TG3_PHY_OUI_1 ||
2438                                     phyid == TG3_PHY_OUI_2 ||
2439                                     phyid == TG3_PHY_OUI_3)
2440                                         do_low_power = true;
2441                         }
2442                 }
2443         } else {
2444                 do_low_power = true;
2445
2446                 if (tp->link_config.phy_is_low_power == 0) {
2447                         tp->link_config.phy_is_low_power = 1;
2448                         tp->link_config.orig_speed = tp->link_config.speed;
2449                         tp->link_config.orig_duplex = tp->link_config.duplex;
2450                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2451                 }
2452
2453                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2454                         tp->link_config.speed = SPEED_10;
2455                         tp->link_config.duplex = DUPLEX_HALF;
2456                         tp->link_config.autoneg = AUTONEG_ENABLE;
2457                         tg3_setup_phy(tp, 0);
2458                 }
2459         }
2460
2461         __tg3_set_mac_addr(tp, 0);
2462
2463         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2464                 u32 val;
2465
2466                 val = tr32(GRC_VCPU_EXT_CTRL);
2467                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2468         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2469                 int i;
2470                 u32 val;
2471
2472                 for (i = 0; i < 200; i++) {
2473                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2474                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2475                                 break;
2476                         msleep(1);
2477                 }
2478         }
2479         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2480                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2481                                                      WOL_DRV_STATE_SHUTDOWN |
2482                                                      WOL_DRV_WOL |
2483                                                      WOL_SET_MAGIC_PKT);
2484
2485         if (device_should_wake) {
2486                 u32 mac_mode;
2487
2488                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2489                         if (do_low_power) {
2490                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2491                                 udelay(40);
2492                         }
2493
2494                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2495                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2496                         else
2497                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2498
2499                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2500                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2501                             ASIC_REV_5700) {
2502                                 u32 speed = (tp->tg3_flags &
2503                                              TG3_FLAG_WOL_SPEED_100MB) ?
2504                                              SPEED_100 : SPEED_10;
2505                                 if (tg3_5700_link_polarity(tp, speed))
2506                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2507                                 else
2508                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2509                         }
2510                 } else {
2511                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2512                 }
2513
2514                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2515                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2516
2517                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2518                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2519                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2520                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2521                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2522                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2523
2524                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2525                         mac_mode |= tp->mac_mode &
2526                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2527                         if (mac_mode & MAC_MODE_APE_TX_EN)
2528                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2529                 }
2530
2531                 tw32_f(MAC_MODE, mac_mode);
2532                 udelay(100);
2533
2534                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2535                 udelay(10);
2536         }
2537
2538         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2539             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2540              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2541                 u32 base_val;
2542
2543                 base_val = tp->pci_clock_ctrl;
2544                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2545                              CLOCK_CTRL_TXCLK_DISABLE);
2546
2547                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2548                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2549         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2550                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2551                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2552                 /* do nothing */
2553         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2554                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2555                 u32 newbits1, newbits2;
2556
2557                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2558                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2559                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2560                                     CLOCK_CTRL_TXCLK_DISABLE |
2561                                     CLOCK_CTRL_ALTCLK);
2562                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2563                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2564                         newbits1 = CLOCK_CTRL_625_CORE;
2565                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2566                 } else {
2567                         newbits1 = CLOCK_CTRL_ALTCLK;
2568                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2569                 }
2570
2571                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2572                             40);
2573
2574                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2575                             40);
2576
2577                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2578                         u32 newbits3;
2579
2580                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2581                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2582                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2583                                             CLOCK_CTRL_TXCLK_DISABLE |
2584                                             CLOCK_CTRL_44MHZ_CORE);
2585                         } else {
2586                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2587                         }
2588
2589                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2590                                     tp->pci_clock_ctrl | newbits3, 40);
2591                 }
2592         }
2593
2594         if (!(device_should_wake) &&
2595             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2596                 tg3_power_down_phy(tp, do_low_power);
2597
2598         tg3_frob_aux_power(tp);
2599
2600         /* Workaround for unstable PLL clock */
2601         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2602             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2603                 u32 val = tr32(0x7d00);
2604
2605                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2606                 tw32(0x7d00, val);
2607                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2608                         int err;
2609
2610                         err = tg3_nvram_lock(tp);
2611                         tg3_halt_cpu(tp, RX_CPU_BASE);
2612                         if (!err)
2613                                 tg3_nvram_unlock(tp);
2614                 }
2615         }
2616
2617         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2618
2619         if (device_should_wake)
2620                 pci_enable_wake(tp->pdev, state, true);
2621
2622         /* Finally, set the new power state. */
2623         pci_set_power_state(tp->pdev, state);
2624
2625         return 0;
2626 }
2627
2628 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2629 {
2630         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2631         case MII_TG3_AUX_STAT_10HALF:
2632                 *speed = SPEED_10;
2633                 *duplex = DUPLEX_HALF;
2634                 break;
2635
2636         case MII_TG3_AUX_STAT_10FULL:
2637                 *speed = SPEED_10;
2638                 *duplex = DUPLEX_FULL;
2639                 break;
2640
2641         case MII_TG3_AUX_STAT_100HALF:
2642                 *speed = SPEED_100;
2643                 *duplex = DUPLEX_HALF;
2644                 break;
2645
2646         case MII_TG3_AUX_STAT_100FULL:
2647                 *speed = SPEED_100;
2648                 *duplex = DUPLEX_FULL;
2649                 break;
2650
2651         case MII_TG3_AUX_STAT_1000HALF:
2652                 *speed = SPEED_1000;
2653                 *duplex = DUPLEX_HALF;
2654                 break;
2655
2656         case MII_TG3_AUX_STAT_1000FULL:
2657                 *speed = SPEED_1000;
2658                 *duplex = DUPLEX_FULL;
2659                 break;
2660
2661         default:
2662                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2663                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2664                                  SPEED_10;
2665                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2666                                   DUPLEX_HALF;
2667                         break;
2668                 }
2669                 *speed = SPEED_INVALID;
2670                 *duplex = DUPLEX_INVALID;
2671                 break;
2672         }
2673 }
2674
2675 static void tg3_phy_copper_begin(struct tg3 *tp)
2676 {
2677         u32 new_adv;
2678         int i;
2679
2680         if (tp->link_config.phy_is_low_power) {
2681                 /* Entering low power mode.  Disable gigabit and
2682                  * 100baseT advertisements.
2683                  */
2684                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2685
2686                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2687                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2688                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2689                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2690
2691                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2692         } else if (tp->link_config.speed == SPEED_INVALID) {
2693                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2694                         tp->link_config.advertising &=
2695                                 ~(ADVERTISED_1000baseT_Half |
2696                                   ADVERTISED_1000baseT_Full);
2697
2698                 new_adv = ADVERTISE_CSMA;
2699                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2700                         new_adv |= ADVERTISE_10HALF;
2701                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2702                         new_adv |= ADVERTISE_10FULL;
2703                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2704                         new_adv |= ADVERTISE_100HALF;
2705                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2706                         new_adv |= ADVERTISE_100FULL;
2707
2708                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2709
2710                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2711
2712                 if (tp->link_config.advertising &
2713                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2714                         new_adv = 0;
2715                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2716                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2717                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2718                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2719                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2720                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2721                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2722                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2723                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2724                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2725                 } else {
2726                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2727                 }
2728         } else {
2729                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2730                 new_adv |= ADVERTISE_CSMA;
2731
2732                 /* Asking for a specific link mode. */
2733                 if (tp->link_config.speed == SPEED_1000) {
2734                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2735
2736                         if (tp->link_config.duplex == DUPLEX_FULL)
2737                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2738                         else
2739                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2740                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2741                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2742                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2743                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2744                 } else {
2745                         if (tp->link_config.speed == SPEED_100) {
2746                                 if (tp->link_config.duplex == DUPLEX_FULL)
2747                                         new_adv |= ADVERTISE_100FULL;
2748                                 else
2749                                         new_adv |= ADVERTISE_100HALF;
2750                         } else {
2751                                 if (tp->link_config.duplex == DUPLEX_FULL)
2752                                         new_adv |= ADVERTISE_10FULL;
2753                                 else
2754                                         new_adv |= ADVERTISE_10HALF;
2755                         }
2756                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2757
2758                         new_adv = 0;
2759                 }
2760
2761                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2762         }
2763
2764         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2765             tp->link_config.speed != SPEED_INVALID) {
2766                 u32 bmcr, orig_bmcr;
2767
2768                 tp->link_config.active_speed = tp->link_config.speed;
2769                 tp->link_config.active_duplex = tp->link_config.duplex;
2770
2771                 bmcr = 0;
2772                 switch (tp->link_config.speed) {
2773                 default:
2774                 case SPEED_10:
2775                         break;
2776
2777                 case SPEED_100:
2778                         bmcr |= BMCR_SPEED100;
2779                         break;
2780
2781                 case SPEED_1000:
2782                         bmcr |= TG3_BMCR_SPEED1000;
2783                         break;
2784                 }
2785
2786                 if (tp->link_config.duplex == DUPLEX_FULL)
2787                         bmcr |= BMCR_FULLDPLX;
2788
2789                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2790                     (bmcr != orig_bmcr)) {
2791                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2792                         for (i = 0; i < 1500; i++) {
2793                                 u32 tmp;
2794
2795                                 udelay(10);
2796                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2797                                     tg3_readphy(tp, MII_BMSR, &tmp))
2798                                         continue;
2799                                 if (!(tmp & BMSR_LSTATUS)) {
2800                                         udelay(40);
2801                                         break;
2802                                 }
2803                         }
2804                         tg3_writephy(tp, MII_BMCR, bmcr);
2805                         udelay(40);
2806                 }
2807         } else {
2808                 tg3_writephy(tp, MII_BMCR,
2809                              BMCR_ANENABLE | BMCR_ANRESTART);
2810         }
2811 }
2812
2813 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2814 {
2815         int err;
2816
2817         /* Turn off tap power management. */
2818         /* Set Extended packet length bit */
2819         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2820
2821         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2822         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2823
2824         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2825         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2826
2827         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2828         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2829
2830         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2831         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2832
2833         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2834         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2835
2836         udelay(40);
2837
2838         return err;
2839 }
2840
2841 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2842 {
2843         u32 adv_reg, all_mask = 0;
2844
2845         if (mask & ADVERTISED_10baseT_Half)
2846                 all_mask |= ADVERTISE_10HALF;
2847         if (mask & ADVERTISED_10baseT_Full)
2848                 all_mask |= ADVERTISE_10FULL;
2849         if (mask & ADVERTISED_100baseT_Half)
2850                 all_mask |= ADVERTISE_100HALF;
2851         if (mask & ADVERTISED_100baseT_Full)
2852                 all_mask |= ADVERTISE_100FULL;
2853
2854         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2855                 return 0;
2856
2857         if ((adv_reg & all_mask) != all_mask)
2858                 return 0;
2859         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2860                 u32 tg3_ctrl;
2861
2862                 all_mask = 0;
2863                 if (mask & ADVERTISED_1000baseT_Half)
2864                         all_mask |= ADVERTISE_1000HALF;
2865                 if (mask & ADVERTISED_1000baseT_Full)
2866                         all_mask |= ADVERTISE_1000FULL;
2867
2868                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2869                         return 0;
2870
2871                 if ((tg3_ctrl & all_mask) != all_mask)
2872                         return 0;
2873         }
2874         return 1;
2875 }
2876
2877 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2878 {
2879         u32 curadv, reqadv;
2880
2881         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2882                 return 1;
2883
2884         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2885         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2886
2887         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2888                 if (curadv != reqadv)
2889                         return 0;
2890
2891                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2892                         tg3_readphy(tp, MII_LPA, rmtadv);
2893         } else {
2894                 /* Reprogram the advertisement register, even if it
2895                  * does not affect the current link.  If the link
2896                  * gets renegotiated in the future, we can save an
2897                  * additional renegotiation cycle by advertising
2898                  * it correctly in the first place.
2899                  */
2900                 if (curadv != reqadv) {
2901                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2902                                      ADVERTISE_PAUSE_ASYM);
2903                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2904                 }
2905         }
2906
2907         return 1;
2908 }
2909
2910 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2911 {
2912         int current_link_up;
2913         u32 bmsr, dummy;
2914         u32 lcl_adv, rmt_adv;
2915         u16 current_speed;
2916         u8 current_duplex;
2917         int i, err;
2918
2919         tw32(MAC_EVENT, 0);
2920
2921         tw32_f(MAC_STATUS,
2922              (MAC_STATUS_SYNC_CHANGED |
2923               MAC_STATUS_CFG_CHANGED |
2924               MAC_STATUS_MI_COMPLETION |
2925               MAC_STATUS_LNKSTATE_CHANGED));
2926         udelay(40);
2927
2928         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2929                 tw32_f(MAC_MI_MODE,
2930                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2931                 udelay(80);
2932         }
2933
2934         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2935
2936         /* Some third-party PHYs need to be reset on link going
2937          * down.
2938          */
2939         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2940              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2941              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2942             netif_carrier_ok(tp->dev)) {
2943                 tg3_readphy(tp, MII_BMSR, &bmsr);
2944                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2945                     !(bmsr & BMSR_LSTATUS))
2946                         force_reset = 1;
2947         }
2948         if (force_reset)
2949                 tg3_phy_reset(tp);
2950
2951         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2952                 tg3_readphy(tp, MII_BMSR, &bmsr);
2953                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2954                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2955                         bmsr = 0;
2956
2957                 if (!(bmsr & BMSR_LSTATUS)) {
2958                         err = tg3_init_5401phy_dsp(tp);
2959                         if (err)
2960                                 return err;
2961
2962                         tg3_readphy(tp, MII_BMSR, &bmsr);
2963                         for (i = 0; i < 1000; i++) {
2964                                 udelay(10);
2965                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2966                                     (bmsr & BMSR_LSTATUS)) {
2967                                         udelay(40);
2968                                         break;
2969                                 }
2970                         }
2971
2972                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2973                             !(bmsr & BMSR_LSTATUS) &&
2974                             tp->link_config.active_speed == SPEED_1000) {
2975                                 err = tg3_phy_reset(tp);
2976                                 if (!err)
2977                                         err = tg3_init_5401phy_dsp(tp);
2978                                 if (err)
2979                                         return err;
2980                         }
2981                 }
2982         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2983                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2984                 /* 5701 {A0,B0} CRC bug workaround */
2985                 tg3_writephy(tp, 0x15, 0x0a75);
2986                 tg3_writephy(tp, 0x1c, 0x8c68);
2987                 tg3_writephy(tp, 0x1c, 0x8d68);
2988                 tg3_writephy(tp, 0x1c, 0x8c68);
2989         }
2990
2991         /* Clear pending interrupts... */
2992         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2993         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2994
2995         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2996                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2997         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2998                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2999
3000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3002                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3003                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3004                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3005                 else
3006                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3007         }
3008
3009         current_link_up = 0;
3010         current_speed = SPEED_INVALID;
3011         current_duplex = DUPLEX_INVALID;
3012
3013         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3014                 u32 val;
3015
3016                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3017                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3018                 if (!(val & (1 << 10))) {
3019                         val |= (1 << 10);
3020                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3021                         goto relink;
3022                 }
3023         }
3024
3025         bmsr = 0;
3026         for (i = 0; i < 100; i++) {
3027                 tg3_readphy(tp, MII_BMSR, &bmsr);
3028                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3029                     (bmsr & BMSR_LSTATUS))
3030                         break;
3031                 udelay(40);
3032         }
3033
3034         if (bmsr & BMSR_LSTATUS) {
3035                 u32 aux_stat, bmcr;
3036
3037                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3038                 for (i = 0; i < 2000; i++) {
3039                         udelay(10);
3040                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3041                             aux_stat)
3042                                 break;
3043                 }
3044
3045                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3046                                              &current_speed,
3047                                              &current_duplex);
3048
3049                 bmcr = 0;
3050                 for (i = 0; i < 200; i++) {
3051                         tg3_readphy(tp, MII_BMCR, &bmcr);
3052                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3053                                 continue;
3054                         if (bmcr && bmcr != 0x7fff)
3055                                 break;
3056                         udelay(10);
3057                 }
3058
3059                 lcl_adv = 0;
3060                 rmt_adv = 0;
3061
3062                 tp->link_config.active_speed = current_speed;
3063                 tp->link_config.active_duplex = current_duplex;
3064
3065                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3066                         if ((bmcr & BMCR_ANENABLE) &&
3067                             tg3_copper_is_advertising_all(tp,
3068                                                 tp->link_config.advertising)) {
3069                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3070                                                                   &rmt_adv))
3071                                         current_link_up = 1;
3072                         }
3073                 } else {
3074                         if (!(bmcr & BMCR_ANENABLE) &&
3075                             tp->link_config.speed == current_speed &&
3076                             tp->link_config.duplex == current_duplex &&
3077                             tp->link_config.flowctrl ==
3078                             tp->link_config.active_flowctrl) {
3079                                 current_link_up = 1;
3080                         }
3081                 }
3082
3083                 if (current_link_up == 1 &&
3084                     tp->link_config.active_duplex == DUPLEX_FULL)
3085                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3086         }
3087
3088 relink:
3089         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3090                 u32 tmp;
3091
3092                 tg3_phy_copper_begin(tp);
3093
3094                 tg3_readphy(tp, MII_BMSR, &tmp);
3095                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3096                     (tmp & BMSR_LSTATUS))
3097                         current_link_up = 1;
3098         }
3099
3100         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3101         if (current_link_up == 1) {
3102                 if (tp->link_config.active_speed == SPEED_100 ||
3103                     tp->link_config.active_speed == SPEED_10)
3104                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3105                 else
3106                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3107         } else
3108                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3109
3110         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3111         if (tp->link_config.active_duplex == DUPLEX_HALF)
3112                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3113
3114         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3115                 if (current_link_up == 1 &&
3116                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3117                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3118                 else
3119                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3120         }
3121
3122         /* ??? Without this setting Netgear GA302T PHY does not
3123          * ??? send/receive packets...
3124          */
3125         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3126             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3127                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3128                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3129                 udelay(80);
3130         }
3131
3132         tw32_f(MAC_MODE, tp->mac_mode);
3133         udelay(40);
3134
3135         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3136                 /* Polled via timer. */
3137                 tw32_f(MAC_EVENT, 0);
3138         } else {
3139                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3140         }
3141         udelay(40);
3142
3143         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3144             current_link_up == 1 &&
3145             tp->link_config.active_speed == SPEED_1000 &&
3146             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3147              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3148                 udelay(120);
3149                 tw32_f(MAC_STATUS,
3150                      (MAC_STATUS_SYNC_CHANGED |
3151                       MAC_STATUS_CFG_CHANGED));
3152                 udelay(40);
3153                 tg3_write_mem(tp,
3154                               NIC_SRAM_FIRMWARE_MBOX,
3155                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3156         }
3157
3158         /* Prevent send BD corruption. */
3159         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3160                 u16 oldlnkctl, newlnkctl;
3161
3162                 pci_read_config_word(tp->pdev,
3163                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3164                                      &oldlnkctl);
3165                 if (tp->link_config.active_speed == SPEED_100 ||
3166                     tp->link_config.active_speed == SPEED_10)
3167                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3168                 else
3169                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3170                 if (newlnkctl != oldlnkctl)
3171                         pci_write_config_word(tp->pdev,
3172                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3173                                               newlnkctl);
3174         }
3175
3176         if (current_link_up != netif_carrier_ok(tp->dev)) {
3177                 if (current_link_up)
3178                         netif_carrier_on(tp->dev);
3179                 else
3180                         netif_carrier_off(tp->dev);
3181                 tg3_link_report(tp);
3182         }
3183
3184         return 0;
3185 }
3186
3187 struct tg3_fiber_aneginfo {
3188         int state;
3189 #define ANEG_STATE_UNKNOWN              0
3190 #define ANEG_STATE_AN_ENABLE            1
3191 #define ANEG_STATE_RESTART_INIT         2
3192 #define ANEG_STATE_RESTART              3
3193 #define ANEG_STATE_DISABLE_LINK_OK      4
3194 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3195 #define ANEG_STATE_ABILITY_DETECT       6
3196 #define ANEG_STATE_ACK_DETECT_INIT      7
3197 #define ANEG_STATE_ACK_DETECT           8
3198 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3199 #define ANEG_STATE_COMPLETE_ACK         10
3200 #define ANEG_STATE_IDLE_DETECT_INIT     11
3201 #define ANEG_STATE_IDLE_DETECT          12
3202 #define ANEG_STATE_LINK_OK              13
3203 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3204 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3205
3206         u32 flags;
3207 #define MR_AN_ENABLE            0x00000001
3208 #define MR_RESTART_AN           0x00000002
3209 #define MR_AN_COMPLETE          0x00000004
3210 #define MR_PAGE_RX              0x00000008
3211 #define MR_NP_LOADED            0x00000010
3212 #define MR_TOGGLE_TX            0x00000020
3213 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3214 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3215 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3216 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3217 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3218 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3219 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3220 #define MR_TOGGLE_RX            0x00002000
3221 #define MR_NP_RX                0x00004000
3222
3223 #define MR_LINK_OK              0x80000000
3224
3225         unsigned long link_time, cur_time;
3226
3227         u32 ability_match_cfg;
3228         int ability_match_count;
3229
3230         char ability_match, idle_match, ack_match;
3231
3232         u32 txconfig, rxconfig;
3233 #define ANEG_CFG_NP             0x00000080
3234 #define ANEG_CFG_ACK            0x00000040
3235 #define ANEG_CFG_RF2            0x00000020
3236 #define ANEG_CFG_RF1            0x00000010
3237 #define ANEG_CFG_PS2            0x00000001
3238 #define ANEG_CFG_PS1            0x00008000
3239 #define ANEG_CFG_HD             0x00004000
3240 #define ANEG_CFG_FD             0x00002000
3241 #define ANEG_CFG_INVAL          0x00001f06
3242
3243 };
3244 #define ANEG_OK         0
3245 #define ANEG_DONE       1
3246 #define ANEG_TIMER_ENAB 2
3247 #define ANEG_FAILED     -1
3248
3249 #define ANEG_STATE_SETTLE_TIME  10000
3250
3251 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3252                                    struct tg3_fiber_aneginfo *ap)
3253 {
3254         u16 flowctrl;
3255         unsigned long delta;
3256         u32 rx_cfg_reg;
3257         int ret;
3258
3259         if (ap->state == ANEG_STATE_UNKNOWN) {
3260                 ap->rxconfig = 0;
3261                 ap->link_time = 0;
3262                 ap->cur_time = 0;
3263                 ap->ability_match_cfg = 0;
3264                 ap->ability_match_count = 0;
3265                 ap->ability_match = 0;
3266                 ap->idle_match = 0;
3267                 ap->ack_match = 0;
3268         }
3269         ap->cur_time++;
3270
3271         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3272                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3273
3274                 if (rx_cfg_reg != ap->ability_match_cfg) {
3275                         ap->ability_match_cfg = rx_cfg_reg;
3276                         ap->ability_match = 0;
3277                         ap->ability_match_count = 0;
3278                 } else {
3279                         if (++ap->ability_match_count > 1) {
3280                                 ap->ability_match = 1;
3281                                 ap->ability_match_cfg = rx_cfg_reg;
3282                         }
3283                 }
3284                 if (rx_cfg_reg & ANEG_CFG_ACK)
3285                         ap->ack_match = 1;
3286                 else
3287                         ap->ack_match = 0;
3288
3289                 ap->idle_match = 0;
3290         } else {
3291                 ap->idle_match = 1;
3292                 ap->ability_match_cfg = 0;
3293                 ap->ability_match_count = 0;
3294                 ap->ability_match = 0;
3295                 ap->ack_match = 0;
3296
3297                 rx_cfg_reg = 0;
3298         }
3299
3300         ap->rxconfig = rx_cfg_reg;
3301         ret = ANEG_OK;
3302
3303         switch(ap->state) {
3304         case ANEG_STATE_UNKNOWN:
3305                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3306                         ap->state = ANEG_STATE_AN_ENABLE;
3307
3308                 /* fallthru */
3309         case ANEG_STATE_AN_ENABLE:
3310                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3311                 if (ap->flags & MR_AN_ENABLE) {
3312                         ap->link_time = 0;
3313                         ap->cur_time = 0;
3314                         ap->ability_match_cfg = 0;
3315                         ap->ability_match_count = 0;
3316                         ap->ability_match = 0;
3317                         ap->idle_match = 0;
3318                         ap->ack_match = 0;
3319
3320                         ap->state = ANEG_STATE_RESTART_INIT;
3321                 } else {
3322                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3323                 }
3324                 break;
3325
3326         case ANEG_STATE_RESTART_INIT:
3327                 ap->link_time = ap->cur_time;
3328                 ap->flags &= ~(MR_NP_LOADED);
3329                 ap->txconfig = 0;
3330                 tw32(MAC_TX_AUTO_NEG, 0);
3331                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3332                 tw32_f(MAC_MODE, tp->mac_mode);
3333                 udelay(40);
3334
3335                 ret = ANEG_TIMER_ENAB;
3336                 ap->state = ANEG_STATE_RESTART;
3337
3338                 /* fallthru */
3339         case ANEG_STATE_RESTART:
3340                 delta = ap->cur_time - ap->link_time;
3341                 if (delta > ANEG_STATE_SETTLE_TIME) {
3342                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3343                 } else {
3344                         ret = ANEG_TIMER_ENAB;
3345                 }
3346                 break;
3347
3348         case ANEG_STATE_DISABLE_LINK_OK:
3349                 ret = ANEG_DONE;
3350                 break;
3351
3352         case ANEG_STATE_ABILITY_DETECT_INIT:
3353                 ap->flags &= ~(MR_TOGGLE_TX);
3354                 ap->txconfig = ANEG_CFG_FD;
3355                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3356                 if (flowctrl & ADVERTISE_1000XPAUSE)
3357                         ap->txconfig |= ANEG_CFG_PS1;
3358                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3359                         ap->txconfig |= ANEG_CFG_PS2;
3360                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3361                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3362                 tw32_f(MAC_MODE, tp->mac_mode);
3363                 udelay(40);
3364
3365                 ap->state = ANEG_STATE_ABILITY_DETECT;
3366                 break;
3367
3368         case ANEG_STATE_ABILITY_DETECT:
3369                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3370                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3371                 }
3372                 break;
3373
3374         case ANEG_STATE_ACK_DETECT_INIT:
3375                 ap->txconfig |= ANEG_CFG_ACK;
3376                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3377                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3378                 tw32_f(MAC_MODE, tp->mac_mode);
3379                 udelay(40);
3380
3381                 ap->state = ANEG_STATE_ACK_DETECT;
3382
3383                 /* fallthru */
3384         case ANEG_STATE_ACK_DETECT:
3385                 if (ap->ack_match != 0) {
3386                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3387                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3388                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3389                         } else {
3390                                 ap->state = ANEG_STATE_AN_ENABLE;
3391                         }
3392                 } else if (ap->ability_match != 0 &&
3393                            ap->rxconfig == 0) {
3394                         ap->state = ANEG_STATE_AN_ENABLE;
3395                 }
3396                 break;
3397
3398         case ANEG_STATE_COMPLETE_ACK_INIT:
3399                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3400                         ret = ANEG_FAILED;
3401                         break;
3402                 }
3403                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3404                                MR_LP_ADV_HALF_DUPLEX |
3405                                MR_LP_ADV_SYM_PAUSE |
3406                                MR_LP_ADV_ASYM_PAUSE |
3407                                MR_LP_ADV_REMOTE_FAULT1 |
3408                                MR_LP_ADV_REMOTE_FAULT2 |
3409                                MR_LP_ADV_NEXT_PAGE |
3410                                MR_TOGGLE_RX |
3411                                MR_NP_RX);
3412                 if (ap->rxconfig & ANEG_CFG_FD)
3413                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3414                 if (ap->rxconfig & ANEG_CFG_HD)
3415                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3416                 if (ap->rxconfig & ANEG_CFG_PS1)
3417                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3418                 if (ap->rxconfig & ANEG_CFG_PS2)
3419                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3420                 if (ap->rxconfig & ANEG_CFG_RF1)
3421                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3422                 if (ap->rxconfig & ANEG_CFG_RF2)
3423                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3424                 if (ap->rxconfig & ANEG_CFG_NP)
3425                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3426
3427                 ap->link_time = ap->cur_time;
3428
3429                 ap->flags ^= (MR_TOGGLE_TX);
3430                 if (ap->rxconfig & 0x0008)
3431                         ap->flags |= MR_TOGGLE_RX;
3432                 if (ap->rxconfig & ANEG_CFG_NP)
3433                         ap->flags |= MR_NP_RX;
3434                 ap->flags |= MR_PAGE_RX;
3435
3436                 ap->state = ANEG_STATE_COMPLETE_ACK;
3437                 ret = ANEG_TIMER_ENAB;
3438                 break;
3439
3440         case ANEG_STATE_COMPLETE_ACK:
3441                 if (ap->ability_match != 0 &&
3442                     ap->rxconfig == 0) {
3443                         ap->state = ANEG_STATE_AN_ENABLE;
3444                         break;
3445                 }
3446                 delta = ap->cur_time - ap->link_time;
3447                 if (delta > ANEG_STATE_SETTLE_TIME) {
3448                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3449                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3450                         } else {
3451                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3452                                     !(ap->flags & MR_NP_RX)) {
3453                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3454                                 } else {
3455                                         ret = ANEG_FAILED;
3456                                 }
3457                         }
3458                 }
3459                 break;
3460
3461         case ANEG_STATE_IDLE_DETECT_INIT:
3462                 ap->link_time = ap->cur_time;
3463                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3464                 tw32_f(MAC_MODE, tp->mac_mode);
3465                 udelay(40);
3466
3467                 ap->state = ANEG_STATE_IDLE_DETECT;
3468                 ret = ANEG_TIMER_ENAB;
3469                 break;
3470
3471         case ANEG_STATE_IDLE_DETECT:
3472                 if (ap->ability_match != 0 &&
3473                     ap->rxconfig == 0) {
3474                         ap->state = ANEG_STATE_AN_ENABLE;
3475                         break;
3476                 }
3477                 delta = ap->cur_time - ap->link_time;
3478                 if (delta > ANEG_STATE_SETTLE_TIME) {
3479                         /* XXX another gem from the Broadcom driver :( */
3480                         ap->state = ANEG_STATE_LINK_OK;
3481                 }
3482                 break;
3483
3484         case ANEG_STATE_LINK_OK:
3485                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3486                 ret = ANEG_DONE;
3487                 break;
3488
3489         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3490                 /* ??? unimplemented */
3491                 break;
3492
3493         case ANEG_STATE_NEXT_PAGE_WAIT:
3494                 /* ??? unimplemented */
3495                 break;
3496
3497         default:
3498                 ret = ANEG_FAILED;
3499                 break;
3500         }
3501
3502         return ret;
3503 }
3504
3505 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3506 {
3507         int res = 0;
3508         struct tg3_fiber_aneginfo aninfo;
3509         int status = ANEG_FAILED;
3510         unsigned int tick;
3511         u32 tmp;
3512
3513         tw32_f(MAC_TX_AUTO_NEG, 0);
3514
3515         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3516         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3517         udelay(40);
3518
3519         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3520         udelay(40);
3521
3522         memset(&aninfo, 0, sizeof(aninfo));
3523         aninfo.flags |= MR_AN_ENABLE;
3524         aninfo.state = ANEG_STATE_UNKNOWN;
3525         aninfo.cur_time = 0;
3526         tick = 0;
3527         while (++tick < 195000) {
3528                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3529                 if (status == ANEG_DONE || status == ANEG_FAILED)
3530                         break;
3531
3532                 udelay(1);
3533         }
3534
3535         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3536         tw32_f(MAC_MODE, tp->mac_mode);
3537         udelay(40);
3538
3539         *txflags = aninfo.txconfig;
3540         *rxflags = aninfo.flags;
3541
3542         if (status == ANEG_DONE &&
3543             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3544                              MR_LP_ADV_FULL_DUPLEX)))
3545                 res = 1;
3546
3547         return res;
3548 }
3549
3550 static void tg3_init_bcm8002(struct tg3 *tp)
3551 {
3552         u32 mac_status = tr32(MAC_STATUS);
3553         int i;
3554
3555         /* Reset when initting first time or we have a link. */
3556         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3557             !(mac_status & MAC_STATUS_PCS_SYNCED))
3558                 return;
3559
3560         /* Set PLL lock range. */
3561         tg3_writephy(tp, 0x16, 0x8007);
3562
3563         /* SW reset */
3564         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3565
3566         /* Wait for reset to complete. */
3567         /* XXX schedule_timeout() ... */
3568         for (i = 0; i < 500; i++)
3569                 udelay(10);
3570
3571         /* Config mode; select PMA/Ch 1 regs. */
3572         tg3_writephy(tp, 0x10, 0x8411);
3573
3574         /* Enable auto-lock and comdet, select txclk for tx. */
3575         tg3_writephy(tp, 0x11, 0x0a10);
3576
3577         tg3_writephy(tp, 0x18, 0x00a0);
3578         tg3_writephy(tp, 0x16, 0x41ff);
3579
3580         /* Assert and deassert POR. */
3581         tg3_writephy(tp, 0x13, 0x0400);
3582         udelay(40);
3583         tg3_writephy(tp, 0x13, 0x0000);
3584
3585         tg3_writephy(tp, 0x11, 0x0a50);
3586         udelay(40);
3587         tg3_writephy(tp, 0x11, 0x0a10);
3588
3589         /* Wait for signal to stabilize */
3590         /* XXX schedule_timeout() ... */
3591         for (i = 0; i < 15000; i++)
3592                 udelay(10);
3593
3594         /* Deselect the channel register so we can read the PHYID
3595          * later.
3596          */
3597         tg3_writephy(tp, 0x10, 0x8011);
3598 }
3599
3600 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3601 {
3602         u16 flowctrl;
3603         u32 sg_dig_ctrl, sg_dig_status;
3604         u32 serdes_cfg, expected_sg_dig_ctrl;
3605         int workaround, port_a;
3606         int current_link_up;
3607
3608         serdes_cfg = 0;
3609         expected_sg_dig_ctrl = 0;
3610         workaround = 0;
3611         port_a = 1;
3612         current_link_up = 0;
3613
3614         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3615             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3616                 workaround = 1;
3617                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3618                         port_a = 0;
3619
3620                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3621                 /* preserve bits 20-23 for voltage regulator */
3622                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3623         }
3624
3625         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3626
3627         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3628                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3629                         if (workaround) {
3630                                 u32 val = serdes_cfg;
3631
3632                                 if (port_a)
3633                                         val |= 0xc010000;
3634                                 else
3635                                         val |= 0x4010000;
3636                                 tw32_f(MAC_SERDES_CFG, val);
3637                         }
3638
3639                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3640                 }
3641                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3642                         tg3_setup_flow_control(tp, 0, 0);
3643                         current_link_up = 1;
3644                 }
3645                 goto out;
3646         }
3647
3648         /* Want auto-negotiation.  */
3649         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3650
3651         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3652         if (flowctrl & ADVERTISE_1000XPAUSE)
3653                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3654         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3655                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3656
3657         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3658                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3659                     tp->serdes_counter &&
3660                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3661                                     MAC_STATUS_RCVD_CFG)) ==
3662                      MAC_STATUS_PCS_SYNCED)) {
3663                         tp->serdes_counter--;
3664                         current_link_up = 1;
3665                         goto out;
3666                 }
3667 restart_autoneg:
3668                 if (workaround)
3669                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3670                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3671                 udelay(5);
3672                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3673
3674                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3675                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3676         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3677                                  MAC_STATUS_SIGNAL_DET)) {
3678                 sg_dig_status = tr32(SG_DIG_STATUS);
3679                 mac_status = tr32(MAC_STATUS);
3680
3681                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3682                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3683                         u32 local_adv = 0, remote_adv = 0;
3684
3685                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3686                                 local_adv |= ADVERTISE_1000XPAUSE;
3687                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3688                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3689
3690                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3691                                 remote_adv |= LPA_1000XPAUSE;
3692                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3693                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3694
3695                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3696                         current_link_up = 1;
3697                         tp->serdes_counter = 0;
3698                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3699                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3700                         if (tp->serdes_counter)
3701                                 tp->serdes_counter--;
3702                         else {
3703                                 if (workaround) {
3704                                         u32 val = serdes_cfg;
3705
3706                                         if (port_a)
3707                                                 val |= 0xc010000;
3708                                         else
3709                                                 val |= 0x4010000;
3710
3711                                         tw32_f(MAC_SERDES_CFG, val);
3712                                 }
3713
3714                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3715                                 udelay(40);
3716
3717                                 /* Link parallel detection - link is up */
3718                                 /* only if we have PCS_SYNC and not */
3719                                 /* receiving config code words */
3720                                 mac_status = tr32(MAC_STATUS);
3721                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3722                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3723                                         tg3_setup_flow_control(tp, 0, 0);
3724                                         current_link_up = 1;
3725                                         tp->tg3_flags2 |=
3726                                                 TG3_FLG2_PARALLEL_DETECT;
3727                                         tp->serdes_counter =
3728                                                 SERDES_PARALLEL_DET_TIMEOUT;
3729                                 } else
3730                                         goto restart_autoneg;
3731                         }
3732                 }
3733         } else {
3734                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3735                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3736         }
3737
3738 out:
3739         return current_link_up;
3740 }
3741
3742 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3743 {
3744         int current_link_up = 0;
3745
3746         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3747                 goto out;
3748
3749         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3750                 u32 txflags, rxflags;
3751                 int i;
3752
3753                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3754                         u32 local_adv = 0, remote_adv = 0;
3755
3756                         if (txflags & ANEG_CFG_PS1)
3757                                 local_adv |= ADVERTISE_1000XPAUSE;
3758                         if (txflags & ANEG_CFG_PS2)
3759                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3760
3761                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3762                                 remote_adv |= LPA_1000XPAUSE;
3763                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3764                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3765
3766                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3767
3768                         current_link_up = 1;
3769                 }
3770                 for (i = 0; i < 30; i++) {
3771                         udelay(20);
3772                         tw32_f(MAC_STATUS,
3773                                (MAC_STATUS_SYNC_CHANGED |
3774                                 MAC_STATUS_CFG_CHANGED));
3775                         udelay(40);
3776                         if ((tr32(MAC_STATUS) &
3777                              (MAC_STATUS_SYNC_CHANGED |
3778                               MAC_STATUS_CFG_CHANGED)) == 0)
3779                                 break;
3780                 }
3781
3782                 mac_status = tr32(MAC_STATUS);
3783                 if (current_link_up == 0 &&
3784                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3785                     !(mac_status & MAC_STATUS_RCVD_CFG))
3786                         current_link_up = 1;
3787         } else {
3788                 tg3_setup_flow_control(tp, 0, 0);
3789
3790                 /* Forcing 1000FD link up. */
3791                 current_link_up = 1;
3792
3793                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3794                 udelay(40);
3795
3796                 tw32_f(MAC_MODE, tp->mac_mode);
3797                 udelay(40);
3798         }
3799
3800 out:
3801         return current_link_up;
3802 }
3803
3804 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3805 {
3806         u32 orig_pause_cfg;
3807         u16 orig_active_speed;
3808         u8 orig_active_duplex;
3809         u32 mac_status;
3810         int current_link_up;
3811         int i;
3812
3813         orig_pause_cfg = tp->link_config.active_flowctrl;
3814         orig_active_speed = tp->link_config.active_speed;
3815         orig_active_duplex = tp->link_config.active_duplex;
3816
3817         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3818             netif_carrier_ok(tp->dev) &&
3819             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3820                 mac_status = tr32(MAC_STATUS);
3821                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3822                                MAC_STATUS_SIGNAL_DET |
3823                                MAC_STATUS_CFG_CHANGED |
3824                                MAC_STATUS_RCVD_CFG);
3825                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3826                                    MAC_STATUS_SIGNAL_DET)) {
3827                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3828                                             MAC_STATUS_CFG_CHANGED));
3829                         return 0;
3830                 }
3831         }
3832
3833         tw32_f(MAC_TX_AUTO_NEG, 0);
3834
3835         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3836         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3837         tw32_f(MAC_MODE, tp->mac_mode);
3838         udelay(40);
3839
3840         if (tp->phy_id == PHY_ID_BCM8002)
3841                 tg3_init_bcm8002(tp);
3842
3843         /* Enable link change event even when serdes polling.  */
3844         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3845         udelay(40);
3846
3847         current_link_up = 0;
3848         mac_status = tr32(MAC_STATUS);
3849
3850         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3851                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3852         else
3853                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3854
3855         tp->hw_status->status =
3856                 (SD_STATUS_UPDATED |
3857                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3858
3859         for (i = 0; i < 100; i++) {
3860                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3861                                     MAC_STATUS_CFG_CHANGED));
3862                 udelay(5);
3863                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3864                                          MAC_STATUS_CFG_CHANGED |
3865                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3866                         break;
3867         }
3868
3869         mac_status = tr32(MAC_STATUS);
3870         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3871                 current_link_up = 0;
3872                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3873                     tp->serdes_counter == 0) {
3874                         tw32_f(MAC_MODE, (tp->mac_mode |
3875                                           MAC_MODE_SEND_CONFIGS));
3876                         udelay(1);
3877                         tw32_f(MAC_MODE, tp->mac_mode);
3878                 }
3879         }
3880
3881         if (current_link_up == 1) {
3882                 tp->link_config.active_speed = SPEED_1000;
3883                 tp->link_config.active_duplex = DUPLEX_FULL;
3884                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3885                                     LED_CTRL_LNKLED_OVERRIDE |
3886                                     LED_CTRL_1000MBPS_ON));
3887         } else {
3888                 tp->link_config.active_speed = SPEED_INVALID;
3889                 tp->link_config.active_duplex = DUPLEX_INVALID;
3890                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3891                                     LED_CTRL_LNKLED_OVERRIDE |
3892                                     LED_CTRL_TRAFFIC_OVERRIDE));
3893         }
3894
3895         if (current_link_up != netif_carrier_ok(tp->dev)) {
3896                 if (current_link_up)
3897                         netif_carrier_on(tp->dev);
3898                 else
3899                         netif_carrier_off(tp->dev);
3900                 tg3_link_report(tp);
3901         } else {
3902                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3903                 if (orig_pause_cfg != now_pause_cfg ||
3904                     orig_active_speed != tp->link_config.active_speed ||
3905                     orig_active_duplex != tp->link_config.active_duplex)
3906                         tg3_link_report(tp);
3907         }
3908
3909         return 0;
3910 }
3911
3912 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3913 {
3914         int current_link_up, err = 0;
3915         u32 bmsr, bmcr;
3916         u16 current_speed;
3917         u8 current_duplex;
3918         u32 local_adv, remote_adv;
3919
3920         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3921         tw32_f(MAC_MODE, tp->mac_mode);
3922         udelay(40);
3923
3924         tw32(MAC_EVENT, 0);
3925
3926         tw32_f(MAC_STATUS,
3927              (MAC_STATUS_SYNC_CHANGED |
3928               MAC_STATUS_CFG_CHANGED |
3929               MAC_STATUS_MI_COMPLETION |
3930               MAC_STATUS_LNKSTATE_CHANGED));
3931         udelay(40);
3932
3933         if (force_reset)
3934                 tg3_phy_reset(tp);
3935
3936         current_link_up = 0;
3937         current_speed = SPEED_INVALID;
3938         current_duplex = DUPLEX_INVALID;
3939
3940         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3941         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3942         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3943                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3944                         bmsr |= BMSR_LSTATUS;
3945                 else
3946                         bmsr &= ~BMSR_LSTATUS;
3947         }
3948
3949         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3950
3951         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3952             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3953                 /* do nothing, just check for link up at the end */
3954         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3955                 u32 adv, new_adv;
3956
3957                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3958                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3959                                   ADVERTISE_1000XPAUSE |
3960                                   ADVERTISE_1000XPSE_ASYM |
3961                                   ADVERTISE_SLCT);
3962
3963                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3964
3965                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3966                         new_adv |= ADVERTISE_1000XHALF;
3967                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3968                         new_adv |= ADVERTISE_1000XFULL;
3969
3970                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3971                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3972                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3973                         tg3_writephy(tp, MII_BMCR, bmcr);
3974
3975                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3976                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3977                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3978
3979                         return err;
3980                 }
3981         } else {
3982                 u32 new_bmcr;
3983
3984                 bmcr &= ~BMCR_SPEED1000;
3985                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3986
3987                 if (tp->link_config.duplex == DUPLEX_FULL)
3988                         new_bmcr |= BMCR_FULLDPLX;
3989
3990                 if (new_bmcr != bmcr) {
3991                         /* BMCR_SPEED1000 is a reserved bit that needs
3992                          * to be set on write.
3993                          */
3994                         new_bmcr |= BMCR_SPEED1000;
3995
3996                         /* Force a linkdown */
3997                         if (netif_carrier_ok(tp->dev)) {
3998                                 u32 adv;
3999
4000                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4001                                 adv &= ~(ADVERTISE_1000XFULL |
4002                                          ADVERTISE_1000XHALF |
4003                                          ADVERTISE_SLCT);
4004                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4005                                 tg3_writephy(tp, MII_BMCR, bmcr |
4006                                                            BMCR_ANRESTART |
4007                                                            BMCR_ANENABLE);
4008                                 udelay(10);
4009                                 netif_carrier_off(tp->dev);
4010                         }
4011                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4012                         bmcr = new_bmcr;
4013                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4014                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4015                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4016                             ASIC_REV_5714) {
4017                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4018                                         bmsr |= BMSR_LSTATUS;
4019                                 else
4020                                         bmsr &= ~BMSR_LSTATUS;
4021                         }
4022                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4023                 }
4024         }
4025
4026         if (bmsr & BMSR_LSTATUS) {
4027                 current_speed = SPEED_1000;
4028                 current_link_up = 1;
4029                 if (bmcr & BMCR_FULLDPLX)
4030                         current_duplex = DUPLEX_FULL;
4031                 else
4032                         current_duplex = DUPLEX_HALF;
4033
4034                 local_adv = 0;
4035                 remote_adv = 0;
4036
4037                 if (bmcr & BMCR_ANENABLE) {
4038                         u32 common;
4039
4040                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4041                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4042                         common = local_adv & remote_adv;
4043                         if (common & (ADVERTISE_1000XHALF |
4044                                       ADVERTISE_1000XFULL)) {
4045                                 if (common & ADVERTISE_1000XFULL)
4046                                         current_duplex = DUPLEX_FULL;
4047                                 else
4048                                         current_duplex = DUPLEX_HALF;
4049                         }
4050                         else
4051                                 current_link_up = 0;
4052                 }
4053         }
4054
4055         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4056                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4057
4058         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4059         if (tp->link_config.active_duplex == DUPLEX_HALF)
4060                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4061
4062         tw32_f(MAC_MODE, tp->mac_mode);
4063         udelay(40);
4064
4065         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4066
4067         tp->link_config.active_speed = current_speed;
4068         tp->link_config.active_duplex = current_duplex;
4069
4070         if (current_link_up != netif_carrier_ok(tp->dev)) {
4071                 if (current_link_up)
4072                         netif_carrier_on(tp->dev);
4073                 else {
4074                         netif_carrier_off(tp->dev);
4075                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4076                 }
4077                 tg3_link_report(tp);
4078         }
4079         return err;
4080 }
4081
4082 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4083 {
4084         if (tp->serdes_counter) {
4085                 /* Give autoneg time to complete. */
4086                 tp->serdes_counter--;
4087                 return;
4088         }
4089         if (!netif_carrier_ok(tp->dev) &&
4090             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4091                 u32 bmcr;
4092
4093                 tg3_readphy(tp, MII_BMCR, &bmcr);
4094                 if (bmcr & BMCR_ANENABLE) {
4095                         u32 phy1, phy2;
4096
4097                         /* Select shadow register 0x1f */
4098                         tg3_writephy(tp, 0x1c, 0x7c00);
4099                         tg3_readphy(tp, 0x1c, &phy1);
4100
4101                         /* Select expansion interrupt status register */
4102                         tg3_writephy(tp, 0x17, 0x0f01);
4103                         tg3_readphy(tp, 0x15, &phy2);
4104                         tg3_readphy(tp, 0x15, &phy2);
4105
4106                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4107                                 /* We have signal detect and not receiving
4108                                  * config code words, link is up by parallel
4109                                  * detection.
4110                                  */
4111
4112                                 bmcr &= ~BMCR_ANENABLE;
4113                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4114                                 tg3_writephy(tp, MII_BMCR, bmcr);
4115                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4116                         }
4117                 }
4118         }
4119         else if (netif_carrier_ok(tp->dev) &&
4120                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4121                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4122                 u32 phy2;
4123
4124                 /* Select expansion interrupt status register */
4125                 tg3_writephy(tp, 0x17, 0x0f01);
4126                 tg3_readphy(tp, 0x15, &phy2);
4127                 if (phy2 & 0x20) {
4128                         u32 bmcr;
4129
4130                         /* Config code words received, turn on autoneg. */
4131                         tg3_readphy(tp, MII_BMCR, &bmcr);
4132                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4133
4134                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4135
4136                 }
4137         }
4138 }
4139
4140 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4141 {
4142         int err;
4143
4144         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4145                 err = tg3_setup_fiber_phy(tp, force_reset);
4146         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4147                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4148         } else {
4149                 err = tg3_setup_copper_phy(tp, force_reset);
4150         }
4151
4152         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4153                 u32 val, scale;
4154
4155                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4156                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4157                         scale = 65;
4158                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4159                         scale = 6;
4160                 else
4161                         scale = 12;
4162
4163                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4164                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4165                 tw32(GRC_MISC_CFG, val);
4166         }
4167
4168         if (tp->link_config.active_speed == SPEED_1000 &&
4169             tp->link_config.active_duplex == DUPLEX_HALF)
4170                 tw32(MAC_TX_LENGTHS,
4171                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4172                       (6 << TX_LENGTHS_IPG_SHIFT) |
4173                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4174         else
4175                 tw32(MAC_TX_LENGTHS,
4176                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4177                       (6 << TX_LENGTHS_IPG_SHIFT) |
4178                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4179
4180         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4181                 if (netif_carrier_ok(tp->dev)) {
4182                         tw32(HOSTCC_STAT_COAL_TICKS,
4183                              tp->coal.stats_block_coalesce_usecs);
4184                 } else {
4185                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4186                 }
4187         }
4188
4189         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4190                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4191                 if (!netif_carrier_ok(tp->dev))
4192                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4193                               tp->pwrmgmt_thresh;
4194                 else
4195                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4196                 tw32(PCIE_PWR_MGMT_THRESH, val);
4197         }
4198
4199         return err;
4200 }
4201
4202 /* This is called whenever we suspect that the system chipset is re-
4203  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4204  * is bogus tx completions. We try to recover by setting the
4205  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4206  * in the workqueue.
4207  */
4208 static void tg3_tx_recover(struct tg3 *tp)
4209 {
4210         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4211                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4212
4213         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4214                "mapped I/O cycles to the network device, attempting to "
4215                "recover. Please report the problem to the driver maintainer "
4216                "and include system chipset information.\n", tp->dev->name);
4217
4218         spin_lock(&tp->lock);
4219         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4220         spin_unlock(&tp->lock);
4221 }
4222
4223 static inline u32 tg3_tx_avail(struct tg3 *tp)
4224 {
4225         smp_mb();
4226         return (tp->tx_pending -
4227                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4228 }
4229
4230 /* Tigon3 never reports partial packet sends.  So we do not
4231  * need special logic to handle SKBs that have not had all
4232  * of their frags sent yet, like SunGEM does.
4233  */
4234 static void tg3_tx(struct tg3 *tp)
4235 {
4236         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4237         u32 sw_idx = tp->tx_cons;
4238
4239         while (sw_idx != hw_idx) {
4240                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4241                 struct sk_buff *skb = ri->skb;
4242                 int i, tx_bug = 0;
4243
4244                 if (unlikely(skb == NULL)) {
4245                         tg3_tx_recover(tp);
4246                         return;
4247                 }
4248
4249                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4250
4251                 ri->skb = NULL;
4252
4253                 sw_idx = NEXT_TX(sw_idx);
4254
4255                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4256                         ri = &tp->tx_buffers[sw_idx];
4257                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4258                                 tx_bug = 1;
4259                         sw_idx = NEXT_TX(sw_idx);
4260                 }
4261
4262                 dev_kfree_skb(skb);
4263
4264                 if (unlikely(tx_bug)) {
4265                         tg3_tx_recover(tp);
4266                         return;
4267                 }
4268         }
4269
4270         tp->tx_cons = sw_idx;
4271
4272         /* Need to make the tx_cons update visible to tg3_start_xmit()
4273          * before checking for netif_queue_stopped().  Without the
4274          * memory barrier, there is a small possibility that tg3_start_xmit()
4275          * will miss it and cause the queue to be stopped forever.
4276          */
4277         smp_mb();
4278
4279         if (unlikely(netif_queue_stopped(tp->dev) &&
4280                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4281                 netif_tx_lock(tp->dev);
4282                 if (netif_queue_stopped(tp->dev) &&
4283                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4284                         netif_wake_queue(tp->dev);
4285                 netif_tx_unlock(tp->dev);
4286         }
4287 }
4288
4289 /* Returns size of skb allocated or < 0 on error.
4290  *
4291  * We only need to fill in the address because the other members
4292  * of the RX descriptor are invariant, see tg3_init_rings.
4293  *
4294  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4295  * posting buffers we only dirty the first cache line of the RX
4296  * descriptor (containing the address).  Whereas for the RX status
4297  * buffers the cpu only reads the last cacheline of the RX descriptor
4298  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4299  */
4300 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4301                             int src_idx, u32 dest_idx_unmasked)
4302 {
4303         struct tg3_rx_buffer_desc *desc;
4304         struct ring_info *map, *src_map;
4305         struct sk_buff *skb;
4306         dma_addr_t mapping;
4307         int skb_size, dest_idx;
4308
4309         src_map = NULL;
4310         switch (opaque_key) {
4311         case RXD_OPAQUE_RING_STD:
4312                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4313                 desc = &tp->rx_std[dest_idx];
4314                 map = &tp->rx_std_buffers[dest_idx];
4315                 if (src_idx >= 0)
4316                         src_map = &tp->rx_std_buffers[src_idx];
4317                 skb_size = tp->rx_pkt_buf_sz;
4318                 break;
4319
4320         case RXD_OPAQUE_RING_JUMBO:
4321                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4322                 desc = &tp->rx_jumbo[dest_idx];
4323                 map = &tp->rx_jumbo_buffers[dest_idx];
4324                 if (src_idx >= 0)
4325                         src_map = &tp->rx_jumbo_buffers[src_idx];
4326                 skb_size = RX_JUMBO_PKT_BUF_SZ;
4327                 break;
4328
4329         default:
4330                 return -EINVAL;
4331         }
4332
4333         /* Do not overwrite any of the map or rp information
4334          * until we are sure we can commit to a new buffer.
4335          *
4336          * Callers depend upon this behavior and assume that
4337          * we leave everything unchanged if we fail.
4338          */
4339         skb = netdev_alloc_skb(tp->dev, skb_size);
4340         if (skb == NULL)
4341                 return -ENOMEM;
4342
4343         skb_reserve(skb, tp->rx_offset);
4344
4345         mapping = pci_map_single(tp->pdev, skb->data,
4346                                  skb_size - tp->rx_offset,
4347                                  PCI_DMA_FROMDEVICE);
4348
4349         map->skb = skb;
4350         pci_unmap_addr_set(map, mapping, mapping);
4351
4352         if (src_map != NULL)
4353                 src_map->skb = NULL;
4354
4355         desc->addr_hi = ((u64)mapping >> 32);
4356         desc->addr_lo = ((u64)mapping & 0xffffffff);
4357
4358         return skb_size;
4359 }
4360
4361 /* We only need to move over in the address because the other
4362  * members of the RX descriptor are invariant.  See notes above
4363  * tg3_alloc_rx_skb for full details.
4364  */
4365 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4366                            int src_idx, u32 dest_idx_unmasked)
4367 {
4368         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4369         struct ring_info *src_map, *dest_map;
4370         int dest_idx;
4371
4372         switch (opaque_key) {
4373         case RXD_OPAQUE_RING_STD:
4374                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4375                 dest_desc = &tp->rx_std[dest_idx];
4376                 dest_map = &tp->rx_std_buffers[dest_idx];
4377                 src_desc = &tp->rx_std[src_idx];
4378                 src_map = &tp->rx_std_buffers[src_idx];
4379                 break;
4380
4381         case RXD_OPAQUE_RING_JUMBO:
4382                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4383                 dest_desc = &tp->rx_jumbo[dest_idx];
4384                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4385                 src_desc = &tp->rx_jumbo[src_idx];
4386                 src_map = &tp->rx_jumbo_buffers[src_idx];
4387                 break;
4388
4389         default:
4390                 return;
4391         }
4392
4393         dest_map->skb = src_map->skb;
4394         pci_unmap_addr_set(dest_map, mapping,
4395                            pci_unmap_addr(src_map, mapping));
4396         dest_desc->addr_hi = src_desc->addr_hi;
4397         dest_desc->addr_lo = src_desc->addr_lo;
4398
4399         src_map->skb = NULL;
4400 }
4401
4402 #if TG3_VLAN_TAG_USED
4403 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4404 {
4405         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4406 }
4407 #endif
4408
4409 /* The RX ring scheme is composed of multiple rings which post fresh
4410  * buffers to the chip, and one special ring the chip uses to report
4411  * status back to the host.
4412  *
4413  * The special ring reports the status of received packets to the
4414  * host.  The chip does not write into the original descriptor the
4415  * RX buffer was obtained from.  The chip simply takes the original
4416  * descriptor as provided by the host, updates the status and length
4417  * field, then writes this into the next status ring entry.
4418  *
4419  * Each ring the host uses to post buffers to the chip is described
4420  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4421  * it is first placed into the on-chip ram.  When the packet's length
4422  * is known, it walks down the TG3_BDINFO entries to select the ring.
4423  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4424  * which is within the range of the new packet's length is chosen.
4425  *
4426  * The "separate ring for rx status" scheme may sound queer, but it makes
4427  * sense from a cache coherency perspective.  If only the host writes
4428  * to the buffer post rings, and only the chip writes to the rx status
4429  * rings, then cache lines never move beyond shared-modified state.
4430  * If both the host and chip were to write into the same ring, cache line
4431  * eviction could occur since both entities want it in an exclusive state.
4432  */
4433 static int tg3_rx(struct tg3 *tp, int budget)
4434 {
4435         u32 work_mask, rx_std_posted = 0;
4436         u32 sw_idx = tp->rx_rcb_ptr;
4437         u16 hw_idx;
4438         int received;
4439
4440         hw_idx = tp->hw_status->idx[0].rx_producer;
4441         /*
4442          * We need to order the read of hw_idx and the read of
4443          * the opaque cookie.
4444          */
4445         rmb();
4446         work_mask = 0;
4447         received = 0;
4448         while (sw_idx != hw_idx && budget > 0) {
4449                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4450                 unsigned int len;
4451                 struct sk_buff *skb;
4452                 dma_addr_t dma_addr;
4453                 u32 opaque_key, desc_idx, *post_ptr;
4454
4455                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4456                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4457                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4458                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4459                                                   mapping);
4460                         skb = tp->rx_std_buffers[desc_idx].skb;
4461                         post_ptr = &tp->rx_std_ptr;
4462                         rx_std_posted++;
4463                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4464                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4465                                                   mapping);
4466                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4467                         post_ptr = &tp->rx_jumbo_ptr;
4468                 }
4469                 else {
4470                         goto next_pkt_nopost;
4471                 }
4472
4473                 work_mask |= opaque_key;
4474
4475                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4476                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4477                 drop_it:
4478                         tg3_recycle_rx(tp, opaque_key,
4479                                        desc_idx, *post_ptr);
4480                 drop_it_no_recycle:
4481                         /* Other statistics kept track of by card. */
4482                         tp->net_stats.rx_dropped++;
4483                         goto next_pkt;
4484                 }
4485
4486                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4487                       ETH_FCS_LEN;
4488
4489                 if (len > RX_COPY_THRESHOLD
4490                         && tp->rx_offset == NET_IP_ALIGN
4491                         /* rx_offset will likely not equal NET_IP_ALIGN
4492                          * if this is a 5701 card running in PCI-X mode
4493                          * [see tg3_get_invariants()]
4494                          */
4495                 ) {
4496                         int skb_size;
4497
4498                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4499                                                     desc_idx, *post_ptr);
4500                         if (skb_size < 0)
4501                                 goto drop_it;
4502
4503                         pci_unmap_single(tp->pdev, dma_addr,
4504                                          skb_size - tp->rx_offset,
4505                                          PCI_DMA_FROMDEVICE);
4506
4507                         skb_put(skb, len);
4508                 } else {
4509                         struct sk_buff *copy_skb;
4510
4511                         tg3_recycle_rx(tp, opaque_key,
4512                                        desc_idx, *post_ptr);
4513
4514                         copy_skb = netdev_alloc_skb(tp->dev,
4515                                                     len + TG3_RAW_IP_ALIGN);
4516                         if (copy_skb == NULL)
4517                                 goto drop_it_no_recycle;
4518
4519                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4520                         skb_put(copy_skb, len);
4521                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4522                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4523                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4524
4525                         /* We'll reuse the original ring buffer. */
4526                         skb = copy_skb;
4527                 }
4528
4529                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4530                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4531                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4532                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4533                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4534                 else
4535                         skb->ip_summed = CHECKSUM_NONE;
4536
4537                 skb->protocol = eth_type_trans(skb, tp->dev);
4538
4539                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4540                     skb->protocol != htons(ETH_P_8021Q)) {
4541                         dev_kfree_skb(skb);
4542                         goto next_pkt;
4543                 }
4544
4545 #if TG3_VLAN_TAG_USED
4546                 if (tp->vlgrp != NULL &&
4547                     desc->type_flags & RXD_FLAG_VLAN) {
4548                         tg3_vlan_rx(tp, skb,
4549                                     desc->err_vlan & RXD_VLAN_MASK);
4550                 } else
4551 #endif
4552                         netif_receive_skb(skb);
4553
4554                 received++;
4555                 budget--;
4556
4557 next_pkt:
4558                 (*post_ptr)++;
4559
4560                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4561                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4562
4563                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4564                                      TG3_64BIT_REG_LOW, idx);
4565                         work_mask &= ~RXD_OPAQUE_RING_STD;
4566                         rx_std_posted = 0;
4567                 }
4568 next_pkt_nopost:
4569                 sw_idx++;
4570                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4571
4572                 /* Refresh hw_idx to see if there is new work */
4573                 if (sw_idx == hw_idx) {
4574                         hw_idx = tp->hw_status->idx[0].rx_producer;
4575                         rmb();
4576                 }
4577         }
4578
4579         /* ACK the status ring. */
4580         tp->rx_rcb_ptr = sw_idx;
4581         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4582
4583         /* Refill RX ring(s). */
4584         if (work_mask & RXD_OPAQUE_RING_STD) {
4585                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4586                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4587                              sw_idx);
4588         }
4589         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4590                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4591                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4592                              sw_idx);
4593         }
4594         mmiowb();
4595
4596         return received;
4597 }
4598
4599 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4600 {
4601         struct tg3_hw_status *sblk = tp->hw_status;
4602
4603         /* handle link change and other phy events */
4604         if (!(tp->tg3_flags &
4605               (TG3_FLAG_USE_LINKCHG_REG |
4606                TG3_FLAG_POLL_SERDES))) {
4607                 if (sblk->status & SD_STATUS_LINK_CHG) {
4608                         sblk->status = SD_STATUS_UPDATED |
4609                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4610                         spin_lock(&tp->lock);
4611                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4612                                 tw32_f(MAC_STATUS,
4613                                      (MAC_STATUS_SYNC_CHANGED |
4614                                       MAC_STATUS_CFG_CHANGED |
4615                                       MAC_STATUS_MI_COMPLETION |
4616                                       MAC_STATUS_LNKSTATE_CHANGED));
4617                                 udelay(40);
4618                         } else
4619                                 tg3_setup_phy(tp, 0);
4620                         spin_unlock(&tp->lock);
4621                 }
4622         }
4623
4624         /* run TX completion thread */
4625         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4626                 tg3_tx(tp);
4627                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4628                         return work_done;
4629         }
4630
4631         /* run RX thread, within the bounds set by NAPI.
4632          * All RX "locking" is done by ensuring outside
4633          * code synchronizes with tg3->napi.poll()
4634          */
4635         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4636                 work_done += tg3_rx(tp, budget - work_done);
4637
4638         return work_done;
4639 }
4640
4641 static int tg3_poll(struct napi_struct *napi, int budget)
4642 {
4643         struct tg3 *tp = container_of(napi, struct tg3, napi);
4644         int work_done = 0;
4645         struct tg3_hw_status *sblk = tp->hw_status;
4646
4647         while (1) {
4648                 work_done = tg3_poll_work(tp, work_done, budget);
4649
4650                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4651                         goto tx_recovery;
4652
4653                 if (unlikely(work_done >= budget))
4654                         break;
4655
4656                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4657                         /* tp->last_tag is used in tg3_restart_ints() below
4658                          * to tell the hw how much work has been processed,
4659                          * so we must read it before checking for more work.
4660                          */
4661                         tp->last_tag = sblk->status_tag;
4662                         rmb();
4663                 } else
4664                         sblk->status &= ~SD_STATUS_UPDATED;
4665
4666                 if (likely(!tg3_has_work(tp))) {
4667                         napi_complete(napi);
4668                         tg3_restart_ints(tp);
4669                         break;
4670                 }
4671         }
4672
4673         return work_done;
4674
4675 tx_recovery:
4676         /* work_done is guaranteed to be less than budget. */
4677         napi_complete(napi);
4678         schedule_work(&tp->reset_task);
4679         return work_done;
4680 }
4681
4682 static void tg3_irq_quiesce(struct tg3 *tp)
4683 {
4684         BUG_ON(tp->irq_sync);
4685
4686         tp->irq_sync = 1;
4687         smp_mb();
4688
4689         synchronize_irq(tp->pdev->irq);
4690 }
4691
4692 static inline int tg3_irq_sync(struct tg3 *tp)
4693 {
4694         return tp->irq_sync;
4695 }
4696
4697 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4698  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4699  * with as well.  Most of the time, this is not necessary except when
4700  * shutting down the device.
4701  */
4702 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4703 {
4704         spin_lock_bh(&tp->lock);
4705         if (irq_sync)
4706                 tg3_irq_quiesce(tp);
4707 }
4708
4709 static inline void tg3_full_unlock(struct tg3 *tp)
4710 {
4711         spin_unlock_bh(&tp->lock);
4712 }
4713
4714 /* One-shot MSI handler - Chip automatically disables interrupt
4715  * after sending MSI so driver doesn't have to do it.
4716  */
4717 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4718 {
4719         struct net_device *dev = dev_id;
4720         struct tg3 *tp = netdev_priv(dev);
4721
4722         prefetch(tp->hw_status);
4723         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4724
4725         if (likely(!tg3_irq_sync(tp)))
4726                 napi_schedule(&tp->napi);
4727
4728         return IRQ_HANDLED;
4729 }
4730
4731 /* MSI ISR - No need to check for interrupt sharing and no need to
4732  * flush status block and interrupt mailbox. PCI ordering rules
4733  * guarantee that MSI will arrive after the status block.
4734  */
4735 static irqreturn_t tg3_msi(int irq, void *dev_id)
4736 {
4737         struct net_device *dev = dev_id;
4738         struct tg3 *tp = netdev_priv(dev);
4739
4740         prefetch(tp->hw_status);
4741         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4742         /*
4743          * Writing any value to intr-mbox-0 clears PCI INTA# and
4744          * chip-internal interrupt pending events.
4745          * Writing non-zero to intr-mbox-0 additional tells the
4746          * NIC to stop sending us irqs, engaging "in-intr-handler"
4747          * event coalescing.
4748          */
4749         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4750         if (likely(!tg3_irq_sync(tp)))
4751                 napi_schedule(&tp->napi);
4752
4753         return IRQ_RETVAL(1);
4754 }
4755
4756 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4757 {
4758         struct net_device *dev = dev_id;
4759         struct tg3 *tp = netdev_priv(dev);
4760         struct tg3_hw_status *sblk = tp->hw_status;
4761         unsigned int handled = 1;
4762
4763         /* In INTx mode, it is possible for the interrupt to arrive at
4764          * the CPU before the status block posted prior to the interrupt.
4765          * Reading the PCI State register will confirm whether the
4766          * interrupt is ours and will flush the status block.
4767          */
4768         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4769                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4770                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4771                         handled = 0;
4772                         goto out;
4773                 }
4774         }
4775
4776         /*
4777          * Writing any value to intr-mbox-0 clears PCI INTA# and
4778          * chip-internal interrupt pending events.
4779          * Writing non-zero to intr-mbox-0 additional tells the
4780          * NIC to stop sending us irqs, engaging "in-intr-handler"
4781          * event coalescing.
4782          *
4783          * Flush the mailbox to de-assert the IRQ immediately to prevent
4784          * spurious interrupts.  The flush impacts performance but
4785          * excessive spurious interrupts can be worse in some cases.
4786          */
4787         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4788         if (tg3_irq_sync(tp))
4789                 goto out;
4790         sblk->status &= ~SD_STATUS_UPDATED;
4791         if (likely(tg3_has_work(tp))) {
4792                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4793                 napi_schedule(&tp->napi);
4794         } else {
4795                 /* No work, shared interrupt perhaps?  re-enable
4796                  * interrupts, and flush that PCI write
4797                  */
4798                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4799                                0x00000000);
4800         }
4801 out:
4802         return IRQ_RETVAL(handled);
4803 }
4804
4805 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4806 {
4807         struct net_device *dev = dev_id;
4808         struct tg3 *tp = netdev_priv(dev);
4809         struct tg3_hw_status *sblk = tp->hw_status;
4810         unsigned int handled = 1;
4811
4812         /* In INTx mode, it is possible for the interrupt to arrive at
4813          * the CPU before the status block posted prior to the interrupt.
4814          * Reading the PCI State register will confirm whether the
4815          * interrupt is ours and will flush the status block.
4816          */
4817         if (unlikely(sblk->status_tag == tp->last_tag)) {
4818                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4819                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4820                         handled = 0;
4821                         goto out;
4822                 }
4823         }
4824
4825         /*
4826          * writing any value to intr-mbox-0 clears PCI INTA# and
4827          * chip-internal interrupt pending events.
4828          * writing non-zero to intr-mbox-0 additional tells the
4829          * NIC to stop sending us irqs, engaging "in-intr-handler"
4830          * event coalescing.
4831          *
4832          * Flush the mailbox to de-assert the IRQ immediately to prevent
4833          * spurious interrupts.  The flush impacts performance but
4834          * excessive spurious interrupts can be worse in some cases.
4835          */
4836         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4837         if (tg3_irq_sync(tp))
4838                 goto out;
4839         if (napi_schedule_prep(&tp->napi)) {
4840                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4841                 /* Update last_tag to mark that this status has been
4842                  * seen. Because interrupt may be shared, we may be
4843                  * racing with tg3_poll(), so only update last_tag
4844                  * if tg3_poll() is not scheduled.
4845                  */
4846                 tp->last_tag = sblk->status_tag;
4847                 __napi_schedule(&tp->napi);
4848         }
4849 out:
4850         return IRQ_RETVAL(handled);
4851 }
4852
4853 /* ISR for interrupt test */
4854 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4855 {
4856         struct net_device *dev = dev_id;
4857         struct tg3 *tp = netdev_priv(dev);
4858         struct tg3_hw_status *sblk = tp->hw_status;
4859
4860         if ((sblk->status & SD_STATUS_UPDATED) ||
4861             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4862                 tg3_disable_ints(tp);
4863                 return IRQ_RETVAL(1);
4864         }
4865         return IRQ_RETVAL(0);
4866 }
4867
4868 static int tg3_init_hw(struct tg3 *, int);
4869 static int tg3_halt(struct tg3 *, int, int);
4870
4871 /* Restart hardware after configuration changes, self-test, etc.
4872  * Invoked with tp->lock held.
4873  */
4874 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4875         __releases(tp->lock)
4876         __acquires(tp->lock)
4877 {
4878         int err;
4879
4880         err = tg3_init_hw(tp, reset_phy);
4881         if (err) {
4882                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4883                        "aborting.\n", tp->dev->name);
4884                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4885                 tg3_full_unlock(tp);
4886                 del_timer_sync(&tp->timer);
4887                 tp->irq_sync = 0;
4888                 napi_enable(&tp->napi);
4889                 dev_close(tp->dev);
4890                 tg3_full_lock(tp, 0);
4891         }
4892         return err;
4893 }
4894
4895 #ifdef CONFIG_NET_POLL_CONTROLLER
4896 static void tg3_poll_controller(struct net_device *dev)
4897 {
4898         struct tg3 *tp = netdev_priv(dev);
4899
4900         tg3_interrupt(tp->pdev->irq, dev);
4901 }
4902 #endif
4903
4904 static void tg3_reset_task(struct work_struct *work)
4905 {
4906         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4907         int err;
4908         unsigned int restart_timer;
4909
4910         tg3_full_lock(tp, 0);
4911
4912         if (!netif_running(tp->dev)) {
4913                 tg3_full_unlock(tp);
4914                 return;
4915         }
4916
4917         tg3_full_unlock(tp);
4918
4919         tg3_phy_stop(tp);
4920
4921         tg3_netif_stop(tp);
4922
4923         tg3_full_lock(tp, 1);
4924
4925         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4926         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4927
4928         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4929                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4930                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4931                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4932                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4933         }
4934
4935         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4936         err = tg3_init_hw(tp, 1);
4937         if (err)
4938                 goto out;
4939
4940         tg3_netif_start(tp);
4941
4942         if (restart_timer)
4943                 mod_timer(&tp->timer, jiffies + 1);
4944
4945 out:
4946         tg3_full_unlock(tp);
4947
4948         if (!err)
4949                 tg3_phy_start(tp);
4950 }
4951
4952 static void tg3_dump_short_state(struct tg3 *tp)
4953 {
4954         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4955                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4956         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4957                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4958 }
4959
4960 static void tg3_tx_timeout(struct net_device *dev)
4961 {
4962         struct tg3 *tp = netdev_priv(dev);
4963
4964         if (netif_msg_tx_err(tp)) {
4965                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4966                        dev->name);
4967                 tg3_dump_short_state(tp);
4968         }
4969
4970         schedule_work(&tp->reset_task);
4971 }
4972
4973 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4974 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4975 {
4976         u32 base = (u32) mapping & 0xffffffff;
4977
4978         return ((base > 0xffffdcc0) &&
4979                 (base + len + 8 < base));
4980 }
4981
4982 /* Test for DMA addresses > 40-bit */
4983 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4984                                           int len)
4985 {
4986 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4987         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4988                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4989         return 0;
4990 #else
4991         return 0;
4992 #endif
4993 }
4994
4995 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4996
4997 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4998 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4999                                        u32 last_plus_one, u32 *start,
5000                                        u32 base_flags, u32 mss)
5001 {
5002         struct sk_buff *new_skb;
5003         dma_addr_t new_addr = 0;
5004         u32 entry = *start;
5005         int i, ret = 0;
5006
5007         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5008                 new_skb = skb_copy(skb, GFP_ATOMIC);
5009         else {
5010                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5011
5012                 new_skb = skb_copy_expand(skb,
5013                                           skb_headroom(skb) + more_headroom,
5014                                           skb_tailroom(skb), GFP_ATOMIC);
5015         }
5016
5017         if (!new_skb) {
5018                 ret = -1;
5019         } else {
5020                 /* New SKB is guaranteed to be linear. */
5021                 entry = *start;
5022                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5023                 new_addr = skb_shinfo(new_skb)->dma_maps[0];
5024
5025                 /* Make sure new skb does not cross any 4G boundaries.
5026                  * Drop the packet if it does.
5027                  */
5028                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5029                         if (!ret)
5030                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5031                                               DMA_TO_DEVICE);
5032                         ret = -1;
5033                         dev_kfree_skb(new_skb);
5034                         new_skb = NULL;
5035                 } else {
5036                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
5037                                     base_flags, 1 | (mss << 1));
5038                         *start = NEXT_TX(entry);
5039                 }
5040         }
5041
5042         /* Now clean up the sw ring entries. */
5043         i = 0;
5044         while (entry != last_plus_one) {
5045                 if (i == 0) {
5046                         tp->tx_buffers[entry].skb = new_skb;
5047                 } else {
5048                         tp->tx_buffers[entry].skb = NULL;
5049                 }
5050                 entry = NEXT_TX(entry);
5051                 i++;
5052         }
5053
5054         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5055         dev_kfree_skb(skb);
5056
5057         return ret;
5058 }
5059
5060 static void tg3_set_txd(struct tg3 *tp, int entry,
5061                         dma_addr_t mapping, int len, u32 flags,
5062                         u32 mss_and_is_end)
5063 {
5064         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5065         int is_end = (mss_and_is_end & 0x1);
5066         u32 mss = (mss_and_is_end >> 1);
5067         u32 vlan_tag = 0;
5068
5069         if (is_end)
5070                 flags |= TXD_FLAG_END;
5071         if (flags & TXD_FLAG_VLAN) {
5072                 vlan_tag = flags >> 16;
5073                 flags &= 0xffff;
5074         }
5075         vlan_tag |= (mss << TXD_MSS_SHIFT);
5076
5077         txd->addr_hi = ((u64) mapping >> 32);
5078         txd->addr_lo = ((u64) mapping & 0xffffffff);
5079         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5080         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5081 }
5082
5083 /* hard_start_xmit for devices that don't have any bugs and
5084  * support TG3_FLG2_HW_TSO_2 only.
5085  */
5086 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5087 {
5088         struct tg3 *tp = netdev_priv(dev);
5089         u32 len, entry, base_flags, mss;
5090         struct skb_shared_info *sp;
5091         dma_addr_t mapping;
5092
5093         len = skb_headlen(skb);
5094
5095         /* We are running in BH disabled context with netif_tx_lock
5096          * and TX reclaim runs via tp->napi.poll inside of a software
5097          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5098          * no IRQ context deadlocks to worry about either.  Rejoice!
5099          */
5100         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5101                 if (!netif_queue_stopped(dev)) {
5102                         netif_stop_queue(dev);
5103
5104                         /* This is a hard error, log it. */
5105                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5106                                "queue awake!\n", dev->name);
5107                 }
5108                 return NETDEV_TX_BUSY;
5109         }
5110
5111         entry = tp->tx_prod;
5112         base_flags = 0;
5113         mss = 0;
5114         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5115                 int tcp_opt_len, ip_tcp_len;
5116
5117                 if (skb_header_cloned(skb) &&
5118                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5119                         dev_kfree_skb(skb);
5120                         goto out_unlock;
5121                 }
5122
5123                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5124                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5125                 else {
5126                         struct iphdr *iph = ip_hdr(skb);
5127
5128                         tcp_opt_len = tcp_optlen(skb);
5129                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5130
5131                         iph->check = 0;
5132                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5133                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5134                 }
5135
5136                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5137                                TXD_FLAG_CPU_POST_DMA);
5138
5139                 tcp_hdr(skb)->check = 0;
5140
5141         }
5142         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5143                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5144 #if TG3_VLAN_TAG_USED
5145         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5146                 base_flags |= (TXD_FLAG_VLAN |
5147                                (vlan_tx_tag_get(skb) << 16));
5148 #endif
5149
5150         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5151                 dev_kfree_skb(skb);
5152                 goto out_unlock;
5153         }
5154
5155         sp = skb_shinfo(skb);
5156
5157         mapping = sp->dma_maps[0];
5158
5159         tp->tx_buffers[entry].skb = skb;
5160
5161         tg3_set_txd(tp, entry, mapping, len, base_flags,
5162                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5163
5164         entry = NEXT_TX(entry);
5165
5166         /* Now loop through additional data fragments, and queue them. */
5167         if (skb_shinfo(skb)->nr_frags > 0) {
5168                 unsigned int i, last;
5169
5170                 last = skb_shinfo(skb)->nr_frags - 1;
5171                 for (i = 0; i <= last; i++) {
5172                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5173
5174                         len = frag->size;
5175                         mapping = sp->dma_maps[i + 1];
5176                         tp->tx_buffers[entry].skb = NULL;
5177
5178                         tg3_set_txd(tp, entry, mapping, len,
5179                                     base_flags, (i == last) | (mss << 1));
5180
5181                         entry = NEXT_TX(entry);
5182                 }
5183         }
5184
5185         /* Packets are ready, update Tx producer idx local and on card. */
5186         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5187
5188         tp->tx_prod = entry;
5189         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5190                 netif_stop_queue(dev);
5191                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5192                         netif_wake_queue(tp->dev);
5193         }
5194
5195 out_unlock:
5196         mmiowb();
5197
5198         dev->trans_start = jiffies;
5199
5200         return NETDEV_TX_OK;
5201 }
5202
5203 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5204
5205 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5206  * TSO header is greater than 80 bytes.
5207  */
5208 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5209 {
5210         struct sk_buff *segs, *nskb;
5211
5212         /* Estimate the number of fragments in the worst case */
5213         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5214                 netif_stop_queue(tp->dev);
5215                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5216                         return NETDEV_TX_BUSY;
5217
5218                 netif_wake_queue(tp->dev);
5219         }
5220
5221         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5222         if (IS_ERR(segs))
5223                 goto tg3_tso_bug_end;
5224
5225         do {
5226                 nskb = segs;
5227                 segs = segs->next;
5228                 nskb->next = NULL;
5229                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5230         } while (segs);
5231
5232 tg3_tso_bug_end:
5233         dev_kfree_skb(skb);
5234
5235         return NETDEV_TX_OK;
5236 }
5237
5238 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5239  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5240  */
5241 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5242 {
5243         struct tg3 *tp = netdev_priv(dev);
5244         u32 len, entry, base_flags, mss;
5245         struct skb_shared_info *sp;
5246         int would_hit_hwbug;
5247         dma_addr_t mapping;
5248
5249         len = skb_headlen(skb);
5250
5251         /* We are running in BH disabled context with netif_tx_lock
5252          * and TX reclaim runs via tp->napi.poll inside of a software
5253          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5254          * no IRQ context deadlocks to worry about either.  Rejoice!
5255          */
5256         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5257                 if (!netif_queue_stopped(dev)) {
5258                         netif_stop_queue(dev);
5259
5260                         /* This is a hard error, log it. */
5261                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5262                                "queue awake!\n", dev->name);
5263                 }
5264                 return NETDEV_TX_BUSY;
5265         }
5266
5267         entry = tp->tx_prod;
5268         base_flags = 0;
5269         if (skb->ip_summed == CHECKSUM_PARTIAL)
5270                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5271         mss = 0;
5272         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5273                 struct iphdr *iph;
5274                 int tcp_opt_len, ip_tcp_len, hdr_len;
5275
5276                 if (skb_header_cloned(skb) &&
5277                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5278                         dev_kfree_skb(skb);
5279                         goto out_unlock;
5280                 }
5281
5282                 tcp_opt_len = tcp_optlen(skb);
5283                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5284
5285                 hdr_len = ip_tcp_len + tcp_opt_len;
5286                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5287                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5288                         return (tg3_tso_bug(tp, skb));
5289
5290                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5291                                TXD_FLAG_CPU_POST_DMA);
5292
5293                 iph = ip_hdr(skb);
5294                 iph->check = 0;
5295                 iph->tot_len = htons(mss + hdr_len);
5296                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5297                         tcp_hdr(skb)->check = 0;
5298                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5299                 } else
5300                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5301                                                                  iph->daddr, 0,
5302                                                                  IPPROTO_TCP,
5303                                                                  0);
5304
5305                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5306                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5307                         if (tcp_opt_len || iph->ihl > 5) {
5308                                 int tsflags;
5309
5310                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5311                                 mss |= (tsflags << 11);
5312                         }
5313                 } else {
5314                         if (tcp_opt_len || iph->ihl > 5) {
5315                                 int tsflags;
5316
5317                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5318                                 base_flags |= tsflags << 12;
5319                         }
5320                 }
5321         }
5322 #if TG3_VLAN_TAG_USED
5323         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5324                 base_flags |= (TXD_FLAG_VLAN |
5325                                (vlan_tx_tag_get(skb) << 16));
5326 #endif
5327
5328         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5329                 dev_kfree_skb(skb);
5330                 goto out_unlock;
5331         }
5332
5333         sp = skb_shinfo(skb);
5334
5335         mapping = sp->dma_maps[0];
5336
5337         tp->tx_buffers[entry].skb = skb;
5338
5339         would_hit_hwbug = 0;
5340
5341         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5342                 would_hit_hwbug = 1;
5343         else if (tg3_4g_overflow_test(mapping, len))
5344                 would_hit_hwbug = 1;
5345
5346         tg3_set_txd(tp, entry, mapping, len, base_flags,
5347                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5348
5349         entry = NEXT_TX(entry);
5350
5351         /* Now loop through additional data fragments, and queue them. */
5352         if (skb_shinfo(skb)->nr_frags > 0) {
5353                 unsigned int i, last;
5354
5355                 last = skb_shinfo(skb)->nr_frags - 1;
5356                 for (i = 0; i <= last; i++) {
5357                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5358
5359                         len = frag->size;
5360                         mapping = sp->dma_maps[i + 1];
5361
5362                         tp->tx_buffers[entry].skb = NULL;
5363
5364                         if (tg3_4g_overflow_test(mapping, len))
5365                                 would_hit_hwbug = 1;
5366
5367                         if (tg3_40bit_overflow_test(tp, mapping, len))
5368                                 would_hit_hwbug = 1;
5369
5370                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5371                                 tg3_set_txd(tp, entry, mapping, len,
5372                                             base_flags, (i == last)|(mss << 1));
5373                         else
5374                                 tg3_set_txd(tp, entry, mapping, len,
5375                                             base_flags, (i == last));
5376
5377                         entry = NEXT_TX(entry);
5378                 }
5379         }
5380
5381         if (would_hit_hwbug) {
5382                 u32 last_plus_one = entry;
5383                 u32 start;
5384
5385                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5386                 start &= (TG3_TX_RING_SIZE - 1);
5387
5388                 /* If the workaround fails due to memory/mapping
5389                  * failure, silently drop this packet.
5390                  */
5391                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5392                                                 &start, base_flags, mss))
5393                         goto out_unlock;
5394
5395                 entry = start;
5396         }
5397
5398         /* Packets are ready, update Tx producer idx local and on card. */
5399         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5400
5401         tp->tx_prod = entry;
5402         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5403                 netif_stop_queue(dev);
5404                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5405                         netif_wake_queue(tp->dev);
5406         }
5407
5408 out_unlock:
5409         mmiowb();
5410
5411         dev->trans_start = jiffies;
5412
5413         return NETDEV_TX_OK;
5414 }
5415
5416 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5417                                int new_mtu)
5418 {
5419         dev->mtu = new_mtu;
5420
5421         if (new_mtu > ETH_DATA_LEN) {
5422                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5423                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5424                         ethtool_op_set_tso(dev, 0);
5425                 }
5426                 else
5427                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5428         } else {
5429                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5430                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5431                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5432         }
5433 }
5434
5435 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5436 {
5437         struct tg3 *tp = netdev_priv(dev);
5438         int err;
5439
5440         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5441                 return -EINVAL;
5442
5443         if (!netif_running(dev)) {
5444                 /* We'll just catch it later when the
5445                  * device is up'd.
5446                  */
5447                 tg3_set_mtu(dev, tp, new_mtu);
5448                 return 0;
5449         }
5450
5451         tg3_phy_stop(tp);
5452
5453         tg3_netif_stop(tp);
5454
5455         tg3_full_lock(tp, 1);
5456
5457         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5458
5459         tg3_set_mtu(dev, tp, new_mtu);
5460
5461         err = tg3_restart_hw(tp, 0);
5462
5463         if (!err)
5464                 tg3_netif_start(tp);
5465
5466         tg3_full_unlock(tp);
5467
5468         if (!err)
5469                 tg3_phy_start(tp);
5470
5471         return err;
5472 }
5473
5474 /* Free up pending packets in all rx/tx rings.
5475  *
5476  * The chip has been shut down and the driver detached from
5477  * the networking, so no interrupts or new tx packets will
5478  * end up in the driver.  tp->{tx,}lock is not held and we are not
5479  * in an interrupt context and thus may sleep.
5480  */
5481 static void tg3_free_rings(struct tg3 *tp)
5482 {
5483         struct ring_info *rxp;
5484         int i;
5485
5486         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5487                 rxp = &tp->rx_std_buffers[i];
5488
5489                 if (rxp->skb == NULL)
5490                         continue;
5491                 pci_unmap_single(tp->pdev,
5492                                  pci_unmap_addr(rxp, mapping),
5493                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5494                                  PCI_DMA_FROMDEVICE);
5495                 dev_kfree_skb_any(rxp->skb);
5496                 rxp->skb = NULL;
5497         }
5498
5499         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5500                 rxp = &tp->rx_jumbo_buffers[i];
5501
5502                 if (rxp->skb == NULL)
5503                         continue;
5504                 pci_unmap_single(tp->pdev,
5505                                  pci_unmap_addr(rxp, mapping),
5506                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5507                                  PCI_DMA_FROMDEVICE);
5508                 dev_kfree_skb_any(rxp->skb);
5509                 rxp->skb = NULL;
5510         }
5511
5512         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5513                 struct tx_ring_info *txp;
5514                 struct sk_buff *skb;
5515
5516                 txp = &tp->tx_buffers[i];
5517                 skb = txp->skb;
5518
5519                 if (skb == NULL) {
5520                         i++;
5521                         continue;
5522                 }
5523
5524                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5525
5526                 txp->skb = NULL;
5527
5528                 i += skb_shinfo(skb)->nr_frags + 1;
5529
5530                 dev_kfree_skb_any(skb);
5531         }
5532 }
5533
5534 /* Initialize tx/rx rings for packet processing.
5535  *
5536  * The chip has been shut down and the driver detached from
5537  * the networking, so no interrupts or new tx packets will
5538  * end up in the driver.  tp->{tx,}lock are held and thus
5539  * we may not sleep.
5540  */
5541 static int tg3_init_rings(struct tg3 *tp)
5542 {
5543         u32 i;
5544
5545         /* Free up all the SKBs. */
5546         tg3_free_rings(tp);
5547
5548         /* Zero out all descriptors. */
5549         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5550         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5551         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5552         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5553
5554         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5555         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5556             (tp->dev->mtu > ETH_DATA_LEN))
5557                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5558
5559         /* Initialize invariants of the rings, we only set this
5560          * stuff once.  This works because the card does not
5561          * write into the rx buffer posting rings.
5562          */
5563         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5564                 struct tg3_rx_buffer_desc *rxd;
5565
5566                 rxd = &tp->rx_std[i];
5567                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5568                         << RXD_LEN_SHIFT;
5569                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5570                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5571                                (i << RXD_OPAQUE_INDEX_SHIFT));
5572         }
5573
5574         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5575                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5576                         struct tg3_rx_buffer_desc *rxd;
5577
5578                         rxd = &tp->rx_jumbo[i];
5579                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5580                                 << RXD_LEN_SHIFT;
5581                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5582                                 RXD_FLAG_JUMBO;
5583                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5584                                (i << RXD_OPAQUE_INDEX_SHIFT));
5585                 }
5586         }
5587
5588         /* Now allocate fresh SKBs for each rx ring. */
5589         for (i = 0; i < tp->rx_pending; i++) {
5590                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5591                         printk(KERN_WARNING PFX
5592                                "%s: Using a smaller RX standard ring, "
5593                                "only %d out of %d buffers were allocated "
5594                                "successfully.\n",
5595                                tp->dev->name, i, tp->rx_pending);
5596                         if (i == 0)
5597                                 return -ENOMEM;
5598                         tp->rx_pending = i;
5599                         break;
5600                 }
5601         }
5602
5603         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5604                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5605                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5606                                              -1, i) < 0) {
5607                                 printk(KERN_WARNING PFX
5608                                        "%s: Using a smaller RX jumbo ring, "
5609                                        "only %d out of %d buffers were "
5610                                        "allocated successfully.\n",
5611                                        tp->dev->name, i, tp->rx_jumbo_pending);
5612                                 if (i == 0) {
5613                                         tg3_free_rings(tp);
5614                                         return -ENOMEM;
5615                                 }
5616                                 tp->rx_jumbo_pending = i;
5617                                 break;
5618                         }
5619                 }
5620         }
5621         return 0;
5622 }
5623
5624 /*
5625  * Must not be invoked with interrupt sources disabled and
5626  * the hardware shutdown down.
5627  */
5628 static void tg3_free_consistent(struct tg3 *tp)
5629 {
5630         kfree(tp->rx_std_buffers);
5631         tp->rx_std_buffers = NULL;
5632         if (tp->rx_std) {
5633                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5634                                     tp->rx_std, tp->rx_std_mapping);
5635                 tp->rx_std = NULL;
5636         }
5637         if (tp->rx_jumbo) {
5638                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5639                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5640                 tp->rx_jumbo = NULL;
5641         }
5642         if (tp->rx_rcb) {
5643                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5644                                     tp->rx_rcb, tp->rx_rcb_mapping);
5645                 tp->rx_rcb = NULL;
5646         }
5647         if (tp->tx_ring) {
5648                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5649                         tp->tx_ring, tp->tx_desc_mapping);
5650                 tp->tx_ring = NULL;
5651         }
5652         if (tp->hw_status) {
5653                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5654                                     tp->hw_status, tp->status_mapping);
5655                 tp->hw_status = NULL;
5656         }
5657         if (tp->hw_stats) {
5658                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5659                                     tp->hw_stats, tp->stats_mapping);
5660                 tp->hw_stats = NULL;
5661         }
5662 }
5663
5664 /*
5665  * Must not be invoked with interrupt sources disabled and
5666  * the hardware shutdown down.  Can sleep.
5667  */
5668 static int tg3_alloc_consistent(struct tg3 *tp)
5669 {
5670         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5671                                       (TG3_RX_RING_SIZE +
5672                                        TG3_RX_JUMBO_RING_SIZE)) +
5673                                      (sizeof(struct tx_ring_info) *
5674                                       TG3_TX_RING_SIZE),
5675                                      GFP_KERNEL);
5676         if (!tp->rx_std_buffers)
5677                 return -ENOMEM;
5678
5679         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5680         tp->tx_buffers = (struct tx_ring_info *)
5681                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5682
5683         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5684                                           &tp->rx_std_mapping);
5685         if (!tp->rx_std)
5686                 goto err_out;
5687
5688         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5689                                             &tp->rx_jumbo_mapping);
5690
5691         if (!tp->rx_jumbo)
5692                 goto err_out;
5693
5694         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5695                                           &tp->rx_rcb_mapping);
5696         if (!tp->rx_rcb)
5697                 goto err_out;
5698
5699         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5700                                            &tp->tx_desc_mapping);
5701         if (!tp->tx_ring)
5702                 goto err_out;
5703
5704         tp->hw_status = pci_alloc_consistent(tp->pdev,
5705                                              TG3_HW_STATUS_SIZE,
5706                                              &tp->status_mapping);
5707         if (!tp->hw_status)
5708                 goto err_out;
5709
5710         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5711                                             sizeof(struct tg3_hw_stats),
5712                                             &tp->stats_mapping);
5713         if (!tp->hw_stats)
5714                 goto err_out;
5715
5716         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5717         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5718
5719         return 0;
5720
5721 err_out:
5722         tg3_free_consistent(tp);
5723         return -ENOMEM;
5724 }
5725
5726 #define MAX_WAIT_CNT 1000
5727
5728 /* To stop a block, clear the enable bit and poll till it
5729  * clears.  tp->lock is held.
5730  */
5731 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5732 {
5733         unsigned int i;
5734         u32 val;
5735
5736         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5737                 switch (ofs) {
5738                 case RCVLSC_MODE:
5739                 case DMAC_MODE:
5740                 case MBFREE_MODE:
5741                 case BUFMGR_MODE:
5742                 case MEMARB_MODE:
5743                         /* We can't enable/disable these bits of the
5744                          * 5705/5750, just say success.
5745                          */
5746                         return 0;
5747
5748                 default:
5749                         break;
5750                 }
5751         }
5752
5753         val = tr32(ofs);
5754         val &= ~enable_bit;
5755         tw32_f(ofs, val);
5756
5757         for (i = 0; i < MAX_WAIT_CNT; i++) {
5758                 udelay(100);
5759                 val = tr32(ofs);
5760                 if ((val & enable_bit) == 0)
5761                         break;
5762         }
5763
5764         if (i == MAX_WAIT_CNT && !silent) {
5765                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5766                        "ofs=%lx enable_bit=%x\n",
5767                        ofs, enable_bit);
5768                 return -ENODEV;
5769         }
5770
5771         return 0;
5772 }
5773
5774 /* tp->lock is held. */
5775 static int tg3_abort_hw(struct tg3 *tp, int silent)
5776 {
5777         int i, err;
5778
5779         tg3_disable_ints(tp);
5780
5781         tp->rx_mode &= ~RX_MODE_ENABLE;
5782         tw32_f(MAC_RX_MODE, tp->rx_mode);
5783         udelay(10);
5784
5785         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5786         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5787         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5788         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5789         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5790         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5791
5792         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5793         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5794         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5795         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5796         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5797         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5798         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5799
5800         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5801         tw32_f(MAC_MODE, tp->mac_mode);
5802         udelay(40);
5803
5804         tp->tx_mode &= ~TX_MODE_ENABLE;
5805         tw32_f(MAC_TX_MODE, tp->tx_mode);
5806
5807         for (i = 0; i < MAX_WAIT_CNT; i++) {
5808                 udelay(100);
5809                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5810                         break;
5811         }
5812         if (i >= MAX_WAIT_CNT) {
5813                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5814                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5815                        tp->dev->name, tr32(MAC_TX_MODE));
5816                 err |= -ENODEV;
5817         }
5818
5819         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5820         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5821         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5822
5823         tw32(FTQ_RESET, 0xffffffff);
5824         tw32(FTQ_RESET, 0x00000000);
5825
5826         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5827         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5828
5829         if (tp->hw_status)
5830                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5831         if (tp->hw_stats)
5832                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5833
5834         return err;
5835 }
5836
5837 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5838 {
5839         int i;
5840         u32 apedata;
5841
5842         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5843         if (apedata != APE_SEG_SIG_MAGIC)
5844                 return;
5845
5846         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5847         if (!(apedata & APE_FW_STATUS_READY))
5848                 return;
5849
5850         /* Wait for up to 1 millisecond for APE to service previous event. */
5851         for (i = 0; i < 10; i++) {
5852                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5853                         return;
5854
5855                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5856
5857                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5858                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5859                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5860
5861                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5862
5863                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5864                         break;
5865
5866                 udelay(100);
5867         }
5868
5869         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5870                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5871 }
5872
5873 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5874 {
5875         u32 event;
5876         u32 apedata;
5877
5878         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5879                 return;
5880
5881         switch (kind) {
5882                 case RESET_KIND_INIT:
5883                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5884                                         APE_HOST_SEG_SIG_MAGIC);
5885                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5886                                         APE_HOST_SEG_LEN_MAGIC);
5887                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5888                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5889                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5890                                         APE_HOST_DRIVER_ID_MAGIC);
5891                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5892                                         APE_HOST_BEHAV_NO_PHYLOCK);
5893
5894                         event = APE_EVENT_STATUS_STATE_START;
5895                         break;
5896                 case RESET_KIND_SHUTDOWN:
5897                         /* With the interface we are currently using,
5898                          * APE does not track driver state.  Wiping
5899                          * out the HOST SEGMENT SIGNATURE forces
5900                          * the APE to assume OS absent status.
5901                          */
5902                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5903
5904                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5905                         break;
5906                 case RESET_KIND_SUSPEND:
5907                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5908                         break;
5909                 default:
5910                         return;
5911         }
5912
5913         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5914
5915         tg3_ape_send_event(tp, event);
5916 }
5917
5918 /* tp->lock is held. */
5919 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5920 {
5921         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5922                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5923
5924         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5925                 switch (kind) {
5926                 case RESET_KIND_INIT:
5927                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5928                                       DRV_STATE_START);
5929                         break;
5930
5931                 case RESET_KIND_SHUTDOWN:
5932                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5933                                       DRV_STATE_UNLOAD);
5934                         break;
5935
5936                 case RESET_KIND_SUSPEND:
5937                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5938                                       DRV_STATE_SUSPEND);
5939                         break;
5940
5941                 default:
5942                         break;
5943                 }
5944         }
5945
5946         if (kind == RESET_KIND_INIT ||
5947             kind == RESET_KIND_SUSPEND)
5948                 tg3_ape_driver_state_change(tp, kind);
5949 }
5950
5951 /* tp->lock is held. */
5952 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5953 {
5954         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5955                 switch (kind) {
5956                 case RESET_KIND_INIT:
5957                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5958                                       DRV_STATE_START_DONE);
5959                         break;
5960
5961                 case RESET_KIND_SHUTDOWN:
5962                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5963                                       DRV_STATE_UNLOAD_DONE);
5964                         break;
5965
5966                 default:
5967                         break;
5968                 }
5969         }
5970
5971         if (kind == RESET_KIND_SHUTDOWN)
5972                 tg3_ape_driver_state_change(tp, kind);
5973 }
5974
5975 /* tp->lock is held. */
5976 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5977 {
5978         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5979                 switch (kind) {
5980                 case RESET_KIND_INIT:
5981                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5982                                       DRV_STATE_START);
5983                         break;
5984
5985                 case RESET_KIND_SHUTDOWN:
5986                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5987                                       DRV_STATE_UNLOAD);
5988                         break;
5989
5990                 case RESET_KIND_SUSPEND:
5991                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5992                                       DRV_STATE_SUSPEND);
5993                         break;
5994
5995                 default:
5996                         break;
5997                 }
5998         }
5999 }
6000
6001 static int tg3_poll_fw(struct tg3 *tp)
6002 {
6003         int i;
6004         u32 val;
6005
6006         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6007                 /* Wait up to 20ms for init done. */
6008                 for (i = 0; i < 200; i++) {
6009                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6010                                 return 0;
6011                         udelay(100);
6012                 }
6013                 return -ENODEV;
6014         }
6015
6016         /* Wait for firmware initialization to complete. */
6017         for (i = 0; i < 100000; i++) {
6018                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6019                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6020                         break;
6021                 udelay(10);
6022         }
6023
6024         /* Chip might not be fitted with firmware.  Some Sun onboard
6025          * parts are configured like that.  So don't signal the timeout
6026          * of the above loop as an error, but do report the lack of
6027          * running firmware once.
6028          */
6029         if (i >= 100000 &&
6030             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6031                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6032
6033                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6034                        tp->dev->name);
6035         }
6036
6037         return 0;
6038 }
6039
6040 /* Save PCI command register before chip reset */
6041 static void tg3_save_pci_state(struct tg3 *tp)
6042 {
6043         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6044 }
6045
6046 /* Restore PCI state after chip reset */
6047 static void tg3_restore_pci_state(struct tg3 *tp)
6048 {
6049         u32 val;
6050
6051         /* Re-enable indirect register accesses. */
6052         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6053                                tp->misc_host_ctrl);
6054
6055         /* Set MAX PCI retry to zero. */
6056         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6057         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6058             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6059                 val |= PCISTATE_RETRY_SAME_DMA;
6060         /* Allow reads and writes to the APE register and memory space. */
6061         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6062                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6063                        PCISTATE_ALLOW_APE_SHMEM_WR;
6064         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6065
6066         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6067
6068         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6069                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6070                         pcie_set_readrq(tp->pdev, 4096);
6071                 else {
6072                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6073                                               tp->pci_cacheline_sz);
6074                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6075                                               tp->pci_lat_timer);
6076                 }
6077         }
6078
6079         /* Make sure PCI-X relaxed ordering bit is clear. */
6080         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6081                 u16 pcix_cmd;
6082
6083                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6084                                      &pcix_cmd);
6085                 pcix_cmd &= ~PCI_X_CMD_ERO;
6086                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6087                                       pcix_cmd);
6088         }
6089
6090         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6091
6092                 /* Chip reset on 5780 will reset MSI enable bit,
6093                  * so need to restore it.
6094                  */
6095                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6096                         u16 ctrl;
6097
6098                         pci_read_config_word(tp->pdev,
6099                                              tp->msi_cap + PCI_MSI_FLAGS,
6100                                              &ctrl);
6101                         pci_write_config_word(tp->pdev,
6102                                               tp->msi_cap + PCI_MSI_FLAGS,
6103                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6104                         val = tr32(MSGINT_MODE);
6105                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6106                 }
6107         }
6108 }
6109
6110 static void tg3_stop_fw(struct tg3 *);
6111
6112 /* tp->lock is held. */
6113 static int tg3_chip_reset(struct tg3 *tp)
6114 {
6115         u32 val;
6116         void (*write_op)(struct tg3 *, u32, u32);
6117         int err;
6118
6119         tg3_nvram_lock(tp);
6120
6121         tg3_mdio_stop(tp);
6122
6123         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6124
6125         /* No matching tg3_nvram_unlock() after this because
6126          * chip reset below will undo the nvram lock.
6127          */
6128         tp->nvram_lock_cnt = 0;
6129
6130         /* GRC_MISC_CFG core clock reset will clear the memory
6131          * enable bit in PCI register 4 and the MSI enable bit
6132          * on some chips, so we save relevant registers here.
6133          */
6134         tg3_save_pci_state(tp);
6135
6136         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6137             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6138                 tw32(GRC_FASTBOOT_PC, 0);
6139
6140         /*
6141          * We must avoid the readl() that normally takes place.
6142          * It locks machines, causes machine checks, and other
6143          * fun things.  So, temporarily disable the 5701
6144          * hardware workaround, while we do the reset.
6145          */
6146         write_op = tp->write32;
6147         if (write_op == tg3_write_flush_reg32)
6148                 tp->write32 = tg3_write32;
6149
6150         /* Prevent the irq handler from reading or writing PCI registers
6151          * during chip reset when the memory enable bit in the PCI command
6152          * register may be cleared.  The chip does not generate interrupt
6153          * at this time, but the irq handler may still be called due to irq
6154          * sharing or irqpoll.
6155          */
6156         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6157         if (tp->hw_status) {
6158                 tp->hw_status->status = 0;
6159                 tp->hw_status->status_tag = 0;
6160         }
6161         tp->last_tag = 0;
6162         smp_mb();
6163         synchronize_irq(tp->pdev->irq);
6164
6165         /* do the reset */
6166         val = GRC_MISC_CFG_CORECLK_RESET;
6167
6168         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6169                 if (tr32(0x7e2c) == 0x60) {
6170                         tw32(0x7e2c, 0x20);
6171                 }
6172                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6173                         tw32(GRC_MISC_CFG, (1 << 29));
6174                         val |= (1 << 29);
6175                 }
6176         }
6177
6178         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6179                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6180                 tw32(GRC_VCPU_EXT_CTRL,
6181                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6182         }
6183
6184         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6185                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6186         tw32(GRC_MISC_CFG, val);
6187
6188         /* restore 5701 hardware bug workaround write method */
6189         tp->write32 = write_op;
6190
6191         /* Unfortunately, we have to delay before the PCI read back.
6192          * Some 575X chips even will not respond to a PCI cfg access
6193          * when the reset command is given to the chip.
6194          *
6195          * How do these hardware designers expect things to work
6196          * properly if the PCI write is posted for a long period
6197          * of time?  It is always necessary to have some method by
6198          * which a register read back can occur to push the write
6199          * out which does the reset.
6200          *
6201          * For most tg3 variants the trick below was working.
6202          * Ho hum...
6203          */
6204         udelay(120);
6205
6206         /* Flush PCI posted writes.  The normal MMIO registers
6207          * are inaccessible at this time so this is the only
6208          * way to make this reliably (actually, this is no longer
6209          * the case, see above).  I tried to use indirect
6210          * register read/write but this upset some 5701 variants.
6211          */
6212         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6213
6214         udelay(120);
6215
6216         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6217                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6218                         int i;
6219                         u32 cfg_val;
6220
6221                         /* Wait for link training to complete.  */
6222                         for (i = 0; i < 5000; i++)
6223                                 udelay(100);
6224
6225                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6226                         pci_write_config_dword(tp->pdev, 0xc4,
6227                                                cfg_val | (1 << 15));
6228                 }
6229
6230                 /* Set PCIE max payload size to 128 bytes and
6231                  * clear the "no snoop" and "relaxed ordering" bits.
6232                  */
6233                 pci_write_config_word(tp->pdev,
6234                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6235                                       0);
6236
6237                 pcie_set_readrq(tp->pdev, 4096);
6238
6239                 /* Clear error status */
6240                 pci_write_config_word(tp->pdev,
6241                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6242                                       PCI_EXP_DEVSTA_CED |
6243                                       PCI_EXP_DEVSTA_NFED |
6244                                       PCI_EXP_DEVSTA_FED |
6245                                       PCI_EXP_DEVSTA_URD);
6246         }
6247
6248         tg3_restore_pci_state(tp);
6249
6250         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6251
6252         val = 0;
6253         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6254                 val = tr32(MEMARB_MODE);
6255         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6256
6257         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6258                 tg3_stop_fw(tp);
6259                 tw32(0x5000, 0x400);
6260         }
6261
6262         tw32(GRC_MODE, tp->grc_mode);
6263
6264         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6265                 val = tr32(0xc4);
6266
6267                 tw32(0xc4, val | (1 << 15));
6268         }
6269
6270         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6271             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6272                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6273                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6274                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6275                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6276         }
6277
6278         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6279                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6280                 tw32_f(MAC_MODE, tp->mac_mode);
6281         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6282                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6283                 tw32_f(MAC_MODE, tp->mac_mode);
6284         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6285                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6286                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6287                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6288                 tw32_f(MAC_MODE, tp->mac_mode);
6289         } else
6290                 tw32_f(MAC_MODE, 0);
6291         udelay(40);
6292
6293         tg3_mdio_start(tp);
6294
6295         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6296
6297         err = tg3_poll_fw(tp);
6298         if (err)
6299                 return err;
6300
6301         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6302             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6303                 val = tr32(0x7c00);
6304
6305                 tw32(0x7c00, val | (1 << 25));
6306         }
6307
6308         /* Reprobe ASF enable state.  */
6309         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6310         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6311         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6312         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6313                 u32 nic_cfg;
6314
6315                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6316                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6317                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6318                         tp->last_event_jiffies = jiffies;
6319                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6320                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6321                 }
6322         }
6323
6324         return 0;
6325 }
6326
6327 /* tp->lock is held. */
6328 static void tg3_stop_fw(struct tg3 *tp)
6329 {
6330         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6331            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6332                 /* Wait for RX cpu to ACK the previous event. */
6333                 tg3_wait_for_event_ack(tp);
6334
6335                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6336
6337                 tg3_generate_fw_event(tp);
6338
6339                 /* Wait for RX cpu to ACK this event. */
6340                 tg3_wait_for_event_ack(tp);
6341         }
6342 }
6343
6344 /* tp->lock is held. */
6345 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6346 {
6347         int err;
6348
6349         tg3_stop_fw(tp);
6350
6351         tg3_write_sig_pre_reset(tp, kind);
6352
6353         tg3_abort_hw(tp, silent);
6354         err = tg3_chip_reset(tp);
6355
6356         tg3_write_sig_legacy(tp, kind);
6357         tg3_write_sig_post_reset(tp, kind);
6358
6359         if (err)
6360                 return err;
6361
6362         return 0;
6363 }
6364
6365 #define RX_CPU_SCRATCH_BASE     0x30000
6366 #define RX_CPU_SCRATCH_SIZE     0x04000
6367 #define TX_CPU_SCRATCH_BASE     0x34000
6368 #define TX_CPU_SCRATCH_SIZE     0x04000
6369
6370 /* tp->lock is held. */
6371 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6372 {
6373         int i;
6374
6375         BUG_ON(offset == TX_CPU_BASE &&
6376             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6377
6378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6379                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6380
6381                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6382                 return 0;
6383         }
6384         if (offset == RX_CPU_BASE) {
6385                 for (i = 0; i < 10000; i++) {
6386                         tw32(offset + CPU_STATE, 0xffffffff);
6387                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6388                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6389                                 break;
6390                 }
6391
6392                 tw32(offset + CPU_STATE, 0xffffffff);
6393                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6394                 udelay(10);
6395         } else {
6396                 for (i = 0; i < 10000; i++) {
6397                         tw32(offset + CPU_STATE, 0xffffffff);
6398                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6399                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6400                                 break;
6401                 }
6402         }
6403
6404         if (i >= 10000) {
6405                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6406                        "and %s CPU\n",
6407                        tp->dev->name,
6408                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6409                 return -ENODEV;
6410         }
6411
6412         /* Clear firmware's nvram arbitration. */
6413         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6414                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6415         return 0;
6416 }
6417
6418 struct fw_info {
6419         unsigned int fw_base;
6420         unsigned int fw_len;
6421         const __be32 *fw_data;
6422 };
6423
6424 /* tp->lock is held. */
6425 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6426                                  int cpu_scratch_size, struct fw_info *info)
6427 {
6428         int err, lock_err, i;
6429         void (*write_op)(struct tg3 *, u32, u32);
6430
6431         if (cpu_base == TX_CPU_BASE &&
6432             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6433                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6434                        "TX cpu firmware on %s which is 5705.\n",
6435                        tp->dev->name);
6436                 return -EINVAL;
6437         }
6438
6439         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6440                 write_op = tg3_write_mem;
6441         else
6442                 write_op = tg3_write_indirect_reg32;
6443
6444         /* It is possible that bootcode is still loading at this point.
6445          * Get the nvram lock first before halting the cpu.
6446          */
6447         lock_err = tg3_nvram_lock(tp);
6448         err = tg3_halt_cpu(tp, cpu_base);
6449         if (!lock_err)
6450                 tg3_nvram_unlock(tp);
6451         if (err)
6452                 goto out;
6453
6454         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6455                 write_op(tp, cpu_scratch_base + i, 0);
6456         tw32(cpu_base + CPU_STATE, 0xffffffff);
6457         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6458         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6459                 write_op(tp, (cpu_scratch_base +
6460                               (info->fw_base & 0xffff) +
6461                               (i * sizeof(u32))),
6462                               be32_to_cpu(info->fw_data[i]));
6463
6464         err = 0;
6465
6466 out:
6467         return err;
6468 }
6469
6470 /* tp->lock is held. */
6471 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6472 {
6473         struct fw_info info;
6474         const __be32 *fw_data;
6475         int err, i;
6476
6477         fw_data = (void *)tp->fw->data;
6478
6479         /* Firmware blob starts with version numbers, followed by
6480            start address and length. We are setting complete length.
6481            length = end_address_of_bss - start_address_of_text.
6482            Remainder is the blob to be loaded contiguously
6483            from start address. */
6484
6485         info.fw_base = be32_to_cpu(fw_data[1]);
6486         info.fw_len = tp->fw->size - 12;
6487         info.fw_data = &fw_data[3];
6488
6489         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6490                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6491                                     &info);
6492         if (err)
6493                 return err;
6494
6495         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6496                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6497                                     &info);
6498         if (err)
6499                 return err;
6500
6501         /* Now startup only the RX cpu. */
6502         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6503         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6504
6505         for (i = 0; i < 5; i++) {
6506                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6507                         break;
6508                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6509                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6510                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6511                 udelay(1000);
6512         }
6513         if (i >= 5) {
6514                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6515                        "to set RX CPU PC, is %08x should be %08x\n",
6516                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6517                        info.fw_base);
6518                 return -ENODEV;
6519         }
6520         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6521         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6522
6523         return 0;
6524 }
6525
6526 /* 5705 needs a special version of the TSO firmware.  */
6527
6528 /* tp->lock is held. */
6529 static int tg3_load_tso_firmware(struct tg3 *tp)
6530 {
6531         struct fw_info info;
6532         const __be32 *fw_data;
6533         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6534         int err, i;
6535
6536         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6537                 return 0;
6538
6539         fw_data = (void *)tp->fw->data;
6540
6541         /* Firmware blob starts with version numbers, followed by
6542            start address and length. We are setting complete length.
6543            length = end_address_of_bss - start_address_of_text.
6544            Remainder is the blob to be loaded contiguously
6545            from start address. */
6546
6547         info.fw_base = be32_to_cpu(fw_data[1]);
6548         cpu_scratch_size = tp->fw_len;
6549         info.fw_len = tp->fw->size - 12;
6550         info.fw_data = &fw_data[3];
6551
6552         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6553                 cpu_base = RX_CPU_BASE;
6554                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6555         } else {
6556                 cpu_base = TX_CPU_BASE;
6557                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6558                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6559         }
6560
6561         err = tg3_load_firmware_cpu(tp, cpu_base,
6562                                     cpu_scratch_base, cpu_scratch_size,
6563                                     &info);
6564         if (err)
6565                 return err;
6566
6567         /* Now startup the cpu. */
6568         tw32(cpu_base + CPU_STATE, 0xffffffff);
6569         tw32_f(cpu_base + CPU_PC, info.fw_base);
6570
6571         for (i = 0; i < 5; i++) {
6572                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6573                         break;
6574                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6575                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6576                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6577                 udelay(1000);
6578         }
6579         if (i >= 5) {
6580                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6581                        "to set CPU PC, is %08x should be %08x\n",
6582                        tp->dev->name, tr32(cpu_base + CPU_PC),
6583                        info.fw_base);
6584                 return -ENODEV;
6585         }
6586         tw32(cpu_base + CPU_STATE, 0xffffffff);
6587         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6588         return 0;
6589 }
6590
6591
6592 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6593 {
6594         struct tg3 *tp = netdev_priv(dev);
6595         struct sockaddr *addr = p;
6596         int err = 0, skip_mac_1 = 0;
6597
6598         if (!is_valid_ether_addr(addr->sa_data))
6599                 return -EINVAL;
6600
6601         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6602
6603         if (!netif_running(dev))
6604                 return 0;
6605
6606         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6607                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6608
6609                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6610                 addr0_low = tr32(MAC_ADDR_0_LOW);
6611                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6612                 addr1_low = tr32(MAC_ADDR_1_LOW);
6613
6614                 /* Skip MAC addr 1 if ASF is using it. */
6615                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6616                     !(addr1_high == 0 && addr1_low == 0))
6617                         skip_mac_1 = 1;
6618         }
6619         spin_lock_bh(&tp->lock);
6620         __tg3_set_mac_addr(tp, skip_mac_1);
6621         spin_unlock_bh(&tp->lock);
6622
6623         return err;
6624 }
6625
6626 /* tp->lock is held. */
6627 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6628                            dma_addr_t mapping, u32 maxlen_flags,
6629                            u32 nic_addr)
6630 {
6631         tg3_write_mem(tp,
6632                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6633                       ((u64) mapping >> 32));
6634         tg3_write_mem(tp,
6635                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6636                       ((u64) mapping & 0xffffffff));
6637         tg3_write_mem(tp,
6638                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6639                        maxlen_flags);
6640
6641         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6642                 tg3_write_mem(tp,
6643                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6644                               nic_addr);
6645 }
6646
6647 static void __tg3_set_rx_mode(struct net_device *);
6648 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6649 {
6650         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6651         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6652         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6653         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6654         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6655                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6656                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6657         }
6658         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6659         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6660         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6661                 u32 val = ec->stats_block_coalesce_usecs;
6662
6663                 if (!netif_carrier_ok(tp->dev))
6664                         val = 0;
6665
6666                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6667         }
6668 }
6669
6670 /* tp->lock is held. */
6671 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6672 {
6673         u32 val, rdmac_mode;
6674         int i, err, limit;
6675
6676         tg3_disable_ints(tp);
6677
6678         tg3_stop_fw(tp);
6679
6680         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6681
6682         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6683                 tg3_abort_hw(tp, 1);
6684         }
6685
6686         if (reset_phy &&
6687             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6688                 tg3_phy_reset(tp);
6689
6690         err = tg3_chip_reset(tp);
6691         if (err)
6692                 return err;
6693
6694         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6695
6696         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6697                 val = tr32(TG3_CPMU_CTRL);
6698                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6699                 tw32(TG3_CPMU_CTRL, val);
6700
6701                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6702                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6703                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6704                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6705
6706                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6707                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6708                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6709                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6710
6711                 val = tr32(TG3_CPMU_HST_ACC);
6712                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6713                 val |= CPMU_HST_ACC_MACCLK_6_25;
6714                 tw32(TG3_CPMU_HST_ACC, val);
6715         }
6716
6717         /* This works around an issue with Athlon chipsets on
6718          * B3 tigon3 silicon.  This bit has no effect on any
6719          * other revision.  But do not set this on PCI Express
6720          * chips and don't even touch the clocks if the CPMU is present.
6721          */
6722         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6723                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6724                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6725                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6726         }
6727
6728         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6729             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6730                 val = tr32(TG3PCI_PCISTATE);
6731                 val |= PCISTATE_RETRY_SAME_DMA;
6732                 tw32(TG3PCI_PCISTATE, val);
6733         }
6734
6735         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6736                 /* Allow reads and writes to the
6737                  * APE register and memory space.
6738                  */
6739                 val = tr32(TG3PCI_PCISTATE);
6740                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6741                        PCISTATE_ALLOW_APE_SHMEM_WR;
6742                 tw32(TG3PCI_PCISTATE, val);
6743         }
6744
6745         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6746                 /* Enable some hw fixes.  */
6747                 val = tr32(TG3PCI_MSI_DATA);
6748                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6749                 tw32(TG3PCI_MSI_DATA, val);
6750         }
6751
6752         /* Descriptor ring init may make accesses to the
6753          * NIC SRAM area to setup the TX descriptors, so we
6754          * can only do this after the hardware has been
6755          * successfully reset.
6756          */
6757         err = tg3_init_rings(tp);
6758         if (err)
6759                 return err;
6760
6761         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6762             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6763                 /* This value is determined during the probe time DMA
6764                  * engine test, tg3_test_dma.
6765                  */
6766                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6767         }
6768
6769         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6770                           GRC_MODE_4X_NIC_SEND_RINGS |
6771                           GRC_MODE_NO_TX_PHDR_CSUM |
6772                           GRC_MODE_NO_RX_PHDR_CSUM);
6773         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6774
6775         /* Pseudo-header checksum is done by hardware logic and not
6776          * the offload processers, so make the chip do the pseudo-
6777          * header checksums on receive.  For transmit it is more
6778          * convenient to do the pseudo-header checksum in software
6779          * as Linux does that on transmit for us in all cases.
6780          */
6781         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6782
6783         tw32(GRC_MODE,
6784              tp->grc_mode |
6785              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6786
6787         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6788         val = tr32(GRC_MISC_CFG);
6789         val &= ~0xff;
6790         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6791         tw32(GRC_MISC_CFG, val);
6792
6793         /* Initialize MBUF/DESC pool. */
6794         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6795                 /* Do nothing.  */
6796         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6797                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6798                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6799                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6800                 else
6801                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6802                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6803                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6804         }
6805         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6806                 int fw_len;
6807
6808                 fw_len = tp->fw_len;
6809                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6810                 tw32(BUFMGR_MB_POOL_ADDR,
6811                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6812                 tw32(BUFMGR_MB_POOL_SIZE,
6813                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6814         }
6815
6816         if (tp->dev->mtu <= ETH_DATA_LEN) {
6817                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6818                      tp->bufmgr_config.mbuf_read_dma_low_water);
6819                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6820                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6821                 tw32(BUFMGR_MB_HIGH_WATER,
6822                      tp->bufmgr_config.mbuf_high_water);
6823         } else {
6824                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6825                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6826                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6827                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6828                 tw32(BUFMGR_MB_HIGH_WATER,
6829                      tp->bufmgr_config.mbuf_high_water_jumbo);
6830         }
6831         tw32(BUFMGR_DMA_LOW_WATER,
6832              tp->bufmgr_config.dma_low_water);
6833         tw32(BUFMGR_DMA_HIGH_WATER,
6834              tp->bufmgr_config.dma_high_water);
6835
6836         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6837         for (i = 0; i < 2000; i++) {
6838                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6839                         break;
6840                 udelay(10);
6841         }
6842         if (i >= 2000) {
6843                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6844                        tp->dev->name);
6845                 return -ENODEV;
6846         }
6847
6848         /* Setup replenish threshold. */
6849         val = tp->rx_pending / 8;
6850         if (val == 0)
6851                 val = 1;
6852         else if (val > tp->rx_std_max_post)
6853                 val = tp->rx_std_max_post;
6854         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6855                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6856                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6857
6858                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6859                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6860         }
6861
6862         tw32(RCVBDI_STD_THRESH, val);
6863
6864         /* Initialize TG3_BDINFO's at:
6865          *  RCVDBDI_STD_BD:     standard eth size rx ring
6866          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6867          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6868          *
6869          * like so:
6870          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6871          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6872          *                              ring attribute flags
6873          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6874          *
6875          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6876          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6877          *
6878          * The size of each ring is fixed in the firmware, but the location is
6879          * configurable.
6880          */
6881         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6882              ((u64) tp->rx_std_mapping >> 32));
6883         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6884              ((u64) tp->rx_std_mapping & 0xffffffff));
6885         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6886              NIC_SRAM_RX_BUFFER_DESC);
6887
6888         /* Don't even try to program the JUMBO/MINI buffer descriptor
6889          * configs on 5705.
6890          */
6891         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6892                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6893                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6894         } else {
6895                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6896                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6897
6898                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6899                      BDINFO_FLAGS_DISABLED);
6900
6901                 /* Setup replenish threshold. */
6902                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6903
6904                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6905                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6906                              ((u64) tp->rx_jumbo_mapping >> 32));
6907                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6908                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6909                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6910                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6911                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6912                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6913                 } else {
6914                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6915                              BDINFO_FLAGS_DISABLED);
6916                 }
6917
6918         }
6919
6920         /* There is only one send ring on 5705/5750, no need to explicitly
6921          * disable the others.
6922          */
6923         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6924                 /* Clear out send RCB ring in SRAM. */
6925                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6926                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6927                                       BDINFO_FLAGS_DISABLED);
6928         }
6929
6930         tp->tx_prod = 0;
6931         tp->tx_cons = 0;
6932         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6933         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6934
6935         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6936                        tp->tx_desc_mapping,
6937                        (TG3_TX_RING_SIZE <<
6938                         BDINFO_FLAGS_MAXLEN_SHIFT),
6939                        NIC_SRAM_TX_BUFFER_DESC);
6940
6941         /* There is only one receive return ring on 5705/5750, no need
6942          * to explicitly disable the others.
6943          */
6944         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6945                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6946                      i += TG3_BDINFO_SIZE) {
6947                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6948                                       BDINFO_FLAGS_DISABLED);
6949                 }
6950         }
6951
6952         tp->rx_rcb_ptr = 0;
6953         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6954
6955         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6956                        tp->rx_rcb_mapping,
6957                        (TG3_RX_RCB_RING_SIZE(tp) <<
6958                         BDINFO_FLAGS_MAXLEN_SHIFT),
6959                        0);
6960
6961         tp->rx_std_ptr = tp->rx_pending;
6962         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6963                      tp->rx_std_ptr);
6964
6965         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6966                                                 tp->rx_jumbo_pending : 0;
6967         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6968                      tp->rx_jumbo_ptr);
6969
6970         /* Initialize MAC address and backoff seed. */
6971         __tg3_set_mac_addr(tp, 0);
6972
6973         /* MTU + ethernet header + FCS + optional VLAN tag */
6974         tw32(MAC_RX_MTU_SIZE,
6975              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
6976
6977         /* The slot time is changed by tg3_setup_phy if we
6978          * run at gigabit with half duplex.
6979          */
6980         tw32(MAC_TX_LENGTHS,
6981              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6982              (6 << TX_LENGTHS_IPG_SHIFT) |
6983              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6984
6985         /* Receive rules. */
6986         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6987         tw32(RCVLPC_CONFIG, 0x0181);
6988
6989         /* Calculate RDMAC_MODE setting early, we need it to determine
6990          * the RCVLPC_STATE_ENABLE mask.
6991          */
6992         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6993                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6994                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6995                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6996                       RDMAC_MODE_LNGREAD_ENAB);
6997
6998         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
6999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7001                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7002                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7003                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7004
7005         /* If statement applies to 5705 and 5750 PCI devices only */
7006         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7007              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7008             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7009                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7010                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7011                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7012                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7013                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7014                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7015                 }
7016         }
7017
7018         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7019                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7020
7021         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7022                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7023
7024         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7025             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7026                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7027
7028         /* Receive/send statistics. */
7029         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7030                 val = tr32(RCVLPC_STATS_ENABLE);
7031                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7032                 tw32(RCVLPC_STATS_ENABLE, val);
7033         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7034                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7035                 val = tr32(RCVLPC_STATS_ENABLE);
7036                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7037                 tw32(RCVLPC_STATS_ENABLE, val);
7038         } else {
7039                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7040         }
7041         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7042         tw32(SNDDATAI_STATSENAB, 0xffffff);
7043         tw32(SNDDATAI_STATSCTRL,
7044              (SNDDATAI_SCTRL_ENABLE |
7045               SNDDATAI_SCTRL_FASTUPD));
7046
7047         /* Setup host coalescing engine. */
7048         tw32(HOSTCC_MODE, 0);
7049         for (i = 0; i < 2000; i++) {
7050                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7051                         break;
7052                 udelay(10);
7053         }
7054
7055         __tg3_set_coalesce(tp, &tp->coal);
7056
7057         /* set status block DMA address */
7058         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7059              ((u64) tp->status_mapping >> 32));
7060         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7061              ((u64) tp->status_mapping & 0xffffffff));
7062
7063         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7064                 /* Status/statistics block address.  See tg3_timer,
7065                  * the tg3_periodic_fetch_stats call there, and
7066                  * tg3_get_stats to see how this works for 5705/5750 chips.
7067                  */
7068                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7069                      ((u64) tp->stats_mapping >> 32));
7070                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7071                      ((u64) tp->stats_mapping & 0xffffffff));
7072                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7073                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7074         }
7075
7076         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7077
7078         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7079         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7080         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7081                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7082
7083         /* Clear statistics/status block in chip, and status block in ram. */
7084         for (i = NIC_SRAM_STATS_BLK;
7085              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7086              i += sizeof(u32)) {
7087                 tg3_write_mem(tp, i, 0);
7088                 udelay(40);
7089         }
7090         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7091
7092         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7093                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7094                 /* reset to prevent losing 1st rx packet intermittently */
7095                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7096                 udelay(10);
7097         }
7098
7099         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7100                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7101         else
7102                 tp->mac_mode = 0;
7103         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7104                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7105         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7106             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7107             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7108                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7109         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7110         udelay(40);
7111
7112         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7113          * If TG3_FLG2_IS_NIC is zero, we should read the
7114          * register to preserve the GPIO settings for LOMs. The GPIOs,
7115          * whether used as inputs or outputs, are set by boot code after
7116          * reset.
7117          */
7118         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7119                 u32 gpio_mask;
7120
7121                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7122                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7123                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7124
7125                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7126                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7127                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7128
7129                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7130                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7131
7132                 tp->grc_local_ctrl &= ~gpio_mask;
7133                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7134
7135                 /* GPIO1 must be driven high for eeprom write protect */
7136                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7137                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7138                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7139         }
7140         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7141         udelay(100);
7142
7143         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7144         tp->last_tag = 0;
7145
7146         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7147                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7148                 udelay(40);
7149         }
7150
7151         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7152                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7153                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7154                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7155                WDMAC_MODE_LNGREAD_ENAB);
7156
7157         /* If statement applies to 5705 and 5750 PCI devices only */
7158         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7159              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7160             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7161                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7162                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7163                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7164                         /* nothing */
7165                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7166                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7167                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7168                         val |= WDMAC_MODE_RX_ACCEL;
7169                 }
7170         }
7171
7172         /* Enable host coalescing bug fix */
7173         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7174                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7175
7176         tw32_f(WDMAC_MODE, val);
7177         udelay(40);
7178
7179         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7180                 u16 pcix_cmd;
7181
7182                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7183                                      &pcix_cmd);
7184                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7185                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7186                         pcix_cmd |= PCI_X_CMD_READ_2K;
7187                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7188                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7189                         pcix_cmd |= PCI_X_CMD_READ_2K;
7190                 }
7191                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7192                                       pcix_cmd);
7193         }
7194
7195         tw32_f(RDMAC_MODE, rdmac_mode);
7196         udelay(40);
7197
7198         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7199         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7200                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7201
7202         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7203                 tw32(SNDDATAC_MODE,
7204                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7205         else
7206                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7207
7208         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7209         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7210         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7211         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7212         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7213                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7214         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7215         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7216
7217         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7218                 err = tg3_load_5701_a0_firmware_fix(tp);
7219                 if (err)
7220                         return err;
7221         }
7222
7223         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7224                 err = tg3_load_tso_firmware(tp);
7225                 if (err)
7226                         return err;
7227         }
7228
7229         tp->tx_mode = TX_MODE_ENABLE;
7230         tw32_f(MAC_TX_MODE, tp->tx_mode);
7231         udelay(100);
7232
7233         tp->rx_mode = RX_MODE_ENABLE;
7234         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7235                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7236
7237         tw32_f(MAC_RX_MODE, tp->rx_mode);
7238         udelay(10);
7239
7240         tw32(MAC_LED_CTRL, tp->led_ctrl);
7241
7242         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7243         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7244                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7245                 udelay(10);
7246         }
7247         tw32_f(MAC_RX_MODE, tp->rx_mode);
7248         udelay(10);
7249
7250         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7251                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7252                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7253                         /* Set drive transmission level to 1.2V  */
7254                         /* only if the signal pre-emphasis bit is not set  */
7255                         val = tr32(MAC_SERDES_CFG);
7256                         val &= 0xfffff000;
7257                         val |= 0x880;
7258                         tw32(MAC_SERDES_CFG, val);
7259                 }
7260                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7261                         tw32(MAC_SERDES_CFG, 0x616000);
7262         }
7263
7264         /* Prevent chip from dropping frames when flow control
7265          * is enabled.
7266          */
7267         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7268
7269         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7270             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7271                 /* Use hardware link auto-negotiation */
7272                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7273         }
7274
7275         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7276             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7277                 u32 tmp;
7278
7279                 tmp = tr32(SERDES_RX_CTRL);
7280                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7281                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7282                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7283                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7284         }
7285
7286         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7287                 if (tp->link_config.phy_is_low_power) {
7288                         tp->link_config.phy_is_low_power = 0;
7289                         tp->link_config.speed = tp->link_config.orig_speed;
7290                         tp->link_config.duplex = tp->link_config.orig_duplex;
7291                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7292                 }
7293
7294                 err = tg3_setup_phy(tp, 0);
7295                 if (err)
7296                         return err;
7297
7298                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7299                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7300                         u32 tmp;
7301
7302                         /* Clear CRC stats. */
7303                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7304                                 tg3_writephy(tp, MII_TG3_TEST1,
7305                                              tmp | MII_TG3_TEST1_CRC_EN);
7306                                 tg3_readphy(tp, 0x14, &tmp);
7307                         }
7308                 }
7309         }
7310
7311         __tg3_set_rx_mode(tp->dev);
7312
7313         /* Initialize receive rules. */
7314         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7315         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7316         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7317         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7318
7319         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7320             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7321                 limit = 8;
7322         else
7323                 limit = 16;
7324         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7325                 limit -= 4;
7326         switch (limit) {
7327         case 16:
7328                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7329         case 15:
7330                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7331         case 14:
7332                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7333         case 13:
7334                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7335         case 12:
7336                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7337         case 11:
7338                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7339         case 10:
7340                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7341         case 9:
7342                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7343         case 8:
7344                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7345         case 7:
7346                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7347         case 6:
7348                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7349         case 5:
7350                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7351         case 4:
7352                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7353         case 3:
7354                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7355         case 2:
7356         case 1:
7357
7358         default:
7359                 break;
7360         }
7361
7362         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7363                 /* Write our heartbeat update interval to APE. */
7364                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7365                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7366
7367         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7368
7369         return 0;
7370 }
7371
7372 /* Called at device open time to get the chip ready for
7373  * packet processing.  Invoked with tp->lock held.
7374  */
7375 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7376 {
7377         tg3_switch_clocks(tp);
7378
7379         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7380
7381         return tg3_reset_hw(tp, reset_phy);
7382 }
7383
7384 #define TG3_STAT_ADD32(PSTAT, REG) \
7385 do {    u32 __val = tr32(REG); \
7386         (PSTAT)->low += __val; \
7387         if ((PSTAT)->low < __val) \
7388                 (PSTAT)->high += 1; \
7389 } while (0)
7390
7391 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7392 {
7393         struct tg3_hw_stats *sp = tp->hw_stats;
7394
7395         if (!netif_carrier_ok(tp->dev))
7396                 return;
7397
7398         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7399         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7400         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7401         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7402         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7403         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7404         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7405         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7406         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7407         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7408         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7409         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7410         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7411
7412         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7413         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7414         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7415         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7416         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7417         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7418         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7419         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7420         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7421         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7422         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7423         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7424         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7425         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7426
7427         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7428         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7429         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7430 }
7431
7432 static void tg3_timer(unsigned long __opaque)
7433 {
7434         struct tg3 *tp = (struct tg3 *) __opaque;
7435
7436         if (tp->irq_sync)
7437                 goto restart_timer;
7438
7439         spin_lock(&tp->lock);
7440
7441         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7442                 /* All of this garbage is because when using non-tagged
7443                  * IRQ status the mailbox/status_block protocol the chip
7444                  * uses with the cpu is race prone.
7445                  */
7446                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7447                         tw32(GRC_LOCAL_CTRL,
7448                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7449                 } else {
7450                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7451                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7452                 }
7453
7454                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7455                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7456                         spin_unlock(&tp->lock);
7457                         schedule_work(&tp->reset_task);
7458                         return;
7459                 }
7460         }
7461
7462         /* This part only runs once per second. */
7463         if (!--tp->timer_counter) {
7464                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7465                         tg3_periodic_fetch_stats(tp);
7466
7467                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7468                         u32 mac_stat;
7469                         int phy_event;
7470
7471                         mac_stat = tr32(MAC_STATUS);
7472
7473                         phy_event = 0;
7474                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7475                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7476                                         phy_event = 1;
7477                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7478                                 phy_event = 1;
7479
7480                         if (phy_event)
7481                                 tg3_setup_phy(tp, 0);
7482                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7483                         u32 mac_stat = tr32(MAC_STATUS);
7484                         int need_setup = 0;
7485
7486                         if (netif_carrier_ok(tp->dev) &&
7487                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7488                                 need_setup = 1;
7489                         }
7490                         if (! netif_carrier_ok(tp->dev) &&
7491                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7492                                          MAC_STATUS_SIGNAL_DET))) {
7493                                 need_setup = 1;
7494                         }
7495                         if (need_setup) {
7496                                 if (!tp->serdes_counter) {
7497                                         tw32_f(MAC_MODE,
7498                                              (tp->mac_mode &
7499                                               ~MAC_MODE_PORT_MODE_MASK));
7500                                         udelay(40);
7501                                         tw32_f(MAC_MODE, tp->mac_mode);
7502                                         udelay(40);
7503                                 }
7504                                 tg3_setup_phy(tp, 0);
7505                         }
7506                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7507                         tg3_serdes_parallel_detect(tp);
7508
7509                 tp->timer_counter = tp->timer_multiplier;
7510         }
7511
7512         /* Heartbeat is only sent once every 2 seconds.
7513          *
7514          * The heartbeat is to tell the ASF firmware that the host
7515          * driver is still alive.  In the event that the OS crashes,
7516          * ASF needs to reset the hardware to free up the FIFO space
7517          * that may be filled with rx packets destined for the host.
7518          * If the FIFO is full, ASF will no longer function properly.
7519          *
7520          * Unintended resets have been reported on real time kernels
7521          * where the timer doesn't run on time.  Netpoll will also have
7522          * same problem.
7523          *
7524          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7525          * to check the ring condition when the heartbeat is expiring
7526          * before doing the reset.  This will prevent most unintended
7527          * resets.
7528          */
7529         if (!--tp->asf_counter) {
7530                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7531                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7532                         tg3_wait_for_event_ack(tp);
7533
7534                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7535                                       FWCMD_NICDRV_ALIVE3);
7536                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7537                         /* 5 seconds timeout */
7538                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7539
7540                         tg3_generate_fw_event(tp);
7541                 }
7542                 tp->asf_counter = tp->asf_multiplier;
7543         }
7544
7545         spin_unlock(&tp->lock);
7546
7547 restart_timer:
7548         tp->timer.expires = jiffies + tp->timer_offset;
7549         add_timer(&tp->timer);
7550 }
7551
7552 static int tg3_request_irq(struct tg3 *tp)
7553 {
7554         irq_handler_t fn;
7555         unsigned long flags;
7556         struct net_device *dev = tp->dev;
7557
7558         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7559                 fn = tg3_msi;
7560                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7561                         fn = tg3_msi_1shot;
7562                 flags = IRQF_SAMPLE_RANDOM;
7563         } else {
7564                 fn = tg3_interrupt;
7565                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7566                         fn = tg3_interrupt_tagged;
7567                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7568         }
7569         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7570 }
7571
7572 static int tg3_test_interrupt(struct tg3 *tp)
7573 {
7574         struct net_device *dev = tp->dev;
7575         int err, i, intr_ok = 0;
7576
7577         if (!netif_running(dev))
7578                 return -ENODEV;
7579
7580         tg3_disable_ints(tp);
7581
7582         free_irq(tp->pdev->irq, dev);
7583
7584         err = request_irq(tp->pdev->irq, tg3_test_isr,
7585                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7586         if (err)
7587                 return err;
7588
7589         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7590         tg3_enable_ints(tp);
7591
7592         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7593                HOSTCC_MODE_NOW);
7594
7595         for (i = 0; i < 5; i++) {
7596                 u32 int_mbox, misc_host_ctrl;
7597
7598                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7599                                         TG3_64BIT_REG_LOW);
7600                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7601
7602                 if ((int_mbox != 0) ||
7603                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7604                         intr_ok = 1;
7605                         break;
7606                 }
7607
7608                 msleep(10);
7609         }
7610
7611         tg3_disable_ints(tp);
7612
7613         free_irq(tp->pdev->irq, dev);
7614
7615         err = tg3_request_irq(tp);
7616
7617         if (err)
7618                 return err;
7619
7620         if (intr_ok)
7621                 return 0;
7622
7623         return -EIO;
7624 }
7625
7626 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7627  * successfully restored
7628  */
7629 static int tg3_test_msi(struct tg3 *tp)
7630 {
7631         struct net_device *dev = tp->dev;
7632         int err;
7633         u16 pci_cmd;
7634
7635         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7636                 return 0;
7637
7638         /* Turn off SERR reporting in case MSI terminates with Master
7639          * Abort.
7640          */
7641         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7642         pci_write_config_word(tp->pdev, PCI_COMMAND,
7643                               pci_cmd & ~PCI_COMMAND_SERR);
7644
7645         err = tg3_test_interrupt(tp);
7646
7647         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7648
7649         if (!err)
7650                 return 0;
7651
7652         /* other failures */
7653         if (err != -EIO)
7654                 return err;
7655
7656         /* MSI test failed, go back to INTx mode */
7657         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7658                "switching to INTx mode. Please report this failure to "
7659                "the PCI maintainer and include system chipset information.\n",
7660                        tp->dev->name);
7661
7662         free_irq(tp->pdev->irq, dev);
7663         pci_disable_msi(tp->pdev);
7664
7665         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7666
7667         err = tg3_request_irq(tp);
7668         if (err)
7669                 return err;
7670
7671         /* Need to reset the chip because the MSI cycle may have terminated
7672          * with Master Abort.
7673          */
7674         tg3_full_lock(tp, 1);
7675
7676         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7677         err = tg3_init_hw(tp, 1);
7678
7679         tg3_full_unlock(tp);
7680
7681         if (err)
7682                 free_irq(tp->pdev->irq, dev);
7683
7684         return err;
7685 }
7686
7687 static int tg3_request_firmware(struct tg3 *tp)
7688 {
7689         const __be32 *fw_data;
7690
7691         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7692                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7693                        tp->dev->name, tp->fw_needed);
7694                 return -ENOENT;
7695         }
7696
7697         fw_data = (void *)tp->fw->data;
7698
7699         /* Firmware blob starts with version numbers, followed by
7700          * start address and _full_ length including BSS sections
7701          * (which must be longer than the actual data, of course
7702          */
7703
7704         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
7705         if (tp->fw_len < (tp->fw->size - 12)) {
7706                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7707                        tp->dev->name, tp->fw_len, tp->fw_needed);
7708                 release_firmware(tp->fw);
7709                 tp->fw = NULL;
7710                 return -EINVAL;
7711         }
7712
7713         /* We no longer need firmware; we have it. */
7714         tp->fw_needed = NULL;
7715         return 0;
7716 }
7717
7718 static int tg3_open(struct net_device *dev)
7719 {
7720         struct tg3 *tp = netdev_priv(dev);
7721         int err;
7722
7723         if (tp->fw_needed) {
7724                 err = tg3_request_firmware(tp);
7725                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7726                         if (err)
7727                                 return err;
7728                 } else if (err) {
7729                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
7730                                tp->dev->name);
7731                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7732                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7733                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
7734                                tp->dev->name);
7735                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7736                 }
7737         }
7738
7739         netif_carrier_off(tp->dev);
7740
7741         err = tg3_set_power_state(tp, PCI_D0);
7742         if (err)
7743                 return err;
7744
7745         tg3_full_lock(tp, 0);
7746
7747         tg3_disable_ints(tp);
7748         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7749
7750         tg3_full_unlock(tp);
7751
7752         /* The placement of this call is tied
7753          * to the setup and use of Host TX descriptors.
7754          */
7755         err = tg3_alloc_consistent(tp);
7756         if (err)
7757                 return err;
7758
7759         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7760                 /* All MSI supporting chips should support tagged
7761                  * status.  Assert that this is the case.
7762                  */
7763                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7764                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7765                                "Not using MSI.\n", tp->dev->name);
7766                 } else if (pci_enable_msi(tp->pdev) == 0) {
7767                         u32 msi_mode;
7768
7769                         msi_mode = tr32(MSGINT_MODE);
7770                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7771                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7772                 }
7773         }
7774         err = tg3_request_irq(tp);
7775
7776         if (err) {
7777                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7778                         pci_disable_msi(tp->pdev);
7779                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7780                 }
7781                 tg3_free_consistent(tp);
7782                 return err;
7783         }
7784
7785         napi_enable(&tp->napi);
7786
7787         tg3_full_lock(tp, 0);
7788
7789         err = tg3_init_hw(tp, 1);
7790         if (err) {
7791                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7792                 tg3_free_rings(tp);
7793         } else {
7794                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7795                         tp->timer_offset = HZ;
7796                 else
7797                         tp->timer_offset = HZ / 10;
7798
7799                 BUG_ON(tp->timer_offset > HZ);
7800                 tp->timer_counter = tp->timer_multiplier =
7801                         (HZ / tp->timer_offset);
7802                 tp->asf_counter = tp->asf_multiplier =
7803                         ((HZ / tp->timer_offset) * 2);
7804
7805                 init_timer(&tp->timer);
7806                 tp->timer.expires = jiffies + tp->timer_offset;
7807                 tp->timer.data = (unsigned long) tp;
7808                 tp->timer.function = tg3_timer;
7809         }
7810
7811         tg3_full_unlock(tp);
7812
7813         if (err) {
7814                 napi_disable(&tp->napi);
7815                 free_irq(tp->pdev->irq, dev);
7816                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7817                         pci_disable_msi(tp->pdev);
7818                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7819                 }
7820                 tg3_free_consistent(tp);
7821                 return err;
7822         }
7823
7824         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7825                 err = tg3_test_msi(tp);
7826
7827                 if (err) {
7828                         tg3_full_lock(tp, 0);
7829
7830                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7831                                 pci_disable_msi(tp->pdev);
7832                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7833                         }
7834                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7835                         tg3_free_rings(tp);
7836                         tg3_free_consistent(tp);
7837
7838                         tg3_full_unlock(tp);
7839
7840                         napi_disable(&tp->napi);
7841
7842                         return err;
7843                 }
7844
7845                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7846                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7847                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7848
7849                                 tw32(PCIE_TRANSACTION_CFG,
7850                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7851                         }
7852                 }
7853         }
7854
7855         tg3_phy_start(tp);
7856
7857         tg3_full_lock(tp, 0);
7858
7859         add_timer(&tp->timer);
7860         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7861         tg3_enable_ints(tp);
7862
7863         tg3_full_unlock(tp);
7864
7865         netif_start_queue(dev);
7866
7867         return 0;
7868 }
7869
7870 #if 0
7871 /*static*/ void tg3_dump_state(struct tg3 *tp)
7872 {
7873         u32 val32, val32_2, val32_3, val32_4, val32_5;
7874         u16 val16;
7875         int i;
7876
7877         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7878         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7879         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7880                val16, val32);
7881
7882         /* MAC block */
7883         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7884                tr32(MAC_MODE), tr32(MAC_STATUS));
7885         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7886                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7887         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7888                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7889         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7890                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7891
7892         /* Send data initiator control block */
7893         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7894                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7895         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7896                tr32(SNDDATAI_STATSCTRL));
7897
7898         /* Send data completion control block */
7899         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7900
7901         /* Send BD ring selector block */
7902         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7903                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7904
7905         /* Send BD initiator control block */
7906         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7907                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7908
7909         /* Send BD completion control block */
7910         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7911
7912         /* Receive list placement control block */
7913         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7914                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7915         printk("       RCVLPC_STATSCTRL[%08x]\n",
7916                tr32(RCVLPC_STATSCTRL));
7917
7918         /* Receive data and receive BD initiator control block */
7919         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7920                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7921
7922         /* Receive data completion control block */
7923         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7924                tr32(RCVDCC_MODE));
7925
7926         /* Receive BD initiator control block */
7927         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7928                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7929
7930         /* Receive BD completion control block */
7931         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7932                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7933
7934         /* Receive list selector control block */
7935         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7936                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7937
7938         /* Mbuf cluster free block */
7939         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7940                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7941
7942         /* Host coalescing control block */
7943         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7944                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7945         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7946                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7947                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7948         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7949                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7950                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7951         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7952                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7953         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7954                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7955
7956         /* Memory arbiter control block */
7957         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7958                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7959
7960         /* Buffer manager control block */
7961         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7962                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7963         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7964                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7965         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7966                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7967                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7968                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7969
7970         /* Read DMA control block */
7971         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7972                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7973
7974         /* Write DMA control block */
7975         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7976                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7977
7978         /* DMA completion block */
7979         printk("DEBUG: DMAC_MODE[%08x]\n",
7980                tr32(DMAC_MODE));
7981
7982         /* GRC block */
7983         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7984                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7985         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7986                tr32(GRC_LOCAL_CTRL));
7987
7988         /* TG3_BDINFOs */
7989         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7990                tr32(RCVDBDI_JUMBO_BD + 0x0),
7991                tr32(RCVDBDI_JUMBO_BD + 0x4),
7992                tr32(RCVDBDI_JUMBO_BD + 0x8),
7993                tr32(RCVDBDI_JUMBO_BD + 0xc));
7994         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7995                tr32(RCVDBDI_STD_BD + 0x0),
7996                tr32(RCVDBDI_STD_BD + 0x4),
7997                tr32(RCVDBDI_STD_BD + 0x8),
7998                tr32(RCVDBDI_STD_BD + 0xc));
7999         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8000                tr32(RCVDBDI_MINI_BD + 0x0),
8001                tr32(RCVDBDI_MINI_BD + 0x4),
8002                tr32(RCVDBDI_MINI_BD + 0x8),
8003                tr32(RCVDBDI_MINI_BD + 0xc));
8004
8005         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8006         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8007         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8008         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8009         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8010                val32, val32_2, val32_3, val32_4);
8011
8012         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8013         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8014         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8015         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8016         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8017                val32, val32_2, val32_3, val32_4);
8018
8019         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8020         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8021         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8022         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8023         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8024         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8025                val32, val32_2, val32_3, val32_4, val32_5);
8026
8027         /* SW status block */
8028         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8029                tp->hw_status->status,
8030                tp->hw_status->status_tag,
8031                tp->hw_status->rx_jumbo_consumer,
8032                tp->hw_status->rx_consumer,
8033                tp->hw_status->rx_mini_consumer,
8034                tp->hw_status->idx[0].rx_producer,
8035                tp->hw_status->idx[0].tx_consumer);
8036
8037         /* SW statistics block */
8038         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8039                ((u32 *)tp->hw_stats)[0],
8040                ((u32 *)tp->hw_stats)[1],
8041                ((u32 *)tp->hw_stats)[2],
8042                ((u32 *)tp->hw_stats)[3]);
8043
8044         /* Mailboxes */
8045         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8046                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8047                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8048                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8049                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8050
8051         /* NIC side send descriptors. */
8052         for (i = 0; i < 6; i++) {
8053                 unsigned long txd;
8054
8055                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8056                         + (i * sizeof(struct tg3_tx_buffer_desc));
8057                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8058                        i,
8059                        readl(txd + 0x0), readl(txd + 0x4),
8060                        readl(txd + 0x8), readl(txd + 0xc));
8061         }
8062
8063         /* NIC side RX descriptors. */
8064         for (i = 0; i < 6; i++) {
8065                 unsigned long rxd;
8066
8067                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8068                         + (i * sizeof(struct tg3_rx_buffer_desc));
8069                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8070                        i,
8071                        readl(rxd + 0x0), readl(rxd + 0x4),
8072                        readl(rxd + 0x8), readl(rxd + 0xc));
8073                 rxd += (4 * sizeof(u32));
8074                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8075                        i,
8076                        readl(rxd + 0x0), readl(rxd + 0x4),
8077                        readl(rxd + 0x8), readl(rxd + 0xc));
8078         }
8079
8080         for (i = 0; i < 6; i++) {
8081                 unsigned long rxd;
8082
8083                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8084                         + (i * sizeof(struct tg3_rx_buffer_desc));
8085                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8086                        i,
8087                        readl(rxd + 0x0), readl(rxd + 0x4),
8088                        readl(rxd + 0x8), readl(rxd + 0xc));
8089                 rxd += (4 * sizeof(u32));
8090                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8091                        i,
8092                        readl(rxd + 0x0), readl(rxd + 0x4),
8093                        readl(rxd + 0x8), readl(rxd + 0xc));
8094         }
8095 }
8096 #endif
8097
8098 static struct net_device_stats *tg3_get_stats(struct net_device *);
8099 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8100
8101 static int tg3_close(struct net_device *dev)
8102 {
8103         struct tg3 *tp = netdev_priv(dev);
8104
8105         napi_disable(&tp->napi);
8106         cancel_work_sync(&tp->reset_task);
8107
8108         netif_stop_queue(dev);
8109
8110         del_timer_sync(&tp->timer);
8111
8112         tg3_full_lock(tp, 1);
8113 #if 0
8114         tg3_dump_state(tp);
8115 #endif
8116
8117         tg3_disable_ints(tp);
8118
8119         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8120         tg3_free_rings(tp);
8121         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8122
8123         tg3_full_unlock(tp);
8124
8125         free_irq(tp->pdev->irq, dev);
8126         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8127                 pci_disable_msi(tp->pdev);
8128                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8129         }
8130
8131         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8132                sizeof(tp->net_stats_prev));
8133         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8134                sizeof(tp->estats_prev));
8135
8136         tg3_free_consistent(tp);
8137
8138         tg3_set_power_state(tp, PCI_D3hot);
8139
8140         netif_carrier_off(tp->dev);
8141
8142         return 0;
8143 }
8144
8145 static inline unsigned long get_stat64(tg3_stat64_t *val)
8146 {
8147         unsigned long ret;
8148
8149 #if (BITS_PER_LONG == 32)
8150         ret = val->low;
8151 #else
8152         ret = ((u64)val->high << 32) | ((u64)val->low);
8153 #endif
8154         return ret;
8155 }
8156
8157 static inline u64 get_estat64(tg3_stat64_t *val)
8158 {
8159        return ((u64)val->high << 32) | ((u64)val->low);
8160 }
8161
8162 static unsigned long calc_crc_errors(struct tg3 *tp)
8163 {
8164         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8165
8166         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8167             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8168              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8169                 u32 val;
8170
8171                 spin_lock_bh(&tp->lock);
8172                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8173                         tg3_writephy(tp, MII_TG3_TEST1,
8174                                      val | MII_TG3_TEST1_CRC_EN);
8175                         tg3_readphy(tp, 0x14, &val);
8176                 } else
8177                         val = 0;
8178                 spin_unlock_bh(&tp->lock);
8179
8180                 tp->phy_crc_errors += val;
8181
8182                 return tp->phy_crc_errors;
8183         }
8184
8185         return get_stat64(&hw_stats->rx_fcs_errors);
8186 }
8187
8188 #define ESTAT_ADD(member) \
8189         estats->member =        old_estats->member + \
8190                                 get_estat64(&hw_stats->member)
8191
8192 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8193 {
8194         struct tg3_ethtool_stats *estats = &tp->estats;
8195         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8196         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8197
8198         if (!hw_stats)
8199                 return old_estats;
8200
8201         ESTAT_ADD(rx_octets);
8202         ESTAT_ADD(rx_fragments);
8203         ESTAT_ADD(rx_ucast_packets);
8204         ESTAT_ADD(rx_mcast_packets);
8205         ESTAT_ADD(rx_bcast_packets);
8206         ESTAT_ADD(rx_fcs_errors);
8207         ESTAT_ADD(rx_align_errors);
8208         ESTAT_ADD(rx_xon_pause_rcvd);
8209         ESTAT_ADD(rx_xoff_pause_rcvd);
8210         ESTAT_ADD(rx_mac_ctrl_rcvd);
8211         ESTAT_ADD(rx_xoff_entered);
8212         ESTAT_ADD(rx_frame_too_long_errors);
8213         ESTAT_ADD(rx_jabbers);
8214         ESTAT_ADD(rx_undersize_packets);
8215         ESTAT_ADD(rx_in_length_errors);
8216         ESTAT_ADD(rx_out_length_errors);
8217         ESTAT_ADD(rx_64_or_less_octet_packets);
8218         ESTAT_ADD(rx_65_to_127_octet_packets);
8219         ESTAT_ADD(rx_128_to_255_octet_packets);
8220         ESTAT_ADD(rx_256_to_511_octet_packets);
8221         ESTAT_ADD(rx_512_to_1023_octet_packets);
8222         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8223         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8224         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8225         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8226         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8227
8228         ESTAT_ADD(tx_octets);
8229         ESTAT_ADD(tx_collisions);
8230         ESTAT_ADD(tx_xon_sent);
8231         ESTAT_ADD(tx_xoff_sent);
8232         ESTAT_ADD(tx_flow_control);
8233         ESTAT_ADD(tx_mac_errors);
8234         ESTAT_ADD(tx_single_collisions);
8235         ESTAT_ADD(tx_mult_collisions);
8236         ESTAT_ADD(tx_deferred);
8237         ESTAT_ADD(tx_excessive_collisions);
8238         ESTAT_ADD(tx_late_collisions);
8239         ESTAT_ADD(tx_collide_2times);
8240         ESTAT_ADD(tx_collide_3times);
8241         ESTAT_ADD(tx_collide_4times);
8242         ESTAT_ADD(tx_collide_5times);
8243         ESTAT_ADD(tx_collide_6times);
8244         ESTAT_ADD(tx_collide_7times);
8245         ESTAT_ADD(tx_collide_8times);
8246         ESTAT_ADD(tx_collide_9times);
8247         ESTAT_ADD(tx_collide_10times);
8248         ESTAT_ADD(tx_collide_11times);
8249         ESTAT_ADD(tx_collide_12times);
8250         ESTAT_ADD(tx_collide_13times);
8251         ESTAT_ADD(tx_collide_14times);
8252         ESTAT_ADD(tx_collide_15times);
8253         ESTAT_ADD(tx_ucast_packets);
8254         ESTAT_ADD(tx_mcast_packets);
8255         ESTAT_ADD(tx_bcast_packets);
8256         ESTAT_ADD(tx_carrier_sense_errors);
8257         ESTAT_ADD(tx_discards);
8258         ESTAT_ADD(tx_errors);
8259
8260         ESTAT_ADD(dma_writeq_full);
8261         ESTAT_ADD(dma_write_prioq_full);
8262         ESTAT_ADD(rxbds_empty);
8263         ESTAT_ADD(rx_discards);
8264         ESTAT_ADD(rx_errors);
8265         ESTAT_ADD(rx_threshold_hit);
8266
8267         ESTAT_ADD(dma_readq_full);
8268         ESTAT_ADD(dma_read_prioq_full);
8269         ESTAT_ADD(tx_comp_queue_full);
8270
8271         ESTAT_ADD(ring_set_send_prod_index);
8272         ESTAT_ADD(ring_status_update);
8273         ESTAT_ADD(nic_irqs);
8274         ESTAT_ADD(nic_avoided_irqs);
8275         ESTAT_ADD(nic_tx_threshold_hit);
8276
8277         return estats;
8278 }
8279
8280 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8281 {
8282         struct tg3 *tp = netdev_priv(dev);
8283         struct net_device_stats *stats = &tp->net_stats;
8284         struct net_device_stats *old_stats = &tp->net_stats_prev;
8285         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8286
8287         if (!hw_stats)
8288                 return old_stats;
8289
8290         stats->rx_packets = old_stats->rx_packets +
8291                 get_stat64(&hw_stats->rx_ucast_packets) +
8292                 get_stat64(&hw_stats->rx_mcast_packets) +
8293                 get_stat64(&hw_stats->rx_bcast_packets);
8294
8295         stats->tx_packets = old_stats->tx_packets +
8296                 get_stat64(&hw_stats->tx_ucast_packets) +
8297                 get_stat64(&hw_stats->tx_mcast_packets) +
8298                 get_stat64(&hw_stats->tx_bcast_packets);
8299
8300         stats->rx_bytes = old_stats->rx_bytes +
8301                 get_stat64(&hw_stats->rx_octets);
8302         stats->tx_bytes = old_stats->tx_bytes +
8303                 get_stat64(&hw_stats->tx_octets);
8304
8305         stats->rx_errors = old_stats->rx_errors +
8306                 get_stat64(&hw_stats->rx_errors);
8307         stats->tx_errors = old_stats->tx_errors +
8308                 get_stat64(&hw_stats->tx_errors) +
8309                 get_stat64(&hw_stats->tx_mac_errors) +
8310                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8311                 get_stat64(&hw_stats->tx_discards);
8312
8313         stats->multicast = old_stats->multicast +
8314                 get_stat64(&hw_stats->rx_mcast_packets);
8315         stats->collisions = old_stats->collisions +
8316                 get_stat64(&hw_stats->tx_collisions);
8317
8318         stats->rx_length_errors = old_stats->rx_length_errors +
8319                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8320                 get_stat64(&hw_stats->rx_undersize_packets);
8321
8322         stats->rx_over_errors = old_stats->rx_over_errors +
8323                 get_stat64(&hw_stats->rxbds_empty);
8324         stats->rx_frame_errors = old_stats->rx_frame_errors +
8325                 get_stat64(&hw_stats->rx_align_errors);
8326         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8327                 get_stat64(&hw_stats->tx_discards);
8328         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8329                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8330
8331         stats->rx_crc_errors = old_stats->rx_crc_errors +
8332                 calc_crc_errors(tp);
8333
8334         stats->rx_missed_errors = old_stats->rx_missed_errors +
8335                 get_stat64(&hw_stats->rx_discards);
8336
8337         return stats;
8338 }
8339
8340 static inline u32 calc_crc(unsigned char *buf, int len)
8341 {
8342         u32 reg;
8343         u32 tmp;
8344         int j, k;
8345
8346         reg = 0xffffffff;
8347
8348         for (j = 0; j < len; j++) {
8349                 reg ^= buf[j];
8350
8351                 for (k = 0; k < 8; k++) {
8352                         tmp = reg & 0x01;
8353
8354                         reg >>= 1;
8355
8356                         if (tmp) {
8357                                 reg ^= 0xedb88320;
8358                         }
8359                 }
8360         }
8361
8362         return ~reg;
8363 }
8364
8365 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8366 {
8367         /* accept or reject all multicast frames */
8368         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8369         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8370         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8371         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8372 }
8373
8374 static void __tg3_set_rx_mode(struct net_device *dev)
8375 {
8376         struct tg3 *tp = netdev_priv(dev);
8377         u32 rx_mode;
8378
8379         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8380                                   RX_MODE_KEEP_VLAN_TAG);
8381
8382         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8383          * flag clear.
8384          */
8385 #if TG3_VLAN_TAG_USED
8386         if (!tp->vlgrp &&
8387             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8388                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8389 #else
8390         /* By definition, VLAN is disabled always in this
8391          * case.
8392          */
8393         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8394                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8395 #endif
8396
8397         if (dev->flags & IFF_PROMISC) {
8398                 /* Promiscuous mode. */
8399                 rx_mode |= RX_MODE_PROMISC;
8400         } else if (dev->flags & IFF_ALLMULTI) {
8401                 /* Accept all multicast. */
8402                 tg3_set_multi (tp, 1);
8403         } else if (dev->mc_count < 1) {
8404                 /* Reject all multicast. */
8405                 tg3_set_multi (tp, 0);
8406         } else {
8407                 /* Accept one or more multicast(s). */
8408                 struct dev_mc_list *mclist;
8409                 unsigned int i;
8410                 u32 mc_filter[4] = { 0, };
8411                 u32 regidx;
8412                 u32 bit;
8413                 u32 crc;
8414
8415                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8416                      i++, mclist = mclist->next) {
8417
8418                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8419                         bit = ~crc & 0x7f;
8420                         regidx = (bit & 0x60) >> 5;
8421                         bit &= 0x1f;
8422                         mc_filter[regidx] |= (1 << bit);
8423                 }
8424
8425                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8426                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8427                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8428                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8429         }
8430
8431         if (rx_mode != tp->rx_mode) {
8432                 tp->rx_mode = rx_mode;
8433                 tw32_f(MAC_RX_MODE, rx_mode);
8434                 udelay(10);
8435         }
8436 }
8437
8438 static void tg3_set_rx_mode(struct net_device *dev)
8439 {
8440         struct tg3 *tp = netdev_priv(dev);
8441
8442         if (!netif_running(dev))
8443                 return;
8444
8445         tg3_full_lock(tp, 0);
8446         __tg3_set_rx_mode(dev);
8447         tg3_full_unlock(tp);
8448 }
8449
8450 #define TG3_REGDUMP_LEN         (32 * 1024)
8451
8452 static int tg3_get_regs_len(struct net_device *dev)
8453 {
8454         return TG3_REGDUMP_LEN;
8455 }
8456
8457 static void tg3_get_regs(struct net_device *dev,
8458                 struct ethtool_regs *regs, void *_p)
8459 {
8460         u32 *p = _p;
8461         struct tg3 *tp = netdev_priv(dev);
8462         u8 *orig_p = _p;
8463         int i;
8464
8465         regs->version = 0;
8466
8467         memset(p, 0, TG3_REGDUMP_LEN);
8468
8469         if (tp->link_config.phy_is_low_power)
8470                 return;
8471
8472         tg3_full_lock(tp, 0);
8473
8474 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8475 #define GET_REG32_LOOP(base,len)                \
8476 do {    p = (u32 *)(orig_p + (base));           \
8477         for (i = 0; i < len; i += 4)            \
8478                 __GET_REG32((base) + i);        \
8479 } while (0)
8480 #define GET_REG32_1(reg)                        \
8481 do {    p = (u32 *)(orig_p + (reg));            \
8482         __GET_REG32((reg));                     \
8483 } while (0)
8484
8485         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8486         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8487         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8488         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8489         GET_REG32_1(SNDDATAC_MODE);
8490         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8491         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8492         GET_REG32_1(SNDBDC_MODE);
8493         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8494         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8495         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8496         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8497         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8498         GET_REG32_1(RCVDCC_MODE);
8499         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8500         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8501         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8502         GET_REG32_1(MBFREE_MODE);
8503         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8504         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8505         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8506         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8507         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8508         GET_REG32_1(RX_CPU_MODE);
8509         GET_REG32_1(RX_CPU_STATE);
8510         GET_REG32_1(RX_CPU_PGMCTR);
8511         GET_REG32_1(RX_CPU_HWBKPT);
8512         GET_REG32_1(TX_CPU_MODE);
8513         GET_REG32_1(TX_CPU_STATE);
8514         GET_REG32_1(TX_CPU_PGMCTR);
8515         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8516         GET_REG32_LOOP(FTQ_RESET, 0x120);
8517         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8518         GET_REG32_1(DMAC_MODE);
8519         GET_REG32_LOOP(GRC_MODE, 0x4c);
8520         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8521                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8522
8523 #undef __GET_REG32
8524 #undef GET_REG32_LOOP
8525 #undef GET_REG32_1
8526
8527         tg3_full_unlock(tp);
8528 }
8529
8530 static int tg3_get_eeprom_len(struct net_device *dev)
8531 {
8532         struct tg3 *tp = netdev_priv(dev);
8533
8534         return tp->nvram_size;
8535 }
8536
8537 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8538 {
8539         struct tg3 *tp = netdev_priv(dev);
8540         int ret;
8541         u8  *pd;
8542         u32 i, offset, len, b_offset, b_count;
8543         __be32 val;
8544
8545         if (tp->link_config.phy_is_low_power)
8546                 return -EAGAIN;
8547
8548         offset = eeprom->offset;
8549         len = eeprom->len;
8550         eeprom->len = 0;
8551
8552         eeprom->magic = TG3_EEPROM_MAGIC;
8553
8554         if (offset & 3) {
8555                 /* adjustments to start on required 4 byte boundary */
8556                 b_offset = offset & 3;
8557                 b_count = 4 - b_offset;
8558                 if (b_count > len) {
8559                         /* i.e. offset=1 len=2 */
8560                         b_count = len;
8561                 }
8562                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8563                 if (ret)
8564                         return ret;
8565                 memcpy(data, ((char*)&val) + b_offset, b_count);
8566                 len -= b_count;
8567                 offset += b_count;
8568                 eeprom->len += b_count;
8569         }
8570
8571         /* read bytes upto the last 4 byte boundary */
8572         pd = &data[eeprom->len];
8573         for (i = 0; i < (len - (len & 3)); i += 4) {
8574                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8575                 if (ret) {
8576                         eeprom->len += i;
8577                         return ret;
8578                 }
8579                 memcpy(pd + i, &val, 4);
8580         }
8581         eeprom->len += i;
8582
8583         if (len & 3) {
8584                 /* read last bytes not ending on 4 byte boundary */
8585                 pd = &data[eeprom->len];
8586                 b_count = len & 3;
8587                 b_offset = offset + len - b_count;
8588                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8589                 if (ret)
8590                         return ret;
8591                 memcpy(pd, &val, b_count);
8592                 eeprom->len += b_count;
8593         }
8594         return 0;
8595 }
8596
8597 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8598
8599 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8600 {
8601         struct tg3 *tp = netdev_priv(dev);
8602         int ret;
8603         u32 offset, len, b_offset, odd_len;
8604         u8 *buf;
8605         __be32 start, end;
8606
8607         if (tp->link_config.phy_is_low_power)
8608                 return -EAGAIN;
8609
8610         if (eeprom->magic != TG3_EEPROM_MAGIC)
8611                 return -EINVAL;
8612
8613         offset = eeprom->offset;
8614         len = eeprom->len;
8615
8616         if ((b_offset = (offset & 3))) {
8617                 /* adjustments to start on required 4 byte boundary */
8618                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8619                 if (ret)
8620                         return ret;
8621                 len += b_offset;
8622                 offset &= ~3;
8623                 if (len < 4)
8624                         len = 4;
8625         }
8626
8627         odd_len = 0;
8628         if (len & 3) {
8629                 /* adjustments to end on required 4 byte boundary */
8630                 odd_len = 1;
8631                 len = (len + 3) & ~3;
8632                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8633                 if (ret)
8634                         return ret;
8635         }
8636
8637         buf = data;
8638         if (b_offset || odd_len) {
8639                 buf = kmalloc(len, GFP_KERNEL);
8640                 if (!buf)
8641                         return -ENOMEM;
8642                 if (b_offset)
8643                         memcpy(buf, &start, 4);
8644                 if (odd_len)
8645                         memcpy(buf+len-4, &end, 4);
8646                 memcpy(buf + b_offset, data, eeprom->len);
8647         }
8648
8649         ret = tg3_nvram_write_block(tp, offset, len, buf);
8650
8651         if (buf != data)
8652                 kfree(buf);
8653
8654         return ret;
8655 }
8656
8657 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8658 {
8659         struct tg3 *tp = netdev_priv(dev);
8660
8661         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8662                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8663                         return -EAGAIN;
8664                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8665         }
8666
8667         cmd->supported = (SUPPORTED_Autoneg);
8668
8669         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8670                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8671                                    SUPPORTED_1000baseT_Full);
8672
8673         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8674                 cmd->supported |= (SUPPORTED_100baseT_Half |
8675                                   SUPPORTED_100baseT_Full |
8676                                   SUPPORTED_10baseT_Half |
8677                                   SUPPORTED_10baseT_Full |
8678                                   SUPPORTED_TP);
8679                 cmd->port = PORT_TP;
8680         } else {
8681                 cmd->supported |= SUPPORTED_FIBRE;
8682                 cmd->port = PORT_FIBRE;
8683         }
8684
8685         cmd->advertising = tp->link_config.advertising;
8686         if (netif_running(dev)) {
8687                 cmd->speed = tp->link_config.active_speed;
8688                 cmd->duplex = tp->link_config.active_duplex;
8689         }
8690         cmd->phy_address = PHY_ADDR;
8691         cmd->transceiver = XCVR_INTERNAL;
8692         cmd->autoneg = tp->link_config.autoneg;
8693         cmd->maxtxpkt = 0;
8694         cmd->maxrxpkt = 0;
8695         return 0;
8696 }
8697
8698 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8699 {
8700         struct tg3 *tp = netdev_priv(dev);
8701
8702         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8703                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8704                         return -EAGAIN;
8705                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8706         }
8707
8708         if (cmd->autoneg != AUTONEG_ENABLE &&
8709             cmd->autoneg != AUTONEG_DISABLE)
8710                 return -EINVAL;
8711
8712         if (cmd->autoneg == AUTONEG_DISABLE &&
8713             cmd->duplex != DUPLEX_FULL &&
8714             cmd->duplex != DUPLEX_HALF)
8715                 return -EINVAL;
8716
8717         if (cmd->autoneg == AUTONEG_ENABLE) {
8718                 u32 mask = ADVERTISED_Autoneg |
8719                            ADVERTISED_Pause |
8720                            ADVERTISED_Asym_Pause;
8721
8722                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8723                         mask |= ADVERTISED_1000baseT_Half |
8724                                 ADVERTISED_1000baseT_Full;
8725
8726                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8727                         mask |= ADVERTISED_100baseT_Half |
8728                                 ADVERTISED_100baseT_Full |
8729                                 ADVERTISED_10baseT_Half |
8730                                 ADVERTISED_10baseT_Full |
8731                                 ADVERTISED_TP;
8732                 else
8733                         mask |= ADVERTISED_FIBRE;
8734
8735                 if (cmd->advertising & ~mask)
8736                         return -EINVAL;
8737
8738                 mask &= (ADVERTISED_1000baseT_Half |
8739                          ADVERTISED_1000baseT_Full |
8740                          ADVERTISED_100baseT_Half |
8741                          ADVERTISED_100baseT_Full |
8742                          ADVERTISED_10baseT_Half |
8743                          ADVERTISED_10baseT_Full);
8744
8745                 cmd->advertising &= mask;
8746         } else {
8747                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8748                         if (cmd->speed != SPEED_1000)
8749                                 return -EINVAL;
8750
8751                         if (cmd->duplex != DUPLEX_FULL)
8752                                 return -EINVAL;
8753                 } else {
8754                         if (cmd->speed != SPEED_100 &&
8755                             cmd->speed != SPEED_10)
8756                                 return -EINVAL;
8757                 }
8758         }
8759
8760         tg3_full_lock(tp, 0);
8761
8762         tp->link_config.autoneg = cmd->autoneg;
8763         if (cmd->autoneg == AUTONEG_ENABLE) {
8764                 tp->link_config.advertising = (cmd->advertising |
8765                                               ADVERTISED_Autoneg);
8766                 tp->link_config.speed = SPEED_INVALID;
8767                 tp->link_config.duplex = DUPLEX_INVALID;
8768         } else {
8769                 tp->link_config.advertising = 0;
8770                 tp->link_config.speed = cmd->speed;
8771                 tp->link_config.duplex = cmd->duplex;
8772         }
8773
8774         tp->link_config.orig_speed = tp->link_config.speed;
8775         tp->link_config.orig_duplex = tp->link_config.duplex;
8776         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8777
8778         if (netif_running(dev))
8779                 tg3_setup_phy(tp, 1);
8780
8781         tg3_full_unlock(tp);
8782
8783         return 0;
8784 }
8785
8786 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8787 {
8788         struct tg3 *tp = netdev_priv(dev);
8789
8790         strcpy(info->driver, DRV_MODULE_NAME);
8791         strcpy(info->version, DRV_MODULE_VERSION);
8792         strcpy(info->fw_version, tp->fw_ver);
8793         strcpy(info->bus_info, pci_name(tp->pdev));
8794 }
8795
8796 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8797 {
8798         struct tg3 *tp = netdev_priv(dev);
8799
8800         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8801             device_can_wakeup(&tp->pdev->dev))
8802                 wol->supported = WAKE_MAGIC;
8803         else
8804                 wol->supported = 0;
8805         wol->wolopts = 0;
8806         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8807             device_can_wakeup(&tp->pdev->dev))
8808                 wol->wolopts = WAKE_MAGIC;
8809         memset(&wol->sopass, 0, sizeof(wol->sopass));
8810 }
8811
8812 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8813 {
8814         struct tg3 *tp = netdev_priv(dev);
8815         struct device *dp = &tp->pdev->dev;
8816
8817         if (wol->wolopts & ~WAKE_MAGIC)
8818                 return -EINVAL;
8819         if ((wol->wolopts & WAKE_MAGIC) &&
8820             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8821                 return -EINVAL;
8822
8823         spin_lock_bh(&tp->lock);
8824         if (wol->wolopts & WAKE_MAGIC) {
8825                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8826                 device_set_wakeup_enable(dp, true);
8827         } else {
8828                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8829                 device_set_wakeup_enable(dp, false);
8830         }
8831         spin_unlock_bh(&tp->lock);
8832
8833         return 0;
8834 }
8835
8836 static u32 tg3_get_msglevel(struct net_device *dev)
8837 {
8838         struct tg3 *tp = netdev_priv(dev);
8839         return tp->msg_enable;
8840 }
8841
8842 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8843 {
8844         struct tg3 *tp = netdev_priv(dev);
8845         tp->msg_enable = value;
8846 }
8847
8848 static int tg3_set_tso(struct net_device *dev, u32 value)
8849 {
8850         struct tg3 *tp = netdev_priv(dev);
8851
8852         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8853                 if (value)
8854                         return -EINVAL;
8855                 return 0;
8856         }
8857         if ((dev->features & NETIF_F_IPV6_CSUM) &&
8858             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8859                 if (value) {
8860                         dev->features |= NETIF_F_TSO6;
8861                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8862                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8863                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8864                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8865                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8866                                 dev->features |= NETIF_F_TSO_ECN;
8867                 } else
8868                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8869         }
8870         return ethtool_op_set_tso(dev, value);
8871 }
8872
8873 static int tg3_nway_reset(struct net_device *dev)
8874 {
8875         struct tg3 *tp = netdev_priv(dev);
8876         int r;
8877
8878         if (!netif_running(dev))
8879                 return -EAGAIN;
8880
8881         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8882                 return -EINVAL;
8883
8884         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8885                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8886                         return -EAGAIN;
8887                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8888         } else {
8889                 u32 bmcr;
8890
8891                 spin_lock_bh(&tp->lock);
8892                 r = -EINVAL;
8893                 tg3_readphy(tp, MII_BMCR, &bmcr);
8894                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8895                     ((bmcr & BMCR_ANENABLE) ||
8896                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8897                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8898                                                    BMCR_ANENABLE);
8899                         r = 0;
8900                 }
8901                 spin_unlock_bh(&tp->lock);
8902         }
8903
8904         return r;
8905 }
8906
8907 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8908 {
8909         struct tg3 *tp = netdev_priv(dev);
8910
8911         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8912         ering->rx_mini_max_pending = 0;
8913         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8914                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8915         else
8916                 ering->rx_jumbo_max_pending = 0;
8917
8918         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8919
8920         ering->rx_pending = tp->rx_pending;
8921         ering->rx_mini_pending = 0;
8922         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8923                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8924         else
8925                 ering->rx_jumbo_pending = 0;
8926
8927         ering->tx_pending = tp->tx_pending;
8928 }
8929
8930 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8931 {
8932         struct tg3 *tp = netdev_priv(dev);
8933         int irq_sync = 0, err = 0;
8934
8935         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8936             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8937             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8938             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8939             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8940              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8941                 return -EINVAL;
8942
8943         if (netif_running(dev)) {
8944                 tg3_phy_stop(tp);
8945                 tg3_netif_stop(tp);
8946                 irq_sync = 1;
8947         }
8948
8949         tg3_full_lock(tp, irq_sync);
8950
8951         tp->rx_pending = ering->rx_pending;
8952
8953         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8954             tp->rx_pending > 63)
8955                 tp->rx_pending = 63;
8956         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8957         tp->tx_pending = ering->tx_pending;
8958
8959         if (netif_running(dev)) {
8960                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8961                 err = tg3_restart_hw(tp, 1);
8962                 if (!err)
8963                         tg3_netif_start(tp);
8964         }
8965
8966         tg3_full_unlock(tp);
8967
8968         if (irq_sync && !err)
8969                 tg3_phy_start(tp);
8970
8971         return err;
8972 }
8973
8974 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8975 {
8976         struct tg3 *tp = netdev_priv(dev);
8977
8978         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8979
8980         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8981                 epause->rx_pause = 1;
8982         else
8983                 epause->rx_pause = 0;
8984
8985         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8986                 epause->tx_pause = 1;
8987         else
8988                 epause->tx_pause = 0;
8989 }
8990
8991 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8992 {
8993         struct tg3 *tp = netdev_priv(dev);
8994         int err = 0;
8995
8996         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8997                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8998                         return -EAGAIN;
8999
9000                 if (epause->autoneg) {
9001                         u32 newadv;
9002                         struct phy_device *phydev;
9003
9004                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9005
9006                         if (epause->rx_pause) {
9007                                 if (epause->tx_pause)
9008                                         newadv = ADVERTISED_Pause;
9009                                 else
9010                                         newadv = ADVERTISED_Pause |
9011                                                  ADVERTISED_Asym_Pause;
9012                         } else if (epause->tx_pause) {
9013                                 newadv = ADVERTISED_Asym_Pause;
9014                         } else
9015                                 newadv = 0;
9016
9017                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9018                                 u32 oldadv = phydev->advertising &
9019                                              (ADVERTISED_Pause |
9020                                               ADVERTISED_Asym_Pause);
9021                                 if (oldadv != newadv) {
9022                                         phydev->advertising &=
9023                                                 ~(ADVERTISED_Pause |
9024                                                   ADVERTISED_Asym_Pause);
9025                                         phydev->advertising |= newadv;
9026                                         err = phy_start_aneg(phydev);
9027                                 }
9028                         } else {
9029                                 tp->link_config.advertising &=
9030                                                 ~(ADVERTISED_Pause |
9031                                                   ADVERTISED_Asym_Pause);
9032                                 tp->link_config.advertising |= newadv;
9033                         }
9034                 } else {
9035                         if (epause->rx_pause)
9036                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9037                         else
9038                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9039
9040                         if (epause->tx_pause)
9041                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9042                         else
9043                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9044
9045                         if (netif_running(dev))
9046                                 tg3_setup_flow_control(tp, 0, 0);
9047                 }
9048         } else {
9049                 int irq_sync = 0;
9050
9051                 if (netif_running(dev)) {
9052                         tg3_netif_stop(tp);
9053                         irq_sync = 1;
9054                 }
9055
9056                 tg3_full_lock(tp, irq_sync);
9057
9058                 if (epause->autoneg)
9059                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9060                 else
9061                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9062                 if (epause->rx_pause)
9063                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9064                 else
9065                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9066                 if (epause->tx_pause)
9067                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9068                 else
9069                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9070
9071                 if (netif_running(dev)) {
9072                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9073                         err = tg3_restart_hw(tp, 1);
9074                         if (!err)
9075                                 tg3_netif_start(tp);
9076                 }
9077
9078                 tg3_full_unlock(tp);
9079         }
9080
9081         return err;
9082 }
9083
9084 static u32 tg3_get_rx_csum(struct net_device *dev)
9085 {
9086         struct tg3 *tp = netdev_priv(dev);
9087         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9088 }
9089
9090 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9091 {
9092         struct tg3 *tp = netdev_priv(dev);
9093
9094         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9095                 if (data != 0)
9096                         return -EINVAL;
9097                 return 0;
9098         }
9099
9100         spin_lock_bh(&tp->lock);
9101         if (data)
9102                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9103         else
9104                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9105         spin_unlock_bh(&tp->lock);
9106
9107         return 0;
9108 }
9109
9110 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9111 {
9112         struct tg3 *tp = netdev_priv(dev);
9113
9114         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9115                 if (data != 0)
9116                         return -EINVAL;
9117                 return 0;
9118         }
9119
9120         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9121                 ethtool_op_set_tx_ipv6_csum(dev, data);
9122         else
9123                 ethtool_op_set_tx_csum(dev, data);
9124
9125         return 0;
9126 }
9127
9128 static int tg3_get_sset_count (struct net_device *dev, int sset)
9129 {
9130         switch (sset) {
9131         case ETH_SS_TEST:
9132                 return TG3_NUM_TEST;
9133         case ETH_SS_STATS:
9134                 return TG3_NUM_STATS;
9135         default:
9136                 return -EOPNOTSUPP;
9137         }
9138 }
9139
9140 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9141 {
9142         switch (stringset) {
9143         case ETH_SS_STATS:
9144                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9145                 break;
9146         case ETH_SS_TEST:
9147                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9148                 break;
9149         default:
9150                 WARN_ON(1);     /* we need a WARN() */
9151                 break;
9152         }
9153 }
9154
9155 static int tg3_phys_id(struct net_device *dev, u32 data)
9156 {
9157         struct tg3 *tp = netdev_priv(dev);
9158         int i;
9159
9160         if (!netif_running(tp->dev))
9161                 return -EAGAIN;
9162
9163         if (data == 0)
9164                 data = UINT_MAX / 2;
9165
9166         for (i = 0; i < (data * 2); i++) {
9167                 if ((i % 2) == 0)
9168                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9169                                            LED_CTRL_1000MBPS_ON |
9170                                            LED_CTRL_100MBPS_ON |
9171                                            LED_CTRL_10MBPS_ON |
9172                                            LED_CTRL_TRAFFIC_OVERRIDE |
9173                                            LED_CTRL_TRAFFIC_BLINK |
9174                                            LED_CTRL_TRAFFIC_LED);
9175
9176                 else
9177                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9178                                            LED_CTRL_TRAFFIC_OVERRIDE);
9179
9180                 if (msleep_interruptible(500))
9181                         break;
9182         }
9183         tw32(MAC_LED_CTRL, tp->led_ctrl);
9184         return 0;
9185 }
9186
9187 static void tg3_get_ethtool_stats (struct net_device *dev,
9188                                    struct ethtool_stats *estats, u64 *tmp_stats)
9189 {
9190         struct tg3 *tp = netdev_priv(dev);
9191         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9192 }
9193
9194 #define NVRAM_TEST_SIZE 0x100
9195 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9196 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9197 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9198 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9199 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9200
9201 static int tg3_test_nvram(struct tg3 *tp)
9202 {
9203         u32 csum, magic;
9204         __be32 *buf;
9205         int i, j, k, err = 0, size;
9206
9207         if (tg3_nvram_read(tp, 0, &magic) != 0)
9208                 return -EIO;
9209
9210         if (magic == TG3_EEPROM_MAGIC)
9211                 size = NVRAM_TEST_SIZE;
9212         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9213                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9214                     TG3_EEPROM_SB_FORMAT_1) {
9215                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9216                         case TG3_EEPROM_SB_REVISION_0:
9217                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9218                                 break;
9219                         case TG3_EEPROM_SB_REVISION_2:
9220                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9221                                 break;
9222                         case TG3_EEPROM_SB_REVISION_3:
9223                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9224                                 break;
9225                         default:
9226                                 return 0;
9227                         }
9228                 } else
9229                         return 0;
9230         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9231                 size = NVRAM_SELFBOOT_HW_SIZE;
9232         else
9233                 return -EIO;
9234
9235         buf = kmalloc(size, GFP_KERNEL);
9236         if (buf == NULL)
9237                 return -ENOMEM;
9238
9239         err = -EIO;
9240         for (i = 0, j = 0; i < size; i += 4, j++) {
9241                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9242                 if (err)
9243                         break;
9244         }
9245         if (i < size)
9246                 goto out;
9247
9248         /* Selfboot format */
9249         magic = be32_to_cpu(buf[0]);
9250         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9251             TG3_EEPROM_MAGIC_FW) {
9252                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9253
9254                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9255                     TG3_EEPROM_SB_REVISION_2) {
9256                         /* For rev 2, the csum doesn't include the MBA. */
9257                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9258                                 csum8 += buf8[i];
9259                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9260                                 csum8 += buf8[i];
9261                 } else {
9262                         for (i = 0; i < size; i++)
9263                                 csum8 += buf8[i];
9264                 }
9265
9266                 if (csum8 == 0) {
9267                         err = 0;
9268                         goto out;
9269                 }
9270
9271                 err = -EIO;
9272                 goto out;
9273         }
9274
9275         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9276             TG3_EEPROM_MAGIC_HW) {
9277                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9278                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9279                 u8 *buf8 = (u8 *) buf;
9280
9281                 /* Separate the parity bits and the data bytes.  */
9282                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9283                         if ((i == 0) || (i == 8)) {
9284                                 int l;
9285                                 u8 msk;
9286
9287                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9288                                         parity[k++] = buf8[i] & msk;
9289                                 i++;
9290                         }
9291                         else if (i == 16) {
9292                                 int l;
9293                                 u8 msk;
9294
9295                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9296                                         parity[k++] = buf8[i] & msk;
9297                                 i++;
9298
9299                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9300                                         parity[k++] = buf8[i] & msk;
9301                                 i++;
9302                         }
9303                         data[j++] = buf8[i];
9304                 }
9305
9306                 err = -EIO;
9307                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9308                         u8 hw8 = hweight8(data[i]);
9309
9310                         if ((hw8 & 0x1) && parity[i])
9311                                 goto out;
9312                         else if (!(hw8 & 0x1) && !parity[i])
9313                                 goto out;
9314                 }
9315                 err = 0;
9316                 goto out;
9317         }
9318
9319         /* Bootstrap checksum at offset 0x10 */
9320         csum = calc_crc((unsigned char *) buf, 0x10);
9321         if (csum != be32_to_cpu(buf[0x10/4]))
9322                 goto out;
9323
9324         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9325         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9326         if (csum != be32_to_cpu(buf[0xfc/4]))
9327                 goto out;
9328
9329         err = 0;
9330
9331 out:
9332         kfree(buf);
9333         return err;
9334 }
9335
9336 #define TG3_SERDES_TIMEOUT_SEC  2
9337 #define TG3_COPPER_TIMEOUT_SEC  6
9338
9339 static int tg3_test_link(struct tg3 *tp)
9340 {
9341         int i, max;
9342
9343         if (!netif_running(tp->dev))
9344                 return -ENODEV;
9345
9346         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9347                 max = TG3_SERDES_TIMEOUT_SEC;
9348         else
9349                 max = TG3_COPPER_TIMEOUT_SEC;
9350
9351         for (i = 0; i < max; i++) {
9352                 if (netif_carrier_ok(tp->dev))
9353                         return 0;
9354
9355                 if (msleep_interruptible(1000))
9356                         break;
9357         }
9358
9359         return -EIO;
9360 }
9361
9362 /* Only test the commonly used registers */
9363 static int tg3_test_registers(struct tg3 *tp)
9364 {
9365         int i, is_5705, is_5750;
9366         u32 offset, read_mask, write_mask, val, save_val, read_val;
9367         static struct {
9368                 u16 offset;
9369                 u16 flags;
9370 #define TG3_FL_5705     0x1
9371 #define TG3_FL_NOT_5705 0x2
9372 #define TG3_FL_NOT_5788 0x4
9373 #define TG3_FL_NOT_5750 0x8
9374                 u32 read_mask;
9375                 u32 write_mask;
9376         } reg_tbl[] = {
9377                 /* MAC Control Registers */
9378                 { MAC_MODE, TG3_FL_NOT_5705,
9379                         0x00000000, 0x00ef6f8c },
9380                 { MAC_MODE, TG3_FL_5705,
9381                         0x00000000, 0x01ef6b8c },
9382                 { MAC_STATUS, TG3_FL_NOT_5705,
9383                         0x03800107, 0x00000000 },
9384                 { MAC_STATUS, TG3_FL_5705,
9385                         0x03800100, 0x00000000 },
9386                 { MAC_ADDR_0_HIGH, 0x0000,
9387                         0x00000000, 0x0000ffff },
9388                 { MAC_ADDR_0_LOW, 0x0000,
9389                         0x00000000, 0xffffffff },
9390                 { MAC_RX_MTU_SIZE, 0x0000,
9391                         0x00000000, 0x0000ffff },
9392                 { MAC_TX_MODE, 0x0000,
9393                         0x00000000, 0x00000070 },
9394                 { MAC_TX_LENGTHS, 0x0000,
9395                         0x00000000, 0x00003fff },
9396                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9397                         0x00000000, 0x000007fc },
9398                 { MAC_RX_MODE, TG3_FL_5705,
9399                         0x00000000, 0x000007dc },
9400                 { MAC_HASH_REG_0, 0x0000,
9401                         0x00000000, 0xffffffff },
9402                 { MAC_HASH_REG_1, 0x0000,
9403                         0x00000000, 0xffffffff },
9404                 { MAC_HASH_REG_2, 0x0000,
9405                         0x00000000, 0xffffffff },
9406                 { MAC_HASH_REG_3, 0x0000,
9407                         0x00000000, 0xffffffff },
9408
9409                 /* Receive Data and Receive BD Initiator Control Registers. */
9410                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9411                         0x00000000, 0xffffffff },
9412                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9413                         0x00000000, 0xffffffff },
9414                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9415                         0x00000000, 0x00000003 },
9416                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9417                         0x00000000, 0xffffffff },
9418                 { RCVDBDI_STD_BD+0, 0x0000,
9419                         0x00000000, 0xffffffff },
9420                 { RCVDBDI_STD_BD+4, 0x0000,
9421                         0x00000000, 0xffffffff },
9422                 { RCVDBDI_STD_BD+8, 0x0000,
9423                         0x00000000, 0xffff0002 },
9424                 { RCVDBDI_STD_BD+0xc, 0x0000,
9425                         0x00000000, 0xffffffff },
9426
9427                 /* Receive BD Initiator Control Registers. */
9428                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9429                         0x00000000, 0xffffffff },
9430                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9431                         0x00000000, 0x000003ff },
9432                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9433                         0x00000000, 0xffffffff },
9434
9435                 /* Host Coalescing Control Registers. */
9436                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9437                         0x00000000, 0x00000004 },
9438                 { HOSTCC_MODE, TG3_FL_5705,
9439                         0x00000000, 0x000000f6 },
9440                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9441                         0x00000000, 0xffffffff },
9442                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9443                         0x00000000, 0x000003ff },
9444                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9445                         0x00000000, 0xffffffff },
9446                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9447                         0x00000000, 0x000003ff },
9448                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9449                         0x00000000, 0xffffffff },
9450                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9451                         0x00000000, 0x000000ff },
9452                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9453                         0x00000000, 0xffffffff },
9454                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9455                         0x00000000, 0x000000ff },
9456                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9457                         0x00000000, 0xffffffff },
9458                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9459                         0x00000000, 0xffffffff },
9460                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9461                         0x00000000, 0xffffffff },
9462                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9463                         0x00000000, 0x000000ff },
9464                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9465                         0x00000000, 0xffffffff },
9466                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9467                         0x00000000, 0x000000ff },
9468                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9469                         0x00000000, 0xffffffff },
9470                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9471                         0x00000000, 0xffffffff },
9472                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9473                         0x00000000, 0xffffffff },
9474                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9475                         0x00000000, 0xffffffff },
9476                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9477                         0x00000000, 0xffffffff },
9478                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9479                         0xffffffff, 0x00000000 },
9480                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9481                         0xffffffff, 0x00000000 },
9482
9483                 /* Buffer Manager Control Registers. */
9484                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9485                         0x00000000, 0x007fff80 },
9486                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9487                         0x00000000, 0x007fffff },
9488                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9489                         0x00000000, 0x0000003f },
9490                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9491                         0x00000000, 0x000001ff },
9492                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9493                         0x00000000, 0x000001ff },
9494                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9495                         0xffffffff, 0x00000000 },
9496                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9497                         0xffffffff, 0x00000000 },
9498
9499                 /* Mailbox Registers */
9500                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9501                         0x00000000, 0x000001ff },
9502                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9503                         0x00000000, 0x000001ff },
9504                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9505                         0x00000000, 0x000007ff },
9506                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9507                         0x00000000, 0x000001ff },
9508
9509                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9510         };
9511
9512         is_5705 = is_5750 = 0;
9513         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9514                 is_5705 = 1;
9515                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9516                         is_5750 = 1;
9517         }
9518
9519         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9520                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9521                         continue;
9522
9523                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9524                         continue;
9525
9526                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9527                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9528                         continue;
9529
9530                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9531                         continue;
9532
9533                 offset = (u32) reg_tbl[i].offset;
9534                 read_mask = reg_tbl[i].read_mask;
9535                 write_mask = reg_tbl[i].write_mask;
9536
9537                 /* Save the original register content */
9538                 save_val = tr32(offset);
9539
9540                 /* Determine the read-only value. */
9541                 read_val = save_val & read_mask;
9542
9543                 /* Write zero to the register, then make sure the read-only bits
9544                  * are not changed and the read/write bits are all zeros.
9545                  */
9546                 tw32(offset, 0);
9547
9548                 val = tr32(offset);
9549
9550                 /* Test the read-only and read/write bits. */
9551                 if (((val & read_mask) != read_val) || (val & write_mask))
9552                         goto out;
9553
9554                 /* Write ones to all the bits defined by RdMask and WrMask, then
9555                  * make sure the read-only bits are not changed and the
9556                  * read/write bits are all ones.
9557                  */
9558                 tw32(offset, read_mask | write_mask);
9559
9560                 val = tr32(offset);
9561
9562                 /* Test the read-only bits. */
9563                 if ((val & read_mask) != read_val)
9564                         goto out;
9565
9566                 /* Test the read/write bits. */
9567                 if ((val & write_mask) != write_mask)
9568                         goto out;
9569
9570                 tw32(offset, save_val);
9571         }
9572
9573         return 0;
9574
9575 out:
9576         if (netif_msg_hw(tp))
9577                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9578                        offset);
9579         tw32(offset, save_val);
9580         return -EIO;
9581 }
9582
9583 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9584 {
9585         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9586         int i;
9587         u32 j;
9588
9589         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9590                 for (j = 0; j < len; j += 4) {
9591                         u32 val;
9592
9593                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9594                         tg3_read_mem(tp, offset + j, &val);
9595                         if (val != test_pattern[i])
9596                                 return -EIO;
9597                 }
9598         }
9599         return 0;
9600 }
9601
9602 static int tg3_test_memory(struct tg3 *tp)
9603 {
9604         static struct mem_entry {
9605                 u32 offset;
9606                 u32 len;
9607         } mem_tbl_570x[] = {
9608                 { 0x00000000, 0x00b50},
9609                 { 0x00002000, 0x1c000},
9610                 { 0xffffffff, 0x00000}
9611         }, mem_tbl_5705[] = {
9612                 { 0x00000100, 0x0000c},
9613                 { 0x00000200, 0x00008},
9614                 { 0x00004000, 0x00800},
9615                 { 0x00006000, 0x01000},
9616                 { 0x00008000, 0x02000},
9617                 { 0x00010000, 0x0e000},
9618                 { 0xffffffff, 0x00000}
9619         }, mem_tbl_5755[] = {
9620                 { 0x00000200, 0x00008},
9621                 { 0x00004000, 0x00800},
9622                 { 0x00006000, 0x00800},
9623                 { 0x00008000, 0x02000},
9624                 { 0x00010000, 0x0c000},
9625                 { 0xffffffff, 0x00000}
9626         }, mem_tbl_5906[] = {
9627                 { 0x00000200, 0x00008},
9628                 { 0x00004000, 0x00400},
9629                 { 0x00006000, 0x00400},
9630                 { 0x00008000, 0x01000},
9631                 { 0x00010000, 0x01000},
9632                 { 0xffffffff, 0x00000}
9633         };
9634         struct mem_entry *mem_tbl;
9635         int err = 0;
9636         int i;
9637
9638         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9639                 mem_tbl = mem_tbl_5755;
9640         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9641                 mem_tbl = mem_tbl_5906;
9642         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9643                 mem_tbl = mem_tbl_5705;
9644         else
9645                 mem_tbl = mem_tbl_570x;
9646
9647         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9648                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9649                     mem_tbl[i].len)) != 0)
9650                         break;
9651         }
9652
9653         return err;
9654 }
9655
9656 #define TG3_MAC_LOOPBACK        0
9657 #define TG3_PHY_LOOPBACK        1
9658
9659 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9660 {
9661         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9662         u32 desc_idx;
9663         struct sk_buff *skb, *rx_skb;
9664         u8 *tx_data;
9665         dma_addr_t map;
9666         int num_pkts, tx_len, rx_len, i, err;
9667         struct tg3_rx_buffer_desc *desc;
9668
9669         if (loopback_mode == TG3_MAC_LOOPBACK) {
9670                 /* HW errata - mac loopback fails in some cases on 5780.
9671                  * Normal traffic and PHY loopback are not affected by
9672                  * errata.
9673                  */
9674                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9675                         return 0;
9676
9677                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9678                            MAC_MODE_PORT_INT_LPBACK;
9679                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9680                         mac_mode |= MAC_MODE_LINK_POLARITY;
9681                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9682                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9683                 else
9684                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9685                 tw32(MAC_MODE, mac_mode);
9686         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9687                 u32 val;
9688
9689                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9690                         u32 phytest;
9691
9692                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9693                                 u32 phy;
9694
9695                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9696                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9697                                 if (!tg3_readphy(tp, 0x1b, &phy))
9698                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9699                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9700                         }
9701                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9702                 } else
9703                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9704
9705                 tg3_phy_toggle_automdix(tp, 0);
9706
9707                 tg3_writephy(tp, MII_BMCR, val);
9708                 udelay(40);
9709
9710                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9711                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9712                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9713                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9714                 } else
9715                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9716
9717                 /* reset to prevent losing 1st rx packet intermittently */
9718                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9719                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9720                         udelay(10);
9721                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9722                 }
9723                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9724                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9725                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9726                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9727                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9728                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9729                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9730                 }
9731                 tw32(MAC_MODE, mac_mode);
9732         }
9733         else
9734                 return -EINVAL;
9735
9736         err = -EIO;
9737
9738         tx_len = 1514;
9739         skb = netdev_alloc_skb(tp->dev, tx_len);
9740         if (!skb)
9741                 return -ENOMEM;
9742
9743         tx_data = skb_put(skb, tx_len);
9744         memcpy(tx_data, tp->dev->dev_addr, 6);
9745         memset(tx_data + 6, 0x0, 8);
9746
9747         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9748
9749         for (i = 14; i < tx_len; i++)
9750                 tx_data[i] = (u8) (i & 0xff);
9751
9752         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9753
9754         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9755              HOSTCC_MODE_NOW);
9756
9757         udelay(10);
9758
9759         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9760
9761         num_pkts = 0;
9762
9763         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9764
9765         tp->tx_prod++;
9766         num_pkts++;
9767
9768         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9769                      tp->tx_prod);
9770         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9771
9772         udelay(10);
9773
9774         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9775         for (i = 0; i < 25; i++) {
9776                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9777                        HOSTCC_MODE_NOW);
9778
9779                 udelay(10);
9780
9781                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9782                 rx_idx = tp->hw_status->idx[0].rx_producer;
9783                 if ((tx_idx == tp->tx_prod) &&
9784                     (rx_idx == (rx_start_idx + num_pkts)))
9785                         break;
9786         }
9787
9788         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9789         dev_kfree_skb(skb);
9790
9791         if (tx_idx != tp->tx_prod)
9792                 goto out;
9793
9794         if (rx_idx != rx_start_idx + num_pkts)
9795                 goto out;
9796
9797         desc = &tp->rx_rcb[rx_start_idx];
9798         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9799         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9800         if (opaque_key != RXD_OPAQUE_RING_STD)
9801                 goto out;
9802
9803         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9804             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9805                 goto out;
9806
9807         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9808         if (rx_len != tx_len)
9809                 goto out;
9810
9811         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9812
9813         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9814         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9815
9816         for (i = 14; i < tx_len; i++) {
9817                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9818                         goto out;
9819         }
9820         err = 0;
9821
9822         /* tg3_free_rings will unmap and free the rx_skb */
9823 out:
9824         return err;
9825 }
9826
9827 #define TG3_MAC_LOOPBACK_FAILED         1
9828 #define TG3_PHY_LOOPBACK_FAILED         2
9829 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9830                                          TG3_PHY_LOOPBACK_FAILED)
9831
9832 static int tg3_test_loopback(struct tg3 *tp)
9833 {
9834         int err = 0;
9835         u32 cpmuctrl = 0;
9836
9837         if (!netif_running(tp->dev))
9838                 return TG3_LOOPBACK_FAILED;
9839
9840         err = tg3_reset_hw(tp, 1);
9841         if (err)
9842                 return TG3_LOOPBACK_FAILED;
9843
9844         /* Turn off gphy autopowerdown. */
9845         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9846                 tg3_phy_toggle_apd(tp, false);
9847
9848         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9849                 int i;
9850                 u32 status;
9851
9852                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9853
9854                 /* Wait for up to 40 microseconds to acquire lock. */
9855                 for (i = 0; i < 4; i++) {
9856                         status = tr32(TG3_CPMU_MUTEX_GNT);
9857                         if (status == CPMU_MUTEX_GNT_DRIVER)
9858                                 break;
9859                         udelay(10);
9860                 }
9861
9862                 if (status != CPMU_MUTEX_GNT_DRIVER)
9863                         return TG3_LOOPBACK_FAILED;
9864
9865                 /* Turn off link-based power management. */
9866                 cpmuctrl = tr32(TG3_CPMU_CTRL);
9867                 tw32(TG3_CPMU_CTRL,
9868                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9869                                   CPMU_CTRL_LINK_AWARE_MODE));
9870         }
9871
9872         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9873                 err |= TG3_MAC_LOOPBACK_FAILED;
9874
9875         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9876                 tw32(TG3_CPMU_CTRL, cpmuctrl);
9877
9878                 /* Release the mutex */
9879                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9880         }
9881
9882         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9883             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9884                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9885                         err |= TG3_PHY_LOOPBACK_FAILED;
9886         }
9887
9888         /* Re-enable gphy autopowerdown. */
9889         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9890                 tg3_phy_toggle_apd(tp, true);
9891
9892         return err;
9893 }
9894
9895 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9896                           u64 *data)
9897 {
9898         struct tg3 *tp = netdev_priv(dev);
9899
9900         if (tp->link_config.phy_is_low_power)
9901                 tg3_set_power_state(tp, PCI_D0);
9902
9903         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9904
9905         if (tg3_test_nvram(tp) != 0) {
9906                 etest->flags |= ETH_TEST_FL_FAILED;
9907                 data[0] = 1;
9908         }
9909         if (tg3_test_link(tp) != 0) {
9910                 etest->flags |= ETH_TEST_FL_FAILED;
9911                 data[1] = 1;
9912         }
9913         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9914                 int err, err2 = 0, irq_sync = 0;
9915
9916                 if (netif_running(dev)) {
9917                         tg3_phy_stop(tp);
9918                         tg3_netif_stop(tp);
9919                         irq_sync = 1;
9920                 }
9921
9922                 tg3_full_lock(tp, irq_sync);
9923
9924                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9925                 err = tg3_nvram_lock(tp);
9926                 tg3_halt_cpu(tp, RX_CPU_BASE);
9927                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9928                         tg3_halt_cpu(tp, TX_CPU_BASE);
9929                 if (!err)
9930                         tg3_nvram_unlock(tp);
9931
9932                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9933                         tg3_phy_reset(tp);
9934
9935                 if (tg3_test_registers(tp) != 0) {
9936                         etest->flags |= ETH_TEST_FL_FAILED;
9937                         data[2] = 1;
9938                 }
9939                 if (tg3_test_memory(tp) != 0) {
9940                         etest->flags |= ETH_TEST_FL_FAILED;
9941                         data[3] = 1;
9942                 }
9943                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9944                         etest->flags |= ETH_TEST_FL_FAILED;
9945
9946                 tg3_full_unlock(tp);
9947
9948                 if (tg3_test_interrupt(tp) != 0) {
9949                         etest->flags |= ETH_TEST_FL_FAILED;
9950                         data[5] = 1;
9951                 }
9952
9953                 tg3_full_lock(tp, 0);
9954
9955                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9956                 if (netif_running(dev)) {
9957                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9958                         err2 = tg3_restart_hw(tp, 1);
9959                         if (!err2)
9960                                 tg3_netif_start(tp);
9961                 }
9962
9963                 tg3_full_unlock(tp);
9964
9965                 if (irq_sync && !err2)
9966                         tg3_phy_start(tp);
9967         }
9968         if (tp->link_config.phy_is_low_power)
9969                 tg3_set_power_state(tp, PCI_D3hot);
9970
9971 }
9972
9973 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9974 {
9975         struct mii_ioctl_data *data = if_mii(ifr);
9976         struct tg3 *tp = netdev_priv(dev);
9977         int err;
9978
9979         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9980                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9981                         return -EAGAIN;
9982                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
9983         }
9984
9985         switch(cmd) {
9986         case SIOCGMIIPHY:
9987                 data->phy_id = PHY_ADDR;
9988
9989                 /* fallthru */
9990         case SIOCGMIIREG: {
9991                 u32 mii_regval;
9992
9993                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9994                         break;                  /* We have no PHY */
9995
9996                 if (tp->link_config.phy_is_low_power)
9997                         return -EAGAIN;
9998
9999                 spin_lock_bh(&tp->lock);
10000                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10001                 spin_unlock_bh(&tp->lock);
10002
10003                 data->val_out = mii_regval;
10004
10005                 return err;
10006         }
10007
10008         case SIOCSMIIREG:
10009                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10010                         break;                  /* We have no PHY */
10011
10012                 if (!capable(CAP_NET_ADMIN))
10013                         return -EPERM;
10014
10015                 if (tp->link_config.phy_is_low_power)
10016                         return -EAGAIN;
10017
10018                 spin_lock_bh(&tp->lock);
10019                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10020                 spin_unlock_bh(&tp->lock);
10021
10022                 return err;
10023
10024         default:
10025                 /* do nothing */
10026                 break;
10027         }
10028         return -EOPNOTSUPP;
10029 }
10030
10031 #if TG3_VLAN_TAG_USED
10032 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10033 {
10034         struct tg3 *tp = netdev_priv(dev);
10035
10036         if (!netif_running(dev)) {
10037                 tp->vlgrp = grp;
10038                 return;
10039         }
10040
10041         tg3_netif_stop(tp);
10042
10043         tg3_full_lock(tp, 0);
10044
10045         tp->vlgrp = grp;
10046
10047         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10048         __tg3_set_rx_mode(dev);
10049
10050         tg3_netif_start(tp);
10051
10052         tg3_full_unlock(tp);
10053 }
10054 #endif
10055
10056 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10057 {
10058         struct tg3 *tp = netdev_priv(dev);
10059
10060         memcpy(ec, &tp->coal, sizeof(*ec));
10061         return 0;
10062 }
10063
10064 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10065 {
10066         struct tg3 *tp = netdev_priv(dev);
10067         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10068         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10069
10070         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10071                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10072                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10073                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10074                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10075         }
10076
10077         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10078             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10079             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10080             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10081             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10082             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10083             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10084             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10085             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10086             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10087                 return -EINVAL;
10088
10089         /* No rx interrupts will be generated if both are zero */
10090         if ((ec->rx_coalesce_usecs == 0) &&
10091             (ec->rx_max_coalesced_frames == 0))
10092                 return -EINVAL;
10093
10094         /* No tx interrupts will be generated if both are zero */
10095         if ((ec->tx_coalesce_usecs == 0) &&
10096             (ec->tx_max_coalesced_frames == 0))
10097                 return -EINVAL;
10098
10099         /* Only copy relevant parameters, ignore all others. */
10100         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10101         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10102         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10103         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10104         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10105         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10106         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10107         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10108         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10109
10110         if (netif_running(dev)) {
10111                 tg3_full_lock(tp, 0);
10112                 __tg3_set_coalesce(tp, &tp->coal);
10113                 tg3_full_unlock(tp);
10114         }
10115         return 0;
10116 }
10117
10118 static const struct ethtool_ops tg3_ethtool_ops = {
10119         .get_settings           = tg3_get_settings,
10120         .set_settings           = tg3_set_settings,
10121         .get_drvinfo            = tg3_get_drvinfo,
10122         .get_regs_len           = tg3_get_regs_len,
10123         .get_regs               = tg3_get_regs,
10124         .get_wol                = tg3_get_wol,
10125         .set_wol                = tg3_set_wol,
10126         .get_msglevel           = tg3_get_msglevel,
10127         .set_msglevel           = tg3_set_msglevel,
10128         .nway_reset             = tg3_nway_reset,
10129         .get_link               = ethtool_op_get_link,
10130         .get_eeprom_len         = tg3_get_eeprom_len,
10131         .get_eeprom             = tg3_get_eeprom,
10132         .set_eeprom             = tg3_set_eeprom,
10133         .get_ringparam          = tg3_get_ringparam,
10134         .set_ringparam          = tg3_set_ringparam,
10135         .get_pauseparam         = tg3_get_pauseparam,
10136         .set_pauseparam         = tg3_set_pauseparam,
10137         .get_rx_csum            = tg3_get_rx_csum,
10138         .set_rx_csum            = tg3_set_rx_csum,
10139         .set_tx_csum            = tg3_set_tx_csum,
10140         .set_sg                 = ethtool_op_set_sg,
10141         .set_tso                = tg3_set_tso,
10142         .self_test              = tg3_self_test,
10143         .get_strings            = tg3_get_strings,
10144         .phys_id                = tg3_phys_id,
10145         .get_ethtool_stats      = tg3_get_ethtool_stats,
10146         .get_coalesce           = tg3_get_coalesce,
10147         .set_coalesce           = tg3_set_coalesce,
10148         .get_sset_count         = tg3_get_sset_count,
10149 };
10150
10151 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10152 {
10153         u32 cursize, val, magic;
10154
10155         tp->nvram_size = EEPROM_CHIP_SIZE;
10156
10157         if (tg3_nvram_read(tp, 0, &magic) != 0)
10158                 return;
10159
10160         if ((magic != TG3_EEPROM_MAGIC) &&
10161             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10162             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10163                 return;
10164
10165         /*
10166          * Size the chip by reading offsets at increasing powers of two.
10167          * When we encounter our validation signature, we know the addressing
10168          * has wrapped around, and thus have our chip size.
10169          */
10170         cursize = 0x10;
10171
10172         while (cursize < tp->nvram_size) {
10173                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10174                         return;
10175
10176                 if (val == magic)
10177                         break;
10178
10179                 cursize <<= 1;
10180         }
10181
10182         tp->nvram_size = cursize;
10183 }
10184
10185 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10186 {
10187         u32 val;
10188
10189         if (tg3_nvram_read(tp, 0, &val) != 0)
10190                 return;
10191
10192         /* Selfboot format */
10193         if (val != TG3_EEPROM_MAGIC) {
10194                 tg3_get_eeprom_size(tp);
10195                 return;
10196         }
10197
10198         if (tg3_nvram_read_swab(tp, 0xf0, &val) == 0) {
10199                 if (val != 0) {
10200                         tp->nvram_size = (val >> 16) * 1024;
10201                         return;
10202                 }
10203         }
10204         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10205 }
10206
10207 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10208 {
10209         u32 nvcfg1;
10210
10211         nvcfg1 = tr32(NVRAM_CFG1);
10212         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10213                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10214         }
10215         else {
10216                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10217                 tw32(NVRAM_CFG1, nvcfg1);
10218         }
10219
10220         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10221             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10222                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10223                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10224                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10225                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10226                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10227                                 break;
10228                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10229                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10230                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10231                                 break;
10232                         case FLASH_VENDOR_ATMEL_EEPROM:
10233                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10234                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10235                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10236                                 break;
10237                         case FLASH_VENDOR_ST:
10238                                 tp->nvram_jedecnum = JEDEC_ST;
10239                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10240                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10241                                 break;
10242                         case FLASH_VENDOR_SAIFUN:
10243                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10244                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10245                                 break;
10246                         case FLASH_VENDOR_SST_SMALL:
10247                         case FLASH_VENDOR_SST_LARGE:
10248                                 tp->nvram_jedecnum = JEDEC_SST;
10249                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10250                                 break;
10251                 }
10252         }
10253         else {
10254                 tp->nvram_jedecnum = JEDEC_ATMEL;
10255                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10256                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10257         }
10258 }
10259
10260 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10261 {
10262         u32 nvcfg1;
10263
10264         nvcfg1 = tr32(NVRAM_CFG1);
10265
10266         /* NVRAM protection for TPM */
10267         if (nvcfg1 & (1 << 27))
10268                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10269
10270         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10271                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10272                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10273                         tp->nvram_jedecnum = JEDEC_ATMEL;
10274                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10275                         break;
10276                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10277                         tp->nvram_jedecnum = JEDEC_ATMEL;
10278                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10279                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10280                         break;
10281                 case FLASH_5752VENDOR_ST_M45PE10:
10282                 case FLASH_5752VENDOR_ST_M45PE20:
10283                 case FLASH_5752VENDOR_ST_M45PE40:
10284                         tp->nvram_jedecnum = JEDEC_ST;
10285                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10286                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10287                         break;
10288         }
10289
10290         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10291                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10292                         case FLASH_5752PAGE_SIZE_256:
10293                                 tp->nvram_pagesize = 256;
10294                                 break;
10295                         case FLASH_5752PAGE_SIZE_512:
10296                                 tp->nvram_pagesize = 512;
10297                                 break;
10298                         case FLASH_5752PAGE_SIZE_1K:
10299                                 tp->nvram_pagesize = 1024;
10300                                 break;
10301                         case FLASH_5752PAGE_SIZE_2K:
10302                                 tp->nvram_pagesize = 2048;
10303                                 break;
10304                         case FLASH_5752PAGE_SIZE_4K:
10305                                 tp->nvram_pagesize = 4096;
10306                                 break;
10307                         case FLASH_5752PAGE_SIZE_264:
10308                                 tp->nvram_pagesize = 264;
10309                                 break;
10310                 }
10311         }
10312         else {
10313                 /* For eeprom, set pagesize to maximum eeprom size */
10314                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10315
10316                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10317                 tw32(NVRAM_CFG1, nvcfg1);
10318         }
10319 }
10320
10321 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10322 {
10323         u32 nvcfg1, protect = 0;
10324
10325         nvcfg1 = tr32(NVRAM_CFG1);
10326
10327         /* NVRAM protection for TPM */
10328         if (nvcfg1 & (1 << 27)) {
10329                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10330                 protect = 1;
10331         }
10332
10333         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10334         switch (nvcfg1) {
10335                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10336                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10337                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10338                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10339                         tp->nvram_jedecnum = JEDEC_ATMEL;
10340                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10341                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10342                         tp->nvram_pagesize = 264;
10343                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10344                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10345                                 tp->nvram_size = (protect ? 0x3e200 :
10346                                                   TG3_NVRAM_SIZE_512KB);
10347                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10348                                 tp->nvram_size = (protect ? 0x1f200 :
10349                                                   TG3_NVRAM_SIZE_256KB);
10350                         else
10351                                 tp->nvram_size = (protect ? 0x1f200 :
10352                                                   TG3_NVRAM_SIZE_128KB);
10353                         break;
10354                 case FLASH_5752VENDOR_ST_M45PE10:
10355                 case FLASH_5752VENDOR_ST_M45PE20:
10356                 case FLASH_5752VENDOR_ST_M45PE40:
10357                         tp->nvram_jedecnum = JEDEC_ST;
10358                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10359                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10360                         tp->nvram_pagesize = 256;
10361                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10362                                 tp->nvram_size = (protect ?
10363                                                   TG3_NVRAM_SIZE_64KB :
10364                                                   TG3_NVRAM_SIZE_128KB);
10365                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10366                                 tp->nvram_size = (protect ?
10367                                                   TG3_NVRAM_SIZE_64KB :
10368                                                   TG3_NVRAM_SIZE_256KB);
10369                         else
10370                                 tp->nvram_size = (protect ?
10371                                                   TG3_NVRAM_SIZE_128KB :
10372                                                   TG3_NVRAM_SIZE_512KB);
10373                         break;
10374         }
10375 }
10376
10377 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10378 {
10379         u32 nvcfg1;
10380
10381         nvcfg1 = tr32(NVRAM_CFG1);
10382
10383         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10384                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10385                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10386                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10387                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10388                         tp->nvram_jedecnum = JEDEC_ATMEL;
10389                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10390                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10391
10392                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10393                         tw32(NVRAM_CFG1, nvcfg1);
10394                         break;
10395                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10396                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10397                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10398                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10399                         tp->nvram_jedecnum = JEDEC_ATMEL;
10400                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10401                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10402                         tp->nvram_pagesize = 264;
10403                         break;
10404                 case FLASH_5752VENDOR_ST_M45PE10:
10405                 case FLASH_5752VENDOR_ST_M45PE20:
10406                 case FLASH_5752VENDOR_ST_M45PE40:
10407                         tp->nvram_jedecnum = JEDEC_ST;
10408                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10409                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10410                         tp->nvram_pagesize = 256;
10411                         break;
10412         }
10413 }
10414
10415 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10416 {
10417         u32 nvcfg1, protect = 0;
10418
10419         nvcfg1 = tr32(NVRAM_CFG1);
10420
10421         /* NVRAM protection for TPM */
10422         if (nvcfg1 & (1 << 27)) {
10423                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10424                 protect = 1;
10425         }
10426
10427         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10428         switch (nvcfg1) {
10429                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10430                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10431                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10432                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10433                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10434                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10435                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10436                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10437                         tp->nvram_jedecnum = JEDEC_ATMEL;
10438                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10439                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10440                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10441                         tp->nvram_pagesize = 256;
10442                         break;
10443                 case FLASH_5761VENDOR_ST_A_M45PE20:
10444                 case FLASH_5761VENDOR_ST_A_M45PE40:
10445                 case FLASH_5761VENDOR_ST_A_M45PE80:
10446                 case FLASH_5761VENDOR_ST_A_M45PE16:
10447                 case FLASH_5761VENDOR_ST_M_M45PE20:
10448                 case FLASH_5761VENDOR_ST_M_M45PE40:
10449                 case FLASH_5761VENDOR_ST_M_M45PE80:
10450                 case FLASH_5761VENDOR_ST_M_M45PE16:
10451                         tp->nvram_jedecnum = JEDEC_ST;
10452                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10453                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10454                         tp->nvram_pagesize = 256;
10455                         break;
10456         }
10457
10458         if (protect) {
10459                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10460         } else {
10461                 switch (nvcfg1) {
10462                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10463                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10464                         case FLASH_5761VENDOR_ST_A_M45PE16:
10465                         case FLASH_5761VENDOR_ST_M_M45PE16:
10466                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10467                                 break;
10468                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10469                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10470                         case FLASH_5761VENDOR_ST_A_M45PE80:
10471                         case FLASH_5761VENDOR_ST_M_M45PE80:
10472                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10473                                 break;
10474                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10475                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10476                         case FLASH_5761VENDOR_ST_A_M45PE40:
10477                         case FLASH_5761VENDOR_ST_M_M45PE40:
10478                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10479                                 break;
10480                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10481                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10482                         case FLASH_5761VENDOR_ST_A_M45PE20:
10483                         case FLASH_5761VENDOR_ST_M_M45PE20:
10484                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10485                                 break;
10486                 }
10487         }
10488 }
10489
10490 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10491 {
10492         tp->nvram_jedecnum = JEDEC_ATMEL;
10493         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10494         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10495 }
10496
10497 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10498 {
10499         u32 nvcfg1;
10500
10501         nvcfg1 = tr32(NVRAM_CFG1);
10502
10503         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10504         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10505         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10506                 tp->nvram_jedecnum = JEDEC_ATMEL;
10507                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10508                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10509
10510                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10511                 tw32(NVRAM_CFG1, nvcfg1);
10512                 return;
10513         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10514         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10515         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10516         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10517         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10518         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10519         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10520                 tp->nvram_jedecnum = JEDEC_ATMEL;
10521                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10522                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10523
10524                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10525                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10526                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10527                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10528                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10529                         break;
10530                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10531                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10532                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10533                         break;
10534                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10535                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10536                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10537                         break;
10538                 }
10539                 break;
10540         case FLASH_5752VENDOR_ST_M45PE10:
10541         case FLASH_5752VENDOR_ST_M45PE20:
10542         case FLASH_5752VENDOR_ST_M45PE40:
10543                 tp->nvram_jedecnum = JEDEC_ST;
10544                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10545                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10546
10547                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10548                 case FLASH_5752VENDOR_ST_M45PE10:
10549                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10550                         break;
10551                 case FLASH_5752VENDOR_ST_M45PE20:
10552                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10553                         break;
10554                 case FLASH_5752VENDOR_ST_M45PE40:
10555                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10556                         break;
10557                 }
10558                 break;
10559         default:
10560                 return;
10561         }
10562
10563         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10564         case FLASH_5752PAGE_SIZE_256:
10565                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10566                 tp->nvram_pagesize = 256;
10567                 break;
10568         case FLASH_5752PAGE_SIZE_512:
10569                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10570                 tp->nvram_pagesize = 512;
10571                 break;
10572         case FLASH_5752PAGE_SIZE_1K:
10573                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10574                 tp->nvram_pagesize = 1024;
10575                 break;
10576         case FLASH_5752PAGE_SIZE_2K:
10577                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10578                 tp->nvram_pagesize = 2048;
10579                 break;
10580         case FLASH_5752PAGE_SIZE_4K:
10581                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10582                 tp->nvram_pagesize = 4096;
10583                 break;
10584         case FLASH_5752PAGE_SIZE_264:
10585                 tp->nvram_pagesize = 264;
10586                 break;
10587         case FLASH_5752PAGE_SIZE_528:
10588                 tp->nvram_pagesize = 528;
10589                 break;
10590         }
10591 }
10592
10593 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10594 static void __devinit tg3_nvram_init(struct tg3 *tp)
10595 {
10596         tw32_f(GRC_EEPROM_ADDR,
10597              (EEPROM_ADDR_FSM_RESET |
10598               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10599                EEPROM_ADDR_CLKPERD_SHIFT)));
10600
10601         msleep(1);
10602
10603         /* Enable seeprom accesses. */
10604         tw32_f(GRC_LOCAL_CTRL,
10605              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10606         udelay(100);
10607
10608         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10609             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10610                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10611
10612                 if (tg3_nvram_lock(tp)) {
10613                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10614                                "tg3_nvram_init failed.\n", tp->dev->name);
10615                         return;
10616                 }
10617                 tg3_enable_nvram_access(tp);
10618
10619                 tp->nvram_size = 0;
10620
10621                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10622                         tg3_get_5752_nvram_info(tp);
10623                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10624                         tg3_get_5755_nvram_info(tp);
10625                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10626                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10627                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10628                         tg3_get_5787_nvram_info(tp);
10629                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10630                         tg3_get_5761_nvram_info(tp);
10631                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10632                         tg3_get_5906_nvram_info(tp);
10633                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10634                         tg3_get_57780_nvram_info(tp);
10635                 else
10636                         tg3_get_nvram_info(tp);
10637
10638                 if (tp->nvram_size == 0)
10639                         tg3_get_nvram_size(tp);
10640
10641                 tg3_disable_nvram_access(tp);
10642                 tg3_nvram_unlock(tp);
10643
10644         } else {
10645                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10646
10647                 tg3_get_eeprom_size(tp);
10648         }
10649 }
10650
10651 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10652                                     u32 offset, u32 len, u8 *buf)
10653 {
10654         int i, j, rc = 0;
10655         u32 val;
10656
10657         for (i = 0; i < len; i += 4) {
10658                 u32 addr;
10659                 __be32 data;
10660
10661                 addr = offset + i;
10662
10663                 memcpy(&data, buf + i, 4);
10664
10665                 tw32(GRC_EEPROM_DATA, be32_to_cpu(data));
10666
10667                 val = tr32(GRC_EEPROM_ADDR);
10668                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10669
10670                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10671                         EEPROM_ADDR_READ);
10672                 tw32(GRC_EEPROM_ADDR, val |
10673                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10674                         (addr & EEPROM_ADDR_ADDR_MASK) |
10675                         EEPROM_ADDR_START |
10676                         EEPROM_ADDR_WRITE);
10677
10678                 for (j = 0; j < 1000; j++) {
10679                         val = tr32(GRC_EEPROM_ADDR);
10680
10681                         if (val & EEPROM_ADDR_COMPLETE)
10682                                 break;
10683                         msleep(1);
10684                 }
10685                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10686                         rc = -EBUSY;
10687                         break;
10688                 }
10689         }
10690
10691         return rc;
10692 }
10693
10694 /* offset and length are dword aligned */
10695 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10696                 u8 *buf)
10697 {
10698         int ret = 0;
10699         u32 pagesize = tp->nvram_pagesize;
10700         u32 pagemask = pagesize - 1;
10701         u32 nvram_cmd;
10702         u8 *tmp;
10703
10704         tmp = kmalloc(pagesize, GFP_KERNEL);
10705         if (tmp == NULL)
10706                 return -ENOMEM;
10707
10708         while (len) {
10709                 int j;
10710                 u32 phy_addr, page_off, size;
10711
10712                 phy_addr = offset & ~pagemask;
10713
10714                 for (j = 0; j < pagesize; j += 4) {
10715                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
10716                                                   (__be32 *) (tmp + j));
10717                         if (ret)
10718                                 break;
10719                 }
10720                 if (ret)
10721                         break;
10722
10723                 page_off = offset & pagemask;
10724                 size = pagesize;
10725                 if (len < size)
10726                         size = len;
10727
10728                 len -= size;
10729
10730                 memcpy(tmp + page_off, buf, size);
10731
10732                 offset = offset + (pagesize - page_off);
10733
10734                 tg3_enable_nvram_access(tp);
10735
10736                 /*
10737                  * Before we can erase the flash page, we need
10738                  * to issue a special "write enable" command.
10739                  */
10740                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10741
10742                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10743                         break;
10744
10745                 /* Erase the target page */
10746                 tw32(NVRAM_ADDR, phy_addr);
10747
10748                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10749                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10750
10751                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10752                         break;
10753
10754                 /* Issue another write enable to start the write. */
10755                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10756
10757                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10758                         break;
10759
10760                 for (j = 0; j < pagesize; j += 4) {
10761                         __be32 data;
10762
10763                         data = *((__be32 *) (tmp + j));
10764
10765                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10766
10767                         tw32(NVRAM_ADDR, phy_addr + j);
10768
10769                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10770                                 NVRAM_CMD_WR;
10771
10772                         if (j == 0)
10773                                 nvram_cmd |= NVRAM_CMD_FIRST;
10774                         else if (j == (pagesize - 4))
10775                                 nvram_cmd |= NVRAM_CMD_LAST;
10776
10777                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10778                                 break;
10779                 }
10780                 if (ret)
10781                         break;
10782         }
10783
10784         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10785         tg3_nvram_exec_cmd(tp, nvram_cmd);
10786
10787         kfree(tmp);
10788
10789         return ret;
10790 }
10791
10792 /* offset and length are dword aligned */
10793 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10794                 u8 *buf)
10795 {
10796         int i, ret = 0;
10797
10798         for (i = 0; i < len; i += 4, offset += 4) {
10799                 u32 page_off, phy_addr, nvram_cmd;
10800                 __be32 data;
10801
10802                 memcpy(&data, buf + i, 4);
10803                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10804
10805                 page_off = offset % tp->nvram_pagesize;
10806
10807                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10808
10809                 tw32(NVRAM_ADDR, phy_addr);
10810
10811                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10812
10813                 if ((page_off == 0) || (i == 0))
10814                         nvram_cmd |= NVRAM_CMD_FIRST;
10815                 if (page_off == (tp->nvram_pagesize - 4))
10816                         nvram_cmd |= NVRAM_CMD_LAST;
10817
10818                 if (i == (len - 4))
10819                         nvram_cmd |= NVRAM_CMD_LAST;
10820
10821                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10822                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10823                     (tp->nvram_jedecnum == JEDEC_ST) &&
10824                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10825
10826                         if ((ret = tg3_nvram_exec_cmd(tp,
10827                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10828                                 NVRAM_CMD_DONE)))
10829
10830                                 break;
10831                 }
10832                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10833                         /* We always do complete word writes to eeprom. */
10834                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10835                 }
10836
10837                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10838                         break;
10839         }
10840         return ret;
10841 }
10842
10843 /* offset and length are dword aligned */
10844 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10845 {
10846         int ret;
10847
10848         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10849                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10850                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
10851                 udelay(40);
10852         }
10853
10854         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10855                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10856         }
10857         else {
10858                 u32 grc_mode;
10859
10860                 ret = tg3_nvram_lock(tp);
10861                 if (ret)
10862                         return ret;
10863
10864                 tg3_enable_nvram_access(tp);
10865                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10866                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10867                         tw32(NVRAM_WRITE1, 0x406);
10868
10869                 grc_mode = tr32(GRC_MODE);
10870                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10871
10872                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10873                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10874
10875                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
10876                                 buf);
10877                 }
10878                 else {
10879                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10880                                 buf);
10881                 }
10882
10883                 grc_mode = tr32(GRC_MODE);
10884                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10885
10886                 tg3_disable_nvram_access(tp);
10887                 tg3_nvram_unlock(tp);
10888         }
10889
10890         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10891                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10892                 udelay(40);
10893         }
10894
10895         return ret;
10896 }
10897
10898 struct subsys_tbl_ent {
10899         u16 subsys_vendor, subsys_devid;
10900         u32 phy_id;
10901 };
10902
10903 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10904         /* Broadcom boards. */
10905         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10906         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10907         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10908         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
10909         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10910         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10911         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
10912         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10913         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10914         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10915         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10916
10917         /* 3com boards. */
10918         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10919         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10920         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
10921         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10922         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10923
10924         /* DELL boards. */
10925         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10926         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10927         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10928         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10929
10930         /* Compaq boards. */
10931         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10932         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10933         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
10934         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10935         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10936
10937         /* IBM boards. */
10938         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10939 };
10940
10941 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10942 {
10943         int i;
10944
10945         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10946                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10947                      tp->pdev->subsystem_vendor) &&
10948                     (subsys_id_to_phy_id[i].subsys_devid ==
10949                      tp->pdev->subsystem_device))
10950                         return &subsys_id_to_phy_id[i];
10951         }
10952         return NULL;
10953 }
10954
10955 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10956 {
10957         u32 val;
10958         u16 pmcsr;
10959
10960         /* On some early chips the SRAM cannot be accessed in D3hot state,
10961          * so need make sure we're in D0.
10962          */
10963         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10964         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10965         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10966         msleep(1);
10967
10968         /* Make sure register accesses (indirect or otherwise)
10969          * will function correctly.
10970          */
10971         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10972                                tp->misc_host_ctrl);
10973
10974         /* The memory arbiter has to be enabled in order for SRAM accesses
10975          * to succeed.  Normally on powerup the tg3 chip firmware will make
10976          * sure it is enabled, but other entities such as system netboot
10977          * code might disable it.
10978          */
10979         val = tr32(MEMARB_MODE);
10980         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10981
10982         tp->phy_id = PHY_ID_INVALID;
10983         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10984
10985         /* Assume an onboard device and WOL capable by default.  */
10986         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10987
10988         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10989                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10990                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10991                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10992                 }
10993                 val = tr32(VCPU_CFGSHDW);
10994                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
10995                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10996                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10997                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
10998                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10999                 goto done;
11000         }
11001
11002         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11003         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11004                 u32 nic_cfg, led_cfg;
11005                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11006                 int eeprom_phy_serdes = 0;
11007
11008                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11009                 tp->nic_sram_data_cfg = nic_cfg;
11010
11011                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11012                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11013                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11014                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11015                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11016                     (ver > 0) && (ver < 0x100))
11017                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11018
11019                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11020                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11021
11022                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11023                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11024                         eeprom_phy_serdes = 1;
11025
11026                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11027                 if (nic_phy_id != 0) {
11028                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11029                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11030
11031                         eeprom_phy_id  = (id1 >> 16) << 10;
11032                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11033                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11034                 } else
11035                         eeprom_phy_id = 0;
11036
11037                 tp->phy_id = eeprom_phy_id;
11038                 if (eeprom_phy_serdes) {
11039                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11040                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11041                         else
11042                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11043                 }
11044
11045                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11046                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11047                                     SHASTA_EXT_LED_MODE_MASK);
11048                 else
11049                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11050
11051                 switch (led_cfg) {
11052                 default:
11053                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11054                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11055                         break;
11056
11057                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11058                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11059                         break;
11060
11061                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11062                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11063
11064                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11065                          * read on some older 5700/5701 bootcode.
11066                          */
11067                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11068                             ASIC_REV_5700 ||
11069                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11070                             ASIC_REV_5701)
11071                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11072
11073                         break;
11074
11075                 case SHASTA_EXT_LED_SHARED:
11076                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11077                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11078                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11079                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11080                                                  LED_CTRL_MODE_PHY_2);
11081                         break;
11082
11083                 case SHASTA_EXT_LED_MAC:
11084                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11085                         break;
11086
11087                 case SHASTA_EXT_LED_COMBO:
11088                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11089                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11090                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11091                                                  LED_CTRL_MODE_PHY_2);
11092                         break;
11093
11094                 }
11095
11096                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11097                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11098                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11099                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11100
11101                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11102                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11103
11104                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11105                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11106                         if ((tp->pdev->subsystem_vendor ==
11107                              PCI_VENDOR_ID_ARIMA) &&
11108                             (tp->pdev->subsystem_device == 0x205a ||
11109                              tp->pdev->subsystem_device == 0x2063))
11110                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11111                 } else {
11112                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11113                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11114                 }
11115
11116                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11117                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11118                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11119                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11120                 }
11121
11122                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11123                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11124                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11125
11126                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11127                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11128                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11129
11130                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11131                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11132                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11133
11134                 if (cfg2 & (1 << 17))
11135                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11136
11137                 /* serdes signal pre-emphasis in register 0x590 set by */
11138                 /* bootcode if bit 18 is set */
11139                 if (cfg2 & (1 << 18))
11140                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11141
11142                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11143                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11144                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11145                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11146
11147                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11148                         u32 cfg3;
11149
11150                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11151                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11152                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11153                 }
11154
11155                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11156                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11157                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11158                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11159                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11160                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11161         }
11162 done:
11163         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11164         device_set_wakeup_enable(&tp->pdev->dev,
11165                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11166 }
11167
11168 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11169 {
11170         int i;
11171         u32 val;
11172
11173         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11174         tw32(OTP_CTRL, cmd);
11175
11176         /* Wait for up to 1 ms for command to execute. */
11177         for (i = 0; i < 100; i++) {
11178                 val = tr32(OTP_STATUS);
11179                 if (val & OTP_STATUS_CMD_DONE)
11180                         break;
11181                 udelay(10);
11182         }
11183
11184         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11185 }
11186
11187 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11188  * configuration is a 32-bit value that straddles the alignment boundary.
11189  * We do two 32-bit reads and then shift and merge the results.
11190  */
11191 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11192 {
11193         u32 bhalf_otp, thalf_otp;
11194
11195         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11196
11197         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11198                 return 0;
11199
11200         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11201
11202         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11203                 return 0;
11204
11205         thalf_otp = tr32(OTP_READ_DATA);
11206
11207         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11208
11209         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11210                 return 0;
11211
11212         bhalf_otp = tr32(OTP_READ_DATA);
11213
11214         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11215 }
11216
11217 static int __devinit tg3_phy_probe(struct tg3 *tp)
11218 {
11219         u32 hw_phy_id_1, hw_phy_id_2;
11220         u32 hw_phy_id, hw_phy_id_masked;
11221         int err;
11222
11223         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11224                 return tg3_phy_init(tp);
11225
11226         /* Reading the PHY ID register can conflict with ASF
11227          * firwmare access to the PHY hardware.
11228          */
11229         err = 0;
11230         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11231             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11232                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11233         } else {
11234                 /* Now read the physical PHY_ID from the chip and verify
11235                  * that it is sane.  If it doesn't look good, we fall back
11236                  * to either the hard-coded table based PHY_ID and failing
11237                  * that the value found in the eeprom area.
11238                  */
11239                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11240                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11241
11242                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11243                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11244                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11245
11246                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11247         }
11248
11249         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11250                 tp->phy_id = hw_phy_id;
11251                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11252                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11253                 else
11254                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11255         } else {
11256                 if (tp->phy_id != PHY_ID_INVALID) {
11257                         /* Do nothing, phy ID already set up in
11258                          * tg3_get_eeprom_hw_cfg().
11259                          */
11260                 } else {
11261                         struct subsys_tbl_ent *p;
11262
11263                         /* No eeprom signature?  Try the hardcoded
11264                          * subsys device table.
11265                          */
11266                         p = lookup_by_subsys(tp);
11267                         if (!p)
11268                                 return -ENODEV;
11269
11270                         tp->phy_id = p->phy_id;
11271                         if (!tp->phy_id ||
11272                             tp->phy_id == PHY_ID_BCM8002)
11273                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11274                 }
11275         }
11276
11277         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11278             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11279             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11280                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11281
11282                 tg3_readphy(tp, MII_BMSR, &bmsr);
11283                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11284                     (bmsr & BMSR_LSTATUS))
11285                         goto skip_phy_reset;
11286
11287                 err = tg3_phy_reset(tp);
11288                 if (err)
11289                         return err;
11290
11291                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11292                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11293                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11294                 tg3_ctrl = 0;
11295                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11296                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11297                                     MII_TG3_CTRL_ADV_1000_FULL);
11298                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11299                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11300                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11301                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11302                 }
11303
11304                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11305                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11306                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11307                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11308                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11309
11310                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11311                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11312
11313                         tg3_writephy(tp, MII_BMCR,
11314                                      BMCR_ANENABLE | BMCR_ANRESTART);
11315                 }
11316                 tg3_phy_set_wirespeed(tp);
11317
11318                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11319                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11320                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11321         }
11322
11323 skip_phy_reset:
11324         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11325                 err = tg3_init_5401phy_dsp(tp);
11326                 if (err)
11327                         return err;
11328         }
11329
11330         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11331                 err = tg3_init_5401phy_dsp(tp);
11332         }
11333
11334         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11335                 tp->link_config.advertising =
11336                         (ADVERTISED_1000baseT_Half |
11337                          ADVERTISED_1000baseT_Full |
11338                          ADVERTISED_Autoneg |
11339                          ADVERTISED_FIBRE);
11340         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11341                 tp->link_config.advertising &=
11342                         ~(ADVERTISED_1000baseT_Half |
11343                           ADVERTISED_1000baseT_Full);
11344
11345         return err;
11346 }
11347
11348 static void __devinit tg3_read_partno(struct tg3 *tp)
11349 {
11350         unsigned char vpd_data[256];
11351         unsigned int i;
11352         u32 magic;
11353
11354         if (tg3_nvram_read(tp, 0x0, &magic))
11355                 goto out_not_found;
11356
11357         if (magic == TG3_EEPROM_MAGIC) {
11358                 for (i = 0; i < 256; i += 4) {
11359                         u32 tmp;
11360
11361                         if (tg3_nvram_read_swab(tp, 0x100 + i, &tmp))
11362                                 goto out_not_found;
11363
11364                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
11365                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
11366                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11367                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11368                 }
11369         } else {
11370                 int vpd_cap;
11371
11372                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11373                 for (i = 0; i < 256; i += 4) {
11374                         u32 tmp, j = 0;
11375                         __le32 v;
11376                         u16 tmp16;
11377
11378                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11379                                               i);
11380                         while (j++ < 100) {
11381                                 pci_read_config_word(tp->pdev, vpd_cap +
11382                                                      PCI_VPD_ADDR, &tmp16);
11383                                 if (tmp16 & 0x8000)
11384                                         break;
11385                                 msleep(1);
11386                         }
11387                         if (!(tmp16 & 0x8000))
11388                                 goto out_not_found;
11389
11390                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11391                                               &tmp);
11392                         v = cpu_to_le32(tmp);
11393                         memcpy(&vpd_data[i], &v, 4);
11394                 }
11395         }
11396
11397         /* Now parse and find the part number. */
11398         for (i = 0; i < 254; ) {
11399                 unsigned char val = vpd_data[i];
11400                 unsigned int block_end;
11401
11402                 if (val == 0x82 || val == 0x91) {
11403                         i = (i + 3 +
11404                              (vpd_data[i + 1] +
11405                               (vpd_data[i + 2] << 8)));
11406                         continue;
11407                 }
11408
11409                 if (val != 0x90)
11410                         goto out_not_found;
11411
11412                 block_end = (i + 3 +
11413                              (vpd_data[i + 1] +
11414                               (vpd_data[i + 2] << 8)));
11415                 i += 3;
11416
11417                 if (block_end > 256)
11418                         goto out_not_found;
11419
11420                 while (i < (block_end - 2)) {
11421                         if (vpd_data[i + 0] == 'P' &&
11422                             vpd_data[i + 1] == 'N') {
11423                                 int partno_len = vpd_data[i + 2];
11424
11425                                 i += 3;
11426                                 if (partno_len > 24 || (partno_len + i) > 256)
11427                                         goto out_not_found;
11428
11429                                 memcpy(tp->board_part_number,
11430                                        &vpd_data[i], partno_len);
11431
11432                                 /* Success. */
11433                                 return;
11434                         }
11435                         i += 3 + vpd_data[i + 2];
11436                 }
11437
11438                 /* Part number not found. */
11439                 goto out_not_found;
11440         }
11441
11442 out_not_found:
11443         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11444                 strcpy(tp->board_part_number, "BCM95906");
11445         else
11446                 strcpy(tp->board_part_number, "none");
11447 }
11448
11449 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11450 {
11451         u32 val;
11452
11453         if (tg3_nvram_read(tp, offset, &val) ||
11454             (val & 0xfc000000) != 0x0c000000 ||
11455             tg3_nvram_read(tp, offset + 4, &val) ||
11456             val != 0)
11457                 return 0;
11458
11459         return 1;
11460 }
11461
11462 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11463 {
11464         u32 offset, major, minor, build;
11465
11466         tp->fw_ver[0] = 's';
11467         tp->fw_ver[1] = 'b';
11468         tp->fw_ver[2] = '\0';
11469
11470         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11471                 return;
11472
11473         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11474         case TG3_EEPROM_SB_REVISION_0:
11475                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11476                 break;
11477         case TG3_EEPROM_SB_REVISION_2:
11478                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11479                 break;
11480         case TG3_EEPROM_SB_REVISION_3:
11481                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11482                 break;
11483         default:
11484                 return;
11485         }
11486
11487         if (tg3_nvram_read(tp, offset, &val))
11488                 return;
11489
11490         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11491                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11492         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11493                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11494         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11495
11496         if (minor > 99 || build > 26)
11497                 return;
11498
11499         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11500
11501         if (build > 0) {
11502                 tp->fw_ver[8] = 'a' + build - 1;
11503                 tp->fw_ver[9] = '\0';
11504         }
11505 }
11506
11507 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11508 {
11509         u32 val, offset, start;
11510         u32 ver_offset;
11511         int i, bcnt;
11512
11513         if (tg3_nvram_read(tp, 0, &val))
11514                 return;
11515
11516         if (val != TG3_EEPROM_MAGIC) {
11517                 if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11518                         tg3_read_sb_ver(tp, val);
11519
11520                 return;
11521         }
11522
11523         if (tg3_nvram_read(tp, 0xc, &offset) ||
11524             tg3_nvram_read(tp, 0x4, &start))
11525                 return;
11526
11527         offset = tg3_nvram_logical_addr(tp, offset);
11528
11529         if (!tg3_fw_img_is_valid(tp, offset) ||
11530             tg3_nvram_read(tp, offset + 8, &ver_offset))
11531                 return;
11532
11533         offset = offset + ver_offset - start;
11534         for (i = 0; i < 16; i += 4) {
11535                 __be32 v;
11536                 if (tg3_nvram_read_be32(tp, offset + i, &v))
11537                         return;
11538
11539                 memcpy(tp->fw_ver + i, &v, 4);
11540         }
11541
11542         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11543              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11544                 return;
11545
11546         for (offset = TG3_NVM_DIR_START;
11547              offset < TG3_NVM_DIR_END;
11548              offset += TG3_NVM_DIRENT_SIZE) {
11549                 if (tg3_nvram_read(tp, offset, &val))
11550                         return;
11551
11552                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11553                         break;
11554         }
11555
11556         if (offset == TG3_NVM_DIR_END)
11557                 return;
11558
11559         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11560                 start = 0x08000000;
11561         else if (tg3_nvram_read(tp, offset - 4, &start))
11562                 return;
11563
11564         if (tg3_nvram_read(tp, offset + 4, &offset) ||
11565             !tg3_fw_img_is_valid(tp, offset) ||
11566             tg3_nvram_read(tp, offset + 8, &val))
11567                 return;
11568
11569         offset += val - start;
11570
11571         bcnt = strlen(tp->fw_ver);
11572
11573         tp->fw_ver[bcnt++] = ',';
11574         tp->fw_ver[bcnt++] = ' ';
11575
11576         for (i = 0; i < 4; i++) {
11577                 __be32 v;
11578                 if (tg3_nvram_read_be32(tp, offset, &v))
11579                         return;
11580
11581                 offset += sizeof(v);
11582
11583                 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11584                         memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11585                         break;
11586                 }
11587
11588                 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11589                 bcnt += sizeof(v);
11590         }
11591
11592         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11593 }
11594
11595 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11596
11597 static int __devinit tg3_get_invariants(struct tg3 *tp)
11598 {
11599         static struct pci_device_id write_reorder_chipsets[] = {
11600                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11601                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11602                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11603                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11604                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11605                              PCI_DEVICE_ID_VIA_8385_0) },
11606                 { },
11607         };
11608         u32 misc_ctrl_reg;
11609         u32 pci_state_reg, grc_misc_cfg;
11610         u32 val;
11611         u16 pci_cmd;
11612         int err;
11613
11614         /* Force memory write invalidate off.  If we leave it on,
11615          * then on 5700_BX chips we have to enable a workaround.
11616          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11617          * to match the cacheline size.  The Broadcom driver have this
11618          * workaround but turns MWI off all the times so never uses
11619          * it.  This seems to suggest that the workaround is insufficient.
11620          */
11621         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11622         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11623         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11624
11625         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11626          * has the register indirect write enable bit set before
11627          * we try to access any of the MMIO registers.  It is also
11628          * critical that the PCI-X hw workaround situation is decided
11629          * before that as well.
11630          */
11631         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11632                               &misc_ctrl_reg);
11633
11634         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11635                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11636         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11637                 u32 prod_id_asic_rev;
11638
11639                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11640                                       &prod_id_asic_rev);
11641                 tp->pci_chip_rev_id = prod_id_asic_rev;
11642         }
11643
11644         /* Wrong chip ID in 5752 A0. This code can be removed later
11645          * as A0 is not in production.
11646          */
11647         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11648                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11649
11650         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11651          * we need to disable memory and use config. cycles
11652          * only to access all registers. The 5702/03 chips
11653          * can mistakenly decode the special cycles from the
11654          * ICH chipsets as memory write cycles, causing corruption
11655          * of register and memory space. Only certain ICH bridges
11656          * will drive special cycles with non-zero data during the
11657          * address phase which can fall within the 5703's address
11658          * range. This is not an ICH bug as the PCI spec allows
11659          * non-zero address during special cycles. However, only
11660          * these ICH bridges are known to drive non-zero addresses
11661          * during special cycles.
11662          *
11663          * Since special cycles do not cross PCI bridges, we only
11664          * enable this workaround if the 5703 is on the secondary
11665          * bus of these ICH bridges.
11666          */
11667         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11668             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11669                 static struct tg3_dev_id {
11670                         u32     vendor;
11671                         u32     device;
11672                         u32     rev;
11673                 } ich_chipsets[] = {
11674                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11675                           PCI_ANY_ID },
11676                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11677                           PCI_ANY_ID },
11678                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11679                           0xa },
11680                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11681                           PCI_ANY_ID },
11682                         { },
11683                 };
11684                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11685                 struct pci_dev *bridge = NULL;
11686
11687                 while (pci_id->vendor != 0) {
11688                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11689                                                 bridge);
11690                         if (!bridge) {
11691                                 pci_id++;
11692                                 continue;
11693                         }
11694                         if (pci_id->rev != PCI_ANY_ID) {
11695                                 if (bridge->revision > pci_id->rev)
11696                                         continue;
11697                         }
11698                         if (bridge->subordinate &&
11699                             (bridge->subordinate->number ==
11700                              tp->pdev->bus->number)) {
11701
11702                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11703                                 pci_dev_put(bridge);
11704                                 break;
11705                         }
11706                 }
11707         }
11708
11709         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11710                 static struct tg3_dev_id {
11711                         u32     vendor;
11712                         u32     device;
11713                 } bridge_chipsets[] = {
11714                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11715                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11716                         { },
11717                 };
11718                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11719                 struct pci_dev *bridge = NULL;
11720
11721                 while (pci_id->vendor != 0) {
11722                         bridge = pci_get_device(pci_id->vendor,
11723                                                 pci_id->device,
11724                                                 bridge);
11725                         if (!bridge) {
11726                                 pci_id++;
11727                                 continue;
11728                         }
11729                         if (bridge->subordinate &&
11730                             (bridge->subordinate->number <=
11731                              tp->pdev->bus->number) &&
11732                             (bridge->subordinate->subordinate >=
11733                              tp->pdev->bus->number)) {
11734                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11735                                 pci_dev_put(bridge);
11736                                 break;
11737                         }
11738                 }
11739         }
11740
11741         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11742          * DMA addresses > 40-bit. This bridge may have other additional
11743          * 57xx devices behind it in some 4-port NIC designs for example.
11744          * Any tg3 device found behind the bridge will also need the 40-bit
11745          * DMA workaround.
11746          */
11747         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11748             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11749                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11750                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11751                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11752         }
11753         else {
11754                 struct pci_dev *bridge = NULL;
11755
11756                 do {
11757                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11758                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11759                                                 bridge);
11760                         if (bridge && bridge->subordinate &&
11761                             (bridge->subordinate->number <=
11762                              tp->pdev->bus->number) &&
11763                             (bridge->subordinate->subordinate >=
11764                              tp->pdev->bus->number)) {
11765                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11766                                 pci_dev_put(bridge);
11767                                 break;
11768                         }
11769                 } while (bridge);
11770         }
11771
11772         /* Initialize misc host control in PCI block. */
11773         tp->misc_host_ctrl |= (misc_ctrl_reg &
11774                                MISC_HOST_CTRL_CHIPREV);
11775         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11776                                tp->misc_host_ctrl);
11777
11778         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11779             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11780                 tp->pdev_peer = tg3_find_peer(tp);
11781
11782         /* Intentionally exclude ASIC_REV_5906 */
11783         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11784             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11785             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11786             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11787             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11788             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11789                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11790
11791         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11792             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11793             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11794             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11795             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11796                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11797
11798         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11799             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11800                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11801
11802         /* 5700 B0 chips do not support checksumming correctly due
11803          * to hardware bugs.
11804          */
11805         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11806                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11807         else {
11808                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11809                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11810                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11811                         tp->dev->features |= NETIF_F_IPV6_CSUM;
11812         }
11813
11814         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11815                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11816                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11817                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11818                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11819                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11820                      tp->pdev_peer == tp->pdev))
11821                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11822
11823                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11824                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11825                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11826                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11827                 } else {
11828                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11829                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11830                                 ASIC_REV_5750 &&
11831                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11832                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11833                 }
11834         }
11835
11836         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11837              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11838                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11839
11840         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11841                               &pci_state_reg);
11842
11843         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11844         if (tp->pcie_cap != 0) {
11845                 u16 lnkctl;
11846
11847                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11848
11849                 pcie_set_readrq(tp->pdev, 4096);
11850
11851                 pci_read_config_word(tp->pdev,
11852                                      tp->pcie_cap + PCI_EXP_LNKCTL,
11853                                      &lnkctl);
11854                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11855                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11856                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11857                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11858                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11859                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11860                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
11861                 }
11862         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
11863                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11864         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11865                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11866                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11867                 if (!tp->pcix_cap) {
11868                         printk(KERN_ERR PFX "Cannot find PCI-X "
11869                                             "capability, aborting.\n");
11870                         return -EIO;
11871                 }
11872
11873                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
11874                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11875         }
11876
11877         /* If we have an AMD 762 or VIA K8T800 chipset, write
11878          * reordering to the mailbox registers done by the host
11879          * controller can cause major troubles.  We read back from
11880          * every mailbox register write to force the writes to be
11881          * posted to the chip in order.
11882          */
11883         if (pci_dev_present(write_reorder_chipsets) &&
11884             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11885                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11886
11887         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
11888                              &tp->pci_cacheline_sz);
11889         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11890                              &tp->pci_lat_timer);
11891         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11892             tp->pci_lat_timer < 64) {
11893                 tp->pci_lat_timer = 64;
11894                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11895                                       tp->pci_lat_timer);
11896         }
11897
11898         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11899                 /* 5700 BX chips need to have their TX producer index
11900                  * mailboxes written twice to workaround a bug.
11901                  */
11902                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11903
11904                 /* If we are in PCI-X mode, enable register write workaround.
11905                  *
11906                  * The workaround is to use indirect register accesses
11907                  * for all chip writes not to mailbox registers.
11908                  */
11909                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11910                         u32 pm_reg;
11911
11912                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11913
11914                         /* The chip can have it's power management PCI config
11915                          * space registers clobbered due to this bug.
11916                          * So explicitly force the chip into D0 here.
11917                          */
11918                         pci_read_config_dword(tp->pdev,
11919                                               tp->pm_cap + PCI_PM_CTRL,
11920                                               &pm_reg);
11921                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11922                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
11923                         pci_write_config_dword(tp->pdev,
11924                                                tp->pm_cap + PCI_PM_CTRL,
11925                                                pm_reg);
11926
11927                         /* Also, force SERR#/PERR# in PCI command. */
11928                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11929                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11930                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11931                 }
11932         }
11933
11934         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11935                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11936         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11937                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11938
11939         /* Chip-specific fixup from Broadcom driver */
11940         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11941             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11942                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11943                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11944         }
11945
11946         /* Default fast path register access methods */
11947         tp->read32 = tg3_read32;
11948         tp->write32 = tg3_write32;
11949         tp->read32_mbox = tg3_read32;
11950         tp->write32_mbox = tg3_write32;
11951         tp->write32_tx_mbox = tg3_write32;
11952         tp->write32_rx_mbox = tg3_write32;
11953
11954         /* Various workaround register access methods */
11955         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11956                 tp->write32 = tg3_write_indirect_reg32;
11957         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11958                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11959                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11960                 /*
11961                  * Back to back register writes can cause problems on these
11962                  * chips, the workaround is to read back all reg writes
11963                  * except those to mailbox regs.
11964                  *
11965                  * See tg3_write_indirect_reg32().
11966                  */
11967                 tp->write32 = tg3_write_flush_reg32;
11968         }
11969
11970
11971         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11972             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11973                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11974                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11975                         tp->write32_rx_mbox = tg3_write_flush_reg32;
11976         }
11977
11978         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11979                 tp->read32 = tg3_read_indirect_reg32;
11980                 tp->write32 = tg3_write_indirect_reg32;
11981                 tp->read32_mbox = tg3_read_indirect_mbox;
11982                 tp->write32_mbox = tg3_write_indirect_mbox;
11983                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11984                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11985
11986                 iounmap(tp->regs);
11987                 tp->regs = NULL;
11988
11989                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11990                 pci_cmd &= ~PCI_COMMAND_MEMORY;
11991                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11992         }
11993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11994                 tp->read32_mbox = tg3_read32_mbox_5906;
11995                 tp->write32_mbox = tg3_write32_mbox_5906;
11996                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11997                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11998         }
11999
12000         if (tp->write32 == tg3_write_indirect_reg32 ||
12001             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12002              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12003               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12004                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12005
12006         /* Get eeprom hw config before calling tg3_set_power_state().
12007          * In particular, the TG3_FLG2_IS_NIC flag must be
12008          * determined before calling tg3_set_power_state() so that
12009          * we know whether or not to switch out of Vaux power.
12010          * When the flag is set, it means that GPIO1 is used for eeprom
12011          * write protect and also implies that it is a LOM where GPIOs
12012          * are not used to switch power.
12013          */
12014         tg3_get_eeprom_hw_cfg(tp);
12015
12016         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12017                 /* Allow reads and writes to the
12018                  * APE register and memory space.
12019                  */
12020                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12021                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12022                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12023                                        pci_state_reg);
12024         }
12025
12026         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12027             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12030                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12031
12032         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12033          * GPIO1 driven high will bring 5700's external PHY out of reset.
12034          * It is also used as eeprom write protect on LOMs.
12035          */
12036         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12037         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12038             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12039                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12040                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12041         /* Unused GPIO3 must be driven as output on 5752 because there
12042          * are no pull-up resistors on unused GPIO pins.
12043          */
12044         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12045                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12046
12047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12048             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12049                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12050
12051         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12052                 /* Turn off the debug UART. */
12053                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12054                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12055                         /* Keep VMain power. */
12056                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12057                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12058         }
12059
12060         /* Force the chip into D0. */
12061         err = tg3_set_power_state(tp, PCI_D0);
12062         if (err) {
12063                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12064                        pci_name(tp->pdev));
12065                 return err;
12066         }
12067
12068         /* Derive initial jumbo mode from MTU assigned in
12069          * ether_setup() via the alloc_etherdev() call
12070          */
12071         if (tp->dev->mtu > ETH_DATA_LEN &&
12072             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12073                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12074
12075         /* Determine WakeOnLan speed to use. */
12076         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12077             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12078             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12079             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12080                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12081         } else {
12082                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12083         }
12084
12085         /* A few boards don't want Ethernet@WireSpeed phy feature */
12086         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12087             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12088              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12089              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12090             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12091             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12092                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12093
12094         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12095             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12096                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12097         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12098                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12099
12100         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12101             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12102             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12103             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12104                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12105                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12106                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12107                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12108                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12109                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12110                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12111                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12112                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12113                 } else
12114                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12115         }
12116
12117         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12118             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12119                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12120                 if (tp->phy_otp == 0)
12121                         tp->phy_otp = TG3_OTP_DEFAULT;
12122         }
12123
12124         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12125                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12126         else
12127                 tp->mi_mode = MAC_MI_MODE_BASE;
12128
12129         tp->coalesce_mode = 0;
12130         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12131             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12132                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12133
12134         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12135             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12136                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12137
12138         err = tg3_mdio_init(tp);
12139         if (err)
12140                 return err;
12141
12142         /* Initialize data/descriptor byte/word swapping. */
12143         val = tr32(GRC_MODE);
12144         val &= GRC_MODE_HOST_STACKUP;
12145         tw32(GRC_MODE, val | tp->grc_mode);
12146
12147         tg3_switch_clocks(tp);
12148
12149         /* Clear this out for sanity. */
12150         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12151
12152         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12153                               &pci_state_reg);
12154         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12155             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12156                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12157
12158                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12159                     chiprevid == CHIPREV_ID_5701_B0 ||
12160                     chiprevid == CHIPREV_ID_5701_B2 ||
12161                     chiprevid == CHIPREV_ID_5701_B5) {
12162                         void __iomem *sram_base;
12163
12164                         /* Write some dummy words into the SRAM status block
12165                          * area, see if it reads back correctly.  If the return
12166                          * value is bad, force enable the PCIX workaround.
12167                          */
12168                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12169
12170                         writel(0x00000000, sram_base);
12171                         writel(0x00000000, sram_base + 4);
12172                         writel(0xffffffff, sram_base + 4);
12173                         if (readl(sram_base) != 0x00000000)
12174                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12175                 }
12176         }
12177
12178         udelay(50);
12179         tg3_nvram_init(tp);
12180
12181         grc_misc_cfg = tr32(GRC_MISC_CFG);
12182         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12183
12184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12185             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12186              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12187                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12188
12189         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12190             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12191                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12192         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12193                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12194                                       HOSTCC_MODE_CLRTICK_TXBD);
12195
12196                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12197                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12198                                        tp->misc_host_ctrl);
12199         }
12200
12201         /* Preserve the APE MAC_MODE bits */
12202         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12203                 tp->mac_mode = tr32(MAC_MODE) |
12204                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12205         else
12206                 tp->mac_mode = TG3_DEF_MAC_MODE;
12207
12208         /* these are limited to 10/100 only */
12209         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12210              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12211             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12212              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12213              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12214               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12215               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12216             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12217              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12218               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12219               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12220             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12221             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12222                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12223
12224         err = tg3_phy_probe(tp);
12225         if (err) {
12226                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12227                        pci_name(tp->pdev), err);
12228                 /* ... but do not return immediately ... */
12229                 tg3_mdio_fini(tp);
12230         }
12231
12232         tg3_read_partno(tp);
12233         tg3_read_fw_ver(tp);
12234
12235         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12236                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12237         } else {
12238                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12239                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12240                 else
12241                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12242         }
12243
12244         /* 5700 {AX,BX} chips have a broken status block link
12245          * change bit implementation, so we must use the
12246          * status register in those cases.
12247          */
12248         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12249                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12250         else
12251                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12252
12253         /* The led_ctrl is set during tg3_phy_probe, here we might
12254          * have to force the link status polling mechanism based
12255          * upon subsystem IDs.
12256          */
12257         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12258             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12259             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12260                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12261                                   TG3_FLAG_USE_LINKCHG_REG);
12262         }
12263
12264         /* For all SERDES we poll the MAC status register. */
12265         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12266                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12267         else
12268                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12269
12270         tp->rx_offset = NET_IP_ALIGN;
12271         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12272             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12273                 tp->rx_offset = 0;
12274
12275         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12276
12277         /* Increment the rx prod index on the rx std ring by at most
12278          * 8 for these chips to workaround hw errata.
12279          */
12280         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12281             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12282             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12283                 tp->rx_std_max_post = 8;
12284
12285         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12286                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12287                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12288
12289         return err;
12290 }
12291
12292 #ifdef CONFIG_SPARC
12293 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12294 {
12295         struct net_device *dev = tp->dev;
12296         struct pci_dev *pdev = tp->pdev;
12297         struct device_node *dp = pci_device_to_OF_node(pdev);
12298         const unsigned char *addr;
12299         int len;
12300
12301         addr = of_get_property(dp, "local-mac-address", &len);
12302         if (addr && len == 6) {
12303                 memcpy(dev->dev_addr, addr, 6);
12304                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12305                 return 0;
12306         }
12307         return -ENODEV;
12308 }
12309
12310 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12311 {
12312         struct net_device *dev = tp->dev;
12313
12314         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12315         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12316         return 0;
12317 }
12318 #endif
12319
12320 static int __devinit tg3_get_device_address(struct tg3 *tp)
12321 {
12322         struct net_device *dev = tp->dev;
12323         u32 hi, lo, mac_offset;
12324         int addr_ok = 0;
12325
12326 #ifdef CONFIG_SPARC
12327         if (!tg3_get_macaddr_sparc(tp))
12328                 return 0;
12329 #endif
12330
12331         mac_offset = 0x7c;
12332         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12333             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12334                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12335                         mac_offset = 0xcc;
12336                 if (tg3_nvram_lock(tp))
12337                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12338                 else
12339                         tg3_nvram_unlock(tp);
12340         }
12341         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12342                 mac_offset = 0x10;
12343
12344         /* First try to get it from MAC address mailbox. */
12345         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12346         if ((hi >> 16) == 0x484b) {
12347                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12348                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12349
12350                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12351                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12352                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12353                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12354                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12355
12356                 /* Some old bootcode may report a 0 MAC address in SRAM */
12357                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12358         }
12359         if (!addr_ok) {
12360                 /* Next, try NVRAM. */
12361                 if (!tg3_nvram_read_swab(tp, mac_offset + 0, &hi) &&
12362                     !tg3_nvram_read_swab(tp, mac_offset + 4, &lo)) {
12363                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
12364                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
12365                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
12366                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
12367                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
12368                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
12369                 }
12370                 /* Finally just fetch it out of the MAC control regs. */
12371                 else {
12372                         hi = tr32(MAC_ADDR_0_HIGH);
12373                         lo = tr32(MAC_ADDR_0_LOW);
12374
12375                         dev->dev_addr[5] = lo & 0xff;
12376                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12377                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12378                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12379                         dev->dev_addr[1] = hi & 0xff;
12380                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12381                 }
12382         }
12383
12384         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12385 #ifdef CONFIG_SPARC
12386                 if (!tg3_get_default_macaddr_sparc(tp))
12387                         return 0;
12388 #endif
12389                 return -EINVAL;
12390         }
12391         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12392         return 0;
12393 }
12394
12395 #define BOUNDARY_SINGLE_CACHELINE       1
12396 #define BOUNDARY_MULTI_CACHELINE        2
12397
12398 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12399 {
12400         int cacheline_size;
12401         u8 byte;
12402         int goal;
12403
12404         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12405         if (byte == 0)
12406                 cacheline_size = 1024;
12407         else
12408                 cacheline_size = (int) byte * 4;
12409
12410         /* On 5703 and later chips, the boundary bits have no
12411          * effect.
12412          */
12413         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12414             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12415             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12416                 goto out;
12417
12418 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12419         goal = BOUNDARY_MULTI_CACHELINE;
12420 #else
12421 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12422         goal = BOUNDARY_SINGLE_CACHELINE;
12423 #else
12424         goal = 0;
12425 #endif
12426 #endif
12427
12428         if (!goal)
12429                 goto out;
12430
12431         /* PCI controllers on most RISC systems tend to disconnect
12432          * when a device tries to burst across a cache-line boundary.
12433          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12434          *
12435          * Unfortunately, for PCI-E there are only limited
12436          * write-side controls for this, and thus for reads
12437          * we will still get the disconnects.  We'll also waste
12438          * these PCI cycles for both read and write for chips
12439          * other than 5700 and 5701 which do not implement the
12440          * boundary bits.
12441          */
12442         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12443             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12444                 switch (cacheline_size) {
12445                 case 16:
12446                 case 32:
12447                 case 64:
12448                 case 128:
12449                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12450                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12451                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12452                         } else {
12453                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12454                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12455                         }
12456                         break;
12457
12458                 case 256:
12459                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12460                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12461                         break;
12462
12463                 default:
12464                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12465                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12466                         break;
12467                 }
12468         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12469                 switch (cacheline_size) {
12470                 case 16:
12471                 case 32:
12472                 case 64:
12473                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12474                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12475                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12476                                 break;
12477                         }
12478                         /* fallthrough */
12479                 case 128:
12480                 default:
12481                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12482                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12483                         break;
12484                 }
12485         } else {
12486                 switch (cacheline_size) {
12487                 case 16:
12488                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12489                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12490                                         DMA_RWCTRL_WRITE_BNDRY_16);
12491                                 break;
12492                         }
12493                         /* fallthrough */
12494                 case 32:
12495                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12496                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12497                                         DMA_RWCTRL_WRITE_BNDRY_32);
12498                                 break;
12499                         }
12500                         /* fallthrough */
12501                 case 64:
12502                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12503                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12504                                         DMA_RWCTRL_WRITE_BNDRY_64);
12505                                 break;
12506                         }
12507                         /* fallthrough */
12508                 case 128:
12509                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12510                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12511                                         DMA_RWCTRL_WRITE_BNDRY_128);
12512                                 break;
12513                         }
12514                         /* fallthrough */
12515                 case 256:
12516                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12517                                 DMA_RWCTRL_WRITE_BNDRY_256);
12518                         break;
12519                 case 512:
12520                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12521                                 DMA_RWCTRL_WRITE_BNDRY_512);
12522                         break;
12523                 case 1024:
12524                 default:
12525                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12526                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12527                         break;
12528                 }
12529         }
12530
12531 out:
12532         return val;
12533 }
12534
12535 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12536 {
12537         struct tg3_internal_buffer_desc test_desc;
12538         u32 sram_dma_descs;
12539         int i, ret;
12540
12541         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12542
12543         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12544         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12545         tw32(RDMAC_STATUS, 0);
12546         tw32(WDMAC_STATUS, 0);
12547
12548         tw32(BUFMGR_MODE, 0);
12549         tw32(FTQ_RESET, 0);
12550
12551         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12552         test_desc.addr_lo = buf_dma & 0xffffffff;
12553         test_desc.nic_mbuf = 0x00002100;
12554         test_desc.len = size;
12555
12556         /*
12557          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12558          * the *second* time the tg3 driver was getting loaded after an
12559          * initial scan.
12560          *
12561          * Broadcom tells me:
12562          *   ...the DMA engine is connected to the GRC block and a DMA
12563          *   reset may affect the GRC block in some unpredictable way...
12564          *   The behavior of resets to individual blocks has not been tested.
12565          *
12566          * Broadcom noted the GRC reset will also reset all sub-components.
12567          */
12568         if (to_device) {
12569                 test_desc.cqid_sqid = (13 << 8) | 2;
12570
12571                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12572                 udelay(40);
12573         } else {
12574                 test_desc.cqid_sqid = (16 << 8) | 7;
12575
12576                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12577                 udelay(40);
12578         }
12579         test_desc.flags = 0x00000005;
12580
12581         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12582                 u32 val;
12583
12584                 val = *(((u32 *)&test_desc) + i);
12585                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12586                                        sram_dma_descs + (i * sizeof(u32)));
12587                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12588         }
12589         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12590
12591         if (to_device) {
12592                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12593         } else {
12594                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12595         }
12596
12597         ret = -ENODEV;
12598         for (i = 0; i < 40; i++) {
12599                 u32 val;
12600
12601                 if (to_device)
12602                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12603                 else
12604                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12605                 if ((val & 0xffff) == sram_dma_descs) {
12606                         ret = 0;
12607                         break;
12608                 }
12609
12610                 udelay(100);
12611         }
12612
12613         return ret;
12614 }
12615
12616 #define TEST_BUFFER_SIZE        0x2000
12617
12618 static int __devinit tg3_test_dma(struct tg3 *tp)
12619 {
12620         dma_addr_t buf_dma;
12621         u32 *buf, saved_dma_rwctrl;
12622         int ret;
12623
12624         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12625         if (!buf) {
12626                 ret = -ENOMEM;
12627                 goto out_nofree;
12628         }
12629
12630         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12631                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12632
12633         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12634
12635         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12636                 /* DMA read watermark not used on PCIE */
12637                 tp->dma_rwctrl |= 0x00180000;
12638         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12639                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12640                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12641                         tp->dma_rwctrl |= 0x003f0000;
12642                 else
12643                         tp->dma_rwctrl |= 0x003f000f;
12644         } else {
12645                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12646                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12647                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12648                         u32 read_water = 0x7;
12649
12650                         /* If the 5704 is behind the EPB bridge, we can
12651                          * do the less restrictive ONE_DMA workaround for
12652                          * better performance.
12653                          */
12654                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12655                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12656                                 tp->dma_rwctrl |= 0x8000;
12657                         else if (ccval == 0x6 || ccval == 0x7)
12658                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12659
12660                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12661                                 read_water = 4;
12662                         /* Set bit 23 to enable PCIX hw bug fix */
12663                         tp->dma_rwctrl |=
12664                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12665                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12666                                 (1 << 23);
12667                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12668                         /* 5780 always in PCIX mode */
12669                         tp->dma_rwctrl |= 0x00144000;
12670                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12671                         /* 5714 always in PCIX mode */
12672                         tp->dma_rwctrl |= 0x00148000;
12673                 } else {
12674                         tp->dma_rwctrl |= 0x001b000f;
12675                 }
12676         }
12677
12678         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12679             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12680                 tp->dma_rwctrl &= 0xfffffff0;
12681
12682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12683             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12684                 /* Remove this if it causes problems for some boards. */
12685                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12686
12687                 /* On 5700/5701 chips, we need to set this bit.
12688                  * Otherwise the chip will issue cacheline transactions
12689                  * to streamable DMA memory with not all the byte
12690                  * enables turned on.  This is an error on several
12691                  * RISC PCI controllers, in particular sparc64.
12692                  *
12693                  * On 5703/5704 chips, this bit has been reassigned
12694                  * a different meaning.  In particular, it is used
12695                  * on those chips to enable a PCI-X workaround.
12696                  */
12697                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12698         }
12699
12700         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12701
12702 #if 0
12703         /* Unneeded, already done by tg3_get_invariants.  */
12704         tg3_switch_clocks(tp);
12705 #endif
12706
12707         ret = 0;
12708         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12709             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12710                 goto out;
12711
12712         /* It is best to perform DMA test with maximum write burst size
12713          * to expose the 5700/5701 write DMA bug.
12714          */
12715         saved_dma_rwctrl = tp->dma_rwctrl;
12716         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12717         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12718
12719         while (1) {
12720                 u32 *p = buf, i;
12721
12722                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12723                         p[i] = i;
12724
12725                 /* Send the buffer to the chip. */
12726                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12727                 if (ret) {
12728                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12729                         break;
12730                 }
12731
12732 #if 0
12733                 /* validate data reached card RAM correctly. */
12734                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12735                         u32 val;
12736                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12737                         if (le32_to_cpu(val) != p[i]) {
12738                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12739                                 /* ret = -ENODEV here? */
12740                         }
12741                         p[i] = 0;
12742                 }
12743 #endif
12744                 /* Now read it back. */
12745                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12746                 if (ret) {
12747                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12748
12749                         break;
12750                 }
12751
12752                 /* Verify it. */
12753                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12754                         if (p[i] == i)
12755                                 continue;
12756
12757                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12758                             DMA_RWCTRL_WRITE_BNDRY_16) {
12759                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12760                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12761                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12762                                 break;
12763                         } else {
12764                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12765                                 ret = -ENODEV;
12766                                 goto out;
12767                         }
12768                 }
12769
12770                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12771                         /* Success. */
12772                         ret = 0;
12773                         break;
12774                 }
12775         }
12776         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12777             DMA_RWCTRL_WRITE_BNDRY_16) {
12778                 static struct pci_device_id dma_wait_state_chipsets[] = {
12779                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12780                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12781                         { },
12782                 };
12783
12784                 /* DMA test passed without adjusting DMA boundary,
12785                  * now look for chipsets that are known to expose the
12786                  * DMA bug without failing the test.
12787                  */
12788                 if (pci_dev_present(dma_wait_state_chipsets)) {
12789                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12790                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12791                 }
12792                 else
12793                         /* Safe to use the calculated DMA boundary. */
12794                         tp->dma_rwctrl = saved_dma_rwctrl;
12795
12796                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12797         }
12798
12799 out:
12800         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12801 out_nofree:
12802         return ret;
12803 }
12804
12805 static void __devinit tg3_init_link_config(struct tg3 *tp)
12806 {
12807         tp->link_config.advertising =
12808                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12809                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12810                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12811                  ADVERTISED_Autoneg | ADVERTISED_MII);
12812         tp->link_config.speed = SPEED_INVALID;
12813         tp->link_config.duplex = DUPLEX_INVALID;
12814         tp->link_config.autoneg = AUTONEG_ENABLE;
12815         tp->link_config.active_speed = SPEED_INVALID;
12816         tp->link_config.active_duplex = DUPLEX_INVALID;
12817         tp->link_config.phy_is_low_power = 0;
12818         tp->link_config.orig_speed = SPEED_INVALID;
12819         tp->link_config.orig_duplex = DUPLEX_INVALID;
12820         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12821 }
12822
12823 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12824 {
12825         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12826                 tp->bufmgr_config.mbuf_read_dma_low_water =
12827                         DEFAULT_MB_RDMA_LOW_WATER_5705;
12828                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12829                         DEFAULT_MB_MACRX_LOW_WATER_5705;
12830                 tp->bufmgr_config.mbuf_high_water =
12831                         DEFAULT_MB_HIGH_WATER_5705;
12832                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12833                         tp->bufmgr_config.mbuf_mac_rx_low_water =
12834                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
12835                         tp->bufmgr_config.mbuf_high_water =
12836                                 DEFAULT_MB_HIGH_WATER_5906;
12837                 }
12838
12839                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12840                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12841                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12842                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12843                 tp->bufmgr_config.mbuf_high_water_jumbo =
12844                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12845         } else {
12846                 tp->bufmgr_config.mbuf_read_dma_low_water =
12847                         DEFAULT_MB_RDMA_LOW_WATER;
12848                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12849                         DEFAULT_MB_MACRX_LOW_WATER;
12850                 tp->bufmgr_config.mbuf_high_water =
12851                         DEFAULT_MB_HIGH_WATER;
12852
12853                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12854                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12855                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12856                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12857                 tp->bufmgr_config.mbuf_high_water_jumbo =
12858                         DEFAULT_MB_HIGH_WATER_JUMBO;
12859         }
12860
12861         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12862         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12863 }
12864
12865 static char * __devinit tg3_phy_string(struct tg3 *tp)
12866 {
12867         switch (tp->phy_id & PHY_ID_MASK) {
12868         case PHY_ID_BCM5400:    return "5400";
12869         case PHY_ID_BCM5401:    return "5401";
12870         case PHY_ID_BCM5411:    return "5411";
12871         case PHY_ID_BCM5701:    return "5701";
12872         case PHY_ID_BCM5703:    return "5703";
12873         case PHY_ID_BCM5704:    return "5704";
12874         case PHY_ID_BCM5705:    return "5705";
12875         case PHY_ID_BCM5750:    return "5750";
12876         case PHY_ID_BCM5752:    return "5752";
12877         case PHY_ID_BCM5714:    return "5714";
12878         case PHY_ID_BCM5780:    return "5780";
12879         case PHY_ID_BCM5755:    return "5755";
12880         case PHY_ID_BCM5787:    return "5787";
12881         case PHY_ID_BCM5784:    return "5784";
12882         case PHY_ID_BCM5756:    return "5722/5756";
12883         case PHY_ID_BCM5906:    return "5906";
12884         case PHY_ID_BCM5761:    return "5761";
12885         case PHY_ID_BCM8002:    return "8002/serdes";
12886         case 0:                 return "serdes";
12887         default:                return "unknown";
12888         }
12889 }
12890
12891 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12892 {
12893         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12894                 strcpy(str, "PCI Express");
12895                 return str;
12896         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12897                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12898
12899                 strcpy(str, "PCIX:");
12900
12901                 if ((clock_ctrl == 7) ||
12902                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12903                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12904                         strcat(str, "133MHz");
12905                 else if (clock_ctrl == 0)
12906                         strcat(str, "33MHz");
12907                 else if (clock_ctrl == 2)
12908                         strcat(str, "50MHz");
12909                 else if (clock_ctrl == 4)
12910                         strcat(str, "66MHz");
12911                 else if (clock_ctrl == 6)
12912                         strcat(str, "100MHz");
12913         } else {
12914                 strcpy(str, "PCI:");
12915                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12916                         strcat(str, "66MHz");
12917                 else
12918                         strcat(str, "33MHz");
12919         }
12920         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12921                 strcat(str, ":32-bit");
12922         else
12923                 strcat(str, ":64-bit");
12924         return str;
12925 }
12926
12927 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
12928 {
12929         struct pci_dev *peer;
12930         unsigned int func, devnr = tp->pdev->devfn & ~7;
12931
12932         for (func = 0; func < 8; func++) {
12933                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12934                 if (peer && peer != tp->pdev)
12935                         break;
12936                 pci_dev_put(peer);
12937         }
12938         /* 5704 can be configured in single-port mode, set peer to
12939          * tp->pdev in that case.
12940          */
12941         if (!peer) {
12942                 peer = tp->pdev;
12943                 return peer;
12944         }
12945
12946         /*
12947          * We don't need to keep the refcount elevated; there's no way
12948          * to remove one half of this device without removing the other
12949          */
12950         pci_dev_put(peer);
12951
12952         return peer;
12953 }
12954
12955 static void __devinit tg3_init_coal(struct tg3 *tp)
12956 {
12957         struct ethtool_coalesce *ec = &tp->coal;
12958
12959         memset(ec, 0, sizeof(*ec));
12960         ec->cmd = ETHTOOL_GCOALESCE;
12961         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12962         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12963         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12964         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12965         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12966         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12967         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12968         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12969         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12970
12971         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12972                                  HOSTCC_MODE_CLRTICK_TXBD)) {
12973                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12974                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12975                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12976                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12977         }
12978
12979         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12980                 ec->rx_coalesce_usecs_irq = 0;
12981                 ec->tx_coalesce_usecs_irq = 0;
12982                 ec->stats_block_coalesce_usecs = 0;
12983         }
12984 }
12985
12986 static const struct net_device_ops tg3_netdev_ops = {
12987         .ndo_open               = tg3_open,
12988         .ndo_stop               = tg3_close,
12989         .ndo_start_xmit         = tg3_start_xmit,
12990         .ndo_get_stats          = tg3_get_stats,
12991         .ndo_validate_addr      = eth_validate_addr,
12992         .ndo_set_multicast_list = tg3_set_rx_mode,
12993         .ndo_set_mac_address    = tg3_set_mac_addr,
12994         .ndo_do_ioctl           = tg3_ioctl,
12995         .ndo_tx_timeout         = tg3_tx_timeout,
12996         .ndo_change_mtu         = tg3_change_mtu,
12997 #if TG3_VLAN_TAG_USED
12998         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
12999 #endif
13000 #ifdef CONFIG_NET_POLL_CONTROLLER
13001         .ndo_poll_controller    = tg3_poll_controller,
13002 #endif
13003 };
13004
13005 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13006         .ndo_open               = tg3_open,
13007         .ndo_stop               = tg3_close,
13008         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13009         .ndo_get_stats          = tg3_get_stats,
13010         .ndo_validate_addr      = eth_validate_addr,
13011         .ndo_set_multicast_list = tg3_set_rx_mode,
13012         .ndo_set_mac_address    = tg3_set_mac_addr,
13013         .ndo_do_ioctl           = tg3_ioctl,
13014         .ndo_tx_timeout         = tg3_tx_timeout,
13015         .ndo_change_mtu         = tg3_change_mtu,
13016 #if TG3_VLAN_TAG_USED
13017         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13018 #endif
13019 #ifdef CONFIG_NET_POLL_CONTROLLER
13020         .ndo_poll_controller    = tg3_poll_controller,
13021 #endif
13022 };
13023
13024 static int __devinit tg3_init_one(struct pci_dev *pdev,
13025                                   const struct pci_device_id *ent)
13026 {
13027         static int tg3_version_printed = 0;
13028         struct net_device *dev;
13029         struct tg3 *tp;
13030         int err, pm_cap;
13031         char str[40];
13032         u64 dma_mask, persist_dma_mask;
13033
13034         if (tg3_version_printed++ == 0)
13035                 printk(KERN_INFO "%s", version);
13036
13037         err = pci_enable_device(pdev);
13038         if (err) {
13039                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13040                        "aborting.\n");
13041                 return err;
13042         }
13043
13044         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13045         if (err) {
13046                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13047                        "aborting.\n");
13048                 goto err_out_disable_pdev;
13049         }
13050
13051         pci_set_master(pdev);
13052
13053         /* Find power-management capability. */
13054         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13055         if (pm_cap == 0) {
13056                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13057                        "aborting.\n");
13058                 err = -EIO;
13059                 goto err_out_free_res;
13060         }
13061
13062         dev = alloc_etherdev(sizeof(*tp));
13063         if (!dev) {
13064                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13065                 err = -ENOMEM;
13066                 goto err_out_free_res;
13067         }
13068
13069         SET_NETDEV_DEV(dev, &pdev->dev);
13070
13071 #if TG3_VLAN_TAG_USED
13072         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13073 #endif
13074
13075         tp = netdev_priv(dev);
13076         tp->pdev = pdev;
13077         tp->dev = dev;
13078         tp->pm_cap = pm_cap;
13079         tp->rx_mode = TG3_DEF_RX_MODE;
13080         tp->tx_mode = TG3_DEF_TX_MODE;
13081
13082         if (tg3_debug > 0)
13083                 tp->msg_enable = tg3_debug;
13084         else
13085                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13086
13087         /* The word/byte swap controls here control register access byte
13088          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13089          * setting below.
13090          */
13091         tp->misc_host_ctrl =
13092                 MISC_HOST_CTRL_MASK_PCI_INT |
13093                 MISC_HOST_CTRL_WORD_SWAP |
13094                 MISC_HOST_CTRL_INDIR_ACCESS |
13095                 MISC_HOST_CTRL_PCISTATE_RW;
13096
13097         /* The NONFRM (non-frame) byte/word swap controls take effect
13098          * on descriptor entries, anything which isn't packet data.
13099          *
13100          * The StrongARM chips on the board (one for tx, one for rx)
13101          * are running in big-endian mode.
13102          */
13103         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13104                         GRC_MODE_WSWAP_NONFRM_DATA);
13105 #ifdef __BIG_ENDIAN
13106         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13107 #endif
13108         spin_lock_init(&tp->lock);
13109         spin_lock_init(&tp->indirect_lock);
13110         INIT_WORK(&tp->reset_task, tg3_reset_task);
13111
13112         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13113         if (!tp->regs) {
13114                 printk(KERN_ERR PFX "Cannot map device registers, "
13115                        "aborting.\n");
13116                 err = -ENOMEM;
13117                 goto err_out_free_dev;
13118         }
13119
13120         tg3_init_link_config(tp);
13121
13122         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13123         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13124         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13125
13126         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13127         dev->ethtool_ops = &tg3_ethtool_ops;
13128         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13129         dev->irq = pdev->irq;
13130
13131         err = tg3_get_invariants(tp);
13132         if (err) {
13133                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13134                        "aborting.\n");
13135                 goto err_out_iounmap;
13136         }
13137
13138         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13139             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13140                 dev->netdev_ops = &tg3_netdev_ops;
13141         else
13142                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13143
13144
13145         /* The EPB bridge inside 5714, 5715, and 5780 and any
13146          * device behind the EPB cannot support DMA addresses > 40-bit.
13147          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13148          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13149          * do DMA address check in tg3_start_xmit().
13150          */
13151         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13152                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13153         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13154                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13155 #ifdef CONFIG_HIGHMEM
13156                 dma_mask = DMA_64BIT_MASK;
13157 #endif
13158         } else
13159                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13160
13161         /* Configure DMA attributes. */
13162         if (dma_mask > DMA_32BIT_MASK) {
13163                 err = pci_set_dma_mask(pdev, dma_mask);
13164                 if (!err) {
13165                         dev->features |= NETIF_F_HIGHDMA;
13166                         err = pci_set_consistent_dma_mask(pdev,
13167                                                           persist_dma_mask);
13168                         if (err < 0) {
13169                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13170                                        "DMA for consistent allocations\n");
13171                                 goto err_out_iounmap;
13172                         }
13173                 }
13174         }
13175         if (err || dma_mask == DMA_32BIT_MASK) {
13176                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13177                 if (err) {
13178                         printk(KERN_ERR PFX "No usable DMA configuration, "
13179                                "aborting.\n");
13180                         goto err_out_iounmap;
13181                 }
13182         }
13183
13184         tg3_init_bufmgr_config(tp);
13185
13186         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13187                 tp->fw_needed = FIRMWARE_TG3;
13188
13189         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13190                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13191         }
13192         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13193             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13194             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13195             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13196             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13197                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13198         } else {
13199                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13200                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13201                         tp->fw_needed = FIRMWARE_TG3TSO5;
13202                 else
13203                         tp->fw_needed = FIRMWARE_TG3TSO;
13204         }
13205
13206         /* TSO is on by default on chips that support hardware TSO.
13207          * Firmware TSO on older chips gives lower performance, so it
13208          * is off by default, but can be enabled using ethtool.
13209          */
13210         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13211                 if (dev->features & NETIF_F_IP_CSUM)
13212                         dev->features |= NETIF_F_TSO;
13213                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13214                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13215                         dev->features |= NETIF_F_TSO6;
13216                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13217                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13218                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13219                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13220                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13221                         dev->features |= NETIF_F_TSO_ECN;
13222         }
13223
13224
13225         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13226             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13227             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13228                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13229                 tp->rx_pending = 63;
13230         }
13231
13232         err = tg3_get_device_address(tp);
13233         if (err) {
13234                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13235                        "aborting.\n");
13236                 goto err_out_fw;
13237         }
13238
13239         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13240                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13241                 if (!tp->aperegs) {
13242                         printk(KERN_ERR PFX "Cannot map APE registers, "
13243                                "aborting.\n");
13244                         err = -ENOMEM;
13245                         goto err_out_fw;
13246                 }
13247
13248                 tg3_ape_lock_init(tp);
13249         }
13250
13251         /*
13252          * Reset chip in case UNDI or EFI driver did not shutdown
13253          * DMA self test will enable WDMAC and we'll see (spurious)
13254          * pending DMA on the PCI bus at that point.
13255          */
13256         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13257             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13258                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13259                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13260         }
13261
13262         err = tg3_test_dma(tp);
13263         if (err) {
13264                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13265                 goto err_out_apeunmap;
13266         }
13267
13268         /* flow control autonegotiation is default behavior */
13269         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13270         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13271
13272         tg3_init_coal(tp);
13273
13274         pci_set_drvdata(pdev, dev);
13275
13276         err = register_netdev(dev);
13277         if (err) {
13278                 printk(KERN_ERR PFX "Cannot register net device, "
13279                        "aborting.\n");
13280                 goto err_out_apeunmap;
13281         }
13282
13283         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13284                dev->name,
13285                tp->board_part_number,
13286                tp->pci_chip_rev_id,
13287                tg3_bus_string(tp, str),
13288                dev->dev_addr);
13289
13290         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13291                 printk(KERN_INFO
13292                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13293                        tp->dev->name,
13294                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13295                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13296         else
13297                 printk(KERN_INFO
13298                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13299                        tp->dev->name, tg3_phy_string(tp),
13300                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13301                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13302                          "10/100/1000Base-T")),
13303                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13304
13305         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13306                dev->name,
13307                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13308                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13309                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13310                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13311                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13312         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13313                dev->name, tp->dma_rwctrl,
13314                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13315                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13316
13317         return 0;
13318
13319 err_out_apeunmap:
13320         if (tp->aperegs) {
13321                 iounmap(tp->aperegs);
13322                 tp->aperegs = NULL;
13323         }
13324
13325 err_out_fw:
13326         if (tp->fw)
13327                 release_firmware(tp->fw);
13328
13329 err_out_iounmap:
13330         if (tp->regs) {
13331                 iounmap(tp->regs);
13332                 tp->regs = NULL;
13333         }
13334
13335 err_out_free_dev:
13336         free_netdev(dev);
13337
13338 err_out_free_res:
13339         pci_release_regions(pdev);
13340
13341 err_out_disable_pdev:
13342         pci_disable_device(pdev);
13343         pci_set_drvdata(pdev, NULL);
13344         return err;
13345 }
13346
13347 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13348 {
13349         struct net_device *dev = pci_get_drvdata(pdev);
13350
13351         if (dev) {
13352                 struct tg3 *tp = netdev_priv(dev);
13353
13354                 if (tp->fw)
13355                         release_firmware(tp->fw);
13356
13357                 flush_scheduled_work();
13358
13359                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13360                         tg3_phy_fini(tp);
13361                         tg3_mdio_fini(tp);
13362                 }
13363
13364                 unregister_netdev(dev);
13365                 if (tp->aperegs) {
13366                         iounmap(tp->aperegs);
13367                         tp->aperegs = NULL;
13368                 }
13369                 if (tp->regs) {
13370                         iounmap(tp->regs);
13371                         tp->regs = NULL;
13372                 }
13373                 free_netdev(dev);
13374                 pci_release_regions(pdev);
13375                 pci_disable_device(pdev);
13376                 pci_set_drvdata(pdev, NULL);
13377         }
13378 }
13379
13380 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13381 {
13382         struct net_device *dev = pci_get_drvdata(pdev);
13383         struct tg3 *tp = netdev_priv(dev);
13384         pci_power_t target_state;
13385         int err;
13386
13387         /* PCI register 4 needs to be saved whether netif_running() or not.
13388          * MSI address and data need to be saved if using MSI and
13389          * netif_running().
13390          */
13391         pci_save_state(pdev);
13392
13393         if (!netif_running(dev))
13394                 return 0;
13395
13396         flush_scheduled_work();
13397         tg3_phy_stop(tp);
13398         tg3_netif_stop(tp);
13399
13400         del_timer_sync(&tp->timer);
13401
13402         tg3_full_lock(tp, 1);
13403         tg3_disable_ints(tp);
13404         tg3_full_unlock(tp);
13405
13406         netif_device_detach(dev);
13407
13408         tg3_full_lock(tp, 0);
13409         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13410         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13411         tg3_full_unlock(tp);
13412
13413         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13414
13415         err = tg3_set_power_state(tp, target_state);
13416         if (err) {
13417                 int err2;
13418
13419                 tg3_full_lock(tp, 0);
13420
13421                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13422                 err2 = tg3_restart_hw(tp, 1);
13423                 if (err2)
13424                         goto out;
13425
13426                 tp->timer.expires = jiffies + tp->timer_offset;
13427                 add_timer(&tp->timer);
13428
13429                 netif_device_attach(dev);
13430                 tg3_netif_start(tp);
13431
13432 out:
13433                 tg3_full_unlock(tp);
13434
13435                 if (!err2)
13436                         tg3_phy_start(tp);
13437         }
13438
13439         return err;
13440 }
13441
13442 static int tg3_resume(struct pci_dev *pdev)
13443 {
13444         struct net_device *dev = pci_get_drvdata(pdev);
13445         struct tg3 *tp = netdev_priv(dev);
13446         int err;
13447
13448         pci_restore_state(tp->pdev);
13449
13450         if (!netif_running(dev))
13451                 return 0;
13452
13453         err = tg3_set_power_state(tp, PCI_D0);
13454         if (err)
13455                 return err;
13456
13457         netif_device_attach(dev);
13458
13459         tg3_full_lock(tp, 0);
13460
13461         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13462         err = tg3_restart_hw(tp, 1);
13463         if (err)
13464                 goto out;
13465
13466         tp->timer.expires = jiffies + tp->timer_offset;
13467         add_timer(&tp->timer);
13468
13469         tg3_netif_start(tp);
13470
13471 out:
13472         tg3_full_unlock(tp);
13473
13474         if (!err)
13475                 tg3_phy_start(tp);
13476
13477         return err;
13478 }
13479
13480 static struct pci_driver tg3_driver = {
13481         .name           = DRV_MODULE_NAME,
13482         .id_table       = tg3_pci_tbl,
13483         .probe          = tg3_init_one,
13484         .remove         = __devexit_p(tg3_remove_one),
13485         .suspend        = tg3_suspend,
13486         .resume         = tg3_resume
13487 };
13488
13489 static int __init tg3_init(void)
13490 {
13491         return pci_register_driver(&tg3_driver);
13492 }
13493
13494 static void __exit tg3_cleanup(void)
13495 {
13496         pci_unregister_driver(&tg3_driver);
13497 }
13498
13499 module_init(tg3_init);
13500 module_exit(tg3_cleanup);