drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #ifdef NETIF_F_TSO
  62 #define TG3_TSO_SUPPORT 1
  63 #else
  64 #define TG3_TSO_SUPPORT 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.68"
  72 #define DRV_MODULE_RELDATE      "November 02, 2006"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 /* number of ETHTOOL_GSTATS u64's */
 135 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 136
 137 #define TG3_NUM_TEST            6
 138
 139 static char version[] __devinitdata =
 140         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 141
 142 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 143 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 144 MODULE_LICENSE("GPL");
 145 MODULE_VERSION(DRV_MODULE_VERSION);
 146
 147 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 148 module_param(tg3_debug, int, 0);
 149 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 150
 151 static struct pci_device_id tg3_pci_tbl[] = {
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 211         {}
 212 };
 213
 214 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 215
 216 static const struct {
 217         const char string[ETH_GSTRING_LEN];
 218 } ethtool_stats_keys[TG3_NUM_STATS] = {
 219         { "rx_octets" },
 220         { "rx_fragments" },
 221         { "rx_ucast_packets" },
 222         { "rx_mcast_packets" },
 223         { "rx_bcast_packets" },
 224         { "rx_fcs_errors" },
 225         { "rx_align_errors" },
 226         { "rx_xon_pause_rcvd" },
 227         { "rx_xoff_pause_rcvd" },
 228         { "rx_mac_ctrl_rcvd" },
 229         { "rx_xoff_entered" },
 230         { "rx_frame_too_long_errors" },
 231         { "rx_jabbers" },
 232         { "rx_undersize_packets" },
 233         { "rx_in_length_errors" },
 234         { "rx_out_length_errors" },
 235         { "rx_64_or_less_octet_packets" },
 236         { "rx_65_to_127_octet_packets" },
 237         { "rx_128_to_255_octet_packets" },
 238         { "rx_256_to_511_octet_packets" },
 239         { "rx_512_to_1023_octet_packets" },
 240         { "rx_1024_to_1522_octet_packets" },
 241         { "rx_1523_to_2047_octet_packets" },
 242         { "rx_2048_to_4095_octet_packets" },
 243         { "rx_4096_to_8191_octet_packets" },
 244         { "rx_8192_to_9022_octet_packets" },
 245
 246         { "tx_octets" },
 247         { "tx_collisions" },
 248
 249         { "tx_xon_sent" },
 250         { "tx_xoff_sent" },
 251         { "tx_flow_control" },
 252         { "tx_mac_errors" },
 253         { "tx_single_collisions" },
 254         { "tx_mult_collisions" },
 255         { "tx_deferred" },
 256         { "tx_excessive_collisions" },
 257         { "tx_late_collisions" },
 258         { "tx_collide_2times" },
 259         { "tx_collide_3times" },
 260         { "tx_collide_4times" },
 261         { "tx_collide_5times" },
 262         { "tx_collide_6times" },
 263         { "tx_collide_7times" },
 264         { "tx_collide_8times" },
 265         { "tx_collide_9times" },
 266         { "tx_collide_10times" },
 267         { "tx_collide_11times" },
 268         { "tx_collide_12times" },
 269         { "tx_collide_13times" },
 270         { "tx_collide_14times" },
 271         { "tx_collide_15times" },
 272         { "tx_ucast_packets" },
 273         { "tx_mcast_packets" },
 274         { "tx_bcast_packets" },
 275         { "tx_carrier_sense_errors" },
 276         { "tx_discards" },
 277         { "tx_errors" },
 278
 279         { "dma_writeq_full" },
 280         { "dma_write_prioq_full" },
 281         { "rxbds_empty" },
 282         { "rx_discards" },
 283         { "rx_errors" },
 284         { "rx_threshold_hit" },
 285
 286         { "dma_readq_full" },
 287         { "dma_read_prioq_full" },
 288         { "tx_comp_queue_full" },
 289
 290         { "ring_set_send_prod_index" },
 291         { "ring_status_update" },
 292         { "nic_irqs" },
 293         { "nic_avoided_irqs" },
 294         { "nic_tx_threshold_hit" }
 295 };
 296
 297 static const struct {
 298         const char string[ETH_GSTRING_LEN];
 299 } ethtool_test_keys[TG3_NUM_TEST] = {
 300         { "nvram test     (online) " },
 301         { "link test      (online) " },
 302         { "register test  (offline)" },
 303         { "memory test    (offline)" },
 304         { "loopback test  (offline)" },
 305         { "interrupt test (offline)" },
 306 };
 307
 308 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 309 {
 310         writel(val, tp->regs + off);
 311 }
 312
 313 static u32 tg3_read32(struct tg3 *tp, u32 off)
 314 {
 315         return (readl(tp->regs + off));
 316 }
 317
 318 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 319 {
 320         unsigned long flags;
 321
 322         spin_lock_irqsave(&tp->indirect_lock, flags);
 323         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 324         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 325         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 326 }
 327
 328 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 329 {
 330         writel(val, tp->regs + off);
 331         readl(tp->regs + off);
 332 }
 333
 334 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 335 {
 336         unsigned long flags;
 337         u32 val;
 338
 339         spin_lock_irqsave(&tp->indirect_lock, flags);
 340         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 341         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 342         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 343         return val;
 344 }
 345
 346 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 347 {
 348         unsigned long flags;
 349
 350         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 351                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 352                                        TG3_64BIT_REG_LOW, val);
 353                 return;
 354         }
 355         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 356                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 357                                        TG3_64BIT_REG_LOW, val);
 358                 return;
 359         }
 360
 361         spin_lock_irqsave(&tp->indirect_lock, flags);
 362         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 363         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 364         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 365
 366         /* In indirect mode when disabling interrupts, we also need
 367          * to clear the interrupt bit in the GRC local ctrl register.
 368          */
 369         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 370             (val == 0x1)) {
 371                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 372                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 373         }
 374 }
 375
 376 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 377 {
 378         unsigned long flags;
 379         u32 val;
 380
 381         spin_lock_irqsave(&tp->indirect_lock, flags);
 382         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 383         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 384         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 385         return val;
 386 }
 387
 388 /* usec_wait specifies the wait time in usec when writing to certain registers
 389  * where it is unsafe to read back the register without some delay.
 390  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 391  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 392  */
 393 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 394 {
 395         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 396             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 397                 /* Non-posted methods */
 398                 tp->write32(tp, off, val);
 399         else {
 400                 /* Posted method */
 401                 tg3_write32(tp, off, val);
 402                 if (usec_wait)
 403                         udelay(usec_wait);
 404                 tp->read32(tp, off);
 405         }
 406         /* Wait again after the read for the posted method to guarantee that
 407          * the wait time is met.
 408          */
 409         if (usec_wait)
 410                 udelay(usec_wait);
 411 }
 412
 413 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 414 {
 415         tp->write32_mbox(tp, off, val);
 416         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 417             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 418                 tp->read32_mbox(tp, off);
 419 }
 420
 421 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 422 {
 423         void __iomem *mbox = tp->regs + off;
 424         writel(val, mbox);
 425         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 426                 writel(val, mbox);
 427         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 428                 readl(mbox);
 429 }
 430
 431 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 432 {
 433         return (readl(tp->regs + off + GRCMBOX_BASE));
 434 }
 435
 436 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 437 {
 438         writel(val, tp->regs + off + GRCMBOX_BASE);
 439 }
 440
 441 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 442 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 443 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 444 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 445 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 446
 447 #define tw32(reg,val)           tp->write32(tp, reg, val)
 448 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 449 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 450 #define tr32(reg)               tp->read32(tp, reg)
 451
 452 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 453 {
 454         unsigned long flags;
 455
 456         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 457             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 458                 return;
 459
 460         spin_lock_irqsave(&tp->indirect_lock, flags);
 461         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 462                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 464
 465                 /* Always leave this as zero. */
 466                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 467         } else {
 468                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 469                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 470
 471                 /* Always leave this as zero. */
 472                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 473         }
 474         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 475 }
 476
 477 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 478 {
 479         unsigned long flags;
 480
 481         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 482             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 483                 *val = 0;
 484                 return;
 485         }
 486
 487         spin_lock_irqsave(&tp->indirect_lock, flags);
 488         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 489                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 490                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 491
 492                 /* Always leave this as zero. */
 493                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 494         } else {
 495                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 496                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 497
 498                 /* Always leave this as zero. */
 499                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 500         }
 501         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 502 }
 503
 504 static void tg3_disable_ints(struct tg3 *tp)
 505 {
 506         tw32(TG3PCI_MISC_HOST_CTRL,
 507              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 508         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 509 }
 510
 511 static inline void tg3_cond_int(struct tg3 *tp)
 512 {
 513         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 514             (tp->hw_status->status & SD_STATUS_UPDATED))
 515                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 516         else
 517                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 518                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 519 }
 520
 521 static void tg3_enable_ints(struct tg3 *tp)
 522 {
 523         tp->irq_sync = 0;
 524         wmb();
 525
 526         tw32(TG3PCI_MISC_HOST_CTRL,
 527              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 528         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 529                        (tp->last_tag << 24));
 530         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 531                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 532                                (tp->last_tag << 24));
 533         tg3_cond_int(tp);
 534 }
 535
 536 static inline unsigned int tg3_has_work(struct tg3 *tp)
 537 {
 538         struct tg3_hw_status *sblk = tp->hw_status;
 539         unsigned int work_exists = 0;
 540
 541         /* check for phy events */
 542         if (!(tp->tg3_flags &
 543               (TG3_FLAG_USE_LINKCHG_REG |
 544                TG3_FLAG_POLL_SERDES))) {
 545                 if (sblk->status & SD_STATUS_LINK_CHG)
 546                         work_exists = 1;
 547         }
 548         /* check for RX/TX work to do */
 549         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 550             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 551                 work_exists = 1;
 552
 553         return work_exists;
 554 }
 555
 556 /* tg3_restart_ints
 557  *  similar to tg3_enable_ints, but it accurately determines whether there
 558  *  is new work pending and can return without flushing the PIO write
 559  *  which reenables interrupts
 560  */
 561 static void tg3_restart_ints(struct tg3 *tp)
 562 {
 563         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 564                      tp->last_tag << 24);
 565         mmiowb();
 566
 567         /* When doing tagged status, this work check is unnecessary.
 568          * The last_tag we write above tells the chip which piece of
 569          * work we've completed.
 570          */
 571         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 572             tg3_has_work(tp))
 573                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 574                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 575 }
 576
 577 static inline void tg3_netif_stop(struct tg3 *tp)
 578 {
 579         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 580         netif_poll_disable(tp->dev);
 581         netif_tx_disable(tp->dev);
 582 }
 583
 584 static inline void tg3_netif_start(struct tg3 *tp)
 585 {
 586         netif_wake_queue(tp->dev);
 587         /* NOTE: unconditional netif_wake_queue is only appropriate
 588          * so long as all callers are assured to have free tx slots
 589          * (such as after tg3_init_hw)
 590          */
 591         netif_poll_enable(tp->dev);
 592         tp->hw_status->status |= SD_STATUS_UPDATED;
 593         tg3_enable_ints(tp);
 594 }
 595
 596 static void tg3_switch_clocks(struct tg3 *tp)
 597 {
 598         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 599         u32 orig_clock_ctrl;
 600
 601         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 602                 return;
 603
 604         orig_clock_ctrl = clock_ctrl;
 605         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 606                        CLOCK_CTRL_CLKRUN_OENABLE |
 607                        0x1f);
 608         tp->pci_clock_ctrl = clock_ctrl;
 609
 610         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 611                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 612                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 613                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 614                 }
 615         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 616                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 617                             clock_ctrl |
 618                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 619                             40);
 620                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 621                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 622                             40);
 623         }
 624         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 625 }
 626
 627 #define PHY_BUSY_LOOPS  5000
 628
 629 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 630 {
 631         u32 frame_val;
 632         unsigned int loops;
 633         int ret;
 634
 635         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 636                 tw32_f(MAC_MI_MODE,
 637                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 638                 udelay(80);
 639         }
 640
 641         *val = 0x0;
 642
 643         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 644                       MI_COM_PHY_ADDR_MASK);
 645         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 646                       MI_COM_REG_ADDR_MASK);
 647         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 648
 649         tw32_f(MAC_MI_COM, frame_val);
 650
 651         loops = PHY_BUSY_LOOPS;
 652         while (loops != 0) {
 653                 udelay(10);
 654                 frame_val = tr32(MAC_MI_COM);
 655
 656                 if ((frame_val & MI_COM_BUSY) == 0) {
 657                         udelay(5);
 658                         frame_val = tr32(MAC_MI_COM);
 659                         break;
 660                 }
 661                 loops -= 1;
 662         }
 663
 664         ret = -EBUSY;
 665         if (loops != 0) {
 666                 *val = frame_val & MI_COM_DATA_MASK;
 667                 ret = 0;
 668         }
 669
 670         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 671                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 672                 udelay(80);
 673         }
 674
 675         return ret;
 676 }
 677
 678 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 679 {
 680         u32 frame_val;
 681         unsigned int loops;
 682         int ret;
 683
 684         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 685             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 686                 return 0;
 687
 688         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 689                 tw32_f(MAC_MI_MODE,
 690                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 691                 udelay(80);
 692         }
 693
 694         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 695                       MI_COM_PHY_ADDR_MASK);
 696         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 697                       MI_COM_REG_ADDR_MASK);
 698         frame_val |= (val & MI_COM_DATA_MASK);
 699         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 700
 701         tw32_f(MAC_MI_COM, frame_val);
 702
 703         loops = PHY_BUSY_LOOPS;
 704         while (loops != 0) {
 705                 udelay(10);
 706                 frame_val = tr32(MAC_MI_COM);
 707                 if ((frame_val & MI_COM_BUSY) == 0) {
 708                         udelay(5);
 709                         frame_val = tr32(MAC_MI_COM);
 710                         break;
 711                 }
 712                 loops -= 1;
 713         }
 714
 715         ret = -EBUSY;
 716         if (loops != 0)
 717                 ret = 0;
 718
 719         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 720                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 721                 udelay(80);
 722         }
 723
 724         return ret;
 725 }
 726
 727 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 728 {
 729         u32 val;
 730
 731         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 732                 return;
 733
 734         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 735             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 736                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 737                              (val | (1 << 15) | (1 << 4)));
 738 }
 739
 740 static int tg3_bmcr_reset(struct tg3 *tp)
 741 {
 742         u32 phy_control;
 743         int limit, err;
 744
 745         /* OK, reset it, and poll the BMCR_RESET bit until it
 746          * clears or we time out.
 747          */
 748         phy_control = BMCR_RESET;
 749         err = tg3_writephy(tp, MII_BMCR, phy_control);
 750         if (err != 0)
 751                 return -EBUSY;
 752
 753         limit = 5000;
 754         while (limit--) {
 755                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 756                 if (err != 0)
 757                         return -EBUSY;
 758
 759                 if ((phy_control & BMCR_RESET) == 0) {
 760                         udelay(40);
 761                         break;
 762                 }
 763                 udelay(10);
 764         }
 765         if (limit <= 0)
 766                 return -EBUSY;
 767
 768         return 0;
 769 }
 770
 771 static int tg3_wait_macro_done(struct tg3 *tp)
 772 {
 773         int limit = 100;
 774
 775         while (limit--) {
 776                 u32 tmp32;
 777
 778                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 779                         if ((tmp32 & 0x1000) == 0)
 780                                 break;
 781                 }
 782         }
 783         if (limit <= 0)
 784                 return -EBUSY;
 785
 786         return 0;
 787 }
 788
 789 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 790 {
 791         static const u32 test_pat[4][6] = {
 792         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 793         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 794         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 795         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 796         };
 797         int chan;
 798
 799         for (chan = 0; chan < 4; chan++) {
 800                 int i;
 801
 802                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 803                              (chan * 0x2000) | 0x0200);
 804                 tg3_writephy(tp, 0x16, 0x0002);
 805
 806                 for (i = 0; i < 6; i++)
 807                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 808                                      test_pat[chan][i]);
 809
 810                 tg3_writephy(tp, 0x16, 0x0202);
 811                 if (tg3_wait_macro_done(tp)) {
 812                         *resetp = 1;
 813                         return -EBUSY;
 814                 }
 815
 816                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 817                              (chan * 0x2000) | 0x0200);
 818                 tg3_writephy(tp, 0x16, 0x0082);
 819                 if (tg3_wait_macro_done(tp)) {
 820                         *resetp = 1;
 821                         return -EBUSY;
 822                 }
 823
 824                 tg3_writephy(tp, 0x16, 0x0802);
 825                 if (tg3_wait_macro_done(tp)) {
 826                         *resetp = 1;
 827                         return -EBUSY;
 828                 }
 829
 830                 for (i = 0; i < 6; i += 2) {
 831                         u32 low, high;
 832
 833                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 834                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 835                             tg3_wait_macro_done(tp)) {
 836                                 *resetp = 1;
 837                                 return -EBUSY;
 838                         }
 839                         low &= 0x7fff;
 840                         high &= 0x000f;
 841                         if (low != test_pat[chan][i] ||
 842                             high != test_pat[chan][i+1]) {
 843                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 844                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 845                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 846
 847                                 return -EBUSY;
 848                         }
 849                 }
 850         }
 851
 852         return 0;
 853 }
 854
 855 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 856 {
 857         int chan;
 858
 859         for (chan = 0; chan < 4; chan++) {
 860                 int i;
 861
 862                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 863                              (chan * 0x2000) | 0x0200);
 864                 tg3_writephy(tp, 0x16, 0x0002);
 865                 for (i = 0; i < 6; i++)
 866                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 867                 tg3_writephy(tp, 0x16, 0x0202);
 868                 if (tg3_wait_macro_done(tp))
 869                         return -EBUSY;
 870         }
 871
 872         return 0;
 873 }
 874
 875 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 876 {
 877         u32 reg32, phy9_orig;
 878         int retries, do_phy_reset, err;
 879
 880         retries = 10;
 881         do_phy_reset = 1;
 882         do {
 883                 if (do_phy_reset) {
 884                         err = tg3_bmcr_reset(tp);
 885                         if (err)
 886                                 return err;
 887                         do_phy_reset = 0;
 888                 }
 889
 890                 /* Disable transmitter and interrupt.  */
 891                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 892                         continue;
 893
 894                 reg32 |= 0x3000;
 895                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 896
 897                 /* Set full-duplex, 1000 mbps.  */
 898                 tg3_writephy(tp, MII_BMCR,
 899                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 900
 901                 /* Set to master mode.  */
 902                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 903                         continue;
 904
 905                 tg3_writephy(tp, MII_TG3_CTRL,
 906                              (MII_TG3_CTRL_AS_MASTER |
 907                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 908
 909                 /* Enable SM_DSP_CLOCK and 6dB.  */
 910                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 911
 912                 /* Block the PHY control access.  */
 913                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 914                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 915
 916                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 917                 if (!err)
 918                         break;
 919         } while (--retries);
 920
 921         err = tg3_phy_reset_chanpat(tp);
 922         if (err)
 923                 return err;
 924
 925         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 926         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 927
 928         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 929         tg3_writephy(tp, 0x16, 0x0000);
 930
 931         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 932             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 933                 /* Set Extended packet length bit for jumbo frames */
 934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 935         }
 936         else {
 937                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 938         }
 939
 940         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 941
 942         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 943                 reg32 &= ~0x3000;
 944                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 945         } else if (!err)
 946                 err = -EBUSY;
 947
 948         return err;
 949 }
 950
 951 static void tg3_link_report(struct tg3 *);
 952
 953 /* This will reset the tigon3 PHY if there is no valid
 954  * link unless the FORCE argument is non-zero.
 955  */
 956 static int tg3_phy_reset(struct tg3 *tp)
 957 {
 958         u32 phy_status;
 959         int err;
 960
 961         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 962         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 963         if (err != 0)
 964                 return -EBUSY;
 965
 966         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 967                 netif_carrier_off(tp->dev);
 968                 tg3_link_report(tp);
 969         }
 970
 971         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 974                 err = tg3_phy_reset_5703_4_5(tp);
 975                 if (err)
 976                         return err;
 977                 goto out;
 978         }
 979
 980         err = tg3_bmcr_reset(tp);
 981         if (err)
 982                 return err;
 983
 984 out:
 985         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 986                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 987                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 988                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 989                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 990                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 991                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 992         }
 993         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 994                 tg3_writephy(tp, 0x1c, 0x8d68);
 995                 tg3_writephy(tp, 0x1c, 0x8d68);
 996         }
 997         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 998                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 999                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1000                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1001                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1002                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1003                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1004                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1005                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1006         }
1007         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1008                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1009                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1010                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1011                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1012         }
1013         /* Set Extended packet length bit (bit 14) on all chips that */
1014         /* support jumbo frames */
1015         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1016                 /* Cannot do read-modify-write on 5401 */
1017                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1018         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1019                 u32 phy_reg;
1020
1021                 /* Set bit 14 with read-modify-write to preserve other bits */
1022                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1023                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1024                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1025         }
1026
1027         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1028          * jumbo frames transmission.
1029          */
1030         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1031                 u32 phy_reg;
1032
1033                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1034                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1035                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1036         }
1037
1038         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1039                 u32 phy_reg;
1040
1041                 /* adjust output voltage */
1042                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1043
1044                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1045                         u32 phy_reg2;
1046
1047                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1048                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1049                         /* Enable auto-MDIX */
1050                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1051                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1052                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1053                 }
1054         }
1055
1056         tg3_phy_set_wirespeed(tp);
1057         return 0;
1058 }
1059
1060 static void tg3_frob_aux_power(struct tg3 *tp)
1061 {
1062         struct tg3 *tp_peer = tp;
1063
1064         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1065                 return;
1066
1067         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1068             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1069                 struct net_device *dev_peer;
1070
1071                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1072                 /* remove_one() may have been run on the peer. */
1073                 if (!dev_peer)
1074                         tp_peer = tp;
1075                 else
1076                         tp_peer = netdev_priv(dev_peer);
1077         }
1078
1079         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1080             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1081             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1082             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1083                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1084                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1085                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1086                                     (GRC_LCLCTRL_GPIO_OE0 |
1087                                      GRC_LCLCTRL_GPIO_OE1 |
1088                                      GRC_LCLCTRL_GPIO_OE2 |
1089                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1090                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1091                                     100);
1092                 } else {
1093                         u32 no_gpio2;
1094                         u32 grc_local_ctrl = 0;
1095
1096                         if (tp_peer != tp &&
1097                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1098                                 return;
1099
1100                         /* Workaround to prevent overdrawing Amps. */
1101                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1102                             ASIC_REV_5714) {
1103                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1104                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1105                                             grc_local_ctrl, 100);
1106                         }
1107
1108                         /* On 5753 and variants, GPIO2 cannot be used. */
1109                         no_gpio2 = tp->nic_sram_data_cfg &
1110                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1111
1112                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1113                                          GRC_LCLCTRL_GPIO_OE1 |
1114                                          GRC_LCLCTRL_GPIO_OE2 |
1115                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1116                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1117                         if (no_gpio2) {
1118                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1119                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1120                         }
1121                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1122                                                     grc_local_ctrl, 100);
1123
1124                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1125
1126                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1127                                                     grc_local_ctrl, 100);
1128
1129                         if (!no_gpio2) {
1130                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1131                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1132                                             grc_local_ctrl, 100);
1133                         }
1134                 }
1135         } else {
1136                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1137                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1138                         if (tp_peer != tp &&
1139                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1140                                 return;
1141
1142                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1143                                     (GRC_LCLCTRL_GPIO_OE1 |
1144                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1145
1146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1147                                     GRC_LCLCTRL_GPIO_OE1, 100);
1148
1149                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1150                                     (GRC_LCLCTRL_GPIO_OE1 |
1151                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1152                 }
1153         }
1154 }
1155
1156 static int tg3_setup_phy(struct tg3 *, int);
1157
1158 #define RESET_KIND_SHUTDOWN     0
1159 #define RESET_KIND_INIT         1
1160 #define RESET_KIND_SUSPEND      2
1161
1162 static void tg3_write_sig_post_reset(struct tg3 *, int);
1163 static int tg3_halt_cpu(struct tg3 *, u32);
1164 static int tg3_nvram_lock(struct tg3 *);
1165 static void tg3_nvram_unlock(struct tg3 *);
1166
1167 static void tg3_power_down_phy(struct tg3 *tp)
1168 {
1169         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1170                 return;
1171
1172         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1173                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1174                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1175                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1176         }
1177
1178         /* The PHY should not be powered down on some chips because
1179          * of bugs.
1180          */
1181         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1182             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1183             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1184              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1185                 return;
1186         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1187 }
1188
1189 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1190 {
1191         u32 misc_host_ctrl;
1192         u16 power_control, power_caps;
1193         int pm = tp->pm_cap;
1194
1195         /* Make sure register accesses (indirect or otherwise)
1196          * will function correctly.
1197          */
1198         pci_write_config_dword(tp->pdev,
1199                                TG3PCI_MISC_HOST_CTRL,
1200                                tp->misc_host_ctrl);
1201
1202         pci_read_config_word(tp->pdev,
1203                              pm + PCI_PM_CTRL,
1204                              &power_control);
1205         power_control |= PCI_PM_CTRL_PME_STATUS;
1206         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1207         switch (state) {
1208         case PCI_D0:
1209                 power_control |= 0;
1210                 pci_write_config_word(tp->pdev,
1211                                       pm + PCI_PM_CTRL,
1212                                       power_control);
1213                 udelay(100);    /* Delay after power state change */
1214
1215                 /* Switch out of Vaux if it is not a LOM */
1216                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1217                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1218
1219                 return 0;
1220
1221         case PCI_D1:
1222                 power_control |= 1;
1223                 break;
1224
1225         case PCI_D2:
1226                 power_control |= 2;
1227                 break;
1228
1229         case PCI_D3hot:
1230                 power_control |= 3;
1231                 break;
1232
1233         default:
1234                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1235                        "requested.\n",
1236                        tp->dev->name, state);
1237                 return -EINVAL;
1238         };
1239
1240         power_control |= PCI_PM_CTRL_PME_ENABLE;
1241
1242         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1243         tw32(TG3PCI_MISC_HOST_CTRL,
1244              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1245
1246         if (tp->link_config.phy_is_low_power == 0) {
1247                 tp->link_config.phy_is_low_power = 1;
1248                 tp->link_config.orig_speed = tp->link_config.speed;
1249                 tp->link_config.orig_duplex = tp->link_config.duplex;
1250                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1251         }
1252
1253         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1254                 tp->link_config.speed = SPEED_10;
1255                 tp->link_config.duplex = DUPLEX_HALF;
1256                 tp->link_config.autoneg = AUTONEG_ENABLE;
1257                 tg3_setup_phy(tp, 0);
1258         }
1259
1260         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1261                 u32 val;
1262
1263                 val = tr32(GRC_VCPU_EXT_CTRL);
1264                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1265         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1266                 int i;
1267                 u32 val;
1268
1269                 for (i = 0; i < 200; i++) {
1270                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1271                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1272                                 break;
1273                         msleep(1);
1274                 }
1275         }
1276         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1277                                              WOL_DRV_STATE_SHUTDOWN |
1278                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1279
1280         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1281
1282         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1283                 u32 mac_mode;
1284
1285                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1286                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1287                         udelay(40);
1288
1289                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1290                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1291                         else
1292                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1293
1294                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1295                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1296                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1297                 } else {
1298                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1299                 }
1300
1301                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1302                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1303
1304                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1305                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1306                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1307
1308                 tw32_f(MAC_MODE, mac_mode);
1309                 udelay(100);
1310
1311                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1312                 udelay(10);
1313         }
1314
1315         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1316             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1317              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1318                 u32 base_val;
1319
1320                 base_val = tp->pci_clock_ctrl;
1321                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1322                              CLOCK_CTRL_TXCLK_DISABLE);
1323
1324                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1325                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1326         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1327                 /* do nothing */
1328         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1329                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1330                 u32 newbits1, newbits2;
1331
1332                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1333                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1334                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1335                                     CLOCK_CTRL_TXCLK_DISABLE |
1336                                     CLOCK_CTRL_ALTCLK);
1337                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1338                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1339                         newbits1 = CLOCK_CTRL_625_CORE;
1340                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1341                 } else {
1342                         newbits1 = CLOCK_CTRL_ALTCLK;
1343                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1344                 }
1345
1346                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1347                             40);
1348
1349                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1350                             40);
1351
1352                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1353                         u32 newbits3;
1354
1355                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1356                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1357                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1358                                             CLOCK_CTRL_TXCLK_DISABLE |
1359                                             CLOCK_CTRL_44MHZ_CORE);
1360                         } else {
1361                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1362                         }
1363
1364                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1365                                     tp->pci_clock_ctrl | newbits3, 40);
1366                 }
1367         }
1368
1369         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1370             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1371                 tg3_power_down_phy(tp);
1372
1373         tg3_frob_aux_power(tp);
1374
1375         /* Workaround for unstable PLL clock */
1376         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1377             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1378                 u32 val = tr32(0x7d00);
1379
1380                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1381                 tw32(0x7d00, val);
1382                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1383                         int err;
1384
1385                         err = tg3_nvram_lock(tp);
1386                         tg3_halt_cpu(tp, RX_CPU_BASE);
1387                         if (!err)
1388                                 tg3_nvram_unlock(tp);
1389                 }
1390         }
1391
1392         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1393
1394         /* Finally, set the new power state. */
1395         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1396         udelay(100);    /* Delay after power state change */
1397
1398         return 0;
1399 }
1400
1401 static void tg3_link_report(struct tg3 *tp)
1402 {
1403         if (!netif_carrier_ok(tp->dev)) {
1404                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1405         } else {
1406                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1407                        tp->dev->name,
1408                        (tp->link_config.active_speed == SPEED_1000 ?
1409                         1000 :
1410                         (tp->link_config.active_speed == SPEED_100 ?
1411                          100 : 10)),
1412                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1413                         "full" : "half"));
1414
1415                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1416                        "%s for RX.\n",
1417                        tp->dev->name,
1418                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1419                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1420         }
1421 }
1422
1423 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1424 {
1425         u32 new_tg3_flags = 0;
1426         u32 old_rx_mode = tp->rx_mode;
1427         u32 old_tx_mode = tp->tx_mode;
1428
1429         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1430
1431                 /* Convert 1000BaseX flow control bits to 1000BaseT
1432                  * bits before resolving flow control.
1433                  */
1434                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1435                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1436                                        ADVERTISE_PAUSE_ASYM);
1437                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1438
1439                         if (local_adv & ADVERTISE_1000XPAUSE)
1440                                 local_adv |= ADVERTISE_PAUSE_CAP;
1441                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1442                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1443                         if (remote_adv & LPA_1000XPAUSE)
1444                                 remote_adv |= LPA_PAUSE_CAP;
1445                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1446                                 remote_adv |= LPA_PAUSE_ASYM;
1447                 }
1448
1449                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1450                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1451                                 if (remote_adv & LPA_PAUSE_CAP)
1452                                         new_tg3_flags |=
1453                                                 (TG3_FLAG_RX_PAUSE |
1454                                                 TG3_FLAG_TX_PAUSE);
1455                                 else if (remote_adv & LPA_PAUSE_ASYM)
1456                                         new_tg3_flags |=
1457                                                 (TG3_FLAG_RX_PAUSE);
1458                         } else {
1459                                 if (remote_adv & LPA_PAUSE_CAP)
1460                                         new_tg3_flags |=
1461                                                 (TG3_FLAG_RX_PAUSE |
1462                                                 TG3_FLAG_TX_PAUSE);
1463                         }
1464                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1465                         if ((remote_adv & LPA_PAUSE_CAP) &&
1466                         (remote_adv & LPA_PAUSE_ASYM))
1467                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1468                 }
1469
1470                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1471                 tp->tg3_flags |= new_tg3_flags;
1472         } else {
1473                 new_tg3_flags = tp->tg3_flags;
1474         }
1475
1476         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1477                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1478         else
1479                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1480
1481         if (old_rx_mode != tp->rx_mode) {
1482                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1483         }
1484
1485         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1486                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1487         else
1488                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1489
1490         if (old_tx_mode != tp->tx_mode) {
1491                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1492         }
1493 }
1494
1495 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1496 {
1497         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1498         case MII_TG3_AUX_STAT_10HALF:
1499                 *speed = SPEED_10;
1500                 *duplex = DUPLEX_HALF;
1501                 break;
1502
1503         case MII_TG3_AUX_STAT_10FULL:
1504                 *speed = SPEED_10;
1505                 *duplex = DUPLEX_FULL;
1506                 break;
1507
1508         case MII_TG3_AUX_STAT_100HALF:
1509                 *speed = SPEED_100;
1510                 *duplex = DUPLEX_HALF;
1511                 break;
1512
1513         case MII_TG3_AUX_STAT_100FULL:
1514                 *speed = SPEED_100;
1515                 *duplex = DUPLEX_FULL;
1516                 break;
1517
1518         case MII_TG3_AUX_STAT_1000HALF:
1519                 *speed = SPEED_1000;
1520                 *duplex = DUPLEX_HALF;
1521                 break;
1522
1523         case MII_TG3_AUX_STAT_1000FULL:
1524                 *speed = SPEED_1000;
1525                 *duplex = DUPLEX_FULL;
1526                 break;
1527
1528         default:
1529                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1530                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1531                                  SPEED_10;
1532                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1533                                   DUPLEX_HALF;
1534                         break;
1535                 }
1536                 *speed = SPEED_INVALID;
1537                 *duplex = DUPLEX_INVALID;
1538                 break;
1539         };
1540 }
1541
1542 static void tg3_phy_copper_begin(struct tg3 *tp)
1543 {
1544         u32 new_adv;
1545         int i;
1546
1547         if (tp->link_config.phy_is_low_power) {
1548                 /* Entering low power mode.  Disable gigabit and
1549                  * 100baseT advertisements.
1550                  */
1551                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1552
1553                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1554                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1555                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1556                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1557
1558                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1559         } else if (tp->link_config.speed == SPEED_INVALID) {
1560                 tp->link_config.advertising =
1561                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1562                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1563                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1564                          ADVERTISED_Autoneg | ADVERTISED_MII);
1565
1566                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1567                         tp->link_config.advertising &=
1568                                 ~(ADVERTISED_1000baseT_Half |
1569                                   ADVERTISED_1000baseT_Full);
1570
1571                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1572                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1573                         new_adv |= ADVERTISE_10HALF;
1574                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1575                         new_adv |= ADVERTISE_10FULL;
1576                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1577                         new_adv |= ADVERTISE_100HALF;
1578                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1579                         new_adv |= ADVERTISE_100FULL;
1580                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1581
1582                 if (tp->link_config.advertising &
1583                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1584                         new_adv = 0;
1585                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1586                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1587                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1588                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1589                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1590                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1591                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1592                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1593                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1594                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1595                 } else {
1596                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1597                 }
1598         } else {
1599                 /* Asking for a specific link mode. */
1600                 if (tp->link_config.speed == SPEED_1000) {
1601                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1602                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1603
1604                         if (tp->link_config.duplex == DUPLEX_FULL)
1605                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1606                         else
1607                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1608                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1609                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1610                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1611                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1612                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1613                 } else {
1614                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1615
1616                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1617                         if (tp->link_config.speed == SPEED_100) {
1618                                 if (tp->link_config.duplex == DUPLEX_FULL)
1619                                         new_adv |= ADVERTISE_100FULL;
1620                                 else
1621                                         new_adv |= ADVERTISE_100HALF;
1622                         } else {
1623                                 if (tp->link_config.duplex == DUPLEX_FULL)
1624                                         new_adv |= ADVERTISE_10FULL;
1625                                 else
1626                                         new_adv |= ADVERTISE_10HALF;
1627                         }
1628                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629                 }
1630         }
1631
1632         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1633             tp->link_config.speed != SPEED_INVALID) {
1634                 u32 bmcr, orig_bmcr;
1635
1636                 tp->link_config.active_speed = tp->link_config.speed;
1637                 tp->link_config.active_duplex = tp->link_config.duplex;
1638
1639                 bmcr = 0;
1640                 switch (tp->link_config.speed) {
1641                 default:
1642                 case SPEED_10:
1643                         break;
1644
1645                 case SPEED_100:
1646                         bmcr |= BMCR_SPEED100;
1647                         break;
1648
1649                 case SPEED_1000:
1650                         bmcr |= TG3_BMCR_SPEED1000;
1651                         break;
1652                 };
1653
1654                 if (tp->link_config.duplex == DUPLEX_FULL)
1655                         bmcr |= BMCR_FULLDPLX;
1656
1657                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1658                     (bmcr != orig_bmcr)) {
1659                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1660                         for (i = 0; i < 1500; i++) {
1661                                 u32 tmp;
1662
1663                                 udelay(10);
1664                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1665                                     tg3_readphy(tp, MII_BMSR, &tmp))
1666                                         continue;
1667                                 if (!(tmp & BMSR_LSTATUS)) {
1668                                         udelay(40);
1669                                         break;
1670                                 }
1671                         }
1672                         tg3_writephy(tp, MII_BMCR, bmcr);
1673                         udelay(40);
1674                 }
1675         } else {
1676                 tg3_writephy(tp, MII_BMCR,
1677                              BMCR_ANENABLE | BMCR_ANRESTART);
1678         }
1679 }
1680
1681 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1682 {
1683         int err;
1684
1685         /* Turn off tap power management. */
1686         /* Set Extended packet length bit */
1687         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1688
1689         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1690         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1691
1692         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1693         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1694
1695         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1696         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1697
1698         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1699         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1700
1701         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1702         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1703
1704         udelay(40);
1705
1706         return err;
1707 }
1708
1709 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1710 {
1711         u32 adv_reg, all_mask;
1712
1713         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1714                 return 0;
1715
1716         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1717                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1718         if ((adv_reg & all_mask) != all_mask)
1719                 return 0;
1720         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1721                 u32 tg3_ctrl;
1722
1723                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1724                         return 0;
1725
1726                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1727                             MII_TG3_CTRL_ADV_1000_FULL);
1728                 if ((tg3_ctrl & all_mask) != all_mask)
1729                         return 0;
1730         }
1731         return 1;
1732 }
1733
1734 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1735 {
1736         int current_link_up;
1737         u32 bmsr, dummy;
1738         u16 current_speed;
1739         u8 current_duplex;
1740         int i, err;
1741
1742         tw32(MAC_EVENT, 0);
1743
1744         tw32_f(MAC_STATUS,
1745              (MAC_STATUS_SYNC_CHANGED |
1746               MAC_STATUS_CFG_CHANGED |
1747               MAC_STATUS_MI_COMPLETION |
1748               MAC_STATUS_LNKSTATE_CHANGED));
1749         udelay(40);
1750
1751         tp->mi_mode = MAC_MI_MODE_BASE;
1752         tw32_f(MAC_MI_MODE, tp->mi_mode);
1753         udelay(80);
1754
1755         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1756
1757         /* Some third-party PHYs need to be reset on link going
1758          * down.
1759          */
1760         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1761              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1762              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1763             netif_carrier_ok(tp->dev)) {
1764                 tg3_readphy(tp, MII_BMSR, &bmsr);
1765                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1766                     !(bmsr & BMSR_LSTATUS))
1767                         force_reset = 1;
1768         }
1769         if (force_reset)
1770                 tg3_phy_reset(tp);
1771
1772         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1773                 tg3_readphy(tp, MII_BMSR, &bmsr);
1774                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1775                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1776                         bmsr = 0;
1777
1778                 if (!(bmsr & BMSR_LSTATUS)) {
1779                         err = tg3_init_5401phy_dsp(tp);
1780                         if (err)
1781                                 return err;
1782
1783                         tg3_readphy(tp, MII_BMSR, &bmsr);
1784                         for (i = 0; i < 1000; i++) {
1785                                 udelay(10);
1786                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1787                                     (bmsr & BMSR_LSTATUS)) {
1788                                         udelay(40);
1789                                         break;
1790                                 }
1791                         }
1792
1793                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1794                             !(bmsr & BMSR_LSTATUS) &&
1795                             tp->link_config.active_speed == SPEED_1000) {
1796                                 err = tg3_phy_reset(tp);
1797                                 if (!err)
1798                                         err = tg3_init_5401phy_dsp(tp);
1799                                 if (err)
1800                                         return err;
1801                         }
1802                 }
1803         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1804                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1805                 /* 5701 {A0,B0} CRC bug workaround */
1806                 tg3_writephy(tp, 0x15, 0x0a75);
1807                 tg3_writephy(tp, 0x1c, 0x8c68);
1808                 tg3_writephy(tp, 0x1c, 0x8d68);
1809                 tg3_writephy(tp, 0x1c, 0x8c68);
1810         }
1811
1812         /* Clear pending interrupts... */
1813         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1814         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1815
1816         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1817                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1818         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1819                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1820
1821         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1822             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1823                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1824                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1825                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1826                 else
1827                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1828         }
1829
1830         current_link_up = 0;
1831         current_speed = SPEED_INVALID;
1832         current_duplex = DUPLEX_INVALID;
1833
1834         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1835                 u32 val;
1836
1837                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1838                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1839                 if (!(val & (1 << 10))) {
1840                         val |= (1 << 10);
1841                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1842                         goto relink;
1843                 }
1844         }
1845
1846         bmsr = 0;
1847         for (i = 0; i < 100; i++) {
1848                 tg3_readphy(tp, MII_BMSR, &bmsr);
1849                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850                     (bmsr & BMSR_LSTATUS))
1851                         break;
1852                 udelay(40);
1853         }
1854
1855         if (bmsr & BMSR_LSTATUS) {
1856                 u32 aux_stat, bmcr;
1857
1858                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1859                 for (i = 0; i < 2000; i++) {
1860                         udelay(10);
1861                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1862                             aux_stat)
1863                                 break;
1864                 }
1865
1866                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1867                                              &current_speed,
1868                                              &current_duplex);
1869
1870                 bmcr = 0;
1871                 for (i = 0; i < 200; i++) {
1872                         tg3_readphy(tp, MII_BMCR, &bmcr);
1873                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1874                                 continue;
1875                         if (bmcr && bmcr != 0x7fff)
1876                                 break;
1877                         udelay(10);
1878                 }
1879
1880                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1881                         if (bmcr & BMCR_ANENABLE) {
1882                                 current_link_up = 1;
1883
1884                                 /* Force autoneg restart if we are exiting
1885                                  * low power mode.
1886                                  */
1887                                 if (!tg3_copper_is_advertising_all(tp))
1888                                         current_link_up = 0;
1889                         } else {
1890                                 current_link_up = 0;
1891                         }
1892                 } else {
1893                         if (!(bmcr & BMCR_ANENABLE) &&
1894                             tp->link_config.speed == current_speed &&
1895                             tp->link_config.duplex == current_duplex) {
1896                                 current_link_up = 1;
1897                         } else {
1898                                 current_link_up = 0;
1899                         }
1900                 }
1901
1902                 tp->link_config.active_speed = current_speed;
1903                 tp->link_config.active_duplex = current_duplex;
1904         }
1905
1906         if (current_link_up == 1 &&
1907             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1908             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1909                 u32 local_adv, remote_adv;
1910
1911                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1912                         local_adv = 0;
1913                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1914
1915                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1916                         remote_adv = 0;
1917
1918                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1919
1920                 /* If we are not advertising full pause capability,
1921                  * something is wrong.  Bring the link down and reconfigure.
1922                  */
1923                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1924                         current_link_up = 0;
1925                 } else {
1926                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1927                 }
1928         }
1929 relink:
1930         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1931                 u32 tmp;
1932
1933                 tg3_phy_copper_begin(tp);
1934
1935                 tg3_readphy(tp, MII_BMSR, &tmp);
1936                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1937                     (tmp & BMSR_LSTATUS))
1938                         current_link_up = 1;
1939         }
1940
1941         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1942         if (current_link_up == 1) {
1943                 if (tp->link_config.active_speed == SPEED_100 ||
1944                     tp->link_config.active_speed == SPEED_10)
1945                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1946                 else
1947                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1948         } else
1949                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1950
1951         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1952         if (tp->link_config.active_duplex == DUPLEX_HALF)
1953                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1954
1955         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1956         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1957                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1958                     (current_link_up == 1 &&
1959                      tp->link_config.active_speed == SPEED_10))
1960                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1961         } else {
1962                 if (current_link_up == 1)
1963                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1964         }
1965
1966         /* ??? Without this setting Netgear GA302T PHY does not
1967          * ??? send/receive packets...
1968          */
1969         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1970             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1971                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1972                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1973                 udelay(80);
1974         }
1975
1976         tw32_f(MAC_MODE, tp->mac_mode);
1977         udelay(40);
1978
1979         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1980                 /* Polled via timer. */
1981                 tw32_f(MAC_EVENT, 0);
1982         } else {
1983                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1984         }
1985         udelay(40);
1986
1987         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1988             current_link_up == 1 &&
1989             tp->link_config.active_speed == SPEED_1000 &&
1990             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1991              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1992                 udelay(120);
1993                 tw32_f(MAC_STATUS,
1994                      (MAC_STATUS_SYNC_CHANGED |
1995                       MAC_STATUS_CFG_CHANGED));
1996                 udelay(40);
1997                 tg3_write_mem(tp,
1998                               NIC_SRAM_FIRMWARE_MBOX,
1999                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2000         }
2001
2002         if (current_link_up != netif_carrier_ok(tp->dev)) {
2003                 if (current_link_up)
2004                         netif_carrier_on(tp->dev);
2005                 else
2006                         netif_carrier_off(tp->dev);
2007                 tg3_link_report(tp);
2008         }
2009
2010         return 0;
2011 }
2012
2013 struct tg3_fiber_aneginfo {
2014         int state;
2015 #define ANEG_STATE_UNKNOWN              0
2016 #define ANEG_STATE_AN_ENABLE            1
2017 #define ANEG_STATE_RESTART_INIT         2
2018 #define ANEG_STATE_RESTART              3
2019 #define ANEG_STATE_DISABLE_LINK_OK      4
2020 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2021 #define ANEG_STATE_ABILITY_DETECT       6
2022 #define ANEG_STATE_ACK_DETECT_INIT      7
2023 #define ANEG_STATE_ACK_DETECT           8
2024 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2025 #define ANEG_STATE_COMPLETE_ACK         10
2026 #define ANEG_STATE_IDLE_DETECT_INIT     11
2027 #define ANEG_STATE_IDLE_DETECT          12
2028 #define ANEG_STATE_LINK_OK              13
2029 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2030 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2031
2032         u32 flags;
2033 #define MR_AN_ENABLE            0x00000001
2034 #define MR_RESTART_AN           0x00000002
2035 #define MR_AN_COMPLETE          0x00000004
2036 #define MR_PAGE_RX              0x00000008
2037 #define MR_NP_LOADED            0x00000010
2038 #define MR_TOGGLE_TX            0x00000020
2039 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2040 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2041 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2042 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2043 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2044 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2045 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2046 #define MR_TOGGLE_RX            0x00002000
2047 #define MR_NP_RX                0x00004000
2048
2049 #define MR_LINK_OK              0x80000000
2050
2051         unsigned long link_time, cur_time;
2052
2053         u32 ability_match_cfg;
2054         int ability_match_count;
2055
2056         char ability_match, idle_match, ack_match;
2057
2058         u32 txconfig, rxconfig;
2059 #define ANEG_CFG_NP             0x00000080
2060 #define ANEG_CFG_ACK            0x00000040
2061 #define ANEG_CFG_RF2            0x00000020
2062 #define ANEG_CFG_RF1            0x00000010
2063 #define ANEG_CFG_PS2            0x00000001
2064 #define ANEG_CFG_PS1            0x00008000
2065 #define ANEG_CFG_HD             0x00004000
2066 #define ANEG_CFG_FD             0x00002000
2067 #define ANEG_CFG_INVAL          0x00001f06
2068
2069 };
2070 #define ANEG_OK         0
2071 #define ANEG_DONE       1
2072 #define ANEG_TIMER_ENAB 2
2073 #define ANEG_FAILED     -1
2074
2075 #define ANEG_STATE_SETTLE_TIME  10000
2076
2077 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2078                                    struct tg3_fiber_aneginfo *ap)
2079 {
2080         unsigned long delta;
2081         u32 rx_cfg_reg;
2082         int ret;
2083
2084         if (ap->state == ANEG_STATE_UNKNOWN) {
2085                 ap->rxconfig = 0;
2086                 ap->link_time = 0;
2087                 ap->cur_time = 0;
2088                 ap->ability_match_cfg = 0;
2089                 ap->ability_match_count = 0;
2090                 ap->ability_match = 0;
2091                 ap->idle_match = 0;
2092                 ap->ack_match = 0;
2093         }
2094         ap->cur_time++;
2095
2096         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2097                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2098
2099                 if (rx_cfg_reg != ap->ability_match_cfg) {
2100                         ap->ability_match_cfg = rx_cfg_reg;
2101                         ap->ability_match = 0;
2102                         ap->ability_match_count = 0;
2103                 } else {
2104                         if (++ap->ability_match_count > 1) {
2105                                 ap->ability_match = 1;
2106                                 ap->ability_match_cfg = rx_cfg_reg;
2107                         }
2108                 }
2109                 if (rx_cfg_reg & ANEG_CFG_ACK)
2110                         ap->ack_match = 1;
2111                 else
2112                         ap->ack_match = 0;
2113
2114                 ap->idle_match = 0;
2115         } else {
2116                 ap->idle_match = 1;
2117                 ap->ability_match_cfg = 0;
2118                 ap->ability_match_count = 0;
2119                 ap->ability_match = 0;
2120                 ap->ack_match = 0;
2121
2122                 rx_cfg_reg = 0;
2123         }
2124
2125         ap->rxconfig = rx_cfg_reg;
2126         ret = ANEG_OK;
2127
2128         switch(ap->state) {
2129         case ANEG_STATE_UNKNOWN:
2130                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2131                         ap->state = ANEG_STATE_AN_ENABLE;
2132
2133                 /* fallthru */
2134         case ANEG_STATE_AN_ENABLE:
2135                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2136                 if (ap->flags & MR_AN_ENABLE) {
2137                         ap->link_time = 0;
2138                         ap->cur_time = 0;
2139                         ap->ability_match_cfg = 0;
2140                         ap->ability_match_count = 0;
2141                         ap->ability_match = 0;
2142                         ap->idle_match = 0;
2143                         ap->ack_match = 0;
2144
2145                         ap->state = ANEG_STATE_RESTART_INIT;
2146                 } else {
2147                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2148                 }
2149                 break;
2150
2151         case ANEG_STATE_RESTART_INIT:
2152                 ap->link_time = ap->cur_time;
2153                 ap->flags &= ~(MR_NP_LOADED);
2154                 ap->txconfig = 0;
2155                 tw32(MAC_TX_AUTO_NEG, 0);
2156                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2157                 tw32_f(MAC_MODE, tp->mac_mode);
2158                 udelay(40);
2159
2160                 ret = ANEG_TIMER_ENAB;
2161                 ap->state = ANEG_STATE_RESTART;
2162
2163                 /* fallthru */
2164         case ANEG_STATE_RESTART:
2165                 delta = ap->cur_time - ap->link_time;
2166                 if (delta > ANEG_STATE_SETTLE_TIME) {
2167                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2168                 } else {
2169                         ret = ANEG_TIMER_ENAB;
2170                 }
2171                 break;
2172
2173         case ANEG_STATE_DISABLE_LINK_OK:
2174                 ret = ANEG_DONE;
2175                 break;
2176
2177         case ANEG_STATE_ABILITY_DETECT_INIT:
2178                 ap->flags &= ~(MR_TOGGLE_TX);
2179                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2180                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2181                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2182                 tw32_f(MAC_MODE, tp->mac_mode);
2183                 udelay(40);
2184
2185                 ap->state = ANEG_STATE_ABILITY_DETECT;
2186                 break;
2187
2188         case ANEG_STATE_ABILITY_DETECT:
2189                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2190                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2191                 }
2192                 break;
2193
2194         case ANEG_STATE_ACK_DETECT_INIT:
2195                 ap->txconfig |= ANEG_CFG_ACK;
2196                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2197                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2198                 tw32_f(MAC_MODE, tp->mac_mode);
2199                 udelay(40);
2200
2201                 ap->state = ANEG_STATE_ACK_DETECT;
2202
2203                 /* fallthru */
2204         case ANEG_STATE_ACK_DETECT:
2205                 if (ap->ack_match != 0) {
2206                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2207                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2208                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2209                         } else {
2210                                 ap->state = ANEG_STATE_AN_ENABLE;
2211                         }
2212                 } else if (ap->ability_match != 0 &&
2213                            ap->rxconfig == 0) {
2214                         ap->state = ANEG_STATE_AN_ENABLE;
2215                 }
2216                 break;
2217
2218         case ANEG_STATE_COMPLETE_ACK_INIT:
2219                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2220                         ret = ANEG_FAILED;
2221                         break;
2222                 }
2223                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2224                                MR_LP_ADV_HALF_DUPLEX |
2225                                MR_LP_ADV_SYM_PAUSE |
2226                                MR_LP_ADV_ASYM_PAUSE |
2227                                MR_LP_ADV_REMOTE_FAULT1 |
2228                                MR_LP_ADV_REMOTE_FAULT2 |
2229                                MR_LP_ADV_NEXT_PAGE |
2230                                MR_TOGGLE_RX |
2231                                MR_NP_RX);
2232                 if (ap->rxconfig & ANEG_CFG_FD)
2233                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2234                 if (ap->rxconfig & ANEG_CFG_HD)
2235                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2236                 if (ap->rxconfig & ANEG_CFG_PS1)
2237                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2238                 if (ap->rxconfig & ANEG_CFG_PS2)
2239                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2240                 if (ap->rxconfig & ANEG_CFG_RF1)
2241                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2242                 if (ap->rxconfig & ANEG_CFG_RF2)
2243                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2244                 if (ap->rxconfig & ANEG_CFG_NP)
2245                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2246
2247                 ap->link_time = ap->cur_time;
2248
2249                 ap->flags ^= (MR_TOGGLE_TX);
2250                 if (ap->rxconfig & 0x0008)
2251                         ap->flags |= MR_TOGGLE_RX;
2252                 if (ap->rxconfig & ANEG_CFG_NP)
2253                         ap->flags |= MR_NP_RX;
2254                 ap->flags |= MR_PAGE_RX;
2255
2256                 ap->state = ANEG_STATE_COMPLETE_ACK;
2257                 ret = ANEG_TIMER_ENAB;
2258                 break;
2259
2260         case ANEG_STATE_COMPLETE_ACK:
2261                 if (ap->ability_match != 0 &&
2262                     ap->rxconfig == 0) {
2263                         ap->state = ANEG_STATE_AN_ENABLE;
2264                         break;
2265                 }
2266                 delta = ap->cur_time - ap->link_time;
2267                 if (delta > ANEG_STATE_SETTLE_TIME) {
2268                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2269                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2270                         } else {
2271                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2272                                     !(ap->flags & MR_NP_RX)) {
2273                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2274                                 } else {
2275                                         ret = ANEG_FAILED;
2276                                 }
2277                         }
2278                 }
2279                 break;
2280
2281         case ANEG_STATE_IDLE_DETECT_INIT:
2282                 ap->link_time = ap->cur_time;
2283                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2284                 tw32_f(MAC_MODE, tp->mac_mode);
2285                 udelay(40);
2286
2287                 ap->state = ANEG_STATE_IDLE_DETECT;
2288                 ret = ANEG_TIMER_ENAB;
2289                 break;
2290
2291         case ANEG_STATE_IDLE_DETECT:
2292                 if (ap->ability_match != 0 &&
2293                     ap->rxconfig == 0) {
2294                         ap->state = ANEG_STATE_AN_ENABLE;
2295                         break;
2296                 }
2297                 delta = ap->cur_time - ap->link_time;
2298                 if (delta > ANEG_STATE_SETTLE_TIME) {
2299                         /* XXX another gem from the Broadcom driver :( */
2300                         ap->state = ANEG_STATE_LINK_OK;
2301                 }
2302                 break;
2303
2304         case ANEG_STATE_LINK_OK:
2305                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2306                 ret = ANEG_DONE;
2307                 break;
2308
2309         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2310                 /* ??? unimplemented */
2311                 break;
2312
2313         case ANEG_STATE_NEXT_PAGE_WAIT:
2314                 /* ??? unimplemented */
2315                 break;
2316
2317         default:
2318                 ret = ANEG_FAILED;
2319                 break;
2320         };
2321
2322         return ret;
2323 }
2324
2325 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2326 {
2327         int res = 0;
2328         struct tg3_fiber_aneginfo aninfo;
2329         int status = ANEG_FAILED;
2330         unsigned int tick;
2331         u32 tmp;
2332
2333         tw32_f(MAC_TX_AUTO_NEG, 0);
2334
2335         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2336         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2337         udelay(40);
2338
2339         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2340         udelay(40);
2341
2342         memset(&aninfo, 0, sizeof(aninfo));
2343         aninfo.flags |= MR_AN_ENABLE;
2344         aninfo.state = ANEG_STATE_UNKNOWN;
2345         aninfo.cur_time = 0;
2346         tick = 0;
2347         while (++tick < 195000) {
2348                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2349                 if (status == ANEG_DONE || status == ANEG_FAILED)
2350                         break;
2351
2352                 udelay(1);
2353         }
2354
2355         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2356         tw32_f(MAC_MODE, tp->mac_mode);
2357         udelay(40);
2358
2359         *flags = aninfo.flags;
2360
2361         if (status == ANEG_DONE &&
2362             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2363                              MR_LP_ADV_FULL_DUPLEX)))
2364                 res = 1;
2365
2366         return res;
2367 }
2368
2369 static void tg3_init_bcm8002(struct tg3 *tp)
2370 {
2371         u32 mac_status = tr32(MAC_STATUS);
2372         int i;
2373
2374         /* Reset when initting first time or we have a link. */
2375         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2376             !(mac_status & MAC_STATUS_PCS_SYNCED))
2377                 return;
2378
2379         /* Set PLL lock range. */
2380         tg3_writephy(tp, 0x16, 0x8007);
2381
2382         /* SW reset */
2383         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2384
2385         /* Wait for reset to complete. */
2386         /* XXX schedule_timeout() ... */
2387         for (i = 0; i < 500; i++)
2388                 udelay(10);
2389
2390         /* Config mode; select PMA/Ch 1 regs. */
2391         tg3_writephy(tp, 0x10, 0x8411);
2392
2393         /* Enable auto-lock and comdet, select txclk for tx. */
2394         tg3_writephy(tp, 0x11, 0x0a10);
2395
2396         tg3_writephy(tp, 0x18, 0x00a0);
2397         tg3_writephy(tp, 0x16, 0x41ff);
2398
2399         /* Assert and deassert POR. */
2400         tg3_writephy(tp, 0x13, 0x0400);
2401         udelay(40);
2402         tg3_writephy(tp, 0x13, 0x0000);
2403
2404         tg3_writephy(tp, 0x11, 0x0a50);
2405         udelay(40);
2406         tg3_writephy(tp, 0x11, 0x0a10);
2407
2408         /* Wait for signal to stabilize */
2409         /* XXX schedule_timeout() ... */
2410         for (i = 0; i < 15000; i++)
2411                 udelay(10);
2412
2413         /* Deselect the channel register so we can read the PHYID
2414          * later.
2415          */
2416         tg3_writephy(tp, 0x10, 0x8011);
2417 }
2418
2419 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2420 {
2421         u32 sg_dig_ctrl, sg_dig_status;
2422         u32 serdes_cfg, expected_sg_dig_ctrl;
2423         int workaround, port_a;
2424         int current_link_up;
2425
2426         serdes_cfg = 0;
2427         expected_sg_dig_ctrl = 0;
2428         workaround = 0;
2429         port_a = 1;
2430         current_link_up = 0;
2431
2432         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2433             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2434                 workaround = 1;
2435                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2436                         port_a = 0;
2437
2438                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2439                 /* preserve bits 20-23 for voltage regulator */
2440                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2441         }
2442
2443         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2444
2445         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2446                 if (sg_dig_ctrl & (1 << 31)) {
2447                         if (workaround) {
2448                                 u32 val = serdes_cfg;
2449
2450                                 if (port_a)
2451                                         val |= 0xc010000;
2452                                 else
2453                                         val |= 0x4010000;
2454                                 tw32_f(MAC_SERDES_CFG, val);
2455                         }
2456                         tw32_f(SG_DIG_CTRL, 0x01388400);
2457                 }
2458                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2459                         tg3_setup_flow_control(tp, 0, 0);
2460                         current_link_up = 1;
2461                 }
2462                 goto out;
2463         }
2464
2465         /* Want auto-negotiation.  */
2466         expected_sg_dig_ctrl = 0x81388400;
2467
2468         /* Pause capability */
2469         expected_sg_dig_ctrl |= (1 << 11);
2470
2471         /* Asymettric pause */
2472         expected_sg_dig_ctrl |= (1 << 12);
2473
2474         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2475                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2476                     tp->serdes_counter &&
2477                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2478                                     MAC_STATUS_RCVD_CFG)) ==
2479                      MAC_STATUS_PCS_SYNCED)) {
2480                         tp->serdes_counter--;
2481                         current_link_up = 1;
2482                         goto out;
2483                 }
2484 restart_autoneg:
2485                 if (workaround)
2486                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2487                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2488                 udelay(5);
2489                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2490
2491                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2492                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2493         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2494                                  MAC_STATUS_SIGNAL_DET)) {
2495                 sg_dig_status = tr32(SG_DIG_STATUS);
2496                 mac_status = tr32(MAC_STATUS);
2497
2498                 if ((sg_dig_status & (1 << 1)) &&
2499                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2500                         u32 local_adv, remote_adv;
2501
2502                         local_adv = ADVERTISE_PAUSE_CAP;
2503                         remote_adv = 0;
2504                         if (sg_dig_status & (1 << 19))
2505                                 remote_adv |= LPA_PAUSE_CAP;
2506                         if (sg_dig_status & (1 << 20))
2507                                 remote_adv |= LPA_PAUSE_ASYM;
2508
2509                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2510                         current_link_up = 1;
2511                         tp->serdes_counter = 0;
2512                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2513                 } else if (!(sg_dig_status & (1 << 1))) {
2514                         if (tp->serdes_counter)
2515                                 tp->serdes_counter--;
2516                         else {
2517                                 if (workaround) {
2518                                         u32 val = serdes_cfg;
2519
2520                                         if (port_a)
2521                                                 val |= 0xc010000;
2522                                         else
2523                                                 val |= 0x4010000;
2524
2525                                         tw32_f(MAC_SERDES_CFG, val);
2526                                 }
2527
2528                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2529                                 udelay(40);
2530
2531                                 /* Link parallel detection - link is up */
2532                                 /* only if we have PCS_SYNC and not */
2533                                 /* receiving config code words */
2534                                 mac_status = tr32(MAC_STATUS);
2535                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2536                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2537                                         tg3_setup_flow_control(tp, 0, 0);
2538                                         current_link_up = 1;
2539                                         tp->tg3_flags2 |=
2540                                                 TG3_FLG2_PARALLEL_DETECT;
2541                                         tp->serdes_counter =
2542                                                 SERDES_PARALLEL_DET_TIMEOUT;
2543                                 } else
2544                                         goto restart_autoneg;
2545                         }
2546                 }
2547         } else {
2548                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2549                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2550         }
2551
2552 out:
2553         return current_link_up;
2554 }
2555
2556 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2557 {
2558         int current_link_up = 0;
2559
2560         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2561                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2562                 goto out;
2563         }
2564
2565         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2566                 u32 flags;
2567                 int i;
2568
2569                 if (fiber_autoneg(tp, &flags)) {
2570                         u32 local_adv, remote_adv;
2571
2572                         local_adv = ADVERTISE_PAUSE_CAP;
2573                         remote_adv = 0;
2574                         if (flags & MR_LP_ADV_SYM_PAUSE)
2575                                 remote_adv |= LPA_PAUSE_CAP;
2576                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2577                                 remote_adv |= LPA_PAUSE_ASYM;
2578
2579                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2580
2581                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2582                         current_link_up = 1;
2583                 }
2584                 for (i = 0; i < 30; i++) {
2585                         udelay(20);
2586                         tw32_f(MAC_STATUS,
2587                                (MAC_STATUS_SYNC_CHANGED |
2588                                 MAC_STATUS_CFG_CHANGED));
2589                         udelay(40);
2590                         if ((tr32(MAC_STATUS) &
2591                              (MAC_STATUS_SYNC_CHANGED |
2592                               MAC_STATUS_CFG_CHANGED)) == 0)
2593                                 break;
2594                 }
2595
2596                 mac_status = tr32(MAC_STATUS);
2597                 if (current_link_up == 0 &&
2598                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2599                     !(mac_status & MAC_STATUS_RCVD_CFG))
2600                         current_link_up = 1;
2601         } else {
2602                 /* Forcing 1000FD link up. */
2603                 current_link_up = 1;
2604                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2605
2606                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2607                 udelay(40);
2608         }
2609
2610 out:
2611         return current_link_up;
2612 }
2613
2614 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2615 {
2616         u32 orig_pause_cfg;
2617         u16 orig_active_speed;
2618         u8 orig_active_duplex;
2619         u32 mac_status;
2620         int current_link_up;
2621         int i;
2622
2623         orig_pause_cfg =
2624                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2625                                   TG3_FLAG_TX_PAUSE));
2626         orig_active_speed = tp->link_config.active_speed;
2627         orig_active_duplex = tp->link_config.active_duplex;
2628
2629         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2630             netif_carrier_ok(tp->dev) &&
2631             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2632                 mac_status = tr32(MAC_STATUS);
2633                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2634                                MAC_STATUS_SIGNAL_DET |
2635                                MAC_STATUS_CFG_CHANGED |
2636                                MAC_STATUS_RCVD_CFG);
2637                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2638                                    MAC_STATUS_SIGNAL_DET)) {
2639                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2640                                             MAC_STATUS_CFG_CHANGED));
2641                         return 0;
2642                 }
2643         }
2644
2645         tw32_f(MAC_TX_AUTO_NEG, 0);
2646
2647         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2648         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2649         tw32_f(MAC_MODE, tp->mac_mode);
2650         udelay(40);
2651
2652         if (tp->phy_id == PHY_ID_BCM8002)
2653                 tg3_init_bcm8002(tp);
2654
2655         /* Enable link change event even when serdes polling.  */
2656         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2657         udelay(40);
2658
2659         current_link_up = 0;
2660         mac_status = tr32(MAC_STATUS);
2661
2662         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2663                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2664         else
2665                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2666
2667         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668         tw32_f(MAC_MODE, tp->mac_mode);
2669         udelay(40);
2670
2671         tp->hw_status->status =
2672                 (SD_STATUS_UPDATED |
2673                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2674
2675         for (i = 0; i < 100; i++) {
2676                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2677                                     MAC_STATUS_CFG_CHANGED));
2678                 udelay(5);
2679                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2680                                          MAC_STATUS_CFG_CHANGED |
2681                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2682                         break;
2683         }
2684
2685         mac_status = tr32(MAC_STATUS);
2686         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2687                 current_link_up = 0;
2688                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2689                     tp->serdes_counter == 0) {
2690                         tw32_f(MAC_MODE, (tp->mac_mode |
2691                                           MAC_MODE_SEND_CONFIGS));
2692                         udelay(1);
2693                         tw32_f(MAC_MODE, tp->mac_mode);
2694                 }
2695         }
2696
2697         if (current_link_up == 1) {
2698                 tp->link_config.active_speed = SPEED_1000;
2699                 tp->link_config.active_duplex = DUPLEX_FULL;
2700                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2701                                     LED_CTRL_LNKLED_OVERRIDE |
2702                                     LED_CTRL_1000MBPS_ON));
2703         } else {
2704                 tp->link_config.active_speed = SPEED_INVALID;
2705                 tp->link_config.active_duplex = DUPLEX_INVALID;
2706                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2707                                     LED_CTRL_LNKLED_OVERRIDE |
2708                                     LED_CTRL_TRAFFIC_OVERRIDE));
2709         }
2710
2711         if (current_link_up != netif_carrier_ok(tp->dev)) {
2712                 if (current_link_up)
2713                         netif_carrier_on(tp->dev);
2714                 else
2715                         netif_carrier_off(tp->dev);
2716                 tg3_link_report(tp);
2717         } else {
2718                 u32 now_pause_cfg =
2719                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2720                                          TG3_FLAG_TX_PAUSE);
2721                 if (orig_pause_cfg != now_pause_cfg ||
2722                     orig_active_speed != tp->link_config.active_speed ||
2723                     orig_active_duplex != tp->link_config.active_duplex)
2724                         tg3_link_report(tp);
2725         }
2726
2727         return 0;
2728 }
2729
2730 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2731 {
2732         int current_link_up, err = 0;
2733         u32 bmsr, bmcr;
2734         u16 current_speed;
2735         u8 current_duplex;
2736
2737         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2738         tw32_f(MAC_MODE, tp->mac_mode);
2739         udelay(40);
2740
2741         tw32(MAC_EVENT, 0);
2742
2743         tw32_f(MAC_STATUS,
2744              (MAC_STATUS_SYNC_CHANGED |
2745               MAC_STATUS_CFG_CHANGED |
2746               MAC_STATUS_MI_COMPLETION |
2747               MAC_STATUS_LNKSTATE_CHANGED));
2748         udelay(40);
2749
2750         if (force_reset)
2751                 tg3_phy_reset(tp);
2752
2753         current_link_up = 0;
2754         current_speed = SPEED_INVALID;
2755         current_duplex = DUPLEX_INVALID;
2756
2757         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2758         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2759         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2760                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2761                         bmsr |= BMSR_LSTATUS;
2762                 else
2763                         bmsr &= ~BMSR_LSTATUS;
2764         }
2765
2766         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2767
2768         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2769             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2770                 /* do nothing, just check for link up at the end */
2771         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2772                 u32 adv, new_adv;
2773
2774                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2775                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2776                                   ADVERTISE_1000XPAUSE |
2777                                   ADVERTISE_1000XPSE_ASYM |
2778                                   ADVERTISE_SLCT);
2779
2780                 /* Always advertise symmetric PAUSE just like copper */
2781                 new_adv |= ADVERTISE_1000XPAUSE;
2782
2783                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2784                         new_adv |= ADVERTISE_1000XHALF;
2785                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2786                         new_adv |= ADVERTISE_1000XFULL;
2787
2788                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2789                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2790                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2791                         tg3_writephy(tp, MII_BMCR, bmcr);
2792
2793                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2794                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2795                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2796
2797                         return err;
2798                 }
2799         } else {
2800                 u32 new_bmcr;
2801
2802                 bmcr &= ~BMCR_SPEED1000;
2803                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2804
2805                 if (tp->link_config.duplex == DUPLEX_FULL)
2806                         new_bmcr |= BMCR_FULLDPLX;
2807
2808                 if (new_bmcr != bmcr) {
2809                         /* BMCR_SPEED1000 is a reserved bit that needs
2810                          * to be set on write.
2811                          */
2812                         new_bmcr |= BMCR_SPEED1000;
2813
2814                         /* Force a linkdown */
2815                         if (netif_carrier_ok(tp->dev)) {
2816                                 u32 adv;
2817
2818                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2819                                 adv &= ~(ADVERTISE_1000XFULL |
2820                                          ADVERTISE_1000XHALF |
2821                                          ADVERTISE_SLCT);
2822                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2823                                 tg3_writephy(tp, MII_BMCR, bmcr |
2824                                                            BMCR_ANRESTART |
2825                                                            BMCR_ANENABLE);
2826                                 udelay(10);
2827                                 netif_carrier_off(tp->dev);
2828                         }
2829                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2830                         bmcr = new_bmcr;
2831                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2832                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2833                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2834                             ASIC_REV_5714) {
2835                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2836                                         bmsr |= BMSR_LSTATUS;
2837                                 else
2838                                         bmsr &= ~BMSR_LSTATUS;
2839                         }
2840                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2841                 }
2842         }
2843
2844         if (bmsr & BMSR_LSTATUS) {
2845                 current_speed = SPEED_1000;
2846                 current_link_up = 1;
2847                 if (bmcr & BMCR_FULLDPLX)
2848                         current_duplex = DUPLEX_FULL;
2849                 else
2850                         current_duplex = DUPLEX_HALF;
2851
2852                 if (bmcr & BMCR_ANENABLE) {
2853                         u32 local_adv, remote_adv, common;
2854
2855                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2856                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2857                         common = local_adv & remote_adv;
2858                         if (common & (ADVERTISE_1000XHALF |
2859                                       ADVERTISE_1000XFULL)) {
2860                                 if (common & ADVERTISE_1000XFULL)
2861                                         current_duplex = DUPLEX_FULL;
2862                                 else
2863                                         current_duplex = DUPLEX_HALF;
2864
2865                                 tg3_setup_flow_control(tp, local_adv,
2866                                                        remote_adv);
2867                         }
2868                         else
2869                                 current_link_up = 0;
2870                 }
2871         }
2872
2873         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2874         if (tp->link_config.active_duplex == DUPLEX_HALF)
2875                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2876
2877         tw32_f(MAC_MODE, tp->mac_mode);
2878         udelay(40);
2879
2880         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2881
2882         tp->link_config.active_speed = current_speed;
2883         tp->link_config.active_duplex = current_duplex;
2884
2885         if (current_link_up != netif_carrier_ok(tp->dev)) {
2886                 if (current_link_up)
2887                         netif_carrier_on(tp->dev);
2888                 else {
2889                         netif_carrier_off(tp->dev);
2890                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2891                 }
2892                 tg3_link_report(tp);
2893         }
2894         return err;
2895 }
2896
2897 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2898 {
2899         if (tp->serdes_counter) {
2900                 /* Give autoneg time to complete. */
2901                 tp->serdes_counter--;
2902                 return;
2903         }
2904         if (!netif_carrier_ok(tp->dev) &&
2905             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2906                 u32 bmcr;
2907
2908                 tg3_readphy(tp, MII_BMCR, &bmcr);
2909                 if (bmcr & BMCR_ANENABLE) {
2910                         u32 phy1, phy2;
2911
2912                         /* Select shadow register 0x1f */
2913                         tg3_writephy(tp, 0x1c, 0x7c00);
2914                         tg3_readphy(tp, 0x1c, &phy1);
2915
2916                         /* Select expansion interrupt status register */
2917                         tg3_writephy(tp, 0x17, 0x0f01);
2918                         tg3_readphy(tp, 0x15, &phy2);
2919                         tg3_readphy(tp, 0x15, &phy2);
2920
2921                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2922                                 /* We have signal detect and not receiving
2923                                  * config code words, link is up by parallel
2924                                  * detection.
2925                                  */
2926
2927                                 bmcr &= ~BMCR_ANENABLE;
2928                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2929                                 tg3_writephy(tp, MII_BMCR, bmcr);
2930                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2931                         }
2932                 }
2933         }
2934         else if (netif_carrier_ok(tp->dev) &&
2935                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2936                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2937                 u32 phy2;
2938
2939                 /* Select expansion interrupt status register */
2940                 tg3_writephy(tp, 0x17, 0x0f01);
2941                 tg3_readphy(tp, 0x15, &phy2);
2942                 if (phy2 & 0x20) {
2943                         u32 bmcr;
2944
2945                         /* Config code words received, turn on autoneg. */
2946                         tg3_readphy(tp, MII_BMCR, &bmcr);
2947                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2948
2949                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2950
2951                 }
2952         }
2953 }
2954
2955 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2956 {
2957         int err;
2958
2959         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2960                 err = tg3_setup_fiber_phy(tp, force_reset);
2961         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2962                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2963         } else {
2964                 err = tg3_setup_copper_phy(tp, force_reset);
2965         }
2966
2967         if (tp->link_config.active_speed == SPEED_1000 &&
2968             tp->link_config.active_duplex == DUPLEX_HALF)
2969                 tw32(MAC_TX_LENGTHS,
2970                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2971                       (6 << TX_LENGTHS_IPG_SHIFT) |
2972                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2973         else
2974                 tw32(MAC_TX_LENGTHS,
2975                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2976                       (6 << TX_LENGTHS_IPG_SHIFT) |
2977                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2978
2979         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2980                 if (netif_carrier_ok(tp->dev)) {
2981                         tw32(HOSTCC_STAT_COAL_TICKS,
2982                              tp->coal.stats_block_coalesce_usecs);
2983                 } else {
2984                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2985                 }
2986         }
2987
2988         return err;
2989 }
2990
2991 /* This is called whenever we suspect that the system chipset is re-
2992  * ordering the sequence of MMIO to the tx send mailbox. The symptom
2993  * is bogus tx completions. We try to recover by setting the
2994  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
2995  * in the workqueue.
2996  */
2997 static void tg3_tx_recover(struct tg3 *tp)
2998 {
2999         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3000                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3001
3002         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3003                "mapped I/O cycles to the network device, attempting to "
3004                "recover. Please report the problem to the driver maintainer "
3005                "and include system chipset information.\n", tp->dev->name);
3006
3007         spin_lock(&tp->lock);
3008         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3009         spin_unlock(&tp->lock);
3010 }
3011
3012 static inline u32 tg3_tx_avail(struct tg3 *tp)
3013 {
3014         smp_mb();
3015         return (tp->tx_pending -
3016                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3017 }
3018
3019 /* Tigon3 never reports partial packet sends.  So we do not
3020  * need special logic to handle SKBs that have not had all
3021  * of their frags sent yet, like SunGEM does.
3022  */
3023 static void tg3_tx(struct tg3 *tp)
3024 {
3025         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3026         u32 sw_idx = tp->tx_cons;
3027
3028         while (sw_idx != hw_idx) {
3029                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3030                 struct sk_buff *skb = ri->skb;
3031                 int i, tx_bug = 0;
3032
3033                 if (unlikely(skb == NULL)) {
3034                         tg3_tx_recover(tp);
3035                         return;
3036                 }
3037
3038                 pci_unmap_single(tp->pdev,
3039                                  pci_unmap_addr(ri, mapping),
3040                                  skb_headlen(skb),
3041                                  PCI_DMA_TODEVICE);
3042
3043                 ri->skb = NULL;
3044
3045                 sw_idx = NEXT_TX(sw_idx);
3046
3047                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3048                         ri = &tp->tx_buffers[sw_idx];
3049                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3050                                 tx_bug = 1;
3051
3052                         pci_unmap_page(tp->pdev,
3053                                        pci_unmap_addr(ri, mapping),
3054                                        skb_shinfo(skb)->frags[i].size,
3055                                        PCI_DMA_TODEVICE);
3056
3057                         sw_idx = NEXT_TX(sw_idx);
3058                 }
3059
3060                 dev_kfree_skb(skb);
3061
3062                 if (unlikely(tx_bug)) {
3063                         tg3_tx_recover(tp);
3064                         return;
3065                 }
3066         }
3067
3068         tp->tx_cons = sw_idx;
3069
3070         /* Need to make the tx_cons update visible to tg3_start_xmit()
3071          * before checking for netif_queue_stopped().  Without the
3072          * memory barrier, there is a small possibility that tg3_start_xmit()
3073          * will miss it and cause the queue to be stopped forever.
3074          */
3075         smp_mb();
3076
3077         if (unlikely(netif_queue_stopped(tp->dev) &&
3078                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3079                 netif_tx_lock(tp->dev);
3080                 if (netif_queue_stopped(tp->dev) &&
3081                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3082                         netif_wake_queue(tp->dev);
3083                 netif_tx_unlock(tp->dev);
3084         }
3085 }
3086
3087 /* Returns size of skb allocated or < 0 on error.
3088  *
3089  * We only need to fill in the address because the other members
3090  * of the RX descriptor are invariant, see tg3_init_rings.
3091  *
3092  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3093  * posting buffers we only dirty the first cache line of the RX
3094  * descriptor (containing the address).  Whereas for the RX status
3095  * buffers the cpu only reads the last cacheline of the RX descriptor
3096  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3097  */
3098 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3099                             int src_idx, u32 dest_idx_unmasked)
3100 {
3101         struct tg3_rx_buffer_desc *desc;
3102         struct ring_info *map, *src_map;
3103         struct sk_buff *skb;
3104         dma_addr_t mapping;
3105         int skb_size, dest_idx;
3106
3107         src_map = NULL;
3108         switch (opaque_key) {
3109         case RXD_OPAQUE_RING_STD:
3110                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3111                 desc = &tp->rx_std[dest_idx];
3112                 map = &tp->rx_std_buffers[dest_idx];
3113                 if (src_idx >= 0)
3114                         src_map = &tp->rx_std_buffers[src_idx];
3115                 skb_size = tp->rx_pkt_buf_sz;
3116                 break;
3117
3118         case RXD_OPAQUE_RING_JUMBO:
3119                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3120                 desc = &tp->rx_jumbo[dest_idx];
3121                 map = &tp->rx_jumbo_buffers[dest_idx];
3122                 if (src_idx >= 0)
3123                         src_map = &tp->rx_jumbo_buffers[src_idx];
3124                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3125                 break;
3126
3127         default:
3128                 return -EINVAL;
3129         };
3130
3131         /* Do not overwrite any of the map or rp information
3132          * until we are sure we can commit to a new buffer.
3133          *
3134          * Callers depend upon this behavior and assume that
3135          * we leave everything unchanged if we fail.
3136          */
3137         skb = netdev_alloc_skb(tp->dev, skb_size);
3138         if (skb == NULL)
3139                 return -ENOMEM;
3140
3141         skb_reserve(skb, tp->rx_offset);
3142
3143         mapping = pci_map_single(tp->pdev, skb->data,
3144                                  skb_size - tp->rx_offset,
3145                                  PCI_DMA_FROMDEVICE);
3146
3147         map->skb = skb;
3148         pci_unmap_addr_set(map, mapping, mapping);
3149
3150         if (src_map != NULL)
3151                 src_map->skb = NULL;
3152
3153         desc->addr_hi = ((u64)mapping >> 32);
3154         desc->addr_lo = ((u64)mapping & 0xffffffff);
3155
3156         return skb_size;
3157 }
3158
3159 /* We only need to move over in the address because the other
3160  * members of the RX descriptor are invariant.  See notes above
3161  * tg3_alloc_rx_skb for full details.
3162  */
3163 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3164                            int src_idx, u32 dest_idx_unmasked)
3165 {
3166         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3167         struct ring_info *src_map, *dest_map;
3168         int dest_idx;
3169
3170         switch (opaque_key) {
3171         case RXD_OPAQUE_RING_STD:
3172                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3173                 dest_desc = &tp->rx_std[dest_idx];
3174                 dest_map = &tp->rx_std_buffers[dest_idx];
3175                 src_desc = &tp->rx_std[src_idx];
3176                 src_map = &tp->rx_std_buffers[src_idx];
3177                 break;
3178
3179         case RXD_OPAQUE_RING_JUMBO:
3180                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3181                 dest_desc = &tp->rx_jumbo[dest_idx];
3182                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3183                 src_desc = &tp->rx_jumbo[src_idx];
3184                 src_map = &tp->rx_jumbo_buffers[src_idx];
3185                 break;
3186
3187         default:
3188                 return;
3189         };
3190
3191         dest_map->skb = src_map->skb;
3192         pci_unmap_addr_set(dest_map, mapping,
3193                            pci_unmap_addr(src_map, mapping));
3194         dest_desc->addr_hi = src_desc->addr_hi;
3195         dest_desc->addr_lo = src_desc->addr_lo;
3196
3197         src_map->skb = NULL;
3198 }
3199
3200 #if TG3_VLAN_TAG_USED
3201 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3202 {
3203         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3204 }
3205 #endif
3206
3207 /* The RX ring scheme is composed of multiple rings which post fresh
3208  * buffers to the chip, and one special ring the chip uses to report
3209  * status back to the host.
3210  *
3211  * The special ring reports the status of received packets to the
3212  * host.  The chip does not write into the original descriptor the
3213  * RX buffer was obtained from.  The chip simply takes the original
3214  * descriptor as provided by the host, updates the status and length
3215  * field, then writes this into the next status ring entry.
3216  *
3217  * Each ring the host uses to post buffers to the chip is described
3218  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3219  * it is first placed into the on-chip ram.  When the packet's length
3220  * is known, it walks down the TG3_BDINFO entries to select the ring.
3221  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3222  * which is within the range of the new packet's length is chosen.
3223  *
3224  * The "separate ring for rx status" scheme may sound queer, but it makes
3225  * sense from a cache coherency perspective.  If only the host writes
3226  * to the buffer post rings, and only the chip writes to the rx status
3227  * rings, then cache lines never move beyond shared-modified state.
3228  * If both the host and chip were to write into the same ring, cache line
3229  * eviction could occur since both entities want it in an exclusive state.
3230  */
3231 static int tg3_rx(struct tg3 *tp, int budget)
3232 {
3233         u32 work_mask, rx_std_posted = 0;
3234         u32 sw_idx = tp->rx_rcb_ptr;
3235         u16 hw_idx;
3236         int received;
3237
3238         hw_idx = tp->hw_status->idx[0].rx_producer;
3239         /*
3240          * We need to order the read of hw_idx and the read of
3241          * the opaque cookie.
3242          */
3243         rmb();
3244         work_mask = 0;
3245         received = 0;
3246         while (sw_idx != hw_idx && budget > 0) {
3247                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3248                 unsigned int len;
3249                 struct sk_buff *skb;
3250                 dma_addr_t dma_addr;
3251                 u32 opaque_key, desc_idx, *post_ptr;
3252
3253                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3254                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3255                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3256                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3257                                                   mapping);
3258                         skb = tp->rx_std_buffers[desc_idx].skb;
3259                         post_ptr = &tp->rx_std_ptr;
3260                         rx_std_posted++;
3261                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3262                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3263                                                   mapping);
3264                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3265                         post_ptr = &tp->rx_jumbo_ptr;
3266                 }
3267                 else {
3268                         goto next_pkt_nopost;
3269                 }
3270
3271                 work_mask |= opaque_key;
3272
3273                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3274                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3275                 drop_it:
3276                         tg3_recycle_rx(tp, opaque_key,
3277                                        desc_idx, *post_ptr);
3278                 drop_it_no_recycle:
3279                         /* Other statistics kept track of by card. */
3280                         tp->net_stats.rx_dropped++;
3281                         goto next_pkt;
3282                 }
3283
3284                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3285
3286                 if (len > RX_COPY_THRESHOLD
3287                         && tp->rx_offset == 2
3288                         /* rx_offset != 2 iff this is a 5701 card running
3289                          * in PCI-X mode [see tg3_get_invariants()] */
3290                 ) {
3291                         int skb_size;
3292
3293                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3294                                                     desc_idx, *post_ptr);
3295                         if (skb_size < 0)
3296                                 goto drop_it;
3297
3298                         pci_unmap_single(tp->pdev, dma_addr,
3299                                          skb_size - tp->rx_offset,
3300                                          PCI_DMA_FROMDEVICE);
3301
3302                         skb_put(skb, len);
3303                 } else {
3304                         struct sk_buff *copy_skb;
3305
3306                         tg3_recycle_rx(tp, opaque_key,
3307                                        desc_idx, *post_ptr);
3308
3309                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3310                         if (copy_skb == NULL)
3311                                 goto drop_it_no_recycle;
3312
3313                         skb_reserve(copy_skb, 2);
3314                         skb_put(copy_skb, len);
3315                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3316                         memcpy(copy_skb->data, skb->data, len);
3317                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3318
3319                         /* We'll reuse the original ring buffer. */
3320                         skb = copy_skb;
3321                 }
3322
3323                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3324                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3325                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3326                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3327                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3328                 else
3329                         skb->ip_summed = CHECKSUM_NONE;
3330
3331                 skb->protocol = eth_type_trans(skb, tp->dev);
3332 #if TG3_VLAN_TAG_USED
3333                 if (tp->vlgrp != NULL &&
3334                     desc->type_flags & RXD_FLAG_VLAN) {
3335                         tg3_vlan_rx(tp, skb,
3336                                     desc->err_vlan & RXD_VLAN_MASK);
3337                 } else
3338 #endif
3339                         netif_receive_skb(skb);
3340
3341                 tp->dev->last_rx = jiffies;
3342                 received++;
3343                 budget--;
3344
3345 next_pkt:
3346                 (*post_ptr)++;
3347
3348                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3349                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3350
3351                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3352                                      TG3_64BIT_REG_LOW, idx);
3353                         work_mask &= ~RXD_OPAQUE_RING_STD;
3354                         rx_std_posted = 0;
3355                 }
3356 next_pkt_nopost:
3357                 sw_idx++;
3358                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3359
3360                 /* Refresh hw_idx to see if there is new work */
3361                 if (sw_idx == hw_idx) {
3362                         hw_idx = tp->hw_status->idx[0].rx_producer;
3363                         rmb();
3364                 }
3365         }
3366
3367         /* ACK the status ring. */
3368         tp->rx_rcb_ptr = sw_idx;
3369         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3370
3371         /* Refill RX ring(s). */
3372         if (work_mask & RXD_OPAQUE_RING_STD) {
3373                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3374                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3375                              sw_idx);
3376         }
3377         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3378                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3379                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3380                              sw_idx);
3381         }
3382         mmiowb();
3383
3384         return received;
3385 }
3386
3387 static int tg3_poll(struct net_device *netdev, int *budget)
3388 {
3389         struct tg3 *tp = netdev_priv(netdev);
3390         struct tg3_hw_status *sblk = tp->hw_status;
3391         int done;
3392
3393         /* handle link change and other phy events */
3394         if (!(tp->tg3_flags &
3395               (TG3_FLAG_USE_LINKCHG_REG |
3396                TG3_FLAG_POLL_SERDES))) {
3397                 if (sblk->status & SD_STATUS_LINK_CHG) {
3398                         sblk->status = SD_STATUS_UPDATED |
3399                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3400                         spin_lock(&tp->lock);
3401                         tg3_setup_phy(tp, 0);
3402                         spin_unlock(&tp->lock);
3403                 }
3404         }
3405
3406         /* run TX completion thread */
3407         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3408                 tg3_tx(tp);
3409                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3410                         netif_rx_complete(netdev);
3411                         schedule_work(&tp->reset_task);
3412                         return 0;
3413                 }
3414         }
3415
3416         /* run RX thread, within the bounds set by NAPI.
3417          * All RX "locking" is done by ensuring outside
3418          * code synchronizes with dev->poll()
3419          */
3420         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3421                 int orig_budget = *budget;
3422                 int work_done;
3423
3424                 if (orig_budget > netdev->quota)
3425                         orig_budget = netdev->quota;
3426
3427                 work_done = tg3_rx(tp, orig_budget);
3428
3429                 *budget -= work_done;
3430                 netdev->quota -= work_done;
3431         }
3432
3433         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3434                 tp->last_tag = sblk->status_tag;
3435                 rmb();
3436         } else
3437                 sblk->status &= ~SD_STATUS_UPDATED;
3438
3439         /* if no more work, tell net stack and NIC we're done */
3440         done = !tg3_has_work(tp);
3441         if (done) {
3442                 netif_rx_complete(netdev);
3443                 tg3_restart_ints(tp);
3444         }
3445
3446         return (done ? 0 : 1);
3447 }
3448
3449 static void tg3_irq_quiesce(struct tg3 *tp)
3450 {
3451         BUG_ON(tp->irq_sync);
3452
3453         tp->irq_sync = 1;
3454         smp_mb();
3455
3456         synchronize_irq(tp->pdev->irq);
3457 }
3458
3459 static inline int tg3_irq_sync(struct tg3 *tp)
3460 {
3461         return tp->irq_sync;
3462 }
3463
3464 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3465  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3466  * with as well.  Most of the time, this is not necessary except when
3467  * shutting down the device.
3468  */
3469 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3470 {
3471         if (irq_sync)
3472                 tg3_irq_quiesce(tp);
3473         spin_lock_bh(&tp->lock);
3474 }
3475
3476 static inline void tg3_full_unlock(struct tg3 *tp)
3477 {
3478         spin_unlock_bh(&tp->lock);
3479 }
3480
3481 /* One-shot MSI handler - Chip automatically disables interrupt
3482  * after sending MSI so driver doesn't have to do it.
3483  */
3484 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3485 {
3486         struct net_device *dev = dev_id;
3487         struct tg3 *tp = netdev_priv(dev);
3488
3489         prefetch(tp->hw_status);
3490         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3491
3492         if (likely(!tg3_irq_sync(tp)))
3493                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3494
3495         return IRQ_HANDLED;
3496 }
3497
3498 /* MSI ISR - No need to check for interrupt sharing and no need to
3499  * flush status block and interrupt mailbox. PCI ordering rules
3500  * guarantee that MSI will arrive after the status block.
3501  */
3502 static irqreturn_t tg3_msi(int irq, void *dev_id)
3503 {
3504         struct net_device *dev = dev_id;
3505         struct tg3 *tp = netdev_priv(dev);
3506
3507         prefetch(tp->hw_status);
3508         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3509         /*
3510          * Writing any value to intr-mbox-0 clears PCI INTA# and
3511          * chip-internal interrupt pending events.
3512          * Writing non-zero to intr-mbox-0 additional tells the
3513          * NIC to stop sending us irqs, engaging "in-intr-handler"
3514          * event coalescing.
3515          */
3516         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3517         if (likely(!tg3_irq_sync(tp)))
3518                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3519
3520         return IRQ_RETVAL(1);
3521 }
3522
3523 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3524 {
3525         struct net_device *dev = dev_id;
3526         struct tg3 *tp = netdev_priv(dev);
3527         struct tg3_hw_status *sblk = tp->hw_status;
3528         unsigned int handled = 1;
3529
3530         /* In INTx mode, it is possible for the interrupt to arrive at
3531          * the CPU before the status block posted prior to the interrupt.
3532          * Reading the PCI State register will confirm whether the
3533          * interrupt is ours and will flush the status block.
3534          */
3535         if ((sblk->status & SD_STATUS_UPDATED) ||
3536             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3537                 /*
3538                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3539                  * chip-internal interrupt pending events.
3540                  * Writing non-zero to intr-mbox-0 additional tells the
3541                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3542                  * event coalescing.
3543                  */
3544                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3545                              0x00000001);
3546                 if (tg3_irq_sync(tp))
3547                         goto out;
3548                 sblk->status &= ~SD_STATUS_UPDATED;
3549                 if (likely(tg3_has_work(tp))) {
3550                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3551                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3552                 } else {
3553                         /* No work, shared interrupt perhaps?  re-enable
3554                          * interrupts, and flush that PCI write
3555                          */
3556                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3557                                 0x00000000);
3558                 }
3559         } else {        /* shared interrupt */
3560                 handled = 0;
3561         }
3562 out:
3563         return IRQ_RETVAL(handled);
3564 }
3565
3566 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3567 {
3568         struct net_device *dev = dev_id;
3569         struct tg3 *tp = netdev_priv(dev);
3570         struct tg3_hw_status *sblk = tp->hw_status;
3571         unsigned int handled = 1;
3572
3573         /* In INTx mode, it is possible for the interrupt to arrive at
3574          * the CPU before the status block posted prior to the interrupt.
3575          * Reading the PCI State register will confirm whether the
3576          * interrupt is ours and will flush the status block.
3577          */
3578         if ((sblk->status_tag != tp->last_tag) ||
3579             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3580                 /*
3581                  * writing any value to intr-mbox-0 clears PCI INTA# and
3582                  * chip-internal interrupt pending events.
3583                  * writing non-zero to intr-mbox-0 additional tells the
3584                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3585                  * event coalescing.
3586                  */
3587                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3588                              0x00000001);
3589                 if (tg3_irq_sync(tp))
3590                         goto out;
3591                 if (netif_rx_schedule_prep(dev)) {
3592                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3593                         /* Update last_tag to mark that this status has been
3594                          * seen. Because interrupt may be shared, we may be
3595                          * racing with tg3_poll(), so only update last_tag
3596                          * if tg3_poll() is not scheduled.
3597                          */
3598                         tp->last_tag = sblk->status_tag;
3599                         __netif_rx_schedule(dev);
3600                 }
3601         } else {        /* shared interrupt */
3602                 handled = 0;
3603         }
3604 out:
3605         return IRQ_RETVAL(handled);
3606 }
3607
3608 /* ISR for interrupt test */
3609 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3610 {
3611         struct net_device *dev = dev_id;
3612         struct tg3 *tp = netdev_priv(dev);
3613         struct tg3_hw_status *sblk = tp->hw_status;
3614
3615         if ((sblk->status & SD_STATUS_UPDATED) ||
3616             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3617                 tg3_disable_ints(tp);
3618                 return IRQ_RETVAL(1);
3619         }
3620         return IRQ_RETVAL(0);
3621 }
3622
3623 static int tg3_init_hw(struct tg3 *, int);
3624 static int tg3_halt(struct tg3 *, int, int);
3625
3626 /* Restart hardware after configuration changes, self-test, etc.
3627  * Invoked with tp->lock held.
3628  */
3629 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3630 {
3631         int err;
3632
3633         err = tg3_init_hw(tp, reset_phy);
3634         if (err) {
3635                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3636                        "aborting.\n", tp->dev->name);
3637                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3638                 tg3_full_unlock(tp);
3639                 del_timer_sync(&tp->timer);
3640                 tp->irq_sync = 0;
3641                 netif_poll_enable(tp->dev);
3642                 dev_close(tp->dev);
3643                 tg3_full_lock(tp, 0);
3644         }
3645         return err;
3646 }
3647
3648 #ifdef CONFIG_NET_POLL_CONTROLLER
3649 static void tg3_poll_controller(struct net_device *dev)
3650 {
3651         struct tg3 *tp = netdev_priv(dev);
3652
3653         tg3_interrupt(tp->pdev->irq, dev);
3654 }
3655 #endif
3656
3657 static void tg3_reset_task(void *_data)
3658 {
3659         struct tg3 *tp = _data;
3660         unsigned int restart_timer;
3661
3662         tg3_full_lock(tp, 0);
3663         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3664
3665         if (!netif_running(tp->dev)) {
3666                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3667                 tg3_full_unlock(tp);
3668                 return;
3669         }
3670
3671         tg3_full_unlock(tp);
3672
3673         tg3_netif_stop(tp);
3674
3675         tg3_full_lock(tp, 1);
3676
3677         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3678         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3679
3680         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3681                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3682                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3683                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3684                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3685         }
3686
3687         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3688         if (tg3_init_hw(tp, 1))
3689                 goto out;
3690
3691         tg3_netif_start(tp);
3692
3693         if (restart_timer)
3694                 mod_timer(&tp->timer, jiffies + 1);
3695
3696 out:
3697         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3698
3699         tg3_full_unlock(tp);
3700 }
3701
3702 static void tg3_tx_timeout(struct net_device *dev)
3703 {
3704         struct tg3 *tp = netdev_priv(dev);
3705
3706         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3707                dev->name);
3708
3709         schedule_work(&tp->reset_task);
3710 }
3711
3712 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3713 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3714 {
3715         u32 base = (u32) mapping & 0xffffffff;
3716
3717         return ((base > 0xffffdcc0) &&
3718                 (base + len + 8 < base));
3719 }
3720
3721 /* Test for DMA addresses > 40-bit */
3722 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3723                                           int len)
3724 {
3725 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3726         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3727                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3728         return 0;
3729 #else
3730         return 0;
3731 #endif
3732 }
3733
3734 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3735
3736 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3737 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3738                                        u32 last_plus_one, u32 *start,
3739                                        u32 base_flags, u32 mss)
3740 {
3741         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3742         dma_addr_t new_addr = 0;
3743         u32 entry = *start;
3744         int i, ret = 0;
3745
3746         if (!new_skb) {
3747                 ret = -1;
3748         } else {
3749                 /* New SKB is guaranteed to be linear. */
3750                 entry = *start;
3751                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3752                                           PCI_DMA_TODEVICE);
3753                 /* Make sure new skb does not cross any 4G boundaries.
3754                  * Drop the packet if it does.
3755                  */
3756                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3757                         ret = -1;
3758                         dev_kfree_skb(new_skb);
3759                         new_skb = NULL;
3760                 } else {
3761                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3762                                     base_flags, 1 | (mss << 1));
3763                         *start = NEXT_TX(entry);
3764                 }
3765         }
3766
3767         /* Now clean up the sw ring entries. */
3768         i = 0;
3769         while (entry != last_plus_one) {
3770                 int len;
3771
3772                 if (i == 0)
3773                         len = skb_headlen(skb);
3774                 else
3775                         len = skb_shinfo(skb)->frags[i-1].size;
3776                 pci_unmap_single(tp->pdev,
3777                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3778                                  len, PCI_DMA_TODEVICE);
3779                 if (i == 0) {
3780                         tp->tx_buffers[entry].skb = new_skb;
3781                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3782                 } else {
3783                         tp->tx_buffers[entry].skb = NULL;
3784                 }
3785                 entry = NEXT_TX(entry);
3786                 i++;
3787         }
3788
3789         dev_kfree_skb(skb);
3790
3791         return ret;
3792 }
3793
3794 static void tg3_set_txd(struct tg3 *tp, int entry,
3795                         dma_addr_t mapping, int len, u32 flags,
3796                         u32 mss_and_is_end)
3797 {
3798         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3799         int is_end = (mss_and_is_end & 0x1);
3800         u32 mss = (mss_and_is_end >> 1);
3801         u32 vlan_tag = 0;
3802
3803         if (is_end)
3804                 flags |= TXD_FLAG_END;
3805         if (flags & TXD_FLAG_VLAN) {
3806                 vlan_tag = flags >> 16;
3807                 flags &= 0xffff;
3808         }
3809         vlan_tag |= (mss << TXD_MSS_SHIFT);
3810
3811         txd->addr_hi = ((u64) mapping >> 32);
3812         txd->addr_lo = ((u64) mapping & 0xffffffff);
3813         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3814         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3815 }
3816
3817 /* hard_start_xmit for devices that don't have any bugs and
3818  * support TG3_FLG2_HW_TSO_2 only.
3819  */
3820 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3821 {
3822         struct tg3 *tp = netdev_priv(dev);
3823         dma_addr_t mapping;
3824         u32 len, entry, base_flags, mss;
3825
3826         len = skb_headlen(skb);
3827
3828         /* We are running in BH disabled context with netif_tx_lock
3829          * and TX reclaim runs via tp->poll inside of a software
3830          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3831          * no IRQ context deadlocks to worry about either.  Rejoice!
3832          */
3833         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3834                 if (!netif_queue_stopped(dev)) {
3835                         netif_stop_queue(dev);
3836
3837                         /* This is a hard error, log it. */
3838                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3839                                "queue awake!\n", dev->name);
3840                 }
3841                 return NETDEV_TX_BUSY;
3842         }
3843
3844         entry = tp->tx_prod;
3845         base_flags = 0;
3846 #if TG3_TSO_SUPPORT != 0
3847         mss = 0;
3848         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3849             (mss = skb_shinfo(skb)->gso_size) != 0) {
3850                 int tcp_opt_len, ip_tcp_len;
3851
3852                 if (skb_header_cloned(skb) &&
3853                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3854                         dev_kfree_skb(skb);
3855                         goto out_unlock;
3856                 }
3857
3858                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3859                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3860                 else {
3861                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3862                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3863                                      sizeof(struct tcphdr);
3864
3865                         skb->nh.iph->check = 0;
3866                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3867                                                      tcp_opt_len);
3868                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3869                 }
3870
3871                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3872                                TXD_FLAG_CPU_POST_DMA);
3873
3874                 skb->h.th->check = 0;
3875
3876         }
3877         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3878                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3879 #else
3880         mss = 0;
3881         if (skb->ip_summed == CHECKSUM_PARTIAL)
3882                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3883 #endif
3884 #if TG3_VLAN_TAG_USED
3885         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3886                 base_flags |= (TXD_FLAG_VLAN |
3887                                (vlan_tx_tag_get(skb) << 16));
3888 #endif
3889
3890         /* Queue skb data, a.k.a. the main skb fragment. */
3891         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3892
3893         tp->tx_buffers[entry].skb = skb;
3894         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3895
3896         tg3_set_txd(tp, entry, mapping, len, base_flags,
3897                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3898
3899         entry = NEXT_TX(entry);
3900
3901         /* Now loop through additional data fragments, and queue them. */
3902         if (skb_shinfo(skb)->nr_frags > 0) {
3903                 unsigned int i, last;
3904
3905                 last = skb_shinfo(skb)->nr_frags - 1;
3906                 for (i = 0; i <= last; i++) {
3907                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3908
3909                         len = frag->size;
3910                         mapping = pci_map_page(tp->pdev,
3911                                                frag->page,
3912                                                frag->page_offset,
3913                                                len, PCI_DMA_TODEVICE);
3914
3915                         tp->tx_buffers[entry].skb = NULL;
3916                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3917
3918                         tg3_set_txd(tp, entry, mapping, len,
3919                                     base_flags, (i == last) | (mss << 1));
3920
3921                         entry = NEXT_TX(entry);
3922                 }
3923         }
3924
3925         /* Packets are ready, update Tx producer idx local and on card. */
3926         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3927
3928         tp->tx_prod = entry;
3929         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3930                 netif_stop_queue(dev);
3931                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3932                         netif_wake_queue(tp->dev);
3933         }
3934
3935 out_unlock:
3936         mmiowb();
3937
3938         dev->trans_start = jiffies;
3939
3940         return NETDEV_TX_OK;
3941 }
3942
3943 #if TG3_TSO_SUPPORT != 0
3944 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3945
3946 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3947  * TSO header is greater than 80 bytes.
3948  */
3949 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3950 {
3951         struct sk_buff *segs, *nskb;
3952
3953         /* Estimate the number of fragments in the worst case */
3954         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3955                 netif_stop_queue(tp->dev);
3956                 return NETDEV_TX_BUSY;
3957         }
3958
3959         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3960         if (unlikely(IS_ERR(segs)))
3961                 goto tg3_tso_bug_end;
3962
3963         do {
3964                 nskb = segs;
3965                 segs = segs->next;
3966                 nskb->next = NULL;
3967                 tg3_start_xmit_dma_bug(nskb, tp->dev);
3968         } while (segs);
3969
3970 tg3_tso_bug_end:
3971         dev_kfree_skb(skb);
3972
3973         return NETDEV_TX_OK;
3974 }
3975 #endif
3976
3977 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3978  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3979  */
3980 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3981 {
3982         struct tg3 *tp = netdev_priv(dev);
3983         dma_addr_t mapping;
3984         u32 len, entry, base_flags, mss;
3985         int would_hit_hwbug;
3986
3987         len = skb_headlen(skb);
3988
3989         /* We are running in BH disabled context with netif_tx_lock
3990          * and TX reclaim runs via tp->poll inside of a software
3991          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3992          * no IRQ context deadlocks to worry about either.  Rejoice!
3993          */
3994         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3995                 if (!netif_queue_stopped(dev)) {
3996                         netif_stop_queue(dev);
3997
3998                         /* This is a hard error, log it. */
3999                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4000                                "queue awake!\n", dev->name);
4001                 }
4002                 return NETDEV_TX_BUSY;
4003         }
4004
4005         entry = tp->tx_prod;
4006         base_flags = 0;
4007         if (skb->ip_summed == CHECKSUM_PARTIAL)
4008                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4009 #if TG3_TSO_SUPPORT != 0
4010         mss = 0;
4011         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4012             (mss = skb_shinfo(skb)->gso_size) != 0) {
4013                 int tcp_opt_len, ip_tcp_len, hdr_len;
4014
4015                 if (skb_header_cloned(skb) &&
4016                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4017                         dev_kfree_skb(skb);
4018                         goto out_unlock;
4019                 }
4020
4021                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4022                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4023
4024                 hdr_len = ip_tcp_len + tcp_opt_len;
4025                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4026                              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4027                         return (tg3_tso_bug(tp, skb));
4028
4029                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4030                                TXD_FLAG_CPU_POST_DMA);
4031
4032                 skb->nh.iph->check = 0;
4033                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4034                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4035                         skb->h.th->check = 0;
4036                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4037                 }
4038                 else {
4039                         skb->h.th->check =
4040                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4041                                                    skb->nh.iph->daddr,
4042                                                    0, IPPROTO_TCP, 0);
4043                 }
4044
4045                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4046                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4047                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4048                                 int tsflags;
4049
4050                                 tsflags = ((skb->nh.iph->ihl - 5) +
4051                                            (tcp_opt_len >> 2));
4052                                 mss |= (tsflags << 11);
4053                         }
4054                 } else {
4055                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4056                                 int tsflags;
4057
4058                                 tsflags = ((skb->nh.iph->ihl - 5) +
4059                                            (tcp_opt_len >> 2));
4060                                 base_flags |= tsflags << 12;
4061                         }
4062                 }
4063         }
4064 #else
4065         mss = 0;
4066 #endif
4067 #if TG3_VLAN_TAG_USED
4068         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4069                 base_flags |= (TXD_FLAG_VLAN |
4070                                (vlan_tx_tag_get(skb) << 16));
4071 #endif
4072
4073         /* Queue skb data, a.k.a. the main skb fragment. */
4074         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4075
4076         tp->tx_buffers[entry].skb = skb;
4077         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4078
4079         would_hit_hwbug = 0;
4080
4081         if (tg3_4g_overflow_test(mapping, len))
4082                 would_hit_hwbug = 1;
4083
4084         tg3_set_txd(tp, entry, mapping, len, base_flags,
4085                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4086
4087         entry = NEXT_TX(entry);
4088
4089         /* Now loop through additional data fragments, and queue them. */
4090         if (skb_shinfo(skb)->nr_frags > 0) {
4091                 unsigned int i, last;
4092
4093                 last = skb_shinfo(skb)->nr_frags - 1;
4094                 for (i = 0; i <= last; i++) {
4095                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4096
4097                         len = frag->size;
4098                         mapping = pci_map_page(tp->pdev,
4099                                                frag->page,
4100                                                frag->page_offset,
4101                                                len, PCI_DMA_TODEVICE);
4102
4103                         tp->tx_buffers[entry].skb = NULL;
4104                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4105
4106                         if (tg3_4g_overflow_test(mapping, len))
4107                                 would_hit_hwbug = 1;
4108
4109                         if (tg3_40bit_overflow_test(tp, mapping, len))
4110                                 would_hit_hwbug = 1;
4111
4112                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4113                                 tg3_set_txd(tp, entry, mapping, len,
4114                                             base_flags, (i == last)|(mss << 1));
4115                         else
4116                                 tg3_set_txd(tp, entry, mapping, len,
4117                                             base_flags, (i == last));
4118
4119                         entry = NEXT_TX(entry);
4120                 }
4121         }
4122
4123         if (would_hit_hwbug) {
4124                 u32 last_plus_one = entry;
4125                 u32 start;
4126
4127                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4128                 start &= (TG3_TX_RING_SIZE - 1);
4129
4130                 /* If the workaround fails due to memory/mapping
4131                  * failure, silently drop this packet.
4132                  */
4133                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4134                                                 &start, base_flags, mss))
4135                         goto out_unlock;
4136
4137                 entry = start;
4138         }
4139
4140         /* Packets are ready, update Tx producer idx local and on card. */
4141         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4142
4143         tp->tx_prod = entry;
4144         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4145                 netif_stop_queue(dev);
4146                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4147                         netif_wake_queue(tp->dev);
4148         }
4149
4150 out_unlock:
4151         mmiowb();
4152
4153         dev->trans_start = jiffies;
4154
4155         return NETDEV_TX_OK;
4156 }
4157
4158 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4159                                int new_mtu)
4160 {
4161         dev->mtu = new_mtu;
4162
4163         if (new_mtu > ETH_DATA_LEN) {
4164                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4165                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4166                         ethtool_op_set_tso(dev, 0);
4167                 }
4168                 else
4169                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4170         } else {
4171                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4172                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4173                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4174         }
4175 }
4176
4177 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4178 {
4179         struct tg3 *tp = netdev_priv(dev);
4180         int err;
4181
4182         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4183                 return -EINVAL;
4184
4185         if (!netif_running(dev)) {
4186                 /* We'll just catch it later when the
4187                  * device is up'd.
4188                  */
4189                 tg3_set_mtu(dev, tp, new_mtu);
4190                 return 0;
4191         }
4192
4193         tg3_netif_stop(tp);
4194
4195         tg3_full_lock(tp, 1);
4196
4197         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4198
4199         tg3_set_mtu(dev, tp, new_mtu);
4200
4201         err = tg3_restart_hw(tp, 0);
4202
4203         if (!err)
4204                 tg3_netif_start(tp);
4205
4206         tg3_full_unlock(tp);
4207
4208         return err;
4209 }
4210
4211 /* Free up pending packets in all rx/tx rings.
4212  *
4213  * The chip has been shut down and the driver detached from
4214  * the networking, so no interrupts or new tx packets will
4215  * end up in the driver.  tp->{tx,}lock is not held and we are not
4216  * in an interrupt context and thus may sleep.
4217  */
4218 static void tg3_free_rings(struct tg3 *tp)
4219 {
4220         struct ring_info *rxp;
4221         int i;
4222
4223         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4224                 rxp = &tp->rx_std_buffers[i];
4225
4226                 if (rxp->skb == NULL)
4227                         continue;
4228                 pci_unmap_single(tp->pdev,
4229                                  pci_unmap_addr(rxp, mapping),
4230                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4231                                  PCI_DMA_FROMDEVICE);
4232                 dev_kfree_skb_any(rxp->skb);
4233                 rxp->skb = NULL;
4234         }
4235
4236         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4237                 rxp = &tp->rx_jumbo_buffers[i];
4238
4239                 if (rxp->skb == NULL)
4240                         continue;
4241                 pci_unmap_single(tp->pdev,
4242                                  pci_unmap_addr(rxp, mapping),
4243                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4244                                  PCI_DMA_FROMDEVICE);
4245                 dev_kfree_skb_any(rxp->skb);
4246                 rxp->skb = NULL;
4247         }
4248
4249         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4250                 struct tx_ring_info *txp;
4251                 struct sk_buff *skb;
4252                 int j;
4253
4254                 txp = &tp->tx_buffers[i];
4255                 skb = txp->skb;
4256
4257                 if (skb == NULL) {
4258                         i++;
4259                         continue;
4260                 }
4261
4262                 pci_unmap_single(tp->pdev,
4263                                  pci_unmap_addr(txp, mapping),
4264                                  skb_headlen(skb),
4265                                  PCI_DMA_TODEVICE);
4266                 txp->skb = NULL;
4267
4268                 i++;
4269
4270                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4271                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4272                         pci_unmap_page(tp->pdev,
4273                                        pci_unmap_addr(txp, mapping),
4274                                        skb_shinfo(skb)->frags[j].size,
4275                                        PCI_DMA_TODEVICE);
4276                         i++;
4277                 }
4278
4279                 dev_kfree_skb_any(skb);
4280         }
4281 }
4282
4283 /* Initialize tx/rx rings for packet processing.
4284  *
4285  * The chip has been shut down and the driver detached from
4286  * the networking, so no interrupts or new tx packets will
4287  * end up in the driver.  tp->{tx,}lock are held and thus
4288  * we may not sleep.
4289  */
4290 static int tg3_init_rings(struct tg3 *tp)
4291 {
4292         u32 i;
4293
4294         /* Free up all the SKBs. */
4295         tg3_free_rings(tp);
4296
4297         /* Zero out all descriptors. */
4298         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4299         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4300         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4301         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4302
4303         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4304         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4305             (tp->dev->mtu > ETH_DATA_LEN))
4306                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4307
4308         /* Initialize invariants of the rings, we only set this
4309          * stuff once.  This works because the card does not
4310          * write into the rx buffer posting rings.
4311          */
4312         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4313                 struct tg3_rx_buffer_desc *rxd;
4314
4315                 rxd = &tp->rx_std[i];
4316                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4317                         << RXD_LEN_SHIFT;
4318                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4319                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4320                                (i << RXD_OPAQUE_INDEX_SHIFT));
4321         }
4322
4323         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4324                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4325                         struct tg3_rx_buffer_desc *rxd;
4326
4327                         rxd = &tp->rx_jumbo[i];
4328                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4329                                 << RXD_LEN_SHIFT;
4330                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4331                                 RXD_FLAG_JUMBO;
4332                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4333                                (i << RXD_OPAQUE_INDEX_SHIFT));
4334                 }
4335         }
4336
4337         /* Now allocate fresh SKBs for each rx ring. */
4338         for (i = 0; i < tp->rx_pending; i++) {
4339                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4340                         printk(KERN_WARNING PFX
4341                                "%s: Using a smaller RX standard ring, "
4342                                "only %d out of %d buffers were allocated "
4343                                "successfully.\n",
4344                                tp->dev->name, i, tp->rx_pending);
4345                         if (i == 0)
4346                                 return -ENOMEM;
4347                         tp->rx_pending = i;
4348                         break;
4349                 }
4350         }
4351
4352         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4353                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4354                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4355                                              -1, i) < 0) {
4356                                 printk(KERN_WARNING PFX
4357                                        "%s: Using a smaller RX jumbo ring, "
4358                                        "only %d out of %d buffers were "
4359                                        "allocated successfully.\n",
4360                                        tp->dev->name, i, tp->rx_jumbo_pending);
4361                                 if (i == 0) {
4362                                         tg3_free_rings(tp);
4363                                         return -ENOMEM;
4364                                 }
4365                                 tp->rx_jumbo_pending = i;
4366                                 break;
4367                         }
4368                 }
4369         }
4370         return 0;
4371 }
4372
4373 /*
4374  * Must not be invoked with interrupt sources disabled and
4375  * the hardware shutdown down.
4376  */
4377 static void tg3_free_consistent(struct tg3 *tp)
4378 {
4379         kfree(tp->rx_std_buffers);
4380         tp->rx_std_buffers = NULL;
4381         if (tp->rx_std) {
4382                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4383                                     tp->rx_std, tp->rx_std_mapping);
4384                 tp->rx_std = NULL;
4385         }
4386         if (tp->rx_jumbo) {
4387                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4388                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4389                 tp->rx_jumbo = NULL;
4390         }
4391         if (tp->rx_rcb) {
4392                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4393                                     tp->rx_rcb, tp->rx_rcb_mapping);
4394                 tp->rx_rcb = NULL;
4395         }
4396         if (tp->tx_ring) {
4397                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4398                         tp->tx_ring, tp->tx_desc_mapping);
4399                 tp->tx_ring = NULL;
4400         }
4401         if (tp->hw_status) {
4402                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4403                                     tp->hw_status, tp->status_mapping);
4404                 tp->hw_status = NULL;
4405         }
4406         if (tp->hw_stats) {
4407                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4408                                     tp->hw_stats, tp->stats_mapping);
4409                 tp->hw_stats = NULL;
4410         }
4411 }
4412
4413 /*
4414  * Must not be invoked with interrupt sources disabled and
4415  * the hardware shutdown down.  Can sleep.
4416  */
4417 static int tg3_alloc_consistent(struct tg3 *tp)
4418 {
4419         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4420                                       (TG3_RX_RING_SIZE +
4421                                        TG3_RX_JUMBO_RING_SIZE)) +
4422                                      (sizeof(struct tx_ring_info) *
4423                                       TG3_TX_RING_SIZE),
4424                                      GFP_KERNEL);
4425         if (!tp->rx_std_buffers)
4426                 return -ENOMEM;
4427
4428         memset(tp->rx_std_buffers, 0,
4429                (sizeof(struct ring_info) *
4430                 (TG3_RX_RING_SIZE +
4431                  TG3_RX_JUMBO_RING_SIZE)) +
4432                (sizeof(struct tx_ring_info) *
4433                 TG3_TX_RING_SIZE));
4434
4435         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4436         tp->tx_buffers = (struct tx_ring_info *)
4437                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4438
4439         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4440                                           &tp->rx_std_mapping);
4441         if (!tp->rx_std)
4442                 goto err_out;
4443
4444         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4445                                             &tp->rx_jumbo_mapping);
4446
4447         if (!tp->rx_jumbo)
4448                 goto err_out;
4449
4450         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4451                                           &tp->rx_rcb_mapping);
4452         if (!tp->rx_rcb)
4453                 goto err_out;
4454
4455         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4456                                            &tp->tx_desc_mapping);
4457         if (!tp->tx_ring)
4458                 goto err_out;
4459
4460         tp->hw_status = pci_alloc_consistent(tp->pdev,
4461                                              TG3_HW_STATUS_SIZE,
4462                                              &tp->status_mapping);
4463         if (!tp->hw_status)
4464                 goto err_out;
4465
4466         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4467                                             sizeof(struct tg3_hw_stats),
4468                                             &tp->stats_mapping);
4469         if (!tp->hw_stats)
4470                 goto err_out;
4471
4472         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4473         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4474
4475         return 0;
4476
4477 err_out:
4478         tg3_free_consistent(tp);
4479         return -ENOMEM;
4480 }
4481
4482 #define MAX_WAIT_CNT 1000
4483
4484 /* To stop a block, clear the enable bit and poll till it
4485  * clears.  tp->lock is held.
4486  */
4487 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4488 {
4489         unsigned int i;
4490         u32 val;
4491
4492         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4493                 switch (ofs) {
4494                 case RCVLSC_MODE:
4495                 case DMAC_MODE:
4496                 case MBFREE_MODE:
4497                 case BUFMGR_MODE:
4498                 case MEMARB_MODE:
4499                         /* We can't enable/disable these bits of the
4500                          * 5705/5750, just say success.
4501                          */
4502                         return 0;
4503
4504                 default:
4505                         break;
4506                 };
4507         }
4508
4509         val = tr32(ofs);
4510         val &= ~enable_bit;
4511         tw32_f(ofs, val);
4512
4513         for (i = 0; i < MAX_WAIT_CNT; i++) {
4514                 udelay(100);
4515                 val = tr32(ofs);
4516                 if ((val & enable_bit) == 0)
4517                         break;
4518         }
4519
4520         if (i == MAX_WAIT_CNT && !silent) {
4521                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4522                        "ofs=%lx enable_bit=%x\n",
4523                        ofs, enable_bit);
4524                 return -ENODEV;
4525         }
4526
4527         return 0;
4528 }
4529
4530 /* tp->lock is held. */
4531 static int tg3_abort_hw(struct tg3 *tp, int silent)
4532 {
4533         int i, err;
4534
4535         tg3_disable_ints(tp);
4536
4537         tp->rx_mode &= ~RX_MODE_ENABLE;
4538         tw32_f(MAC_RX_MODE, tp->rx_mode);
4539         udelay(10);
4540
4541         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4542         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4543         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4544         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4545         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4546         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4547
4548         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4549         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4550         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4551         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4552         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4553         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4554         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4555
4556         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4557         tw32_f(MAC_MODE, tp->mac_mode);
4558         udelay(40);
4559
4560         tp->tx_mode &= ~TX_MODE_ENABLE;
4561         tw32_f(MAC_TX_MODE, tp->tx_mode);
4562
4563         for (i = 0; i < MAX_WAIT_CNT; i++) {
4564                 udelay(100);
4565                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4566                         break;
4567         }
4568         if (i >= MAX_WAIT_CNT) {
4569                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4570                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4571                        tp->dev->name, tr32(MAC_TX_MODE));
4572                 err |= -ENODEV;
4573         }
4574
4575         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4576         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4578
4579         tw32(FTQ_RESET, 0xffffffff);
4580         tw32(FTQ_RESET, 0x00000000);
4581
4582         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4583         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4584
4585         if (tp->hw_status)
4586                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4587         if (tp->hw_stats)
4588                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4589
4590         return err;
4591 }
4592
4593 /* tp->lock is held. */
4594 static int tg3_nvram_lock(struct tg3 *tp)
4595 {
4596         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4597                 int i;
4598
4599                 if (tp->nvram_lock_cnt == 0) {
4600                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4601                         for (i = 0; i < 8000; i++) {
4602                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4603                                         break;
4604                                 udelay(20);
4605                         }
4606                         if (i == 8000) {
4607                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4608                                 return -ENODEV;
4609                         }
4610                 }
4611                 tp->nvram_lock_cnt++;
4612         }
4613         return 0;
4614 }
4615
4616 /* tp->lock is held. */
4617 static void tg3_nvram_unlock(struct tg3 *tp)
4618 {
4619         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4620                 if (tp->nvram_lock_cnt > 0)
4621                         tp->nvram_lock_cnt--;
4622                 if (tp->nvram_lock_cnt == 0)
4623                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4624         }
4625 }
4626
4627 /* tp->lock is held. */
4628 static void tg3_enable_nvram_access(struct tg3 *tp)
4629 {
4630         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4631             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4632                 u32 nvaccess = tr32(NVRAM_ACCESS);
4633
4634                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4635         }
4636 }
4637
4638 /* tp->lock is held. */
4639 static void tg3_disable_nvram_access(struct tg3 *tp)
4640 {
4641         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4642             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4643                 u32 nvaccess = tr32(NVRAM_ACCESS);
4644
4645                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4646         }
4647 }
4648
4649 /* tp->lock is held. */
4650 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4651 {
4652         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4653                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4654
4655         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4656                 switch (kind) {
4657                 case RESET_KIND_INIT:
4658                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4659                                       DRV_STATE_START);
4660                         break;
4661
4662                 case RESET_KIND_SHUTDOWN:
4663                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4664                                       DRV_STATE_UNLOAD);
4665                         break;
4666
4667                 case RESET_KIND_SUSPEND:
4668                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4669                                       DRV_STATE_SUSPEND);
4670                         break;
4671
4672                 default:
4673                         break;
4674                 };
4675         }
4676 }
4677
4678 /* tp->lock is held. */
4679 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4680 {
4681         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4682                 switch (kind) {
4683                 case RESET_KIND_INIT:
4684                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4685                                       DRV_STATE_START_DONE);
4686                         break;
4687
4688                 case RESET_KIND_SHUTDOWN:
4689                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4690                                       DRV_STATE_UNLOAD_DONE);
4691                         break;
4692
4693                 default:
4694                         break;
4695                 };
4696         }
4697 }
4698
4699 /* tp->lock is held. */
4700 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4701 {
4702         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4703                 switch (kind) {
4704                 case RESET_KIND_INIT:
4705                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4706                                       DRV_STATE_START);
4707                         break;
4708
4709                 case RESET_KIND_SHUTDOWN:
4710                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4711                                       DRV_STATE_UNLOAD);
4712                         break;
4713
4714                 case RESET_KIND_SUSPEND:
4715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4716                                       DRV_STATE_SUSPEND);
4717                         break;
4718
4719                 default:
4720                         break;
4721                 };
4722         }
4723 }
4724
4725 static int tg3_poll_fw(struct tg3 *tp)
4726 {
4727         int i;
4728         u32 val;
4729
4730         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4731                 /* Wait up to 20ms for init done. */
4732                 for (i = 0; i < 200; i++) {
4733                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4734                                 return 0;
4735                         udelay(100);
4736                 }
4737                 return -ENODEV;
4738         }
4739
4740         /* Wait for firmware initialization to complete. */
4741         for (i = 0; i < 100000; i++) {
4742                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4743                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4744                         break;
4745                 udelay(10);
4746         }
4747
4748         /* Chip might not be fitted with firmware.  Some Sun onboard
4749          * parts are configured like that.  So don't signal the timeout
4750          * of the above loop as an error, but do report the lack of
4751          * running firmware once.
4752          */
4753         if (i >= 100000 &&
4754             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4755                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4756
4757                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4758                        tp->dev->name);
4759         }
4760
4761         return 0;
4762 }
4763
4764 static void tg3_stop_fw(struct tg3 *);
4765
4766 /* tp->lock is held. */
4767 static int tg3_chip_reset(struct tg3 *tp)
4768 {
4769         u32 val;
4770         void (*write_op)(struct tg3 *, u32, u32);
4771         int err;
4772
4773         tg3_nvram_lock(tp);
4774
4775         /* No matching tg3_nvram_unlock() after this because
4776          * chip reset below will undo the nvram lock.
4777          */
4778         tp->nvram_lock_cnt = 0;
4779
4780         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4781             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4782             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4783                 tw32(GRC_FASTBOOT_PC, 0);
4784
4785         /*
4786          * We must avoid the readl() that normally takes place.
4787          * It locks machines, causes machine checks, and other
4788          * fun things.  So, temporarily disable the 5701
4789          * hardware workaround, while we do the reset.
4790          */
4791         write_op = tp->write32;
4792         if (write_op == tg3_write_flush_reg32)
4793                 tp->write32 = tg3_write32;
4794
4795         /* do the reset */
4796         val = GRC_MISC_CFG_CORECLK_RESET;
4797
4798         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4799                 if (tr32(0x7e2c) == 0x60) {
4800                         tw32(0x7e2c, 0x20);
4801                 }
4802                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4803                         tw32(GRC_MISC_CFG, (1 << 29));
4804                         val |= (1 << 29);
4805                 }
4806         }
4807
4808         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4809                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4810                 tw32(GRC_VCPU_EXT_CTRL,
4811                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4812         }
4813
4814         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4815                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4816         tw32(GRC_MISC_CFG, val);
4817
4818         /* restore 5701 hardware bug workaround write method */
4819         tp->write32 = write_op;
4820
4821         /* Unfortunately, we have to delay before the PCI read back.
4822          * Some 575X chips even will not respond to a PCI cfg access
4823          * when the reset command is given to the chip.
4824          *
4825          * How do these hardware designers expect things to work
4826          * properly if the PCI write is posted for a long period
4827          * of time?  It is always necessary to have some method by
4828          * which a register read back can occur to push the write
4829          * out which does the reset.
4830          *
4831          * For most tg3 variants the trick below was working.
4832          * Ho hum...
4833          */
4834         udelay(120);
4835
4836         /* Flush PCI posted writes.  The normal MMIO registers
4837          * are inaccessible at this time so this is the only
4838          * way to make this reliably (actually, this is no longer
4839          * the case, see above).  I tried to use indirect
4840          * register read/write but this upset some 5701 variants.
4841          */
4842         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4843
4844         udelay(120);
4845
4846         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4847                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4848                         int i;
4849                         u32 cfg_val;
4850
4851                         /* Wait for link training to complete.  */
4852                         for (i = 0; i < 5000; i++)
4853                                 udelay(100);
4854
4855                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4856                         pci_write_config_dword(tp->pdev, 0xc4,
4857                                                cfg_val | (1 << 15));
4858                 }
4859                 /* Set PCIE max payload size and clear error status.  */
4860                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4861         }
4862
4863         /* Re-enable indirect register accesses. */
4864         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4865                                tp->misc_host_ctrl);
4866
4867         /* Set MAX PCI retry to zero. */
4868         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4869         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4870             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4871                 val |= PCISTATE_RETRY_SAME_DMA;
4872         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4873
4874         pci_restore_state(tp->pdev);
4875
4876         /* Make sure PCI-X relaxed ordering bit is clear. */
4877         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4878         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4879         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4880
4881         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4882                 u32 val;
4883
4884                 /* Chip reset on 5780 will reset MSI enable bit,
4885                  * so need to restore it.
4886                  */
4887                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4888                         u16 ctrl;
4889
4890                         pci_read_config_word(tp->pdev,
4891                                              tp->msi_cap + PCI_MSI_FLAGS,
4892                                              &ctrl);
4893                         pci_write_config_word(tp->pdev,
4894                                               tp->msi_cap + PCI_MSI_FLAGS,
4895                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4896                         val = tr32(MSGINT_MODE);
4897                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4898                 }
4899
4900                 val = tr32(MEMARB_MODE);
4901                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4902
4903         } else
4904                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4905
4906         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4907                 tg3_stop_fw(tp);
4908                 tw32(0x5000, 0x400);
4909         }
4910
4911         tw32(GRC_MODE, tp->grc_mode);
4912
4913         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4914                 u32 val = tr32(0xc4);
4915
4916                 tw32(0xc4, val | (1 << 15));
4917         }
4918
4919         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4920             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4921                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4922                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4923                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4924                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4925         }
4926
4927         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4928                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4929                 tw32_f(MAC_MODE, tp->mac_mode);
4930         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4931                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4932                 tw32_f(MAC_MODE, tp->mac_mode);
4933         } else
4934                 tw32_f(MAC_MODE, 0);
4935         udelay(40);
4936
4937         err = tg3_poll_fw(tp);
4938         if (err)
4939                 return err;
4940
4941         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4942             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4943                 u32 val = tr32(0x7c00);
4944
4945                 tw32(0x7c00, val | (1 << 25));
4946         }
4947
4948         /* Reprobe ASF enable state.  */
4949         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4950         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4951         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4952         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4953                 u32 nic_cfg;
4954
4955                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4956                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4957                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4958                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4959                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4960                 }
4961         }
4962
4963         return 0;
4964 }
4965
4966 /* tp->lock is held. */
4967 static void tg3_stop_fw(struct tg3 *tp)
4968 {
4969         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4970                 u32 val;
4971                 int i;
4972
4973                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4974                 val = tr32(GRC_RX_CPU_EVENT);
4975                 val |= (1 << 14);
4976                 tw32(GRC_RX_CPU_EVENT, val);
4977
4978                 /* Wait for RX cpu to ACK the event.  */
4979                 for (i = 0; i < 100; i++) {
4980                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4981                                 break;
4982                         udelay(1);
4983                 }
4984         }
4985 }
4986
4987 /* tp->lock is held. */
4988 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4989 {
4990         int err;
4991
4992         tg3_stop_fw(tp);
4993
4994         tg3_write_sig_pre_reset(tp, kind);
4995
4996         tg3_abort_hw(tp, silent);
4997         err = tg3_chip_reset(tp);
4998
4999         tg3_write_sig_legacy(tp, kind);
5000         tg3_write_sig_post_reset(tp, kind);
5001
5002         if (err)
5003                 return err;
5004
5005         return 0;
5006 }
5007
5008 #define TG3_FW_RELEASE_MAJOR    0x0
5009 #define TG3_FW_RELASE_MINOR     0x0
5010 #define TG3_FW_RELEASE_FIX      0x0
5011 #define TG3_FW_START_ADDR       0x08000000
5012 #define TG3_FW_TEXT_ADDR        0x08000000
5013 #define TG3_FW_TEXT_LEN         0x9c0
5014 #define TG3_FW_RODATA_ADDR      0x080009c0
5015 #define TG3_FW_RODATA_LEN       0x60
5016 #define TG3_FW_DATA_ADDR        0x08000a40
5017 #define TG3_FW_DATA_LEN         0x20
5018 #define TG3_FW_SBSS_ADDR        0x08000a60
5019 #define TG3_FW_SBSS_LEN         0xc
5020 #define TG3_FW_BSS_ADDR         0x08000a70
5021 #define TG3_FW_BSS_LEN          0x10
5022
5023 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5024         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5025         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5026         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5027         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5028         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5029         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5030         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5031         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5032         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5033         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5034         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5035         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5036         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5037         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5038         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5039         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5040         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5041         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5042         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5043         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5044         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5045         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5046         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5047         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5048         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5049         0, 0, 0, 0, 0, 0,
5050         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5051         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5052         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5053         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5054         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5055         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5056         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5057         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5058         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5059         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5060         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5061         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5062         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5063         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5064         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5065         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5066         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5067         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5068         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5069         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5070         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5071         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5072         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5073         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5074         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5075         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5076         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5077         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5078         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5079         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5080         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5081         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5082         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5083         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5084         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5085         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5086         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5087         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5088         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5089         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5090         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5091         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5092         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5093         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5094         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5095         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5096         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5097         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5098         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5099         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5100         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5101         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5102         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5103         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5104         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5105         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5106         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5107         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5108         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5109         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5110         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5111         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5112         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5113         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5114         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5115 };
5116
5117 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5118         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5119         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5120         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5121         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5122         0x00000000
5123 };
5124
5125 #if 0 /* All zeros, don't eat up space with it. */
5126 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5127         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5128         0x00000000, 0x00000000, 0x00000000, 0x00000000
5129 };
5130 #endif
5131
5132 #define RX_CPU_SCRATCH_BASE     0x30000
5133 #define RX_CPU_SCRATCH_SIZE     0x04000
5134 #define TX_CPU_SCRATCH_BASE     0x34000
5135 #define TX_CPU_SCRATCH_SIZE     0x04000
5136
5137 /* tp->lock is held. */
5138 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5139 {
5140         int i;
5141
5142         BUG_ON(offset == TX_CPU_BASE &&
5143             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5144
5145         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5146                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5147
5148                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5149                 return 0;
5150         }
5151         if (offset == RX_CPU_BASE) {
5152                 for (i = 0; i < 10000; i++) {
5153                         tw32(offset + CPU_STATE, 0xffffffff);
5154                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5155                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5156                                 break;
5157                 }
5158
5159                 tw32(offset + CPU_STATE, 0xffffffff);
5160                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5161                 udelay(10);
5162         } else {
5163                 for (i = 0; i < 10000; i++) {
5164                         tw32(offset + CPU_STATE, 0xffffffff);
5165                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5166                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5167                                 break;
5168                 }
5169         }
5170
5171         if (i >= 10000) {
5172                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5173                        "and %s CPU\n",
5174                        tp->dev->name,
5175                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5176                 return -ENODEV;
5177         }
5178
5179         /* Clear firmware's nvram arbitration. */
5180         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5181                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5182         return 0;
5183 }
5184
5185 struct fw_info {
5186         unsigned int text_base;
5187         unsigned int text_len;
5188         const u32 *text_data;
5189         unsigned int rodata_base;
5190         unsigned int rodata_len;
5191         const u32 *rodata_data;
5192         unsigned int data_base;
5193         unsigned int data_len;
5194         const u32 *data_data;
5195 };
5196
5197 /* tp->lock is held. */
5198 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5199                                  int cpu_scratch_size, struct fw_info *info)
5200 {
5201         int err, lock_err, i;
5202         void (*write_op)(struct tg3 *, u32, u32);
5203
5204         if (cpu_base == TX_CPU_BASE &&
5205             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5206                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5207                        "TX cpu firmware on %s which is 5705.\n",
5208                        tp->dev->name);
5209                 return -EINVAL;
5210         }
5211
5212         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5213                 write_op = tg3_write_mem;
5214         else
5215                 write_op = tg3_write_indirect_reg32;
5216
5217         /* It is possible that bootcode is still loading at this point.
5218          * Get the nvram lock first before halting the cpu.
5219          */
5220         lock_err = tg3_nvram_lock(tp);
5221         err = tg3_halt_cpu(tp, cpu_base);
5222         if (!lock_err)
5223                 tg3_nvram_unlock(tp);
5224         if (err)
5225                 goto out;
5226
5227         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5228                 write_op(tp, cpu_scratch_base + i, 0);
5229         tw32(cpu_base + CPU_STATE, 0xffffffff);
5230         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5231         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5232                 write_op(tp, (cpu_scratch_base +
5233                               (info->text_base & 0xffff) +
5234                               (i * sizeof(u32))),
5235                          (info->text_data ?
5236                           info->text_data[i] : 0));
5237         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5238                 write_op(tp, (cpu_scratch_base +
5239                               (info->rodata_base & 0xffff) +
5240                               (i * sizeof(u32))),
5241                          (info->rodata_data ?
5242                           info->rodata_data[i] : 0));
5243         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5244                 write_op(tp, (cpu_scratch_base +
5245                               (info->data_base & 0xffff) +
5246                               (i * sizeof(u32))),
5247                          (info->data_data ?
5248                           info->data_data[i] : 0));
5249
5250         err = 0;
5251
5252 out:
5253         return err;
5254 }
5255
5256 /* tp->lock is held. */
5257 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5258 {
5259         struct fw_info info;
5260         int err, i;
5261
5262         info.text_base = TG3_FW_TEXT_ADDR;
5263         info.text_len = TG3_FW_TEXT_LEN;
5264         info.text_data = &tg3FwText[0];
5265         info.rodata_base = TG3_FW_RODATA_ADDR;
5266         info.rodata_len = TG3_FW_RODATA_LEN;
5267         info.rodata_data = &tg3FwRodata[0];
5268         info.data_base = TG3_FW_DATA_ADDR;
5269         info.data_len = TG3_FW_DATA_LEN;
5270         info.data_data = NULL;
5271
5272         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5273                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5274                                     &info);
5275         if (err)
5276                 return err;
5277
5278         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5279                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5280                                     &info);
5281         if (err)
5282                 return err;
5283
5284         /* Now startup only the RX cpu. */
5285         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5286         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5287
5288         for (i = 0; i < 5; i++) {
5289                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5290                         break;
5291                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5292                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5293                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5294                 udelay(1000);
5295         }
5296         if (i >= 5) {
5297                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5298                        "to set RX CPU PC, is %08x should be %08x\n",
5299                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5300                        TG3_FW_TEXT_ADDR);
5301                 return -ENODEV;
5302         }
5303         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5304         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5305
5306         return 0;
5307 }
5308
5309 #if TG3_TSO_SUPPORT != 0
5310
5311 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5312 #define TG3_TSO_FW_RELASE_MINOR         0x6
5313 #define TG3_TSO_FW_RELEASE_FIX          0x0
5314 #define TG3_TSO_FW_START_ADDR           0x08000000
5315 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5316 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5317 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5318 #define TG3_TSO_FW_RODATA_LEN           0x60
5319 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5320 #define TG3_TSO_FW_DATA_LEN             0x30
5321 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5322 #define TG3_TSO_FW_SBSS_LEN             0x2c
5323 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5324 #define TG3_TSO_FW_BSS_LEN              0x894
5325
5326 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5327         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5328         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5329         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5330         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5331         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5332         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5333         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5334         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5335         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5336         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5337         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5338         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5339         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5340         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5341         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5342         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5343         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5344         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5345         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5346         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5347         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5348         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5349         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5350         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5351         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5352         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5353         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5354         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5355         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5356         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5357         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5358         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5359         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5360         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5361         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5362         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5363         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5364         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5365         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5366         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5367         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5368         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5369         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5370         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5371         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5372         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5373         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5374         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5375         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5376         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5377         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5378         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5379         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5380         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5381         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5382         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5383         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5384         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5385         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5386         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5387         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5388         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5389         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5390         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5391         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5392         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5393         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5394         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5395         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5396         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5397         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5398         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5399         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5400         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5401         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5402         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5403         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5404         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5405         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5406         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5407         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5408         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5409         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5410         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5411         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5412         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5413         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5414         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5415         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5416         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5417         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5418         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5419         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5420         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5421         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5422         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5423         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5424         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5425         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5426         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5427         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5428         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5429         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5430         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5431         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5432         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5433         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5434         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5435         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5436         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5437         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5438         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5439         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5440         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5441         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5442         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5443         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5444         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5445         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5446         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5447         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5448         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5449         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5450         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5451         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5452         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5453         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5454         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5455         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5456         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5457         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5458         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5459         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5460         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5461         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5462         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5463         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5464         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5465         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5466         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5467         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5468         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5469         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5470         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5471         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5472         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5473         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5474         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5475         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5476         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5477         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5478         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5479         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5480         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5481         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5482         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5483         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5484         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5485         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5486         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5487         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5488         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5489         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5490         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5491         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5492         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5493         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5494         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5495         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5496         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5497         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5498         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5499         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5500         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5501         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5502         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5503         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5504         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5505         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5506         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5507         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5508         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5509         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5510         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5511         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5512         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5513         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5514         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5515         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5516         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5517         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5518         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5519         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5520         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5521         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5522         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5523         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5524         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5525         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5526         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5527         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5528         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5529         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5530         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5531         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5532         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5533         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5534         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5535         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5536         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5537         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5538         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5539         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5540         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5541         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5542         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5543         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5544         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5545         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5546         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5547         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5548         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5549         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5550         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5551         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5552         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5553         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5554         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5555         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5556         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5557         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5558         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5559         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5560         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5561         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5562         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5563         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5564         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5565         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5566         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5567         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5568         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5569         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5570         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5571         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5572         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5573         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5574         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5575         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5576         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5577         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5578         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5579         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5580         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5581         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5582         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5583         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5584         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5585         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5586         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5587         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5588         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5589         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5590         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5591         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5592         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5593         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5594         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5595         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5596         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5597         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5598         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5599         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5600         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5601         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5602         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5603         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5604         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5605         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5606         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5607         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5608         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5609         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5610         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5611 };
5612
5613 static const u32 tg3TsoFwRodata[] = {
5614         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5615         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5616         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5617         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5618         0x00000000,
5619 };
5620
5621 static const u32 tg3TsoFwData[] = {
5622         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5623         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5624         0x00000000,
5625 };
5626
5627 /* 5705 needs a special version of the TSO firmware.  */
5628 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5629 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5630 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5631 #define TG3_TSO5_FW_START_ADDR          0x00010000
5632 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5633 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5634 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5635 #define TG3_TSO5_FW_RODATA_LEN          0x50
5636 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5637 #define TG3_TSO5_FW_DATA_LEN            0x20
5638 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5639 #define TG3_TSO5_FW_SBSS_LEN            0x28
5640 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5641 #define TG3_TSO5_FW_BSS_LEN             0x88
5642
5643 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5644         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5645         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5646         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5647         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5648         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5649         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5650         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5651         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5652         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5653         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5654         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5655         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5656         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5657         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5658         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5659         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5660         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5661         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5662         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5663         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5664         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5665         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5666         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5667         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5668         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5669         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5670         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5671         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5672         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5673         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5674         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5675         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5676         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5677         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5678         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5679         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5680         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5681         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5682         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5683         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5684         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5685         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5686         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5687         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5688         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5689         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5690         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5691         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5692         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5693         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5694         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5695         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5696         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5697         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5698         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5699         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5700         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5701         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5702         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5703         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5704         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5705         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5706         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5707         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5708         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5709         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5710         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5711         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5712         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5713         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5714         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5715         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5716         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5717         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5718         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5719         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5720         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5721         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5722         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5723         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5724         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5725         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5726         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5727         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5728         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5729         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5730         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5731         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5732         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5733         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5734         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5735         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5736         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5737         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5738         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5739         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5740         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5741         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5742         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5743         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5744         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5745         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5746         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5747         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5748         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5749         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5750         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5751         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5752         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5753         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5754         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5755         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5756         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5757         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5758         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5759         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5760         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5761         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5762         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5763         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5764         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5765         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5766         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5767         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5768         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5769         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5770         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5771         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5772         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5773         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5774         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5775         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5776         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5777         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5778         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5779         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5780         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5781         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5782         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5783         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5784         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5785         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5786         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5787         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5788         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5789         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5790         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5791         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5792         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5793         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5794         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5795         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5796         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5797         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5798         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5799         0x00000000, 0x00000000, 0x00000000,
5800 };
5801
5802 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5803         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5804         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5805         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5806         0x00000000, 0x00000000, 0x00000000,
5807 };
5808
5809 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5810         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5811         0x00000000, 0x00000000, 0x00000000,
5812 };
5813
5814 /* tp->lock is held. */
5815 static int tg3_load_tso_firmware(struct tg3 *tp)
5816 {
5817         struct fw_info info;
5818         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5819         int err, i;
5820
5821         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5822                 return 0;
5823
5824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5825                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5826                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5827                 info.text_data = &tg3Tso5FwText[0];
5828                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5829                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5830                 info.rodata_data = &tg3Tso5FwRodata[0];
5831                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5832                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5833                 info.data_data = &tg3Tso5FwData[0];
5834                 cpu_base = RX_CPU_BASE;
5835                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5836                 cpu_scratch_size = (info.text_len +
5837                                     info.rodata_len +
5838                                     info.data_len +
5839                                     TG3_TSO5_FW_SBSS_LEN +
5840                                     TG3_TSO5_FW_BSS_LEN);
5841         } else {
5842                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5843                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5844                 info.text_data = &tg3TsoFwText[0];
5845                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5846                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5847                 info.rodata_data = &tg3TsoFwRodata[0];
5848                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5849                 info.data_len = TG3_TSO_FW_DATA_LEN;
5850                 info.data_data = &tg3TsoFwData[0];
5851                 cpu_base = TX_CPU_BASE;
5852                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5853                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5854         }
5855
5856         err = tg3_load_firmware_cpu(tp, cpu_base,
5857                                     cpu_scratch_base, cpu_scratch_size,
5858                                     &info);
5859         if (err)
5860                 return err;
5861
5862         /* Now startup the cpu. */
5863         tw32(cpu_base + CPU_STATE, 0xffffffff);
5864         tw32_f(cpu_base + CPU_PC,    info.text_base);
5865
5866         for (i = 0; i < 5; i++) {
5867                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5868                         break;
5869                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5870                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5871                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5872                 udelay(1000);
5873         }
5874         if (i >= 5) {
5875                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5876                        "to set CPU PC, is %08x should be %08x\n",
5877                        tp->dev->name, tr32(cpu_base + CPU_PC),
5878                        info.text_base);
5879                 return -ENODEV;
5880         }
5881         tw32(cpu_base + CPU_STATE, 0xffffffff);
5882         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5883         return 0;
5884 }
5885
5886 #endif /* TG3_TSO_SUPPORT != 0 */
5887
5888 /* tp->lock is held. */
5889 static void __tg3_set_mac_addr(struct tg3 *tp)
5890 {
5891         u32 addr_high, addr_low;
5892         int i;
5893
5894         addr_high = ((tp->dev->dev_addr[0] << 8) |
5895                      tp->dev->dev_addr[1]);
5896         addr_low = ((tp->dev->dev_addr[2] << 24) |
5897                     (tp->dev->dev_addr[3] << 16) |
5898                     (tp->dev->dev_addr[4] <<  8) |
5899                     (tp->dev->dev_addr[5] <<  0));
5900         for (i = 0; i < 4; i++) {
5901                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5902                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5903         }
5904
5905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5906             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5907                 for (i = 0; i < 12; i++) {
5908                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5909                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5910                 }
5911         }
5912
5913         addr_high = (tp->dev->dev_addr[0] +
5914                      tp->dev->dev_addr[1] +
5915                      tp->dev->dev_addr[2] +
5916                      tp->dev->dev_addr[3] +
5917                      tp->dev->dev_addr[4] +
5918                      tp->dev->dev_addr[5]) &
5919                 TX_BACKOFF_SEED_MASK;
5920         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5921 }
5922
5923 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5924 {
5925         struct tg3 *tp = netdev_priv(dev);
5926         struct sockaddr *addr = p;
5927         int err = 0;
5928
5929         if (!is_valid_ether_addr(addr->sa_data))
5930                 return -EINVAL;
5931
5932         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5933
5934         if (!netif_running(dev))
5935                 return 0;
5936
5937         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5938                 /* Reset chip so that ASF can re-init any MAC addresses it
5939                  * needs.
5940                  */
5941                 tg3_netif_stop(tp);
5942                 tg3_full_lock(tp, 1);
5943
5944                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5945                 err = tg3_restart_hw(tp, 0);
5946                 if (!err)
5947                         tg3_netif_start(tp);
5948                 tg3_full_unlock(tp);
5949         } else {
5950                 spin_lock_bh(&tp->lock);
5951                 __tg3_set_mac_addr(tp);
5952                 spin_unlock_bh(&tp->lock);
5953         }
5954
5955         return err;
5956 }
5957
5958 /* tp->lock is held. */
5959 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5960                            dma_addr_t mapping, u32 maxlen_flags,
5961                            u32 nic_addr)
5962 {
5963         tg3_write_mem(tp,
5964                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5965                       ((u64) mapping >> 32));
5966         tg3_write_mem(tp,
5967                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5968                       ((u64) mapping & 0xffffffff));
5969         tg3_write_mem(tp,
5970                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5971                        maxlen_flags);
5972
5973         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5974                 tg3_write_mem(tp,
5975                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5976                               nic_addr);
5977 }
5978
5979 static void __tg3_set_rx_mode(struct net_device *);
5980 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5981 {
5982         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5983         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5984         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5985         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5986         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5987                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5988                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5989         }
5990         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5991         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5992         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5993                 u32 val = ec->stats_block_coalesce_usecs;
5994
5995                 if (!netif_carrier_ok(tp->dev))
5996                         val = 0;
5997
5998                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5999         }
6000 }
6001
6002 /* tp->lock is held. */
6003 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6004 {
6005         u32 val, rdmac_mode;
6006         int i, err, limit;
6007
6008         tg3_disable_ints(tp);
6009
6010         tg3_stop_fw(tp);
6011
6012         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6013
6014         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6015                 tg3_abort_hw(tp, 1);
6016         }
6017
6018         if (reset_phy)
6019                 tg3_phy_reset(tp);
6020
6021         err = tg3_chip_reset(tp);
6022         if (err)
6023                 return err;
6024
6025         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6026
6027         /* This works around an issue with Athlon chipsets on
6028          * B3 tigon3 silicon.  This bit has no effect on any
6029          * other revision.  But do not set this on PCI Express
6030          * chips.
6031          */
6032         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6033                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6034         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6035
6036         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6037             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6038                 val = tr32(TG3PCI_PCISTATE);
6039                 val |= PCISTATE_RETRY_SAME_DMA;
6040                 tw32(TG3PCI_PCISTATE, val);
6041         }
6042
6043         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6044                 /* Enable some hw fixes.  */
6045                 val = tr32(TG3PCI_MSI_DATA);
6046                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6047                 tw32(TG3PCI_MSI_DATA, val);
6048         }
6049
6050         /* Descriptor ring init may make accesses to the
6051          * NIC SRAM area to setup the TX descriptors, so we
6052          * can only do this after the hardware has been
6053          * successfully reset.
6054          */
6055         err = tg3_init_rings(tp);
6056         if (err)
6057                 return err;
6058
6059         /* This value is determined during the probe time DMA
6060          * engine test, tg3_test_dma.
6061          */
6062         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6063
6064         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6065                           GRC_MODE_4X_NIC_SEND_RINGS |
6066                           GRC_MODE_NO_TX_PHDR_CSUM |
6067                           GRC_MODE_NO_RX_PHDR_CSUM);
6068         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6069
6070         /* Pseudo-header checksum is done by hardware logic and not
6071          * the offload processers, so make the chip do the pseudo-
6072          * header checksums on receive.  For transmit it is more
6073          * convenient to do the pseudo-header checksum in software
6074          * as Linux does that on transmit for us in all cases.
6075          */
6076         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6077
6078         tw32(GRC_MODE,
6079              tp->grc_mode |
6080              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6081
6082         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6083         val = tr32(GRC_MISC_CFG);
6084         val &= ~0xff;
6085         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6086         tw32(GRC_MISC_CFG, val);
6087
6088         /* Initialize MBUF/DESC pool. */
6089         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6090                 /* Do nothing.  */
6091         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6092                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6094                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6095                 else
6096                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6097                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6098                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6099         }
6100 #if TG3_TSO_SUPPORT != 0
6101         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6102                 int fw_len;
6103
6104                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6105                           TG3_TSO5_FW_RODATA_LEN +
6106                           TG3_TSO5_FW_DATA_LEN +
6107                           TG3_TSO5_FW_SBSS_LEN +
6108                           TG3_TSO5_FW_BSS_LEN);
6109                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6110                 tw32(BUFMGR_MB_POOL_ADDR,
6111                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6112                 tw32(BUFMGR_MB_POOL_SIZE,
6113                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6114         }
6115 #endif
6116
6117         if (tp->dev->mtu <= ETH_DATA_LEN) {
6118                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6119                      tp->bufmgr_config.mbuf_read_dma_low_water);
6120                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6121                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6122                 tw32(BUFMGR_MB_HIGH_WATER,
6123                      tp->bufmgr_config.mbuf_high_water);
6124         } else {
6125                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6126                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6127                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6128                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6129                 tw32(BUFMGR_MB_HIGH_WATER,
6130                      tp->bufmgr_config.mbuf_high_water_jumbo);
6131         }
6132         tw32(BUFMGR_DMA_LOW_WATER,
6133              tp->bufmgr_config.dma_low_water);
6134         tw32(BUFMGR_DMA_HIGH_WATER,
6135              tp->bufmgr_config.dma_high_water);
6136
6137         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6138         for (i = 0; i < 2000; i++) {
6139                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6140                         break;
6141                 udelay(10);
6142         }
6143         if (i >= 2000) {
6144                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6145                        tp->dev->name);
6146                 return -ENODEV;
6147         }
6148
6149         /* Setup replenish threshold. */
6150         val = tp->rx_pending / 8;
6151         if (val == 0)
6152                 val = 1;
6153         else if (val > tp->rx_std_max_post)
6154                 val = tp->rx_std_max_post;
6155         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6156                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6157                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6158
6159                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6160                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6161         }
6162
6163         tw32(RCVBDI_STD_THRESH, val);
6164
6165         /* Initialize TG3_BDINFO's at:
6166          *  RCVDBDI_STD_BD:     standard eth size rx ring
6167          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6168          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6169          *
6170          * like so:
6171          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6172          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6173          *                              ring attribute flags
6174          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6175          *
6176          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6177          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6178          *
6179          * The size of each ring is fixed in the firmware, but the location is
6180          * configurable.
6181          */
6182         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6183              ((u64) tp->rx_std_mapping >> 32));
6184         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6185              ((u64) tp->rx_std_mapping & 0xffffffff));
6186         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6187              NIC_SRAM_RX_BUFFER_DESC);
6188
6189         /* Don't even try to program the JUMBO/MINI buffer descriptor
6190          * configs on 5705.
6191          */
6192         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6193                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6194                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6195         } else {
6196                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6197                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6198
6199                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6200                      BDINFO_FLAGS_DISABLED);
6201
6202                 /* Setup replenish threshold. */
6203                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6204
6205                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6206                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6207                              ((u64) tp->rx_jumbo_mapping >> 32));
6208                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6209                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6210                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6211                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6212                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6213                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6214                 } else {
6215                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6216                              BDINFO_FLAGS_DISABLED);
6217                 }
6218
6219         }
6220
6221         /* There is only one send ring on 5705/5750, no need to explicitly
6222          * disable the others.
6223          */
6224         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6225                 /* Clear out send RCB ring in SRAM. */
6226                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6227                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6228                                       BDINFO_FLAGS_DISABLED);
6229         }
6230
6231         tp->tx_prod = 0;
6232         tp->tx_cons = 0;
6233         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6234         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6235
6236         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6237                        tp->tx_desc_mapping,
6238                        (TG3_TX_RING_SIZE <<
6239                         BDINFO_FLAGS_MAXLEN_SHIFT),
6240                        NIC_SRAM_TX_BUFFER_DESC);
6241
6242         /* There is only one receive return ring on 5705/5750, no need
6243          * to explicitly disable the others.
6244          */
6245         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6246                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6247                      i += TG3_BDINFO_SIZE) {
6248                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6249                                       BDINFO_FLAGS_DISABLED);
6250                 }
6251         }
6252
6253         tp->rx_rcb_ptr = 0;
6254         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6255
6256         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6257                        tp->rx_rcb_mapping,
6258                        (TG3_RX_RCB_RING_SIZE(tp) <<
6259                         BDINFO_FLAGS_MAXLEN_SHIFT),
6260                        0);
6261
6262         tp->rx_std_ptr = tp->rx_pending;
6263         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6264                      tp->rx_std_ptr);
6265
6266         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6267                                                 tp->rx_jumbo_pending : 0;
6268         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6269                      tp->rx_jumbo_ptr);
6270
6271         /* Initialize MAC address and backoff seed. */
6272         __tg3_set_mac_addr(tp);
6273
6274         /* MTU + ethernet header + FCS + optional VLAN tag */
6275         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6276
6277         /* The slot time is changed by tg3_setup_phy if we
6278          * run at gigabit with half duplex.
6279          */
6280         tw32(MAC_TX_LENGTHS,
6281              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6282              (6 << TX_LENGTHS_IPG_SHIFT) |
6283              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6284
6285         /* Receive rules. */
6286         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6287         tw32(RCVLPC_CONFIG, 0x0181);
6288
6289         /* Calculate RDMAC_MODE setting early, we need it to determine
6290          * the RCVLPC_STATE_ENABLE mask.
6291          */
6292         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6293                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6294                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6295                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6296                       RDMAC_MODE_LNGREAD_ENAB);
6297         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6298                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6299
6300         /* If statement applies to 5705 and 5750 PCI devices only */
6301         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6302              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6303             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6304                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6305                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6306                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6307                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6308                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6309                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6310                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6311                 }
6312         }
6313
6314         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6315                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6316
6317 #if TG3_TSO_SUPPORT != 0
6318         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6319                 rdmac_mode |= (1 << 27);
6320 #endif
6321
6322         /* Receive/send statistics. */
6323         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6324                 val = tr32(RCVLPC_STATS_ENABLE);
6325                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6326                 tw32(RCVLPC_STATS_ENABLE, val);
6327         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6328                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6329                 val = tr32(RCVLPC_STATS_ENABLE);
6330                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6331                 tw32(RCVLPC_STATS_ENABLE, val);
6332         } else {
6333                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6334         }
6335         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6336         tw32(SNDDATAI_STATSENAB, 0xffffff);
6337         tw32(SNDDATAI_STATSCTRL,
6338              (SNDDATAI_SCTRL_ENABLE |
6339               SNDDATAI_SCTRL_FASTUPD));
6340
6341         /* Setup host coalescing engine. */
6342         tw32(HOSTCC_MODE, 0);
6343         for (i = 0; i < 2000; i++) {
6344                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6345                         break;
6346                 udelay(10);
6347         }
6348
6349         __tg3_set_coalesce(tp, &tp->coal);
6350
6351         /* set status block DMA address */
6352         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6353              ((u64) tp->status_mapping >> 32));
6354         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6355              ((u64) tp->status_mapping & 0xffffffff));
6356
6357         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6358                 /* Status/statistics block address.  See tg3_timer,
6359                  * the tg3_periodic_fetch_stats call there, and
6360                  * tg3_get_stats to see how this works for 5705/5750 chips.
6361                  */
6362                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6363                      ((u64) tp->stats_mapping >> 32));
6364                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6365                      ((u64) tp->stats_mapping & 0xffffffff));
6366                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6367                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6368         }
6369
6370         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6371
6372         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6373         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6374         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6375                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6376
6377         /* Clear statistics/status block in chip, and status block in ram. */
6378         for (i = NIC_SRAM_STATS_BLK;
6379              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6380              i += sizeof(u32)) {
6381                 tg3_write_mem(tp, i, 0);
6382                 udelay(40);
6383         }
6384         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6385
6386         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6387                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6388                 /* reset to prevent losing 1st rx packet intermittently */
6389                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6390                 udelay(10);
6391         }
6392
6393         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6394                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6395         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6396         udelay(40);
6397
6398         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6399          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
6400          * register to preserve the GPIO settings for LOMs. The GPIOs,
6401          * whether used as inputs or outputs, are set by boot code after
6402          * reset.
6403          */
6404         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6405                 u32 gpio_mask;
6406
6407                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
6408                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
6409
6410                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6411                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6412                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6413
6414                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6415                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6416
6417                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6418
6419                 /* GPIO1 must be driven high for eeprom write protect */
6420                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6421                                        GRC_LCLCTRL_GPIO_OUTPUT1);
6422         }
6423         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6424         udelay(100);
6425
6426         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6427         tp->last_tag = 0;
6428
6429         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6430                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6431                 udelay(40);
6432         }
6433
6434         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6435                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6436                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6437                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6438                WDMAC_MODE_LNGREAD_ENAB);
6439
6440         /* If statement applies to 5705 and 5750 PCI devices only */
6441         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6442              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6443             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6444                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6445                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6446                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6447                         /* nothing */
6448                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6449                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6450                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6451                         val |= WDMAC_MODE_RX_ACCEL;
6452                 }
6453         }
6454
6455         /* Enable host coalescing bug fix */
6456         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6457             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6458                 val |= (1 << 29);
6459
6460         tw32_f(WDMAC_MODE, val);
6461         udelay(40);
6462
6463         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6464                 val = tr32(TG3PCI_X_CAPS);
6465                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6466                         val &= ~PCIX_CAPS_BURST_MASK;
6467                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6468                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6469                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6470                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6471                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6472                                 val |= (tp->split_mode_max_reqs <<
6473                                         PCIX_CAPS_SPLIT_SHIFT);
6474                 }
6475                 tw32(TG3PCI_X_CAPS, val);
6476         }
6477
6478         tw32_f(RDMAC_MODE, rdmac_mode);
6479         udelay(40);
6480
6481         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6482         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6483                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6484         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6485         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6486         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6487         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6488         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6489 #if TG3_TSO_SUPPORT != 0
6490         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6491                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6492 #endif
6493         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6494         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6495
6496         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6497                 err = tg3_load_5701_a0_firmware_fix(tp);
6498                 if (err)
6499                         return err;
6500         }
6501
6502 #if TG3_TSO_SUPPORT != 0
6503         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6504                 err = tg3_load_tso_firmware(tp);
6505                 if (err)
6506                         return err;
6507         }
6508 #endif
6509
6510         tp->tx_mode = TX_MODE_ENABLE;
6511         tw32_f(MAC_TX_MODE, tp->tx_mode);
6512         udelay(100);
6513
6514         tp->rx_mode = RX_MODE_ENABLE;
6515         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6516                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6517
6518         tw32_f(MAC_RX_MODE, tp->rx_mode);
6519         udelay(10);
6520
6521         if (tp->link_config.phy_is_low_power) {
6522                 tp->link_config.phy_is_low_power = 0;
6523                 tp->link_config.speed = tp->link_config.orig_speed;
6524                 tp->link_config.duplex = tp->link_config.orig_duplex;
6525                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6526         }
6527
6528         tp->mi_mode = MAC_MI_MODE_BASE;
6529         tw32_f(MAC_MI_MODE, tp->mi_mode);
6530         udelay(80);
6531
6532         tw32(MAC_LED_CTRL, tp->led_ctrl);
6533
6534         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6535         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6536                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6537                 udelay(10);
6538         }
6539         tw32_f(MAC_RX_MODE, tp->rx_mode);
6540         udelay(10);
6541
6542         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6543                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6544                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6545                         /* Set drive transmission level to 1.2V  */
6546                         /* only if the signal pre-emphasis bit is not set  */
6547                         val = tr32(MAC_SERDES_CFG);
6548                         val &= 0xfffff000;
6549                         val |= 0x880;
6550                         tw32(MAC_SERDES_CFG, val);
6551                 }
6552                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6553                         tw32(MAC_SERDES_CFG, 0x616000);
6554         }
6555
6556         /* Prevent chip from dropping frames when flow control
6557          * is enabled.
6558          */
6559         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6560
6561         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6562             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6563                 /* Use hardware link auto-negotiation */
6564                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6565         }
6566
6567         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6568             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6569                 u32 tmp;
6570
6571                 tmp = tr32(SERDES_RX_CTRL);
6572                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6573                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6574                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6575                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6576         }
6577
6578         err = tg3_setup_phy(tp, 0);
6579         if (err)
6580                 return err;
6581
6582         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6583             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6584                 u32 tmp;
6585
6586                 /* Clear CRC stats. */
6587                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6588                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6589                         tg3_readphy(tp, 0x14, &tmp);
6590                 }
6591         }
6592
6593         __tg3_set_rx_mode(tp->dev);
6594
6595         /* Initialize receive rules. */
6596         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6597         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6598         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6599         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6600
6601         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6602             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6603                 limit = 8;
6604         else
6605                 limit = 16;
6606         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6607                 limit -= 4;
6608         switch (limit) {
6609         case 16:
6610                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6611         case 15:
6612                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6613         case 14:
6614                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6615         case 13:
6616                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6617         case 12:
6618                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6619         case 11:
6620                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6621         case 10:
6622                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6623         case 9:
6624                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6625         case 8:
6626                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6627         case 7:
6628                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6629         case 6:
6630                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6631         case 5:
6632                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6633         case 4:
6634                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6635         case 3:
6636                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6637         case 2:
6638         case 1:
6639
6640         default:
6641                 break;
6642         };
6643
6644         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6645
6646         return 0;
6647 }
6648
6649 /* Called at device open time to get the chip ready for
6650  * packet processing.  Invoked with tp->lock held.
6651  */
6652 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6653 {
6654         int err;
6655
6656         /* Force the chip into D0. */
6657         err = tg3_set_power_state(tp, PCI_D0);
6658         if (err)
6659                 goto out;
6660
6661         tg3_switch_clocks(tp);
6662
6663         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6664
6665         err = tg3_reset_hw(tp, reset_phy);
6666
6667 out:
6668         return err;
6669 }
6670
6671 #define TG3_STAT_ADD32(PSTAT, REG) \
6672 do {    u32 __val = tr32(REG); \
6673         (PSTAT)->low += __val; \
6674         if ((PSTAT)->low < __val) \
6675                 (PSTAT)->high += 1; \
6676 } while (0)
6677
6678 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6679 {
6680         struct tg3_hw_stats *sp = tp->hw_stats;
6681
6682         if (!netif_carrier_ok(tp->dev))
6683                 return;
6684
6685         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6686         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6687         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6688         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6689         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6690         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6691         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6692         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6693         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6694         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6695         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6696         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6697         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6698
6699         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6700         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6701         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6702         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6703         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6704         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6705         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6706         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6707         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6708         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6709         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6710         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6711         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6712         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6713
6714         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6715         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6716         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6717 }
6718
6719 static void tg3_timer(unsigned long __opaque)
6720 {
6721         struct tg3 *tp = (struct tg3 *) __opaque;
6722
6723         if (tp->irq_sync)
6724                 goto restart_timer;
6725
6726         spin_lock(&tp->lock);
6727
6728         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6729                 /* All of this garbage is because when using non-tagged
6730                  * IRQ status the mailbox/status_block protocol the chip
6731                  * uses with the cpu is race prone.
6732                  */
6733                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6734                         tw32(GRC_LOCAL_CTRL,
6735                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6736                 } else {
6737                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6738                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6739                 }
6740
6741                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6742                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6743                         spin_unlock(&tp->lock);
6744                         schedule_work(&tp->reset_task);
6745                         return;
6746                 }
6747         }
6748
6749         /* This part only runs once per second. */
6750         if (!--tp->timer_counter) {
6751                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6752                         tg3_periodic_fetch_stats(tp);
6753
6754                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6755                         u32 mac_stat;
6756                         int phy_event;
6757
6758                         mac_stat = tr32(MAC_STATUS);
6759
6760                         phy_event = 0;
6761                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6762                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6763                                         phy_event = 1;
6764                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6765                                 phy_event = 1;
6766
6767                         if (phy_event)
6768                                 tg3_setup_phy(tp, 0);
6769                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6770                         u32 mac_stat = tr32(MAC_STATUS);
6771                         int need_setup = 0;
6772
6773                         if (netif_carrier_ok(tp->dev) &&
6774                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6775                                 need_setup = 1;
6776                         }
6777                         if (! netif_carrier_ok(tp->dev) &&
6778                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6779                                          MAC_STATUS_SIGNAL_DET))) {
6780                                 need_setup = 1;
6781                         }
6782                         if (need_setup) {
6783                                 if (!tp->serdes_counter) {
6784                                         tw32_f(MAC_MODE,
6785                                              (tp->mac_mode &
6786                                               ~MAC_MODE_PORT_MODE_MASK));
6787                                         udelay(40);
6788                                         tw32_f(MAC_MODE, tp->mac_mode);
6789                                         udelay(40);
6790                                 }
6791                                 tg3_setup_phy(tp, 0);
6792                         }
6793                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6794                         tg3_serdes_parallel_detect(tp);
6795
6796                 tp->timer_counter = tp->timer_multiplier;
6797         }
6798
6799         /* Heartbeat is only sent once every 2 seconds.
6800          *
6801          * The heartbeat is to tell the ASF firmware that the host
6802          * driver is still alive.  In the event that the OS crashes,
6803          * ASF needs to reset the hardware to free up the FIFO space
6804          * that may be filled with rx packets destined for the host.
6805          * If the FIFO is full, ASF will no longer function properly.
6806          *
6807          * Unintended resets have been reported on real time kernels
6808          * where the timer doesn't run on time.  Netpoll will also have
6809          * same problem.
6810          *
6811          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6812          * to check the ring condition when the heartbeat is expiring
6813          * before doing the reset.  This will prevent most unintended
6814          * resets.
6815          */
6816         if (!--tp->asf_counter) {
6817                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6818                         u32 val;
6819
6820                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6821                                       FWCMD_NICDRV_ALIVE3);
6822                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6823                         /* 5 seconds timeout */
6824                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6825                         val = tr32(GRC_RX_CPU_EVENT);
6826                         val |= (1 << 14);
6827                         tw32(GRC_RX_CPU_EVENT, val);
6828                 }
6829                 tp->asf_counter = tp->asf_multiplier;
6830         }
6831
6832         spin_unlock(&tp->lock);
6833
6834 restart_timer:
6835         tp->timer.expires = jiffies + tp->timer_offset;
6836         add_timer(&tp->timer);
6837 }
6838
6839 static int tg3_request_irq(struct tg3 *tp)
6840 {
6841         irq_handler_t fn;
6842         unsigned long flags;
6843         struct net_device *dev = tp->dev;
6844
6845         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6846                 fn = tg3_msi;
6847                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6848                         fn = tg3_msi_1shot;
6849                 flags = IRQF_SAMPLE_RANDOM;
6850         } else {
6851                 fn = tg3_interrupt;
6852                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6853                         fn = tg3_interrupt_tagged;
6854                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6855         }
6856         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6857 }
6858
6859 static int tg3_test_interrupt(struct tg3 *tp)
6860 {
6861         struct net_device *dev = tp->dev;
6862         int err, i, intr_ok = 0;
6863
6864         if (!netif_running(dev))
6865                 return -ENODEV;
6866
6867         tg3_disable_ints(tp);
6868
6869         free_irq(tp->pdev->irq, dev);
6870
6871         err = request_irq(tp->pdev->irq, tg3_test_isr,
6872                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6873         if (err)
6874                 return err;
6875
6876         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6877         tg3_enable_ints(tp);
6878
6879         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6880                HOSTCC_MODE_NOW);
6881
6882         for (i = 0; i < 5; i++) {
6883                 u32 int_mbox, misc_host_ctrl;
6884
6885                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6886                                         TG3_64BIT_REG_LOW);
6887                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6888
6889                 if ((int_mbox != 0) ||
6890                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6891                         intr_ok = 1;
6892                         break;
6893                 }
6894
6895                 msleep(10);
6896         }
6897
6898         tg3_disable_ints(tp);
6899
6900         free_irq(tp->pdev->irq, dev);
6901
6902         err = tg3_request_irq(tp);
6903
6904         if (err)
6905                 return err;
6906
6907         if (intr_ok)
6908                 return 0;
6909
6910         return -EIO;
6911 }
6912
6913 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6914  * successfully restored
6915  */
6916 static int tg3_test_msi(struct tg3 *tp)
6917 {
6918         struct net_device *dev = tp->dev;
6919         int err;
6920         u16 pci_cmd;
6921
6922         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6923                 return 0;
6924
6925         /* Turn off SERR reporting in case MSI terminates with Master
6926          * Abort.
6927          */
6928         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6929         pci_write_config_word(tp->pdev, PCI_COMMAND,
6930                               pci_cmd & ~PCI_COMMAND_SERR);
6931
6932         err = tg3_test_interrupt(tp);
6933
6934         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6935
6936         if (!err)
6937                 return 0;
6938
6939         /* other failures */
6940         if (err != -EIO)
6941                 return err;
6942
6943         /* MSI test failed, go back to INTx mode */
6944         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6945                "switching to INTx mode. Please report this failure to "
6946                "the PCI maintainer and include system chipset information.\n",
6947                        tp->dev->name);
6948
6949         free_irq(tp->pdev->irq, dev);
6950         pci_disable_msi(tp->pdev);
6951
6952         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6953
6954         err = tg3_request_irq(tp);
6955         if (err)
6956                 return err;
6957
6958         /* Need to reset the chip because the MSI cycle may have terminated
6959          * with Master Abort.
6960          */
6961         tg3_full_lock(tp, 1);
6962
6963         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6964         err = tg3_init_hw(tp, 1);
6965
6966         tg3_full_unlock(tp);
6967
6968         if (err)
6969                 free_irq(tp->pdev->irq, dev);
6970
6971         return err;
6972 }
6973
6974 static int tg3_open(struct net_device *dev)
6975 {
6976         struct tg3 *tp = netdev_priv(dev);
6977         int err;
6978
6979         tg3_full_lock(tp, 0);
6980
6981         err = tg3_set_power_state(tp, PCI_D0);
6982         if (err)
6983                 return err;
6984
6985         tg3_disable_ints(tp);
6986         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6987
6988         tg3_full_unlock(tp);
6989
6990         /* The placement of this call is tied
6991          * to the setup and use of Host TX descriptors.
6992          */
6993         err = tg3_alloc_consistent(tp);
6994         if (err)
6995                 return err;
6996
6997         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6998             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6999             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7000             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7001               (tp->pdev_peer == tp->pdev))) {
7002                 /* All MSI supporting chips should support tagged
7003                  * status.  Assert that this is the case.
7004                  */
7005                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7006                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7007                                "Not using MSI.\n", tp->dev->name);
7008                 } else if (pci_enable_msi(tp->pdev) == 0) {
7009                         u32 msi_mode;
7010
7011                         msi_mode = tr32(MSGINT_MODE);
7012                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7013                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7014                 }
7015         }
7016         err = tg3_request_irq(tp);
7017
7018         if (err) {
7019                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7020                         pci_disable_msi(tp->pdev);
7021                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7022                 }
7023                 tg3_free_consistent(tp);
7024                 return err;
7025         }
7026
7027         tg3_full_lock(tp, 0);
7028
7029         err = tg3_init_hw(tp, 1);
7030         if (err) {
7031                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7032                 tg3_free_rings(tp);
7033         } else {
7034                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7035                         tp->timer_offset = HZ;
7036                 else
7037                         tp->timer_offset = HZ / 10;
7038
7039                 BUG_ON(tp->timer_offset > HZ);
7040                 tp->timer_counter = tp->timer_multiplier =
7041                         (HZ / tp->timer_offset);
7042                 tp->asf_counter = tp->asf_multiplier =
7043                         ((HZ / tp->timer_offset) * 2);
7044
7045                 init_timer(&tp->timer);
7046                 tp->timer.expires = jiffies + tp->timer_offset;
7047                 tp->timer.data = (unsigned long) tp;
7048                 tp->timer.function = tg3_timer;
7049         }
7050
7051         tg3_full_unlock(tp);
7052
7053         if (err) {
7054                 free_irq(tp->pdev->irq, dev);
7055                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7056                         pci_disable_msi(tp->pdev);
7057                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7058                 }
7059                 tg3_free_consistent(tp);
7060                 return err;
7061         }
7062
7063         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7064                 err = tg3_test_msi(tp);
7065
7066                 if (err) {
7067                         tg3_full_lock(tp, 0);
7068
7069                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7070                                 pci_disable_msi(tp->pdev);
7071                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7072                         }
7073                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7074                         tg3_free_rings(tp);
7075                         tg3_free_consistent(tp);
7076
7077                         tg3_full_unlock(tp);
7078
7079                         return err;
7080                 }
7081
7082                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7083                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7084                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7085
7086                                 tw32(PCIE_TRANSACTION_CFG,
7087                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7088                         }
7089                 }
7090         }
7091
7092         tg3_full_lock(tp, 0);
7093
7094         add_timer(&tp->timer);
7095         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7096         tg3_enable_ints(tp);
7097
7098         tg3_full_unlock(tp);
7099
7100         netif_start_queue(dev);
7101
7102         return 0;
7103 }
7104
7105 #if 0
7106 /*static*/ void tg3_dump_state(struct tg3 *tp)
7107 {
7108         u32 val32, val32_2, val32_3, val32_4, val32_5;
7109         u16 val16;
7110         int i;
7111
7112         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7113         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7114         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7115                val16, val32);
7116
7117         /* MAC block */
7118         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7119                tr32(MAC_MODE), tr32(MAC_STATUS));
7120         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7121                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7122         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7123                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7124         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7125                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7126
7127         /* Send data initiator control block */
7128         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7129                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7130         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7131                tr32(SNDDATAI_STATSCTRL));
7132
7133         /* Send data completion control block */
7134         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7135
7136         /* Send BD ring selector block */
7137         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7138                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7139
7140         /* Send BD initiator control block */
7141         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7142                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7143
7144         /* Send BD completion control block */
7145         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7146
7147         /* Receive list placement control block */
7148         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7149                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7150         printk("       RCVLPC_STATSCTRL[%08x]\n",
7151                tr32(RCVLPC_STATSCTRL));
7152
7153         /* Receive data and receive BD initiator control block */
7154         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7155                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7156
7157         /* Receive data completion control block */
7158         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7159                tr32(RCVDCC_MODE));
7160
7161         /* Receive BD initiator control block */
7162         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7163                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7164
7165         /* Receive BD completion control block */
7166         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7167                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7168
7169         /* Receive list selector control block */
7170         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7171                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7172
7173         /* Mbuf cluster free block */
7174         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7175                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7176
7177         /* Host coalescing control block */
7178         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7179                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7180         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7181                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7182                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7183         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7184                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7185                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7186         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7187                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7188         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7189                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7190
7191         /* Memory arbiter control block */
7192         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7193                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7194
7195         /* Buffer manager control block */
7196         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7197                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7198         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7199                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7200         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7201                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7202                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7203                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7204
7205         /* Read DMA control block */
7206         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7207                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7208
7209         /* Write DMA control block */
7210         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7211                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7212
7213         /* DMA completion block */
7214         printk("DEBUG: DMAC_MODE[%08x]\n",
7215                tr32(DMAC_MODE));
7216
7217         /* GRC block */
7218         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7219                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7220         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7221                tr32(GRC_LOCAL_CTRL));
7222
7223         /* TG3_BDINFOs */
7224         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7225                tr32(RCVDBDI_JUMBO_BD + 0x0),
7226                tr32(RCVDBDI_JUMBO_BD + 0x4),
7227                tr32(RCVDBDI_JUMBO_BD + 0x8),
7228                tr32(RCVDBDI_JUMBO_BD + 0xc));
7229         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7230                tr32(RCVDBDI_STD_BD + 0x0),
7231                tr32(RCVDBDI_STD_BD + 0x4),
7232                tr32(RCVDBDI_STD_BD + 0x8),
7233                tr32(RCVDBDI_STD_BD + 0xc));
7234         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7235                tr32(RCVDBDI_MINI_BD + 0x0),
7236                tr32(RCVDBDI_MINI_BD + 0x4),
7237                tr32(RCVDBDI_MINI_BD + 0x8),
7238                tr32(RCVDBDI_MINI_BD + 0xc));
7239
7240         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7241         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7242         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7243         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7244         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7245                val32, val32_2, val32_3, val32_4);
7246
7247         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7248         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7249         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7250         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7251         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7252                val32, val32_2, val32_3, val32_4);
7253
7254         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7255         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7256         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7257         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7258         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7259         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7260                val32, val32_2, val32_3, val32_4, val32_5);
7261
7262         /* SW status block */
7263         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7264                tp->hw_status->status,
7265                tp->hw_status->status_tag,
7266                tp->hw_status->rx_jumbo_consumer,
7267                tp->hw_status->rx_consumer,
7268                tp->hw_status->rx_mini_consumer,
7269                tp->hw_status->idx[0].rx_producer,
7270                tp->hw_status->idx[0].tx_consumer);
7271
7272         /* SW statistics block */
7273         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7274                ((u32 *)tp->hw_stats)[0],
7275                ((u32 *)tp->hw_stats)[1],
7276                ((u32 *)tp->hw_stats)[2],
7277                ((u32 *)tp->hw_stats)[3]);
7278
7279         /* Mailboxes */
7280         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7281                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7282                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7283                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7284                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7285
7286         /* NIC side send descriptors. */
7287         for (i = 0; i < 6; i++) {
7288                 unsigned long txd;
7289
7290                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7291                         + (i * sizeof(struct tg3_tx_buffer_desc));
7292                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7293                        i,
7294                        readl(txd + 0x0), readl(txd + 0x4),
7295                        readl(txd + 0x8), readl(txd + 0xc));
7296         }
7297
7298         /* NIC side RX descriptors. */
7299         for (i = 0; i < 6; i++) {
7300                 unsigned long rxd;
7301
7302                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7303                         + (i * sizeof(struct tg3_rx_buffer_desc));
7304                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7305                        i,
7306                        readl(rxd + 0x0), readl(rxd + 0x4),
7307                        readl(rxd + 0x8), readl(rxd + 0xc));
7308                 rxd += (4 * sizeof(u32));
7309                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7310                        i,
7311                        readl(rxd + 0x0), readl(rxd + 0x4),
7312                        readl(rxd + 0x8), readl(rxd + 0xc));
7313         }
7314
7315         for (i = 0; i < 6; i++) {
7316                 unsigned long rxd;
7317
7318                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7319                         + (i * sizeof(struct tg3_rx_buffer_desc));
7320                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7321                        i,
7322                        readl(rxd + 0x0), readl(rxd + 0x4),
7323                        readl(rxd + 0x8), readl(rxd + 0xc));
7324                 rxd += (4 * sizeof(u32));
7325                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7326                        i,
7327                        readl(rxd + 0x0), readl(rxd + 0x4),
7328                        readl(rxd + 0x8), readl(rxd + 0xc));
7329         }
7330 }
7331 #endif
7332
7333 static struct net_device_stats *tg3_get_stats(struct net_device *);
7334 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7335
7336 static int tg3_close(struct net_device *dev)
7337 {
7338         struct tg3 *tp = netdev_priv(dev);
7339
7340         /* Calling flush_scheduled_work() may deadlock because
7341          * linkwatch_event() may be on the workqueue and it will try to get
7342          * the rtnl_lock which we are holding.
7343          */
7344         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7345                 msleep(1);
7346
7347         netif_stop_queue(dev);
7348
7349         del_timer_sync(&tp->timer);
7350
7351         tg3_full_lock(tp, 1);
7352 #if 0
7353         tg3_dump_state(tp);
7354 #endif
7355
7356         tg3_disable_ints(tp);
7357
7358         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7359         tg3_free_rings(tp);
7360         tp->tg3_flags &=
7361                 ~(TG3_FLAG_INIT_COMPLETE |
7362                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7363
7364         tg3_full_unlock(tp);
7365
7366         free_irq(tp->pdev->irq, dev);
7367         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7368                 pci_disable_msi(tp->pdev);
7369                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7370         }
7371
7372         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7373                sizeof(tp->net_stats_prev));
7374         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7375                sizeof(tp->estats_prev));
7376
7377         tg3_free_consistent(tp);
7378
7379         tg3_set_power_state(tp, PCI_D3hot);
7380
7381         netif_carrier_off(tp->dev);
7382
7383         return 0;
7384 }
7385
7386 static inline unsigned long get_stat64(tg3_stat64_t *val)
7387 {
7388         unsigned long ret;
7389
7390 #if (BITS_PER_LONG == 32)
7391         ret = val->low;
7392 #else
7393         ret = ((u64)val->high << 32) | ((u64)val->low);
7394 #endif
7395         return ret;
7396 }
7397
7398 static unsigned long calc_crc_errors(struct tg3 *tp)
7399 {
7400         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7401
7402         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7403             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7404              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7405                 u32 val;
7406
7407                 spin_lock_bh(&tp->lock);
7408                 if (!tg3_readphy(tp, 0x1e, &val)) {
7409                         tg3_writephy(tp, 0x1e, val | 0x8000);
7410                         tg3_readphy(tp, 0x14, &val);
7411                 } else
7412                         val = 0;
7413                 spin_unlock_bh(&tp->lock);
7414
7415                 tp->phy_crc_errors += val;
7416
7417                 return tp->phy_crc_errors;
7418         }
7419
7420         return get_stat64(&hw_stats->rx_fcs_errors);
7421 }
7422
7423 #define ESTAT_ADD(member) \
7424         estats->member =        old_estats->member + \
7425                                 get_stat64(&hw_stats->member)
7426
7427 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7428 {
7429         struct tg3_ethtool_stats *estats = &tp->estats;
7430         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7431         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7432
7433         if (!hw_stats)
7434                 return old_estats;
7435
7436         ESTAT_ADD(rx_octets);
7437         ESTAT_ADD(rx_fragments);
7438         ESTAT_ADD(rx_ucast_packets);
7439         ESTAT_ADD(rx_mcast_packets);
7440         ESTAT_ADD(rx_bcast_packets);
7441         ESTAT_ADD(rx_fcs_errors);
7442         ESTAT_ADD(rx_align_errors);
7443         ESTAT_ADD(rx_xon_pause_rcvd);
7444         ESTAT_ADD(rx_xoff_pause_rcvd);
7445         ESTAT_ADD(rx_mac_ctrl_rcvd);
7446         ESTAT_ADD(rx_xoff_entered);
7447         ESTAT_ADD(rx_frame_too_long_errors);
7448         ESTAT_ADD(rx_jabbers);
7449         ESTAT_ADD(rx_undersize_packets);
7450         ESTAT_ADD(rx_in_length_errors);
7451         ESTAT_ADD(rx_out_length_errors);
7452         ESTAT_ADD(rx_64_or_less_octet_packets);
7453         ESTAT_ADD(rx_65_to_127_octet_packets);
7454         ESTAT_ADD(rx_128_to_255_octet_packets);
7455         ESTAT_ADD(rx_256_to_511_octet_packets);
7456         ESTAT_ADD(rx_512_to_1023_octet_packets);
7457         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7458         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7459         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7460         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7461         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7462
7463         ESTAT_ADD(tx_octets);
7464         ESTAT_ADD(tx_collisions);
7465         ESTAT_ADD(tx_xon_sent);
7466         ESTAT_ADD(tx_xoff_sent);
7467         ESTAT_ADD(tx_flow_control);
7468         ESTAT_ADD(tx_mac_errors);
7469         ESTAT_ADD(tx_single_collisions);
7470         ESTAT_ADD(tx_mult_collisions);
7471         ESTAT_ADD(tx_deferred);
7472         ESTAT_ADD(tx_excessive_collisions);
7473         ESTAT_ADD(tx_late_collisions);
7474         ESTAT_ADD(tx_collide_2times);
7475         ESTAT_ADD(tx_collide_3times);
7476         ESTAT_ADD(tx_collide_4times);
7477         ESTAT_ADD(tx_collide_5times);
7478         ESTAT_ADD(tx_collide_6times);
7479         ESTAT_ADD(tx_collide_7times);
7480         ESTAT_ADD(tx_collide_8times);
7481         ESTAT_ADD(tx_collide_9times);
7482         ESTAT_ADD(tx_collide_10times);
7483         ESTAT_ADD(tx_collide_11times);
7484         ESTAT_ADD(tx_collide_12times);
7485         ESTAT_ADD(tx_collide_13times);
7486         ESTAT_ADD(tx_collide_14times);
7487         ESTAT_ADD(tx_collide_15times);
7488         ESTAT_ADD(tx_ucast_packets);
7489         ESTAT_ADD(tx_mcast_packets);
7490         ESTAT_ADD(tx_bcast_packets);
7491         ESTAT_ADD(tx_carrier_sense_errors);
7492         ESTAT_ADD(tx_discards);
7493         ESTAT_ADD(tx_errors);
7494
7495         ESTAT_ADD(dma_writeq_full);
7496         ESTAT_ADD(dma_write_prioq_full);
7497         ESTAT_ADD(rxbds_empty);
7498         ESTAT_ADD(rx_discards);
7499         ESTAT_ADD(rx_errors);
7500         ESTAT_ADD(rx_threshold_hit);
7501
7502         ESTAT_ADD(dma_readq_full);
7503         ESTAT_ADD(dma_read_prioq_full);
7504         ESTAT_ADD(tx_comp_queue_full);
7505
7506         ESTAT_ADD(ring_set_send_prod_index);
7507         ESTAT_ADD(ring_status_update);
7508         ESTAT_ADD(nic_irqs);
7509         ESTAT_ADD(nic_avoided_irqs);
7510         ESTAT_ADD(nic_tx_threshold_hit);
7511
7512         return estats;
7513 }
7514
7515 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7516 {
7517         struct tg3 *tp = netdev_priv(dev);
7518         struct net_device_stats *stats = &tp->net_stats;
7519         struct net_device_stats *old_stats = &tp->net_stats_prev;
7520         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7521
7522         if (!hw_stats)
7523                 return old_stats;
7524
7525         stats->rx_packets = old_stats->rx_packets +
7526                 get_stat64(&hw_stats->rx_ucast_packets) +
7527                 get_stat64(&hw_stats->rx_mcast_packets) +
7528                 get_stat64(&hw_stats->rx_bcast_packets);
7529
7530         stats->tx_packets = old_stats->tx_packets +
7531                 get_stat64(&hw_stats->tx_ucast_packets) +
7532                 get_stat64(&hw_stats->tx_mcast_packets) +
7533                 get_stat64(&hw_stats->tx_bcast_packets);
7534
7535         stats->rx_bytes = old_stats->rx_bytes +
7536                 get_stat64(&hw_stats->rx_octets);
7537         stats->tx_bytes = old_stats->tx_bytes +
7538                 get_stat64(&hw_stats->tx_octets);
7539
7540         stats->rx_errors = old_stats->rx_errors +
7541                 get_stat64(&hw_stats->rx_errors);
7542         stats->tx_errors = old_stats->tx_errors +
7543                 get_stat64(&hw_stats->tx_errors) +
7544                 get_stat64(&hw_stats->tx_mac_errors) +
7545                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7546                 get_stat64(&hw_stats->tx_discards);
7547
7548         stats->multicast = old_stats->multicast +
7549                 get_stat64(&hw_stats->rx_mcast_packets);
7550         stats->collisions = old_stats->collisions +
7551                 get_stat64(&hw_stats->tx_collisions);
7552
7553         stats->rx_length_errors = old_stats->rx_length_errors +
7554                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7555                 get_stat64(&hw_stats->rx_undersize_packets);
7556
7557         stats->rx_over_errors = old_stats->rx_over_errors +
7558                 get_stat64(&hw_stats->rxbds_empty);
7559         stats->rx_frame_errors = old_stats->rx_frame_errors +
7560                 get_stat64(&hw_stats->rx_align_errors);
7561         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7562                 get_stat64(&hw_stats->tx_discards);
7563         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7564                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7565
7566         stats->rx_crc_errors = old_stats->rx_crc_errors +
7567                 calc_crc_errors(tp);
7568
7569         stats->rx_missed_errors = old_stats->rx_missed_errors +
7570                 get_stat64(&hw_stats->rx_discards);
7571
7572         return stats;
7573 }
7574
7575 static inline u32 calc_crc(unsigned char *buf, int len)
7576 {
7577         u32 reg;
7578         u32 tmp;
7579         int j, k;
7580
7581         reg = 0xffffffff;
7582
7583         for (j = 0; j < len; j++) {
7584                 reg ^= buf[j];
7585
7586                 for (k = 0; k < 8; k++) {
7587                         tmp = reg & 0x01;
7588
7589                         reg >>= 1;
7590
7591                         if (tmp) {
7592                                 reg ^= 0xedb88320;
7593                         }
7594                 }
7595         }
7596
7597         return ~reg;
7598 }
7599
7600 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7601 {
7602         /* accept or reject all multicast frames */
7603         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7604         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7605         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7606         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7607 }
7608
7609 static void __tg3_set_rx_mode(struct net_device *dev)
7610 {
7611         struct tg3 *tp = netdev_priv(dev);
7612         u32 rx_mode;
7613
7614         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7615                                   RX_MODE_KEEP_VLAN_TAG);
7616
7617         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7618          * flag clear.
7619          */
7620 #if TG3_VLAN_TAG_USED
7621         if (!tp->vlgrp &&
7622             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7623                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7624 #else
7625         /* By definition, VLAN is disabled always in this
7626          * case.
7627          */
7628         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7629                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7630 #endif
7631
7632         if (dev->flags & IFF_PROMISC) {
7633                 /* Promiscuous mode. */
7634                 rx_mode |= RX_MODE_PROMISC;
7635         } else if (dev->flags & IFF_ALLMULTI) {
7636                 /* Accept all multicast. */
7637                 tg3_set_multi (tp, 1);
7638         } else if (dev->mc_count < 1) {
7639                 /* Reject all multicast. */
7640                 tg3_set_multi (tp, 0);
7641         } else {
7642                 /* Accept one or more multicast(s). */
7643                 struct dev_mc_list *mclist;
7644                 unsigned int i;
7645                 u32 mc_filter[4] = { 0, };
7646                 u32 regidx;
7647                 u32 bit;
7648                 u32 crc;
7649
7650                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7651                      i++, mclist = mclist->next) {
7652
7653                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7654                         bit = ~crc & 0x7f;
7655                         regidx = (bit & 0x60) >> 5;
7656                         bit &= 0x1f;
7657                         mc_filter[regidx] |= (1 << bit);
7658                 }
7659
7660                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7661                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7662                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7663                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7664         }
7665
7666         if (rx_mode != tp->rx_mode) {
7667                 tp->rx_mode = rx_mode;
7668                 tw32_f(MAC_RX_MODE, rx_mode);
7669                 udelay(10);
7670         }
7671 }
7672
7673 static void tg3_set_rx_mode(struct net_device *dev)
7674 {
7675         struct tg3 *tp = netdev_priv(dev);
7676
7677         if (!netif_running(dev))
7678                 return;
7679
7680         tg3_full_lock(tp, 0);
7681         __tg3_set_rx_mode(dev);
7682         tg3_full_unlock(tp);
7683 }
7684
7685 #define TG3_REGDUMP_LEN         (32 * 1024)
7686
7687 static int tg3_get_regs_len(struct net_device *dev)
7688 {
7689         return TG3_REGDUMP_LEN;
7690 }
7691
7692 static void tg3_get_regs(struct net_device *dev,
7693                 struct ethtool_regs *regs, void *_p)
7694 {
7695         u32 *p = _p;
7696         struct tg3 *tp = netdev_priv(dev);
7697         u8 *orig_p = _p;
7698         int i;
7699
7700         regs->version = 0;
7701
7702         memset(p, 0, TG3_REGDUMP_LEN);
7703
7704         if (tp->link_config.phy_is_low_power)
7705                 return;
7706
7707         tg3_full_lock(tp, 0);
7708
7709 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7710 #define GET_REG32_LOOP(base,len)                \
7711 do {    p = (u32 *)(orig_p + (base));           \
7712         for (i = 0; i < len; i += 4)            \
7713                 __GET_REG32((base) + i);        \
7714 } while (0)
7715 #define GET_REG32_1(reg)                        \
7716 do {    p = (u32 *)(orig_p + (reg));            \
7717         __GET_REG32((reg));                     \
7718 } while (0)
7719
7720         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7721         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7722         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7723         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7724         GET_REG32_1(SNDDATAC_MODE);
7725         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7726         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7727         GET_REG32_1(SNDBDC_MODE);
7728         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7729         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7730         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7731         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7732         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7733         GET_REG32_1(RCVDCC_MODE);
7734         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7735         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7736         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7737         GET_REG32_1(MBFREE_MODE);
7738         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7739         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7740         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7741         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7742         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7743         GET_REG32_1(RX_CPU_MODE);
7744         GET_REG32_1(RX_CPU_STATE);
7745         GET_REG32_1(RX_CPU_PGMCTR);
7746         GET_REG32_1(RX_CPU_HWBKPT);
7747         GET_REG32_1(TX_CPU_MODE);
7748         GET_REG32_1(TX_CPU_STATE);
7749         GET_REG32_1(TX_CPU_PGMCTR);
7750         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7751         GET_REG32_LOOP(FTQ_RESET, 0x120);
7752         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7753         GET_REG32_1(DMAC_MODE);
7754         GET_REG32_LOOP(GRC_MODE, 0x4c);
7755         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7756                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7757
7758 #undef __GET_REG32
7759 #undef GET_REG32_LOOP
7760 #undef GET_REG32_1
7761
7762         tg3_full_unlock(tp);
7763 }
7764
7765 static int tg3_get_eeprom_len(struct net_device *dev)
7766 {
7767         struct tg3 *tp = netdev_priv(dev);
7768
7769         return tp->nvram_size;
7770 }
7771
7772 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7773 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7774
7775 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7776 {
7777         struct tg3 *tp = netdev_priv(dev);
7778         int ret;
7779         u8  *pd;
7780         u32 i, offset, len, val, b_offset, b_count;
7781
7782         if (tp->link_config.phy_is_low_power)
7783                 return -EAGAIN;
7784
7785         offset = eeprom->offset;
7786         len = eeprom->len;
7787         eeprom->len = 0;
7788
7789         eeprom->magic = TG3_EEPROM_MAGIC;
7790
7791         if (offset & 3) {
7792                 /* adjustments to start on required 4 byte boundary */
7793                 b_offset = offset & 3;
7794                 b_count = 4 - b_offset;
7795                 if (b_count > len) {
7796                         /* i.e. offset=1 len=2 */
7797                         b_count = len;
7798                 }
7799                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7800                 if (ret)
7801                         return ret;
7802                 val = cpu_to_le32(val);
7803                 memcpy(data, ((char*)&val) + b_offset, b_count);
7804                 len -= b_count;
7805                 offset += b_count;
7806                 eeprom->len += b_count;
7807         }
7808
7809         /* read bytes upto the last 4 byte boundary */
7810         pd = &data[eeprom->len];
7811         for (i = 0; i < (len - (len & 3)); i += 4) {
7812                 ret = tg3_nvram_read(tp, offset + i, &val);
7813                 if (ret) {
7814                         eeprom->len += i;
7815                         return ret;
7816                 }
7817                 val = cpu_to_le32(val);
7818                 memcpy(pd + i, &val, 4);
7819         }
7820         eeprom->len += i;
7821
7822         if (len & 3) {
7823                 /* read last bytes not ending on 4 byte boundary */
7824                 pd = &data[eeprom->len];
7825                 b_count = len & 3;
7826                 b_offset = offset + len - b_count;
7827                 ret = tg3_nvram_read(tp, b_offset, &val);
7828                 if (ret)
7829                         return ret;
7830                 val = cpu_to_le32(val);
7831                 memcpy(pd, ((char*)&val), b_count);
7832                 eeprom->len += b_count;
7833         }
7834         return 0;
7835 }
7836
7837 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7838
7839 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7840 {
7841         struct tg3 *tp = netdev_priv(dev);
7842         int ret;
7843         u32 offset, len, b_offset, odd_len, start, end;
7844         u8 *buf;
7845
7846         if (tp->link_config.phy_is_low_power)
7847                 return -EAGAIN;
7848
7849         if (eeprom->magic != TG3_EEPROM_MAGIC)
7850                 return -EINVAL;
7851
7852         offset = eeprom->offset;
7853         len = eeprom->len;
7854
7855         if ((b_offset = (offset & 3))) {
7856                 /* adjustments to start on required 4 byte boundary */
7857                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7858                 if (ret)
7859                         return ret;
7860                 start = cpu_to_le32(start);
7861                 len += b_offset;
7862                 offset &= ~3;
7863                 if (len < 4)
7864                         len = 4;
7865         }
7866
7867         odd_len = 0;
7868         if (len & 3) {
7869                 /* adjustments to end on required 4 byte boundary */
7870                 odd_len = 1;
7871                 len = (len + 3) & ~3;
7872                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7873                 if (ret)
7874                         return ret;
7875                 end = cpu_to_le32(end);
7876         }
7877
7878         buf = data;
7879         if (b_offset || odd_len) {
7880                 buf = kmalloc(len, GFP_KERNEL);
7881                 if (buf == 0)
7882                         return -ENOMEM;
7883                 if (b_offset)
7884                         memcpy(buf, &start, 4);
7885                 if (odd_len)
7886                         memcpy(buf+len-4, &end, 4);
7887                 memcpy(buf + b_offset, data, eeprom->len);
7888         }
7889
7890         ret = tg3_nvram_write_block(tp, offset, len, buf);
7891
7892         if (buf != data)
7893                 kfree(buf);
7894
7895         return ret;
7896 }
7897
7898 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7899 {
7900         struct tg3 *tp = netdev_priv(dev);
7901
7902         cmd->supported = (SUPPORTED_Autoneg);
7903
7904         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7905                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7906                                    SUPPORTED_1000baseT_Full);
7907
7908         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7909                 cmd->supported |= (SUPPORTED_100baseT_Half |
7910                                   SUPPORTED_100baseT_Full |
7911                                   SUPPORTED_10baseT_Half |
7912                                   SUPPORTED_10baseT_Full |
7913                                   SUPPORTED_MII);
7914                 cmd->port = PORT_TP;
7915         } else {
7916                 cmd->supported |= SUPPORTED_FIBRE;
7917                 cmd->port = PORT_FIBRE;
7918         }
7919
7920         cmd->advertising = tp->link_config.advertising;
7921         if (netif_running(dev)) {
7922                 cmd->speed = tp->link_config.active_speed;
7923                 cmd->duplex = tp->link_config.active_duplex;
7924         }
7925         cmd->phy_address = PHY_ADDR;
7926         cmd->transceiver = 0;
7927         cmd->autoneg = tp->link_config.autoneg;
7928         cmd->maxtxpkt = 0;
7929         cmd->maxrxpkt = 0;
7930         return 0;
7931 }
7932
7933 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7934 {
7935         struct tg3 *tp = netdev_priv(dev);
7936
7937         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7938                 /* These are the only valid advertisement bits allowed.  */
7939                 if (cmd->autoneg == AUTONEG_ENABLE &&
7940                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7941                                           ADVERTISED_1000baseT_Full |
7942                                           ADVERTISED_Autoneg |
7943                                           ADVERTISED_FIBRE)))
7944                         return -EINVAL;
7945                 /* Fiber can only do SPEED_1000.  */
7946                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7947                          (cmd->speed != SPEED_1000))
7948                         return -EINVAL;
7949         /* Copper cannot force SPEED_1000.  */
7950         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7951                    (cmd->speed == SPEED_1000))
7952                 return -EINVAL;
7953         else if ((cmd->speed == SPEED_1000) &&
7954                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7955                 return -EINVAL;
7956
7957         tg3_full_lock(tp, 0);
7958
7959         tp->link_config.autoneg = cmd->autoneg;
7960         if (cmd->autoneg == AUTONEG_ENABLE) {
7961                 tp->link_config.advertising = cmd->advertising;
7962                 tp->link_config.speed = SPEED_INVALID;
7963                 tp->link_config.duplex = DUPLEX_INVALID;
7964         } else {
7965                 tp->link_config.advertising = 0;
7966                 tp->link_config.speed = cmd->speed;
7967                 tp->link_config.duplex = cmd->duplex;
7968         }
7969
7970         if (netif_running(dev))
7971                 tg3_setup_phy(tp, 1);
7972
7973         tg3_full_unlock(tp);
7974
7975         return 0;
7976 }
7977
7978 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7979 {
7980         struct tg3 *tp = netdev_priv(dev);
7981
7982         strcpy(info->driver, DRV_MODULE_NAME);
7983         strcpy(info->version, DRV_MODULE_VERSION);
7984         strcpy(info->fw_version, tp->fw_ver);
7985         strcpy(info->bus_info, pci_name(tp->pdev));
7986 }
7987
7988 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7989 {
7990         struct tg3 *tp = netdev_priv(dev);
7991
7992         wol->supported = WAKE_MAGIC;
7993         wol->wolopts = 0;
7994         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7995                 wol->wolopts = WAKE_MAGIC;
7996         memset(&wol->sopass, 0, sizeof(wol->sopass));
7997 }
7998
7999 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8000 {
8001         struct tg3 *tp = netdev_priv(dev);
8002
8003         if (wol->wolopts & ~WAKE_MAGIC)
8004                 return -EINVAL;
8005         if ((wol->wolopts & WAKE_MAGIC) &&
8006             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8007             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8008                 return -EINVAL;
8009
8010         spin_lock_bh(&tp->lock);
8011         if (wol->wolopts & WAKE_MAGIC)
8012                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8013         else
8014                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8015         spin_unlock_bh(&tp->lock);
8016
8017         return 0;
8018 }
8019
8020 static u32 tg3_get_msglevel(struct net_device *dev)
8021 {
8022         struct tg3 *tp = netdev_priv(dev);
8023         return tp->msg_enable;
8024 }
8025
8026 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8027 {
8028         struct tg3 *tp = netdev_priv(dev);
8029         tp->msg_enable = value;
8030 }
8031
8032 #if TG3_TSO_SUPPORT != 0
8033 static int tg3_set_tso(struct net_device *dev, u32 value)
8034 {
8035         struct tg3 *tp = netdev_priv(dev);
8036
8037         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8038                 if (value)
8039                         return -EINVAL;
8040                 return 0;
8041         }
8042         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8043             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8044                 if (value)
8045                         dev->features |= NETIF_F_TSO6;
8046                 else
8047                         dev->features &= ~NETIF_F_TSO6;
8048         }
8049         return ethtool_op_set_tso(dev, value);
8050 }
8051 #endif
8052
8053 static int tg3_nway_reset(struct net_device *dev)
8054 {
8055         struct tg3 *tp = netdev_priv(dev);
8056         u32 bmcr;
8057         int r;
8058
8059         if (!netif_running(dev))
8060                 return -EAGAIN;
8061
8062         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8063                 return -EINVAL;
8064
8065         spin_lock_bh(&tp->lock);
8066         r = -EINVAL;
8067         tg3_readphy(tp, MII_BMCR, &bmcr);
8068         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8069             ((bmcr & BMCR_ANENABLE) ||
8070              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8071                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8072                                            BMCR_ANENABLE);
8073                 r = 0;
8074         }
8075         spin_unlock_bh(&tp->lock);
8076
8077         return r;
8078 }
8079
8080 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8081 {
8082         struct tg3 *tp = netdev_priv(dev);
8083
8084         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8085         ering->rx_mini_max_pending = 0;
8086         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8087                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8088         else
8089                 ering->rx_jumbo_max_pending = 0;
8090
8091         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8092
8093         ering->rx_pending = tp->rx_pending;
8094         ering->rx_mini_pending = 0;
8095         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8096                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8097         else
8098                 ering->rx_jumbo_pending = 0;
8099
8100         ering->tx_pending = tp->tx_pending;
8101 }
8102
8103 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8104 {
8105         struct tg3 *tp = netdev_priv(dev);
8106         int irq_sync = 0, err = 0;
8107
8108         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8109             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8110             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8111             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8112             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8113              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8114                 return -EINVAL;
8115
8116         if (netif_running(dev)) {
8117                 tg3_netif_stop(tp);
8118                 irq_sync = 1;
8119         }
8120
8121         tg3_full_lock(tp, irq_sync);
8122
8123         tp->rx_pending = ering->rx_pending;
8124
8125         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8126             tp->rx_pending > 63)
8127                 tp->rx_pending = 63;
8128         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8129         tp->tx_pending = ering->tx_pending;
8130
8131         if (netif_running(dev)) {
8132                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8133                 err = tg3_restart_hw(tp, 1);
8134                 if (!err)
8135                         tg3_netif_start(tp);
8136         }
8137
8138         tg3_full_unlock(tp);
8139
8140         return err;
8141 }
8142
8143 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8144 {
8145         struct tg3 *tp = netdev_priv(dev);
8146
8147         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8148         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8149         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8150 }
8151
8152 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8153 {
8154         struct tg3 *tp = netdev_priv(dev);
8155         int irq_sync = 0, err = 0;
8156
8157         if (netif_running(dev)) {
8158                 tg3_netif_stop(tp);
8159                 irq_sync = 1;
8160         }
8161
8162         tg3_full_lock(tp, irq_sync);
8163
8164         if (epause->autoneg)
8165                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8166         else
8167                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8168         if (epause->rx_pause)
8169                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8170         else
8171                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8172         if (epause->tx_pause)
8173                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8174         else
8175                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8176
8177         if (netif_running(dev)) {
8178                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8179                 err = tg3_restart_hw(tp, 1);
8180                 if (!err)
8181                         tg3_netif_start(tp);
8182         }
8183
8184         tg3_full_unlock(tp);
8185
8186         return err;
8187 }
8188
8189 static u32 tg3_get_rx_csum(struct net_device *dev)
8190 {
8191         struct tg3 *tp = netdev_priv(dev);
8192         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8193 }
8194
8195 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8196 {
8197         struct tg3 *tp = netdev_priv(dev);
8198
8199         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8200                 if (data != 0)
8201                         return -EINVAL;
8202                 return 0;
8203         }
8204
8205         spin_lock_bh(&tp->lock);
8206         if (data)
8207                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8208         else
8209                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8210         spin_unlock_bh(&tp->lock);
8211
8212         return 0;
8213 }
8214
8215 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8216 {
8217         struct tg3 *tp = netdev_priv(dev);
8218
8219         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8220                 if (data != 0)
8221                         return -EINVAL;
8222                 return 0;
8223         }
8224
8225         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8226             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8227                 ethtool_op_set_tx_hw_csum(dev, data);
8228         else
8229                 ethtool_op_set_tx_csum(dev, data);
8230
8231         return 0;
8232 }
8233
8234 static int tg3_get_stats_count (struct net_device *dev)
8235 {
8236         return TG3_NUM_STATS;
8237 }
8238
8239 static int tg3_get_test_count (struct net_device *dev)
8240 {
8241         return TG3_NUM_TEST;
8242 }
8243
8244 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8245 {
8246         switch (stringset) {
8247         case ETH_SS_STATS:
8248                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8249                 break;
8250         case ETH_SS_TEST:
8251                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8252                 break;
8253         default:
8254                 WARN_ON(1);     /* we need a WARN() */
8255                 break;
8256         }
8257 }
8258
8259 static int tg3_phys_id(struct net_device *dev, u32 data)
8260 {
8261         struct tg3 *tp = netdev_priv(dev);
8262         int i;
8263
8264         if (!netif_running(tp->dev))
8265                 return -EAGAIN;
8266
8267         if (data == 0)
8268                 data = 2;
8269
8270         for (i = 0; i < (data * 2); i++) {
8271                 if ((i % 2) == 0)
8272                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8273                                            LED_CTRL_1000MBPS_ON |
8274                                            LED_CTRL_100MBPS_ON |
8275                                            LED_CTRL_10MBPS_ON |
8276                                            LED_CTRL_TRAFFIC_OVERRIDE |
8277                                            LED_CTRL_TRAFFIC_BLINK |
8278                                            LED_CTRL_TRAFFIC_LED);
8279
8280                 else
8281                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8282                                            LED_CTRL_TRAFFIC_OVERRIDE);
8283
8284                 if (msleep_interruptible(500))
8285                         break;
8286         }
8287         tw32(MAC_LED_CTRL, tp->led_ctrl);
8288         return 0;
8289 }
8290
8291 static void tg3_get_ethtool_stats (struct net_device *dev,
8292                                    struct ethtool_stats *estats, u64 *tmp_stats)
8293 {
8294         struct tg3 *tp = netdev_priv(dev);
8295         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8296 }
8297
8298 #define NVRAM_TEST_SIZE 0x100
8299 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8300 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8301 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8302
8303 static int tg3_test_nvram(struct tg3 *tp)
8304 {
8305         u32 *buf, csum, magic;
8306         int i, j, err = 0, size;
8307
8308         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8309                 return -EIO;
8310
8311         if (magic == TG3_EEPROM_MAGIC)
8312                 size = NVRAM_TEST_SIZE;
8313         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8314                 if ((magic & 0xe00000) == 0x200000)
8315                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8316                 else
8317                         return 0;
8318         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8319                 size = NVRAM_SELFBOOT_HW_SIZE;
8320         else
8321                 return -EIO;
8322
8323         buf = kmalloc(size, GFP_KERNEL);
8324         if (buf == NULL)
8325                 return -ENOMEM;
8326
8327         err = -EIO;
8328         for (i = 0, j = 0; i < size; i += 4, j++) {
8329                 u32 val;
8330
8331                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8332                         break;
8333                 buf[j] = cpu_to_le32(val);
8334         }
8335         if (i < size)
8336                 goto out;
8337
8338         /* Selfboot format */
8339         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8340             TG3_EEPROM_MAGIC_FW) {
8341                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8342
8343                 for (i = 0; i < size; i++)
8344                         csum8 += buf8[i];
8345
8346                 if (csum8 == 0) {
8347                         err = 0;
8348                         goto out;
8349                 }
8350
8351                 err = -EIO;
8352                 goto out;
8353         }
8354
8355         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8356             TG3_EEPROM_MAGIC_HW) {
8357                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8358                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8359                 u8 *buf8 = (u8 *) buf;
8360                 int j, k;
8361
8362                 /* Separate the parity bits and the data bytes.  */
8363                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8364                         if ((i == 0) || (i == 8)) {
8365                                 int l;
8366                                 u8 msk;
8367
8368                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8369                                         parity[k++] = buf8[i] & msk;
8370                                 i++;
8371                         }
8372                         else if (i == 16) {
8373                                 int l;
8374                                 u8 msk;
8375
8376                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8377                                         parity[k++] = buf8[i] & msk;
8378                                 i++;
8379
8380                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8381                                         parity[k++] = buf8[i] & msk;
8382                                 i++;
8383                         }
8384                         data[j++] = buf8[i];
8385                 }
8386
8387                 err = -EIO;
8388                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8389                         u8 hw8 = hweight8(data[i]);
8390
8391                         if ((hw8 & 0x1) && parity[i])
8392                                 goto out;
8393                         else if (!(hw8 & 0x1) && !parity[i])
8394                                 goto out;
8395                 }
8396                 err = 0;
8397                 goto out;
8398         }
8399
8400         /* Bootstrap checksum at offset 0x10 */
8401         csum = calc_crc((unsigned char *) buf, 0x10);
8402         if(csum != cpu_to_le32(buf[0x10/4]))
8403                 goto out;
8404
8405         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8406         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8407         if (csum != cpu_to_le32(buf[0xfc/4]))
8408                  goto out;
8409
8410         err = 0;
8411
8412 out:
8413         kfree(buf);
8414         return err;
8415 }
8416
8417 #define TG3_SERDES_TIMEOUT_SEC  2
8418 #define TG3_COPPER_TIMEOUT_SEC  6
8419
8420 static int tg3_test_link(struct tg3 *tp)
8421 {
8422         int i, max;
8423
8424         if (!netif_running(tp->dev))
8425                 return -ENODEV;
8426
8427         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8428                 max = TG3_SERDES_TIMEOUT_SEC;
8429         else
8430                 max = TG3_COPPER_TIMEOUT_SEC;
8431
8432         for (i = 0; i < max; i++) {
8433                 if (netif_carrier_ok(tp->dev))
8434                         return 0;
8435
8436                 if (msleep_interruptible(1000))
8437                         break;
8438         }
8439
8440         return -EIO;
8441 }
8442
8443 /* Only test the commonly used registers */
8444 static int tg3_test_registers(struct tg3 *tp)
8445 {
8446         int i, is_5705, is_5750;
8447         u32 offset, read_mask, write_mask, val, save_val, read_val;
8448         static struct {
8449                 u16 offset;
8450                 u16 flags;
8451 #define TG3_FL_5705     0x1
8452 #define TG3_FL_NOT_5705 0x2
8453 #define TG3_FL_NOT_5788 0x4
8454 #define TG3_FL_NOT_5750 0x8
8455                 u32 read_mask;
8456                 u32 write_mask;
8457         } reg_tbl[] = {
8458                 /* MAC Control Registers */
8459                 { MAC_MODE, TG3_FL_NOT_5705,
8460                         0x00000000, 0x00ef6f8c },
8461                 { MAC_MODE, TG3_FL_5705,
8462                         0x00000000, 0x01ef6b8c },
8463                 { MAC_STATUS, TG3_FL_NOT_5705,
8464                         0x03800107, 0x00000000 },
8465                 { MAC_STATUS, TG3_FL_5705,
8466                         0x03800100, 0x00000000 },
8467                 { MAC_ADDR_0_HIGH, 0x0000,
8468                         0x00000000, 0x0000ffff },
8469                 { MAC_ADDR_0_LOW, 0x0000,
8470                         0x00000000, 0xffffffff },
8471                 { MAC_RX_MTU_SIZE, 0x0000,
8472                         0x00000000, 0x0000ffff },
8473                 { MAC_TX_MODE, 0x0000,
8474                         0x00000000, 0x00000070 },
8475                 { MAC_TX_LENGTHS, 0x0000,
8476                         0x00000000, 0x00003fff },
8477                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8478                         0x00000000, 0x000007fc },
8479                 { MAC_RX_MODE, TG3_FL_5705,
8480                         0x00000000, 0x000007dc },
8481                 { MAC_HASH_REG_0, 0x0000,
8482                         0x00000000, 0xffffffff },
8483                 { MAC_HASH_REG_1, 0x0000,
8484                         0x00000000, 0xffffffff },
8485                 { MAC_HASH_REG_2, 0x0000,
8486                         0x00000000, 0xffffffff },
8487                 { MAC_HASH_REG_3, 0x0000,
8488                         0x00000000, 0xffffffff },
8489
8490                 /* Receive Data and Receive BD Initiator Control Registers. */
8491                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8492                         0x00000000, 0xffffffff },
8493                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8494                         0x00000000, 0xffffffff },
8495                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8496                         0x00000000, 0x00000003 },
8497                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8498                         0x00000000, 0xffffffff },
8499                 { RCVDBDI_STD_BD+0, 0x0000,
8500                         0x00000000, 0xffffffff },
8501                 { RCVDBDI_STD_BD+4, 0x0000,
8502                         0x00000000, 0xffffffff },
8503                 { RCVDBDI_STD_BD+8, 0x0000,
8504                         0x00000000, 0xffff0002 },
8505                 { RCVDBDI_STD_BD+0xc, 0x0000,
8506                         0x00000000, 0xffffffff },
8507
8508                 /* Receive BD Initiator Control Registers. */
8509                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8510                         0x00000000, 0xffffffff },
8511                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8512                         0x00000000, 0x000003ff },
8513                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8514                         0x00000000, 0xffffffff },
8515
8516                 /* Host Coalescing Control Registers. */
8517                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8518                         0x00000000, 0x00000004 },
8519                 { HOSTCC_MODE, TG3_FL_5705,
8520                         0x00000000, 0x000000f6 },
8521                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8522                         0x00000000, 0xffffffff },
8523                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8524                         0x00000000, 0x000003ff },
8525                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8526                         0x00000000, 0xffffffff },
8527                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8528                         0x00000000, 0x000003ff },
8529                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8530                         0x00000000, 0xffffffff },
8531                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8532                         0x00000000, 0x000000ff },
8533                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8534                         0x00000000, 0xffffffff },
8535                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8536                         0x00000000, 0x000000ff },
8537                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8538                         0x00000000, 0xffffffff },
8539                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8540                         0x00000000, 0xffffffff },
8541                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8542                         0x00000000, 0xffffffff },
8543                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8544                         0x00000000, 0x000000ff },
8545                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8546                         0x00000000, 0xffffffff },
8547                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8548                         0x00000000, 0x000000ff },
8549                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8550                         0x00000000, 0xffffffff },
8551                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8552                         0x00000000, 0xffffffff },
8553                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8554                         0x00000000, 0xffffffff },
8555                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8556                         0x00000000, 0xffffffff },
8557                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8558                         0x00000000, 0xffffffff },
8559                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8560                         0xffffffff, 0x00000000 },
8561                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8562                         0xffffffff, 0x00000000 },
8563
8564                 /* Buffer Manager Control Registers. */
8565                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8566                         0x00000000, 0x007fff80 },
8567                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8568                         0x00000000, 0x007fffff },
8569                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8570                         0x00000000, 0x0000003f },
8571                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8572                         0x00000000, 0x000001ff },
8573                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8574                         0x00000000, 0x000001ff },
8575                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8576                         0xffffffff, 0x00000000 },
8577                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8578                         0xffffffff, 0x00000000 },
8579
8580                 /* Mailbox Registers */
8581                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8582                         0x00000000, 0x000001ff },
8583                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8584                         0x00000000, 0x000001ff },
8585                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8586                         0x00000000, 0x000007ff },
8587                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8588                         0x00000000, 0x000001ff },
8589
8590                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8591         };
8592
8593         is_5705 = is_5750 = 0;
8594         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8595                 is_5705 = 1;
8596                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8597                         is_5750 = 1;
8598         }
8599
8600         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8601                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8602                         continue;
8603
8604                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8605                         continue;
8606
8607                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8608                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8609                         continue;
8610
8611                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8612                         continue;
8613
8614                 offset = (u32) reg_tbl[i].offset;
8615                 read_mask = reg_tbl[i].read_mask;
8616                 write_mask = reg_tbl[i].write_mask;
8617
8618                 /* Save the original register content */
8619                 save_val = tr32(offset);
8620
8621                 /* Determine the read-only value. */
8622                 read_val = save_val & read_mask;
8623
8624                 /* Write zero to the register, then make sure the read-only bits
8625                  * are not changed and the read/write bits are all zeros.
8626                  */
8627                 tw32(offset, 0);
8628
8629                 val = tr32(offset);
8630
8631                 /* Test the read-only and read/write bits. */
8632                 if (((val & read_mask) != read_val) || (val & write_mask))
8633                         goto out;
8634
8635                 /* Write ones to all the bits defined by RdMask and WrMask, then
8636                  * make sure the read-only bits are not changed and the
8637                  * read/write bits are all ones.
8638                  */
8639                 tw32(offset, read_mask | write_mask);
8640
8641                 val = tr32(offset);
8642
8643                 /* Test the read-only bits. */
8644                 if ((val & read_mask) != read_val)
8645                         goto out;
8646
8647                 /* Test the read/write bits. */
8648                 if ((val & write_mask) != write_mask)
8649                         goto out;
8650
8651                 tw32(offset, save_val);
8652         }
8653
8654         return 0;
8655
8656 out:
8657         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8658         tw32(offset, save_val);
8659         return -EIO;
8660 }
8661
8662 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8663 {
8664         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8665         int i;
8666         u32 j;
8667
8668         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8669                 for (j = 0; j < len; j += 4) {
8670                         u32 val;
8671
8672                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8673                         tg3_read_mem(tp, offset + j, &val);
8674                         if (val != test_pattern[i])
8675                                 return -EIO;
8676                 }
8677         }
8678         return 0;
8679 }
8680
8681 static int tg3_test_memory(struct tg3 *tp)
8682 {
8683         static struct mem_entry {
8684                 u32 offset;
8685                 u32 len;
8686         } mem_tbl_570x[] = {
8687                 { 0x00000000, 0x00b50},
8688                 { 0x00002000, 0x1c000},
8689                 { 0xffffffff, 0x00000}
8690         }, mem_tbl_5705[] = {
8691                 { 0x00000100, 0x0000c},
8692                 { 0x00000200, 0x00008},
8693                 { 0x00004000, 0x00800},
8694                 { 0x00006000, 0x01000},
8695                 { 0x00008000, 0x02000},
8696                 { 0x00010000, 0x0e000},
8697                 { 0xffffffff, 0x00000}
8698         }, mem_tbl_5755[] = {
8699                 { 0x00000200, 0x00008},
8700                 { 0x00004000, 0x00800},
8701                 { 0x00006000, 0x00800},
8702                 { 0x00008000, 0x02000},
8703                 { 0x00010000, 0x0c000},
8704                 { 0xffffffff, 0x00000}
8705         }, mem_tbl_5906[] = {
8706                 { 0x00000200, 0x00008},
8707                 { 0x00004000, 0x00400},
8708                 { 0x00006000, 0x00400},
8709                 { 0x00008000, 0x01000},
8710                 { 0x00010000, 0x01000},
8711                 { 0xffffffff, 0x00000}
8712         };
8713         struct mem_entry *mem_tbl;
8714         int err = 0;
8715         int i;
8716
8717         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8718                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8719                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8720                         mem_tbl = mem_tbl_5755;
8721                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8722                         mem_tbl = mem_tbl_5906;
8723                 else
8724                         mem_tbl = mem_tbl_5705;
8725         } else
8726                 mem_tbl = mem_tbl_570x;
8727
8728         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8729                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8730                     mem_tbl[i].len)) != 0)
8731                         break;
8732         }
8733
8734         return err;
8735 }
8736
8737 #define TG3_MAC_LOOPBACK        0
8738 #define TG3_PHY_LOOPBACK        1
8739
8740 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8741 {
8742         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8743         u32 desc_idx;
8744         struct sk_buff *skb, *rx_skb;
8745         u8 *tx_data;
8746         dma_addr_t map;
8747         int num_pkts, tx_len, rx_len, i, err;
8748         struct tg3_rx_buffer_desc *desc;
8749
8750         if (loopback_mode == TG3_MAC_LOOPBACK) {
8751                 /* HW errata - mac loopback fails in some cases on 5780.
8752                  * Normal traffic and PHY loopback are not affected by
8753                  * errata.
8754                  */
8755                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8756                         return 0;
8757
8758                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8759                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8760                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8761                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8762                 else
8763                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8764                 tw32(MAC_MODE, mac_mode);
8765         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8766                 u32 val;
8767
8768                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8769                         u32 phytest;
8770
8771                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8772                                 u32 phy;
8773
8774                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8775                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8776                                 if (!tg3_readphy(tp, 0x1b, &phy))
8777                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8778                                 if (!tg3_readphy(tp, 0x10, &phy))
8779                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8780                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8781                         }
8782                 }
8783                 val = BMCR_LOOPBACK | BMCR_FULLDPLX;
8784                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8785                         val |= BMCR_SPEED100;
8786                 else
8787                         val |= BMCR_SPEED1000;
8788
8789                 tg3_writephy(tp, MII_BMCR, val);
8790                 udelay(40);
8791                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8792                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8793
8794                 /* reset to prevent losing 1st rx packet intermittently */
8795                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8796                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8797                         udelay(10);
8798                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8799                 }
8800                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8801                            MAC_MODE_LINK_POLARITY;
8802                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8803                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8804                 else
8805                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8806                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8807                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8808                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8809                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8810                 }
8811                 tw32(MAC_MODE, mac_mode);
8812         }
8813         else
8814                 return -EINVAL;
8815
8816         err = -EIO;
8817
8818         tx_len = 1514;
8819         skb = netdev_alloc_skb(tp->dev, tx_len);
8820         if (!skb)
8821                 return -ENOMEM;
8822
8823         tx_data = skb_put(skb, tx_len);
8824         memcpy(tx_data, tp->dev->dev_addr, 6);
8825         memset(tx_data + 6, 0x0, 8);
8826
8827         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8828
8829         for (i = 14; i < tx_len; i++)
8830                 tx_data[i] = (u8) (i & 0xff);
8831
8832         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8833
8834         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8835              HOSTCC_MODE_NOW);
8836
8837         udelay(10);
8838
8839         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8840
8841         num_pkts = 0;
8842
8843         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8844
8845         tp->tx_prod++;
8846         num_pkts++;
8847
8848         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8849                      tp->tx_prod);
8850         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8851
8852         udelay(10);
8853
8854         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8855         for (i = 0; i < 25; i++) {
8856                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8857                        HOSTCC_MODE_NOW);
8858
8859                 udelay(10);
8860
8861                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8862                 rx_idx = tp->hw_status->idx[0].rx_producer;
8863                 if ((tx_idx == tp->tx_prod) &&
8864                     (rx_idx == (rx_start_idx + num_pkts)))
8865                         break;
8866         }
8867
8868         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8869         dev_kfree_skb(skb);
8870
8871         if (tx_idx != tp->tx_prod)
8872                 goto out;
8873
8874         if (rx_idx != rx_start_idx + num_pkts)
8875                 goto out;
8876
8877         desc = &tp->rx_rcb[rx_start_idx];
8878         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8879         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8880         if (opaque_key != RXD_OPAQUE_RING_STD)
8881                 goto out;
8882
8883         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8884             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8885                 goto out;
8886
8887         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8888         if (rx_len != tx_len)
8889                 goto out;
8890
8891         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8892
8893         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8894         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8895
8896         for (i = 14; i < tx_len; i++) {
8897                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8898                         goto out;
8899         }
8900         err = 0;
8901
8902         /* tg3_free_rings will unmap and free the rx_skb */
8903 out:
8904         return err;
8905 }
8906
8907 #define TG3_MAC_LOOPBACK_FAILED         1
8908 #define TG3_PHY_LOOPBACK_FAILED         2
8909 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8910                                          TG3_PHY_LOOPBACK_FAILED)
8911
8912 static int tg3_test_loopback(struct tg3 *tp)
8913 {
8914         int err = 0;
8915
8916         if (!netif_running(tp->dev))
8917                 return TG3_LOOPBACK_FAILED;
8918
8919         err = tg3_reset_hw(tp, 1);
8920         if (err)
8921                 return TG3_LOOPBACK_FAILED;
8922
8923         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8924                 err |= TG3_MAC_LOOPBACK_FAILED;
8925         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8926                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8927                         err |= TG3_PHY_LOOPBACK_FAILED;
8928         }
8929
8930         return err;
8931 }
8932
8933 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8934                           u64 *data)
8935 {
8936         struct tg3 *tp = netdev_priv(dev);
8937
8938         if (tp->link_config.phy_is_low_power)
8939                 tg3_set_power_state(tp, PCI_D0);
8940
8941         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8942
8943         if (tg3_test_nvram(tp) != 0) {
8944                 etest->flags |= ETH_TEST_FL_FAILED;
8945                 data[0] = 1;
8946         }
8947         if (tg3_test_link(tp) != 0) {
8948                 etest->flags |= ETH_TEST_FL_FAILED;
8949                 data[1] = 1;
8950         }
8951         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8952                 int err, irq_sync = 0;
8953
8954                 if (netif_running(dev)) {
8955                         tg3_netif_stop(tp);
8956                         irq_sync = 1;
8957                 }
8958
8959                 tg3_full_lock(tp, irq_sync);
8960
8961                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8962                 err = tg3_nvram_lock(tp);
8963                 tg3_halt_cpu(tp, RX_CPU_BASE);
8964                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8965                         tg3_halt_cpu(tp, TX_CPU_BASE);
8966                 if (!err)
8967                         tg3_nvram_unlock(tp);
8968
8969                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8970                         tg3_phy_reset(tp);
8971
8972                 if (tg3_test_registers(tp) != 0) {
8973                         etest->flags |= ETH_TEST_FL_FAILED;
8974                         data[2] = 1;
8975                 }
8976                 if (tg3_test_memory(tp) != 0) {
8977                         etest->flags |= ETH_TEST_FL_FAILED;
8978                         data[3] = 1;
8979                 }
8980                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8981                         etest->flags |= ETH_TEST_FL_FAILED;
8982
8983                 tg3_full_unlock(tp);
8984
8985                 if (tg3_test_interrupt(tp) != 0) {
8986                         etest->flags |= ETH_TEST_FL_FAILED;
8987                         data[5] = 1;
8988                 }
8989
8990                 tg3_full_lock(tp, 0);
8991
8992                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8993                 if (netif_running(dev)) {
8994                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8995                         if (!tg3_restart_hw(tp, 1))
8996                                 tg3_netif_start(tp);
8997                 }
8998
8999                 tg3_full_unlock(tp);
9000         }
9001         if (tp->link_config.phy_is_low_power)
9002                 tg3_set_power_state(tp, PCI_D3hot);
9003
9004 }
9005
9006 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9007 {
9008         struct mii_ioctl_data *data = if_mii(ifr);
9009         struct tg3 *tp = netdev_priv(dev);
9010         int err;
9011
9012         switch(cmd) {
9013         case SIOCGMIIPHY:
9014                 data->phy_id = PHY_ADDR;
9015
9016                 /* fallthru */
9017         case SIOCGMIIREG: {
9018                 u32 mii_regval;
9019
9020                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9021                         break;                  /* We have no PHY */
9022
9023                 if (tp->link_config.phy_is_low_power)
9024                         return -EAGAIN;
9025
9026                 spin_lock_bh(&tp->lock);
9027                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9028                 spin_unlock_bh(&tp->lock);
9029
9030                 data->val_out = mii_regval;
9031
9032                 return err;
9033         }
9034
9035         case SIOCSMIIREG:
9036                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9037                         break;                  /* We have no PHY */
9038
9039                 if (!capable(CAP_NET_ADMIN))
9040                         return -EPERM;
9041
9042                 if (tp->link_config.phy_is_low_power)
9043                         return -EAGAIN;
9044
9045                 spin_lock_bh(&tp->lock);
9046                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9047                 spin_unlock_bh(&tp->lock);
9048
9049                 return err;
9050
9051         default:
9052                 /* do nothing */
9053                 break;
9054         }
9055         return -EOPNOTSUPP;
9056 }
9057
9058 #if TG3_VLAN_TAG_USED
9059 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9060 {
9061         struct tg3 *tp = netdev_priv(dev);
9062
9063         if (netif_running(dev))
9064                 tg3_netif_stop(tp);
9065
9066         tg3_full_lock(tp, 0);
9067
9068         tp->vlgrp = grp;
9069
9070         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9071         __tg3_set_rx_mode(dev);
9072
9073         tg3_full_unlock(tp);
9074
9075         if (netif_running(dev))
9076                 tg3_netif_start(tp);
9077 }
9078
9079 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9080 {
9081         struct tg3 *tp = netdev_priv(dev);
9082
9083         if (netif_running(dev))
9084                 tg3_netif_stop(tp);
9085
9086         tg3_full_lock(tp, 0);
9087         if (tp->vlgrp)
9088                 tp->vlgrp->vlan_devices[vid] = NULL;
9089         tg3_full_unlock(tp);
9090
9091         if (netif_running(dev))
9092                 tg3_netif_start(tp);
9093 }
9094 #endif
9095
9096 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9097 {
9098         struct tg3 *tp = netdev_priv(dev);
9099
9100         memcpy(ec, &tp->coal, sizeof(*ec));
9101         return 0;
9102 }
9103
9104 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9105 {
9106         struct tg3 *tp = netdev_priv(dev);
9107         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9108         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9109
9110         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9111                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9112                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9113                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9114                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9115         }
9116
9117         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9118             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9119             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9120             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9121             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9122             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9123             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9124             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9125             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9126             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9127                 return -EINVAL;
9128
9129         /* No rx interrupts will be generated if both are zero */
9130         if ((ec->rx_coalesce_usecs == 0) &&
9131             (ec->rx_max_coalesced_frames == 0))
9132                 return -EINVAL;
9133
9134         /* No tx interrupts will be generated if both are zero */
9135         if ((ec->tx_coalesce_usecs == 0) &&
9136             (ec->tx_max_coalesced_frames == 0))
9137                 return -EINVAL;
9138
9139         /* Only copy relevant parameters, ignore all others. */
9140         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9141         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9142         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9143         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9144         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9145         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9146         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9147         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9148         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9149
9150         if (netif_running(dev)) {
9151                 tg3_full_lock(tp, 0);
9152                 __tg3_set_coalesce(tp, &tp->coal);
9153                 tg3_full_unlock(tp);
9154         }
9155         return 0;
9156 }
9157
9158 static const struct ethtool_ops tg3_ethtool_ops = {
9159         .get_settings           = tg3_get_settings,
9160         .set_settings           = tg3_set_settings,
9161         .get_drvinfo            = tg3_get_drvinfo,
9162         .get_regs_len           = tg3_get_regs_len,
9163         .get_regs               = tg3_get_regs,
9164         .get_wol                = tg3_get_wol,
9165         .set_wol                = tg3_set_wol,
9166         .get_msglevel           = tg3_get_msglevel,
9167         .set_msglevel           = tg3_set_msglevel,
9168         .nway_reset             = tg3_nway_reset,
9169         .get_link               = ethtool_op_get_link,
9170         .get_eeprom_len         = tg3_get_eeprom_len,
9171         .get_eeprom             = tg3_get_eeprom,
9172         .set_eeprom             = tg3_set_eeprom,
9173         .get_ringparam          = tg3_get_ringparam,
9174         .set_ringparam          = tg3_set_ringparam,
9175         .get_pauseparam         = tg3_get_pauseparam,
9176         .set_pauseparam         = tg3_set_pauseparam,
9177         .get_rx_csum            = tg3_get_rx_csum,
9178         .set_rx_csum            = tg3_set_rx_csum,
9179         .get_tx_csum            = ethtool_op_get_tx_csum,
9180         .set_tx_csum            = tg3_set_tx_csum,
9181         .get_sg                 = ethtool_op_get_sg,
9182         .set_sg                 = ethtool_op_set_sg,
9183 #if TG3_TSO_SUPPORT != 0
9184         .get_tso                = ethtool_op_get_tso,
9185         .set_tso                = tg3_set_tso,
9186 #endif
9187         .self_test_count        = tg3_get_test_count,
9188         .self_test              = tg3_self_test,
9189         .get_strings            = tg3_get_strings,
9190         .phys_id                = tg3_phys_id,
9191         .get_stats_count        = tg3_get_stats_count,
9192         .get_ethtool_stats      = tg3_get_ethtool_stats,
9193         .get_coalesce           = tg3_get_coalesce,
9194         .set_coalesce           = tg3_set_coalesce,
9195         .get_perm_addr          = ethtool_op_get_perm_addr,
9196 };
9197
9198 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9199 {
9200         u32 cursize, val, magic;
9201
9202         tp->nvram_size = EEPROM_CHIP_SIZE;
9203
9204         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9205                 return;
9206
9207         if ((magic != TG3_EEPROM_MAGIC) &&
9208             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9209             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9210                 return;
9211
9212         /*
9213          * Size the chip by reading offsets at increasing powers of two.
9214          * When we encounter our validation signature, we know the addressing
9215          * has wrapped around, and thus have our chip size.
9216          */
9217         cursize = 0x10;
9218
9219         while (cursize < tp->nvram_size) {
9220                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9221                         return;
9222
9223                 if (val == magic)
9224                         break;
9225
9226                 cursize <<= 1;
9227         }
9228
9229         tp->nvram_size = cursize;
9230 }
9231
9232 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9233 {
9234         u32 val;
9235
9236         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9237                 return;
9238
9239         /* Selfboot format */
9240         if (val != TG3_EEPROM_MAGIC) {
9241                 tg3_get_eeprom_size(tp);
9242                 return;
9243         }
9244
9245         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9246                 if (val != 0) {
9247                         tp->nvram_size = (val >> 16) * 1024;
9248                         return;
9249                 }
9250         }
9251         tp->nvram_size = 0x20000;
9252 }
9253
9254 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9255 {
9256         u32 nvcfg1;
9257
9258         nvcfg1 = tr32(NVRAM_CFG1);
9259         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9260                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9261         }
9262         else {
9263                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9264                 tw32(NVRAM_CFG1, nvcfg1);
9265         }
9266
9267         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9268             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9269                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9270                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9271                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9272                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9273                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9274                                 break;
9275                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9276                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9277                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9278                                 break;
9279                         case FLASH_VENDOR_ATMEL_EEPROM:
9280                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9281                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9282                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9283                                 break;
9284                         case FLASH_VENDOR_ST:
9285                                 tp->nvram_jedecnum = JEDEC_ST;
9286                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9287                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9288                                 break;
9289                         case FLASH_VENDOR_SAIFUN:
9290                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9291                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9292                                 break;
9293                         case FLASH_VENDOR_SST_SMALL:
9294                         case FLASH_VENDOR_SST_LARGE:
9295                                 tp->nvram_jedecnum = JEDEC_SST;
9296                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9297                                 break;
9298                 }
9299         }
9300         else {
9301                 tp->nvram_jedecnum = JEDEC_ATMEL;
9302                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9303                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9304         }
9305 }
9306
9307 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9308 {
9309         u32 nvcfg1;
9310
9311         nvcfg1 = tr32(NVRAM_CFG1);
9312
9313         /* NVRAM protection for TPM */
9314         if (nvcfg1 & (1 << 27))
9315                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9316
9317         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9318                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9319                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9320                         tp->nvram_jedecnum = JEDEC_ATMEL;
9321                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9322                         break;
9323                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9324                         tp->nvram_jedecnum = JEDEC_ATMEL;
9325                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9326                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9327                         break;
9328                 case FLASH_5752VENDOR_ST_M45PE10:
9329                 case FLASH_5752VENDOR_ST_M45PE20:
9330                 case FLASH_5752VENDOR_ST_M45PE40:
9331                         tp->nvram_jedecnum = JEDEC_ST;
9332                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9333                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9334                         break;
9335         }
9336
9337         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9338                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9339                         case FLASH_5752PAGE_SIZE_256:
9340                                 tp->nvram_pagesize = 256;
9341                                 break;
9342                         case FLASH_5752PAGE_SIZE_512:
9343                                 tp->nvram_pagesize = 512;
9344                                 break;
9345                         case FLASH_5752PAGE_SIZE_1K:
9346                                 tp->nvram_pagesize = 1024;
9347                                 break;
9348                         case FLASH_5752PAGE_SIZE_2K:
9349                                 tp->nvram_pagesize = 2048;
9350                                 break;
9351                         case FLASH_5752PAGE_SIZE_4K:
9352                                 tp->nvram_pagesize = 4096;
9353                                 break;
9354                         case FLASH_5752PAGE_SIZE_264:
9355                                 tp->nvram_pagesize = 264;
9356                                 break;
9357                 }
9358         }
9359         else {
9360                 /* For eeprom, set pagesize to maximum eeprom size */
9361                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9362
9363                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9364                 tw32(NVRAM_CFG1, nvcfg1);
9365         }
9366 }
9367
9368 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9369 {
9370         u32 nvcfg1;
9371
9372         nvcfg1 = tr32(NVRAM_CFG1);
9373
9374         /* NVRAM protection for TPM */
9375         if (nvcfg1 & (1 << 27))
9376                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9377
9378         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9379                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9380                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9381                         tp->nvram_jedecnum = JEDEC_ATMEL;
9382                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9383                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9384
9385                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9386                         tw32(NVRAM_CFG1, nvcfg1);
9387                         break;
9388                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9389                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9390                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9391                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9392                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9393                         tp->nvram_jedecnum = JEDEC_ATMEL;
9394                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9395                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9396                         tp->nvram_pagesize = 264;
9397                         break;
9398                 case FLASH_5752VENDOR_ST_M45PE10:
9399                 case FLASH_5752VENDOR_ST_M45PE20:
9400                 case FLASH_5752VENDOR_ST_M45PE40:
9401                         tp->nvram_jedecnum = JEDEC_ST;
9402                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9403                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9404                         tp->nvram_pagesize = 256;
9405                         break;
9406         }
9407 }
9408
9409 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9410 {
9411         u32 nvcfg1;
9412
9413         nvcfg1 = tr32(NVRAM_CFG1);
9414
9415         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9416                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9417                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9418                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9419                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9420                         tp->nvram_jedecnum = JEDEC_ATMEL;
9421                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9422                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9423
9424                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9425                         tw32(NVRAM_CFG1, nvcfg1);
9426                         break;
9427                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9428                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9429                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9430                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9431                         tp->nvram_jedecnum = JEDEC_ATMEL;
9432                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9433                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9434                         tp->nvram_pagesize = 264;
9435                         break;
9436                 case FLASH_5752VENDOR_ST_M45PE10:
9437                 case FLASH_5752VENDOR_ST_M45PE20:
9438                 case FLASH_5752VENDOR_ST_M45PE40:
9439                         tp->nvram_jedecnum = JEDEC_ST;
9440                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9441                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9442                         tp->nvram_pagesize = 256;
9443                         break;
9444         }
9445 }
9446
9447 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9448 {
9449         tp->nvram_jedecnum = JEDEC_ATMEL;
9450         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9451         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9452 }
9453
9454 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9455 static void __devinit tg3_nvram_init(struct tg3 *tp)
9456 {
9457         int j;
9458
9459         tw32_f(GRC_EEPROM_ADDR,
9460              (EEPROM_ADDR_FSM_RESET |
9461               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9462                EEPROM_ADDR_CLKPERD_SHIFT)));
9463
9464         /* XXX schedule_timeout() ... */
9465         for (j = 0; j < 100; j++)
9466                 udelay(10);
9467
9468         /* Enable seeprom accesses. */
9469         tw32_f(GRC_LOCAL_CTRL,
9470              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9471         udelay(100);
9472
9473         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9474             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9475                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9476
9477                 if (tg3_nvram_lock(tp)) {
9478                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9479                                "tg3_nvram_init failed.\n", tp->dev->name);
9480                         return;
9481                 }
9482                 tg3_enable_nvram_access(tp);
9483
9484                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9485                         tg3_get_5752_nvram_info(tp);
9486                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9487                         tg3_get_5755_nvram_info(tp);
9488                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9489                         tg3_get_5787_nvram_info(tp);
9490                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9491                         tg3_get_5906_nvram_info(tp);
9492                 else
9493                         tg3_get_nvram_info(tp);
9494
9495                 tg3_get_nvram_size(tp);
9496
9497                 tg3_disable_nvram_access(tp);
9498                 tg3_nvram_unlock(tp);
9499
9500         } else {
9501                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9502
9503                 tg3_get_eeprom_size(tp);
9504         }
9505 }
9506
9507 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9508                                         u32 offset, u32 *val)
9509 {
9510         u32 tmp;
9511         int i;
9512
9513         if (offset > EEPROM_ADDR_ADDR_MASK ||
9514             (offset % 4) != 0)
9515                 return -EINVAL;
9516
9517         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9518                                         EEPROM_ADDR_DEVID_MASK |
9519                                         EEPROM_ADDR_READ);
9520         tw32(GRC_EEPROM_ADDR,
9521              tmp |
9522              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9523              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9524               EEPROM_ADDR_ADDR_MASK) |
9525              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9526
9527         for (i = 0; i < 10000; i++) {
9528                 tmp = tr32(GRC_EEPROM_ADDR);
9529
9530                 if (tmp & EEPROM_ADDR_COMPLETE)
9531                         break;
9532                 udelay(100);
9533         }
9534         if (!(tmp & EEPROM_ADDR_COMPLETE))
9535                 return -EBUSY;
9536
9537         *val = tr32(GRC_EEPROM_DATA);
9538         return 0;
9539 }
9540
9541 #define NVRAM_CMD_TIMEOUT 10000
9542
9543 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9544 {
9545         int i;
9546
9547         tw32(NVRAM_CMD, nvram_cmd);
9548         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9549                 udelay(10);
9550                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9551                         udelay(10);
9552                         break;
9553                 }
9554         }
9555         if (i == NVRAM_CMD_TIMEOUT) {
9556                 return -EBUSY;
9557         }
9558         return 0;
9559 }
9560
9561 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9562 {
9563         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9564             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9565             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9566             (tp->nvram_jedecnum == JEDEC_ATMEL))
9567
9568                 addr = ((addr / tp->nvram_pagesize) <<
9569                         ATMEL_AT45DB0X1B_PAGE_POS) +
9570                        (addr % tp->nvram_pagesize);
9571
9572         return addr;
9573 }
9574
9575 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9576 {
9577         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9578             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9579             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9580             (tp->nvram_jedecnum == JEDEC_ATMEL))
9581
9582                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9583                         tp->nvram_pagesize) +
9584                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9585
9586         return addr;
9587 }
9588
9589 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9590 {
9591         int ret;
9592
9593         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9594                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9595
9596         offset = tg3_nvram_phys_addr(tp, offset);
9597
9598         if (offset > NVRAM_ADDR_MSK)
9599                 return -EINVAL;
9600
9601         ret = tg3_nvram_lock(tp);
9602         if (ret)
9603                 return ret;
9604
9605         tg3_enable_nvram_access(tp);
9606
9607         tw32(NVRAM_ADDR, offset);
9608         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9609                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9610
9611         if (ret == 0)
9612                 *val = swab32(tr32(NVRAM_RDDATA));
9613
9614         tg3_disable_nvram_access(tp);
9615
9616         tg3_nvram_unlock(tp);
9617
9618         return ret;
9619 }
9620
9621 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9622 {
9623         int err;
9624         u32 tmp;
9625
9626         err = tg3_nvram_read(tp, offset, &tmp);
9627         *val = swab32(tmp);
9628         return err;
9629 }
9630
9631 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9632                                     u32 offset, u32 len, u8 *buf)
9633 {
9634         int i, j, rc = 0;
9635         u32 val;
9636
9637         for (i = 0; i < len; i += 4) {
9638                 u32 addr, data;
9639
9640                 addr = offset + i;
9641
9642                 memcpy(&data, buf + i, 4);
9643
9644                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9645
9646                 val = tr32(GRC_EEPROM_ADDR);
9647                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9648
9649                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9650                         EEPROM_ADDR_READ);
9651                 tw32(GRC_EEPROM_ADDR, val |
9652                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9653                         (addr & EEPROM_ADDR_ADDR_MASK) |
9654                         EEPROM_ADDR_START |
9655                         EEPROM_ADDR_WRITE);
9656
9657                 for (j = 0; j < 10000; j++) {
9658                         val = tr32(GRC_EEPROM_ADDR);
9659
9660                         if (val & EEPROM_ADDR_COMPLETE)
9661                                 break;
9662                         udelay(100);
9663                 }
9664                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9665                         rc = -EBUSY;
9666                         break;
9667                 }
9668         }
9669
9670         return rc;
9671 }
9672
9673 /* offset and length are dword aligned */
9674 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9675                 u8 *buf)
9676 {
9677         int ret = 0;
9678         u32 pagesize = tp->nvram_pagesize;
9679         u32 pagemask = pagesize - 1;
9680         u32 nvram_cmd;
9681         u8 *tmp;
9682
9683         tmp = kmalloc(pagesize, GFP_KERNEL);
9684         if (tmp == NULL)
9685                 return -ENOMEM;
9686
9687         while (len) {
9688                 int j;
9689                 u32 phy_addr, page_off, size;
9690
9691                 phy_addr = offset & ~pagemask;
9692
9693                 for (j = 0; j < pagesize; j += 4) {
9694                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9695                                                 (u32 *) (tmp + j))))
9696                                 break;
9697                 }
9698                 if (ret)
9699                         break;
9700
9701                 page_off = offset & pagemask;
9702                 size = pagesize;
9703                 if (len < size)
9704                         size = len;
9705
9706                 len -= size;
9707
9708                 memcpy(tmp + page_off, buf, size);
9709
9710                 offset = offset + (pagesize - page_off);
9711
9712                 tg3_enable_nvram_access(tp);
9713
9714                 /*
9715                  * Before we can erase the flash page, we need
9716                  * to issue a special "write enable" command.
9717                  */
9718                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9719
9720                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9721                         break;
9722
9723                 /* Erase the target page */
9724                 tw32(NVRAM_ADDR, phy_addr);
9725
9726                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9727                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9728
9729                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9730                         break;
9731
9732                 /* Issue another write enable to start the write. */
9733                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9734
9735                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9736                         break;
9737
9738                 for (j = 0; j < pagesize; j += 4) {
9739                         u32 data;
9740
9741                         data = *((u32 *) (tmp + j));
9742                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9743
9744                         tw32(NVRAM_ADDR, phy_addr + j);
9745
9746                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9747                                 NVRAM_CMD_WR;
9748
9749                         if (j == 0)
9750                                 nvram_cmd |= NVRAM_CMD_FIRST;
9751                         else if (j == (pagesize - 4))
9752                                 nvram_cmd |= NVRAM_CMD_LAST;
9753
9754                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9755                                 break;
9756                 }
9757                 if (ret)
9758                         break;
9759         }
9760
9761         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9762         tg3_nvram_exec_cmd(tp, nvram_cmd);
9763
9764         kfree(tmp);
9765
9766         return ret;
9767 }
9768
9769 /* offset and length are dword aligned */
9770 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9771                 u8 *buf)
9772 {
9773         int i, ret = 0;
9774
9775         for (i = 0; i < len; i += 4, offset += 4) {
9776                 u32 data, page_off, phy_addr, nvram_cmd;
9777
9778                 memcpy(&data, buf + i, 4);
9779                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9780
9781                 page_off = offset % tp->nvram_pagesize;
9782
9783                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9784
9785                 tw32(NVRAM_ADDR, phy_addr);
9786
9787                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9788
9789                 if ((page_off == 0) || (i == 0))
9790                         nvram_cmd |= NVRAM_CMD_FIRST;
9791                 if (page_off == (tp->nvram_pagesize - 4))
9792                         nvram_cmd |= NVRAM_CMD_LAST;
9793
9794                 if (i == (len - 4))
9795                         nvram_cmd |= NVRAM_CMD_LAST;
9796
9797                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9798                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9799                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9800                     (tp->nvram_jedecnum == JEDEC_ST) &&
9801                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9802
9803                         if ((ret = tg3_nvram_exec_cmd(tp,
9804                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9805                                 NVRAM_CMD_DONE)))
9806
9807                                 break;
9808                 }
9809                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9810                         /* We always do complete word writes to eeprom. */
9811                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9812                 }
9813
9814                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9815                         break;
9816         }
9817         return ret;
9818 }
9819
9820 /* offset and length are dword aligned */
9821 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9822 {
9823         int ret;
9824
9825         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9826                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9827                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9828                 udelay(40);
9829         }
9830
9831         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9832                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9833         }
9834         else {
9835                 u32 grc_mode;
9836
9837                 ret = tg3_nvram_lock(tp);
9838                 if (ret)
9839                         return ret;
9840
9841                 tg3_enable_nvram_access(tp);
9842                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9843                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9844                         tw32(NVRAM_WRITE1, 0x406);
9845
9846                 grc_mode = tr32(GRC_MODE);
9847                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9848
9849                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9850                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9851
9852                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9853                                 buf);
9854                 }
9855                 else {
9856                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9857                                 buf);
9858                 }
9859
9860                 grc_mode = tr32(GRC_MODE);
9861                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9862
9863                 tg3_disable_nvram_access(tp);
9864                 tg3_nvram_unlock(tp);
9865         }
9866
9867         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9868                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9869                 udelay(40);
9870         }
9871
9872         return ret;
9873 }
9874
9875 struct subsys_tbl_ent {
9876         u16 subsys_vendor, subsys_devid;
9877         u32 phy_id;
9878 };
9879
9880 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9881         /* Broadcom boards. */
9882         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9883         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9884         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9885         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9886         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9887         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9888         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9889         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9890         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9891         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9892         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9893
9894         /* 3com boards. */
9895         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9896         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9897         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9898         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9899         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9900
9901         /* DELL boards. */
9902         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9903         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9904         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9905         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9906
9907         /* Compaq boards. */
9908         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9909         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9910         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9911         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9912         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9913
9914         /* IBM boards. */
9915         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9916 };
9917
9918 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9919 {
9920         int i;
9921
9922         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9923                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9924                      tp->pdev->subsystem_vendor) &&
9925                     (subsys_id_to_phy_id[i].subsys_devid ==
9926                      tp->pdev->subsystem_device))
9927                         return &subsys_id_to_phy_id[i];
9928         }
9929         return NULL;
9930 }
9931
9932 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9933 {
9934         u32 val;
9935         u16 pmcsr;
9936
9937         /* On some early chips the SRAM cannot be accessed in D3hot state,
9938          * so need make sure we're in D0.
9939          */
9940         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9941         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9942         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9943         msleep(1);
9944
9945         /* Make sure register accesses (indirect or otherwise)
9946          * will function correctly.
9947          */
9948         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9949                                tp->misc_host_ctrl);
9950
9951         /* The memory arbiter has to be enabled in order for SRAM accesses
9952          * to succeed.  Normally on powerup the tg3 chip firmware will make
9953          * sure it is enabled, but other entities such as system netboot
9954          * code might disable it.
9955          */
9956         val = tr32(MEMARB_MODE);
9957         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9958
9959         tp->phy_id = PHY_ID_INVALID;
9960         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9961
9962         /* Assume an onboard device by default.  */
9963         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9964
9965         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9966                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM))
9967                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9968                 return;
9969         }
9970
9971         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9972         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9973                 u32 nic_cfg, led_cfg;
9974                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9975                 int eeprom_phy_serdes = 0;
9976
9977                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9978                 tp->nic_sram_data_cfg = nic_cfg;
9979
9980                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9981                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9982                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9983                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9984                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9985                     (ver > 0) && (ver < 0x100))
9986                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9987
9988                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9989                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9990                         eeprom_phy_serdes = 1;
9991
9992                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9993                 if (nic_phy_id != 0) {
9994                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9995                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9996
9997                         eeprom_phy_id  = (id1 >> 16) << 10;
9998                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
9999                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10000                 } else
10001                         eeprom_phy_id = 0;
10002
10003                 tp->phy_id = eeprom_phy_id;
10004                 if (eeprom_phy_serdes) {
10005                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10006                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10007                         else
10008                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10009                 }
10010
10011                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10012                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10013                                     SHASTA_EXT_LED_MODE_MASK);
10014                 else
10015                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10016
10017                 switch (led_cfg) {
10018                 default:
10019                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10020                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10021                         break;
10022
10023                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10024                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10025                         break;
10026
10027                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10028                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10029
10030                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10031                          * read on some older 5700/5701 bootcode.
10032                          */
10033                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10034                             ASIC_REV_5700 ||
10035                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10036                             ASIC_REV_5701)
10037                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10038
10039                         break;
10040
10041                 case SHASTA_EXT_LED_SHARED:
10042                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10043                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10044                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10045                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10046                                                  LED_CTRL_MODE_PHY_2);
10047                         break;
10048
10049                 case SHASTA_EXT_LED_MAC:
10050                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10051                         break;
10052
10053                 case SHASTA_EXT_LED_COMBO:
10054                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10055                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10056                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10057                                                  LED_CTRL_MODE_PHY_2);
10058                         break;
10059
10060                 };
10061
10062                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10063                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10064                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10065                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10066
10067                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
10068                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10069                 else
10070                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10071
10072                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10073                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10074                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10075                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10076                 }
10077                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10078                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10079
10080                 if (cfg2 & (1 << 17))
10081                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10082
10083                 /* serdes signal pre-emphasis in register 0x590 set by */
10084                 /* bootcode if bit 18 is set */
10085                 if (cfg2 & (1 << 18))
10086                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10087         }
10088 }
10089
10090 static int __devinit tg3_phy_probe(struct tg3 *tp)
10091 {
10092         u32 hw_phy_id_1, hw_phy_id_2;
10093         u32 hw_phy_id, hw_phy_id_masked;
10094         int err;
10095
10096         /* Reading the PHY ID register can conflict with ASF
10097          * firwmare access to the PHY hardware.
10098          */
10099         err = 0;
10100         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10101                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10102         } else {
10103                 /* Now read the physical PHY_ID from the chip and verify
10104                  * that it is sane.  If it doesn't look good, we fall back
10105                  * to either the hard-coded table based PHY_ID and failing
10106                  * that the value found in the eeprom area.
10107                  */
10108                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10109                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10110
10111                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10112                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10113                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10114
10115                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10116         }
10117
10118         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10119                 tp->phy_id = hw_phy_id;
10120                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10121                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10122                 else
10123                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10124         } else {
10125                 if (tp->phy_id != PHY_ID_INVALID) {
10126                         /* Do nothing, phy ID already set up in
10127                          * tg3_get_eeprom_hw_cfg().
10128                          */
10129                 } else {
10130                         struct subsys_tbl_ent *p;
10131
10132                         /* No eeprom signature?  Try the hardcoded
10133                          * subsys device table.
10134                          */
10135                         p = lookup_by_subsys(tp);
10136                         if (!p)
10137                                 return -ENODEV;
10138
10139                         tp->phy_id = p->phy_id;
10140                         if (!tp->phy_id ||
10141                             tp->phy_id == PHY_ID_BCM8002)
10142                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10143                 }
10144         }
10145
10146         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10147             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10148                 u32 bmsr, adv_reg, tg3_ctrl;
10149
10150                 tg3_readphy(tp, MII_BMSR, &bmsr);
10151                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10152                     (bmsr & BMSR_LSTATUS))
10153                         goto skip_phy_reset;
10154
10155                 err = tg3_phy_reset(tp);
10156                 if (err)
10157                         return err;
10158
10159                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10160                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10161                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10162                 tg3_ctrl = 0;
10163                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10164                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10165                                     MII_TG3_CTRL_ADV_1000_FULL);
10166                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10167                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10168                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10169                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10170                 }
10171
10172                 if (!tg3_copper_is_advertising_all(tp)) {
10173                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10174
10175                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10176                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10177
10178                         tg3_writephy(tp, MII_BMCR,
10179                                      BMCR_ANENABLE | BMCR_ANRESTART);
10180                 }
10181                 tg3_phy_set_wirespeed(tp);
10182
10183                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10184                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10185                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10186         }
10187
10188 skip_phy_reset:
10189         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10190                 err = tg3_init_5401phy_dsp(tp);
10191                 if (err)
10192                         return err;
10193         }
10194
10195         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10196                 err = tg3_init_5401phy_dsp(tp);
10197         }
10198
10199         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10200                 tp->link_config.advertising =
10201                         (ADVERTISED_1000baseT_Half |
10202                          ADVERTISED_1000baseT_Full |
10203                          ADVERTISED_Autoneg |
10204                          ADVERTISED_FIBRE);
10205         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10206                 tp->link_config.advertising &=
10207                         ~(ADVERTISED_1000baseT_Half |
10208                           ADVERTISED_1000baseT_Full);
10209
10210         return err;
10211 }
10212
10213 static void __devinit tg3_read_partno(struct tg3 *tp)
10214 {
10215         unsigned char vpd_data[256];
10216         unsigned int i;
10217         u32 magic;
10218
10219         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10220                 goto out_not_found;
10221
10222         if (magic == TG3_EEPROM_MAGIC) {
10223                 for (i = 0; i < 256; i += 4) {
10224                         u32 tmp;
10225
10226                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10227                                 goto out_not_found;
10228
10229                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10230                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10231                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10232                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10233                 }
10234         } else {
10235                 int vpd_cap;
10236
10237                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10238                 for (i = 0; i < 256; i += 4) {
10239                         u32 tmp, j = 0;
10240                         u16 tmp16;
10241
10242                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10243                                               i);
10244                         while (j++ < 100) {
10245                                 pci_read_config_word(tp->pdev, vpd_cap +
10246                                                      PCI_VPD_ADDR, &tmp16);
10247                                 if (tmp16 & 0x8000)
10248                                         break;
10249                                 msleep(1);
10250                         }
10251                         if (!(tmp16 & 0x8000))
10252                                 goto out_not_found;
10253
10254                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10255                                               &tmp);
10256                         tmp = cpu_to_le32(tmp);
10257                         memcpy(&vpd_data[i], &tmp, 4);
10258                 }
10259         }
10260
10261         /* Now parse and find the part number. */
10262         for (i = 0; i < 254; ) {
10263                 unsigned char val = vpd_data[i];
10264                 unsigned int block_end;
10265
10266                 if (val == 0x82 || val == 0x91) {
10267                         i = (i + 3 +
10268                              (vpd_data[i + 1] +
10269                               (vpd_data[i + 2] << 8)));
10270                         continue;
10271                 }
10272
10273                 if (val != 0x90)
10274                         goto out_not_found;
10275
10276                 block_end = (i + 3 +
10277                              (vpd_data[i + 1] +
10278                               (vpd_data[i + 2] << 8)));
10279                 i += 3;
10280
10281                 if (block_end > 256)
10282                         goto out_not_found;
10283
10284                 while (i < (block_end - 2)) {
10285                         if (vpd_data[i + 0] == 'P' &&
10286                             vpd_data[i + 1] == 'N') {
10287                                 int partno_len = vpd_data[i + 2];
10288
10289                                 i += 3;
10290                                 if (partno_len > 24 || (partno_len + i) > 256)
10291                                         goto out_not_found;
10292
10293                                 memcpy(tp->board_part_number,
10294                                        &vpd_data[i], partno_len);
10295
10296                                 /* Success. */
10297                                 return;
10298                         }
10299                         i += 3 + vpd_data[i + 2];
10300                 }
10301
10302                 /* Part number not found. */
10303                 goto out_not_found;
10304         }
10305
10306 out_not_found:
10307         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10308                 strcpy(tp->board_part_number, "BCM95906");
10309         else
10310                 strcpy(tp->board_part_number, "none");
10311 }
10312
10313 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10314 {
10315         u32 val, offset, start;
10316
10317         if (tg3_nvram_read_swab(tp, 0, &val))
10318                 return;
10319
10320         if (val != TG3_EEPROM_MAGIC)
10321                 return;
10322
10323         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10324             tg3_nvram_read_swab(tp, 0x4, &start))
10325                 return;
10326
10327         offset = tg3_nvram_logical_addr(tp, offset);
10328         if (tg3_nvram_read_swab(tp, offset, &val))
10329                 return;
10330
10331         if ((val & 0xfc000000) == 0x0c000000) {
10332                 u32 ver_offset, addr;
10333                 int i;
10334
10335                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10336                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10337                         return;
10338
10339                 if (val != 0)
10340                         return;
10341
10342                 addr = offset + ver_offset - start;
10343                 for (i = 0; i < 16; i += 4) {
10344                         if (tg3_nvram_read(tp, addr + i, &val))
10345                                 return;
10346
10347                         val = cpu_to_le32(val);
10348                         memcpy(tp->fw_ver + i, &val, 4);
10349                 }
10350         }
10351 }
10352
10353 static int __devinit tg3_get_invariants(struct tg3 *tp)
10354 {
10355         static struct pci_device_id write_reorder_chipsets[] = {
10356                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10357                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10358                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10359                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10360                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10361                              PCI_DEVICE_ID_VIA_8385_0) },
10362                 { },
10363         };
10364         u32 misc_ctrl_reg;
10365         u32 cacheline_sz_reg;
10366         u32 pci_state_reg, grc_misc_cfg;
10367         u32 val;
10368         u16 pci_cmd;
10369         int err;
10370
10371         /* Force memory write invalidate off.  If we leave it on,
10372          * then on 5700_BX chips we have to enable a workaround.
10373          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10374          * to match the cacheline size.  The Broadcom driver have this
10375          * workaround but turns MWI off all the times so never uses
10376          * it.  This seems to suggest that the workaround is insufficient.
10377          */
10378         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10379         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10380         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10381
10382         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10383          * has the register indirect write enable bit set before
10384          * we try to access any of the MMIO registers.  It is also
10385          * critical that the PCI-X hw workaround situation is decided
10386          * before that as well.
10387          */
10388         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10389                               &misc_ctrl_reg);
10390
10391         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10392                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10393
10394         /* Wrong chip ID in 5752 A0. This code can be removed later
10395          * as A0 is not in production.
10396          */
10397         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10398                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10399
10400         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10401          * we need to disable memory and use config. cycles
10402          * only to access all registers. The 5702/03 chips
10403          * can mistakenly decode the special cycles from the
10404          * ICH chipsets as memory write cycles, causing corruption
10405          * of register and memory space. Only certain ICH bridges
10406          * will drive special cycles with non-zero data during the
10407          * address phase which can fall within the 5703's address
10408          * range. This is not an ICH bug as the PCI spec allows
10409          * non-zero address during special cycles. However, only
10410          * these ICH bridges are known to drive non-zero addresses
10411          * during special cycles.
10412          *
10413          * Since special cycles do not cross PCI bridges, we only
10414          * enable this workaround if the 5703 is on the secondary
10415          * bus of these ICH bridges.
10416          */
10417         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10418             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10419                 static struct tg3_dev_id {
10420                         u32     vendor;
10421                         u32     device;
10422                         u32     rev;
10423                 } ich_chipsets[] = {
10424                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10425                           PCI_ANY_ID },
10426                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10427                           PCI_ANY_ID },
10428                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10429                           0xa },
10430                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10431                           PCI_ANY_ID },
10432                         { },
10433                 };
10434                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10435                 struct pci_dev *bridge = NULL;
10436
10437                 while (pci_id->vendor != 0) {
10438                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10439                                                 bridge);
10440                         if (!bridge) {
10441                                 pci_id++;
10442                                 continue;
10443                         }
10444                         if (pci_id->rev != PCI_ANY_ID) {
10445                                 u8 rev;
10446
10447                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10448                                                      &rev);
10449                                 if (rev > pci_id->rev)
10450                                         continue;
10451                         }
10452                         if (bridge->subordinate &&
10453                             (bridge->subordinate->number ==
10454                              tp->pdev->bus->number)) {
10455
10456                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10457                                 pci_dev_put(bridge);
10458                                 break;
10459                         }
10460                 }
10461         }
10462
10463         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10464          * DMA addresses > 40-bit. This bridge may have other additional
10465          * 57xx devices behind it in some 4-port NIC designs for example.
10466          * Any tg3 device found behind the bridge will also need the 40-bit
10467          * DMA workaround.
10468          */
10469         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10470             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10471                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10472                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10473                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10474         }
10475         else {
10476                 struct pci_dev *bridge = NULL;
10477
10478                 do {
10479                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10480                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10481                                                 bridge);
10482                         if (bridge && bridge->subordinate &&
10483                             (bridge->subordinate->number <=
10484                              tp->pdev->bus->number) &&
10485                             (bridge->subordinate->subordinate >=
10486                              tp->pdev->bus->number)) {
10487                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10488                                 pci_dev_put(bridge);
10489                                 break;
10490                         }
10491                 } while (bridge);
10492         }
10493
10494         /* Initialize misc host control in PCI block. */
10495         tp->misc_host_ctrl |= (misc_ctrl_reg &
10496                                MISC_HOST_CTRL_CHIPREV);
10497         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10498                                tp->misc_host_ctrl);
10499
10500         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10501                               &cacheline_sz_reg);
10502
10503         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10504         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10505         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10506         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10507
10508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10509             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10510             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10511             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10512             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10513             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10514                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10515
10516         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10517             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10518                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10519
10520         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10521                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10522                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10523                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10524                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10525                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10526                 } else {
10527                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10528                                           TG3_FLG2_HW_TSO_1_BUG;
10529                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10530                                 ASIC_REV_5750 &&
10531                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10532                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10533                 }
10534         }
10535
10536         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10537             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10538             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10539             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10540             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10541             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10542                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10543
10544         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10545                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10546
10547         /* If we have an AMD 762 or VIA K8T800 chipset, write
10548          * reordering to the mailbox registers done by the host
10549          * controller can cause major troubles.  We read back from
10550          * every mailbox register write to force the writes to be
10551          * posted to the chip in order.
10552          */
10553         if (pci_dev_present(write_reorder_chipsets) &&
10554             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10555                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10556
10557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10558             tp->pci_lat_timer < 64) {
10559                 tp->pci_lat_timer = 64;
10560
10561                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10562                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10563                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10564                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10565
10566                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10567                                        cacheline_sz_reg);
10568         }
10569
10570         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10571                               &pci_state_reg);
10572
10573         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10574                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10575
10576                 /* If this is a 5700 BX chipset, and we are in PCI-X
10577                  * mode, enable register write workaround.
10578                  *
10579                  * The workaround is to use indirect register accesses
10580                  * for all chip writes not to mailbox registers.
10581                  */
10582                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10583                         u32 pm_reg;
10584                         u16 pci_cmd;
10585
10586                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10587
10588                         /* The chip can have it's power management PCI config
10589                          * space registers clobbered due to this bug.
10590                          * So explicitly force the chip into D0 here.
10591                          */
10592                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10593                                               &pm_reg);
10594                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10595                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10596                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10597                                                pm_reg);
10598
10599                         /* Also, force SERR#/PERR# in PCI command. */
10600                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10601                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10602                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10603                 }
10604         }
10605
10606         /* 5700 BX chips need to have their TX producer index mailboxes
10607          * written twice to workaround a bug.
10608          */
10609         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10610                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10611
10612         /* Back to back register writes can cause problems on this chip,
10613          * the workaround is to read back all reg writes except those to
10614          * mailbox regs.  See tg3_write_indirect_reg32().
10615          *
10616          * PCI Express 5750_A0 rev chips need this workaround too.
10617          */
10618         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10619             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10620              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10621                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10622
10623         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10624                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10625         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10626                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10627
10628         /* Chip-specific fixup from Broadcom driver */
10629         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10630             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10631                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10632                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10633         }
10634
10635         /* Default fast path register access methods */
10636         tp->read32 = tg3_read32;
10637         tp->write32 = tg3_write32;
10638         tp->read32_mbox = tg3_read32;
10639         tp->write32_mbox = tg3_write32;
10640         tp->write32_tx_mbox = tg3_write32;
10641         tp->write32_rx_mbox = tg3_write32;
10642
10643         /* Various workaround register access methods */
10644         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10645                 tp->write32 = tg3_write_indirect_reg32;
10646         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10647                 tp->write32 = tg3_write_flush_reg32;
10648
10649         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10650             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10651                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10652                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10653                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10654         }
10655
10656         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10657                 tp->read32 = tg3_read_indirect_reg32;
10658                 tp->write32 = tg3_write_indirect_reg32;
10659                 tp->read32_mbox = tg3_read_indirect_mbox;
10660                 tp->write32_mbox = tg3_write_indirect_mbox;
10661                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10662                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10663
10664                 iounmap(tp->regs);
10665                 tp->regs = NULL;
10666
10667                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10668                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10669                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10670         }
10671         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10672                 tp->read32_mbox = tg3_read32_mbox_5906;
10673                 tp->write32_mbox = tg3_write32_mbox_5906;
10674                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10675                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10676         }
10677
10678         if (tp->write32 == tg3_write_indirect_reg32 ||
10679             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10680              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10681               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10682                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10683
10684         /* Get eeprom hw config before calling tg3_set_power_state().
10685          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10686          * determined before calling tg3_set_power_state() so that
10687          * we know whether or not to switch out of Vaux power.
10688          * When the flag is set, it means that GPIO1 is used for eeprom
10689          * write protect and also implies that it is a LOM where GPIOs
10690          * are not used to switch power.
10691          */
10692         tg3_get_eeprom_hw_cfg(tp);
10693
10694         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10695          * GPIO1 driven high will bring 5700's external PHY out of reset.
10696          * It is also used as eeprom write protect on LOMs.
10697          */
10698         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10699         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10700             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10701                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10702                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10703         /* Unused GPIO3 must be driven as output on 5752 because there
10704          * are no pull-up resistors on unused GPIO pins.
10705          */
10706         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10707                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10708
10709         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10710                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10711
10712         /* Force the chip into D0. */
10713         err = tg3_set_power_state(tp, PCI_D0);
10714         if (err) {
10715                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10716                        pci_name(tp->pdev));
10717                 return err;
10718         }
10719
10720         /* 5700 B0 chips do not support checksumming correctly due
10721          * to hardware bugs.
10722          */
10723         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10724                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10725
10726         /* Derive initial jumbo mode from MTU assigned in
10727          * ether_setup() via the alloc_etherdev() call
10728          */
10729         if (tp->dev->mtu > ETH_DATA_LEN &&
10730             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10731                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10732
10733         /* Determine WakeOnLan speed to use. */
10734         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10735             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10736             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10737             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10738                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10739         } else {
10740                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10741         }
10742
10743         /* A few boards don't want Ethernet@WireSpeed phy feature */
10744         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10745             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10746              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10747              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10748             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10749             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10750                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10751
10752         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10753             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10754                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10755         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10756                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10757
10758         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10759                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10760                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10761                         tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10762                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10763                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10764         }
10765
10766         tp->coalesce_mode = 0;
10767         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10768             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10769                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10770
10771         /* Initialize MAC MI mode, polling disabled. */
10772         tw32_f(MAC_MI_MODE, tp->mi_mode);
10773         udelay(80);
10774
10775         /* Initialize data/descriptor byte/word swapping. */
10776         val = tr32(GRC_MODE);
10777         val &= GRC_MODE_HOST_STACKUP;
10778         tw32(GRC_MODE, val | tp->grc_mode);
10779
10780         tg3_switch_clocks(tp);
10781
10782         /* Clear this out for sanity. */
10783         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10784
10785         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10786                               &pci_state_reg);
10787         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10788             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10789                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10790
10791                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10792                     chiprevid == CHIPREV_ID_5701_B0 ||
10793                     chiprevid == CHIPREV_ID_5701_B2 ||
10794                     chiprevid == CHIPREV_ID_5701_B5) {
10795                         void __iomem *sram_base;
10796
10797                         /* Write some dummy words into the SRAM status block
10798                          * area, see if it reads back correctly.  If the return
10799                          * value is bad, force enable the PCIX workaround.
10800                          */
10801                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10802
10803                         writel(0x00000000, sram_base);
10804                         writel(0x00000000, sram_base + 4);
10805                         writel(0xffffffff, sram_base + 4);
10806                         if (readl(sram_base) != 0x00000000)
10807                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10808                 }
10809         }
10810
10811         udelay(50);
10812         tg3_nvram_init(tp);
10813
10814         grc_misc_cfg = tr32(GRC_MISC_CFG);
10815         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10816
10817         /* Broadcom's driver says that CIOBE multisplit has a bug */
10818 #if 0
10819         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10820             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10821                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10822                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10823         }
10824 #endif
10825         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10826             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10827              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10828                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10829
10830         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10831             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10832                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10833         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10834                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10835                                       HOSTCC_MODE_CLRTICK_TXBD);
10836
10837                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10838                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10839                                        tp->misc_host_ctrl);
10840         }
10841
10842         /* these are limited to 10/100 only */
10843         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10844              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10845             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10846              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10847              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10848               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10849               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10850             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10851              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10852               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)) ||
10853             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10854                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10855
10856         err = tg3_phy_probe(tp);
10857         if (err) {
10858                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10859                        pci_name(tp->pdev), err);
10860                 /* ... but do not return immediately ... */
10861         }
10862
10863         tg3_read_partno(tp);
10864         tg3_read_fw_ver(tp);
10865
10866         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10867                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10868         } else {
10869                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10870                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10871                 else
10872                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10873         }
10874
10875         /* 5700 {AX,BX} chips have a broken status block link
10876          * change bit implementation, so we must use the
10877          * status register in those cases.
10878          */
10879         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10880                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10881         else
10882                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10883
10884         /* The led_ctrl is set during tg3_phy_probe, here we might
10885          * have to force the link status polling mechanism based
10886          * upon subsystem IDs.
10887          */
10888         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10889             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10890                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10891                                   TG3_FLAG_USE_LINKCHG_REG);
10892         }
10893
10894         /* For all SERDES we poll the MAC status register. */
10895         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10896                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10897         else
10898                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10899
10900         /* All chips before 5787 can get confused if TX buffers
10901          * straddle the 4GB address boundary in some cases.
10902          */
10903         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10904             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10905             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10906                 tp->dev->hard_start_xmit = tg3_start_xmit;
10907         else
10908                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10909
10910         tp->rx_offset = 2;
10911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10912             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10913                 tp->rx_offset = 0;
10914
10915         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10916
10917         /* Increment the rx prod index on the rx std ring by at most
10918          * 8 for these chips to workaround hw errata.
10919          */
10920         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10921             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10922             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10923                 tp->rx_std_max_post = 8;
10924
10925         /* By default, disable wake-on-lan.  User can change this
10926          * using ETHTOOL_SWOL.
10927          */
10928         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10929
10930         return err;
10931 }
10932
10933 #ifdef CONFIG_SPARC64
10934 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10935 {
10936         struct net_device *dev = tp->dev;
10937         struct pci_dev *pdev = tp->pdev;
10938         struct pcidev_cookie *pcp = pdev->sysdata;
10939
10940         if (pcp != NULL) {
10941                 unsigned char *addr;
10942                 int len;
10943
10944                 addr = of_get_property(pcp->prom_node, "local-mac-address",
10945                                         &len);
10946                 if (addr && len == 6) {
10947                         memcpy(dev->dev_addr, addr, 6);
10948                         memcpy(dev->perm_addr, dev->dev_addr, 6);
10949                         return 0;
10950                 }
10951         }
10952         return -ENODEV;
10953 }
10954
10955 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10956 {
10957         struct net_device *dev = tp->dev;
10958
10959         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10960         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10961         return 0;
10962 }
10963 #endif
10964
10965 static int __devinit tg3_get_device_address(struct tg3 *tp)
10966 {
10967         struct net_device *dev = tp->dev;
10968         u32 hi, lo, mac_offset;
10969         int addr_ok = 0;
10970
10971 #ifdef CONFIG_SPARC64
10972         if (!tg3_get_macaddr_sparc(tp))
10973                 return 0;
10974 #endif
10975
10976         mac_offset = 0x7c;
10977         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10978             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10979                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10980                         mac_offset = 0xcc;
10981                 if (tg3_nvram_lock(tp))
10982                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
10983                 else
10984                         tg3_nvram_unlock(tp);
10985         }
10986         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10987                 mac_offset = 0x10;
10988
10989         /* First try to get it from MAC address mailbox. */
10990         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
10991         if ((hi >> 16) == 0x484b) {
10992                 dev->dev_addr[0] = (hi >>  8) & 0xff;
10993                 dev->dev_addr[1] = (hi >>  0) & 0xff;
10994
10995                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
10996                 dev->dev_addr[2] = (lo >> 24) & 0xff;
10997                 dev->dev_addr[3] = (lo >> 16) & 0xff;
10998                 dev->dev_addr[4] = (lo >>  8) & 0xff;
10999                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11000
11001                 /* Some old bootcode may report a 0 MAC address in SRAM */
11002                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11003         }
11004         if (!addr_ok) {
11005                 /* Next, try NVRAM. */
11006                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11007                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11008                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11009                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11010                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11011                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11012                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11013                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11014                 }
11015                 /* Finally just fetch it out of the MAC control regs. */
11016                 else {
11017                         hi = tr32(MAC_ADDR_0_HIGH);
11018                         lo = tr32(MAC_ADDR_0_LOW);
11019
11020                         dev->dev_addr[5] = lo & 0xff;
11021                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11022                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11023                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11024                         dev->dev_addr[1] = hi & 0xff;
11025                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11026                 }
11027         }
11028
11029         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11030 #ifdef CONFIG_SPARC64
11031                 if (!tg3_get_default_macaddr_sparc(tp))
11032                         return 0;
11033 #endif
11034                 return -EINVAL;
11035         }
11036         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11037         return 0;
11038 }
11039
11040 #define BOUNDARY_SINGLE_CACHELINE       1
11041 #define BOUNDARY_MULTI_CACHELINE        2
11042
11043 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11044 {
11045         int cacheline_size;
11046         u8 byte;
11047         int goal;
11048
11049         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11050         if (byte == 0)
11051                 cacheline_size = 1024;
11052         else
11053                 cacheline_size = (int) byte * 4;
11054
11055         /* On 5703 and later chips, the boundary bits have no
11056          * effect.
11057          */
11058         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11059             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11060             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11061                 goto out;
11062
11063 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11064         goal = BOUNDARY_MULTI_CACHELINE;
11065 #else
11066 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11067         goal = BOUNDARY_SINGLE_CACHELINE;
11068 #else
11069         goal = 0;
11070 #endif
11071 #endif
11072
11073         if (!goal)
11074                 goto out;
11075
11076         /* PCI controllers on most RISC systems tend to disconnect
11077          * when a device tries to burst across a cache-line boundary.
11078          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11079          *
11080          * Unfortunately, for PCI-E there are only limited
11081          * write-side controls for this, and thus for reads
11082          * we will still get the disconnects.  We'll also waste
11083          * these PCI cycles for both read and write for chips
11084          * other than 5700 and 5701 which do not implement the
11085          * boundary bits.
11086          */
11087         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11088             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11089                 switch (cacheline_size) {
11090                 case 16:
11091                 case 32:
11092                 case 64:
11093                 case 128:
11094                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11095                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11096                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11097                         } else {
11098                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11099                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11100                         }
11101                         break;
11102
11103                 case 256:
11104                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11105                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11106                         break;
11107
11108                 default:
11109                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11110                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11111                         break;
11112                 };
11113         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11114                 switch (cacheline_size) {
11115                 case 16:
11116                 case 32:
11117                 case 64:
11118                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11119                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11120                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11121                                 break;
11122                         }
11123                         /* fallthrough */
11124                 case 128:
11125                 default:
11126                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11127                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11128                         break;
11129                 };
11130         } else {
11131                 switch (cacheline_size) {
11132                 case 16:
11133                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11134                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11135                                         DMA_RWCTRL_WRITE_BNDRY_16);
11136                                 break;
11137                         }
11138                         /* fallthrough */
11139                 case 32:
11140                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11141                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11142                                         DMA_RWCTRL_WRITE_BNDRY_32);
11143                                 break;
11144                         }
11145                         /* fallthrough */
11146                 case 64:
11147                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11148                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11149                                         DMA_RWCTRL_WRITE_BNDRY_64);
11150                                 break;
11151                         }
11152                         /* fallthrough */
11153                 case 128:
11154                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11155                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11156                                         DMA_RWCTRL_WRITE_BNDRY_128);
11157                                 break;
11158                         }
11159                         /* fallthrough */
11160                 case 256:
11161                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11162                                 DMA_RWCTRL_WRITE_BNDRY_256);
11163                         break;
11164                 case 512:
11165                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11166                                 DMA_RWCTRL_WRITE_BNDRY_512);
11167                         break;
11168                 case 1024:
11169                 default:
11170                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11171                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11172                         break;
11173                 };
11174         }
11175
11176 out:
11177         return val;
11178 }
11179
11180 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11181 {
11182         struct tg3_internal_buffer_desc test_desc;
11183         u32 sram_dma_descs;
11184         int i, ret;
11185
11186         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11187
11188         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11189         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11190         tw32(RDMAC_STATUS, 0);
11191         tw32(WDMAC_STATUS, 0);
11192
11193         tw32(BUFMGR_MODE, 0);
11194         tw32(FTQ_RESET, 0);
11195
11196         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11197         test_desc.addr_lo = buf_dma & 0xffffffff;
11198         test_desc.nic_mbuf = 0x00002100;
11199         test_desc.len = size;
11200
11201         /*
11202          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11203          * the *second* time the tg3 driver was getting loaded after an
11204          * initial scan.
11205          *
11206          * Broadcom tells me:
11207          *   ...the DMA engine is connected to the GRC block and a DMA
11208          *   reset may affect the GRC block in some unpredictable way...
11209          *   The behavior of resets to individual blocks has not been tested.
11210          *
11211          * Broadcom noted the GRC reset will also reset all sub-components.
11212          */
11213         if (to_device) {
11214                 test_desc.cqid_sqid = (13 << 8) | 2;
11215
11216                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11217                 udelay(40);
11218         } else {
11219                 test_desc.cqid_sqid = (16 << 8) | 7;
11220
11221                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11222                 udelay(40);
11223         }
11224         test_desc.flags = 0x00000005;
11225
11226         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11227                 u32 val;
11228
11229                 val = *(((u32 *)&test_desc) + i);
11230                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11231                                        sram_dma_descs + (i * sizeof(u32)));
11232                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11233         }
11234         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11235
11236         if (to_device) {
11237                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11238         } else {
11239                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11240         }
11241
11242         ret = -ENODEV;
11243         for (i = 0; i < 40; i++) {
11244                 u32 val;
11245
11246                 if (to_device)
11247                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11248                 else
11249                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11250                 if ((val & 0xffff) == sram_dma_descs) {
11251                         ret = 0;
11252                         break;
11253                 }
11254
11255                 udelay(100);
11256         }
11257
11258         return ret;
11259 }
11260
11261 #define TEST_BUFFER_SIZE        0x2000
11262
11263 static int __devinit tg3_test_dma(struct tg3 *tp)
11264 {
11265         dma_addr_t buf_dma;
11266         u32 *buf, saved_dma_rwctrl;
11267         int ret;
11268
11269         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11270         if (!buf) {
11271                 ret = -ENOMEM;
11272                 goto out_nofree;
11273         }
11274
11275         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11276                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11277
11278         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11279
11280         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11281                 /* DMA read watermark not used on PCIE */
11282                 tp->dma_rwctrl |= 0x00180000;
11283         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11284                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11285                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11286                         tp->dma_rwctrl |= 0x003f0000;
11287                 else
11288                         tp->dma_rwctrl |= 0x003f000f;
11289         } else {
11290                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11291                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11292                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11293
11294                         /* If the 5704 is behind the EPB bridge, we can
11295                          * do the less restrictive ONE_DMA workaround for
11296                          * better performance.
11297                          */
11298                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11299                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11300                                 tp->dma_rwctrl |= 0x8000;
11301                         else if (ccval == 0x6 || ccval == 0x7)
11302                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11303
11304                         /* Set bit 23 to enable PCIX hw bug fix */
11305                         tp->dma_rwctrl |= 0x009f0000;
11306                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11307                         /* 5780 always in PCIX mode */
11308                         tp->dma_rwctrl |= 0x00144000;
11309                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11310                         /* 5714 always in PCIX mode */
11311                         tp->dma_rwctrl |= 0x00148000;
11312                 } else {
11313                         tp->dma_rwctrl |= 0x001b000f;
11314                 }
11315         }
11316
11317         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11318             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11319                 tp->dma_rwctrl &= 0xfffffff0;
11320
11321         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11322             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11323                 /* Remove this if it causes problems for some boards. */
11324                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11325
11326                 /* On 5700/5701 chips, we need to set this bit.
11327                  * Otherwise the chip will issue cacheline transactions
11328                  * to streamable DMA memory with not all the byte
11329                  * enables turned on.  This is an error on several
11330                  * RISC PCI controllers, in particular sparc64.
11331                  *
11332                  * On 5703/5704 chips, this bit has been reassigned
11333                  * a different meaning.  In particular, it is used
11334                  * on those chips to enable a PCI-X workaround.
11335                  */
11336                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11337         }
11338
11339         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11340
11341 #if 0
11342         /* Unneeded, already done by tg3_get_invariants.  */
11343         tg3_switch_clocks(tp);
11344 #endif
11345
11346         ret = 0;
11347         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11348             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11349                 goto out;
11350
11351         /* It is best to perform DMA test with maximum write burst size
11352          * to expose the 5700/5701 write DMA bug.
11353          */
11354         saved_dma_rwctrl = tp->dma_rwctrl;
11355         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11356         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11357
11358         while (1) {
11359                 u32 *p = buf, i;
11360
11361                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11362                         p[i] = i;
11363
11364                 /* Send the buffer to the chip. */
11365                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11366                 if (ret) {
11367                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11368                         break;
11369                 }
11370
11371 #if 0
11372                 /* validate data reached card RAM correctly. */
11373                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11374                         u32 val;
11375                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11376                         if (le32_to_cpu(val) != p[i]) {
11377                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11378                                 /* ret = -ENODEV here? */
11379                         }
11380                         p[i] = 0;
11381                 }
11382 #endif
11383                 /* Now read it back. */
11384                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11385                 if (ret) {
11386                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11387
11388                         break;
11389                 }
11390
11391                 /* Verify it. */
11392                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11393                         if (p[i] == i)
11394                                 continue;
11395
11396                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11397                             DMA_RWCTRL_WRITE_BNDRY_16) {
11398                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11399                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11400                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11401                                 break;
11402                         } else {
11403                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11404                                 ret = -ENODEV;
11405                                 goto out;
11406                         }
11407                 }
11408
11409                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11410                         /* Success. */
11411                         ret = 0;
11412                         break;
11413                 }
11414         }
11415         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11416             DMA_RWCTRL_WRITE_BNDRY_16) {
11417                 static struct pci_device_id dma_wait_state_chipsets[] = {
11418                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11419                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11420                         { },
11421                 };
11422
11423                 /* DMA test passed without adjusting DMA boundary,
11424                  * now look for chipsets that are known to expose the
11425                  * DMA bug without failing the test.
11426                  */
11427                 if (pci_dev_present(dma_wait_state_chipsets)) {
11428                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11429                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11430                 }
11431                 else
11432                         /* Safe to use the calculated DMA boundary. */
11433                         tp->dma_rwctrl = saved_dma_rwctrl;
11434
11435                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11436         }
11437
11438 out:
11439         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11440 out_nofree:
11441         return ret;
11442 }
11443
11444 static void __devinit tg3_init_link_config(struct tg3 *tp)
11445 {
11446         tp->link_config.advertising =
11447                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11448                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11449                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11450                  ADVERTISED_Autoneg | ADVERTISED_MII);
11451         tp->link_config.speed = SPEED_INVALID;
11452         tp->link_config.duplex = DUPLEX_INVALID;
11453         tp->link_config.autoneg = AUTONEG_ENABLE;
11454         tp->link_config.active_speed = SPEED_INVALID;
11455         tp->link_config.active_duplex = DUPLEX_INVALID;
11456         tp->link_config.phy_is_low_power = 0;
11457         tp->link_config.orig_speed = SPEED_INVALID;
11458         tp->link_config.orig_duplex = DUPLEX_INVALID;
11459         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11460 }
11461
11462 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11463 {
11464         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11465                 tp->bufmgr_config.mbuf_read_dma_low_water =
11466                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11467                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11468                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11469                 tp->bufmgr_config.mbuf_high_water =
11470                         DEFAULT_MB_HIGH_WATER_5705;
11471                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11472                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11473                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11474                         tp->bufmgr_config.mbuf_high_water =
11475                                 DEFAULT_MB_HIGH_WATER_5906;
11476                 }
11477
11478                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11479                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11480                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11481                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11482                 tp->bufmgr_config.mbuf_high_water_jumbo =
11483                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11484         } else {
11485                 tp->bufmgr_config.mbuf_read_dma_low_water =
11486                         DEFAULT_MB_RDMA_LOW_WATER;
11487                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11488                         DEFAULT_MB_MACRX_LOW_WATER;
11489                 tp->bufmgr_config.mbuf_high_water =
11490                         DEFAULT_MB_HIGH_WATER;
11491
11492                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11493                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11494                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11495                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11496                 tp->bufmgr_config.mbuf_high_water_jumbo =
11497                         DEFAULT_MB_HIGH_WATER_JUMBO;
11498         }
11499
11500         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11501         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11502 }
11503
11504 static char * __devinit tg3_phy_string(struct tg3 *tp)
11505 {
11506         switch (tp->phy_id & PHY_ID_MASK) {
11507         case PHY_ID_BCM5400:    return "5400";
11508         case PHY_ID_BCM5401:    return "5401";
11509         case PHY_ID_BCM5411:    return "5411";
11510         case PHY_ID_BCM5701:    return "5701";
11511         case PHY_ID_BCM5703:    return "5703";
11512         case PHY_ID_BCM5704:    return "5704";
11513         case PHY_ID_BCM5705:    return "5705";
11514         case PHY_ID_BCM5750:    return "5750";
11515         case PHY_ID_BCM5752:    return "5752";
11516         case PHY_ID_BCM5714:    return "5714";
11517         case PHY_ID_BCM5780:    return "5780";
11518         case PHY_ID_BCM5755:    return "5755";
11519         case PHY_ID_BCM5787:    return "5787";
11520         case PHY_ID_BCM5756:    return "5722/5756";
11521         case PHY_ID_BCM5906:    return "5906";
11522         case PHY_ID_BCM8002:    return "8002/serdes";
11523         case 0:                 return "serdes";
11524         default:                return "unknown";
11525         };
11526 }
11527
11528 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11529 {
11530         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11531                 strcpy(str, "PCI Express");
11532                 return str;
11533         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11534                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11535
11536                 strcpy(str, "PCIX:");
11537
11538                 if ((clock_ctrl == 7) ||
11539                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11540                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11541                         strcat(str, "133MHz");
11542                 else if (clock_ctrl == 0)
11543                         strcat(str, "33MHz");
11544                 else if (clock_ctrl == 2)
11545                         strcat(str, "50MHz");
11546                 else if (clock_ctrl == 4)
11547                         strcat(str, "66MHz");
11548                 else if (clock_ctrl == 6)
11549                         strcat(str, "100MHz");
11550         } else {
11551                 strcpy(str, "PCI:");
11552                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11553                         strcat(str, "66MHz");
11554                 else
11555                         strcat(str, "33MHz");
11556         }
11557         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11558                 strcat(str, ":32-bit");
11559         else
11560                 strcat(str, ":64-bit");
11561         return str;
11562 }
11563
11564 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11565 {
11566         struct pci_dev *peer;
11567         unsigned int func, devnr = tp->pdev->devfn & ~7;
11568
11569         for (func = 0; func < 8; func++) {
11570                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11571                 if (peer && peer != tp->pdev)
11572                         break;
11573                 pci_dev_put(peer);
11574         }
11575         /* 5704 can be configured in single-port mode, set peer to
11576          * tp->pdev in that case.
11577          */
11578         if (!peer) {
11579                 peer = tp->pdev;
11580                 return peer;
11581         }
11582
11583         /*
11584          * We don't need to keep the refcount elevated; there's no way
11585          * to remove one half of this device without removing the other
11586          */
11587         pci_dev_put(peer);
11588
11589         return peer;
11590 }
11591
11592 static void __devinit tg3_init_coal(struct tg3 *tp)
11593 {
11594         struct ethtool_coalesce *ec = &tp->coal;
11595
11596         memset(ec, 0, sizeof(*ec));
11597         ec->cmd = ETHTOOL_GCOALESCE;
11598         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11599         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11600         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11601         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11602         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11603         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11604         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11605         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11606         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11607
11608         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11609                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11610                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11611                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11612                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11613                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11614         }
11615
11616         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11617                 ec->rx_coalesce_usecs_irq = 0;
11618                 ec->tx_coalesce_usecs_irq = 0;
11619                 ec->stats_block_coalesce_usecs = 0;
11620         }
11621 }
11622
11623 static int __devinit tg3_init_one(struct pci_dev *pdev,
11624                                   const struct pci_device_id *ent)
11625 {
11626         static int tg3_version_printed = 0;
11627         unsigned long tg3reg_base, tg3reg_len;
11628         struct net_device *dev;
11629         struct tg3 *tp;
11630         int i, err, pm_cap;
11631         char str[40];
11632         u64 dma_mask, persist_dma_mask;
11633
11634         if (tg3_version_printed++ == 0)
11635                 printk(KERN_INFO "%s", version);
11636
11637         err = pci_enable_device(pdev);
11638         if (err) {
11639                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11640                        "aborting.\n");
11641                 return err;
11642         }
11643
11644         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11645                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11646                        "base address, aborting.\n");
11647                 err = -ENODEV;
11648                 goto err_out_disable_pdev;
11649         }
11650
11651         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11652         if (err) {
11653                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11654                        "aborting.\n");
11655                 goto err_out_disable_pdev;
11656         }
11657
11658         pci_set_master(pdev);
11659
11660         /* Find power-management capability. */
11661         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11662         if (pm_cap == 0) {
11663                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11664                        "aborting.\n");
11665                 err = -EIO;
11666                 goto err_out_free_res;
11667         }
11668
11669         tg3reg_base = pci_resource_start(pdev, 0);
11670         tg3reg_len = pci_resource_len(pdev, 0);
11671
11672         dev = alloc_etherdev(sizeof(*tp));
11673         if (!dev) {
11674                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11675                 err = -ENOMEM;
11676                 goto err_out_free_res;
11677         }
11678
11679         SET_MODULE_OWNER(dev);
11680         SET_NETDEV_DEV(dev, &pdev->dev);
11681
11682 #if TG3_VLAN_TAG_USED
11683         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11684         dev->vlan_rx_register = tg3_vlan_rx_register;
11685         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11686 #endif
11687
11688         tp = netdev_priv(dev);
11689         tp->pdev = pdev;
11690         tp->dev = dev;
11691         tp->pm_cap = pm_cap;
11692         tp->mac_mode = TG3_DEF_MAC_MODE;
11693         tp->rx_mode = TG3_DEF_RX_MODE;
11694         tp->tx_mode = TG3_DEF_TX_MODE;
11695         tp->mi_mode = MAC_MI_MODE_BASE;
11696         if (tg3_debug > 0)
11697                 tp->msg_enable = tg3_debug;
11698         else
11699                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11700
11701         /* The word/byte swap controls here control register access byte
11702          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11703          * setting below.
11704          */
11705         tp->misc_host_ctrl =
11706                 MISC_HOST_CTRL_MASK_PCI_INT |
11707                 MISC_HOST_CTRL_WORD_SWAP |
11708                 MISC_HOST_CTRL_INDIR_ACCESS |
11709                 MISC_HOST_CTRL_PCISTATE_RW;
11710
11711         /* The NONFRM (non-frame) byte/word swap controls take effect
11712          * on descriptor entries, anything which isn't packet data.
11713          *
11714          * The StrongARM chips on the board (one for tx, one for rx)
11715          * are running in big-endian mode.
11716          */
11717         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11718                         GRC_MODE_WSWAP_NONFRM_DATA);
11719 #ifdef __BIG_ENDIAN
11720         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11721 #endif
11722         spin_lock_init(&tp->lock);
11723         spin_lock_init(&tp->indirect_lock);
11724         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11725
11726         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11727         if (tp->regs == 0UL) {
11728                 printk(KERN_ERR PFX "Cannot map device registers, "
11729                        "aborting.\n");
11730                 err = -ENOMEM;
11731                 goto err_out_free_dev;
11732         }
11733
11734         tg3_init_link_config(tp);
11735
11736         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11737         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11738         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11739
11740         dev->open = tg3_open;
11741         dev->stop = tg3_close;
11742         dev->get_stats = tg3_get_stats;
11743         dev->set_multicast_list = tg3_set_rx_mode;
11744         dev->set_mac_address = tg3_set_mac_addr;
11745         dev->do_ioctl = tg3_ioctl;
11746         dev->tx_timeout = tg3_tx_timeout;
11747         dev->poll = tg3_poll;
11748         dev->ethtool_ops = &tg3_ethtool_ops;
11749         dev->weight = 64;
11750         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11751         dev->change_mtu = tg3_change_mtu;
11752         dev->irq = pdev->irq;
11753 #ifdef CONFIG_NET_POLL_CONTROLLER
11754         dev->poll_controller = tg3_poll_controller;
11755 #endif
11756
11757         err = tg3_get_invariants(tp);
11758         if (err) {
11759                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11760                        "aborting.\n");
11761                 goto err_out_iounmap;
11762         }
11763
11764         /* The EPB bridge inside 5714, 5715, and 5780 and any
11765          * device behind the EPB cannot support DMA addresses > 40-bit.
11766          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11767          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11768          * do DMA address check in tg3_start_xmit().
11769          */
11770         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11771                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11772         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11773                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11774 #ifdef CONFIG_HIGHMEM
11775                 dma_mask = DMA_64BIT_MASK;
11776 #endif
11777         } else
11778                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11779
11780         /* Configure DMA attributes. */
11781         if (dma_mask > DMA_32BIT_MASK) {
11782                 err = pci_set_dma_mask(pdev, dma_mask);
11783                 if (!err) {
11784                         dev->features |= NETIF_F_HIGHDMA;
11785                         err = pci_set_consistent_dma_mask(pdev,
11786                                                           persist_dma_mask);
11787                         if (err < 0) {
11788                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11789                                        "DMA for consistent allocations\n");
11790                                 goto err_out_iounmap;
11791                         }
11792                 }
11793         }
11794         if (err || dma_mask == DMA_32BIT_MASK) {
11795                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11796                 if (err) {
11797                         printk(KERN_ERR PFX "No usable DMA configuration, "
11798                                "aborting.\n");
11799                         goto err_out_iounmap;
11800                 }
11801         }
11802
11803         tg3_init_bufmgr_config(tp);
11804
11805 #if TG3_TSO_SUPPORT != 0
11806         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11807                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11808         }
11809         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11810             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11811             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11812             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11813                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11814         } else {
11815                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11816         }
11817
11818         /* TSO is on by default on chips that support hardware TSO.
11819          * Firmware TSO on older chips gives lower performance, so it
11820          * is off by default, but can be enabled using ethtool.
11821          */
11822         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11823                 dev->features |= NETIF_F_TSO;
11824                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11825                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11826                         dev->features |= NETIF_F_TSO6;
11827         }
11828
11829 #endif
11830
11831         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11832             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11833             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11834                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11835                 tp->rx_pending = 63;
11836         }
11837
11838         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11839             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11840                 tp->pdev_peer = tg3_find_peer(tp);
11841
11842         err = tg3_get_device_address(tp);
11843         if (err) {
11844                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11845                        "aborting.\n");
11846                 goto err_out_iounmap;
11847         }
11848
11849         /*
11850          * Reset chip in case UNDI or EFI driver did not shutdown
11851          * DMA self test will enable WDMAC and we'll see (spurious)
11852          * pending DMA on the PCI bus at that point.
11853          */
11854         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11855             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11856                 pci_save_state(tp->pdev);
11857                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11858                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11859         }
11860
11861         err = tg3_test_dma(tp);
11862         if (err) {
11863                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11864                 goto err_out_iounmap;
11865         }
11866
11867         /* Tigon3 can do ipv4 only... and some chips have buggy
11868          * checksumming.
11869          */
11870         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11871                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11872                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11873                         dev->features |= NETIF_F_HW_CSUM;
11874                 else
11875                         dev->features |= NETIF_F_IP_CSUM;
11876                 dev->features |= NETIF_F_SG;
11877                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11878         } else
11879                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11880
11881         /* flow control autonegotiation is default behavior */
11882         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11883
11884         tg3_init_coal(tp);
11885
11886         /* Now that we have fully setup the chip, save away a snapshot
11887          * of the PCI config space.  We need to restore this after
11888          * GRC_MISC_CFG core clock resets and some resume events.
11889          */
11890         pci_save_state(tp->pdev);
11891
11892         err = register_netdev(dev);
11893         if (err) {
11894                 printk(KERN_ERR PFX "Cannot register net device, "
11895                        "aborting.\n");
11896                 goto err_out_iounmap;
11897         }
11898
11899         pci_set_drvdata(pdev, dev);
11900
11901         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11902                dev->name,
11903                tp->board_part_number,
11904                tp->pci_chip_rev_id,
11905                tg3_phy_string(tp),
11906                tg3_bus_string(tp, str),
11907                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11908
11909         for (i = 0; i < 6; i++)
11910                 printk("%2.2x%c", dev->dev_addr[i],
11911                        i == 5 ? '\n' : ':');
11912
11913         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11914                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11915                "TSOcap[%d] \n",
11916                dev->name,
11917                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11918                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11919                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11920                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11921                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11922                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11923                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11924         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11925                dev->name, tp->dma_rwctrl,
11926                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11927                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11928
11929         netif_carrier_off(tp->dev);
11930
11931         return 0;
11932
11933 err_out_iounmap:
11934         if (tp->regs) {
11935                 iounmap(tp->regs);
11936                 tp->regs = NULL;
11937         }
11938
11939 err_out_free_dev:
11940         free_netdev(dev);
11941
11942 err_out_free_res:
11943         pci_release_regions(pdev);
11944
11945 err_out_disable_pdev:
11946         pci_disable_device(pdev);
11947         pci_set_drvdata(pdev, NULL);
11948         return err;
11949 }
11950
11951 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11952 {
11953         struct net_device *dev = pci_get_drvdata(pdev);
11954
11955         if (dev) {
11956                 struct tg3 *tp = netdev_priv(dev);
11957
11958                 flush_scheduled_work();
11959                 unregister_netdev(dev);
11960                 if (tp->regs) {
11961                         iounmap(tp->regs);
11962                         tp->regs = NULL;
11963                 }
11964                 free_netdev(dev);
11965                 pci_release_regions(pdev);
11966                 pci_disable_device(pdev);
11967                 pci_set_drvdata(pdev, NULL);
11968         }
11969 }
11970
11971 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11972 {
11973         struct net_device *dev = pci_get_drvdata(pdev);
11974         struct tg3 *tp = netdev_priv(dev);
11975         int err;
11976
11977         if (!netif_running(dev))
11978                 return 0;
11979
11980         flush_scheduled_work();
11981         tg3_netif_stop(tp);
11982
11983         del_timer_sync(&tp->timer);
11984
11985         tg3_full_lock(tp, 1);
11986         tg3_disable_ints(tp);
11987         tg3_full_unlock(tp);
11988
11989         netif_device_detach(dev);
11990
11991         tg3_full_lock(tp, 0);
11992         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11993         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
11994         tg3_full_unlock(tp);
11995
11996         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
11997         if (err) {
11998                 tg3_full_lock(tp, 0);
11999
12000                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12001                 if (tg3_restart_hw(tp, 1))
12002                         goto out;
12003
12004                 tp->timer.expires = jiffies + tp->timer_offset;
12005                 add_timer(&tp->timer);
12006
12007                 netif_device_attach(dev);
12008                 tg3_netif_start(tp);
12009
12010 out:
12011                 tg3_full_unlock(tp);
12012         }
12013
12014         return err;
12015 }
12016
12017 static int tg3_resume(struct pci_dev *pdev)
12018 {
12019         struct net_device *dev = pci_get_drvdata(pdev);
12020         struct tg3 *tp = netdev_priv(dev);
12021         int err;
12022
12023         if (!netif_running(dev))
12024                 return 0;
12025
12026         pci_restore_state(tp->pdev);
12027
12028         err = tg3_set_power_state(tp, PCI_D0);
12029         if (err)
12030                 return err;
12031
12032         netif_device_attach(dev);
12033
12034         tg3_full_lock(tp, 0);
12035
12036         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12037         err = tg3_restart_hw(tp, 1);
12038         if (err)
12039                 goto out;
12040
12041         tp->timer.expires = jiffies + tp->timer_offset;
12042         add_timer(&tp->timer);
12043
12044         tg3_netif_start(tp);
12045
12046 out:
12047         tg3_full_unlock(tp);
12048
12049         return err;
12050 }
12051
12052 static struct pci_driver tg3_driver = {
12053         .name           = DRV_MODULE_NAME,
12054         .id_table       = tg3_pci_tbl,
12055         .probe          = tg3_init_one,
12056         .remove         = __devexit_p(tg3_remove_one),
12057         .suspend        = tg3_suspend,
12058         .resume         = tg3_resume
12059 };
12060
12061 static int __init tg3_init(void)
12062 {
12063         return pci_register_driver(&tg3_driver);
12064 }
12065
12066 static void __exit tg3_cleanup(void)
12067 {
12068         pci_unregister_driver(&tg3_driver);
12069 }
12070
12071 module_init(tg3_init);
12072 module_exit(tg3_cleanup);