drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.102"
  72 #define DRV_MODULE_RELDATE      "September 1, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         spin_lock_bh(&tp->lock);
 906
 907         if (tg3_readphy(tp, reg, &val))
 908                 val = -EIO;
 909
 910         spin_unlock_bh(&tp->lock);
 911
 912         return val;
 913 }
 914
 915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 ret = 0;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_writephy(tp, reg, val))
 923                 ret = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return ret;
 928 }
 929
 930 static int tg3_mdio_reset(struct mii_bus *bp)
 931 {
 932         return 0;
 933 }
 934
 935 static void tg3_mdio_config_5785(struct tg3 *tp)
 936 {
 937         u32 val;
 938         struct phy_device *phydev;
 939
 940         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 942         case TG3_PHY_ID_BCM50610:
 943                 val = MAC_PHYCFG2_50610_LED_MODES;
 944                 break;
 945         case TG3_PHY_ID_BCMAC131:
 946                 val = MAC_PHYCFG2_AC131_LED_MODES;
 947                 break;
 948         case TG3_PHY_ID_RTL8211C:
 949                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 950                 break;
 951         case TG3_PHY_ID_RTL8201E:
 952                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 953                 break;
 954         default:
 955                 return;
 956         }
 957
 958         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 959                 tw32(MAC_PHYCFG2, val);
 960
 961                 val = tr32(MAC_PHYCFG1);
 962                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 963                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 964                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 965                 tw32(MAC_PHYCFG1, val);
 966
 967                 return;
 968         }
 969
 970         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 971                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 972                        MAC_PHYCFG2_FMODE_MASK_MASK |
 973                        MAC_PHYCFG2_GMODE_MASK_MASK |
 974                        MAC_PHYCFG2_ACT_MASK_MASK   |
 975                        MAC_PHYCFG2_QUAL_MASK_MASK |
 976                        MAC_PHYCFG2_INBAND_ENABLE;
 977
 978         tw32(MAC_PHYCFG2, val);
 979
 980         val = tr32(MAC_PHYCFG1);
 981         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 982                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 983         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 984                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 985                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 986                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 987                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 988         }
 989         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 990                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 991         tw32(MAC_PHYCFG1, val);
 992
 993         val = tr32(MAC_EXT_RGMII_MODE);
 994         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 995                  MAC_RGMII_MODE_RX_QUALITY |
 996                  MAC_RGMII_MODE_RX_ACTIVITY |
 997                  MAC_RGMII_MODE_RX_ENG_DET |
 998                  MAC_RGMII_MODE_TX_ENABLE |
 999                  MAC_RGMII_MODE_TX_LOWPWR |
1000                  MAC_RGMII_MODE_TX_RESET);
1001         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1002                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1003                         val |= MAC_RGMII_MODE_RX_INT_B |
1004                                MAC_RGMII_MODE_RX_QUALITY |
1005                                MAC_RGMII_MODE_RX_ACTIVITY |
1006                                MAC_RGMII_MODE_RX_ENG_DET;
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1008                         val |= MAC_RGMII_MODE_TX_ENABLE |
1009                                MAC_RGMII_MODE_TX_LOWPWR |
1010                                MAC_RGMII_MODE_TX_RESET;
1011         }
1012         tw32(MAC_EXT_RGMII_MODE, val);
1013 }
1014
1015 static void tg3_mdio_start(struct tg3 *tp)
1016 {
1017         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1018         tw32_f(MAC_MI_MODE, tp->mi_mode);
1019         udelay(80);
1020
1021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1022                 u32 funcnum, is_serdes;
1023
1024                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1025                 if (funcnum)
1026                         tp->phy_addr = 2;
1027                 else
1028                         tp->phy_addr = 1;
1029
1030                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1031                 if (is_serdes)
1032                         tp->phy_addr += 7;
1033         } else
1034                 tp->phy_addr = TG3_PHY_MII_ADDR;
1035
1036         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038                 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043         int i;
1044         u32 reg;
1045         struct phy_device *phydev;
1046
1047         tg3_mdio_start(tp);
1048
1049         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1050             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1051                 return 0;
1052
1053         tp->mdio_bus = mdiobus_alloc();
1054         if (tp->mdio_bus == NULL)
1055                 return -ENOMEM;
1056
1057         tp->mdio_bus->name     = "tg3 mdio bus";
1058         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1059                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1060         tp->mdio_bus->priv     = tp;
1061         tp->mdio_bus->parent   = &tp->pdev->dev;
1062         tp->mdio_bus->read     = &tg3_mdio_read;
1063         tp->mdio_bus->write    = &tg3_mdio_write;
1064         tp->mdio_bus->reset    = &tg3_mdio_reset;
1065         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1066         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1067
1068         for (i = 0; i < PHY_MAX_ADDR; i++)
1069                 tp->mdio_bus->irq[i] = PHY_POLL;
1070
1071         /* The bus registration will look for all the PHYs on the mdio bus.
1072          * Unfortunately, it does not ensure the PHY is powered up before
1073          * accessing the PHY ID registers.  A chip reset is the
1074          * quickest way to bring the device back to an operational state..
1075          */
1076         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1077                 tg3_bmcr_reset(tp);
1078
1079         i = mdiobus_register(tp->mdio_bus);
1080         if (i) {
1081                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1082                         tp->dev->name, i);
1083                 mdiobus_free(tp->mdio_bus);
1084                 return i;
1085         }
1086
1087         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1088
1089         if (!phydev || !phydev->drv) {
1090                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1091                 mdiobus_unregister(tp->mdio_bus);
1092                 mdiobus_free(tp->mdio_bus);
1093                 return -ENODEV;
1094         }
1095
1096         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1097         case TG3_PHY_ID_BCM57780:
1098                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1099                 break;
1100         case TG3_PHY_ID_BCM50610:
1101                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1102                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1103                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1104                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1105                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1106                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1107                 /* fallthru */
1108         case TG3_PHY_ID_RTL8211C:
1109                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1110                 break;
1111         case TG3_PHY_ID_RTL8201E:
1112         case TG3_PHY_ID_BCMAC131:
1113                 phydev->interface = PHY_INTERFACE_MODE_MII;
1114                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1115                 break;
1116         }
1117
1118         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1119
1120         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1121                 tg3_mdio_config_5785(tp);
1122
1123         return 0;
1124 }
1125
1126 static void tg3_mdio_fini(struct tg3 *tp)
1127 {
1128         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1129                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1130                 mdiobus_unregister(tp->mdio_bus);
1131                 mdiobus_free(tp->mdio_bus);
1132         }
1133 }
1134
1135 /* tp->lock is held. */
1136 static inline void tg3_generate_fw_event(struct tg3 *tp)
1137 {
1138         u32 val;
1139
1140         val = tr32(GRC_RX_CPU_EVENT);
1141         val |= GRC_RX_CPU_DRIVER_EVENT;
1142         tw32_f(GRC_RX_CPU_EVENT, val);
1143
1144         tp->last_event_jiffies = jiffies;
1145 }
1146
1147 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1148
1149 /* tp->lock is held. */
1150 static void tg3_wait_for_event_ack(struct tg3 *tp)
1151 {
1152         int i;
1153         unsigned int delay_cnt;
1154         long time_remain;
1155
1156         /* If enough time has passed, no wait is necessary. */
1157         time_remain = (long)(tp->last_event_jiffies + 1 +
1158                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1159                       (long)jiffies;
1160         if (time_remain < 0)
1161                 return;
1162
1163         /* Check if we can shorten the wait time. */
1164         delay_cnt = jiffies_to_usecs(time_remain);
1165         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1166                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1167         delay_cnt = (delay_cnt >> 3) + 1;
1168
1169         for (i = 0; i < delay_cnt; i++) {
1170                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1171                         break;
1172                 udelay(8);
1173         }
1174 }
1175
1176 /* tp->lock is held. */
1177 static void tg3_ump_link_report(struct tg3 *tp)
1178 {
1179         u32 reg;
1180         u32 val;
1181
1182         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1183             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1184                 return;
1185
1186         tg3_wait_for_event_ack(tp);
1187
1188         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1189
1190         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1191
1192         val = 0;
1193         if (!tg3_readphy(tp, MII_BMCR, &reg))
1194                 val = reg << 16;
1195         if (!tg3_readphy(tp, MII_BMSR, &reg))
1196                 val |= (reg & 0xffff);
1197         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1198
1199         val = 0;
1200         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1201                 val = reg << 16;
1202         if (!tg3_readphy(tp, MII_LPA, &reg))
1203                 val |= (reg & 0xffff);
1204         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1205
1206         val = 0;
1207         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1208                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1209                         val = reg << 16;
1210                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1211                         val |= (reg & 0xffff);
1212         }
1213         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1214
1215         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1216                 val = reg << 16;
1217         else
1218                 val = 0;
1219         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1220
1221         tg3_generate_fw_event(tp);
1222 }
1223
1224 static void tg3_link_report(struct tg3 *tp)
1225 {
1226         if (!netif_carrier_ok(tp->dev)) {
1227                 if (netif_msg_link(tp))
1228                         printk(KERN_INFO PFX "%s: Link is down.\n",
1229                                tp->dev->name);
1230                 tg3_ump_link_report(tp);
1231         } else if (netif_msg_link(tp)) {
1232                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1233                        tp->dev->name,
1234                        (tp->link_config.active_speed == SPEED_1000 ?
1235                         1000 :
1236                         (tp->link_config.active_speed == SPEED_100 ?
1237                          100 : 10)),
1238                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1239                         "full" : "half"));
1240
1241                 printk(KERN_INFO PFX
1242                        "%s: Flow control is %s for TX and %s for RX.\n",
1243                        tp->dev->name,
1244                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1245                        "on" : "off",
1246                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1247                        "on" : "off");
1248                 tg3_ump_link_report(tp);
1249         }
1250 }
1251
1252 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1253 {
1254         u16 miireg;
1255
1256         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1257                 miireg = ADVERTISE_PAUSE_CAP;
1258         else if (flow_ctrl & FLOW_CTRL_TX)
1259                 miireg = ADVERTISE_PAUSE_ASYM;
1260         else if (flow_ctrl & FLOW_CTRL_RX)
1261                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1262         else
1263                 miireg = 0;
1264
1265         return miireg;
1266 }
1267
1268 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1269 {
1270         u16 miireg;
1271
1272         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1273                 miireg = ADVERTISE_1000XPAUSE;
1274         else if (flow_ctrl & FLOW_CTRL_TX)
1275                 miireg = ADVERTISE_1000XPSE_ASYM;
1276         else if (flow_ctrl & FLOW_CTRL_RX)
1277                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1278         else
1279                 miireg = 0;
1280
1281         return miireg;
1282 }
1283
1284 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1285 {
1286         u8 cap = 0;
1287
1288         if (lcladv & ADVERTISE_1000XPAUSE) {
1289                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1290                         if (rmtadv & LPA_1000XPAUSE)
1291                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1292                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1293                                 cap = FLOW_CTRL_RX;
1294                 } else {
1295                         if (rmtadv & LPA_1000XPAUSE)
1296                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1297                 }
1298         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1299                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1300                         cap = FLOW_CTRL_TX;
1301         }
1302
1303         return cap;
1304 }
1305
1306 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1307 {
1308         u8 autoneg;
1309         u8 flowctrl = 0;
1310         u32 old_rx_mode = tp->rx_mode;
1311         u32 old_tx_mode = tp->tx_mode;
1312
1313         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1314                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1315         else
1316                 autoneg = tp->link_config.autoneg;
1317
1318         if (autoneg == AUTONEG_ENABLE &&
1319             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1320                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1321                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1322                 else
1323                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1324         } else
1325                 flowctrl = tp->link_config.flowctrl;
1326
1327         tp->link_config.active_flowctrl = flowctrl;
1328
1329         if (flowctrl & FLOW_CTRL_RX)
1330                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1331         else
1332                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1333
1334         if (old_rx_mode != tp->rx_mode)
1335                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1336
1337         if (flowctrl & FLOW_CTRL_TX)
1338                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1339         else
1340                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1341
1342         if (old_tx_mode != tp->tx_mode)
1343                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1344 }
1345
1346 static void tg3_adjust_link(struct net_device *dev)
1347 {
1348         u8 oldflowctrl, linkmesg = 0;
1349         u32 mac_mode, lcl_adv, rmt_adv;
1350         struct tg3 *tp = netdev_priv(dev);
1351         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1352
1353         spin_lock_bh(&tp->lock);
1354
1355         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1356                                     MAC_MODE_HALF_DUPLEX);
1357
1358         oldflowctrl = tp->link_config.active_flowctrl;
1359
1360         if (phydev->link) {
1361                 lcl_adv = 0;
1362                 rmt_adv = 0;
1363
1364                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1365                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1366                 else if (phydev->speed == SPEED_1000 ||
1367                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1368                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1369                 else
1370                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1371
1372                 if (phydev->duplex == DUPLEX_HALF)
1373                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1374                 else {
1375                         lcl_adv = tg3_advert_flowctrl_1000T(
1376                                   tp->link_config.flowctrl);
1377
1378                         if (phydev->pause)
1379                                 rmt_adv = LPA_PAUSE_CAP;
1380                         if (phydev->asym_pause)
1381                                 rmt_adv |= LPA_PAUSE_ASYM;
1382                 }
1383
1384                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1385         } else
1386                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1387
1388         if (mac_mode != tp->mac_mode) {
1389                 tp->mac_mode = mac_mode;
1390                 tw32_f(MAC_MODE, tp->mac_mode);
1391                 udelay(40);
1392         }
1393
1394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1395                 if (phydev->speed == SPEED_10)
1396                         tw32(MAC_MI_STAT,
1397                              MAC_MI_STAT_10MBPS_MODE |
1398                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1399                 else
1400                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1401         }
1402
1403         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1404                 tw32(MAC_TX_LENGTHS,
1405                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1406                       (6 << TX_LENGTHS_IPG_SHIFT) |
1407                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1408         else
1409                 tw32(MAC_TX_LENGTHS,
1410                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1411                       (6 << TX_LENGTHS_IPG_SHIFT) |
1412                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1413
1414         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1415             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1416             phydev->speed != tp->link_config.active_speed ||
1417             phydev->duplex != tp->link_config.active_duplex ||
1418             oldflowctrl != tp->link_config.active_flowctrl)
1419             linkmesg = 1;
1420
1421         tp->link_config.active_speed = phydev->speed;
1422         tp->link_config.active_duplex = phydev->duplex;
1423
1424         spin_unlock_bh(&tp->lock);
1425
1426         if (linkmesg)
1427                 tg3_link_report(tp);
1428 }
1429
1430 static int tg3_phy_init(struct tg3 *tp)
1431 {
1432         struct phy_device *phydev;
1433
1434         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1435                 return 0;
1436
1437         /* Bring the PHY back to a known state. */
1438         tg3_bmcr_reset(tp);
1439
1440         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1441
1442         /* Attach the MAC to the PHY. */
1443         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1444                              phydev->dev_flags, phydev->interface);
1445         if (IS_ERR(phydev)) {
1446                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1447                 return PTR_ERR(phydev);
1448         }
1449
1450         /* Mask with MAC supported features. */
1451         switch (phydev->interface) {
1452         case PHY_INTERFACE_MODE_GMII:
1453         case PHY_INTERFACE_MODE_RGMII:
1454                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1455                         phydev->supported &= (PHY_GBIT_FEATURES |
1456                                               SUPPORTED_Pause |
1457                                               SUPPORTED_Asym_Pause);
1458                         break;
1459                 }
1460                 /* fallthru */
1461         case PHY_INTERFACE_MODE_MII:
1462                 phydev->supported &= (PHY_BASIC_FEATURES |
1463                                       SUPPORTED_Pause |
1464                                       SUPPORTED_Asym_Pause);
1465                 break;
1466         default:
1467                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1468                 return -EINVAL;
1469         }
1470
1471         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1472
1473         phydev->advertising = phydev->supported;
1474
1475         return 0;
1476 }
1477
1478 static void tg3_phy_start(struct tg3 *tp)
1479 {
1480         struct phy_device *phydev;
1481
1482         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1483                 return;
1484
1485         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1486
1487         if (tp->link_config.phy_is_low_power) {
1488                 tp->link_config.phy_is_low_power = 0;
1489                 phydev->speed = tp->link_config.orig_speed;
1490                 phydev->duplex = tp->link_config.orig_duplex;
1491                 phydev->autoneg = tp->link_config.orig_autoneg;
1492                 phydev->advertising = tp->link_config.orig_advertising;
1493         }
1494
1495         phy_start(phydev);
1496
1497         phy_start_aneg(phydev);
1498 }
1499
1500 static void tg3_phy_stop(struct tg3 *tp)
1501 {
1502         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1503                 return;
1504
1505         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1506 }
1507
1508 static void tg3_phy_fini(struct tg3 *tp)
1509 {
1510         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1511                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1512                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1513         }
1514 }
1515
1516 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1517 {
1518         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1519         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1520 }
1521
1522 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1523 {
1524         u32 phytest;
1525
1526         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1527                 u32 phy;
1528
1529                 tg3_writephy(tp, MII_TG3_FET_TEST,
1530                              phytest | MII_TG3_FET_SHADOW_EN);
1531                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1532                         if (enable)
1533                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1534                         else
1535                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1536                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1537                 }
1538                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1539         }
1540 }
1541
1542 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1543 {
1544         u32 reg;
1545
1546         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1547                 return;
1548
1549         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1550                 tg3_phy_fet_toggle_apd(tp, enable);
1551                 return;
1552         }
1553
1554         reg = MII_TG3_MISC_SHDW_WREN |
1555               MII_TG3_MISC_SHDW_SCR5_SEL |
1556               MII_TG3_MISC_SHDW_SCR5_LPED |
1557               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1558               MII_TG3_MISC_SHDW_SCR5_SDTL |
1559               MII_TG3_MISC_SHDW_SCR5_C125OE;
1560         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1561                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1562
1563         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1564
1565
1566         reg = MII_TG3_MISC_SHDW_WREN |
1567               MII_TG3_MISC_SHDW_APD_SEL |
1568               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1569         if (enable)
1570                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1571
1572         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1573 }
1574
1575 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1576 {
1577         u32 phy;
1578
1579         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1580             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1581                 return;
1582
1583         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1584                 u32 ephy;
1585
1586                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1587                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1588
1589                         tg3_writephy(tp, MII_TG3_FET_TEST,
1590                                      ephy | MII_TG3_FET_SHADOW_EN);
1591                         if (!tg3_readphy(tp, reg, &phy)) {
1592                                 if (enable)
1593                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1594                                 else
1595                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1596                                 tg3_writephy(tp, reg, phy);
1597                         }
1598                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1599                 }
1600         } else {
1601                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1602                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1603                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1604                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1605                         if (enable)
1606                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1607                         else
1608                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1609                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1610                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1611                 }
1612         }
1613 }
1614
1615 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1616 {
1617         u32 val;
1618
1619         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1620                 return;
1621
1622         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1623             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1624                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1625                              (val | (1 << 15) | (1 << 4)));
1626 }
1627
1628 static void tg3_phy_apply_otp(struct tg3 *tp)
1629 {
1630         u32 otp, phy;
1631
1632         if (!tp->phy_otp)
1633                 return;
1634
1635         otp = tp->phy_otp;
1636
1637         /* Enable SM_DSP clock and tx 6dB coding. */
1638         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1639               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1640               MII_TG3_AUXCTL_ACTL_TX_6DB;
1641         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1642
1643         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1644         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1645         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1646
1647         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1648               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1649         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1650
1651         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1652         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1653         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1654
1655         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1656         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1657
1658         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1659         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1660
1661         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1662               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1663         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1664
1665         /* Turn off SM_DSP clock. */
1666         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1667               MII_TG3_AUXCTL_ACTL_TX_6DB;
1668         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1669 }
1670
1671 static int tg3_wait_macro_done(struct tg3 *tp)
1672 {
1673         int limit = 100;
1674
1675         while (limit--) {
1676                 u32 tmp32;
1677
1678                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1679                         if ((tmp32 & 0x1000) == 0)
1680                                 break;
1681                 }
1682         }
1683         if (limit < 0)
1684                 return -EBUSY;
1685
1686         return 0;
1687 }
1688
1689 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1690 {
1691         static const u32 test_pat[4][6] = {
1692         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1693         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1694         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1695         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1696         };
1697         int chan;
1698
1699         for (chan = 0; chan < 4; chan++) {
1700                 int i;
1701
1702                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1703                              (chan * 0x2000) | 0x0200);
1704                 tg3_writephy(tp, 0x16, 0x0002);
1705
1706                 for (i = 0; i < 6; i++)
1707                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1708                                      test_pat[chan][i]);
1709
1710                 tg3_writephy(tp, 0x16, 0x0202);
1711                 if (tg3_wait_macro_done(tp)) {
1712                         *resetp = 1;
1713                         return -EBUSY;
1714                 }
1715
1716                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1717                              (chan * 0x2000) | 0x0200);
1718                 tg3_writephy(tp, 0x16, 0x0082);
1719                 if (tg3_wait_macro_done(tp)) {
1720                         *resetp = 1;
1721                         return -EBUSY;
1722                 }
1723
1724                 tg3_writephy(tp, 0x16, 0x0802);
1725                 if (tg3_wait_macro_done(tp)) {
1726                         *resetp = 1;
1727                         return -EBUSY;
1728                 }
1729
1730                 for (i = 0; i < 6; i += 2) {
1731                         u32 low, high;
1732
1733                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1734                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1735                             tg3_wait_macro_done(tp)) {
1736                                 *resetp = 1;
1737                                 return -EBUSY;
1738                         }
1739                         low &= 0x7fff;
1740                         high &= 0x000f;
1741                         if (low != test_pat[chan][i] ||
1742                             high != test_pat[chan][i+1]) {
1743                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1744                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1745                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1746
1747                                 return -EBUSY;
1748                         }
1749                 }
1750         }
1751
1752         return 0;
1753 }
1754
1755 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1756 {
1757         int chan;
1758
1759         for (chan = 0; chan < 4; chan++) {
1760                 int i;
1761
1762                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1763                              (chan * 0x2000) | 0x0200);
1764                 tg3_writephy(tp, 0x16, 0x0002);
1765                 for (i = 0; i < 6; i++)
1766                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1767                 tg3_writephy(tp, 0x16, 0x0202);
1768                 if (tg3_wait_macro_done(tp))
1769                         return -EBUSY;
1770         }
1771
1772         return 0;
1773 }
1774
1775 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1776 {
1777         u32 reg32, phy9_orig;
1778         int retries, do_phy_reset, err;
1779
1780         retries = 10;
1781         do_phy_reset = 1;
1782         do {
1783                 if (do_phy_reset) {
1784                         err = tg3_bmcr_reset(tp);
1785                         if (err)
1786                                 return err;
1787                         do_phy_reset = 0;
1788                 }
1789
1790                 /* Disable transmitter and interrupt.  */
1791                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1792                         continue;
1793
1794                 reg32 |= 0x3000;
1795                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1796
1797                 /* Set full-duplex, 1000 mbps.  */
1798                 tg3_writephy(tp, MII_BMCR,
1799                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1800
1801                 /* Set to master mode.  */
1802                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1803                         continue;
1804
1805                 tg3_writephy(tp, MII_TG3_CTRL,
1806                              (MII_TG3_CTRL_AS_MASTER |
1807                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1808
1809                 /* Enable SM_DSP_CLOCK and 6dB.  */
1810                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1811
1812                 /* Block the PHY control access.  */
1813                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1814                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1815
1816                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1817                 if (!err)
1818                         break;
1819         } while (--retries);
1820
1821         err = tg3_phy_reset_chanpat(tp);
1822         if (err)
1823                 return err;
1824
1825         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1826         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1827
1828         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1829         tg3_writephy(tp, 0x16, 0x0000);
1830
1831         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1832             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1833                 /* Set Extended packet length bit for jumbo frames */
1834                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1835         }
1836         else {
1837                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1838         }
1839
1840         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1841
1842         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1843                 reg32 &= ~0x3000;
1844                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1845         } else if (!err)
1846                 err = -EBUSY;
1847
1848         return err;
1849 }
1850
1851 /* This will reset the tigon3 PHY if there is no valid
1852  * link unless the FORCE argument is non-zero.
1853  */
1854 static int tg3_phy_reset(struct tg3 *tp)
1855 {
1856         u32 cpmuctrl;
1857         u32 phy_status;
1858         int err;
1859
1860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1861                 u32 val;
1862
1863                 val = tr32(GRC_MISC_CFG);
1864                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1865                 udelay(40);
1866         }
1867         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1868         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1869         if (err != 0)
1870                 return -EBUSY;
1871
1872         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1873                 netif_carrier_off(tp->dev);
1874                 tg3_link_report(tp);
1875         }
1876
1877         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1878             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1879             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1880                 err = tg3_phy_reset_5703_4_5(tp);
1881                 if (err)
1882                         return err;
1883                 goto out;
1884         }
1885
1886         cpmuctrl = 0;
1887         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1888             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1889                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1890                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1891                         tw32(TG3_CPMU_CTRL,
1892                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1893         }
1894
1895         err = tg3_bmcr_reset(tp);
1896         if (err)
1897                 return err;
1898
1899         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1900                 u32 phy;
1901
1902                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1903                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1904
1905                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1906         }
1907
1908         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1909             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1910                 u32 val;
1911
1912                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1913                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1914                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1915                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1916                         udelay(40);
1917                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1918                 }
1919         }
1920
1921         tg3_phy_apply_otp(tp);
1922
1923         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1924                 tg3_phy_toggle_apd(tp, true);
1925         else
1926                 tg3_phy_toggle_apd(tp, false);
1927
1928 out:
1929         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1930                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1931                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1932                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1933                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1934                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1935                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1936         }
1937         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1938                 tg3_writephy(tp, 0x1c, 0x8d68);
1939                 tg3_writephy(tp, 0x1c, 0x8d68);
1940         }
1941         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1942                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1943                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1944                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1945                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1946                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1947                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1948                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1949                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1950         }
1951         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1952                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1953                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1954                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1955                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1956                         tg3_writephy(tp, MII_TG3_TEST1,
1957                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1958                 } else
1959                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961         }
1962         /* Set Extended packet length bit (bit 14) on all chips that */
1963         /* support jumbo frames */
1964         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1965                 /* Cannot do read-modify-write on 5401 */
1966                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1967         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1968                 u32 phy_reg;
1969
1970                 /* Set bit 14 with read-modify-write to preserve other bits */
1971                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1972                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1973                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1974         }
1975
1976         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1977          * jumbo frames transmission.
1978          */
1979         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1980                 u32 phy_reg;
1981
1982                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1983                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1984                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1985         }
1986
1987         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1988                 /* adjust output voltage */
1989                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1990         }
1991
1992         tg3_phy_toggle_automdix(tp, 1);
1993         tg3_phy_set_wirespeed(tp);
1994         return 0;
1995 }
1996
1997 static void tg3_frob_aux_power(struct tg3 *tp)
1998 {
1999         struct tg3 *tp_peer = tp;
2000
2001         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2002                 return;
2003
2004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2006             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2007                 struct net_device *dev_peer;
2008
2009                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2010                 /* remove_one() may have been run on the peer. */
2011                 if (!dev_peer)
2012                         tp_peer = tp;
2013                 else
2014                         tp_peer = netdev_priv(dev_peer);
2015         }
2016
2017         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2018             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2019             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2020             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2021                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2022                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2023                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024                                     (GRC_LCLCTRL_GPIO_OE0 |
2025                                      GRC_LCLCTRL_GPIO_OE1 |
2026                                      GRC_LCLCTRL_GPIO_OE2 |
2027                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2028                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2029                                     100);
2030                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2031                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2032                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2033                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2034                                              GRC_LCLCTRL_GPIO_OE1 |
2035                                              GRC_LCLCTRL_GPIO_OE2 |
2036                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2037                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2038                                              tp->grc_local_ctrl;
2039                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2040
2041                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2042                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2043
2044                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2045                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2046                 } else {
2047                         u32 no_gpio2;
2048                         u32 grc_local_ctrl = 0;
2049
2050                         if (tp_peer != tp &&
2051                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2052                                 return;
2053
2054                         /* Workaround to prevent overdrawing Amps. */
2055                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2056                             ASIC_REV_5714) {
2057                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2058                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2059                                             grc_local_ctrl, 100);
2060                         }
2061
2062                         /* On 5753 and variants, GPIO2 cannot be used. */
2063                         no_gpio2 = tp->nic_sram_data_cfg &
2064                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2065
2066                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2067                                          GRC_LCLCTRL_GPIO_OE1 |
2068                                          GRC_LCLCTRL_GPIO_OE2 |
2069                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2070                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2071                         if (no_gpio2) {
2072                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2073                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2074                         }
2075                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076                                                     grc_local_ctrl, 100);
2077
2078                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2079
2080                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2081                                                     grc_local_ctrl, 100);
2082
2083                         if (!no_gpio2) {
2084                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2085                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2086                                             grc_local_ctrl, 100);
2087                         }
2088                 }
2089         } else {
2090                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2091                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2092                         if (tp_peer != tp &&
2093                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2094                                 return;
2095
2096                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2097                                     (GRC_LCLCTRL_GPIO_OE1 |
2098                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2099
2100                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2101                                     GRC_LCLCTRL_GPIO_OE1, 100);
2102
2103                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104                                     (GRC_LCLCTRL_GPIO_OE1 |
2105                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2106                 }
2107         }
2108 }
2109
2110 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2111 {
2112         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2113                 return 1;
2114         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2115                 if (speed != SPEED_10)
2116                         return 1;
2117         } else if (speed == SPEED_10)
2118                 return 1;
2119
2120         return 0;
2121 }
2122
2123 static int tg3_setup_phy(struct tg3 *, int);
2124
2125 #define RESET_KIND_SHUTDOWN     0
2126 #define RESET_KIND_INIT         1
2127 #define RESET_KIND_SUSPEND      2
2128
2129 static void tg3_write_sig_post_reset(struct tg3 *, int);
2130 static int tg3_halt_cpu(struct tg3 *, u32);
2131
2132 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2133 {
2134         u32 val;
2135
2136         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2137                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2138                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2139                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2140
2141                         sg_dig_ctrl |=
2142                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2143                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2144                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2145                 }
2146                 return;
2147         }
2148
2149         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2150                 tg3_bmcr_reset(tp);
2151                 val = tr32(GRC_MISC_CFG);
2152                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2153                 udelay(40);
2154                 return;
2155         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2156                 u32 phytest;
2157                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2158                         u32 phy;
2159
2160                         tg3_writephy(tp, MII_ADVERTISE, 0);
2161                         tg3_writephy(tp, MII_BMCR,
2162                                      BMCR_ANENABLE | BMCR_ANRESTART);
2163
2164                         tg3_writephy(tp, MII_TG3_FET_TEST,
2165                                      phytest | MII_TG3_FET_SHADOW_EN);
2166                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2167                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2168                                 tg3_writephy(tp,
2169                                              MII_TG3_FET_SHDW_AUXMODE4,
2170                                              phy);
2171                         }
2172                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2173                 }
2174                 return;
2175         } else if (do_low_power) {
2176                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2177                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2178
2179                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2180                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2181                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2182                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2183                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2184         }
2185
2186         /* The PHY should not be powered down on some chips because
2187          * of bugs.
2188          */
2189         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2190             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2191             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2192              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2193                 return;
2194
2195         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2196             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2197                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2198                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2199                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2200                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2201         }
2202
2203         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2204 }
2205
2206 /* tp->lock is held. */
2207 static int tg3_nvram_lock(struct tg3 *tp)
2208 {
2209         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2210                 int i;
2211
2212                 if (tp->nvram_lock_cnt == 0) {
2213                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2214                         for (i = 0; i < 8000; i++) {
2215                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2216                                         break;
2217                                 udelay(20);
2218                         }
2219                         if (i == 8000) {
2220                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2221                                 return -ENODEV;
2222                         }
2223                 }
2224                 tp->nvram_lock_cnt++;
2225         }
2226         return 0;
2227 }
2228
2229 /* tp->lock is held. */
2230 static void tg3_nvram_unlock(struct tg3 *tp)
2231 {
2232         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2233                 if (tp->nvram_lock_cnt > 0)
2234                         tp->nvram_lock_cnt--;
2235                 if (tp->nvram_lock_cnt == 0)
2236                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2237         }
2238 }
2239
2240 /* tp->lock is held. */
2241 static void tg3_enable_nvram_access(struct tg3 *tp)
2242 {
2243         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2244             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2245                 u32 nvaccess = tr32(NVRAM_ACCESS);
2246
2247                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2248         }
2249 }
2250
2251 /* tp->lock is held. */
2252 static void tg3_disable_nvram_access(struct tg3 *tp)
2253 {
2254         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2255             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2256                 u32 nvaccess = tr32(NVRAM_ACCESS);
2257
2258                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2259         }
2260 }
2261
2262 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2263                                         u32 offset, u32 *val)
2264 {
2265         u32 tmp;
2266         int i;
2267
2268         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2269                 return -EINVAL;
2270
2271         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2272                                         EEPROM_ADDR_DEVID_MASK |
2273                                         EEPROM_ADDR_READ);
2274         tw32(GRC_EEPROM_ADDR,
2275              tmp |
2276              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2277              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2278               EEPROM_ADDR_ADDR_MASK) |
2279              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2280
2281         for (i = 0; i < 1000; i++) {
2282                 tmp = tr32(GRC_EEPROM_ADDR);
2283
2284                 if (tmp & EEPROM_ADDR_COMPLETE)
2285                         break;
2286                 msleep(1);
2287         }
2288         if (!(tmp & EEPROM_ADDR_COMPLETE))
2289                 return -EBUSY;
2290
2291         tmp = tr32(GRC_EEPROM_DATA);
2292
2293         /*
2294          * The data will always be opposite the native endian
2295          * format.  Perform a blind byteswap to compensate.
2296          */
2297         *val = swab32(tmp);
2298
2299         return 0;
2300 }
2301
2302 #define NVRAM_CMD_TIMEOUT 10000
2303
2304 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2305 {
2306         int i;
2307
2308         tw32(NVRAM_CMD, nvram_cmd);
2309         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2310                 udelay(10);
2311                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2312                         udelay(10);
2313                         break;
2314                 }
2315         }
2316
2317         if (i == NVRAM_CMD_TIMEOUT)
2318                 return -EBUSY;
2319
2320         return 0;
2321 }
2322
2323 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2324 {
2325         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2326             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2327             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2328            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2329             (tp->nvram_jedecnum == JEDEC_ATMEL))
2330
2331                 addr = ((addr / tp->nvram_pagesize) <<
2332                         ATMEL_AT45DB0X1B_PAGE_POS) +
2333                        (addr % tp->nvram_pagesize);
2334
2335         return addr;
2336 }
2337
2338 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2339 {
2340         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2341             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2342             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2343            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2344             (tp->nvram_jedecnum == JEDEC_ATMEL))
2345
2346                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2347                         tp->nvram_pagesize) +
2348                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2349
2350         return addr;
2351 }
2352
2353 /* NOTE: Data read in from NVRAM is byteswapped according to
2354  * the byteswapping settings for all other register accesses.
2355  * tg3 devices are BE devices, so on a BE machine, the data
2356  * returned will be exactly as it is seen in NVRAM.  On a LE
2357  * machine, the 32-bit value will be byteswapped.
2358  */
2359 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2360 {
2361         int ret;
2362
2363         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2364                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2365
2366         offset = tg3_nvram_phys_addr(tp, offset);
2367
2368         if (offset > NVRAM_ADDR_MSK)
2369                 return -EINVAL;
2370
2371         ret = tg3_nvram_lock(tp);
2372         if (ret)
2373                 return ret;
2374
2375         tg3_enable_nvram_access(tp);
2376
2377         tw32(NVRAM_ADDR, offset);
2378         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2379                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2380
2381         if (ret == 0)
2382                 *val = tr32(NVRAM_RDDATA);
2383
2384         tg3_disable_nvram_access(tp);
2385
2386         tg3_nvram_unlock(tp);
2387
2388         return ret;
2389 }
2390
2391 /* Ensures NVRAM data is in bytestream format. */
2392 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2393 {
2394         u32 v;
2395         int res = tg3_nvram_read(tp, offset, &v);
2396         if (!res)
2397                 *val = cpu_to_be32(v);
2398         return res;
2399 }
2400
2401 /* tp->lock is held. */
2402 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2403 {
2404         u32 addr_high, addr_low;
2405         int i;
2406
2407         addr_high = ((tp->dev->dev_addr[0] << 8) |
2408                      tp->dev->dev_addr[1]);
2409         addr_low = ((tp->dev->dev_addr[2] << 24) |
2410                     (tp->dev->dev_addr[3] << 16) |
2411                     (tp->dev->dev_addr[4] <<  8) |
2412                     (tp->dev->dev_addr[5] <<  0));
2413         for (i = 0; i < 4; i++) {
2414                 if (i == 1 && skip_mac_1)
2415                         continue;
2416                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2417                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2418         }
2419
2420         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2421             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2422                 for (i = 0; i < 12; i++) {
2423                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2424                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2425                 }
2426         }
2427
2428         addr_high = (tp->dev->dev_addr[0] +
2429                      tp->dev->dev_addr[1] +
2430                      tp->dev->dev_addr[2] +
2431                      tp->dev->dev_addr[3] +
2432                      tp->dev->dev_addr[4] +
2433                      tp->dev->dev_addr[5]) &
2434                 TX_BACKOFF_SEED_MASK;
2435         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2436 }
2437
2438 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2439 {
2440         u32 misc_host_ctrl;
2441         bool device_should_wake, do_low_power;
2442
2443         /* Make sure register accesses (indirect or otherwise)
2444          * will function correctly.
2445          */
2446         pci_write_config_dword(tp->pdev,
2447                                TG3PCI_MISC_HOST_CTRL,
2448                                tp->misc_host_ctrl);
2449
2450         switch (state) {
2451         case PCI_D0:
2452                 pci_enable_wake(tp->pdev, state, false);
2453                 pci_set_power_state(tp->pdev, PCI_D0);
2454
2455                 /* Switch out of Vaux if it is a NIC */
2456                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2457                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2458
2459                 return 0;
2460
2461         case PCI_D1:
2462         case PCI_D2:
2463         case PCI_D3hot:
2464                 break;
2465
2466         default:
2467                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2468                         tp->dev->name, state);
2469                 return -EINVAL;
2470         }
2471
2472         /* Restore the CLKREQ setting. */
2473         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2474                 u16 lnkctl;
2475
2476                 pci_read_config_word(tp->pdev,
2477                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2478                                      &lnkctl);
2479                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2480                 pci_write_config_word(tp->pdev,
2481                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2482                                       lnkctl);
2483         }
2484
2485         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2486         tw32(TG3PCI_MISC_HOST_CTRL,
2487              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2488
2489         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2490                              device_may_wakeup(&tp->pdev->dev) &&
2491                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2492
2493         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2494                 do_low_power = false;
2495                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2496                     !tp->link_config.phy_is_low_power) {
2497                         struct phy_device *phydev;
2498                         u32 phyid, advertising;
2499
2500                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2501
2502                         tp->link_config.phy_is_low_power = 1;
2503
2504                         tp->link_config.orig_speed = phydev->speed;
2505                         tp->link_config.orig_duplex = phydev->duplex;
2506                         tp->link_config.orig_autoneg = phydev->autoneg;
2507                         tp->link_config.orig_advertising = phydev->advertising;
2508
2509                         advertising = ADVERTISED_TP |
2510                                       ADVERTISED_Pause |
2511                                       ADVERTISED_Autoneg |
2512                                       ADVERTISED_10baseT_Half;
2513
2514                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2515                             device_should_wake) {
2516                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2517                                         advertising |=
2518                                                 ADVERTISED_100baseT_Half |
2519                                                 ADVERTISED_100baseT_Full |
2520                                                 ADVERTISED_10baseT_Full;
2521                                 else
2522                                         advertising |= ADVERTISED_10baseT_Full;
2523                         }
2524
2525                         phydev->advertising = advertising;
2526
2527                         phy_start_aneg(phydev);
2528
2529                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2530                         if (phyid != TG3_PHY_ID_BCMAC131) {
2531                                 phyid &= TG3_PHY_OUI_MASK;
2532                                 if (phyid == TG3_PHY_OUI_1 ||
2533                                     phyid == TG3_PHY_OUI_2 ||
2534                                     phyid == TG3_PHY_OUI_3)
2535                                         do_low_power = true;
2536                         }
2537                 }
2538         } else {
2539                 do_low_power = true;
2540
2541                 if (tp->link_config.phy_is_low_power == 0) {
2542                         tp->link_config.phy_is_low_power = 1;
2543                         tp->link_config.orig_speed = tp->link_config.speed;
2544                         tp->link_config.orig_duplex = tp->link_config.duplex;
2545                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2546                 }
2547
2548                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2549                         tp->link_config.speed = SPEED_10;
2550                         tp->link_config.duplex = DUPLEX_HALF;
2551                         tp->link_config.autoneg = AUTONEG_ENABLE;
2552                         tg3_setup_phy(tp, 0);
2553                 }
2554         }
2555
2556         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2557                 u32 val;
2558
2559                 val = tr32(GRC_VCPU_EXT_CTRL);
2560                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2561         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2562                 int i;
2563                 u32 val;
2564
2565                 for (i = 0; i < 200; i++) {
2566                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2567                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2568                                 break;
2569                         msleep(1);
2570                 }
2571         }
2572         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2573                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2574                                                      WOL_DRV_STATE_SHUTDOWN |
2575                                                      WOL_DRV_WOL |
2576                                                      WOL_SET_MAGIC_PKT);
2577
2578         if (device_should_wake) {
2579                 u32 mac_mode;
2580
2581                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2582                         if (do_low_power) {
2583                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2584                                 udelay(40);
2585                         }
2586
2587                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2588                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2589                         else
2590                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2591
2592                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2593                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2594                             ASIC_REV_5700) {
2595                                 u32 speed = (tp->tg3_flags &
2596                                              TG3_FLAG_WOL_SPEED_100MB) ?
2597                                              SPEED_100 : SPEED_10;
2598                                 if (tg3_5700_link_polarity(tp, speed))
2599                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2600                                 else
2601                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2602                         }
2603                 } else {
2604                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2605                 }
2606
2607                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2608                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2609
2610                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2611                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2612                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2613                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2614                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2615                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2616
2617                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2618                         mac_mode |= tp->mac_mode &
2619                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2620                         if (mac_mode & MAC_MODE_APE_TX_EN)
2621                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2622                 }
2623
2624                 tw32_f(MAC_MODE, mac_mode);
2625                 udelay(100);
2626
2627                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2628                 udelay(10);
2629         }
2630
2631         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2632             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2633              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2634                 u32 base_val;
2635
2636                 base_val = tp->pci_clock_ctrl;
2637                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2638                              CLOCK_CTRL_TXCLK_DISABLE);
2639
2640                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2641                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2642         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2643                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2644                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2645                 /* do nothing */
2646         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2647                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2648                 u32 newbits1, newbits2;
2649
2650                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2652                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2653                                     CLOCK_CTRL_TXCLK_DISABLE |
2654                                     CLOCK_CTRL_ALTCLK);
2655                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2656                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2657                         newbits1 = CLOCK_CTRL_625_CORE;
2658                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2659                 } else {
2660                         newbits1 = CLOCK_CTRL_ALTCLK;
2661                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2662                 }
2663
2664                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2665                             40);
2666
2667                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2668                             40);
2669
2670                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2671                         u32 newbits3;
2672
2673                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2674                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2675                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2676                                             CLOCK_CTRL_TXCLK_DISABLE |
2677                                             CLOCK_CTRL_44MHZ_CORE);
2678                         } else {
2679                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2680                         }
2681
2682                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2683                                     tp->pci_clock_ctrl | newbits3, 40);
2684                 }
2685         }
2686
2687         if (!(device_should_wake) &&
2688             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2689                 tg3_power_down_phy(tp, do_low_power);
2690
2691         tg3_frob_aux_power(tp);
2692
2693         /* Workaround for unstable PLL clock */
2694         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2695             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2696                 u32 val = tr32(0x7d00);
2697
2698                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2699                 tw32(0x7d00, val);
2700                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2701                         int err;
2702
2703                         err = tg3_nvram_lock(tp);
2704                         tg3_halt_cpu(tp, RX_CPU_BASE);
2705                         if (!err)
2706                                 tg3_nvram_unlock(tp);
2707                 }
2708         }
2709
2710         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2711
2712         if (device_should_wake)
2713                 pci_enable_wake(tp->pdev, state, true);
2714
2715         /* Finally, set the new power state. */
2716         pci_set_power_state(tp->pdev, state);
2717
2718         return 0;
2719 }
2720
2721 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2722 {
2723         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2724         case MII_TG3_AUX_STAT_10HALF:
2725                 *speed = SPEED_10;
2726                 *duplex = DUPLEX_HALF;
2727                 break;
2728
2729         case MII_TG3_AUX_STAT_10FULL:
2730                 *speed = SPEED_10;
2731                 *duplex = DUPLEX_FULL;
2732                 break;
2733
2734         case MII_TG3_AUX_STAT_100HALF:
2735                 *speed = SPEED_100;
2736                 *duplex = DUPLEX_HALF;
2737                 break;
2738
2739         case MII_TG3_AUX_STAT_100FULL:
2740                 *speed = SPEED_100;
2741                 *duplex = DUPLEX_FULL;
2742                 break;
2743
2744         case MII_TG3_AUX_STAT_1000HALF:
2745                 *speed = SPEED_1000;
2746                 *duplex = DUPLEX_HALF;
2747                 break;
2748
2749         case MII_TG3_AUX_STAT_1000FULL:
2750                 *speed = SPEED_1000;
2751                 *duplex = DUPLEX_FULL;
2752                 break;
2753
2754         default:
2755                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2756                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2757                                  SPEED_10;
2758                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2759                                   DUPLEX_HALF;
2760                         break;
2761                 }
2762                 *speed = SPEED_INVALID;
2763                 *duplex = DUPLEX_INVALID;
2764                 break;
2765         }
2766 }
2767
2768 static void tg3_phy_copper_begin(struct tg3 *tp)
2769 {
2770         u32 new_adv;
2771         int i;
2772
2773         if (tp->link_config.phy_is_low_power) {
2774                 /* Entering low power mode.  Disable gigabit and
2775                  * 100baseT advertisements.
2776                  */
2777                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2778
2779                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2780                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2781                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2782                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2783
2784                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2785         } else if (tp->link_config.speed == SPEED_INVALID) {
2786                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2787                         tp->link_config.advertising &=
2788                                 ~(ADVERTISED_1000baseT_Half |
2789                                   ADVERTISED_1000baseT_Full);
2790
2791                 new_adv = ADVERTISE_CSMA;
2792                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2793                         new_adv |= ADVERTISE_10HALF;
2794                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2795                         new_adv |= ADVERTISE_10FULL;
2796                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2797                         new_adv |= ADVERTISE_100HALF;
2798                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2799                         new_adv |= ADVERTISE_100FULL;
2800
2801                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2802
2803                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2804
2805                 if (tp->link_config.advertising &
2806                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2807                         new_adv = 0;
2808                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2809                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2810                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2811                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2812                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2813                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2814                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2815                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2816                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2817                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2818                 } else {
2819                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2820                 }
2821         } else {
2822                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2823                 new_adv |= ADVERTISE_CSMA;
2824
2825                 /* Asking for a specific link mode. */
2826                 if (tp->link_config.speed == SPEED_1000) {
2827                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2828
2829                         if (tp->link_config.duplex == DUPLEX_FULL)
2830                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2831                         else
2832                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2833                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2834                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2835                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2836                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2837                 } else {
2838                         if (tp->link_config.speed == SPEED_100) {
2839                                 if (tp->link_config.duplex == DUPLEX_FULL)
2840                                         new_adv |= ADVERTISE_100FULL;
2841                                 else
2842                                         new_adv |= ADVERTISE_100HALF;
2843                         } else {
2844                                 if (tp->link_config.duplex == DUPLEX_FULL)
2845                                         new_adv |= ADVERTISE_10FULL;
2846                                 else
2847                                         new_adv |= ADVERTISE_10HALF;
2848                         }
2849                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2850
2851                         new_adv = 0;
2852                 }
2853
2854                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2855         }
2856
2857         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2858             tp->link_config.speed != SPEED_INVALID) {
2859                 u32 bmcr, orig_bmcr;
2860
2861                 tp->link_config.active_speed = tp->link_config.speed;
2862                 tp->link_config.active_duplex = tp->link_config.duplex;
2863
2864                 bmcr = 0;
2865                 switch (tp->link_config.speed) {
2866                 default:
2867                 case SPEED_10:
2868                         break;
2869
2870                 case SPEED_100:
2871                         bmcr |= BMCR_SPEED100;
2872                         break;
2873
2874                 case SPEED_1000:
2875                         bmcr |= TG3_BMCR_SPEED1000;
2876                         break;
2877                 }
2878
2879                 if (tp->link_config.duplex == DUPLEX_FULL)
2880                         bmcr |= BMCR_FULLDPLX;
2881
2882                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2883                     (bmcr != orig_bmcr)) {
2884                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2885                         for (i = 0; i < 1500; i++) {
2886                                 u32 tmp;
2887
2888                                 udelay(10);
2889                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2890                                     tg3_readphy(tp, MII_BMSR, &tmp))
2891                                         continue;
2892                                 if (!(tmp & BMSR_LSTATUS)) {
2893                                         udelay(40);
2894                                         break;
2895                                 }
2896                         }
2897                         tg3_writephy(tp, MII_BMCR, bmcr);
2898                         udelay(40);
2899                 }
2900         } else {
2901                 tg3_writephy(tp, MII_BMCR,
2902                              BMCR_ANENABLE | BMCR_ANRESTART);
2903         }
2904 }
2905
2906 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2907 {
2908         int err;
2909
2910         /* Turn off tap power management. */
2911         /* Set Extended packet length bit */
2912         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2913
2914         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2915         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2916
2917         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2918         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2919
2920         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2921         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2922
2923         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2924         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2925
2926         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2927         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2928
2929         udelay(40);
2930
2931         return err;
2932 }
2933
2934 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2935 {
2936         u32 adv_reg, all_mask = 0;
2937
2938         if (mask & ADVERTISED_10baseT_Half)
2939                 all_mask |= ADVERTISE_10HALF;
2940         if (mask & ADVERTISED_10baseT_Full)
2941                 all_mask |= ADVERTISE_10FULL;
2942         if (mask & ADVERTISED_100baseT_Half)
2943                 all_mask |= ADVERTISE_100HALF;
2944         if (mask & ADVERTISED_100baseT_Full)
2945                 all_mask |= ADVERTISE_100FULL;
2946
2947         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2948                 return 0;
2949
2950         if ((adv_reg & all_mask) != all_mask)
2951                 return 0;
2952         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2953                 u32 tg3_ctrl;
2954
2955                 all_mask = 0;
2956                 if (mask & ADVERTISED_1000baseT_Half)
2957                         all_mask |= ADVERTISE_1000HALF;
2958                 if (mask & ADVERTISED_1000baseT_Full)
2959                         all_mask |= ADVERTISE_1000FULL;
2960
2961                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2962                         return 0;
2963
2964                 if ((tg3_ctrl & all_mask) != all_mask)
2965                         return 0;
2966         }
2967         return 1;
2968 }
2969
2970 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2971 {
2972         u32 curadv, reqadv;
2973
2974         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2975                 return 1;
2976
2977         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2978         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2979
2980         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2981                 if (curadv != reqadv)
2982                         return 0;
2983
2984                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2985                         tg3_readphy(tp, MII_LPA, rmtadv);
2986         } else {
2987                 /* Reprogram the advertisement register, even if it
2988                  * does not affect the current link.  If the link
2989                  * gets renegotiated in the future, we can save an
2990                  * additional renegotiation cycle by advertising
2991                  * it correctly in the first place.
2992                  */
2993                 if (curadv != reqadv) {
2994                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2995                                      ADVERTISE_PAUSE_ASYM);
2996                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2997                 }
2998         }
2999
3000         return 1;
3001 }
3002
3003 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3004 {
3005         int current_link_up;
3006         u32 bmsr, dummy;
3007         u32 lcl_adv, rmt_adv;
3008         u16 current_speed;
3009         u8 current_duplex;
3010         int i, err;
3011
3012         tw32(MAC_EVENT, 0);
3013
3014         tw32_f(MAC_STATUS,
3015              (MAC_STATUS_SYNC_CHANGED |
3016               MAC_STATUS_CFG_CHANGED |
3017               MAC_STATUS_MI_COMPLETION |
3018               MAC_STATUS_LNKSTATE_CHANGED));
3019         udelay(40);
3020
3021         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3022                 tw32_f(MAC_MI_MODE,
3023                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3024                 udelay(80);
3025         }
3026
3027         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3028
3029         /* Some third-party PHYs need to be reset on link going
3030          * down.
3031          */
3032         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3033              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3034              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3035             netif_carrier_ok(tp->dev)) {
3036                 tg3_readphy(tp, MII_BMSR, &bmsr);
3037                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3038                     !(bmsr & BMSR_LSTATUS))
3039                         force_reset = 1;
3040         }
3041         if (force_reset)
3042                 tg3_phy_reset(tp);
3043
3044         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3045                 tg3_readphy(tp, MII_BMSR, &bmsr);
3046                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3047                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3048                         bmsr = 0;
3049
3050                 if (!(bmsr & BMSR_LSTATUS)) {
3051                         err = tg3_init_5401phy_dsp(tp);
3052                         if (err)
3053                                 return err;
3054
3055                         tg3_readphy(tp, MII_BMSR, &bmsr);
3056                         for (i = 0; i < 1000; i++) {
3057                                 udelay(10);
3058                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3059                                     (bmsr & BMSR_LSTATUS)) {
3060                                         udelay(40);
3061                                         break;
3062                                 }
3063                         }
3064
3065                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3066                             !(bmsr & BMSR_LSTATUS) &&
3067                             tp->link_config.active_speed == SPEED_1000) {
3068                                 err = tg3_phy_reset(tp);
3069                                 if (!err)
3070                                         err = tg3_init_5401phy_dsp(tp);
3071                                 if (err)
3072                                         return err;
3073                         }
3074                 }
3075         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3076                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3077                 /* 5701 {A0,B0} CRC bug workaround */
3078                 tg3_writephy(tp, 0x15, 0x0a75);
3079                 tg3_writephy(tp, 0x1c, 0x8c68);
3080                 tg3_writephy(tp, 0x1c, 0x8d68);
3081                 tg3_writephy(tp, 0x1c, 0x8c68);
3082         }
3083
3084         /* Clear pending interrupts... */
3085         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3086         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3087
3088         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3089                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3090         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3091                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3092
3093         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3094             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3095                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3096                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3097                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3098                 else
3099                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3100         }
3101
3102         current_link_up = 0;
3103         current_speed = SPEED_INVALID;
3104         current_duplex = DUPLEX_INVALID;
3105
3106         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3107                 u32 val;
3108
3109                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3110                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3111                 if (!(val & (1 << 10))) {
3112                         val |= (1 << 10);
3113                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3114                         goto relink;
3115                 }
3116         }
3117
3118         bmsr = 0;
3119         for (i = 0; i < 100; i++) {
3120                 tg3_readphy(tp, MII_BMSR, &bmsr);
3121                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3122                     (bmsr & BMSR_LSTATUS))
3123                         break;
3124                 udelay(40);
3125         }
3126
3127         if (bmsr & BMSR_LSTATUS) {
3128                 u32 aux_stat, bmcr;
3129
3130                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3131                 for (i = 0; i < 2000; i++) {
3132                         udelay(10);
3133                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3134                             aux_stat)
3135                                 break;
3136                 }
3137
3138                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3139                                              &current_speed,
3140                                              &current_duplex);
3141
3142                 bmcr = 0;
3143                 for (i = 0; i < 200; i++) {
3144                         tg3_readphy(tp, MII_BMCR, &bmcr);
3145                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3146                                 continue;
3147                         if (bmcr && bmcr != 0x7fff)
3148                                 break;
3149                         udelay(10);
3150                 }
3151
3152                 lcl_adv = 0;
3153                 rmt_adv = 0;
3154
3155                 tp->link_config.active_speed = current_speed;
3156                 tp->link_config.active_duplex = current_duplex;
3157
3158                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3159                         if ((bmcr & BMCR_ANENABLE) &&
3160                             tg3_copper_is_advertising_all(tp,
3161                                                 tp->link_config.advertising)) {
3162                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3163                                                                   &rmt_adv))
3164                                         current_link_up = 1;
3165                         }
3166                 } else {
3167                         if (!(bmcr & BMCR_ANENABLE) &&
3168                             tp->link_config.speed == current_speed &&
3169                             tp->link_config.duplex == current_duplex &&
3170                             tp->link_config.flowctrl ==
3171                             tp->link_config.active_flowctrl) {
3172                                 current_link_up = 1;
3173                         }
3174                 }
3175
3176                 if (current_link_up == 1 &&
3177                     tp->link_config.active_duplex == DUPLEX_FULL)
3178                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3179         }
3180
3181 relink:
3182         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3183                 u32 tmp;
3184
3185                 tg3_phy_copper_begin(tp);
3186
3187                 tg3_readphy(tp, MII_BMSR, &tmp);
3188                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3189                     (tmp & BMSR_LSTATUS))
3190                         current_link_up = 1;
3191         }
3192
3193         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3194         if (current_link_up == 1) {
3195                 if (tp->link_config.active_speed == SPEED_100 ||
3196                     tp->link_config.active_speed == SPEED_10)
3197                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3198                 else
3199                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3200         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3201                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3202         else
3203                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3204
3205         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3206         if (tp->link_config.active_duplex == DUPLEX_HALF)
3207                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3208
3209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3210                 if (current_link_up == 1 &&
3211                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3212                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3213                 else
3214                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3215         }
3216
3217         /* ??? Without this setting Netgear GA302T PHY does not
3218          * ??? send/receive packets...
3219          */
3220         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3221             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3222                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3223                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3224                 udelay(80);
3225         }
3226
3227         tw32_f(MAC_MODE, tp->mac_mode);
3228         udelay(40);
3229
3230         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3231                 /* Polled via timer. */
3232                 tw32_f(MAC_EVENT, 0);
3233         } else {
3234                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3235         }
3236         udelay(40);
3237
3238         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3239             current_link_up == 1 &&
3240             tp->link_config.active_speed == SPEED_1000 &&
3241             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3242              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3243                 udelay(120);
3244                 tw32_f(MAC_STATUS,
3245                      (MAC_STATUS_SYNC_CHANGED |
3246                       MAC_STATUS_CFG_CHANGED));
3247                 udelay(40);
3248                 tg3_write_mem(tp,
3249                               NIC_SRAM_FIRMWARE_MBOX,
3250                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3251         }
3252
3253         /* Prevent send BD corruption. */
3254         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3255                 u16 oldlnkctl, newlnkctl;
3256
3257                 pci_read_config_word(tp->pdev,
3258                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3259                                      &oldlnkctl);
3260                 if (tp->link_config.active_speed == SPEED_100 ||
3261                     tp->link_config.active_speed == SPEED_10)
3262                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3263                 else
3264                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3265                 if (newlnkctl != oldlnkctl)
3266                         pci_write_config_word(tp->pdev,
3267                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3268                                               newlnkctl);
3269         }
3270
3271         if (current_link_up != netif_carrier_ok(tp->dev)) {
3272                 if (current_link_up)
3273                         netif_carrier_on(tp->dev);
3274                 else
3275                         netif_carrier_off(tp->dev);
3276                 tg3_link_report(tp);
3277         }
3278
3279         return 0;
3280 }
3281
3282 struct tg3_fiber_aneginfo {
3283         int state;
3284 #define ANEG_STATE_UNKNOWN              0
3285 #define ANEG_STATE_AN_ENABLE            1
3286 #define ANEG_STATE_RESTART_INIT         2
3287 #define ANEG_STATE_RESTART              3
3288 #define ANEG_STATE_DISABLE_LINK_OK      4
3289 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3290 #define ANEG_STATE_ABILITY_DETECT       6
3291 #define ANEG_STATE_ACK_DETECT_INIT      7
3292 #define ANEG_STATE_ACK_DETECT           8
3293 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3294 #define ANEG_STATE_COMPLETE_ACK         10
3295 #define ANEG_STATE_IDLE_DETECT_INIT     11
3296 #define ANEG_STATE_IDLE_DETECT          12
3297 #define ANEG_STATE_LINK_OK              13
3298 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3299 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3300
3301         u32 flags;
3302 #define MR_AN_ENABLE            0x00000001
3303 #define MR_RESTART_AN           0x00000002
3304 #define MR_AN_COMPLETE          0x00000004
3305 #define MR_PAGE_RX              0x00000008
3306 #define MR_NP_LOADED            0x00000010
3307 #define MR_TOGGLE_TX            0x00000020
3308 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3309 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3310 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3311 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3312 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3313 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3314 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3315 #define MR_TOGGLE_RX            0x00002000
3316 #define MR_NP_RX                0x00004000
3317
3318 #define MR_LINK_OK              0x80000000
3319
3320         unsigned long link_time, cur_time;
3321
3322         u32 ability_match_cfg;
3323         int ability_match_count;
3324
3325         char ability_match, idle_match, ack_match;
3326
3327         u32 txconfig, rxconfig;
3328 #define ANEG_CFG_NP             0x00000080
3329 #define ANEG_CFG_ACK            0x00000040
3330 #define ANEG_CFG_RF2            0x00000020
3331 #define ANEG_CFG_RF1            0x00000010
3332 #define ANEG_CFG_PS2            0x00000001
3333 #define ANEG_CFG_PS1            0x00008000
3334 #define ANEG_CFG_HD             0x00004000
3335 #define ANEG_CFG_FD             0x00002000
3336 #define ANEG_CFG_INVAL          0x00001f06
3337
3338 };
3339 #define ANEG_OK         0
3340 #define ANEG_DONE       1
3341 #define ANEG_TIMER_ENAB 2
3342 #define ANEG_FAILED     -1
3343
3344 #define ANEG_STATE_SETTLE_TIME  10000
3345
3346 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3347                                    struct tg3_fiber_aneginfo *ap)
3348 {
3349         u16 flowctrl;
3350         unsigned long delta;
3351         u32 rx_cfg_reg;
3352         int ret;
3353
3354         if (ap->state == ANEG_STATE_UNKNOWN) {
3355                 ap->rxconfig = 0;
3356                 ap->link_time = 0;
3357                 ap->cur_time = 0;
3358                 ap->ability_match_cfg = 0;
3359                 ap->ability_match_count = 0;
3360                 ap->ability_match = 0;
3361                 ap->idle_match = 0;
3362                 ap->ack_match = 0;
3363         }
3364         ap->cur_time++;
3365
3366         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3367                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3368
3369                 if (rx_cfg_reg != ap->ability_match_cfg) {
3370                         ap->ability_match_cfg = rx_cfg_reg;
3371                         ap->ability_match = 0;
3372                         ap->ability_match_count = 0;
3373                 } else {
3374                         if (++ap->ability_match_count > 1) {
3375                                 ap->ability_match = 1;
3376                                 ap->ability_match_cfg = rx_cfg_reg;
3377                         }
3378                 }
3379                 if (rx_cfg_reg & ANEG_CFG_ACK)
3380                         ap->ack_match = 1;
3381                 else
3382                         ap->ack_match = 0;
3383
3384                 ap->idle_match = 0;
3385         } else {
3386                 ap->idle_match = 1;
3387                 ap->ability_match_cfg = 0;
3388                 ap->ability_match_count = 0;
3389                 ap->ability_match = 0;
3390                 ap->ack_match = 0;
3391
3392                 rx_cfg_reg = 0;
3393         }
3394
3395         ap->rxconfig = rx_cfg_reg;
3396         ret = ANEG_OK;
3397
3398         switch(ap->state) {
3399         case ANEG_STATE_UNKNOWN:
3400                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3401                         ap->state = ANEG_STATE_AN_ENABLE;
3402
3403                 /* fallthru */
3404         case ANEG_STATE_AN_ENABLE:
3405                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3406                 if (ap->flags & MR_AN_ENABLE) {
3407                         ap->link_time = 0;
3408                         ap->cur_time = 0;
3409                         ap->ability_match_cfg = 0;
3410                         ap->ability_match_count = 0;
3411                         ap->ability_match = 0;
3412                         ap->idle_match = 0;
3413                         ap->ack_match = 0;
3414
3415                         ap->state = ANEG_STATE_RESTART_INIT;
3416                 } else {
3417                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3418                 }
3419                 break;
3420
3421         case ANEG_STATE_RESTART_INIT:
3422                 ap->link_time = ap->cur_time;
3423                 ap->flags &= ~(MR_NP_LOADED);
3424                 ap->txconfig = 0;
3425                 tw32(MAC_TX_AUTO_NEG, 0);
3426                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3427                 tw32_f(MAC_MODE, tp->mac_mode);
3428                 udelay(40);
3429
3430                 ret = ANEG_TIMER_ENAB;
3431                 ap->state = ANEG_STATE_RESTART;
3432
3433                 /* fallthru */
3434         case ANEG_STATE_RESTART:
3435                 delta = ap->cur_time - ap->link_time;
3436                 if (delta > ANEG_STATE_SETTLE_TIME) {
3437                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3438                 } else {
3439                         ret = ANEG_TIMER_ENAB;
3440                 }
3441                 break;
3442
3443         case ANEG_STATE_DISABLE_LINK_OK:
3444                 ret = ANEG_DONE;
3445                 break;
3446
3447         case ANEG_STATE_ABILITY_DETECT_INIT:
3448                 ap->flags &= ~(MR_TOGGLE_TX);
3449                 ap->txconfig = ANEG_CFG_FD;
3450                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3451                 if (flowctrl & ADVERTISE_1000XPAUSE)
3452                         ap->txconfig |= ANEG_CFG_PS1;
3453                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3454                         ap->txconfig |= ANEG_CFG_PS2;
3455                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3456                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3457                 tw32_f(MAC_MODE, tp->mac_mode);
3458                 udelay(40);
3459
3460                 ap->state = ANEG_STATE_ABILITY_DETECT;
3461                 break;
3462
3463         case ANEG_STATE_ABILITY_DETECT:
3464                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3465                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3466                 }
3467                 break;
3468
3469         case ANEG_STATE_ACK_DETECT_INIT:
3470                 ap->txconfig |= ANEG_CFG_ACK;
3471                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3472                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3473                 tw32_f(MAC_MODE, tp->mac_mode);
3474                 udelay(40);
3475
3476                 ap->state = ANEG_STATE_ACK_DETECT;
3477
3478                 /* fallthru */
3479         case ANEG_STATE_ACK_DETECT:
3480                 if (ap->ack_match != 0) {
3481                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3482                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3483                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3484                         } else {
3485                                 ap->state = ANEG_STATE_AN_ENABLE;
3486                         }
3487                 } else if (ap->ability_match != 0 &&
3488                            ap->rxconfig == 0) {
3489                         ap->state = ANEG_STATE_AN_ENABLE;
3490                 }
3491                 break;
3492
3493         case ANEG_STATE_COMPLETE_ACK_INIT:
3494                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3495                         ret = ANEG_FAILED;
3496                         break;
3497                 }
3498                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3499                                MR_LP_ADV_HALF_DUPLEX |
3500                                MR_LP_ADV_SYM_PAUSE |
3501                                MR_LP_ADV_ASYM_PAUSE |
3502                                MR_LP_ADV_REMOTE_FAULT1 |
3503                                MR_LP_ADV_REMOTE_FAULT2 |
3504                                MR_LP_ADV_NEXT_PAGE |
3505                                MR_TOGGLE_RX |
3506                                MR_NP_RX);
3507                 if (ap->rxconfig & ANEG_CFG_FD)
3508                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3509                 if (ap->rxconfig & ANEG_CFG_HD)
3510                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3511                 if (ap->rxconfig & ANEG_CFG_PS1)
3512                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3513                 if (ap->rxconfig & ANEG_CFG_PS2)
3514                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3515                 if (ap->rxconfig & ANEG_CFG_RF1)
3516                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3517                 if (ap->rxconfig & ANEG_CFG_RF2)
3518                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3519                 if (ap->rxconfig & ANEG_CFG_NP)
3520                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3521
3522                 ap->link_time = ap->cur_time;
3523
3524                 ap->flags ^= (MR_TOGGLE_TX);
3525                 if (ap->rxconfig & 0x0008)
3526                         ap->flags |= MR_TOGGLE_RX;
3527                 if (ap->rxconfig & ANEG_CFG_NP)
3528                         ap->flags |= MR_NP_RX;
3529                 ap->flags |= MR_PAGE_RX;
3530
3531                 ap->state = ANEG_STATE_COMPLETE_ACK;
3532                 ret = ANEG_TIMER_ENAB;
3533                 break;
3534
3535         case ANEG_STATE_COMPLETE_ACK:
3536                 if (ap->ability_match != 0 &&
3537                     ap->rxconfig == 0) {
3538                         ap->state = ANEG_STATE_AN_ENABLE;
3539                         break;
3540                 }
3541                 delta = ap->cur_time - ap->link_time;
3542                 if (delta > ANEG_STATE_SETTLE_TIME) {
3543                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3544                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3545                         } else {
3546                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3547                                     !(ap->flags & MR_NP_RX)) {
3548                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3549                                 } else {
3550                                         ret = ANEG_FAILED;
3551                                 }
3552                         }
3553                 }
3554                 break;
3555
3556         case ANEG_STATE_IDLE_DETECT_INIT:
3557                 ap->link_time = ap->cur_time;
3558                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3559                 tw32_f(MAC_MODE, tp->mac_mode);
3560                 udelay(40);
3561
3562                 ap->state = ANEG_STATE_IDLE_DETECT;
3563                 ret = ANEG_TIMER_ENAB;
3564                 break;
3565
3566         case ANEG_STATE_IDLE_DETECT:
3567                 if (ap->ability_match != 0 &&
3568                     ap->rxconfig == 0) {
3569                         ap->state = ANEG_STATE_AN_ENABLE;
3570                         break;
3571                 }
3572                 delta = ap->cur_time - ap->link_time;
3573                 if (delta > ANEG_STATE_SETTLE_TIME) {
3574                         /* XXX another gem from the Broadcom driver :( */
3575                         ap->state = ANEG_STATE_LINK_OK;
3576                 }
3577                 break;
3578
3579         case ANEG_STATE_LINK_OK:
3580                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3581                 ret = ANEG_DONE;
3582                 break;
3583
3584         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3585                 /* ??? unimplemented */
3586                 break;
3587
3588         case ANEG_STATE_NEXT_PAGE_WAIT:
3589                 /* ??? unimplemented */
3590                 break;
3591
3592         default:
3593                 ret = ANEG_FAILED;
3594                 break;
3595         }
3596
3597         return ret;
3598 }
3599
3600 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3601 {
3602         int res = 0;
3603         struct tg3_fiber_aneginfo aninfo;
3604         int status = ANEG_FAILED;
3605         unsigned int tick;
3606         u32 tmp;
3607
3608         tw32_f(MAC_TX_AUTO_NEG, 0);
3609
3610         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3611         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3612         udelay(40);
3613
3614         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3615         udelay(40);
3616
3617         memset(&aninfo, 0, sizeof(aninfo));
3618         aninfo.flags |= MR_AN_ENABLE;
3619         aninfo.state = ANEG_STATE_UNKNOWN;
3620         aninfo.cur_time = 0;
3621         tick = 0;
3622         while (++tick < 195000) {
3623                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3624                 if (status == ANEG_DONE || status == ANEG_FAILED)
3625                         break;
3626
3627                 udelay(1);
3628         }
3629
3630         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3631         tw32_f(MAC_MODE, tp->mac_mode);
3632         udelay(40);
3633
3634         *txflags = aninfo.txconfig;
3635         *rxflags = aninfo.flags;
3636
3637         if (status == ANEG_DONE &&
3638             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3639                              MR_LP_ADV_FULL_DUPLEX)))
3640                 res = 1;
3641
3642         return res;
3643 }
3644
3645 static void tg3_init_bcm8002(struct tg3 *tp)
3646 {
3647         u32 mac_status = tr32(MAC_STATUS);
3648         int i;
3649
3650         /* Reset when initting first time or we have a link. */
3651         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3652             !(mac_status & MAC_STATUS_PCS_SYNCED))
3653                 return;
3654
3655         /* Set PLL lock range. */
3656         tg3_writephy(tp, 0x16, 0x8007);
3657
3658         /* SW reset */
3659         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3660
3661         /* Wait for reset to complete. */
3662         /* XXX schedule_timeout() ... */
3663         for (i = 0; i < 500; i++)
3664                 udelay(10);
3665
3666         /* Config mode; select PMA/Ch 1 regs. */
3667         tg3_writephy(tp, 0x10, 0x8411);
3668
3669         /* Enable auto-lock and comdet, select txclk for tx. */
3670         tg3_writephy(tp, 0x11, 0x0a10);
3671
3672         tg3_writephy(tp, 0x18, 0x00a0);
3673         tg3_writephy(tp, 0x16, 0x41ff);
3674
3675         /* Assert and deassert POR. */
3676         tg3_writephy(tp, 0x13, 0x0400);
3677         udelay(40);
3678         tg3_writephy(tp, 0x13, 0x0000);
3679
3680         tg3_writephy(tp, 0x11, 0x0a50);
3681         udelay(40);
3682         tg3_writephy(tp, 0x11, 0x0a10);
3683
3684         /* Wait for signal to stabilize */
3685         /* XXX schedule_timeout() ... */
3686         for (i = 0; i < 15000; i++)
3687                 udelay(10);
3688
3689         /* Deselect the channel register so we can read the PHYID
3690          * later.
3691          */
3692         tg3_writephy(tp, 0x10, 0x8011);
3693 }
3694
3695 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3696 {
3697         u16 flowctrl;
3698         u32 sg_dig_ctrl, sg_dig_status;
3699         u32 serdes_cfg, expected_sg_dig_ctrl;
3700         int workaround, port_a;
3701         int current_link_up;
3702
3703         serdes_cfg = 0;
3704         expected_sg_dig_ctrl = 0;
3705         workaround = 0;
3706         port_a = 1;
3707         current_link_up = 0;
3708
3709         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3710             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3711                 workaround = 1;
3712                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3713                         port_a = 0;
3714
3715                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3716                 /* preserve bits 20-23 for voltage regulator */
3717                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3718         }
3719
3720         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3721
3722         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3723                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3724                         if (workaround) {
3725                                 u32 val = serdes_cfg;
3726
3727                                 if (port_a)
3728                                         val |= 0xc010000;
3729                                 else
3730                                         val |= 0x4010000;
3731                                 tw32_f(MAC_SERDES_CFG, val);
3732                         }
3733
3734                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3735                 }
3736                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3737                         tg3_setup_flow_control(tp, 0, 0);
3738                         current_link_up = 1;
3739                 }
3740                 goto out;
3741         }
3742
3743         /* Want auto-negotiation.  */
3744         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3745
3746         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3747         if (flowctrl & ADVERTISE_1000XPAUSE)
3748                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3749         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3750                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3751
3752         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3753                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3754                     tp->serdes_counter &&
3755                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3756                                     MAC_STATUS_RCVD_CFG)) ==
3757                      MAC_STATUS_PCS_SYNCED)) {
3758                         tp->serdes_counter--;
3759                         current_link_up = 1;
3760                         goto out;
3761                 }
3762 restart_autoneg:
3763                 if (workaround)
3764                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3765                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3766                 udelay(5);
3767                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3768
3769                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3770                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3771         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3772                                  MAC_STATUS_SIGNAL_DET)) {
3773                 sg_dig_status = tr32(SG_DIG_STATUS);
3774                 mac_status = tr32(MAC_STATUS);
3775
3776                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3777                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3778                         u32 local_adv = 0, remote_adv = 0;
3779
3780                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3781                                 local_adv |= ADVERTISE_1000XPAUSE;
3782                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3783                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3784
3785                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3786                                 remote_adv |= LPA_1000XPAUSE;
3787                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3788                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3789
3790                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3791                         current_link_up = 1;
3792                         tp->serdes_counter = 0;
3793                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3794                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3795                         if (tp->serdes_counter)
3796                                 tp->serdes_counter--;
3797                         else {
3798                                 if (workaround) {
3799                                         u32 val = serdes_cfg;
3800
3801                                         if (port_a)
3802                                                 val |= 0xc010000;
3803                                         else
3804                                                 val |= 0x4010000;
3805
3806                                         tw32_f(MAC_SERDES_CFG, val);
3807                                 }
3808
3809                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3810                                 udelay(40);
3811
3812                                 /* Link parallel detection - link is up */
3813                                 /* only if we have PCS_SYNC and not */
3814                                 /* receiving config code words */
3815                                 mac_status = tr32(MAC_STATUS);
3816                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3817                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3818                                         tg3_setup_flow_control(tp, 0, 0);
3819                                         current_link_up = 1;
3820                                         tp->tg3_flags2 |=
3821                                                 TG3_FLG2_PARALLEL_DETECT;
3822                                         tp->serdes_counter =
3823                                                 SERDES_PARALLEL_DET_TIMEOUT;
3824                                 } else
3825                                         goto restart_autoneg;
3826                         }
3827                 }
3828         } else {
3829                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3830                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3831         }
3832
3833 out:
3834         return current_link_up;
3835 }
3836
3837 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3838 {
3839         int current_link_up = 0;
3840
3841         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3842                 goto out;
3843
3844         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3845                 u32 txflags, rxflags;
3846                 int i;
3847
3848                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3849                         u32 local_adv = 0, remote_adv = 0;
3850
3851                         if (txflags & ANEG_CFG_PS1)
3852                                 local_adv |= ADVERTISE_1000XPAUSE;
3853                         if (txflags & ANEG_CFG_PS2)
3854                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3855
3856                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3857                                 remote_adv |= LPA_1000XPAUSE;
3858                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3859                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3860
3861                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3862
3863                         current_link_up = 1;
3864                 }
3865                 for (i = 0; i < 30; i++) {
3866                         udelay(20);
3867                         tw32_f(MAC_STATUS,
3868                                (MAC_STATUS_SYNC_CHANGED |
3869                                 MAC_STATUS_CFG_CHANGED));
3870                         udelay(40);
3871                         if ((tr32(MAC_STATUS) &
3872                              (MAC_STATUS_SYNC_CHANGED |
3873                               MAC_STATUS_CFG_CHANGED)) == 0)
3874                                 break;
3875                 }
3876
3877                 mac_status = tr32(MAC_STATUS);
3878                 if (current_link_up == 0 &&
3879                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3880                     !(mac_status & MAC_STATUS_RCVD_CFG))
3881                         current_link_up = 1;
3882         } else {
3883                 tg3_setup_flow_control(tp, 0, 0);
3884
3885                 /* Forcing 1000FD link up. */
3886                 current_link_up = 1;
3887
3888                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3889                 udelay(40);
3890
3891                 tw32_f(MAC_MODE, tp->mac_mode);
3892                 udelay(40);
3893         }
3894
3895 out:
3896         return current_link_up;
3897 }
3898
3899 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3900 {
3901         u32 orig_pause_cfg;
3902         u16 orig_active_speed;
3903         u8 orig_active_duplex;
3904         u32 mac_status;
3905         int current_link_up;
3906         int i;
3907
3908         orig_pause_cfg = tp->link_config.active_flowctrl;
3909         orig_active_speed = tp->link_config.active_speed;
3910         orig_active_duplex = tp->link_config.active_duplex;
3911
3912         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3913             netif_carrier_ok(tp->dev) &&
3914             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3915                 mac_status = tr32(MAC_STATUS);
3916                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3917                                MAC_STATUS_SIGNAL_DET |
3918                                MAC_STATUS_CFG_CHANGED |
3919                                MAC_STATUS_RCVD_CFG);
3920                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3921                                    MAC_STATUS_SIGNAL_DET)) {
3922                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3923                                             MAC_STATUS_CFG_CHANGED));
3924                         return 0;
3925                 }
3926         }
3927
3928         tw32_f(MAC_TX_AUTO_NEG, 0);
3929
3930         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3931         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3932         tw32_f(MAC_MODE, tp->mac_mode);
3933         udelay(40);
3934
3935         if (tp->phy_id == PHY_ID_BCM8002)
3936                 tg3_init_bcm8002(tp);
3937
3938         /* Enable link change event even when serdes polling.  */
3939         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3940         udelay(40);
3941
3942         current_link_up = 0;
3943         mac_status = tr32(MAC_STATUS);
3944
3945         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3946                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3947         else
3948                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3949
3950         tp->napi[0].hw_status->status =
3951                 (SD_STATUS_UPDATED |
3952                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3953
3954         for (i = 0; i < 100; i++) {
3955                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3956                                     MAC_STATUS_CFG_CHANGED));
3957                 udelay(5);
3958                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3959                                          MAC_STATUS_CFG_CHANGED |
3960                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3961                         break;
3962         }
3963
3964         mac_status = tr32(MAC_STATUS);
3965         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3966                 current_link_up = 0;
3967                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3968                     tp->serdes_counter == 0) {
3969                         tw32_f(MAC_MODE, (tp->mac_mode |
3970                                           MAC_MODE_SEND_CONFIGS));
3971                         udelay(1);
3972                         tw32_f(MAC_MODE, tp->mac_mode);
3973                 }
3974         }
3975
3976         if (current_link_up == 1) {
3977                 tp->link_config.active_speed = SPEED_1000;
3978                 tp->link_config.active_duplex = DUPLEX_FULL;
3979                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3980                                     LED_CTRL_LNKLED_OVERRIDE |
3981                                     LED_CTRL_1000MBPS_ON));
3982         } else {
3983                 tp->link_config.active_speed = SPEED_INVALID;
3984                 tp->link_config.active_duplex = DUPLEX_INVALID;
3985                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3986                                     LED_CTRL_LNKLED_OVERRIDE |
3987                                     LED_CTRL_TRAFFIC_OVERRIDE));
3988         }
3989
3990         if (current_link_up != netif_carrier_ok(tp->dev)) {
3991                 if (current_link_up)
3992                         netif_carrier_on(tp->dev);
3993                 else
3994                         netif_carrier_off(tp->dev);
3995                 tg3_link_report(tp);
3996         } else {
3997                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3998                 if (orig_pause_cfg != now_pause_cfg ||
3999                     orig_active_speed != tp->link_config.active_speed ||
4000                     orig_active_duplex != tp->link_config.active_duplex)
4001                         tg3_link_report(tp);
4002         }
4003
4004         return 0;
4005 }
4006
4007 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4008 {
4009         int current_link_up, err = 0;
4010         u32 bmsr, bmcr;
4011         u16 current_speed;
4012         u8 current_duplex;
4013         u32 local_adv, remote_adv;
4014
4015         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4016         tw32_f(MAC_MODE, tp->mac_mode);
4017         udelay(40);
4018
4019         tw32(MAC_EVENT, 0);
4020
4021         tw32_f(MAC_STATUS,
4022              (MAC_STATUS_SYNC_CHANGED |
4023               MAC_STATUS_CFG_CHANGED |
4024               MAC_STATUS_MI_COMPLETION |
4025               MAC_STATUS_LNKSTATE_CHANGED));
4026         udelay(40);
4027
4028         if (force_reset)
4029                 tg3_phy_reset(tp);
4030
4031         current_link_up = 0;
4032         current_speed = SPEED_INVALID;
4033         current_duplex = DUPLEX_INVALID;
4034
4035         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4036         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4037         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4038                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4039                         bmsr |= BMSR_LSTATUS;
4040                 else
4041                         bmsr &= ~BMSR_LSTATUS;
4042         }
4043
4044         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4045
4046         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4047             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4048                 /* do nothing, just check for link up at the end */
4049         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4050                 u32 adv, new_adv;
4051
4052                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4053                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4054                                   ADVERTISE_1000XPAUSE |
4055                                   ADVERTISE_1000XPSE_ASYM |
4056                                   ADVERTISE_SLCT);
4057
4058                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4059
4060                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4061                         new_adv |= ADVERTISE_1000XHALF;
4062                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4063                         new_adv |= ADVERTISE_1000XFULL;
4064
4065                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4066                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4067                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4068                         tg3_writephy(tp, MII_BMCR, bmcr);
4069
4070                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4071                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4072                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4073
4074                         return err;
4075                 }
4076         } else {
4077                 u32 new_bmcr;
4078
4079                 bmcr &= ~BMCR_SPEED1000;
4080                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4081
4082                 if (tp->link_config.duplex == DUPLEX_FULL)
4083                         new_bmcr |= BMCR_FULLDPLX;
4084
4085                 if (new_bmcr != bmcr) {
4086                         /* BMCR_SPEED1000 is a reserved bit that needs
4087                          * to be set on write.
4088                          */
4089                         new_bmcr |= BMCR_SPEED1000;
4090
4091                         /* Force a linkdown */
4092                         if (netif_carrier_ok(tp->dev)) {
4093                                 u32 adv;
4094
4095                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4096                                 adv &= ~(ADVERTISE_1000XFULL |
4097                                          ADVERTISE_1000XHALF |
4098                                          ADVERTISE_SLCT);
4099                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4100                                 tg3_writephy(tp, MII_BMCR, bmcr |
4101                                                            BMCR_ANRESTART |
4102                                                            BMCR_ANENABLE);
4103                                 udelay(10);
4104                                 netif_carrier_off(tp->dev);
4105                         }
4106                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4107                         bmcr = new_bmcr;
4108                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4109                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4111                             ASIC_REV_5714) {
4112                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4113                                         bmsr |= BMSR_LSTATUS;
4114                                 else
4115                                         bmsr &= ~BMSR_LSTATUS;
4116                         }
4117                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4118                 }
4119         }
4120
4121         if (bmsr & BMSR_LSTATUS) {
4122                 current_speed = SPEED_1000;
4123                 current_link_up = 1;
4124                 if (bmcr & BMCR_FULLDPLX)
4125                         current_duplex = DUPLEX_FULL;
4126                 else
4127                         current_duplex = DUPLEX_HALF;
4128
4129                 local_adv = 0;
4130                 remote_adv = 0;
4131
4132                 if (bmcr & BMCR_ANENABLE) {
4133                         u32 common;
4134
4135                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4136                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4137                         common = local_adv & remote_adv;
4138                         if (common & (ADVERTISE_1000XHALF |
4139                                       ADVERTISE_1000XFULL)) {
4140                                 if (common & ADVERTISE_1000XFULL)
4141                                         current_duplex = DUPLEX_FULL;
4142                                 else
4143                                         current_duplex = DUPLEX_HALF;
4144                         }
4145                         else
4146                                 current_link_up = 0;
4147                 }
4148         }
4149
4150         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4151                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4152
4153         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4154         if (tp->link_config.active_duplex == DUPLEX_HALF)
4155                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4156
4157         tw32_f(MAC_MODE, tp->mac_mode);
4158         udelay(40);
4159
4160         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4161
4162         tp->link_config.active_speed = current_speed;
4163         tp->link_config.active_duplex = current_duplex;
4164
4165         if (current_link_up != netif_carrier_ok(tp->dev)) {
4166                 if (current_link_up)
4167                         netif_carrier_on(tp->dev);
4168                 else {
4169                         netif_carrier_off(tp->dev);
4170                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4171                 }
4172                 tg3_link_report(tp);
4173         }
4174         return err;
4175 }
4176
4177 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4178 {
4179         if (tp->serdes_counter) {
4180                 /* Give autoneg time to complete. */
4181                 tp->serdes_counter--;
4182                 return;
4183         }
4184         if (!netif_carrier_ok(tp->dev) &&
4185             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4186                 u32 bmcr;
4187
4188                 tg3_readphy(tp, MII_BMCR, &bmcr);
4189                 if (bmcr & BMCR_ANENABLE) {
4190                         u32 phy1, phy2;
4191
4192                         /* Select shadow register 0x1f */
4193                         tg3_writephy(tp, 0x1c, 0x7c00);
4194                         tg3_readphy(tp, 0x1c, &phy1);
4195
4196                         /* Select expansion interrupt status register */
4197                         tg3_writephy(tp, 0x17, 0x0f01);
4198                         tg3_readphy(tp, 0x15, &phy2);
4199                         tg3_readphy(tp, 0x15, &phy2);
4200
4201                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4202                                 /* We have signal detect and not receiving
4203                                  * config code words, link is up by parallel
4204                                  * detection.
4205                                  */
4206
4207                                 bmcr &= ~BMCR_ANENABLE;
4208                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4209                                 tg3_writephy(tp, MII_BMCR, bmcr);
4210                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4211                         }
4212                 }
4213         }
4214         else if (netif_carrier_ok(tp->dev) &&
4215                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4216                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4217                 u32 phy2;
4218
4219                 /* Select expansion interrupt status register */
4220                 tg3_writephy(tp, 0x17, 0x0f01);
4221                 tg3_readphy(tp, 0x15, &phy2);
4222                 if (phy2 & 0x20) {
4223                         u32 bmcr;
4224
4225                         /* Config code words received, turn on autoneg. */
4226                         tg3_readphy(tp, MII_BMCR, &bmcr);
4227                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4228
4229                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4230
4231                 }
4232         }
4233 }
4234
4235 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4236 {
4237         int err;
4238
4239         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4240                 err = tg3_setup_fiber_phy(tp, force_reset);
4241         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4242                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4243         } else {
4244                 err = tg3_setup_copper_phy(tp, force_reset);
4245         }
4246
4247         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4248                 u32 val, scale;
4249
4250                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4251                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4252                         scale = 65;
4253                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4254                         scale = 6;
4255                 else
4256                         scale = 12;
4257
4258                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4259                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4260                 tw32(GRC_MISC_CFG, val);
4261         }
4262
4263         if (tp->link_config.active_speed == SPEED_1000 &&
4264             tp->link_config.active_duplex == DUPLEX_HALF)
4265                 tw32(MAC_TX_LENGTHS,
4266                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4267                       (6 << TX_LENGTHS_IPG_SHIFT) |
4268                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4269         else
4270                 tw32(MAC_TX_LENGTHS,
4271                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4272                       (6 << TX_LENGTHS_IPG_SHIFT) |
4273                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4274
4275         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4276                 if (netif_carrier_ok(tp->dev)) {
4277                         tw32(HOSTCC_STAT_COAL_TICKS,
4278                              tp->coal.stats_block_coalesce_usecs);
4279                 } else {
4280                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4281                 }
4282         }
4283
4284         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4285                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4286                 if (!netif_carrier_ok(tp->dev))
4287                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4288                               tp->pwrmgmt_thresh;
4289                 else
4290                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4291                 tw32(PCIE_PWR_MGMT_THRESH, val);
4292         }
4293
4294         return err;
4295 }
4296
4297 /* This is called whenever we suspect that the system chipset is re-
4298  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4299  * is bogus tx completions. We try to recover by setting the
4300  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4301  * in the workqueue.
4302  */
4303 static void tg3_tx_recover(struct tg3 *tp)
4304 {
4305         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4306                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4307
4308         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4309                "mapped I/O cycles to the network device, attempting to "
4310                "recover. Please report the problem to the driver maintainer "
4311                "and include system chipset information.\n", tp->dev->name);
4312
4313         spin_lock(&tp->lock);
4314         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4315         spin_unlock(&tp->lock);
4316 }
4317
4318 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4319 {
4320         smp_mb();
4321         return tnapi->tx_pending -
4322                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4323 }
4324
4325 /* Tigon3 never reports partial packet sends.  So we do not
4326  * need special logic to handle SKBs that have not had all
4327  * of their frags sent yet, like SunGEM does.
4328  */
4329 static void tg3_tx(struct tg3_napi *tnapi)
4330 {
4331         struct tg3 *tp = tnapi->tp;
4332         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4333         u32 sw_idx = tnapi->tx_cons;
4334         struct netdev_queue *txq;
4335         int index = tnapi - tp->napi;
4336
4337         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4338                 index--;
4339
4340         txq = netdev_get_tx_queue(tp->dev, index);
4341
4342         while (sw_idx != hw_idx) {
4343                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4344                 struct sk_buff *skb = ri->skb;
4345                 int i, tx_bug = 0;
4346
4347                 if (unlikely(skb == NULL)) {
4348                         tg3_tx_recover(tp);
4349                         return;
4350                 }
4351
4352                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4353
4354                 ri->skb = NULL;
4355
4356                 sw_idx = NEXT_TX(sw_idx);
4357
4358                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4359                         ri = &tnapi->tx_buffers[sw_idx];
4360                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4361                                 tx_bug = 1;
4362                         sw_idx = NEXT_TX(sw_idx);
4363                 }
4364
4365                 dev_kfree_skb(skb);
4366
4367                 if (unlikely(tx_bug)) {
4368                         tg3_tx_recover(tp);
4369                         return;
4370                 }
4371         }
4372
4373         tnapi->tx_cons = sw_idx;
4374
4375         /* Need to make the tx_cons update visible to tg3_start_xmit()
4376          * before checking for netif_queue_stopped().  Without the
4377          * memory barrier, there is a small possibility that tg3_start_xmit()
4378          * will miss it and cause the queue to be stopped forever.
4379          */
4380         smp_mb();
4381
4382         if (unlikely(netif_tx_queue_stopped(txq) &&
4383                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4384                 __netif_tx_lock(txq, smp_processor_id());
4385                 if (netif_tx_queue_stopped(txq) &&
4386                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4387                         netif_tx_wake_queue(txq);
4388                 __netif_tx_unlock(txq);
4389         }
4390 }
4391
4392 /* Returns size of skb allocated or < 0 on error.
4393  *
4394  * We only need to fill in the address because the other members
4395  * of the RX descriptor are invariant, see tg3_init_rings.
4396  *
4397  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4398  * posting buffers we only dirty the first cache line of the RX
4399  * descriptor (containing the address).  Whereas for the RX status
4400  * buffers the cpu only reads the last cacheline of the RX descriptor
4401  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4402  */
4403 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4404                             int src_idx, u32 dest_idx_unmasked)
4405 {
4406         struct tg3 *tp = tnapi->tp;
4407         struct tg3_rx_buffer_desc *desc;
4408         struct ring_info *map, *src_map;
4409         struct sk_buff *skb;
4410         dma_addr_t mapping;
4411         int skb_size, dest_idx;
4412         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4413
4414         src_map = NULL;
4415         switch (opaque_key) {
4416         case RXD_OPAQUE_RING_STD:
4417                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4418                 desc = &tpr->rx_std[dest_idx];
4419                 map = &tpr->rx_std_buffers[dest_idx];
4420                 if (src_idx >= 0)
4421                         src_map = &tpr->rx_std_buffers[src_idx];
4422                 skb_size = tp->rx_pkt_map_sz;
4423                 break;
4424
4425         case RXD_OPAQUE_RING_JUMBO:
4426                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4427                 desc = &tpr->rx_jmb[dest_idx].std;
4428                 map = &tpr->rx_jmb_buffers[dest_idx];
4429                 if (src_idx >= 0)
4430                         src_map = &tpr->rx_jmb_buffers[src_idx];
4431                 skb_size = TG3_RX_JMB_MAP_SZ;
4432                 break;
4433
4434         default:
4435                 return -EINVAL;
4436         }
4437
4438         /* Do not overwrite any of the map or rp information
4439          * until we are sure we can commit to a new buffer.
4440          *
4441          * Callers depend upon this behavior and assume that
4442          * we leave everything unchanged if we fail.
4443          */
4444         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4445         if (skb == NULL)
4446                 return -ENOMEM;
4447
4448         skb_reserve(skb, tp->rx_offset);
4449
4450         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4451                                  PCI_DMA_FROMDEVICE);
4452         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4453                 dev_kfree_skb(skb);
4454                 return -EIO;
4455         }
4456
4457         map->skb = skb;
4458         pci_unmap_addr_set(map, mapping, mapping);
4459
4460         if (src_map != NULL)
4461                 src_map->skb = NULL;
4462
4463         desc->addr_hi = ((u64)mapping >> 32);
4464         desc->addr_lo = ((u64)mapping & 0xffffffff);
4465
4466         return skb_size;
4467 }
4468
4469 /* We only need to move over in the address because the other
4470  * members of the RX descriptor are invariant.  See notes above
4471  * tg3_alloc_rx_skb for full details.
4472  */
4473 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4474                            int src_idx, u32 dest_idx_unmasked)
4475 {
4476         struct tg3 *tp = tnapi->tp;
4477         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4478         struct ring_info *src_map, *dest_map;
4479         int dest_idx;
4480         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4481
4482         switch (opaque_key) {
4483         case RXD_OPAQUE_RING_STD:
4484                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4485                 dest_desc = &tpr->rx_std[dest_idx];
4486                 dest_map = &tpr->rx_std_buffers[dest_idx];
4487                 src_desc = &tpr->rx_std[src_idx];
4488                 src_map = &tpr->rx_std_buffers[src_idx];
4489                 break;
4490
4491         case RXD_OPAQUE_RING_JUMBO:
4492                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4493                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4494                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4495                 src_desc = &tpr->rx_jmb[src_idx].std;
4496                 src_map = &tpr->rx_jmb_buffers[src_idx];
4497                 break;
4498
4499         default:
4500                 return;
4501         }
4502
4503         dest_map->skb = src_map->skb;
4504         pci_unmap_addr_set(dest_map, mapping,
4505                            pci_unmap_addr(src_map, mapping));
4506         dest_desc->addr_hi = src_desc->addr_hi;
4507         dest_desc->addr_lo = src_desc->addr_lo;
4508
4509         src_map->skb = NULL;
4510 }
4511
4512 /* The RX ring scheme is composed of multiple rings which post fresh
4513  * buffers to the chip, and one special ring the chip uses to report
4514  * status back to the host.
4515  *
4516  * The special ring reports the status of received packets to the
4517  * host.  The chip does not write into the original descriptor the
4518  * RX buffer was obtained from.  The chip simply takes the original
4519  * descriptor as provided by the host, updates the status and length
4520  * field, then writes this into the next status ring entry.
4521  *
4522  * Each ring the host uses to post buffers to the chip is described
4523  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4524  * it is first placed into the on-chip ram.  When the packet's length
4525  * is known, it walks down the TG3_BDINFO entries to select the ring.
4526  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4527  * which is within the range of the new packet's length is chosen.
4528  *
4529  * The "separate ring for rx status" scheme may sound queer, but it makes
4530  * sense from a cache coherency perspective.  If only the host writes
4531  * to the buffer post rings, and only the chip writes to the rx status
4532  * rings, then cache lines never move beyond shared-modified state.
4533  * If both the host and chip were to write into the same ring, cache line
4534  * eviction could occur since both entities want it in an exclusive state.
4535  */
4536 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4537 {
4538         struct tg3 *tp = tnapi->tp;
4539         u32 work_mask, rx_std_posted = 0;
4540         u32 sw_idx = tnapi->rx_rcb_ptr;
4541         u16 hw_idx;
4542         int received;
4543         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4544
4545         hw_idx = *(tnapi->rx_rcb_prod_idx);
4546         /*
4547          * We need to order the read of hw_idx and the read of
4548          * the opaque cookie.
4549          */
4550         rmb();
4551         work_mask = 0;
4552         received = 0;
4553         while (sw_idx != hw_idx && budget > 0) {
4554                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4555                 unsigned int len;
4556                 struct sk_buff *skb;
4557                 dma_addr_t dma_addr;
4558                 u32 opaque_key, desc_idx, *post_ptr;
4559
4560                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4561                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4562                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4563                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4564                         dma_addr = pci_unmap_addr(ri, mapping);
4565                         skb = ri->skb;
4566                         post_ptr = &tpr->rx_std_ptr;
4567                         rx_std_posted++;
4568                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4569                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4570                         dma_addr = pci_unmap_addr(ri, mapping);
4571                         skb = ri->skb;
4572                         post_ptr = &tpr->rx_jmb_ptr;
4573                 } else
4574                         goto next_pkt_nopost;
4575
4576                 work_mask |= opaque_key;
4577
4578                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4579                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4580                 drop_it:
4581                         tg3_recycle_rx(tnapi, opaque_key,
4582                                        desc_idx, *post_ptr);
4583                 drop_it_no_recycle:
4584                         /* Other statistics kept track of by card. */
4585                         tp->net_stats.rx_dropped++;
4586                         goto next_pkt;
4587                 }
4588
4589                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4590                       ETH_FCS_LEN;
4591
4592                 if (len > RX_COPY_THRESHOLD
4593                         && tp->rx_offset == NET_IP_ALIGN
4594                         /* rx_offset will likely not equal NET_IP_ALIGN
4595                          * if this is a 5701 card running in PCI-X mode
4596                          * [see tg3_get_invariants()]
4597                          */
4598                 ) {
4599                         int skb_size;
4600
4601                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4602                                                     desc_idx, *post_ptr);
4603                         if (skb_size < 0)
4604                                 goto drop_it;
4605
4606                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4607                                          PCI_DMA_FROMDEVICE);
4608
4609                         skb_put(skb, len);
4610                 } else {
4611                         struct sk_buff *copy_skb;
4612
4613                         tg3_recycle_rx(tnapi, opaque_key,
4614                                        desc_idx, *post_ptr);
4615
4616                         copy_skb = netdev_alloc_skb(tp->dev,
4617                                                     len + TG3_RAW_IP_ALIGN);
4618                         if (copy_skb == NULL)
4619                                 goto drop_it_no_recycle;
4620
4621                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4622                         skb_put(copy_skb, len);
4623                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4624                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4625                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4626
4627                         /* We'll reuse the original ring buffer. */
4628                         skb = copy_skb;
4629                 }
4630
4631                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4632                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4633                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4634                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4635                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4636                 else
4637                         skb->ip_summed = CHECKSUM_NONE;
4638
4639                 skb->protocol = eth_type_trans(skb, tp->dev);
4640
4641                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4642                     skb->protocol != htons(ETH_P_8021Q)) {
4643                         dev_kfree_skb(skb);
4644                         goto next_pkt;
4645                 }
4646
4647 #if TG3_VLAN_TAG_USED
4648                 if (tp->vlgrp != NULL &&
4649                     desc->type_flags & RXD_FLAG_VLAN) {
4650                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4651                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4652                 } else
4653 #endif
4654                         napi_gro_receive(&tnapi->napi, skb);
4655
4656                 received++;
4657                 budget--;
4658
4659 next_pkt:
4660                 (*post_ptr)++;
4661
4662                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4663                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4664
4665                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4666                                      TG3_64BIT_REG_LOW, idx);
4667                         work_mask &= ~RXD_OPAQUE_RING_STD;
4668                         rx_std_posted = 0;
4669                 }
4670 next_pkt_nopost:
4671                 sw_idx++;
4672                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4673
4674                 /* Refresh hw_idx to see if there is new work */
4675                 if (sw_idx == hw_idx) {
4676                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4677                         rmb();
4678                 }
4679         }
4680
4681         /* ACK the status ring. */
4682         tnapi->rx_rcb_ptr = sw_idx;
4683         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4684
4685         /* Refill RX ring(s). */
4686         if (work_mask & RXD_OPAQUE_RING_STD) {
4687                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4688                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4689                              sw_idx);
4690         }
4691         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4692                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4693                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4694                              sw_idx);
4695         }
4696         mmiowb();
4697
4698         return received;
4699 }
4700
4701 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4702 {
4703         struct tg3 *tp = tnapi->tp;
4704         struct tg3_hw_status *sblk = tnapi->hw_status;
4705
4706         /* handle link change and other phy events */
4707         if (!(tp->tg3_flags &
4708               (TG3_FLAG_USE_LINKCHG_REG |
4709                TG3_FLAG_POLL_SERDES))) {
4710                 if (sblk->status & SD_STATUS_LINK_CHG) {
4711                         sblk->status = SD_STATUS_UPDATED |
4712                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4713                         spin_lock(&tp->lock);
4714                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4715                                 tw32_f(MAC_STATUS,
4716                                      (MAC_STATUS_SYNC_CHANGED |
4717                                       MAC_STATUS_CFG_CHANGED |
4718                                       MAC_STATUS_MI_COMPLETION |
4719                                       MAC_STATUS_LNKSTATE_CHANGED));
4720                                 udelay(40);
4721                         } else
4722                                 tg3_setup_phy(tp, 0);
4723                         spin_unlock(&tp->lock);
4724                 }
4725         }
4726
4727         /* run TX completion thread */
4728         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4729                 tg3_tx(tnapi);
4730                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4731                         return work_done;
4732         }
4733
4734         /* run RX thread, within the bounds set by NAPI.
4735          * All RX "locking" is done by ensuring outside
4736          * code synchronizes with tg3->napi.poll()
4737          */
4738         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4739                 work_done += tg3_rx(tnapi, budget - work_done);
4740
4741         return work_done;
4742 }
4743
4744 static int tg3_poll(struct napi_struct *napi, int budget)
4745 {
4746         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4747         struct tg3 *tp = tnapi->tp;
4748         int work_done = 0;
4749         struct tg3_hw_status *sblk = tnapi->hw_status;
4750
4751         while (1) {
4752                 work_done = tg3_poll_work(tnapi, work_done, budget);
4753
4754                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4755                         goto tx_recovery;
4756
4757                 if (unlikely(work_done >= budget))
4758                         break;
4759
4760                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4761                         /* tp->last_tag is used in tg3_int_reenable() below
4762                          * to tell the hw how much work has been processed,
4763                          * so we must read it before checking for more work.
4764                          */
4765                         tnapi->last_tag = sblk->status_tag;
4766                         tnapi->last_irq_tag = tnapi->last_tag;
4767                         rmb();
4768                 } else
4769                         sblk->status &= ~SD_STATUS_UPDATED;
4770
4771                 if (likely(!tg3_has_work(tnapi))) {
4772                         napi_complete(napi);
4773                         tg3_int_reenable(tnapi);
4774                         break;
4775                 }
4776         }
4777
4778         return work_done;
4779
4780 tx_recovery:
4781         /* work_done is guaranteed to be less than budget. */
4782         napi_complete(napi);
4783         schedule_work(&tp->reset_task);
4784         return work_done;
4785 }
4786
4787 static void tg3_irq_quiesce(struct tg3 *tp)
4788 {
4789         int i;
4790
4791         BUG_ON(tp->irq_sync);
4792
4793         tp->irq_sync = 1;
4794         smp_mb();
4795
4796         for (i = 0; i < tp->irq_cnt; i++)
4797                 synchronize_irq(tp->napi[i].irq_vec);
4798 }
4799
4800 static inline int tg3_irq_sync(struct tg3 *tp)
4801 {
4802         return tp->irq_sync;
4803 }
4804
4805 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4806  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4807  * with as well.  Most of the time, this is not necessary except when
4808  * shutting down the device.
4809  */
4810 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4811 {
4812         spin_lock_bh(&tp->lock);
4813         if (irq_sync)
4814                 tg3_irq_quiesce(tp);
4815 }
4816
4817 static inline void tg3_full_unlock(struct tg3 *tp)
4818 {
4819         spin_unlock_bh(&tp->lock);
4820 }
4821
4822 /* One-shot MSI handler - Chip automatically disables interrupt
4823  * after sending MSI so driver doesn't have to do it.
4824  */
4825 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4826 {
4827         struct tg3_napi *tnapi = dev_id;
4828         struct tg3 *tp = tnapi->tp;
4829
4830         prefetch(tnapi->hw_status);
4831         if (tnapi->rx_rcb)
4832                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4833
4834         if (likely(!tg3_irq_sync(tp)))
4835                 napi_schedule(&tnapi->napi);
4836
4837         return IRQ_HANDLED;
4838 }
4839
4840 /* MSI ISR - No need to check for interrupt sharing and no need to
4841  * flush status block and interrupt mailbox. PCI ordering rules
4842  * guarantee that MSI will arrive after the status block.
4843  */
4844 static irqreturn_t tg3_msi(int irq, void *dev_id)
4845 {
4846         struct tg3_napi *tnapi = dev_id;
4847         struct tg3 *tp = tnapi->tp;
4848
4849         prefetch(tnapi->hw_status);
4850         if (tnapi->rx_rcb)
4851                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4852         /*
4853          * Writing any value to intr-mbox-0 clears PCI INTA# and
4854          * chip-internal interrupt pending events.
4855          * Writing non-zero to intr-mbox-0 additional tells the
4856          * NIC to stop sending us irqs, engaging "in-intr-handler"
4857          * event coalescing.
4858          */
4859         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4860         if (likely(!tg3_irq_sync(tp)))
4861                 napi_schedule(&tnapi->napi);
4862
4863         return IRQ_RETVAL(1);
4864 }
4865
4866 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4867 {
4868         struct tg3_napi *tnapi = dev_id;
4869         struct tg3 *tp = tnapi->tp;
4870         struct tg3_hw_status *sblk = tnapi->hw_status;
4871         unsigned int handled = 1;
4872
4873         /* In INTx mode, it is possible for the interrupt to arrive at
4874          * the CPU before the status block posted prior to the interrupt.
4875          * Reading the PCI State register will confirm whether the
4876          * interrupt is ours and will flush the status block.
4877          */
4878         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4879                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4880                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4881                         handled = 0;
4882                         goto out;
4883                 }
4884         }
4885
4886         /*
4887          * Writing any value to intr-mbox-0 clears PCI INTA# and
4888          * chip-internal interrupt pending events.
4889          * Writing non-zero to intr-mbox-0 additional tells the
4890          * NIC to stop sending us irqs, engaging "in-intr-handler"
4891          * event coalescing.
4892          *
4893          * Flush the mailbox to de-assert the IRQ immediately to prevent
4894          * spurious interrupts.  The flush impacts performance but
4895          * excessive spurious interrupts can be worse in some cases.
4896          */
4897         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4898         if (tg3_irq_sync(tp))
4899                 goto out;
4900         sblk->status &= ~SD_STATUS_UPDATED;
4901         if (likely(tg3_has_work(tnapi))) {
4902                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4903                 napi_schedule(&tnapi->napi);
4904         } else {
4905                 /* No work, shared interrupt perhaps?  re-enable
4906                  * interrupts, and flush that PCI write
4907                  */
4908                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4909                                0x00000000);
4910         }
4911 out:
4912         return IRQ_RETVAL(handled);
4913 }
4914
4915 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4916 {
4917         struct tg3_napi *tnapi = dev_id;
4918         struct tg3 *tp = tnapi->tp;
4919         struct tg3_hw_status *sblk = tnapi->hw_status;
4920         unsigned int handled = 1;
4921
4922         /* In INTx mode, it is possible for the interrupt to arrive at
4923          * the CPU before the status block posted prior to the interrupt.
4924          * Reading the PCI State register will confirm whether the
4925          * interrupt is ours and will flush the status block.
4926          */
4927         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4928                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4929                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4930                         handled = 0;
4931                         goto out;
4932                 }
4933         }
4934
4935         /*
4936          * writing any value to intr-mbox-0 clears PCI INTA# and
4937          * chip-internal interrupt pending events.
4938          * writing non-zero to intr-mbox-0 additional tells the
4939          * NIC to stop sending us irqs, engaging "in-intr-handler"
4940          * event coalescing.
4941          *
4942          * Flush the mailbox to de-assert the IRQ immediately to prevent
4943          * spurious interrupts.  The flush impacts performance but
4944          * excessive spurious interrupts can be worse in some cases.
4945          */
4946         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4947
4948         /*
4949          * In a shared interrupt configuration, sometimes other devices'
4950          * interrupts will scream.  We record the current status tag here
4951          * so that the above check can report that the screaming interrupts
4952          * are unhandled.  Eventually they will be silenced.
4953          */
4954         tnapi->last_irq_tag = sblk->status_tag;
4955
4956         if (tg3_irq_sync(tp))
4957                 goto out;
4958
4959         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4960
4961         napi_schedule(&tnapi->napi);
4962
4963 out:
4964         return IRQ_RETVAL(handled);
4965 }
4966
4967 /* ISR for interrupt test */
4968 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4969 {
4970         struct tg3_napi *tnapi = dev_id;
4971         struct tg3 *tp = tnapi->tp;
4972         struct tg3_hw_status *sblk = tnapi->hw_status;
4973
4974         if ((sblk->status & SD_STATUS_UPDATED) ||
4975             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4976                 tg3_disable_ints(tp);
4977                 return IRQ_RETVAL(1);
4978         }
4979         return IRQ_RETVAL(0);
4980 }
4981
4982 static int tg3_init_hw(struct tg3 *, int);
4983 static int tg3_halt(struct tg3 *, int, int);
4984
4985 /* Restart hardware after configuration changes, self-test, etc.
4986  * Invoked with tp->lock held.
4987  */
4988 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4989         __releases(tp->lock)
4990         __acquires(tp->lock)
4991 {
4992         int err;
4993
4994         err = tg3_init_hw(tp, reset_phy);
4995         if (err) {
4996                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4997                        "aborting.\n", tp->dev->name);
4998                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4999                 tg3_full_unlock(tp);
5000                 del_timer_sync(&tp->timer);
5001                 tp->irq_sync = 0;
5002                 tg3_napi_enable(tp);
5003                 dev_close(tp->dev);
5004                 tg3_full_lock(tp, 0);
5005         }
5006         return err;
5007 }
5008
5009 #ifdef CONFIG_NET_POLL_CONTROLLER
5010 static void tg3_poll_controller(struct net_device *dev)
5011 {
5012         int i;
5013         struct tg3 *tp = netdev_priv(dev);
5014
5015         for (i = 0; i < tp->irq_cnt; i++)
5016                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5017 }
5018 #endif
5019
5020 static void tg3_reset_task(struct work_struct *work)
5021 {
5022         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5023         int err;
5024         unsigned int restart_timer;
5025
5026         tg3_full_lock(tp, 0);
5027
5028         if (!netif_running(tp->dev)) {
5029                 tg3_full_unlock(tp);
5030                 return;
5031         }
5032
5033         tg3_full_unlock(tp);
5034
5035         tg3_phy_stop(tp);
5036
5037         tg3_netif_stop(tp);
5038
5039         tg3_full_lock(tp, 1);
5040
5041         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5042         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5043
5044         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5045                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5046                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5047                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5048                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5049         }
5050
5051         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5052         err = tg3_init_hw(tp, 1);
5053         if (err)
5054                 goto out;
5055
5056         tg3_netif_start(tp);
5057
5058         if (restart_timer)
5059                 mod_timer(&tp->timer, jiffies + 1);
5060
5061 out:
5062         tg3_full_unlock(tp);
5063
5064         if (!err)
5065                 tg3_phy_start(tp);
5066 }
5067
5068 static void tg3_dump_short_state(struct tg3 *tp)
5069 {
5070         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5071                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5072         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5073                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5074 }
5075
5076 static void tg3_tx_timeout(struct net_device *dev)
5077 {
5078         struct tg3 *tp = netdev_priv(dev);
5079
5080         if (netif_msg_tx_err(tp)) {
5081                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5082                        dev->name);
5083                 tg3_dump_short_state(tp);
5084         }
5085
5086         schedule_work(&tp->reset_task);
5087 }
5088
5089 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5090 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5091 {
5092         u32 base = (u32) mapping & 0xffffffff;
5093
5094         return ((base > 0xffffdcc0) &&
5095                 (base + len + 8 < base));
5096 }
5097
5098 /* Test for DMA addresses > 40-bit */
5099 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5100                                           int len)
5101 {
5102 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5103         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5104                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5105         return 0;
5106 #else
5107         return 0;
5108 #endif
5109 }
5110
5111 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5112
5113 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5114 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5115                                        u32 last_plus_one, u32 *start,
5116                                        u32 base_flags, u32 mss)
5117 {
5118         struct tg3_napi *tnapi = &tp->napi[0];
5119         struct sk_buff *new_skb;
5120         dma_addr_t new_addr = 0;
5121         u32 entry = *start;
5122         int i, ret = 0;
5123
5124         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5125                 new_skb = skb_copy(skb, GFP_ATOMIC);
5126         else {
5127                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5128
5129                 new_skb = skb_copy_expand(skb,
5130                                           skb_headroom(skb) + more_headroom,
5131                                           skb_tailroom(skb), GFP_ATOMIC);
5132         }
5133
5134         if (!new_skb) {
5135                 ret = -1;
5136         } else {
5137                 /* New SKB is guaranteed to be linear. */
5138                 entry = *start;
5139                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5140                 new_addr = skb_shinfo(new_skb)->dma_head;
5141
5142                 /* Make sure new skb does not cross any 4G boundaries.
5143                  * Drop the packet if it does.
5144                  */
5145                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5146                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5147                         if (!ret)
5148                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5149                                               DMA_TO_DEVICE);
5150                         ret = -1;
5151                         dev_kfree_skb(new_skb);
5152                         new_skb = NULL;
5153                 } else {
5154                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5155                                     base_flags, 1 | (mss << 1));
5156                         *start = NEXT_TX(entry);
5157                 }
5158         }
5159
5160         /* Now clean up the sw ring entries. */
5161         i = 0;
5162         while (entry != last_plus_one) {
5163                 if (i == 0)
5164                         tnapi->tx_buffers[entry].skb = new_skb;
5165                 else
5166                         tnapi->tx_buffers[entry].skb = NULL;
5167                 entry = NEXT_TX(entry);
5168                 i++;
5169         }
5170
5171         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5172         dev_kfree_skb(skb);
5173
5174         return ret;
5175 }
5176
5177 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5178                         dma_addr_t mapping, int len, u32 flags,
5179                         u32 mss_and_is_end)
5180 {
5181         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5182         int is_end = (mss_and_is_end & 0x1);
5183         u32 mss = (mss_and_is_end >> 1);
5184         u32 vlan_tag = 0;
5185
5186         if (is_end)
5187                 flags |= TXD_FLAG_END;
5188         if (flags & TXD_FLAG_VLAN) {
5189                 vlan_tag = flags >> 16;
5190                 flags &= 0xffff;
5191         }
5192         vlan_tag |= (mss << TXD_MSS_SHIFT);
5193
5194         txd->addr_hi = ((u64) mapping >> 32);
5195         txd->addr_lo = ((u64) mapping & 0xffffffff);
5196         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5197         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5198 }
5199
5200 /* hard_start_xmit for devices that don't have any bugs and
5201  * support TG3_FLG2_HW_TSO_2 only.
5202  */
5203 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5204                                   struct net_device *dev)
5205 {
5206         struct tg3 *tp = netdev_priv(dev);
5207         u32 len, entry, base_flags, mss;
5208         struct skb_shared_info *sp;
5209         dma_addr_t mapping;
5210         struct tg3_napi *tnapi;
5211         struct netdev_queue *txq;
5212
5213         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5214         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5215         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5216                 tnapi++;
5217
5218         /* We are running in BH disabled context with netif_tx_lock
5219          * and TX reclaim runs via tp->napi.poll inside of a software
5220          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5221          * no IRQ context deadlocks to worry about either.  Rejoice!
5222          */
5223         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5224                 if (!netif_tx_queue_stopped(txq)) {
5225                         netif_tx_stop_queue(txq);
5226
5227                         /* This is a hard error, log it. */
5228                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5229                                "queue awake!\n", dev->name);
5230                 }
5231                 return NETDEV_TX_BUSY;
5232         }
5233
5234         entry = tnapi->tx_prod;
5235         base_flags = 0;
5236         mss = 0;
5237         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5238                 int tcp_opt_len, ip_tcp_len;
5239                 u32 hdrlen;
5240
5241                 if (skb_header_cloned(skb) &&
5242                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5243                         dev_kfree_skb(skb);
5244                         goto out_unlock;
5245                 }
5246
5247                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5248                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5249                 else {
5250                         struct iphdr *iph = ip_hdr(skb);
5251
5252                         tcp_opt_len = tcp_optlen(skb);
5253                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5254
5255                         iph->check = 0;
5256                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5257                         hdrlen = ip_tcp_len + tcp_opt_len;
5258                 }
5259
5260                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5261                         mss |= (hdrlen & 0xc) << 12;
5262                         if (hdrlen & 0x10)
5263                                 base_flags |= 0x00000010;
5264                         base_flags |= (hdrlen & 0x3e0) << 5;
5265                 } else
5266                         mss |= hdrlen << 9;
5267
5268                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5269                                TXD_FLAG_CPU_POST_DMA);
5270
5271                 tcp_hdr(skb)->check = 0;
5272
5273         }
5274         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5275                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5276 #if TG3_VLAN_TAG_USED
5277         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5278                 base_flags |= (TXD_FLAG_VLAN |
5279                                (vlan_tx_tag_get(skb) << 16));
5280 #endif
5281
5282         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5283                 dev_kfree_skb(skb);
5284                 goto out_unlock;
5285         }
5286
5287         sp = skb_shinfo(skb);
5288
5289         mapping = sp->dma_head;
5290
5291         tnapi->tx_buffers[entry].skb = skb;
5292
5293         len = skb_headlen(skb);
5294
5295         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5296             !mss && skb->len > ETH_DATA_LEN)
5297                 base_flags |= TXD_FLAG_JMB_PKT;
5298
5299         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5300                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5301
5302         entry = NEXT_TX(entry);
5303
5304         /* Now loop through additional data fragments, and queue them. */
5305         if (skb_shinfo(skb)->nr_frags > 0) {
5306                 unsigned int i, last;
5307
5308                 last = skb_shinfo(skb)->nr_frags - 1;
5309                 for (i = 0; i <= last; i++) {
5310                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5311
5312                         len = frag->size;
5313                         mapping = sp->dma_maps[i];
5314                         tnapi->tx_buffers[entry].skb = NULL;
5315
5316                         tg3_set_txd(tnapi, entry, mapping, len,
5317                                     base_flags, (i == last) | (mss << 1));
5318
5319                         entry = NEXT_TX(entry);
5320                 }
5321         }
5322
5323         /* Packets are ready, update Tx producer idx local and on card. */
5324         tw32_tx_mbox(tnapi->prodmbox, entry);
5325
5326         tnapi->tx_prod = entry;
5327         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5328                 netif_tx_stop_queue(txq);
5329                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5330                         netif_tx_wake_queue(txq);
5331         }
5332
5333 out_unlock:
5334         mmiowb();
5335
5336         return NETDEV_TX_OK;
5337 }
5338
5339 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5340                                           struct net_device *);
5341
5342 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5343  * TSO header is greater than 80 bytes.
5344  */
5345 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5346 {
5347         struct sk_buff *segs, *nskb;
5348         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5349
5350         /* Estimate the number of fragments in the worst case */
5351         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5352                 netif_stop_queue(tp->dev);
5353                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5354                         return NETDEV_TX_BUSY;
5355
5356                 netif_wake_queue(tp->dev);
5357         }
5358
5359         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5360         if (IS_ERR(segs))
5361                 goto tg3_tso_bug_end;
5362
5363         do {
5364                 nskb = segs;
5365                 segs = segs->next;
5366                 nskb->next = NULL;
5367                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5368         } while (segs);
5369
5370 tg3_tso_bug_end:
5371         dev_kfree_skb(skb);
5372
5373         return NETDEV_TX_OK;
5374 }
5375
5376 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5377  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5378  */
5379 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5380                                           struct net_device *dev)
5381 {
5382         struct tg3 *tp = netdev_priv(dev);
5383         u32 len, entry, base_flags, mss;
5384         struct skb_shared_info *sp;
5385         int would_hit_hwbug;
5386         dma_addr_t mapping;
5387         struct tg3_napi *tnapi = &tp->napi[0];
5388
5389         len = skb_headlen(skb);
5390
5391         /* We are running in BH disabled context with netif_tx_lock
5392          * and TX reclaim runs via tp->napi.poll inside of a software
5393          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5394          * no IRQ context deadlocks to worry about either.  Rejoice!
5395          */
5396         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5397                 if (!netif_queue_stopped(dev)) {
5398                         netif_stop_queue(dev);
5399
5400                         /* This is a hard error, log it. */
5401                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5402                                "queue awake!\n", dev->name);
5403                 }
5404                 return NETDEV_TX_BUSY;
5405         }
5406
5407         entry = tnapi->tx_prod;
5408         base_flags = 0;
5409         if (skb->ip_summed == CHECKSUM_PARTIAL)
5410                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5411         mss = 0;
5412         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5413                 struct iphdr *iph;
5414                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5415
5416                 if (skb_header_cloned(skb) &&
5417                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5418                         dev_kfree_skb(skb);
5419                         goto out_unlock;
5420                 }
5421
5422                 tcp_opt_len = tcp_optlen(skb);
5423                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5424
5425                 hdr_len = ip_tcp_len + tcp_opt_len;
5426                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5427                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5428                         return (tg3_tso_bug(tp, skb));
5429
5430                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5431                                TXD_FLAG_CPU_POST_DMA);
5432
5433                 iph = ip_hdr(skb);
5434                 iph->check = 0;
5435                 iph->tot_len = htons(mss + hdr_len);
5436                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5437                         tcp_hdr(skb)->check = 0;
5438                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5439                 } else
5440                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5441                                                                  iph->daddr, 0,
5442                                                                  IPPROTO_TCP,
5443                                                                  0);
5444
5445                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5446                         mss |= hdr_len << 9;
5447                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5448                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5449                         if (tcp_opt_len || iph->ihl > 5) {
5450                                 int tsflags;
5451
5452                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5453                                 mss |= (tsflags << 11);
5454                         }
5455                 } else {
5456                         if (tcp_opt_len || iph->ihl > 5) {
5457                                 int tsflags;
5458
5459                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5460                                 base_flags |= tsflags << 12;
5461                         }
5462                 }
5463         }
5464 #if TG3_VLAN_TAG_USED
5465         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5466                 base_flags |= (TXD_FLAG_VLAN |
5467                                (vlan_tx_tag_get(skb) << 16));
5468 #endif
5469
5470         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5471                 dev_kfree_skb(skb);
5472                 goto out_unlock;
5473         }
5474
5475         sp = skb_shinfo(skb);
5476
5477         mapping = sp->dma_head;
5478
5479         tnapi->tx_buffers[entry].skb = skb;
5480
5481         would_hit_hwbug = 0;
5482
5483         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5484                 would_hit_hwbug = 1;
5485
5486         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5487             tg3_4g_overflow_test(mapping, len))
5488                 would_hit_hwbug = 1;
5489
5490         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5491             tg3_40bit_overflow_test(tp, mapping, len))
5492                 would_hit_hwbug = 1;
5493
5494         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5495                 would_hit_hwbug = 1;
5496
5497         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5498                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5499
5500         entry = NEXT_TX(entry);
5501
5502         /* Now loop through additional data fragments, and queue them. */
5503         if (skb_shinfo(skb)->nr_frags > 0) {
5504                 unsigned int i, last;
5505
5506                 last = skb_shinfo(skb)->nr_frags - 1;
5507                 for (i = 0; i <= last; i++) {
5508                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5509
5510                         len = frag->size;
5511                         mapping = sp->dma_maps[i];
5512
5513                         tnapi->tx_buffers[entry].skb = NULL;
5514
5515                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5516                             len <= 8)
5517                                 would_hit_hwbug = 1;
5518
5519                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5520                             tg3_4g_overflow_test(mapping, len))
5521                                 would_hit_hwbug = 1;
5522
5523                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5524                             tg3_40bit_overflow_test(tp, mapping, len))
5525                                 would_hit_hwbug = 1;
5526
5527                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5528                                 tg3_set_txd(tnapi, entry, mapping, len,
5529                                             base_flags, (i == last)|(mss << 1));
5530                         else
5531                                 tg3_set_txd(tnapi, entry, mapping, len,
5532                                             base_flags, (i == last));
5533
5534                         entry = NEXT_TX(entry);
5535                 }
5536         }
5537
5538         if (would_hit_hwbug) {
5539                 u32 last_plus_one = entry;
5540                 u32 start;
5541
5542                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5543                 start &= (TG3_TX_RING_SIZE - 1);
5544
5545                 /* If the workaround fails due to memory/mapping
5546                  * failure, silently drop this packet.
5547                  */
5548                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5549                                                 &start, base_flags, mss))
5550                         goto out_unlock;
5551
5552                 entry = start;
5553         }
5554
5555         /* Packets are ready, update Tx producer idx local and on card. */
5556         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5557
5558         tnapi->tx_prod = entry;
5559         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5560                 netif_stop_queue(dev);
5561                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5562                         netif_wake_queue(tp->dev);
5563         }
5564
5565 out_unlock:
5566         mmiowb();
5567
5568         return NETDEV_TX_OK;
5569 }
5570
5571 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5572                                int new_mtu)
5573 {
5574         dev->mtu = new_mtu;
5575
5576         if (new_mtu > ETH_DATA_LEN) {
5577                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5578                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5579                         ethtool_op_set_tso(dev, 0);
5580                 }
5581                 else
5582                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5583         } else {
5584                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5585                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5586                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5587         }
5588 }
5589
5590 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5591 {
5592         struct tg3 *tp = netdev_priv(dev);
5593         int err;
5594
5595         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5596                 return -EINVAL;
5597
5598         if (!netif_running(dev)) {
5599                 /* We'll just catch it later when the
5600                  * device is up'd.
5601                  */
5602                 tg3_set_mtu(dev, tp, new_mtu);
5603                 return 0;
5604         }
5605
5606         tg3_phy_stop(tp);
5607
5608         tg3_netif_stop(tp);
5609
5610         tg3_full_lock(tp, 1);
5611
5612         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5613
5614         tg3_set_mtu(dev, tp, new_mtu);
5615
5616         err = tg3_restart_hw(tp, 0);
5617
5618         if (!err)
5619                 tg3_netif_start(tp);
5620
5621         tg3_full_unlock(tp);
5622
5623         if (!err)
5624                 tg3_phy_start(tp);
5625
5626         return err;
5627 }
5628
5629 static void tg3_rx_prodring_free(struct tg3 *tp,
5630                                  struct tg3_rx_prodring_set *tpr)
5631 {
5632         int i;
5633         struct ring_info *rxp;
5634
5635         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5636                 rxp = &tpr->rx_std_buffers[i];
5637
5638                 if (rxp->skb == NULL)
5639                         continue;
5640
5641                 pci_unmap_single(tp->pdev,
5642                                  pci_unmap_addr(rxp, mapping),
5643                                  tp->rx_pkt_map_sz,
5644                                  PCI_DMA_FROMDEVICE);
5645                 dev_kfree_skb_any(rxp->skb);
5646                 rxp->skb = NULL;
5647         }
5648
5649         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5650                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5651                         rxp = &tpr->rx_jmb_buffers[i];
5652
5653                         if (rxp->skb == NULL)
5654                                 continue;
5655
5656                         pci_unmap_single(tp->pdev,
5657                                          pci_unmap_addr(rxp, mapping),
5658                                          TG3_RX_JMB_MAP_SZ,
5659                                          PCI_DMA_FROMDEVICE);
5660                         dev_kfree_skb_any(rxp->skb);
5661                         rxp->skb = NULL;
5662                 }
5663         }
5664 }
5665
5666 /* Initialize tx/rx rings for packet processing.
5667  *
5668  * The chip has been shut down and the driver detached from
5669  * the networking, so no interrupts or new tx packets will
5670  * end up in the driver.  tp->{tx,}lock are held and thus
5671  * we may not sleep.
5672  */
5673 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5674                                  struct tg3_rx_prodring_set *tpr)
5675 {
5676         u32 i, rx_pkt_dma_sz;
5677         struct tg3_napi *tnapi = &tp->napi[0];
5678
5679         /* Zero out all descriptors. */
5680         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5681
5682         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5683         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5684             tp->dev->mtu > ETH_DATA_LEN)
5685                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5686         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5687
5688         /* Initialize invariants of the rings, we only set this
5689          * stuff once.  This works because the card does not
5690          * write into the rx buffer posting rings.
5691          */
5692         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5693                 struct tg3_rx_buffer_desc *rxd;
5694
5695                 rxd = &tpr->rx_std[i];
5696                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5697                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5698                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5699                                (i << RXD_OPAQUE_INDEX_SHIFT));
5700         }
5701
5702         /* Now allocate fresh SKBs for each rx ring. */
5703         for (i = 0; i < tp->rx_pending; i++) {
5704                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5705                         printk(KERN_WARNING PFX
5706                                "%s: Using a smaller RX standard ring, "
5707                                "only %d out of %d buffers were allocated "
5708                                "successfully.\n",
5709                                tp->dev->name, i, tp->rx_pending);
5710                         if (i == 0)
5711                                 goto initfail;
5712                         tp->rx_pending = i;
5713                         break;
5714                 }
5715         }
5716
5717         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5718                 goto done;
5719
5720         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5721
5722         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5723                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5724                         struct tg3_rx_buffer_desc *rxd;
5725
5726                         rxd = &tpr->rx_jmb[i].std;
5727                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5728                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5729                                 RXD_FLAG_JUMBO;
5730                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5731                                (i << RXD_OPAQUE_INDEX_SHIFT));
5732                 }
5733
5734                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5735                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5736                                              -1, i) < 0) {
5737                                 printk(KERN_WARNING PFX
5738                                        "%s: Using a smaller RX jumbo ring, "
5739                                        "only %d out of %d buffers were "
5740                                        "allocated successfully.\n",
5741                                        tp->dev->name, i, tp->rx_jumbo_pending);
5742                                 if (i == 0)
5743                                         goto initfail;
5744                                 tp->rx_jumbo_pending = i;
5745                                 break;
5746                         }
5747                 }
5748         }
5749
5750 done:
5751         return 0;
5752
5753 initfail:
5754         tg3_rx_prodring_free(tp, tpr);
5755         return -ENOMEM;
5756 }
5757
5758 static void tg3_rx_prodring_fini(struct tg3 *tp,
5759                                  struct tg3_rx_prodring_set *tpr)
5760 {
5761         kfree(tpr->rx_std_buffers);
5762         tpr->rx_std_buffers = NULL;
5763         kfree(tpr->rx_jmb_buffers);
5764         tpr->rx_jmb_buffers = NULL;
5765         if (tpr->rx_std) {
5766                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5767                                     tpr->rx_std, tpr->rx_std_mapping);
5768                 tpr->rx_std = NULL;
5769         }
5770         if (tpr->rx_jmb) {
5771                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5772                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5773                 tpr->rx_jmb = NULL;
5774         }
5775 }
5776
5777 static int tg3_rx_prodring_init(struct tg3 *tp,
5778                                 struct tg3_rx_prodring_set *tpr)
5779 {
5780         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5781                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5782         if (!tpr->rx_std_buffers)
5783                 return -ENOMEM;
5784
5785         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5786                                            &tpr->rx_std_mapping);
5787         if (!tpr->rx_std)
5788                 goto err_out;
5789
5790         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5791                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5792                                               TG3_RX_JUMBO_RING_SIZE,
5793                                               GFP_KERNEL);
5794                 if (!tpr->rx_jmb_buffers)
5795                         goto err_out;
5796
5797                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5798                                                    TG3_RX_JUMBO_RING_BYTES,
5799                                                    &tpr->rx_jmb_mapping);
5800                 if (!tpr->rx_jmb)
5801                         goto err_out;
5802         }
5803
5804         return 0;
5805
5806 err_out:
5807         tg3_rx_prodring_fini(tp, tpr);
5808         return -ENOMEM;
5809 }
5810
5811 /* Free up pending packets in all rx/tx rings.
5812  *
5813  * The chip has been shut down and the driver detached from
5814  * the networking, so no interrupts or new tx packets will
5815  * end up in the driver.  tp->{tx,}lock is not held and we are not
5816  * in an interrupt context and thus may sleep.
5817  */
5818 static void tg3_free_rings(struct tg3 *tp)
5819 {
5820         int i, j;
5821
5822         for (j = 0; j < tp->irq_cnt; j++) {
5823                 struct tg3_napi *tnapi = &tp->napi[j];
5824
5825                 if (!tnapi->tx_buffers)
5826                         continue;
5827
5828                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5829                         struct tx_ring_info *txp;
5830                         struct sk_buff *skb;
5831
5832                         txp = &tnapi->tx_buffers[i];
5833                         skb = txp->skb;
5834
5835                         if (skb == NULL) {
5836                                 i++;
5837                                 continue;
5838                         }
5839
5840                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5841
5842                         txp->skb = NULL;
5843
5844                         i += skb_shinfo(skb)->nr_frags + 1;
5845
5846                         dev_kfree_skb_any(skb);
5847                 }
5848         }
5849
5850         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5851 }
5852
5853 /* Initialize tx/rx rings for packet processing.
5854  *
5855  * The chip has been shut down and the driver detached from
5856  * the networking, so no interrupts or new tx packets will
5857  * end up in the driver.  tp->{tx,}lock are held and thus
5858  * we may not sleep.
5859  */
5860 static int tg3_init_rings(struct tg3 *tp)
5861 {
5862         int i;
5863
5864         /* Free up all the SKBs. */
5865         tg3_free_rings(tp);
5866
5867         for (i = 0; i < tp->irq_cnt; i++) {
5868                 struct tg3_napi *tnapi = &tp->napi[i];
5869
5870                 tnapi->last_tag = 0;
5871                 tnapi->last_irq_tag = 0;
5872                 tnapi->hw_status->status = 0;
5873                 tnapi->hw_status->status_tag = 0;
5874                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5875
5876                 tnapi->tx_prod = 0;
5877                 tnapi->tx_cons = 0;
5878                 if (tnapi->tx_ring)
5879                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5880
5881                 tnapi->rx_rcb_ptr = 0;
5882                 if (tnapi->rx_rcb)
5883                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5884         }
5885
5886         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5887 }
5888
5889 /*
5890  * Must not be invoked with interrupt sources disabled and
5891  * the hardware shutdown down.
5892  */
5893 static void tg3_free_consistent(struct tg3 *tp)
5894 {
5895         int i;
5896
5897         for (i = 0; i < tp->irq_cnt; i++) {
5898                 struct tg3_napi *tnapi = &tp->napi[i];
5899
5900                 if (tnapi->tx_ring) {
5901                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5902                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5903                         tnapi->tx_ring = NULL;
5904                 }
5905
5906                 kfree(tnapi->tx_buffers);
5907                 tnapi->tx_buffers = NULL;
5908
5909                 if (tnapi->rx_rcb) {
5910                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5911                                             tnapi->rx_rcb,
5912                                             tnapi->rx_rcb_mapping);
5913                         tnapi->rx_rcb = NULL;
5914                 }
5915
5916                 if (tnapi->hw_status) {
5917                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5918                                             tnapi->hw_status,
5919                                             tnapi->status_mapping);
5920                         tnapi->hw_status = NULL;
5921                 }
5922         }
5923
5924         if (tp->hw_stats) {
5925                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5926                                     tp->hw_stats, tp->stats_mapping);
5927                 tp->hw_stats = NULL;
5928         }
5929
5930         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5931 }
5932
5933 /*
5934  * Must not be invoked with interrupt sources disabled and
5935  * the hardware shutdown down.  Can sleep.
5936  */
5937 static int tg3_alloc_consistent(struct tg3 *tp)
5938 {
5939         int i;
5940
5941         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5942                 return -ENOMEM;
5943
5944         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5945                                             sizeof(struct tg3_hw_stats),
5946                                             &tp->stats_mapping);
5947         if (!tp->hw_stats)
5948                 goto err_out;
5949
5950         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5951
5952         for (i = 0; i < tp->irq_cnt; i++) {
5953                 struct tg3_napi *tnapi = &tp->napi[i];
5954                 struct tg3_hw_status *sblk;
5955
5956                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5957                                                         TG3_HW_STATUS_SIZE,
5958                                                         &tnapi->status_mapping);
5959                 if (!tnapi->hw_status)
5960                         goto err_out;
5961
5962                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5963                 sblk = tnapi->hw_status;
5964
5965                 /*
5966                  * When RSS is enabled, the status block format changes
5967                  * slightly.  The "rx_jumbo_consumer", "reserved",
5968                  * and "rx_mini_consumer" members get mapped to the
5969                  * other three rx return ring producer indexes.
5970                  */
5971                 switch (i) {
5972                 default:
5973                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5974                         break;
5975                 case 2:
5976                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5977                         break;
5978                 case 3:
5979                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
5980                         break;
5981                 case 4:
5982                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5983                         break;
5984                 }
5985
5986                 /*
5987                  * If multivector RSS is enabled, vector 0 does not handle
5988                  * rx or tx interrupts.  Don't allocate any resources for it.
5989                  */
5990                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5991                         continue;
5992
5993                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5994                                                      TG3_RX_RCB_RING_BYTES(tp),
5995                                                      &tnapi->rx_rcb_mapping);
5996                 if (!tnapi->rx_rcb)
5997                         goto err_out;
5998
5999                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6000
6001                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6002                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6003                 if (!tnapi->tx_buffers)
6004                         goto err_out;
6005
6006                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6007                                                       TG3_TX_RING_BYTES,
6008                                                       &tnapi->tx_desc_mapping);
6009                 if (!tnapi->tx_ring)
6010                         goto err_out;
6011         }
6012
6013         return 0;
6014
6015 err_out:
6016         tg3_free_consistent(tp);
6017         return -ENOMEM;
6018 }
6019
6020 #define MAX_WAIT_CNT 1000
6021
6022 /* To stop a block, clear the enable bit and poll till it
6023  * clears.  tp->lock is held.
6024  */
6025 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6026 {
6027         unsigned int i;
6028         u32 val;
6029
6030         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6031                 switch (ofs) {
6032                 case RCVLSC_MODE:
6033                 case DMAC_MODE:
6034                 case MBFREE_MODE:
6035                 case BUFMGR_MODE:
6036                 case MEMARB_MODE:
6037                         /* We can't enable/disable these bits of the
6038                          * 5705/5750, just say success.
6039                          */
6040                         return 0;
6041
6042                 default:
6043                         break;
6044                 }
6045         }
6046
6047         val = tr32(ofs);
6048         val &= ~enable_bit;
6049         tw32_f(ofs, val);
6050
6051         for (i = 0; i < MAX_WAIT_CNT; i++) {
6052                 udelay(100);
6053                 val = tr32(ofs);
6054                 if ((val & enable_bit) == 0)
6055                         break;
6056         }
6057
6058         if (i == MAX_WAIT_CNT && !silent) {
6059                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6060                        "ofs=%lx enable_bit=%x\n",
6061                        ofs, enable_bit);
6062                 return -ENODEV;
6063         }
6064
6065         return 0;
6066 }
6067
6068 /* tp->lock is held. */
6069 static int tg3_abort_hw(struct tg3 *tp, int silent)
6070 {
6071         int i, err;
6072
6073         tg3_disable_ints(tp);
6074
6075         tp->rx_mode &= ~RX_MODE_ENABLE;
6076         tw32_f(MAC_RX_MODE, tp->rx_mode);
6077         udelay(10);
6078
6079         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6080         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6081         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6082         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6083         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6084         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6085
6086         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6087         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6088         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6089         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6090         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6091         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6092         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6093
6094         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6095         tw32_f(MAC_MODE, tp->mac_mode);
6096         udelay(40);
6097
6098         tp->tx_mode &= ~TX_MODE_ENABLE;
6099         tw32_f(MAC_TX_MODE, tp->tx_mode);
6100
6101         for (i = 0; i < MAX_WAIT_CNT; i++) {
6102                 udelay(100);
6103                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6104                         break;
6105         }
6106         if (i >= MAX_WAIT_CNT) {
6107                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6108                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6109                        tp->dev->name, tr32(MAC_TX_MODE));
6110                 err |= -ENODEV;
6111         }
6112
6113         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6114         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6115         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6116
6117         tw32(FTQ_RESET, 0xffffffff);
6118         tw32(FTQ_RESET, 0x00000000);
6119
6120         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6121         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6122
6123         for (i = 0; i < tp->irq_cnt; i++) {
6124                 struct tg3_napi *tnapi = &tp->napi[i];
6125                 if (tnapi->hw_status)
6126                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6127         }
6128         if (tp->hw_stats)
6129                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6130
6131         return err;
6132 }
6133
6134 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6135 {
6136         int i;
6137         u32 apedata;
6138
6139         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6140         if (apedata != APE_SEG_SIG_MAGIC)
6141                 return;
6142
6143         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6144         if (!(apedata & APE_FW_STATUS_READY))
6145                 return;
6146
6147         /* Wait for up to 1 millisecond for APE to service previous event. */
6148         for (i = 0; i < 10; i++) {
6149                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6150                         return;
6151
6152                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6153
6154                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6155                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6156                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6157
6158                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6159
6160                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6161                         break;
6162
6163                 udelay(100);
6164         }
6165
6166         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6167                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6168 }
6169
6170 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6171 {
6172         u32 event;
6173         u32 apedata;
6174
6175         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6176                 return;
6177
6178         switch (kind) {
6179                 case RESET_KIND_INIT:
6180                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6181                                         APE_HOST_SEG_SIG_MAGIC);
6182                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6183                                         APE_HOST_SEG_LEN_MAGIC);
6184                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6185                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6186                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6187                                         APE_HOST_DRIVER_ID_MAGIC);
6188                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6189                                         APE_HOST_BEHAV_NO_PHYLOCK);
6190
6191                         event = APE_EVENT_STATUS_STATE_START;
6192                         break;
6193                 case RESET_KIND_SHUTDOWN:
6194                         /* With the interface we are currently using,
6195                          * APE does not track driver state.  Wiping
6196                          * out the HOST SEGMENT SIGNATURE forces
6197                          * the APE to assume OS absent status.
6198                          */
6199                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6200
6201                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6202                         break;
6203                 case RESET_KIND_SUSPEND:
6204                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6205                         break;
6206                 default:
6207                         return;
6208         }
6209
6210         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6211
6212         tg3_ape_send_event(tp, event);
6213 }
6214
6215 /* tp->lock is held. */
6216 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6217 {
6218         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6219                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6220
6221         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6222                 switch (kind) {
6223                 case RESET_KIND_INIT:
6224                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6225                                       DRV_STATE_START);
6226                         break;
6227
6228                 case RESET_KIND_SHUTDOWN:
6229                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6230                                       DRV_STATE_UNLOAD);
6231                         break;
6232
6233                 case RESET_KIND_SUSPEND:
6234                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6235                                       DRV_STATE_SUSPEND);
6236                         break;
6237
6238                 default:
6239                         break;
6240                 }
6241         }
6242
6243         if (kind == RESET_KIND_INIT ||
6244             kind == RESET_KIND_SUSPEND)
6245                 tg3_ape_driver_state_change(tp, kind);
6246 }
6247
6248 /* tp->lock is held. */
6249 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6250 {
6251         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6252                 switch (kind) {
6253                 case RESET_KIND_INIT:
6254                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6255                                       DRV_STATE_START_DONE);
6256                         break;
6257
6258                 case RESET_KIND_SHUTDOWN:
6259                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6260                                       DRV_STATE_UNLOAD_DONE);
6261                         break;
6262
6263                 default:
6264                         break;
6265                 }
6266         }
6267
6268         if (kind == RESET_KIND_SHUTDOWN)
6269                 tg3_ape_driver_state_change(tp, kind);
6270 }
6271
6272 /* tp->lock is held. */
6273 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6274 {
6275         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6276                 switch (kind) {
6277                 case RESET_KIND_INIT:
6278                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6279                                       DRV_STATE_START);
6280                         break;
6281
6282                 case RESET_KIND_SHUTDOWN:
6283                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6284                                       DRV_STATE_UNLOAD);
6285                         break;
6286
6287                 case RESET_KIND_SUSPEND:
6288                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6289                                       DRV_STATE_SUSPEND);
6290                         break;
6291
6292                 default:
6293                         break;
6294                 }
6295         }
6296 }
6297
6298 static int tg3_poll_fw(struct tg3 *tp)
6299 {
6300         int i;
6301         u32 val;
6302
6303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6304                 /* Wait up to 20ms for init done. */
6305                 for (i = 0; i < 200; i++) {
6306                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6307                                 return 0;
6308                         udelay(100);
6309                 }
6310                 return -ENODEV;
6311         }
6312
6313         /* Wait for firmware initialization to complete. */
6314         for (i = 0; i < 100000; i++) {
6315                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6316                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6317                         break;
6318                 udelay(10);
6319         }
6320
6321         /* Chip might not be fitted with firmware.  Some Sun onboard
6322          * parts are configured like that.  So don't signal the timeout
6323          * of the above loop as an error, but do report the lack of
6324          * running firmware once.
6325          */
6326         if (i >= 100000 &&
6327             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6328                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6329
6330                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6331                        tp->dev->name);
6332         }
6333
6334         return 0;
6335 }
6336
6337 /* Save PCI command register before chip reset */
6338 static void tg3_save_pci_state(struct tg3 *tp)
6339 {
6340         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6341 }
6342
6343 /* Restore PCI state after chip reset */
6344 static void tg3_restore_pci_state(struct tg3 *tp)
6345 {
6346         u32 val;
6347
6348         /* Re-enable indirect register accesses. */
6349         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6350                                tp->misc_host_ctrl);
6351
6352         /* Set MAX PCI retry to zero. */
6353         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6354         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6355             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6356                 val |= PCISTATE_RETRY_SAME_DMA;
6357         /* Allow reads and writes to the APE register and memory space. */
6358         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6359                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6360                        PCISTATE_ALLOW_APE_SHMEM_WR;
6361         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6362
6363         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6364
6365         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6366                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6367                         pcie_set_readrq(tp->pdev, 4096);
6368                 else {
6369                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6370                                               tp->pci_cacheline_sz);
6371                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6372                                               tp->pci_lat_timer);
6373                 }
6374         }
6375
6376         /* Make sure PCI-X relaxed ordering bit is clear. */
6377         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6378                 u16 pcix_cmd;
6379
6380                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6381                                      &pcix_cmd);
6382                 pcix_cmd &= ~PCI_X_CMD_ERO;
6383                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6384                                       pcix_cmd);
6385         }
6386
6387         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6388
6389                 /* Chip reset on 5780 will reset MSI enable bit,
6390                  * so need to restore it.
6391                  */
6392                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6393                         u16 ctrl;
6394
6395                         pci_read_config_word(tp->pdev,
6396                                              tp->msi_cap + PCI_MSI_FLAGS,
6397                                              &ctrl);
6398                         pci_write_config_word(tp->pdev,
6399                                               tp->msi_cap + PCI_MSI_FLAGS,
6400                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6401                         val = tr32(MSGINT_MODE);
6402                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6403                 }
6404         }
6405 }
6406
6407 static void tg3_stop_fw(struct tg3 *);
6408
6409 /* tp->lock is held. */
6410 static int tg3_chip_reset(struct tg3 *tp)
6411 {
6412         u32 val;
6413         void (*write_op)(struct tg3 *, u32, u32);
6414         int i, err;
6415
6416         tg3_nvram_lock(tp);
6417
6418         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6419
6420         /* No matching tg3_nvram_unlock() after this because
6421          * chip reset below will undo the nvram lock.
6422          */
6423         tp->nvram_lock_cnt = 0;
6424
6425         /* GRC_MISC_CFG core clock reset will clear the memory
6426          * enable bit in PCI register 4 and the MSI enable bit
6427          * on some chips, so we save relevant registers here.
6428          */
6429         tg3_save_pci_state(tp);
6430
6431         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6432             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6433                 tw32(GRC_FASTBOOT_PC, 0);
6434
6435         /*
6436          * We must avoid the readl() that normally takes place.
6437          * It locks machines, causes machine checks, and other
6438          * fun things.  So, temporarily disable the 5701
6439          * hardware workaround, while we do the reset.
6440          */
6441         write_op = tp->write32;
6442         if (write_op == tg3_write_flush_reg32)
6443                 tp->write32 = tg3_write32;
6444
6445         /* Prevent the irq handler from reading or writing PCI registers
6446          * during chip reset when the memory enable bit in the PCI command
6447          * register may be cleared.  The chip does not generate interrupt
6448          * at this time, but the irq handler may still be called due to irq
6449          * sharing or irqpoll.
6450          */
6451         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6452         for (i = 0; i < tp->irq_cnt; i++) {
6453                 struct tg3_napi *tnapi = &tp->napi[i];
6454                 if (tnapi->hw_status) {
6455                         tnapi->hw_status->status = 0;
6456                         tnapi->hw_status->status_tag = 0;
6457                 }
6458                 tnapi->last_tag = 0;
6459                 tnapi->last_irq_tag = 0;
6460         }
6461         smp_mb();
6462
6463         for (i = 0; i < tp->irq_cnt; i++)
6464                 synchronize_irq(tp->napi[i].irq_vec);
6465
6466         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6467                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6468                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6469         }
6470
6471         /* do the reset */
6472         val = GRC_MISC_CFG_CORECLK_RESET;
6473
6474         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6475                 if (tr32(0x7e2c) == 0x60) {
6476                         tw32(0x7e2c, 0x20);
6477                 }
6478                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6479                         tw32(GRC_MISC_CFG, (1 << 29));
6480                         val |= (1 << 29);
6481                 }
6482         }
6483
6484         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6485                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6486                 tw32(GRC_VCPU_EXT_CTRL,
6487                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6488         }
6489
6490         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6491                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6492         tw32(GRC_MISC_CFG, val);
6493
6494         /* restore 5701 hardware bug workaround write method */
6495         tp->write32 = write_op;
6496
6497         /* Unfortunately, we have to delay before the PCI read back.
6498          * Some 575X chips even will not respond to a PCI cfg access
6499          * when the reset command is given to the chip.
6500          *
6501          * How do these hardware designers expect things to work
6502          * properly if the PCI write is posted for a long period
6503          * of time?  It is always necessary to have some method by
6504          * which a register read back can occur to push the write
6505          * out which does the reset.
6506          *
6507          * For most tg3 variants the trick below was working.
6508          * Ho hum...
6509          */
6510         udelay(120);
6511
6512         /* Flush PCI posted writes.  The normal MMIO registers
6513          * are inaccessible at this time so this is the only
6514          * way to make this reliably (actually, this is no longer
6515          * the case, see above).  I tried to use indirect
6516          * register read/write but this upset some 5701 variants.
6517          */
6518         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6519
6520         udelay(120);
6521
6522         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6523                 u16 val16;
6524
6525                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6526                         int i;
6527                         u32 cfg_val;
6528
6529                         /* Wait for link training to complete.  */
6530                         for (i = 0; i < 5000; i++)
6531                                 udelay(100);
6532
6533                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6534                         pci_write_config_dword(tp->pdev, 0xc4,
6535                                                cfg_val | (1 << 15));
6536                 }
6537
6538                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6539                 pci_read_config_word(tp->pdev,
6540                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6541                                      &val16);
6542                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6543                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6544                 /*
6545                  * Older PCIe devices only support the 128 byte
6546                  * MPS setting.  Enforce the restriction.
6547                  */
6548                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6549                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6550                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6551                 pci_write_config_word(tp->pdev,
6552                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6553                                       val16);
6554
6555                 pcie_set_readrq(tp->pdev, 4096);
6556
6557                 /* Clear error status */
6558                 pci_write_config_word(tp->pdev,
6559                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6560                                       PCI_EXP_DEVSTA_CED |
6561                                       PCI_EXP_DEVSTA_NFED |
6562                                       PCI_EXP_DEVSTA_FED |
6563                                       PCI_EXP_DEVSTA_URD);
6564         }
6565
6566         tg3_restore_pci_state(tp);
6567
6568         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6569
6570         val = 0;
6571         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6572                 val = tr32(MEMARB_MODE);
6573         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6574
6575         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6576                 tg3_stop_fw(tp);
6577                 tw32(0x5000, 0x400);
6578         }
6579
6580         tw32(GRC_MODE, tp->grc_mode);
6581
6582         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6583                 val = tr32(0xc4);
6584
6585                 tw32(0xc4, val | (1 << 15));
6586         }
6587
6588         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6589             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6590                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6591                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6592                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6593                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6594         }
6595
6596         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6597                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6598                 tw32_f(MAC_MODE, tp->mac_mode);
6599         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6600                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6601                 tw32_f(MAC_MODE, tp->mac_mode);
6602         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6603                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6604                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6605                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6606                 tw32_f(MAC_MODE, tp->mac_mode);
6607         } else
6608                 tw32_f(MAC_MODE, 0);
6609         udelay(40);
6610
6611         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6612
6613         err = tg3_poll_fw(tp);
6614         if (err)
6615                 return err;
6616
6617         tg3_mdio_start(tp);
6618
6619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6620                 u8 phy_addr;
6621
6622                 phy_addr = tp->phy_addr;
6623                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6624
6625                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6626                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6627                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6628                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6629                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6630                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6631                 udelay(10);
6632
6633                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6634                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6635                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6636                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6637                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6638                 udelay(10);
6639
6640                 tp->phy_addr = phy_addr;
6641         }
6642
6643         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6644             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6645             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6646             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6647                 val = tr32(0x7c00);
6648
6649                 tw32(0x7c00, val | (1 << 25));
6650         }
6651
6652         /* Reprobe ASF enable state.  */
6653         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6654         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6655         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6656         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6657                 u32 nic_cfg;
6658
6659                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6660                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6661                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6662                         tp->last_event_jiffies = jiffies;
6663                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6664                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6665                 }
6666         }
6667
6668         return 0;
6669 }
6670
6671 /* tp->lock is held. */
6672 static void tg3_stop_fw(struct tg3 *tp)
6673 {
6674         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6675            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6676                 /* Wait for RX cpu to ACK the previous event. */
6677                 tg3_wait_for_event_ack(tp);
6678
6679                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6680
6681                 tg3_generate_fw_event(tp);
6682
6683                 /* Wait for RX cpu to ACK this event. */
6684                 tg3_wait_for_event_ack(tp);
6685         }
6686 }
6687
6688 /* tp->lock is held. */
6689 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6690 {
6691         int err;
6692
6693         tg3_stop_fw(tp);
6694
6695         tg3_write_sig_pre_reset(tp, kind);
6696
6697         tg3_abort_hw(tp, silent);
6698         err = tg3_chip_reset(tp);
6699
6700         __tg3_set_mac_addr(tp, 0);
6701
6702         tg3_write_sig_legacy(tp, kind);
6703         tg3_write_sig_post_reset(tp, kind);
6704
6705         if (err)
6706                 return err;
6707
6708         return 0;
6709 }
6710
6711 #define RX_CPU_SCRATCH_BASE     0x30000
6712 #define RX_CPU_SCRATCH_SIZE     0x04000
6713 #define TX_CPU_SCRATCH_BASE     0x34000
6714 #define TX_CPU_SCRATCH_SIZE     0x04000
6715
6716 /* tp->lock is held. */
6717 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6718 {
6719         int i;
6720
6721         BUG_ON(offset == TX_CPU_BASE &&
6722             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6723
6724         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6725                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6726
6727                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6728                 return 0;
6729         }
6730         if (offset == RX_CPU_BASE) {
6731                 for (i = 0; i < 10000; i++) {
6732                         tw32(offset + CPU_STATE, 0xffffffff);
6733                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6734                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6735                                 break;
6736                 }
6737
6738                 tw32(offset + CPU_STATE, 0xffffffff);
6739                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6740                 udelay(10);
6741         } else {
6742                 for (i = 0; i < 10000; i++) {
6743                         tw32(offset + CPU_STATE, 0xffffffff);
6744                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6745                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6746                                 break;
6747                 }
6748         }
6749
6750         if (i >= 10000) {
6751                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6752                        "and %s CPU\n",
6753                        tp->dev->name,
6754                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6755                 return -ENODEV;
6756         }
6757
6758         /* Clear firmware's nvram arbitration. */
6759         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6760                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6761         return 0;
6762 }
6763
6764 struct fw_info {
6765         unsigned int fw_base;
6766         unsigned int fw_len;
6767         const __be32 *fw_data;
6768 };
6769
6770 /* tp->lock is held. */
6771 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6772                                  int cpu_scratch_size, struct fw_info *info)
6773 {
6774         int err, lock_err, i;
6775         void (*write_op)(struct tg3 *, u32, u32);
6776
6777         if (cpu_base == TX_CPU_BASE &&
6778             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6779                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6780                        "TX cpu firmware on %s which is 5705.\n",
6781                        tp->dev->name);
6782                 return -EINVAL;
6783         }
6784
6785         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6786                 write_op = tg3_write_mem;
6787         else
6788                 write_op = tg3_write_indirect_reg32;
6789
6790         /* It is possible that bootcode is still loading at this point.
6791          * Get the nvram lock first before halting the cpu.
6792          */
6793         lock_err = tg3_nvram_lock(tp);
6794         err = tg3_halt_cpu(tp, cpu_base);
6795         if (!lock_err)
6796                 tg3_nvram_unlock(tp);
6797         if (err)
6798                 goto out;
6799
6800         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6801                 write_op(tp, cpu_scratch_base + i, 0);
6802         tw32(cpu_base + CPU_STATE, 0xffffffff);
6803         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6804         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6805                 write_op(tp, (cpu_scratch_base +
6806                               (info->fw_base & 0xffff) +
6807                               (i * sizeof(u32))),
6808                               be32_to_cpu(info->fw_data[i]));
6809
6810         err = 0;
6811
6812 out:
6813         return err;
6814 }
6815
6816 /* tp->lock is held. */
6817 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6818 {
6819         struct fw_info info;
6820         const __be32 *fw_data;
6821         int err, i;
6822
6823         fw_data = (void *)tp->fw->data;
6824
6825         /* Firmware blob starts with version numbers, followed by
6826            start address and length. We are setting complete length.
6827            length = end_address_of_bss - start_address_of_text.
6828            Remainder is the blob to be loaded contiguously
6829            from start address. */
6830
6831         info.fw_base = be32_to_cpu(fw_data[1]);
6832         info.fw_len = tp->fw->size - 12;
6833         info.fw_data = &fw_data[3];
6834
6835         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6836                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6837                                     &info);
6838         if (err)
6839                 return err;
6840
6841         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6842                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6843                                     &info);
6844         if (err)
6845                 return err;
6846
6847         /* Now startup only the RX cpu. */
6848         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6849         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6850
6851         for (i = 0; i < 5; i++) {
6852                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6853                         break;
6854                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6855                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6856                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6857                 udelay(1000);
6858         }
6859         if (i >= 5) {
6860                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6861                        "to set RX CPU PC, is %08x should be %08x\n",
6862                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6863                        info.fw_base);
6864                 return -ENODEV;
6865         }
6866         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6867         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6868
6869         return 0;
6870 }
6871
6872 /* 5705 needs a special version of the TSO firmware.  */
6873
6874 /* tp->lock is held. */
6875 static int tg3_load_tso_firmware(struct tg3 *tp)
6876 {
6877         struct fw_info info;
6878         const __be32 *fw_data;
6879         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6880         int err, i;
6881
6882         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6883                 return 0;
6884
6885         fw_data = (void *)tp->fw->data;
6886
6887         /* Firmware blob starts with version numbers, followed by
6888            start address and length. We are setting complete length.
6889            length = end_address_of_bss - start_address_of_text.
6890            Remainder is the blob to be loaded contiguously
6891            from start address. */
6892
6893         info.fw_base = be32_to_cpu(fw_data[1]);
6894         cpu_scratch_size = tp->fw_len;
6895         info.fw_len = tp->fw->size - 12;
6896         info.fw_data = &fw_data[3];
6897
6898         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6899                 cpu_base = RX_CPU_BASE;
6900                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6901         } else {
6902                 cpu_base = TX_CPU_BASE;
6903                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6904                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6905         }
6906
6907         err = tg3_load_firmware_cpu(tp, cpu_base,
6908                                     cpu_scratch_base, cpu_scratch_size,
6909                                     &info);
6910         if (err)
6911                 return err;
6912
6913         /* Now startup the cpu. */
6914         tw32(cpu_base + CPU_STATE, 0xffffffff);
6915         tw32_f(cpu_base + CPU_PC, info.fw_base);
6916
6917         for (i = 0; i < 5; i++) {
6918                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6919                         break;
6920                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6921                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6922                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6923                 udelay(1000);
6924         }
6925         if (i >= 5) {
6926                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6927                        "to set CPU PC, is %08x should be %08x\n",
6928                        tp->dev->name, tr32(cpu_base + CPU_PC),
6929                        info.fw_base);
6930                 return -ENODEV;
6931         }
6932         tw32(cpu_base + CPU_STATE, 0xffffffff);
6933         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6934         return 0;
6935 }
6936
6937
6938 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6939 {
6940         struct tg3 *tp = netdev_priv(dev);
6941         struct sockaddr *addr = p;
6942         int err = 0, skip_mac_1 = 0;
6943
6944         if (!is_valid_ether_addr(addr->sa_data))
6945                 return -EINVAL;
6946
6947         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6948
6949         if (!netif_running(dev))
6950                 return 0;
6951
6952         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6953                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6954
6955                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6956                 addr0_low = tr32(MAC_ADDR_0_LOW);
6957                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6958                 addr1_low = tr32(MAC_ADDR_1_LOW);
6959
6960                 /* Skip MAC addr 1 if ASF is using it. */
6961                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6962                     !(addr1_high == 0 && addr1_low == 0))
6963                         skip_mac_1 = 1;
6964         }
6965         spin_lock_bh(&tp->lock);
6966         __tg3_set_mac_addr(tp, skip_mac_1);
6967         spin_unlock_bh(&tp->lock);
6968
6969         return err;
6970 }
6971
6972 /* tp->lock is held. */
6973 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6974                            dma_addr_t mapping, u32 maxlen_flags,
6975                            u32 nic_addr)
6976 {
6977         tg3_write_mem(tp,
6978                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6979                       ((u64) mapping >> 32));
6980         tg3_write_mem(tp,
6981                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6982                       ((u64) mapping & 0xffffffff));
6983         tg3_write_mem(tp,
6984                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6985                        maxlen_flags);
6986
6987         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6988                 tg3_write_mem(tp,
6989                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6990                               nic_addr);
6991 }
6992
6993 static void __tg3_set_rx_mode(struct net_device *);
6994 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6995 {
6996         int i;
6997
6998         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6999                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7000                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7001                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7002
7003                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7004                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7005                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7006         } else {
7007                 tw32(HOSTCC_TXCOL_TICKS, 0);
7008                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7009                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7010
7011                 tw32(HOSTCC_RXCOL_TICKS, 0);
7012                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7013                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7014         }
7015
7016         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7017                 u32 val = ec->stats_block_coalesce_usecs;
7018
7019                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7020                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7021
7022                 if (!netif_carrier_ok(tp->dev))
7023                         val = 0;
7024
7025                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7026         }
7027
7028         for (i = 0; i < tp->irq_cnt - 1; i++) {
7029                 u32 reg;
7030
7031                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7032                 tw32(reg, ec->rx_coalesce_usecs);
7033                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7034                 tw32(reg, ec->tx_coalesce_usecs);
7035                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7036                 tw32(reg, ec->rx_max_coalesced_frames);
7037                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7038                 tw32(reg, ec->tx_max_coalesced_frames);
7039                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7040                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7041                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7042                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7043         }
7044
7045         for (; i < tp->irq_max - 1; i++) {
7046                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7047                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7048                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7049                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7050                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7051                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7052         }
7053 }
7054
7055 /* tp->lock is held. */
7056 static void tg3_rings_reset(struct tg3 *tp)
7057 {
7058         int i;
7059         u32 stblk, txrcb, rxrcb, limit;
7060         struct tg3_napi *tnapi = &tp->napi[0];
7061
7062         /* Disable all transmit rings but the first. */
7063         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7064                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7065         else
7066                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7067
7068         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7069              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7070                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7071                               BDINFO_FLAGS_DISABLED);
7072
7073
7074         /* Disable all receive return rings but the first. */
7075         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7076                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7077         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7078                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7079         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7080                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7081         else
7082                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7083
7084         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7085              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7086                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7087                               BDINFO_FLAGS_DISABLED);
7088
7089         /* Disable interrupts */
7090         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7091
7092         /* Zero mailbox registers. */
7093         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7094                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7095                         tp->napi[i].tx_prod = 0;
7096                         tp->napi[i].tx_cons = 0;
7097                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7098                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7099                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7100                 }
7101         } else {
7102                 tp->napi[0].tx_prod = 0;
7103                 tp->napi[0].tx_cons = 0;
7104                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7105                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7106         }
7107
7108         /* Make sure the NIC-based send BD rings are disabled. */
7109         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7110                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7111                 for (i = 0; i < 16; i++)
7112                         tw32_tx_mbox(mbox + i * 8, 0);
7113         }
7114
7115         txrcb = NIC_SRAM_SEND_RCB;
7116         rxrcb = NIC_SRAM_RCV_RET_RCB;
7117
7118         /* Clear status block in ram. */
7119         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7120
7121         /* Set status block DMA address */
7122         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7123              ((u64) tnapi->status_mapping >> 32));
7124         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7125              ((u64) tnapi->status_mapping & 0xffffffff));
7126
7127         if (tnapi->tx_ring) {
7128                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7129                                (TG3_TX_RING_SIZE <<
7130                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7131                                NIC_SRAM_TX_BUFFER_DESC);
7132                 txrcb += TG3_BDINFO_SIZE;
7133         }
7134
7135         if (tnapi->rx_rcb) {
7136                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7137                                (TG3_RX_RCB_RING_SIZE(tp) <<
7138                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7139                 rxrcb += TG3_BDINFO_SIZE;
7140         }
7141
7142         stblk = HOSTCC_STATBLCK_RING1;
7143
7144         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7145                 u64 mapping = (u64)tnapi->status_mapping;
7146                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7147                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7148
7149                 /* Clear status block in ram. */
7150                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7151
7152                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7153                                (TG3_TX_RING_SIZE <<
7154                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7155                                NIC_SRAM_TX_BUFFER_DESC);
7156
7157                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7158                                (TG3_RX_RCB_RING_SIZE(tp) <<
7159                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7160
7161                 stblk += 8;
7162                 txrcb += TG3_BDINFO_SIZE;
7163                 rxrcb += TG3_BDINFO_SIZE;
7164         }
7165 }
7166
7167 /* tp->lock is held. */
7168 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7169 {
7170         u32 val, rdmac_mode;
7171         int i, err, limit;
7172         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7173
7174         tg3_disable_ints(tp);
7175
7176         tg3_stop_fw(tp);
7177
7178         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7179
7180         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7181                 tg3_abort_hw(tp, 1);
7182         }
7183
7184         if (reset_phy &&
7185             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7186                 tg3_phy_reset(tp);
7187
7188         err = tg3_chip_reset(tp);
7189         if (err)
7190                 return err;
7191
7192         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7193
7194         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7195                 val = tr32(TG3_CPMU_CTRL);
7196                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7197                 tw32(TG3_CPMU_CTRL, val);
7198
7199                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7200                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7201                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7202                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7203
7204                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7205                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7206                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7207                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7208
7209                 val = tr32(TG3_CPMU_HST_ACC);
7210                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7211                 val |= CPMU_HST_ACC_MACCLK_6_25;
7212                 tw32(TG3_CPMU_HST_ACC, val);
7213         }
7214
7215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7216                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7217                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7218                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7219                 tw32(PCIE_PWR_MGMT_THRESH, val);
7220
7221                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7222                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7223
7224                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7225
7226                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7227                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7228         }
7229
7230         /* This works around an issue with Athlon chipsets on
7231          * B3 tigon3 silicon.  This bit has no effect on any
7232          * other revision.  But do not set this on PCI Express
7233          * chips and don't even touch the clocks if the CPMU is present.
7234          */
7235         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7236                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7237                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7238                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7239         }
7240
7241         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7242             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7243                 val = tr32(TG3PCI_PCISTATE);
7244                 val |= PCISTATE_RETRY_SAME_DMA;
7245                 tw32(TG3PCI_PCISTATE, val);
7246         }
7247
7248         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7249                 /* Allow reads and writes to the
7250                  * APE register and memory space.
7251                  */
7252                 val = tr32(TG3PCI_PCISTATE);
7253                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7254                        PCISTATE_ALLOW_APE_SHMEM_WR;
7255                 tw32(TG3PCI_PCISTATE, val);
7256         }
7257
7258         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7259                 /* Enable some hw fixes.  */
7260                 val = tr32(TG3PCI_MSI_DATA);
7261                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7262                 tw32(TG3PCI_MSI_DATA, val);
7263         }
7264
7265         /* Descriptor ring init may make accesses to the
7266          * NIC SRAM area to setup the TX descriptors, so we
7267          * can only do this after the hardware has been
7268          * successfully reset.
7269          */
7270         err = tg3_init_rings(tp);
7271         if (err)
7272                 return err;
7273
7274         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7275             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7276             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7277                 /* This value is determined during the probe time DMA
7278                  * engine test, tg3_test_dma.
7279                  */
7280                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7281         }
7282
7283         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7284                           GRC_MODE_4X_NIC_SEND_RINGS |
7285                           GRC_MODE_NO_TX_PHDR_CSUM |
7286                           GRC_MODE_NO_RX_PHDR_CSUM);
7287         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7288
7289         /* Pseudo-header checksum is done by hardware logic and not
7290          * the offload processers, so make the chip do the pseudo-
7291          * header checksums on receive.  For transmit it is more
7292          * convenient to do the pseudo-header checksum in software
7293          * as Linux does that on transmit for us in all cases.
7294          */
7295         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7296
7297         tw32(GRC_MODE,
7298              tp->grc_mode |
7299              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7300
7301         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7302         val = tr32(GRC_MISC_CFG);
7303         val &= ~0xff;
7304         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7305         tw32(GRC_MISC_CFG, val);
7306
7307         /* Initialize MBUF/DESC pool. */
7308         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7309                 /* Do nothing.  */
7310         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7311                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7312                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7313                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7314                 else
7315                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7316                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7317                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7318         }
7319         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7320                 int fw_len;
7321
7322                 fw_len = tp->fw_len;
7323                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7324                 tw32(BUFMGR_MB_POOL_ADDR,
7325                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7326                 tw32(BUFMGR_MB_POOL_SIZE,
7327                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7328         }
7329
7330         if (tp->dev->mtu <= ETH_DATA_LEN) {
7331                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7332                      tp->bufmgr_config.mbuf_read_dma_low_water);
7333                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7334                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7335                 tw32(BUFMGR_MB_HIGH_WATER,
7336                      tp->bufmgr_config.mbuf_high_water);
7337         } else {
7338                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7339                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7340                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7341                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7342                 tw32(BUFMGR_MB_HIGH_WATER,
7343                      tp->bufmgr_config.mbuf_high_water_jumbo);
7344         }
7345         tw32(BUFMGR_DMA_LOW_WATER,
7346              tp->bufmgr_config.dma_low_water);
7347         tw32(BUFMGR_DMA_HIGH_WATER,
7348              tp->bufmgr_config.dma_high_water);
7349
7350         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7351         for (i = 0; i < 2000; i++) {
7352                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7353                         break;
7354                 udelay(10);
7355         }
7356         if (i >= 2000) {
7357                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7358                        tp->dev->name);
7359                 return -ENODEV;
7360         }
7361
7362         /* Setup replenish threshold. */
7363         val = tp->rx_pending / 8;
7364         if (val == 0)
7365                 val = 1;
7366         else if (val > tp->rx_std_max_post)
7367                 val = tp->rx_std_max_post;
7368         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7369                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7370                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7371
7372                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7373                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7374         }
7375
7376         tw32(RCVBDI_STD_THRESH, val);
7377
7378         /* Initialize TG3_BDINFO's at:
7379          *  RCVDBDI_STD_BD:     standard eth size rx ring
7380          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7381          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7382          *
7383          * like so:
7384          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7385          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7386          *                              ring attribute flags
7387          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7388          *
7389          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7390          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7391          *
7392          * The size of each ring is fixed in the firmware, but the location is
7393          * configurable.
7394          */
7395         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7396              ((u64) tpr->rx_std_mapping >> 32));
7397         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7398              ((u64) tpr->rx_std_mapping & 0xffffffff));
7399         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7400              NIC_SRAM_RX_BUFFER_DESC);
7401
7402         /* Disable the mini ring */
7403         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7404                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7405                      BDINFO_FLAGS_DISABLED);
7406
7407         /* Program the jumbo buffer descriptor ring control
7408          * blocks on those devices that have them.
7409          */
7410         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7411             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7412                 /* Setup replenish threshold. */
7413                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7414
7415                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7416                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7417                              ((u64) tpr->rx_jmb_mapping >> 32));
7418                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7419                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7420                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7421                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7422                              BDINFO_FLAGS_USE_EXT_RECV);
7423                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7424                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7425                 } else {
7426                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7427                              BDINFO_FLAGS_DISABLED);
7428                 }
7429
7430                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7431                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7432                               (RX_STD_MAX_SIZE << 2);
7433                 else
7434                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7435         } else
7436                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7437
7438         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7439
7440         tpr->rx_std_ptr = tp->rx_pending;
7441         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7442                      tpr->rx_std_ptr);
7443
7444         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7445                           tp->rx_jumbo_pending : 0;
7446         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7447                      tpr->rx_jmb_ptr);
7448
7449         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7450                 tw32(STD_REPLENISH_LWM, 32);
7451                 tw32(JMB_REPLENISH_LWM, 16);
7452         }
7453
7454         tg3_rings_reset(tp);
7455
7456         /* Initialize MAC address and backoff seed. */
7457         __tg3_set_mac_addr(tp, 0);
7458
7459         /* MTU + ethernet header + FCS + optional VLAN tag */
7460         tw32(MAC_RX_MTU_SIZE,
7461              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7462
7463         /* The slot time is changed by tg3_setup_phy if we
7464          * run at gigabit with half duplex.
7465          */
7466         tw32(MAC_TX_LENGTHS,
7467              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7468              (6 << TX_LENGTHS_IPG_SHIFT) |
7469              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7470
7471         /* Receive rules. */
7472         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7473         tw32(RCVLPC_CONFIG, 0x0181);
7474
7475         /* Calculate RDMAC_MODE setting early, we need it to determine
7476          * the RCVLPC_STATE_ENABLE mask.
7477          */
7478         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7479                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7480                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7481                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7482                       RDMAC_MODE_LNGREAD_ENAB);
7483
7484         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7485             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7486             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7487                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7488                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7489                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7490
7491         /* If statement applies to 5705 and 5750 PCI devices only */
7492         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7493              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7494             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7495                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7496                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7497                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7498                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7499                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7500                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7501                 }
7502         }
7503
7504         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7505                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7506
7507         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7508                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7509
7510         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7511             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7512                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7513
7514         /* Receive/send statistics. */
7515         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7516                 val = tr32(RCVLPC_STATS_ENABLE);
7517                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7518                 tw32(RCVLPC_STATS_ENABLE, val);
7519         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7520                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7521                 val = tr32(RCVLPC_STATS_ENABLE);
7522                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7523                 tw32(RCVLPC_STATS_ENABLE, val);
7524         } else {
7525                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7526         }
7527         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7528         tw32(SNDDATAI_STATSENAB, 0xffffff);
7529         tw32(SNDDATAI_STATSCTRL,
7530              (SNDDATAI_SCTRL_ENABLE |
7531               SNDDATAI_SCTRL_FASTUPD));
7532
7533         /* Setup host coalescing engine. */
7534         tw32(HOSTCC_MODE, 0);
7535         for (i = 0; i < 2000; i++) {
7536                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7537                         break;
7538                 udelay(10);
7539         }
7540
7541         __tg3_set_coalesce(tp, &tp->coal);
7542
7543         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7544                 /* Status/statistics block address.  See tg3_timer,
7545                  * the tg3_periodic_fetch_stats call there, and
7546                  * tg3_get_stats to see how this works for 5705/5750 chips.
7547                  */
7548                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7549                      ((u64) tp->stats_mapping >> 32));
7550                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7551                      ((u64) tp->stats_mapping & 0xffffffff));
7552                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7553
7554                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7555
7556                 /* Clear statistics and status block memory areas */
7557                 for (i = NIC_SRAM_STATS_BLK;
7558                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7559                      i += sizeof(u32)) {
7560                         tg3_write_mem(tp, i, 0);
7561                         udelay(40);
7562                 }
7563         }
7564
7565         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7566
7567         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7568         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7569         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7570                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7571
7572         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7573                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7574                 /* reset to prevent losing 1st rx packet intermittently */
7575                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7576                 udelay(10);
7577         }
7578
7579         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7580                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7581         else
7582                 tp->mac_mode = 0;
7583         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7584                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7585         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7586             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7587             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7588                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7589         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7590         udelay(40);
7591
7592         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7593          * If TG3_FLG2_IS_NIC is zero, we should read the
7594          * register to preserve the GPIO settings for LOMs. The GPIOs,
7595          * whether used as inputs or outputs, are set by boot code after
7596          * reset.
7597          */
7598         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7599                 u32 gpio_mask;
7600
7601                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7602                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7603                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7604
7605                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7606                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7607                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7608
7609                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7610                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7611
7612                 tp->grc_local_ctrl &= ~gpio_mask;
7613                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7614
7615                 /* GPIO1 must be driven high for eeprom write protect */
7616                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7617                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7618                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7619         }
7620         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7621         udelay(100);
7622
7623         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7624                 val = tr32(MSGINT_MODE);
7625                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7626                 tw32(MSGINT_MODE, val);
7627         }
7628
7629         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7630                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7631                 udelay(40);
7632         }
7633
7634         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7635                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7636                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7637                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7638                WDMAC_MODE_LNGREAD_ENAB);
7639
7640         /* If statement applies to 5705 and 5750 PCI devices only */
7641         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7642              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7643             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7644                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7645                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7646                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7647                         /* nothing */
7648                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7649                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7650                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7651                         val |= WDMAC_MODE_RX_ACCEL;
7652                 }
7653         }
7654
7655         /* Enable host coalescing bug fix */
7656         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7657                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7658
7659         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7660                 val |= WDMAC_MODE_BURST_ALL_DATA;
7661
7662         tw32_f(WDMAC_MODE, val);
7663         udelay(40);
7664
7665         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7666                 u16 pcix_cmd;
7667
7668                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7669                                      &pcix_cmd);
7670                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7671                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7672                         pcix_cmd |= PCI_X_CMD_READ_2K;
7673                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7674                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7675                         pcix_cmd |= PCI_X_CMD_READ_2K;
7676                 }
7677                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7678                                       pcix_cmd);
7679         }
7680
7681         tw32_f(RDMAC_MODE, rdmac_mode);
7682         udelay(40);
7683
7684         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7685         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7686                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7687
7688         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7689                 tw32(SNDDATAC_MODE,
7690                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7691         else
7692                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7693
7694         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7695         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7696         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7697         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7698         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7699                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7700         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7701         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7702                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7703         tw32(SNDBDI_MODE, val);
7704         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7705
7706         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7707                 err = tg3_load_5701_a0_firmware_fix(tp);
7708                 if (err)
7709                         return err;
7710         }
7711
7712         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7713                 err = tg3_load_tso_firmware(tp);
7714                 if (err)
7715                         return err;
7716         }
7717
7718         tp->tx_mode = TX_MODE_ENABLE;
7719         tw32_f(MAC_TX_MODE, tp->tx_mode);
7720         udelay(100);
7721
7722         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7723                 u32 reg = MAC_RSS_INDIR_TBL_0;
7724                 u8 *ent = (u8 *)&val;
7725
7726                 /* Setup the indirection table */
7727                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7728                         int idx = i % sizeof(val);
7729
7730                         ent[idx] = i % (tp->irq_cnt - 1);
7731                         if (idx == sizeof(val) - 1) {
7732                                 tw32(reg, val);
7733                                 reg += 4;
7734                         }
7735                 }
7736
7737                 /* Setup the "secret" hash key. */
7738                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7739                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7740                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7741                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7742                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7743                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7744                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7745                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7746                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7747                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7748         }
7749
7750         tp->rx_mode = RX_MODE_ENABLE;
7751         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7752                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7753
7754         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7755                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7756                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7757                                RX_MODE_RSS_IPV6_HASH_EN |
7758                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7759                                RX_MODE_RSS_IPV4_HASH_EN |
7760                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7761
7762         tw32_f(MAC_RX_MODE, tp->rx_mode);
7763         udelay(10);
7764
7765         tw32(MAC_LED_CTRL, tp->led_ctrl);
7766
7767         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7768         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7769                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7770                 udelay(10);
7771         }
7772         tw32_f(MAC_RX_MODE, tp->rx_mode);
7773         udelay(10);
7774
7775         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7776                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7777                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7778                         /* Set drive transmission level to 1.2V  */
7779                         /* only if the signal pre-emphasis bit is not set  */
7780                         val = tr32(MAC_SERDES_CFG);
7781                         val &= 0xfffff000;
7782                         val |= 0x880;
7783                         tw32(MAC_SERDES_CFG, val);
7784                 }
7785                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7786                         tw32(MAC_SERDES_CFG, 0x616000);
7787         }
7788
7789         /* Prevent chip from dropping frames when flow control
7790          * is enabled.
7791          */
7792         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7793
7794         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7795             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7796                 /* Use hardware link auto-negotiation */
7797                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7798         }
7799
7800         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7801             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7802                 u32 tmp;
7803
7804                 tmp = tr32(SERDES_RX_CTRL);
7805                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7806                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7807                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7808                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7809         }
7810
7811         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7812                 if (tp->link_config.phy_is_low_power) {
7813                         tp->link_config.phy_is_low_power = 0;
7814                         tp->link_config.speed = tp->link_config.orig_speed;
7815                         tp->link_config.duplex = tp->link_config.orig_duplex;
7816                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7817                 }
7818
7819                 err = tg3_setup_phy(tp, 0);
7820                 if (err)
7821                         return err;
7822
7823                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7824                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7825                         u32 tmp;
7826
7827                         /* Clear CRC stats. */
7828                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7829                                 tg3_writephy(tp, MII_TG3_TEST1,
7830                                              tmp | MII_TG3_TEST1_CRC_EN);
7831                                 tg3_readphy(tp, 0x14, &tmp);
7832                         }
7833                 }
7834         }
7835
7836         __tg3_set_rx_mode(tp->dev);
7837
7838         /* Initialize receive rules. */
7839         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7840         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7841         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7842         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7843
7844         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7845             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7846                 limit = 8;
7847         else
7848                 limit = 16;
7849         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7850                 limit -= 4;
7851         switch (limit) {
7852         case 16:
7853                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7854         case 15:
7855                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7856         case 14:
7857                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7858         case 13:
7859                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7860         case 12:
7861                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7862         case 11:
7863                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7864         case 10:
7865                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7866         case 9:
7867                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7868         case 8:
7869                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7870         case 7:
7871                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7872         case 6:
7873                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7874         case 5:
7875                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7876         case 4:
7877                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7878         case 3:
7879                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7880         case 2:
7881         case 1:
7882
7883         default:
7884                 break;
7885         }
7886
7887         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7888                 /* Write our heartbeat update interval to APE. */
7889                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7890                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7891
7892         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7893
7894         return 0;
7895 }
7896
7897 /* Called at device open time to get the chip ready for
7898  * packet processing.  Invoked with tp->lock held.
7899  */
7900 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7901 {
7902         tg3_switch_clocks(tp);
7903
7904         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7905
7906         return tg3_reset_hw(tp, reset_phy);
7907 }
7908
7909 #define TG3_STAT_ADD32(PSTAT, REG) \
7910 do {    u32 __val = tr32(REG); \
7911         (PSTAT)->low += __val; \
7912         if ((PSTAT)->low < __val) \
7913                 (PSTAT)->high += 1; \
7914 } while (0)
7915
7916 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7917 {
7918         struct tg3_hw_stats *sp = tp->hw_stats;
7919
7920         if (!netif_carrier_ok(tp->dev))
7921                 return;
7922
7923         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7924         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7925         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7926         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7927         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7928         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7929         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7930         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7931         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7932         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7933         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7934         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7935         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7936
7937         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7938         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7939         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7940         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7941         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7942         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7943         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7944         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7945         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7946         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7947         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7948         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7949         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7950         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7951
7952         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7953         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7954         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7955 }
7956
7957 static void tg3_timer(unsigned long __opaque)
7958 {
7959         struct tg3 *tp = (struct tg3 *) __opaque;
7960
7961         if (tp->irq_sync)
7962                 goto restart_timer;
7963
7964         spin_lock(&tp->lock);
7965
7966         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7967                 /* All of this garbage is because when using non-tagged
7968                  * IRQ status the mailbox/status_block protocol the chip
7969                  * uses with the cpu is race prone.
7970                  */
7971                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7972                         tw32(GRC_LOCAL_CTRL,
7973                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7974                 } else {
7975                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7976                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7977                 }
7978
7979                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7980                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7981                         spin_unlock(&tp->lock);
7982                         schedule_work(&tp->reset_task);
7983                         return;
7984                 }
7985         }
7986
7987         /* This part only runs once per second. */
7988         if (!--tp->timer_counter) {
7989                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7990                         tg3_periodic_fetch_stats(tp);
7991
7992                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7993                         u32 mac_stat;
7994                         int phy_event;
7995
7996                         mac_stat = tr32(MAC_STATUS);
7997
7998                         phy_event = 0;
7999                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8000                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8001                                         phy_event = 1;
8002                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8003                                 phy_event = 1;
8004
8005                         if (phy_event)
8006                                 tg3_setup_phy(tp, 0);
8007                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8008                         u32 mac_stat = tr32(MAC_STATUS);
8009                         int need_setup = 0;
8010
8011                         if (netif_carrier_ok(tp->dev) &&
8012                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8013                                 need_setup = 1;
8014                         }
8015                         if (! netif_carrier_ok(tp->dev) &&
8016                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8017                                          MAC_STATUS_SIGNAL_DET))) {
8018                                 need_setup = 1;
8019                         }
8020                         if (need_setup) {
8021                                 if (!tp->serdes_counter) {
8022                                         tw32_f(MAC_MODE,
8023                                              (tp->mac_mode &
8024                                               ~MAC_MODE_PORT_MODE_MASK));
8025                                         udelay(40);
8026                                         tw32_f(MAC_MODE, tp->mac_mode);
8027                                         udelay(40);
8028                                 }
8029                                 tg3_setup_phy(tp, 0);
8030                         }
8031                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8032                         tg3_serdes_parallel_detect(tp);
8033
8034                 tp->timer_counter = tp->timer_multiplier;
8035         }
8036
8037         /* Heartbeat is only sent once every 2 seconds.
8038          *
8039          * The heartbeat is to tell the ASF firmware that the host
8040          * driver is still alive.  In the event that the OS crashes,
8041          * ASF needs to reset the hardware to free up the FIFO space
8042          * that may be filled with rx packets destined for the host.
8043          * If the FIFO is full, ASF will no longer function properly.
8044          *
8045          * Unintended resets have been reported on real time kernels
8046          * where the timer doesn't run on time.  Netpoll will also have
8047          * same problem.
8048          *
8049          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8050          * to check the ring condition when the heartbeat is expiring
8051          * before doing the reset.  This will prevent most unintended
8052          * resets.
8053          */
8054         if (!--tp->asf_counter) {
8055                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8056                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8057                         tg3_wait_for_event_ack(tp);
8058
8059                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8060                                       FWCMD_NICDRV_ALIVE3);
8061                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8062                         /* 5 seconds timeout */
8063                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8064
8065                         tg3_generate_fw_event(tp);
8066                 }
8067                 tp->asf_counter = tp->asf_multiplier;
8068         }
8069
8070         spin_unlock(&tp->lock);
8071
8072 restart_timer:
8073         tp->timer.expires = jiffies + tp->timer_offset;
8074         add_timer(&tp->timer);
8075 }
8076
8077 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8078 {
8079         irq_handler_t fn;
8080         unsigned long flags;
8081         char *name;
8082         struct tg3_napi *tnapi = &tp->napi[irq_num];
8083
8084         if (tp->irq_cnt == 1)
8085                 name = tp->dev->name;
8086         else {
8087                 name = &tnapi->irq_lbl[0];
8088                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8089                 name[IFNAMSIZ-1] = 0;
8090         }
8091
8092         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8093                 fn = tg3_msi;
8094                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8095                         fn = tg3_msi_1shot;
8096                 flags = IRQF_SAMPLE_RANDOM;
8097         } else {
8098                 fn = tg3_interrupt;
8099                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8100                         fn = tg3_interrupt_tagged;
8101                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8102         }
8103
8104         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8105 }
8106
8107 static int tg3_test_interrupt(struct tg3 *tp)
8108 {
8109         struct tg3_napi *tnapi = &tp->napi[0];
8110         struct net_device *dev = tp->dev;
8111         int err, i, intr_ok = 0;
8112         u32 val;
8113
8114         if (!netif_running(dev))
8115                 return -ENODEV;
8116
8117         tg3_disable_ints(tp);
8118
8119         free_irq(tnapi->irq_vec, tnapi);
8120
8121         /*
8122          * Turn off MSI one shot mode.  Otherwise this test has no
8123          * observable way to know whether the interrupt was delivered.
8124          */
8125         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8126             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8127                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8128                 tw32(MSGINT_MODE, val);
8129         }
8130
8131         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8132                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8133         if (err)
8134                 return err;
8135
8136         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8137         tg3_enable_ints(tp);
8138
8139         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8140                tnapi->coal_now);
8141
8142         for (i = 0; i < 5; i++) {
8143                 u32 int_mbox, misc_host_ctrl;
8144
8145                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8146                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8147
8148                 if ((int_mbox != 0) ||
8149                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8150                         intr_ok = 1;
8151                         break;
8152                 }
8153
8154                 msleep(10);
8155         }
8156
8157         tg3_disable_ints(tp);
8158
8159         free_irq(tnapi->irq_vec, tnapi);
8160
8161         err = tg3_request_irq(tp, 0);
8162
8163         if (err)
8164                 return err;
8165
8166         if (intr_ok) {
8167                 /* Reenable MSI one shot mode. */
8168                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8169                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8170                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8171                         tw32(MSGINT_MODE, val);
8172                 }
8173                 return 0;
8174         }
8175
8176         return -EIO;
8177 }
8178
8179 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8180  * successfully restored
8181  */
8182 static int tg3_test_msi(struct tg3 *tp)
8183 {
8184         int err;
8185         u16 pci_cmd;
8186
8187         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8188                 return 0;
8189
8190         /* Turn off SERR reporting in case MSI terminates with Master
8191          * Abort.
8192          */
8193         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8194         pci_write_config_word(tp->pdev, PCI_COMMAND,
8195                               pci_cmd & ~PCI_COMMAND_SERR);
8196
8197         err = tg3_test_interrupt(tp);
8198
8199         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8200
8201         if (!err)
8202                 return 0;
8203
8204         /* other failures */
8205         if (err != -EIO)
8206                 return err;
8207
8208         /* MSI test failed, go back to INTx mode */
8209         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8210                "switching to INTx mode. Please report this failure to "
8211                "the PCI maintainer and include system chipset information.\n",
8212                        tp->dev->name);
8213
8214         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8215
8216         pci_disable_msi(tp->pdev);
8217
8218         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8219
8220         err = tg3_request_irq(tp, 0);
8221         if (err)
8222                 return err;
8223
8224         /* Need to reset the chip because the MSI cycle may have terminated
8225          * with Master Abort.
8226          */
8227         tg3_full_lock(tp, 1);
8228
8229         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8230         err = tg3_init_hw(tp, 1);
8231
8232         tg3_full_unlock(tp);
8233
8234         if (err)
8235                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8236
8237         return err;
8238 }
8239
8240 static int tg3_request_firmware(struct tg3 *tp)
8241 {
8242         const __be32 *fw_data;
8243
8244         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8245                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8246                        tp->dev->name, tp->fw_needed);
8247                 return -ENOENT;
8248         }
8249
8250         fw_data = (void *)tp->fw->data;
8251
8252         /* Firmware blob starts with version numbers, followed by
8253          * start address and _full_ length including BSS sections
8254          * (which must be longer than the actual data, of course
8255          */
8256
8257         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8258         if (tp->fw_len < (tp->fw->size - 12)) {
8259                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8260                        tp->dev->name, tp->fw_len, tp->fw_needed);
8261                 release_firmware(tp->fw);
8262                 tp->fw = NULL;
8263                 return -EINVAL;
8264         }
8265
8266         /* We no longer need firmware; we have it. */
8267         tp->fw_needed = NULL;
8268         return 0;
8269 }
8270
8271 static bool tg3_enable_msix(struct tg3 *tp)
8272 {
8273         int i, rc, cpus = num_online_cpus();
8274         struct msix_entry msix_ent[tp->irq_max];
8275
8276         if (cpus == 1)
8277                 /* Just fallback to the simpler MSI mode. */
8278                 return false;
8279
8280         /*
8281          * We want as many rx rings enabled as there are cpus.
8282          * The first MSIX vector only deals with link interrupts, etc,
8283          * so we add one to the number of vectors we are requesting.
8284          */
8285         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8286
8287         for (i = 0; i < tp->irq_max; i++) {
8288                 msix_ent[i].entry  = i;
8289                 msix_ent[i].vector = 0;
8290         }
8291
8292         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8293         if (rc != 0) {
8294                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8295                         return false;
8296                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8297                         return false;
8298                 printk(KERN_NOTICE
8299                        "%s: Requested %d MSI-X vectors, received %d\n",
8300                        tp->dev->name, tp->irq_cnt, rc);
8301                 tp->irq_cnt = rc;
8302         }
8303
8304         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8305
8306         for (i = 0; i < tp->irq_max; i++)
8307                 tp->napi[i].irq_vec = msix_ent[i].vector;
8308
8309         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8310
8311         return true;
8312 }
8313
8314 static void tg3_ints_init(struct tg3 *tp)
8315 {
8316         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8317             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8318                 /* All MSI supporting chips should support tagged
8319                  * status.  Assert that this is the case.
8320                  */
8321                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8322                        "Not using MSI.\n", tp->dev->name);
8323                 goto defcfg;
8324         }
8325
8326         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8327                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8328         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8329                  pci_enable_msi(tp->pdev) == 0)
8330                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8331
8332         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8333                 u32 msi_mode = tr32(MSGINT_MODE);
8334                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8335                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8336                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8337         }
8338 defcfg:
8339         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8340                 tp->irq_cnt = 1;
8341                 tp->napi[0].irq_vec = tp->pdev->irq;
8342                 tp->dev->real_num_tx_queues = 1;
8343         }
8344 }
8345
8346 static void tg3_ints_fini(struct tg3 *tp)
8347 {
8348         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8349                 pci_disable_msix(tp->pdev);
8350         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8351                 pci_disable_msi(tp->pdev);
8352         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8353         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8354 }
8355
8356 static int tg3_open(struct net_device *dev)
8357 {
8358         struct tg3 *tp = netdev_priv(dev);
8359         int i, err;
8360
8361         if (tp->fw_needed) {
8362                 err = tg3_request_firmware(tp);
8363                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8364                         if (err)
8365                                 return err;
8366                 } else if (err) {
8367                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8368                                tp->dev->name);
8369                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8370                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8371                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8372                                tp->dev->name);
8373                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8374                 }
8375         }
8376
8377         netif_carrier_off(tp->dev);
8378
8379         err = tg3_set_power_state(tp, PCI_D0);
8380         if (err)
8381                 return err;
8382
8383         tg3_full_lock(tp, 0);
8384
8385         tg3_disable_ints(tp);
8386         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8387
8388         tg3_full_unlock(tp);
8389
8390         /*
8391          * Setup interrupts first so we know how
8392          * many NAPI resources to allocate
8393          */
8394         tg3_ints_init(tp);
8395
8396         /* The placement of this call is tied
8397          * to the setup and use of Host TX descriptors.
8398          */
8399         err = tg3_alloc_consistent(tp);
8400         if (err)
8401                 goto err_out1;
8402
8403         tg3_napi_enable(tp);
8404
8405         for (i = 0; i < tp->irq_cnt; i++) {
8406                 struct tg3_napi *tnapi = &tp->napi[i];
8407                 err = tg3_request_irq(tp, i);
8408                 if (err) {
8409                         for (i--; i >= 0; i--)
8410                                 free_irq(tnapi->irq_vec, tnapi);
8411                         break;
8412                 }
8413         }
8414
8415         if (err)
8416                 goto err_out2;
8417
8418         tg3_full_lock(tp, 0);
8419
8420         err = tg3_init_hw(tp, 1);
8421         if (err) {
8422                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8423                 tg3_free_rings(tp);
8424         } else {
8425                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8426                         tp->timer_offset = HZ;
8427                 else
8428                         tp->timer_offset = HZ / 10;
8429
8430                 BUG_ON(tp->timer_offset > HZ);
8431                 tp->timer_counter = tp->timer_multiplier =
8432                         (HZ / tp->timer_offset);
8433                 tp->asf_counter = tp->asf_multiplier =
8434                         ((HZ / tp->timer_offset) * 2);
8435
8436                 init_timer(&tp->timer);
8437                 tp->timer.expires = jiffies + tp->timer_offset;
8438                 tp->timer.data = (unsigned long) tp;
8439                 tp->timer.function = tg3_timer;
8440         }
8441
8442         tg3_full_unlock(tp);
8443
8444         if (err)
8445                 goto err_out3;
8446
8447         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8448                 err = tg3_test_msi(tp);
8449
8450                 if (err) {
8451                         tg3_full_lock(tp, 0);
8452                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8453                         tg3_free_rings(tp);
8454                         tg3_full_unlock(tp);
8455
8456                         goto err_out2;
8457                 }
8458
8459                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8460                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8461                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8462                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8463
8464                         tw32(PCIE_TRANSACTION_CFG,
8465                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8466                 }
8467         }
8468
8469         tg3_phy_start(tp);
8470
8471         tg3_full_lock(tp, 0);
8472
8473         add_timer(&tp->timer);
8474         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8475         tg3_enable_ints(tp);
8476
8477         tg3_full_unlock(tp);
8478
8479         netif_tx_start_all_queues(dev);
8480
8481         return 0;
8482
8483 err_out3:
8484         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8485                 struct tg3_napi *tnapi = &tp->napi[i];
8486                 free_irq(tnapi->irq_vec, tnapi);
8487         }
8488
8489 err_out2:
8490         tg3_napi_disable(tp);
8491         tg3_free_consistent(tp);
8492
8493 err_out1:
8494         tg3_ints_fini(tp);
8495         return err;
8496 }
8497
8498 #if 0
8499 /*static*/ void tg3_dump_state(struct tg3 *tp)
8500 {
8501         u32 val32, val32_2, val32_3, val32_4, val32_5;
8502         u16 val16;
8503         int i;
8504         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8505
8506         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8507         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8508         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8509                val16, val32);
8510
8511         /* MAC block */
8512         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8513                tr32(MAC_MODE), tr32(MAC_STATUS));
8514         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8515                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8516         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8517                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8518         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8519                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8520
8521         /* Send data initiator control block */
8522         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8523                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8524         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8525                tr32(SNDDATAI_STATSCTRL));
8526
8527         /* Send data completion control block */
8528         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8529
8530         /* Send BD ring selector block */
8531         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8532                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8533
8534         /* Send BD initiator control block */
8535         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8536                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8537
8538         /* Send BD completion control block */
8539         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8540
8541         /* Receive list placement control block */
8542         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8543                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8544         printk("       RCVLPC_STATSCTRL[%08x]\n",
8545                tr32(RCVLPC_STATSCTRL));
8546
8547         /* Receive data and receive BD initiator control block */
8548         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8549                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8550
8551         /* Receive data completion control block */
8552         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8553                tr32(RCVDCC_MODE));
8554
8555         /* Receive BD initiator control block */
8556         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8557                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8558
8559         /* Receive BD completion control block */
8560         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8561                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8562
8563         /* Receive list selector control block */
8564         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8565                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8566
8567         /* Mbuf cluster free block */
8568         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8569                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8570
8571         /* Host coalescing control block */
8572         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8573                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8574         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8575                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8576                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8577         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8578                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8579                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8580         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8581                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8582         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8583                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8584
8585         /* Memory arbiter control block */
8586         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8587                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8588
8589         /* Buffer manager control block */
8590         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8591                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8592         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8593                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8594         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8595                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8596                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8597                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8598
8599         /* Read DMA control block */
8600         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8601                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8602
8603         /* Write DMA control block */
8604         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8605                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8606
8607         /* DMA completion block */
8608         printk("DEBUG: DMAC_MODE[%08x]\n",
8609                tr32(DMAC_MODE));
8610
8611         /* GRC block */
8612         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8613                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8614         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8615                tr32(GRC_LOCAL_CTRL));
8616
8617         /* TG3_BDINFOs */
8618         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8619                tr32(RCVDBDI_JUMBO_BD + 0x0),
8620                tr32(RCVDBDI_JUMBO_BD + 0x4),
8621                tr32(RCVDBDI_JUMBO_BD + 0x8),
8622                tr32(RCVDBDI_JUMBO_BD + 0xc));
8623         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8624                tr32(RCVDBDI_STD_BD + 0x0),
8625                tr32(RCVDBDI_STD_BD + 0x4),
8626                tr32(RCVDBDI_STD_BD + 0x8),
8627                tr32(RCVDBDI_STD_BD + 0xc));
8628         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8629                tr32(RCVDBDI_MINI_BD + 0x0),
8630                tr32(RCVDBDI_MINI_BD + 0x4),
8631                tr32(RCVDBDI_MINI_BD + 0x8),
8632                tr32(RCVDBDI_MINI_BD + 0xc));
8633
8634         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8635         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8636         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8637         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8638         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8639                val32, val32_2, val32_3, val32_4);
8640
8641         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8642         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8643         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8644         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8645         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8646                val32, val32_2, val32_3, val32_4);
8647
8648         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8649         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8650         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8651         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8652         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8653         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8654                val32, val32_2, val32_3, val32_4, val32_5);
8655
8656         /* SW status block */
8657         printk(KERN_DEBUG
8658          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8659                sblk->status,
8660                sblk->status_tag,
8661                sblk->rx_jumbo_consumer,
8662                sblk->rx_consumer,
8663                sblk->rx_mini_consumer,
8664                sblk->idx[0].rx_producer,
8665                sblk->idx[0].tx_consumer);
8666
8667         /* SW statistics block */
8668         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8669                ((u32 *)tp->hw_stats)[0],
8670                ((u32 *)tp->hw_stats)[1],
8671                ((u32 *)tp->hw_stats)[2],
8672                ((u32 *)tp->hw_stats)[3]);
8673
8674         /* Mailboxes */
8675         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8676                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8677                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8678                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8679                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8680
8681         /* NIC side send descriptors. */
8682         for (i = 0; i < 6; i++) {
8683                 unsigned long txd;
8684
8685                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8686                         + (i * sizeof(struct tg3_tx_buffer_desc));
8687                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8688                        i,
8689                        readl(txd + 0x0), readl(txd + 0x4),
8690                        readl(txd + 0x8), readl(txd + 0xc));
8691         }
8692
8693         /* NIC side RX descriptors. */
8694         for (i = 0; i < 6; i++) {
8695                 unsigned long rxd;
8696
8697                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8698                         + (i * sizeof(struct tg3_rx_buffer_desc));
8699                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8700                        i,
8701                        readl(rxd + 0x0), readl(rxd + 0x4),
8702                        readl(rxd + 0x8), readl(rxd + 0xc));
8703                 rxd += (4 * sizeof(u32));
8704                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8705                        i,
8706                        readl(rxd + 0x0), readl(rxd + 0x4),
8707                        readl(rxd + 0x8), readl(rxd + 0xc));
8708         }
8709
8710         for (i = 0; i < 6; i++) {
8711                 unsigned long rxd;
8712
8713                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8714                         + (i * sizeof(struct tg3_rx_buffer_desc));
8715                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8716                        i,
8717                        readl(rxd + 0x0), readl(rxd + 0x4),
8718                        readl(rxd + 0x8), readl(rxd + 0xc));
8719                 rxd += (4 * sizeof(u32));
8720                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8721                        i,
8722                        readl(rxd + 0x0), readl(rxd + 0x4),
8723                        readl(rxd + 0x8), readl(rxd + 0xc));
8724         }
8725 }
8726 #endif
8727
8728 static struct net_device_stats *tg3_get_stats(struct net_device *);
8729 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8730
8731 static int tg3_close(struct net_device *dev)
8732 {
8733         int i;
8734         struct tg3 *tp = netdev_priv(dev);
8735
8736         tg3_napi_disable(tp);
8737         cancel_work_sync(&tp->reset_task);
8738
8739         netif_tx_stop_all_queues(dev);
8740
8741         del_timer_sync(&tp->timer);
8742
8743         tg3_phy_stop(tp);
8744
8745         tg3_full_lock(tp, 1);
8746 #if 0
8747         tg3_dump_state(tp);
8748 #endif
8749
8750         tg3_disable_ints(tp);
8751
8752         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8753         tg3_free_rings(tp);
8754         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8755
8756         tg3_full_unlock(tp);
8757
8758         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8759                 struct tg3_napi *tnapi = &tp->napi[i];
8760                 free_irq(tnapi->irq_vec, tnapi);
8761         }
8762
8763         tg3_ints_fini(tp);
8764
8765         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8766                sizeof(tp->net_stats_prev));
8767         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8768                sizeof(tp->estats_prev));
8769
8770         tg3_free_consistent(tp);
8771
8772         tg3_set_power_state(tp, PCI_D3hot);
8773
8774         netif_carrier_off(tp->dev);
8775
8776         return 0;
8777 }
8778
8779 static inline unsigned long get_stat64(tg3_stat64_t *val)
8780 {
8781         unsigned long ret;
8782
8783 #if (BITS_PER_LONG == 32)
8784         ret = val->low;
8785 #else
8786         ret = ((u64)val->high << 32) | ((u64)val->low);
8787 #endif
8788         return ret;
8789 }
8790
8791 static inline u64 get_estat64(tg3_stat64_t *val)
8792 {
8793        return ((u64)val->high << 32) | ((u64)val->low);
8794 }
8795
8796 static unsigned long calc_crc_errors(struct tg3 *tp)
8797 {
8798         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8799
8800         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8801             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8802              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8803                 u32 val;
8804
8805                 spin_lock_bh(&tp->lock);
8806                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8807                         tg3_writephy(tp, MII_TG3_TEST1,
8808                                      val | MII_TG3_TEST1_CRC_EN);
8809                         tg3_readphy(tp, 0x14, &val);
8810                 } else
8811                         val = 0;
8812                 spin_unlock_bh(&tp->lock);
8813
8814                 tp->phy_crc_errors += val;
8815
8816                 return tp->phy_crc_errors;
8817         }
8818
8819         return get_stat64(&hw_stats->rx_fcs_errors);
8820 }
8821
8822 #define ESTAT_ADD(member) \
8823         estats->member =        old_estats->member + \
8824                                 get_estat64(&hw_stats->member)
8825
8826 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8827 {
8828         struct tg3_ethtool_stats *estats = &tp->estats;
8829         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8830         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8831
8832         if (!hw_stats)
8833                 return old_estats;
8834
8835         ESTAT_ADD(rx_octets);
8836         ESTAT_ADD(rx_fragments);
8837         ESTAT_ADD(rx_ucast_packets);
8838         ESTAT_ADD(rx_mcast_packets);
8839         ESTAT_ADD(rx_bcast_packets);
8840         ESTAT_ADD(rx_fcs_errors);
8841         ESTAT_ADD(rx_align_errors);
8842         ESTAT_ADD(rx_xon_pause_rcvd);
8843         ESTAT_ADD(rx_xoff_pause_rcvd);
8844         ESTAT_ADD(rx_mac_ctrl_rcvd);
8845         ESTAT_ADD(rx_xoff_entered);
8846         ESTAT_ADD(rx_frame_too_long_errors);
8847         ESTAT_ADD(rx_jabbers);
8848         ESTAT_ADD(rx_undersize_packets);
8849         ESTAT_ADD(rx_in_length_errors);
8850         ESTAT_ADD(rx_out_length_errors);
8851         ESTAT_ADD(rx_64_or_less_octet_packets);
8852         ESTAT_ADD(rx_65_to_127_octet_packets);
8853         ESTAT_ADD(rx_128_to_255_octet_packets);
8854         ESTAT_ADD(rx_256_to_511_octet_packets);
8855         ESTAT_ADD(rx_512_to_1023_octet_packets);
8856         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8857         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8858         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8859         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8860         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8861
8862         ESTAT_ADD(tx_octets);
8863         ESTAT_ADD(tx_collisions);
8864         ESTAT_ADD(tx_xon_sent);
8865         ESTAT_ADD(tx_xoff_sent);
8866         ESTAT_ADD(tx_flow_control);
8867         ESTAT_ADD(tx_mac_errors);
8868         ESTAT_ADD(tx_single_collisions);
8869         ESTAT_ADD(tx_mult_collisions);
8870         ESTAT_ADD(tx_deferred);
8871         ESTAT_ADD(tx_excessive_collisions);
8872         ESTAT_ADD(tx_late_collisions);
8873         ESTAT_ADD(tx_collide_2times);
8874         ESTAT_ADD(tx_collide_3times);
8875         ESTAT_ADD(tx_collide_4times);
8876         ESTAT_ADD(tx_collide_5times);
8877         ESTAT_ADD(tx_collide_6times);
8878         ESTAT_ADD(tx_collide_7times);
8879         ESTAT_ADD(tx_collide_8times);
8880         ESTAT_ADD(tx_collide_9times);
8881         ESTAT_ADD(tx_collide_10times);
8882         ESTAT_ADD(tx_collide_11times);
8883         ESTAT_ADD(tx_collide_12times);
8884         ESTAT_ADD(tx_collide_13times);
8885         ESTAT_ADD(tx_collide_14times);
8886         ESTAT_ADD(tx_collide_15times);
8887         ESTAT_ADD(tx_ucast_packets);
8888         ESTAT_ADD(tx_mcast_packets);
8889         ESTAT_ADD(tx_bcast_packets);
8890         ESTAT_ADD(tx_carrier_sense_errors);
8891         ESTAT_ADD(tx_discards);
8892         ESTAT_ADD(tx_errors);
8893
8894         ESTAT_ADD(dma_writeq_full);
8895         ESTAT_ADD(dma_write_prioq_full);
8896         ESTAT_ADD(rxbds_empty);
8897         ESTAT_ADD(rx_discards);
8898         ESTAT_ADD(rx_errors);
8899         ESTAT_ADD(rx_threshold_hit);
8900
8901         ESTAT_ADD(dma_readq_full);
8902         ESTAT_ADD(dma_read_prioq_full);
8903         ESTAT_ADD(tx_comp_queue_full);
8904
8905         ESTAT_ADD(ring_set_send_prod_index);
8906         ESTAT_ADD(ring_status_update);
8907         ESTAT_ADD(nic_irqs);
8908         ESTAT_ADD(nic_avoided_irqs);
8909         ESTAT_ADD(nic_tx_threshold_hit);
8910
8911         return estats;
8912 }
8913
8914 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8915 {
8916         struct tg3 *tp = netdev_priv(dev);
8917         struct net_device_stats *stats = &tp->net_stats;
8918         struct net_device_stats *old_stats = &tp->net_stats_prev;
8919         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8920
8921         if (!hw_stats)
8922                 return old_stats;
8923
8924         stats->rx_packets = old_stats->rx_packets +
8925                 get_stat64(&hw_stats->rx_ucast_packets) +
8926                 get_stat64(&hw_stats->rx_mcast_packets) +
8927                 get_stat64(&hw_stats->rx_bcast_packets);
8928
8929         stats->tx_packets = old_stats->tx_packets +
8930                 get_stat64(&hw_stats->tx_ucast_packets) +
8931                 get_stat64(&hw_stats->tx_mcast_packets) +
8932                 get_stat64(&hw_stats->tx_bcast_packets);
8933
8934         stats->rx_bytes = old_stats->rx_bytes +
8935                 get_stat64(&hw_stats->rx_octets);
8936         stats->tx_bytes = old_stats->tx_bytes +
8937                 get_stat64(&hw_stats->tx_octets);
8938
8939         stats->rx_errors = old_stats->rx_errors +
8940                 get_stat64(&hw_stats->rx_errors);
8941         stats->tx_errors = old_stats->tx_errors +
8942                 get_stat64(&hw_stats->tx_errors) +
8943                 get_stat64(&hw_stats->tx_mac_errors) +
8944                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8945                 get_stat64(&hw_stats->tx_discards);
8946
8947         stats->multicast = old_stats->multicast +
8948                 get_stat64(&hw_stats->rx_mcast_packets);
8949         stats->collisions = old_stats->collisions +
8950                 get_stat64(&hw_stats->tx_collisions);
8951
8952         stats->rx_length_errors = old_stats->rx_length_errors +
8953                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8954                 get_stat64(&hw_stats->rx_undersize_packets);
8955
8956         stats->rx_over_errors = old_stats->rx_over_errors +
8957                 get_stat64(&hw_stats->rxbds_empty);
8958         stats->rx_frame_errors = old_stats->rx_frame_errors +
8959                 get_stat64(&hw_stats->rx_align_errors);
8960         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8961                 get_stat64(&hw_stats->tx_discards);
8962         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8963                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8964
8965         stats->rx_crc_errors = old_stats->rx_crc_errors +
8966                 calc_crc_errors(tp);
8967
8968         stats->rx_missed_errors = old_stats->rx_missed_errors +
8969                 get_stat64(&hw_stats->rx_discards);
8970
8971         return stats;
8972 }
8973
8974 static inline u32 calc_crc(unsigned char *buf, int len)
8975 {
8976         u32 reg;
8977         u32 tmp;
8978         int j, k;
8979
8980         reg = 0xffffffff;
8981
8982         for (j = 0; j < len; j++) {
8983                 reg ^= buf[j];
8984
8985                 for (k = 0; k < 8; k++) {
8986                         tmp = reg & 0x01;
8987
8988                         reg >>= 1;
8989
8990                         if (tmp) {
8991                                 reg ^= 0xedb88320;
8992                         }
8993                 }
8994         }
8995
8996         return ~reg;
8997 }
8998
8999 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9000 {
9001         /* accept or reject all multicast frames */
9002         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9003         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9004         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9005         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9006 }
9007
9008 static void __tg3_set_rx_mode(struct net_device *dev)
9009 {
9010         struct tg3 *tp = netdev_priv(dev);
9011         u32 rx_mode;
9012
9013         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9014                                   RX_MODE_KEEP_VLAN_TAG);
9015
9016         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9017          * flag clear.
9018          */
9019 #if TG3_VLAN_TAG_USED
9020         if (!tp->vlgrp &&
9021             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9022                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9023 #else
9024         /* By definition, VLAN is disabled always in this
9025          * case.
9026          */
9027         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9028                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9029 #endif
9030
9031         if (dev->flags & IFF_PROMISC) {
9032                 /* Promiscuous mode. */
9033                 rx_mode |= RX_MODE_PROMISC;
9034         } else if (dev->flags & IFF_ALLMULTI) {
9035                 /* Accept all multicast. */
9036                 tg3_set_multi (tp, 1);
9037         } else if (dev->mc_count < 1) {
9038                 /* Reject all multicast. */
9039                 tg3_set_multi (tp, 0);
9040         } else {
9041                 /* Accept one or more multicast(s). */
9042                 struct dev_mc_list *mclist;
9043                 unsigned int i;
9044                 u32 mc_filter[4] = { 0, };
9045                 u32 regidx;
9046                 u32 bit;
9047                 u32 crc;
9048
9049                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9050                      i++, mclist = mclist->next) {
9051
9052                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9053                         bit = ~crc & 0x7f;
9054                         regidx = (bit & 0x60) >> 5;
9055                         bit &= 0x1f;
9056                         mc_filter[regidx] |= (1 << bit);
9057                 }
9058
9059                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9060                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9061                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9062                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9063         }
9064
9065         if (rx_mode != tp->rx_mode) {
9066                 tp->rx_mode = rx_mode;
9067                 tw32_f(MAC_RX_MODE, rx_mode);
9068                 udelay(10);
9069         }
9070 }
9071
9072 static void tg3_set_rx_mode(struct net_device *dev)
9073 {
9074         struct tg3 *tp = netdev_priv(dev);
9075
9076         if (!netif_running(dev))
9077                 return;
9078
9079         tg3_full_lock(tp, 0);
9080         __tg3_set_rx_mode(dev);
9081         tg3_full_unlock(tp);
9082 }
9083
9084 #define TG3_REGDUMP_LEN         (32 * 1024)
9085
9086 static int tg3_get_regs_len(struct net_device *dev)
9087 {
9088         return TG3_REGDUMP_LEN;
9089 }
9090
9091 static void tg3_get_regs(struct net_device *dev,
9092                 struct ethtool_regs *regs, void *_p)
9093 {
9094         u32 *p = _p;
9095         struct tg3 *tp = netdev_priv(dev);
9096         u8 *orig_p = _p;
9097         int i;
9098
9099         regs->version = 0;
9100
9101         memset(p, 0, TG3_REGDUMP_LEN);
9102
9103         if (tp->link_config.phy_is_low_power)
9104                 return;
9105
9106         tg3_full_lock(tp, 0);
9107
9108 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9109 #define GET_REG32_LOOP(base,len)                \
9110 do {    p = (u32 *)(orig_p + (base));           \
9111         for (i = 0; i < len; i += 4)            \
9112                 __GET_REG32((base) + i);        \
9113 } while (0)
9114 #define GET_REG32_1(reg)                        \
9115 do {    p = (u32 *)(orig_p + (reg));            \
9116         __GET_REG32((reg));                     \
9117 } while (0)
9118
9119         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9120         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9121         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9122         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9123         GET_REG32_1(SNDDATAC_MODE);
9124         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9125         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9126         GET_REG32_1(SNDBDC_MODE);
9127         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9128         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9129         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9130         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9131         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9132         GET_REG32_1(RCVDCC_MODE);
9133         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9134         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9135         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9136         GET_REG32_1(MBFREE_MODE);
9137         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9138         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9139         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9140         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9141         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9142         GET_REG32_1(RX_CPU_MODE);
9143         GET_REG32_1(RX_CPU_STATE);
9144         GET_REG32_1(RX_CPU_PGMCTR);
9145         GET_REG32_1(RX_CPU_HWBKPT);
9146         GET_REG32_1(TX_CPU_MODE);
9147         GET_REG32_1(TX_CPU_STATE);
9148         GET_REG32_1(TX_CPU_PGMCTR);
9149         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9150         GET_REG32_LOOP(FTQ_RESET, 0x120);
9151         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9152         GET_REG32_1(DMAC_MODE);
9153         GET_REG32_LOOP(GRC_MODE, 0x4c);
9154         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9155                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9156
9157 #undef __GET_REG32
9158 #undef GET_REG32_LOOP
9159 #undef GET_REG32_1
9160
9161         tg3_full_unlock(tp);
9162 }
9163
9164 static int tg3_get_eeprom_len(struct net_device *dev)
9165 {
9166         struct tg3 *tp = netdev_priv(dev);
9167
9168         return tp->nvram_size;
9169 }
9170
9171 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9172 {
9173         struct tg3 *tp = netdev_priv(dev);
9174         int ret;
9175         u8  *pd;
9176         u32 i, offset, len, b_offset, b_count;
9177         __be32 val;
9178
9179         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9180                 return -EINVAL;
9181
9182         if (tp->link_config.phy_is_low_power)
9183                 return -EAGAIN;
9184
9185         offset = eeprom->offset;
9186         len = eeprom->len;
9187         eeprom->len = 0;
9188
9189         eeprom->magic = TG3_EEPROM_MAGIC;
9190
9191         if (offset & 3) {
9192                 /* adjustments to start on required 4 byte boundary */
9193                 b_offset = offset & 3;
9194                 b_count = 4 - b_offset;
9195                 if (b_count > len) {
9196                         /* i.e. offset=1 len=2 */
9197                         b_count = len;
9198                 }
9199                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9200                 if (ret)
9201                         return ret;
9202                 memcpy(data, ((char*)&val) + b_offset, b_count);
9203                 len -= b_count;
9204                 offset += b_count;
9205                 eeprom->len += b_count;
9206         }
9207
9208         /* read bytes upto the last 4 byte boundary */
9209         pd = &data[eeprom->len];
9210         for (i = 0; i < (len - (len & 3)); i += 4) {
9211                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9212                 if (ret) {
9213                         eeprom->len += i;
9214                         return ret;
9215                 }
9216                 memcpy(pd + i, &val, 4);
9217         }
9218         eeprom->len += i;
9219
9220         if (len & 3) {
9221                 /* read last bytes not ending on 4 byte boundary */
9222                 pd = &data[eeprom->len];
9223                 b_count = len & 3;
9224                 b_offset = offset + len - b_count;
9225                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9226                 if (ret)
9227                         return ret;
9228                 memcpy(pd, &val, b_count);
9229                 eeprom->len += b_count;
9230         }
9231         return 0;
9232 }
9233
9234 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9235
9236 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9237 {
9238         struct tg3 *tp = netdev_priv(dev);
9239         int ret;
9240         u32 offset, len, b_offset, odd_len;
9241         u8 *buf;
9242         __be32 start, end;
9243
9244         if (tp->link_config.phy_is_low_power)
9245                 return -EAGAIN;
9246
9247         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9248             eeprom->magic != TG3_EEPROM_MAGIC)
9249                 return -EINVAL;
9250
9251         offset = eeprom->offset;
9252         len = eeprom->len;
9253
9254         if ((b_offset = (offset & 3))) {
9255                 /* adjustments to start on required 4 byte boundary */
9256                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9257                 if (ret)
9258                         return ret;
9259                 len += b_offset;
9260                 offset &= ~3;
9261                 if (len < 4)
9262                         len = 4;
9263         }
9264
9265         odd_len = 0;
9266         if (len & 3) {
9267                 /* adjustments to end on required 4 byte boundary */
9268                 odd_len = 1;
9269                 len = (len + 3) & ~3;
9270                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9271                 if (ret)
9272                         return ret;
9273         }
9274
9275         buf = data;
9276         if (b_offset || odd_len) {
9277                 buf = kmalloc(len, GFP_KERNEL);
9278                 if (!buf)
9279                         return -ENOMEM;
9280                 if (b_offset)
9281                         memcpy(buf, &start, 4);
9282                 if (odd_len)
9283                         memcpy(buf+len-4, &end, 4);
9284                 memcpy(buf + b_offset, data, eeprom->len);
9285         }
9286
9287         ret = tg3_nvram_write_block(tp, offset, len, buf);
9288
9289         if (buf != data)
9290                 kfree(buf);
9291
9292         return ret;
9293 }
9294
9295 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9296 {
9297         struct tg3 *tp = netdev_priv(dev);
9298
9299         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9300                 struct phy_device *phydev;
9301                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9302                         return -EAGAIN;
9303                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9304                 return phy_ethtool_gset(phydev, cmd);
9305         }
9306
9307         cmd->supported = (SUPPORTED_Autoneg);
9308
9309         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9310                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9311                                    SUPPORTED_1000baseT_Full);
9312
9313         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9314                 cmd->supported |= (SUPPORTED_100baseT_Half |
9315                                   SUPPORTED_100baseT_Full |
9316                                   SUPPORTED_10baseT_Half |
9317                                   SUPPORTED_10baseT_Full |
9318                                   SUPPORTED_TP);
9319                 cmd->port = PORT_TP;
9320         } else {
9321                 cmd->supported |= SUPPORTED_FIBRE;
9322                 cmd->port = PORT_FIBRE;
9323         }
9324
9325         cmd->advertising = tp->link_config.advertising;
9326         if (netif_running(dev)) {
9327                 cmd->speed = tp->link_config.active_speed;
9328                 cmd->duplex = tp->link_config.active_duplex;
9329         }
9330         cmd->phy_address = tp->phy_addr;
9331         cmd->transceiver = XCVR_INTERNAL;
9332         cmd->autoneg = tp->link_config.autoneg;
9333         cmd->maxtxpkt = 0;
9334         cmd->maxrxpkt = 0;
9335         return 0;
9336 }
9337
9338 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9339 {
9340         struct tg3 *tp = netdev_priv(dev);
9341
9342         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9343                 struct phy_device *phydev;
9344                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9345                         return -EAGAIN;
9346                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9347                 return phy_ethtool_sset(phydev, cmd);
9348         }
9349
9350         if (cmd->autoneg != AUTONEG_ENABLE &&
9351             cmd->autoneg != AUTONEG_DISABLE)
9352                 return -EINVAL;
9353
9354         if (cmd->autoneg == AUTONEG_DISABLE &&
9355             cmd->duplex != DUPLEX_FULL &&
9356             cmd->duplex != DUPLEX_HALF)
9357                 return -EINVAL;
9358
9359         if (cmd->autoneg == AUTONEG_ENABLE) {
9360                 u32 mask = ADVERTISED_Autoneg |
9361                            ADVERTISED_Pause |
9362                            ADVERTISED_Asym_Pause;
9363
9364                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9365                         mask |= ADVERTISED_1000baseT_Half |
9366                                 ADVERTISED_1000baseT_Full;
9367
9368                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9369                         mask |= ADVERTISED_100baseT_Half |
9370                                 ADVERTISED_100baseT_Full |
9371                                 ADVERTISED_10baseT_Half |
9372                                 ADVERTISED_10baseT_Full |
9373                                 ADVERTISED_TP;
9374                 else
9375                         mask |= ADVERTISED_FIBRE;
9376
9377                 if (cmd->advertising & ~mask)
9378                         return -EINVAL;
9379
9380                 mask &= (ADVERTISED_1000baseT_Half |
9381                          ADVERTISED_1000baseT_Full |
9382                          ADVERTISED_100baseT_Half |
9383                          ADVERTISED_100baseT_Full |
9384                          ADVERTISED_10baseT_Half |
9385                          ADVERTISED_10baseT_Full);
9386
9387                 cmd->advertising &= mask;
9388         } else {
9389                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9390                         if (cmd->speed != SPEED_1000)
9391                                 return -EINVAL;
9392
9393                         if (cmd->duplex != DUPLEX_FULL)
9394                                 return -EINVAL;
9395                 } else {
9396                         if (cmd->speed != SPEED_100 &&
9397                             cmd->speed != SPEED_10)
9398                                 return -EINVAL;
9399                 }
9400         }
9401
9402         tg3_full_lock(tp, 0);
9403
9404         tp->link_config.autoneg = cmd->autoneg;
9405         if (cmd->autoneg == AUTONEG_ENABLE) {
9406                 tp->link_config.advertising = (cmd->advertising |
9407                                               ADVERTISED_Autoneg);
9408                 tp->link_config.speed = SPEED_INVALID;
9409                 tp->link_config.duplex = DUPLEX_INVALID;
9410         } else {
9411                 tp->link_config.advertising = 0;
9412                 tp->link_config.speed = cmd->speed;
9413                 tp->link_config.duplex = cmd->duplex;
9414         }
9415
9416         tp->link_config.orig_speed = tp->link_config.speed;
9417         tp->link_config.orig_duplex = tp->link_config.duplex;
9418         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9419
9420         if (netif_running(dev))
9421                 tg3_setup_phy(tp, 1);
9422
9423         tg3_full_unlock(tp);
9424
9425         return 0;
9426 }
9427
9428 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9429 {
9430         struct tg3 *tp = netdev_priv(dev);
9431
9432         strcpy(info->driver, DRV_MODULE_NAME);
9433         strcpy(info->version, DRV_MODULE_VERSION);
9434         strcpy(info->fw_version, tp->fw_ver);
9435         strcpy(info->bus_info, pci_name(tp->pdev));
9436 }
9437
9438 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9439 {
9440         struct tg3 *tp = netdev_priv(dev);
9441
9442         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9443             device_can_wakeup(&tp->pdev->dev))
9444                 wol->supported = WAKE_MAGIC;
9445         else
9446                 wol->supported = 0;
9447         wol->wolopts = 0;
9448         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9449             device_can_wakeup(&tp->pdev->dev))
9450                 wol->wolopts = WAKE_MAGIC;
9451         memset(&wol->sopass, 0, sizeof(wol->sopass));
9452 }
9453
9454 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9455 {
9456         struct tg3 *tp = netdev_priv(dev);
9457         struct device *dp = &tp->pdev->dev;
9458
9459         if (wol->wolopts & ~WAKE_MAGIC)
9460                 return -EINVAL;
9461         if ((wol->wolopts & WAKE_MAGIC) &&
9462             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9463                 return -EINVAL;
9464
9465         spin_lock_bh(&tp->lock);
9466         if (wol->wolopts & WAKE_MAGIC) {
9467                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9468                 device_set_wakeup_enable(dp, true);
9469         } else {
9470                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9471                 device_set_wakeup_enable(dp, false);
9472         }
9473         spin_unlock_bh(&tp->lock);
9474
9475         return 0;
9476 }
9477
9478 static u32 tg3_get_msglevel(struct net_device *dev)
9479 {
9480         struct tg3 *tp = netdev_priv(dev);
9481         return tp->msg_enable;
9482 }
9483
9484 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9485 {
9486         struct tg3 *tp = netdev_priv(dev);
9487         tp->msg_enable = value;
9488 }
9489
9490 static int tg3_set_tso(struct net_device *dev, u32 value)
9491 {
9492         struct tg3 *tp = netdev_priv(dev);
9493
9494         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9495                 if (value)
9496                         return -EINVAL;
9497                 return 0;
9498         }
9499         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9500             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9501                 if (value) {
9502                         dev->features |= NETIF_F_TSO6;
9503                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9504                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9505                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9506                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9507                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9508                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9509                                 dev->features |= NETIF_F_TSO_ECN;
9510                 } else
9511                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9512         }
9513         return ethtool_op_set_tso(dev, value);
9514 }
9515
9516 static int tg3_nway_reset(struct net_device *dev)
9517 {
9518         struct tg3 *tp = netdev_priv(dev);
9519         int r;
9520
9521         if (!netif_running(dev))
9522                 return -EAGAIN;
9523
9524         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9525                 return -EINVAL;
9526
9527         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9528                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9529                         return -EAGAIN;
9530                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9531         } else {
9532                 u32 bmcr;
9533
9534                 spin_lock_bh(&tp->lock);
9535                 r = -EINVAL;
9536                 tg3_readphy(tp, MII_BMCR, &bmcr);
9537                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9538                     ((bmcr & BMCR_ANENABLE) ||
9539                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9540                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9541                                                    BMCR_ANENABLE);
9542                         r = 0;
9543                 }
9544                 spin_unlock_bh(&tp->lock);
9545         }
9546
9547         return r;
9548 }
9549
9550 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9551 {
9552         struct tg3 *tp = netdev_priv(dev);
9553
9554         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9555         ering->rx_mini_max_pending = 0;
9556         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9557                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9558         else
9559                 ering->rx_jumbo_max_pending = 0;
9560
9561         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9562
9563         ering->rx_pending = tp->rx_pending;
9564         ering->rx_mini_pending = 0;
9565         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9566                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9567         else
9568                 ering->rx_jumbo_pending = 0;
9569
9570         ering->tx_pending = tp->napi[0].tx_pending;
9571 }
9572
9573 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9574 {
9575         struct tg3 *tp = netdev_priv(dev);
9576         int i, irq_sync = 0, err = 0;
9577
9578         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9579             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9580             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9581             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9582             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9583              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9584                 return -EINVAL;
9585
9586         if (netif_running(dev)) {
9587                 tg3_phy_stop(tp);
9588                 tg3_netif_stop(tp);
9589                 irq_sync = 1;
9590         }
9591
9592         tg3_full_lock(tp, irq_sync);
9593
9594         tp->rx_pending = ering->rx_pending;
9595
9596         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9597             tp->rx_pending > 63)
9598                 tp->rx_pending = 63;
9599         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9600
9601         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9602                 tp->napi[i].tx_pending = ering->tx_pending;
9603
9604         if (netif_running(dev)) {
9605                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9606                 err = tg3_restart_hw(tp, 1);
9607                 if (!err)
9608                         tg3_netif_start(tp);
9609         }
9610
9611         tg3_full_unlock(tp);
9612
9613         if (irq_sync && !err)
9614                 tg3_phy_start(tp);
9615
9616         return err;
9617 }
9618
9619 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9620 {
9621         struct tg3 *tp = netdev_priv(dev);
9622
9623         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9624
9625         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9626                 epause->rx_pause = 1;
9627         else
9628                 epause->rx_pause = 0;
9629
9630         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9631                 epause->tx_pause = 1;
9632         else
9633                 epause->tx_pause = 0;
9634 }
9635
9636 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9637 {
9638         struct tg3 *tp = netdev_priv(dev);
9639         int err = 0;
9640
9641         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9642                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9643                         return -EAGAIN;
9644
9645                 if (epause->autoneg) {
9646                         u32 newadv;
9647                         struct phy_device *phydev;
9648
9649                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9650
9651                         if (epause->rx_pause) {
9652                                 if (epause->tx_pause)
9653                                         newadv = ADVERTISED_Pause;
9654                                 else
9655                                         newadv = ADVERTISED_Pause |
9656                                                  ADVERTISED_Asym_Pause;
9657                         } else if (epause->tx_pause) {
9658                                 newadv = ADVERTISED_Asym_Pause;
9659                         } else
9660                                 newadv = 0;
9661
9662                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9663                                 u32 oldadv = phydev->advertising &
9664                                              (ADVERTISED_Pause |
9665                                               ADVERTISED_Asym_Pause);
9666                                 if (oldadv != newadv) {
9667                                         phydev->advertising &=
9668                                                 ~(ADVERTISED_Pause |
9669                                                   ADVERTISED_Asym_Pause);
9670                                         phydev->advertising |= newadv;
9671                                         err = phy_start_aneg(phydev);
9672                                 }
9673                         } else {
9674                                 tp->link_config.advertising &=
9675                                                 ~(ADVERTISED_Pause |
9676                                                   ADVERTISED_Asym_Pause);
9677                                 tp->link_config.advertising |= newadv;
9678                         }
9679                 } else {
9680                         if (epause->rx_pause)
9681                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9682                         else
9683                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9684
9685                         if (epause->tx_pause)
9686                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9687                         else
9688                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9689
9690                         if (netif_running(dev))
9691                                 tg3_setup_flow_control(tp, 0, 0);
9692                 }
9693         } else {
9694                 int irq_sync = 0;
9695
9696                 if (netif_running(dev)) {
9697                         tg3_netif_stop(tp);
9698                         irq_sync = 1;
9699                 }
9700
9701                 tg3_full_lock(tp, irq_sync);
9702
9703                 if (epause->autoneg)
9704                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9705                 else
9706                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9707                 if (epause->rx_pause)
9708                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9709                 else
9710                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9711                 if (epause->tx_pause)
9712                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9713                 else
9714                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9715
9716                 if (netif_running(dev)) {
9717                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9718                         err = tg3_restart_hw(tp, 1);
9719                         if (!err)
9720                                 tg3_netif_start(tp);
9721                 }
9722
9723                 tg3_full_unlock(tp);
9724         }
9725
9726         return err;
9727 }
9728
9729 static u32 tg3_get_rx_csum(struct net_device *dev)
9730 {
9731         struct tg3 *tp = netdev_priv(dev);
9732         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9733 }
9734
9735 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9736 {
9737         struct tg3 *tp = netdev_priv(dev);
9738
9739         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9740                 if (data != 0)
9741                         return -EINVAL;
9742                 return 0;
9743         }
9744
9745         spin_lock_bh(&tp->lock);
9746         if (data)
9747                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9748         else
9749                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9750         spin_unlock_bh(&tp->lock);
9751
9752         return 0;
9753 }
9754
9755 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9756 {
9757         struct tg3 *tp = netdev_priv(dev);
9758
9759         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9760                 if (data != 0)
9761                         return -EINVAL;
9762                 return 0;
9763         }
9764
9765         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9766                 ethtool_op_set_tx_ipv6_csum(dev, data);
9767         else
9768                 ethtool_op_set_tx_csum(dev, data);
9769
9770         return 0;
9771 }
9772
9773 static int tg3_get_sset_count (struct net_device *dev, int sset)
9774 {
9775         switch (sset) {
9776         case ETH_SS_TEST:
9777                 return TG3_NUM_TEST;
9778         case ETH_SS_STATS:
9779                 return TG3_NUM_STATS;
9780         default:
9781                 return -EOPNOTSUPP;
9782         }
9783 }
9784
9785 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9786 {
9787         switch (stringset) {
9788         case ETH_SS_STATS:
9789                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9790                 break;
9791         case ETH_SS_TEST:
9792                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9793                 break;
9794         default:
9795                 WARN_ON(1);     /* we need a WARN() */
9796                 break;
9797         }
9798 }
9799
9800 static int tg3_phys_id(struct net_device *dev, u32 data)
9801 {
9802         struct tg3 *tp = netdev_priv(dev);
9803         int i;
9804
9805         if (!netif_running(tp->dev))
9806                 return -EAGAIN;
9807
9808         if (data == 0)
9809                 data = UINT_MAX / 2;
9810
9811         for (i = 0; i < (data * 2); i++) {
9812                 if ((i % 2) == 0)
9813                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9814                                            LED_CTRL_1000MBPS_ON |
9815                                            LED_CTRL_100MBPS_ON |
9816                                            LED_CTRL_10MBPS_ON |
9817                                            LED_CTRL_TRAFFIC_OVERRIDE |
9818                                            LED_CTRL_TRAFFIC_BLINK |
9819                                            LED_CTRL_TRAFFIC_LED);
9820
9821                 else
9822                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9823                                            LED_CTRL_TRAFFIC_OVERRIDE);
9824
9825                 if (msleep_interruptible(500))
9826                         break;
9827         }
9828         tw32(MAC_LED_CTRL, tp->led_ctrl);
9829         return 0;
9830 }
9831
9832 static void tg3_get_ethtool_stats (struct net_device *dev,
9833                                    struct ethtool_stats *estats, u64 *tmp_stats)
9834 {
9835         struct tg3 *tp = netdev_priv(dev);
9836         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9837 }
9838
9839 #define NVRAM_TEST_SIZE 0x100
9840 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9841 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9842 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9843 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9844 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9845
9846 static int tg3_test_nvram(struct tg3 *tp)
9847 {
9848         u32 csum, magic;
9849         __be32 *buf;
9850         int i, j, k, err = 0, size;
9851
9852         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9853                 return 0;
9854
9855         if (tg3_nvram_read(tp, 0, &magic) != 0)
9856                 return -EIO;
9857
9858         if (magic == TG3_EEPROM_MAGIC)
9859                 size = NVRAM_TEST_SIZE;
9860         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9861                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9862                     TG3_EEPROM_SB_FORMAT_1) {
9863                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9864                         case TG3_EEPROM_SB_REVISION_0:
9865                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9866                                 break;
9867                         case TG3_EEPROM_SB_REVISION_2:
9868                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9869                                 break;
9870                         case TG3_EEPROM_SB_REVISION_3:
9871                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9872                                 break;
9873                         default:
9874                                 return 0;
9875                         }
9876                 } else
9877                         return 0;
9878         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9879                 size = NVRAM_SELFBOOT_HW_SIZE;
9880         else
9881                 return -EIO;
9882
9883         buf = kmalloc(size, GFP_KERNEL);
9884         if (buf == NULL)
9885                 return -ENOMEM;
9886
9887         err = -EIO;
9888         for (i = 0, j = 0; i < size; i += 4, j++) {
9889                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9890                 if (err)
9891                         break;
9892         }
9893         if (i < size)
9894                 goto out;
9895
9896         /* Selfboot format */
9897         magic = be32_to_cpu(buf[0]);
9898         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9899             TG3_EEPROM_MAGIC_FW) {
9900                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9901
9902                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9903                     TG3_EEPROM_SB_REVISION_2) {
9904                         /* For rev 2, the csum doesn't include the MBA. */
9905                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9906                                 csum8 += buf8[i];
9907                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9908                                 csum8 += buf8[i];
9909                 } else {
9910                         for (i = 0; i < size; i++)
9911                                 csum8 += buf8[i];
9912                 }
9913
9914                 if (csum8 == 0) {
9915                         err = 0;
9916                         goto out;
9917                 }
9918
9919                 err = -EIO;
9920                 goto out;
9921         }
9922
9923         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9924             TG3_EEPROM_MAGIC_HW) {
9925                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9926                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9927                 u8 *buf8 = (u8 *) buf;
9928
9929                 /* Separate the parity bits and the data bytes.  */
9930                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9931                         if ((i == 0) || (i == 8)) {
9932                                 int l;
9933                                 u8 msk;
9934
9935                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9936                                         parity[k++] = buf8[i] & msk;
9937                                 i++;
9938                         }
9939                         else if (i == 16) {
9940                                 int l;
9941                                 u8 msk;
9942
9943                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9944                                         parity[k++] = buf8[i] & msk;
9945                                 i++;
9946
9947                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9948                                         parity[k++] = buf8[i] & msk;
9949                                 i++;
9950                         }
9951                         data[j++] = buf8[i];
9952                 }
9953
9954                 err = -EIO;
9955                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9956                         u8 hw8 = hweight8(data[i]);
9957
9958                         if ((hw8 & 0x1) && parity[i])
9959                                 goto out;
9960                         else if (!(hw8 & 0x1) && !parity[i])
9961                                 goto out;
9962                 }
9963                 err = 0;
9964                 goto out;
9965         }
9966
9967         /* Bootstrap checksum at offset 0x10 */
9968         csum = calc_crc((unsigned char *) buf, 0x10);
9969         if (csum != be32_to_cpu(buf[0x10/4]))
9970                 goto out;
9971
9972         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9973         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9974         if (csum != be32_to_cpu(buf[0xfc/4]))
9975                 goto out;
9976
9977         err = 0;
9978
9979 out:
9980         kfree(buf);
9981         return err;
9982 }
9983
9984 #define TG3_SERDES_TIMEOUT_SEC  2
9985 #define TG3_COPPER_TIMEOUT_SEC  6
9986
9987 static int tg3_test_link(struct tg3 *tp)
9988 {
9989         int i, max;
9990
9991         if (!netif_running(tp->dev))
9992                 return -ENODEV;
9993
9994         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9995                 max = TG3_SERDES_TIMEOUT_SEC;
9996         else
9997                 max = TG3_COPPER_TIMEOUT_SEC;
9998
9999         for (i = 0; i < max; i++) {
10000                 if (netif_carrier_ok(tp->dev))
10001                         return 0;
10002
10003                 if (msleep_interruptible(1000))
10004                         break;
10005         }
10006
10007         return -EIO;
10008 }
10009
10010 /* Only test the commonly used registers */
10011 static int tg3_test_registers(struct tg3 *tp)
10012 {
10013         int i, is_5705, is_5750;
10014         u32 offset, read_mask, write_mask, val, save_val, read_val;
10015         static struct {
10016                 u16 offset;
10017                 u16 flags;
10018 #define TG3_FL_5705     0x1
10019 #define TG3_FL_NOT_5705 0x2
10020 #define TG3_FL_NOT_5788 0x4
10021 #define TG3_FL_NOT_5750 0x8
10022                 u32 read_mask;
10023                 u32 write_mask;
10024         } reg_tbl[] = {
10025                 /* MAC Control Registers */
10026                 { MAC_MODE, TG3_FL_NOT_5705,
10027                         0x00000000, 0x00ef6f8c },
10028                 { MAC_MODE, TG3_FL_5705,
10029                         0x00000000, 0x01ef6b8c },
10030                 { MAC_STATUS, TG3_FL_NOT_5705,
10031                         0x03800107, 0x00000000 },
10032                 { MAC_STATUS, TG3_FL_5705,
10033                         0x03800100, 0x00000000 },
10034                 { MAC_ADDR_0_HIGH, 0x0000,
10035                         0x00000000, 0x0000ffff },
10036                 { MAC_ADDR_0_LOW, 0x0000,
10037                         0x00000000, 0xffffffff },
10038                 { MAC_RX_MTU_SIZE, 0x0000,
10039                         0x00000000, 0x0000ffff },
10040                 { MAC_TX_MODE, 0x0000,
10041                         0x00000000, 0x00000070 },
10042                 { MAC_TX_LENGTHS, 0x0000,
10043                         0x00000000, 0x00003fff },
10044                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10045                         0x00000000, 0x000007fc },
10046                 { MAC_RX_MODE, TG3_FL_5705,
10047                         0x00000000, 0x000007dc },
10048                 { MAC_HASH_REG_0, 0x0000,
10049                         0x00000000, 0xffffffff },
10050                 { MAC_HASH_REG_1, 0x0000,
10051                         0x00000000, 0xffffffff },
10052                 { MAC_HASH_REG_2, 0x0000,
10053                         0x00000000, 0xffffffff },
10054                 { MAC_HASH_REG_3, 0x0000,
10055                         0x00000000, 0xffffffff },
10056
10057                 /* Receive Data and Receive BD Initiator Control Registers. */
10058                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10059                         0x00000000, 0xffffffff },
10060                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10061                         0x00000000, 0xffffffff },
10062                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10063                         0x00000000, 0x00000003 },
10064                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10065                         0x00000000, 0xffffffff },
10066                 { RCVDBDI_STD_BD+0, 0x0000,
10067                         0x00000000, 0xffffffff },
10068                 { RCVDBDI_STD_BD+4, 0x0000,
10069                         0x00000000, 0xffffffff },
10070                 { RCVDBDI_STD_BD+8, 0x0000,
10071                         0x00000000, 0xffff0002 },
10072                 { RCVDBDI_STD_BD+0xc, 0x0000,
10073                         0x00000000, 0xffffffff },
10074
10075                 /* Receive BD Initiator Control Registers. */
10076                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10077                         0x00000000, 0xffffffff },
10078                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10079                         0x00000000, 0x000003ff },
10080                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10081                         0x00000000, 0xffffffff },
10082
10083                 /* Host Coalescing Control Registers. */
10084                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10085                         0x00000000, 0x00000004 },
10086                 { HOSTCC_MODE, TG3_FL_5705,
10087                         0x00000000, 0x000000f6 },
10088                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10089                         0x00000000, 0xffffffff },
10090                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10091                         0x00000000, 0x000003ff },
10092                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10093                         0x00000000, 0xffffffff },
10094                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10095                         0x00000000, 0x000003ff },
10096                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10097                         0x00000000, 0xffffffff },
10098                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10099                         0x00000000, 0x000000ff },
10100                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10101                         0x00000000, 0xffffffff },
10102                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10103                         0x00000000, 0x000000ff },
10104                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10105                         0x00000000, 0xffffffff },
10106                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10107                         0x00000000, 0xffffffff },
10108                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10109                         0x00000000, 0xffffffff },
10110                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10111                         0x00000000, 0x000000ff },
10112                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10113                         0x00000000, 0xffffffff },
10114                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10115                         0x00000000, 0x000000ff },
10116                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10117                         0x00000000, 0xffffffff },
10118                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10119                         0x00000000, 0xffffffff },
10120                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10121                         0x00000000, 0xffffffff },
10122                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10123                         0x00000000, 0xffffffff },
10124                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10125                         0x00000000, 0xffffffff },
10126                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10127                         0xffffffff, 0x00000000 },
10128                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10129                         0xffffffff, 0x00000000 },
10130
10131                 /* Buffer Manager Control Registers. */
10132                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10133                         0x00000000, 0x007fff80 },
10134                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10135                         0x00000000, 0x007fffff },
10136                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10137                         0x00000000, 0x0000003f },
10138                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10139                         0x00000000, 0x000001ff },
10140                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10141                         0x00000000, 0x000001ff },
10142                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10143                         0xffffffff, 0x00000000 },
10144                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10145                         0xffffffff, 0x00000000 },
10146
10147                 /* Mailbox Registers */
10148                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10149                         0x00000000, 0x000001ff },
10150                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10151                         0x00000000, 0x000001ff },
10152                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10153                         0x00000000, 0x000007ff },
10154                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10155                         0x00000000, 0x000001ff },
10156
10157                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10158         };
10159
10160         is_5705 = is_5750 = 0;
10161         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10162                 is_5705 = 1;
10163                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10164                         is_5750 = 1;
10165         }
10166
10167         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10168                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10169                         continue;
10170
10171                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10172                         continue;
10173
10174                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10175                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10176                         continue;
10177
10178                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10179                         continue;
10180
10181                 offset = (u32) reg_tbl[i].offset;
10182                 read_mask = reg_tbl[i].read_mask;
10183                 write_mask = reg_tbl[i].write_mask;
10184
10185                 /* Save the original register content */
10186                 save_val = tr32(offset);
10187
10188                 /* Determine the read-only value. */
10189                 read_val = save_val & read_mask;
10190
10191                 /* Write zero to the register, then make sure the read-only bits
10192                  * are not changed and the read/write bits are all zeros.
10193                  */
10194                 tw32(offset, 0);
10195
10196                 val = tr32(offset);
10197
10198                 /* Test the read-only and read/write bits. */
10199                 if (((val & read_mask) != read_val) || (val & write_mask))
10200                         goto out;
10201
10202                 /* Write ones to all the bits defined by RdMask and WrMask, then
10203                  * make sure the read-only bits are not changed and the
10204                  * read/write bits are all ones.
10205                  */
10206                 tw32(offset, read_mask | write_mask);
10207
10208                 val = tr32(offset);
10209
10210                 /* Test the read-only bits. */
10211                 if ((val & read_mask) != read_val)
10212                         goto out;
10213
10214                 /* Test the read/write bits. */
10215                 if ((val & write_mask) != write_mask)
10216                         goto out;
10217
10218                 tw32(offset, save_val);
10219         }
10220
10221         return 0;
10222
10223 out:
10224         if (netif_msg_hw(tp))
10225                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10226                        offset);
10227         tw32(offset, save_val);
10228         return -EIO;
10229 }
10230
10231 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10232 {
10233         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10234         int i;
10235         u32 j;
10236
10237         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10238                 for (j = 0; j < len; j += 4) {
10239                         u32 val;
10240
10241                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10242                         tg3_read_mem(tp, offset + j, &val);
10243                         if (val != test_pattern[i])
10244                                 return -EIO;
10245                 }
10246         }
10247         return 0;
10248 }
10249
10250 static int tg3_test_memory(struct tg3 *tp)
10251 {
10252         static struct mem_entry {
10253                 u32 offset;
10254                 u32 len;
10255         } mem_tbl_570x[] = {
10256                 { 0x00000000, 0x00b50},
10257                 { 0x00002000, 0x1c000},
10258                 { 0xffffffff, 0x00000}
10259         }, mem_tbl_5705[] = {
10260                 { 0x00000100, 0x0000c},
10261                 { 0x00000200, 0x00008},
10262                 { 0x00004000, 0x00800},
10263                 { 0x00006000, 0x01000},
10264                 { 0x00008000, 0x02000},
10265                 { 0x00010000, 0x0e000},
10266                 { 0xffffffff, 0x00000}
10267         }, mem_tbl_5755[] = {
10268                 { 0x00000200, 0x00008},
10269                 { 0x00004000, 0x00800},
10270                 { 0x00006000, 0x00800},
10271                 { 0x00008000, 0x02000},
10272                 { 0x00010000, 0x0c000},
10273                 { 0xffffffff, 0x00000}
10274         }, mem_tbl_5906[] = {
10275                 { 0x00000200, 0x00008},
10276                 { 0x00004000, 0x00400},
10277                 { 0x00006000, 0x00400},
10278                 { 0x00008000, 0x01000},
10279                 { 0x00010000, 0x01000},
10280                 { 0xffffffff, 0x00000}
10281         };
10282         struct mem_entry *mem_tbl;
10283         int err = 0;
10284         int i;
10285
10286         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10287                 mem_tbl = mem_tbl_5755;
10288         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10289                 mem_tbl = mem_tbl_5906;
10290         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10291                 mem_tbl = mem_tbl_5705;
10292         else
10293                 mem_tbl = mem_tbl_570x;
10294
10295         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10296                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10297                     mem_tbl[i].len)) != 0)
10298                         break;
10299         }
10300
10301         return err;
10302 }
10303
10304 #define TG3_MAC_LOOPBACK        0
10305 #define TG3_PHY_LOOPBACK        1
10306
10307 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10308 {
10309         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10310         u32 desc_idx, coal_now;
10311         struct sk_buff *skb, *rx_skb;
10312         u8 *tx_data;
10313         dma_addr_t map;
10314         int num_pkts, tx_len, rx_len, i, err;
10315         struct tg3_rx_buffer_desc *desc;
10316         struct tg3_napi *tnapi, *rnapi;
10317         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10318
10319         if (tp->irq_cnt > 1) {
10320                 tnapi = &tp->napi[1];
10321                 rnapi = &tp->napi[1];
10322         } else {
10323                 tnapi = &tp->napi[0];
10324                 rnapi = &tp->napi[0];
10325         }
10326         coal_now = tnapi->coal_now | rnapi->coal_now;
10327
10328         if (loopback_mode == TG3_MAC_LOOPBACK) {
10329                 /* HW errata - mac loopback fails in some cases on 5780.
10330                  * Normal traffic and PHY loopback are not affected by
10331                  * errata.
10332                  */
10333                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10334                         return 0;
10335
10336                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10337                            MAC_MODE_PORT_INT_LPBACK;
10338                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10339                         mac_mode |= MAC_MODE_LINK_POLARITY;
10340                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10341                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10342                 else
10343                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10344                 tw32(MAC_MODE, mac_mode);
10345         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10346                 u32 val;
10347
10348                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10349                         tg3_phy_fet_toggle_apd(tp, false);
10350                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10351                 } else
10352                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10353
10354                 tg3_phy_toggle_automdix(tp, 0);
10355
10356                 tg3_writephy(tp, MII_BMCR, val);
10357                 udelay(40);
10358
10359                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10360                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10361                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10362                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10363                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10364                 } else
10365                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10366
10367                 /* reset to prevent losing 1st rx packet intermittently */
10368                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10369                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10370                         udelay(10);
10371                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10372                 }
10373                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10374                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10375                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10376                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10377                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10378                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10379                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10380                 }
10381                 tw32(MAC_MODE, mac_mode);
10382         }
10383         else
10384                 return -EINVAL;
10385
10386         err = -EIO;
10387
10388         tx_len = 1514;
10389         skb = netdev_alloc_skb(tp->dev, tx_len);
10390         if (!skb)
10391                 return -ENOMEM;
10392
10393         tx_data = skb_put(skb, tx_len);
10394         memcpy(tx_data, tp->dev->dev_addr, 6);
10395         memset(tx_data + 6, 0x0, 8);
10396
10397         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10398
10399         for (i = 14; i < tx_len; i++)
10400                 tx_data[i] = (u8) (i & 0xff);
10401
10402         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10403                 dev_kfree_skb(skb);
10404                 return -EIO;
10405         }
10406
10407         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10408                rnapi->coal_now);
10409
10410         udelay(10);
10411
10412         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10413
10414         num_pkts = 0;
10415
10416         tg3_set_txd(tnapi, tnapi->tx_prod,
10417                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10418
10419         tnapi->tx_prod++;
10420         num_pkts++;
10421
10422         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10423         tr32_mailbox(tnapi->prodmbox);
10424
10425         udelay(10);
10426
10427         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10428         for (i = 0; i < 25; i++) {
10429                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10430                        coal_now);
10431
10432                 udelay(10);
10433
10434                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10435                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10436                 if ((tx_idx == tnapi->tx_prod) &&
10437                     (rx_idx == (rx_start_idx + num_pkts)))
10438                         break;
10439         }
10440
10441         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10442         dev_kfree_skb(skb);
10443
10444         if (tx_idx != tnapi->tx_prod)
10445                 goto out;
10446
10447         if (rx_idx != rx_start_idx + num_pkts)
10448                 goto out;
10449
10450         desc = &rnapi->rx_rcb[rx_start_idx];
10451         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10452         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10453         if (opaque_key != RXD_OPAQUE_RING_STD)
10454                 goto out;
10455
10456         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10457             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10458                 goto out;
10459
10460         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10461         if (rx_len != tx_len)
10462                 goto out;
10463
10464         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10465
10466         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10467         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10468
10469         for (i = 14; i < tx_len; i++) {
10470                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10471                         goto out;
10472         }
10473         err = 0;
10474
10475         /* tg3_free_rings will unmap and free the rx_skb */
10476 out:
10477         return err;
10478 }
10479
10480 #define TG3_MAC_LOOPBACK_FAILED         1
10481 #define TG3_PHY_LOOPBACK_FAILED         2
10482 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10483                                          TG3_PHY_LOOPBACK_FAILED)
10484
10485 static int tg3_test_loopback(struct tg3 *tp)
10486 {
10487         int err = 0;
10488         u32 cpmuctrl = 0;
10489
10490         if (!netif_running(tp->dev))
10491                 return TG3_LOOPBACK_FAILED;
10492
10493         err = tg3_reset_hw(tp, 1);
10494         if (err)
10495                 return TG3_LOOPBACK_FAILED;
10496
10497         /* Turn off gphy autopowerdown. */
10498         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10499                 tg3_phy_toggle_apd(tp, false);
10500
10501         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10502                 int i;
10503                 u32 status;
10504
10505                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10506
10507                 /* Wait for up to 40 microseconds to acquire lock. */
10508                 for (i = 0; i < 4; i++) {
10509                         status = tr32(TG3_CPMU_MUTEX_GNT);
10510                         if (status == CPMU_MUTEX_GNT_DRIVER)
10511                                 break;
10512                         udelay(10);
10513                 }
10514
10515                 if (status != CPMU_MUTEX_GNT_DRIVER)
10516                         return TG3_LOOPBACK_FAILED;
10517
10518                 /* Turn off link-based power management. */
10519                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10520                 tw32(TG3_CPMU_CTRL,
10521                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10522                                   CPMU_CTRL_LINK_AWARE_MODE));
10523         }
10524
10525         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10526                 err |= TG3_MAC_LOOPBACK_FAILED;
10527
10528         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10529                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10530
10531                 /* Release the mutex */
10532                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10533         }
10534
10535         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10536             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10537                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10538                         err |= TG3_PHY_LOOPBACK_FAILED;
10539         }
10540
10541         /* Re-enable gphy autopowerdown. */
10542         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10543                 tg3_phy_toggle_apd(tp, true);
10544
10545         return err;
10546 }
10547
10548 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10549                           u64 *data)
10550 {
10551         struct tg3 *tp = netdev_priv(dev);
10552
10553         if (tp->link_config.phy_is_low_power)
10554                 tg3_set_power_state(tp, PCI_D0);
10555
10556         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10557
10558         if (tg3_test_nvram(tp) != 0) {
10559                 etest->flags |= ETH_TEST_FL_FAILED;
10560                 data[0] = 1;
10561         }
10562         if (tg3_test_link(tp) != 0) {
10563                 etest->flags |= ETH_TEST_FL_FAILED;
10564                 data[1] = 1;
10565         }
10566         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10567                 int err, err2 = 0, irq_sync = 0;
10568
10569                 if (netif_running(dev)) {
10570                         tg3_phy_stop(tp);
10571                         tg3_netif_stop(tp);
10572                         irq_sync = 1;
10573                 }
10574
10575                 tg3_full_lock(tp, irq_sync);
10576
10577                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10578                 err = tg3_nvram_lock(tp);
10579                 tg3_halt_cpu(tp, RX_CPU_BASE);
10580                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10581                         tg3_halt_cpu(tp, TX_CPU_BASE);
10582                 if (!err)
10583                         tg3_nvram_unlock(tp);
10584
10585                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10586                         tg3_phy_reset(tp);
10587
10588                 if (tg3_test_registers(tp) != 0) {
10589                         etest->flags |= ETH_TEST_FL_FAILED;
10590                         data[2] = 1;
10591                 }
10592                 if (tg3_test_memory(tp) != 0) {
10593                         etest->flags |= ETH_TEST_FL_FAILED;
10594                         data[3] = 1;
10595                 }
10596                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10597                         etest->flags |= ETH_TEST_FL_FAILED;
10598
10599                 tg3_full_unlock(tp);
10600
10601                 if (tg3_test_interrupt(tp) != 0) {
10602                         etest->flags |= ETH_TEST_FL_FAILED;
10603                         data[5] = 1;
10604                 }
10605
10606                 tg3_full_lock(tp, 0);
10607
10608                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10609                 if (netif_running(dev)) {
10610                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10611                         err2 = tg3_restart_hw(tp, 1);
10612                         if (!err2)
10613                                 tg3_netif_start(tp);
10614                 }
10615
10616                 tg3_full_unlock(tp);
10617
10618                 if (irq_sync && !err2)
10619                         tg3_phy_start(tp);
10620         }
10621         if (tp->link_config.phy_is_low_power)
10622                 tg3_set_power_state(tp, PCI_D3hot);
10623
10624 }
10625
10626 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10627 {
10628         struct mii_ioctl_data *data = if_mii(ifr);
10629         struct tg3 *tp = netdev_priv(dev);
10630         int err;
10631
10632         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10633                 struct phy_device *phydev;
10634                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10635                         return -EAGAIN;
10636                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10637                 return phy_mii_ioctl(phydev, data, cmd);
10638         }
10639
10640         switch(cmd) {
10641         case SIOCGMIIPHY:
10642                 data->phy_id = tp->phy_addr;
10643
10644                 /* fallthru */
10645         case SIOCGMIIREG: {
10646                 u32 mii_regval;
10647
10648                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10649                         break;                  /* We have no PHY */
10650
10651                 if (tp->link_config.phy_is_low_power)
10652                         return -EAGAIN;
10653
10654                 spin_lock_bh(&tp->lock);
10655                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10656                 spin_unlock_bh(&tp->lock);
10657
10658                 data->val_out = mii_regval;
10659
10660                 return err;
10661         }
10662
10663         case SIOCSMIIREG:
10664                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10665                         break;                  /* We have no PHY */
10666
10667                 if (tp->link_config.phy_is_low_power)
10668                         return -EAGAIN;
10669
10670                 spin_lock_bh(&tp->lock);
10671                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10672                 spin_unlock_bh(&tp->lock);
10673
10674                 return err;
10675
10676         default:
10677                 /* do nothing */
10678                 break;
10679         }
10680         return -EOPNOTSUPP;
10681 }
10682
10683 #if TG3_VLAN_TAG_USED
10684 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10685 {
10686         struct tg3 *tp = netdev_priv(dev);
10687
10688         if (!netif_running(dev)) {
10689                 tp->vlgrp = grp;
10690                 return;
10691         }
10692
10693         tg3_netif_stop(tp);
10694
10695         tg3_full_lock(tp, 0);
10696
10697         tp->vlgrp = grp;
10698
10699         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10700         __tg3_set_rx_mode(dev);
10701
10702         tg3_netif_start(tp);
10703
10704         tg3_full_unlock(tp);
10705 }
10706 #endif
10707
10708 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10709 {
10710         struct tg3 *tp = netdev_priv(dev);
10711
10712         memcpy(ec, &tp->coal, sizeof(*ec));
10713         return 0;
10714 }
10715
10716 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10717 {
10718         struct tg3 *tp = netdev_priv(dev);
10719         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10720         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10721
10722         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10723                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10724                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10725                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10726                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10727         }
10728
10729         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10730             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10731             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10732             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10733             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10734             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10735             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10736             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10737             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10738             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10739                 return -EINVAL;
10740
10741         /* No rx interrupts will be generated if both are zero */
10742         if ((ec->rx_coalesce_usecs == 0) &&
10743             (ec->rx_max_coalesced_frames == 0))
10744                 return -EINVAL;
10745
10746         /* No tx interrupts will be generated if both are zero */
10747         if ((ec->tx_coalesce_usecs == 0) &&
10748             (ec->tx_max_coalesced_frames == 0))
10749                 return -EINVAL;
10750
10751         /* Only copy relevant parameters, ignore all others. */
10752         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10753         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10754         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10755         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10756         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10757         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10758         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10759         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10760         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10761
10762         if (netif_running(dev)) {
10763                 tg3_full_lock(tp, 0);
10764                 __tg3_set_coalesce(tp, &tp->coal);
10765                 tg3_full_unlock(tp);
10766         }
10767         return 0;
10768 }
10769
10770 static const struct ethtool_ops tg3_ethtool_ops = {
10771         .get_settings           = tg3_get_settings,
10772         .set_settings           = tg3_set_settings,
10773         .get_drvinfo            = tg3_get_drvinfo,
10774         .get_regs_len           = tg3_get_regs_len,
10775         .get_regs               = tg3_get_regs,
10776         .get_wol                = tg3_get_wol,
10777         .set_wol                = tg3_set_wol,
10778         .get_msglevel           = tg3_get_msglevel,
10779         .set_msglevel           = tg3_set_msglevel,
10780         .nway_reset             = tg3_nway_reset,
10781         .get_link               = ethtool_op_get_link,
10782         .get_eeprom_len         = tg3_get_eeprom_len,
10783         .get_eeprom             = tg3_get_eeprom,
10784         .set_eeprom             = tg3_set_eeprom,
10785         .get_ringparam          = tg3_get_ringparam,
10786         .set_ringparam          = tg3_set_ringparam,
10787         .get_pauseparam         = tg3_get_pauseparam,
10788         .set_pauseparam         = tg3_set_pauseparam,
10789         .get_rx_csum            = tg3_get_rx_csum,
10790         .set_rx_csum            = tg3_set_rx_csum,
10791         .set_tx_csum            = tg3_set_tx_csum,
10792         .set_sg                 = ethtool_op_set_sg,
10793         .set_tso                = tg3_set_tso,
10794         .self_test              = tg3_self_test,
10795         .get_strings            = tg3_get_strings,
10796         .phys_id                = tg3_phys_id,
10797         .get_ethtool_stats      = tg3_get_ethtool_stats,
10798         .get_coalesce           = tg3_get_coalesce,
10799         .set_coalesce           = tg3_set_coalesce,
10800         .get_sset_count         = tg3_get_sset_count,
10801 };
10802
10803 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10804 {
10805         u32 cursize, val, magic;
10806
10807         tp->nvram_size = EEPROM_CHIP_SIZE;
10808
10809         if (tg3_nvram_read(tp, 0, &magic) != 0)
10810                 return;
10811
10812         if ((magic != TG3_EEPROM_MAGIC) &&
10813             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10814             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10815                 return;
10816
10817         /*
10818          * Size the chip by reading offsets at increasing powers of two.
10819          * When we encounter our validation signature, we know the addressing
10820          * has wrapped around, and thus have our chip size.
10821          */
10822         cursize = 0x10;
10823
10824         while (cursize < tp->nvram_size) {
10825                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10826                         return;
10827
10828                 if (val == magic)
10829                         break;
10830
10831                 cursize <<= 1;
10832         }
10833
10834         tp->nvram_size = cursize;
10835 }
10836
10837 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10838 {
10839         u32 val;
10840
10841         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10842             tg3_nvram_read(tp, 0, &val) != 0)
10843                 return;
10844
10845         /* Selfboot format */
10846         if (val != TG3_EEPROM_MAGIC) {
10847                 tg3_get_eeprom_size(tp);
10848                 return;
10849         }
10850
10851         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10852                 if (val != 0) {
10853                         /* This is confusing.  We want to operate on the
10854                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10855                          * call will read from NVRAM and byteswap the data
10856                          * according to the byteswapping settings for all
10857                          * other register accesses.  This ensures the data we
10858                          * want will always reside in the lower 16-bits.
10859                          * However, the data in NVRAM is in LE format, which
10860                          * means the data from the NVRAM read will always be
10861                          * opposite the endianness of the CPU.  The 16-bit
10862                          * byteswap then brings the data to CPU endianness.
10863                          */
10864                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10865                         return;
10866                 }
10867         }
10868         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10869 }
10870
10871 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10872 {
10873         u32 nvcfg1;
10874
10875         nvcfg1 = tr32(NVRAM_CFG1);
10876         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10877                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10878         } else {
10879                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10880                 tw32(NVRAM_CFG1, nvcfg1);
10881         }
10882
10883         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10884             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10885                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10886                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10887                         tp->nvram_jedecnum = JEDEC_ATMEL;
10888                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10889                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10890                         break;
10891                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10892                         tp->nvram_jedecnum = JEDEC_ATMEL;
10893                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10894                         break;
10895                 case FLASH_VENDOR_ATMEL_EEPROM:
10896                         tp->nvram_jedecnum = JEDEC_ATMEL;
10897                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10898                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10899                         break;
10900                 case FLASH_VENDOR_ST:
10901                         tp->nvram_jedecnum = JEDEC_ST;
10902                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10903                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10904                         break;
10905                 case FLASH_VENDOR_SAIFUN:
10906                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10907                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10908                         break;
10909                 case FLASH_VENDOR_SST_SMALL:
10910                 case FLASH_VENDOR_SST_LARGE:
10911                         tp->nvram_jedecnum = JEDEC_SST;
10912                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10913                         break;
10914                 }
10915         } else {
10916                 tp->nvram_jedecnum = JEDEC_ATMEL;
10917                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10918                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10919         }
10920 }
10921
10922 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10923 {
10924         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10925         case FLASH_5752PAGE_SIZE_256:
10926                 tp->nvram_pagesize = 256;
10927                 break;
10928         case FLASH_5752PAGE_SIZE_512:
10929                 tp->nvram_pagesize = 512;
10930                 break;
10931         case FLASH_5752PAGE_SIZE_1K:
10932                 tp->nvram_pagesize = 1024;
10933                 break;
10934         case FLASH_5752PAGE_SIZE_2K:
10935                 tp->nvram_pagesize = 2048;
10936                 break;
10937         case FLASH_5752PAGE_SIZE_4K:
10938                 tp->nvram_pagesize = 4096;
10939                 break;
10940         case FLASH_5752PAGE_SIZE_264:
10941                 tp->nvram_pagesize = 264;
10942                 break;
10943         case FLASH_5752PAGE_SIZE_528:
10944                 tp->nvram_pagesize = 528;
10945                 break;
10946         }
10947 }
10948
10949 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10950 {
10951         u32 nvcfg1;
10952
10953         nvcfg1 = tr32(NVRAM_CFG1);
10954
10955         /* NVRAM protection for TPM */
10956         if (nvcfg1 & (1 << 27))
10957                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10958
10959         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10960         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10961         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10962                 tp->nvram_jedecnum = JEDEC_ATMEL;
10963                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10964                 break;
10965         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10966                 tp->nvram_jedecnum = JEDEC_ATMEL;
10967                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10968                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10969                 break;
10970         case FLASH_5752VENDOR_ST_M45PE10:
10971         case FLASH_5752VENDOR_ST_M45PE20:
10972         case FLASH_5752VENDOR_ST_M45PE40:
10973                 tp->nvram_jedecnum = JEDEC_ST;
10974                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10975                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10976                 break;
10977         }
10978
10979         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10980                 tg3_nvram_get_pagesize(tp, nvcfg1);
10981         } else {
10982                 /* For eeprom, set pagesize to maximum eeprom size */
10983                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10984
10985                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10986                 tw32(NVRAM_CFG1, nvcfg1);
10987         }
10988 }
10989
10990 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10991 {
10992         u32 nvcfg1, protect = 0;
10993
10994         nvcfg1 = tr32(NVRAM_CFG1);
10995
10996         /* NVRAM protection for TPM */
10997         if (nvcfg1 & (1 << 27)) {
10998                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10999                 protect = 1;
11000         }
11001
11002         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11003         switch (nvcfg1) {
11004         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11005         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11006         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11007         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11008                 tp->nvram_jedecnum = JEDEC_ATMEL;
11009                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11010                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11011                 tp->nvram_pagesize = 264;
11012                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11013                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11014                         tp->nvram_size = (protect ? 0x3e200 :
11015                                           TG3_NVRAM_SIZE_512KB);
11016                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11017                         tp->nvram_size = (protect ? 0x1f200 :
11018                                           TG3_NVRAM_SIZE_256KB);
11019                 else
11020                         tp->nvram_size = (protect ? 0x1f200 :
11021                                           TG3_NVRAM_SIZE_128KB);
11022                 break;
11023         case FLASH_5752VENDOR_ST_M45PE10:
11024         case FLASH_5752VENDOR_ST_M45PE20:
11025         case FLASH_5752VENDOR_ST_M45PE40:
11026                 tp->nvram_jedecnum = JEDEC_ST;
11027                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11028                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11029                 tp->nvram_pagesize = 256;
11030                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11031                         tp->nvram_size = (protect ?
11032                                           TG3_NVRAM_SIZE_64KB :
11033                                           TG3_NVRAM_SIZE_128KB);
11034                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11035                         tp->nvram_size = (protect ?
11036                                           TG3_NVRAM_SIZE_64KB :
11037                                           TG3_NVRAM_SIZE_256KB);
11038                 else
11039                         tp->nvram_size = (protect ?
11040                                           TG3_NVRAM_SIZE_128KB :
11041                                           TG3_NVRAM_SIZE_512KB);
11042                 break;
11043         }
11044 }
11045
11046 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11047 {
11048         u32 nvcfg1;
11049
11050         nvcfg1 = tr32(NVRAM_CFG1);
11051
11052         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11053         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11054         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11055         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11056         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11057                 tp->nvram_jedecnum = JEDEC_ATMEL;
11058                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11059                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11060
11061                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11062                 tw32(NVRAM_CFG1, nvcfg1);
11063                 break;
11064         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11065         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11066         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11067         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11068                 tp->nvram_jedecnum = JEDEC_ATMEL;
11069                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11070                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11071                 tp->nvram_pagesize = 264;
11072                 break;
11073         case FLASH_5752VENDOR_ST_M45PE10:
11074         case FLASH_5752VENDOR_ST_M45PE20:
11075         case FLASH_5752VENDOR_ST_M45PE40:
11076                 tp->nvram_jedecnum = JEDEC_ST;
11077                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11078                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11079                 tp->nvram_pagesize = 256;
11080                 break;
11081         }
11082 }
11083
11084 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11085 {
11086         u32 nvcfg1, protect = 0;
11087
11088         nvcfg1 = tr32(NVRAM_CFG1);
11089
11090         /* NVRAM protection for TPM */
11091         if (nvcfg1 & (1 << 27)) {
11092                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11093                 protect = 1;
11094         }
11095
11096         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11097         switch (nvcfg1) {
11098         case FLASH_5761VENDOR_ATMEL_ADB021D:
11099         case FLASH_5761VENDOR_ATMEL_ADB041D:
11100         case FLASH_5761VENDOR_ATMEL_ADB081D:
11101         case FLASH_5761VENDOR_ATMEL_ADB161D:
11102         case FLASH_5761VENDOR_ATMEL_MDB021D:
11103         case FLASH_5761VENDOR_ATMEL_MDB041D:
11104         case FLASH_5761VENDOR_ATMEL_MDB081D:
11105         case FLASH_5761VENDOR_ATMEL_MDB161D:
11106                 tp->nvram_jedecnum = JEDEC_ATMEL;
11107                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11108                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11109                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11110                 tp->nvram_pagesize = 256;
11111                 break;
11112         case FLASH_5761VENDOR_ST_A_M45PE20:
11113         case FLASH_5761VENDOR_ST_A_M45PE40:
11114         case FLASH_5761VENDOR_ST_A_M45PE80:
11115         case FLASH_5761VENDOR_ST_A_M45PE16:
11116         case FLASH_5761VENDOR_ST_M_M45PE20:
11117         case FLASH_5761VENDOR_ST_M_M45PE40:
11118         case FLASH_5761VENDOR_ST_M_M45PE80:
11119         case FLASH_5761VENDOR_ST_M_M45PE16:
11120                 tp->nvram_jedecnum = JEDEC_ST;
11121                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11122                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11123                 tp->nvram_pagesize = 256;
11124                 break;
11125         }
11126
11127         if (protect) {
11128                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11129         } else {
11130                 switch (nvcfg1) {
11131                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11132                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11133                 case FLASH_5761VENDOR_ST_A_M45PE16:
11134                 case FLASH_5761VENDOR_ST_M_M45PE16:
11135                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11136                         break;
11137                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11138                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11139                 case FLASH_5761VENDOR_ST_A_M45PE80:
11140                 case FLASH_5761VENDOR_ST_M_M45PE80:
11141                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11142                         break;
11143                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11144                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11145                 case FLASH_5761VENDOR_ST_A_M45PE40:
11146                 case FLASH_5761VENDOR_ST_M_M45PE40:
11147                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11148                         break;
11149                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11150                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11151                 case FLASH_5761VENDOR_ST_A_M45PE20:
11152                 case FLASH_5761VENDOR_ST_M_M45PE20:
11153                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11154                         break;
11155                 }
11156         }
11157 }
11158
11159 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11160 {
11161         tp->nvram_jedecnum = JEDEC_ATMEL;
11162         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11163         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11164 }
11165
11166 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11167 {
11168         u32 nvcfg1;
11169
11170         nvcfg1 = tr32(NVRAM_CFG1);
11171
11172         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11173         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11174         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11175                 tp->nvram_jedecnum = JEDEC_ATMEL;
11176                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11177                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11178
11179                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11180                 tw32(NVRAM_CFG1, nvcfg1);
11181                 return;
11182         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11183         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11184         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11185         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11186         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11187         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11188         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11189                 tp->nvram_jedecnum = JEDEC_ATMEL;
11190                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11191                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11192
11193                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11194                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11195                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11196                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11197                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11198                         break;
11199                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11200                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11201                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11202                         break;
11203                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11204                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11205                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11206                         break;
11207                 }
11208                 break;
11209         case FLASH_5752VENDOR_ST_M45PE10:
11210         case FLASH_5752VENDOR_ST_M45PE20:
11211         case FLASH_5752VENDOR_ST_M45PE40:
11212                 tp->nvram_jedecnum = JEDEC_ST;
11213                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11214                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11215
11216                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11217                 case FLASH_5752VENDOR_ST_M45PE10:
11218                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11219                         break;
11220                 case FLASH_5752VENDOR_ST_M45PE20:
11221                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11222                         break;
11223                 case FLASH_5752VENDOR_ST_M45PE40:
11224                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11225                         break;
11226                 }
11227                 break;
11228         default:
11229                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11230                 return;
11231         }
11232
11233         tg3_nvram_get_pagesize(tp, nvcfg1);
11234         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11235                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11236 }
11237
11238
11239 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11240 {
11241         u32 nvcfg1;
11242
11243         nvcfg1 = tr32(NVRAM_CFG1);
11244
11245         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11246         case FLASH_5717VENDOR_ATMEL_EEPROM:
11247         case FLASH_5717VENDOR_MICRO_EEPROM:
11248                 tp->nvram_jedecnum = JEDEC_ATMEL;
11249                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11250                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11251
11252                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11253                 tw32(NVRAM_CFG1, nvcfg1);
11254                 return;
11255         case FLASH_5717VENDOR_ATMEL_MDB011D:
11256         case FLASH_5717VENDOR_ATMEL_ADB011B:
11257         case FLASH_5717VENDOR_ATMEL_ADB011D:
11258         case FLASH_5717VENDOR_ATMEL_MDB021D:
11259         case FLASH_5717VENDOR_ATMEL_ADB021B:
11260         case FLASH_5717VENDOR_ATMEL_ADB021D:
11261         case FLASH_5717VENDOR_ATMEL_45USPT:
11262                 tp->nvram_jedecnum = JEDEC_ATMEL;
11263                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11264                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11265
11266                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11267                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11268                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11269                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11270                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11271                         break;
11272                 default:
11273                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11274                         break;
11275                 }
11276                 break;
11277         case FLASH_5717VENDOR_ST_M_M25PE10:
11278         case FLASH_5717VENDOR_ST_A_M25PE10:
11279         case FLASH_5717VENDOR_ST_M_M45PE10:
11280         case FLASH_5717VENDOR_ST_A_M45PE10:
11281         case FLASH_5717VENDOR_ST_M_M25PE20:
11282         case FLASH_5717VENDOR_ST_A_M25PE20:
11283         case FLASH_5717VENDOR_ST_M_M45PE20:
11284         case FLASH_5717VENDOR_ST_A_M45PE20:
11285         case FLASH_5717VENDOR_ST_25USPT:
11286         case FLASH_5717VENDOR_ST_45USPT:
11287                 tp->nvram_jedecnum = JEDEC_ST;
11288                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11289                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11290
11291                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11292                 case FLASH_5717VENDOR_ST_M_M25PE20:
11293                 case FLASH_5717VENDOR_ST_A_M25PE20:
11294                 case FLASH_5717VENDOR_ST_M_M45PE20:
11295                 case FLASH_5717VENDOR_ST_A_M45PE20:
11296                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11297                         break;
11298                 default:
11299                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11300                         break;
11301                 }
11302                 break;
11303         default:
11304                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11305                 return;
11306         }
11307
11308         tg3_nvram_get_pagesize(tp, nvcfg1);
11309         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11310                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11311 }
11312
11313 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11314 static void __devinit tg3_nvram_init(struct tg3 *tp)
11315 {
11316         tw32_f(GRC_EEPROM_ADDR,
11317              (EEPROM_ADDR_FSM_RESET |
11318               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11319                EEPROM_ADDR_CLKPERD_SHIFT)));
11320
11321         msleep(1);
11322
11323         /* Enable seeprom accesses. */
11324         tw32_f(GRC_LOCAL_CTRL,
11325              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11326         udelay(100);
11327
11328         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11329             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11330                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11331
11332                 if (tg3_nvram_lock(tp)) {
11333                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11334                                "tg3_nvram_init failed.\n", tp->dev->name);
11335                         return;
11336                 }
11337                 tg3_enable_nvram_access(tp);
11338
11339                 tp->nvram_size = 0;
11340
11341                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11342                         tg3_get_5752_nvram_info(tp);
11343                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11344                         tg3_get_5755_nvram_info(tp);
11345                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11346                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11347                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11348                         tg3_get_5787_nvram_info(tp);
11349                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11350                         tg3_get_5761_nvram_info(tp);
11351                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11352                         tg3_get_5906_nvram_info(tp);
11353                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11354                         tg3_get_57780_nvram_info(tp);
11355                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11356                         tg3_get_5717_nvram_info(tp);
11357                 else
11358                         tg3_get_nvram_info(tp);
11359
11360                 if (tp->nvram_size == 0)
11361                         tg3_get_nvram_size(tp);
11362
11363                 tg3_disable_nvram_access(tp);
11364                 tg3_nvram_unlock(tp);
11365
11366         } else {
11367                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11368
11369                 tg3_get_eeprom_size(tp);
11370         }
11371 }
11372
11373 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11374                                     u32 offset, u32 len, u8 *buf)
11375 {
11376         int i, j, rc = 0;
11377         u32 val;
11378
11379         for (i = 0; i < len; i += 4) {
11380                 u32 addr;
11381                 __be32 data;
11382
11383                 addr = offset + i;
11384
11385                 memcpy(&data, buf + i, 4);
11386
11387                 /*
11388                  * The SEEPROM interface expects the data to always be opposite
11389                  * the native endian format.  We accomplish this by reversing
11390                  * all the operations that would have been performed on the
11391                  * data from a call to tg3_nvram_read_be32().
11392                  */
11393                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11394
11395                 val = tr32(GRC_EEPROM_ADDR);
11396                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11397
11398                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11399                         EEPROM_ADDR_READ);
11400                 tw32(GRC_EEPROM_ADDR, val |
11401                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11402                         (addr & EEPROM_ADDR_ADDR_MASK) |
11403                         EEPROM_ADDR_START |
11404                         EEPROM_ADDR_WRITE);
11405
11406                 for (j = 0; j < 1000; j++) {
11407                         val = tr32(GRC_EEPROM_ADDR);
11408
11409                         if (val & EEPROM_ADDR_COMPLETE)
11410                                 break;
11411                         msleep(1);
11412                 }
11413                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11414                         rc = -EBUSY;
11415                         break;
11416                 }
11417         }
11418
11419         return rc;
11420 }
11421
11422 /* offset and length are dword aligned */
11423 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11424                 u8 *buf)
11425 {
11426         int ret = 0;
11427         u32 pagesize = tp->nvram_pagesize;
11428         u32 pagemask = pagesize - 1;
11429         u32 nvram_cmd;
11430         u8 *tmp;
11431
11432         tmp = kmalloc(pagesize, GFP_KERNEL);
11433         if (tmp == NULL)
11434                 return -ENOMEM;
11435
11436         while (len) {
11437                 int j;
11438                 u32 phy_addr, page_off, size;
11439
11440                 phy_addr = offset & ~pagemask;
11441
11442                 for (j = 0; j < pagesize; j += 4) {
11443                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11444                                                   (__be32 *) (tmp + j));
11445                         if (ret)
11446                                 break;
11447                 }
11448                 if (ret)
11449                         break;
11450
11451                 page_off = offset & pagemask;
11452                 size = pagesize;
11453                 if (len < size)
11454                         size = len;
11455
11456                 len -= size;
11457
11458                 memcpy(tmp + page_off, buf, size);
11459
11460                 offset = offset + (pagesize - page_off);
11461
11462                 tg3_enable_nvram_access(tp);
11463
11464                 /*
11465                  * Before we can erase the flash page, we need
11466                  * to issue a special "write enable" command.
11467                  */
11468                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11469
11470                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11471                         break;
11472
11473                 /* Erase the target page */
11474                 tw32(NVRAM_ADDR, phy_addr);
11475
11476                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11477                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11478
11479                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11480                         break;
11481
11482                 /* Issue another write enable to start the write. */
11483                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11484
11485                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11486                         break;
11487
11488                 for (j = 0; j < pagesize; j += 4) {
11489                         __be32 data;
11490
11491                         data = *((__be32 *) (tmp + j));
11492
11493                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11494
11495                         tw32(NVRAM_ADDR, phy_addr + j);
11496
11497                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11498                                 NVRAM_CMD_WR;
11499
11500                         if (j == 0)
11501                                 nvram_cmd |= NVRAM_CMD_FIRST;
11502                         else if (j == (pagesize - 4))
11503                                 nvram_cmd |= NVRAM_CMD_LAST;
11504
11505                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11506                                 break;
11507                 }
11508                 if (ret)
11509                         break;
11510         }
11511
11512         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11513         tg3_nvram_exec_cmd(tp, nvram_cmd);
11514
11515         kfree(tmp);
11516
11517         return ret;
11518 }
11519
11520 /* offset and length are dword aligned */
11521 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11522                 u8 *buf)
11523 {
11524         int i, ret = 0;
11525
11526         for (i = 0; i < len; i += 4, offset += 4) {
11527                 u32 page_off, phy_addr, nvram_cmd;
11528                 __be32 data;
11529
11530                 memcpy(&data, buf + i, 4);
11531                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11532
11533                 page_off = offset % tp->nvram_pagesize;
11534
11535                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11536
11537                 tw32(NVRAM_ADDR, phy_addr);
11538
11539                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11540
11541                 if ((page_off == 0) || (i == 0))
11542                         nvram_cmd |= NVRAM_CMD_FIRST;
11543                 if (page_off == (tp->nvram_pagesize - 4))
11544                         nvram_cmd |= NVRAM_CMD_LAST;
11545
11546                 if (i == (len - 4))
11547                         nvram_cmd |= NVRAM_CMD_LAST;
11548
11549                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11550                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11551                     (tp->nvram_jedecnum == JEDEC_ST) &&
11552                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11553
11554                         if ((ret = tg3_nvram_exec_cmd(tp,
11555                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11556                                 NVRAM_CMD_DONE)))
11557
11558                                 break;
11559                 }
11560                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11561                         /* We always do complete word writes to eeprom. */
11562                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11563                 }
11564
11565                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11566                         break;
11567         }
11568         return ret;
11569 }
11570
11571 /* offset and length are dword aligned */
11572 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11573 {
11574         int ret;
11575
11576         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11577                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11578                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11579                 udelay(40);
11580         }
11581
11582         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11583                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11584         }
11585         else {
11586                 u32 grc_mode;
11587
11588                 ret = tg3_nvram_lock(tp);
11589                 if (ret)
11590                         return ret;
11591
11592                 tg3_enable_nvram_access(tp);
11593                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11594                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11595                         tw32(NVRAM_WRITE1, 0x406);
11596
11597                 grc_mode = tr32(GRC_MODE);
11598                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11599
11600                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11601                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11602
11603                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11604                                 buf);
11605                 }
11606                 else {
11607                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11608                                 buf);
11609                 }
11610
11611                 grc_mode = tr32(GRC_MODE);
11612                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11613
11614                 tg3_disable_nvram_access(tp);
11615                 tg3_nvram_unlock(tp);
11616         }
11617
11618         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11619                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11620                 udelay(40);
11621         }
11622
11623         return ret;
11624 }
11625
11626 struct subsys_tbl_ent {
11627         u16 subsys_vendor, subsys_devid;
11628         u32 phy_id;
11629 };
11630
11631 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11632         /* Broadcom boards. */
11633         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11634         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11635         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11636         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11637         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11638         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11639         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11640         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11641         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11642         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11643         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11644
11645         /* 3com boards. */
11646         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11647         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11648         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11649         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11650         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11651
11652         /* DELL boards. */
11653         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11654         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11655         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11656         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11657
11658         /* Compaq boards. */
11659         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11660         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11661         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11662         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11663         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11664
11665         /* IBM boards. */
11666         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11667 };
11668
11669 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11670 {
11671         int i;
11672
11673         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11674                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11675                      tp->pdev->subsystem_vendor) &&
11676                     (subsys_id_to_phy_id[i].subsys_devid ==
11677                      tp->pdev->subsystem_device))
11678                         return &subsys_id_to_phy_id[i];
11679         }
11680         return NULL;
11681 }
11682
11683 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11684 {
11685         u32 val;
11686         u16 pmcsr;
11687
11688         /* On some early chips the SRAM cannot be accessed in D3hot state,
11689          * so need make sure we're in D0.
11690          */
11691         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11692         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11693         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11694         msleep(1);
11695
11696         /* Make sure register accesses (indirect or otherwise)
11697          * will function correctly.
11698          */
11699         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11700                                tp->misc_host_ctrl);
11701
11702         /* The memory arbiter has to be enabled in order for SRAM accesses
11703          * to succeed.  Normally on powerup the tg3 chip firmware will make
11704          * sure it is enabled, but other entities such as system netboot
11705          * code might disable it.
11706          */
11707         val = tr32(MEMARB_MODE);
11708         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11709
11710         tp->phy_id = PHY_ID_INVALID;
11711         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11712
11713         /* Assume an onboard device and WOL capable by default.  */
11714         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11715
11716         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11717                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11718                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11719                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11720                 }
11721                 val = tr32(VCPU_CFGSHDW);
11722                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11723                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11724                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11725                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11726                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11727                 goto done;
11728         }
11729
11730         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11731         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11732                 u32 nic_cfg, led_cfg;
11733                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11734                 int eeprom_phy_serdes = 0;
11735
11736                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11737                 tp->nic_sram_data_cfg = nic_cfg;
11738
11739                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11740                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11741                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11742                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11743                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11744                     (ver > 0) && (ver < 0x100))
11745                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11746
11747                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11748                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11749
11750                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11751                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11752                         eeprom_phy_serdes = 1;
11753
11754                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11755                 if (nic_phy_id != 0) {
11756                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11757                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11758
11759                         eeprom_phy_id  = (id1 >> 16) << 10;
11760                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11761                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11762                 } else
11763                         eeprom_phy_id = 0;
11764
11765                 tp->phy_id = eeprom_phy_id;
11766                 if (eeprom_phy_serdes) {
11767                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11768                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11769                         else
11770                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11771                 }
11772
11773                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11774                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11775                                     SHASTA_EXT_LED_MODE_MASK);
11776                 else
11777                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11778
11779                 switch (led_cfg) {
11780                 default:
11781                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11782                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11783                         break;
11784
11785                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11786                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11787                         break;
11788
11789                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11790                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11791
11792                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11793                          * read on some older 5700/5701 bootcode.
11794                          */
11795                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11796                             ASIC_REV_5700 ||
11797                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11798                             ASIC_REV_5701)
11799                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11800
11801                         break;
11802
11803                 case SHASTA_EXT_LED_SHARED:
11804                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11805                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11806                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11807                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11808                                                  LED_CTRL_MODE_PHY_2);
11809                         break;
11810
11811                 case SHASTA_EXT_LED_MAC:
11812                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11813                         break;
11814
11815                 case SHASTA_EXT_LED_COMBO:
11816                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11817                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11818                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11819                                                  LED_CTRL_MODE_PHY_2);
11820                         break;
11821
11822                 }
11823
11824                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11825                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11826                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11827                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11828
11829                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11830                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11831
11832                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11833                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11834                         if ((tp->pdev->subsystem_vendor ==
11835                              PCI_VENDOR_ID_ARIMA) &&
11836                             (tp->pdev->subsystem_device == 0x205a ||
11837                              tp->pdev->subsystem_device == 0x2063))
11838                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11839                 } else {
11840                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11841                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11842                 }
11843
11844                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11845                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11846                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11847                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11848                 }
11849
11850                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11851                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11852                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11853
11854                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11855                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11856                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11857
11858                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11859                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11860                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11861
11862                 if (cfg2 & (1 << 17))
11863                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11864
11865                 /* serdes signal pre-emphasis in register 0x590 set by */
11866                 /* bootcode if bit 18 is set */
11867                 if (cfg2 & (1 << 18))
11868                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11869
11870                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11871                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11872                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11873                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11874
11875                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11876                         u32 cfg3;
11877
11878                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11879                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11880                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11881                 }
11882
11883                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11884                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11885                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11886                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11887                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11888                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11889         }
11890 done:
11891         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11892         device_set_wakeup_enable(&tp->pdev->dev,
11893                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11894 }
11895
11896 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11897 {
11898         int i;
11899         u32 val;
11900
11901         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11902         tw32(OTP_CTRL, cmd);
11903
11904         /* Wait for up to 1 ms for command to execute. */
11905         for (i = 0; i < 100; i++) {
11906                 val = tr32(OTP_STATUS);
11907                 if (val & OTP_STATUS_CMD_DONE)
11908                         break;
11909                 udelay(10);
11910         }
11911
11912         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11913 }
11914
11915 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11916  * configuration is a 32-bit value that straddles the alignment boundary.
11917  * We do two 32-bit reads and then shift and merge the results.
11918  */
11919 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11920 {
11921         u32 bhalf_otp, thalf_otp;
11922
11923         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11924
11925         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11926                 return 0;
11927
11928         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11929
11930         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11931                 return 0;
11932
11933         thalf_otp = tr32(OTP_READ_DATA);
11934
11935         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11936
11937         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11938                 return 0;
11939
11940         bhalf_otp = tr32(OTP_READ_DATA);
11941
11942         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11943 }
11944
11945 static int __devinit tg3_phy_probe(struct tg3 *tp)
11946 {
11947         u32 hw_phy_id_1, hw_phy_id_2;
11948         u32 hw_phy_id, hw_phy_id_masked;
11949         int err;
11950
11951         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11952                 return tg3_phy_init(tp);
11953
11954         /* Reading the PHY ID register can conflict with ASF
11955          * firmware access to the PHY hardware.
11956          */
11957         err = 0;
11958         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11959             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11960                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11961         } else {
11962                 /* Now read the physical PHY_ID from the chip and verify
11963                  * that it is sane.  If it doesn't look good, we fall back
11964                  * to either the hard-coded table based PHY_ID and failing
11965                  * that the value found in the eeprom area.
11966                  */
11967                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11968                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11969
11970                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11971                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11972                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11973
11974                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11975         }
11976
11977         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11978                 tp->phy_id = hw_phy_id;
11979                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11980                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11981                 else
11982                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11983         } else {
11984                 if (tp->phy_id != PHY_ID_INVALID) {
11985                         /* Do nothing, phy ID already set up in
11986                          * tg3_get_eeprom_hw_cfg().
11987                          */
11988                 } else {
11989                         struct subsys_tbl_ent *p;
11990
11991                         /* No eeprom signature?  Try the hardcoded
11992                          * subsys device table.
11993                          */
11994                         p = lookup_by_subsys(tp);
11995                         if (!p)
11996                                 return -ENODEV;
11997
11998                         tp->phy_id = p->phy_id;
11999                         if (!tp->phy_id ||
12000                             tp->phy_id == PHY_ID_BCM8002)
12001                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12002                 }
12003         }
12004
12005         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12006             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12007             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12008                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12009
12010                 tg3_readphy(tp, MII_BMSR, &bmsr);
12011                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12012                     (bmsr & BMSR_LSTATUS))
12013                         goto skip_phy_reset;
12014
12015                 err = tg3_phy_reset(tp);
12016                 if (err)
12017                         return err;
12018
12019                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12020                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12021                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12022                 tg3_ctrl = 0;
12023                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12024                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12025                                     MII_TG3_CTRL_ADV_1000_FULL);
12026                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12027                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12028                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12029                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12030                 }
12031
12032                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12033                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12034                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12035                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12036                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12037
12038                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12039                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12040
12041                         tg3_writephy(tp, MII_BMCR,
12042                                      BMCR_ANENABLE | BMCR_ANRESTART);
12043                 }
12044                 tg3_phy_set_wirespeed(tp);
12045
12046                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12047                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12048                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12049         }
12050
12051 skip_phy_reset:
12052         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12053                 err = tg3_init_5401phy_dsp(tp);
12054                 if (err)
12055                         return err;
12056         }
12057
12058         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12059                 err = tg3_init_5401phy_dsp(tp);
12060         }
12061
12062         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12063                 tp->link_config.advertising =
12064                         (ADVERTISED_1000baseT_Half |
12065                          ADVERTISED_1000baseT_Full |
12066                          ADVERTISED_Autoneg |
12067                          ADVERTISED_FIBRE);
12068         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12069                 tp->link_config.advertising &=
12070                         ~(ADVERTISED_1000baseT_Half |
12071                           ADVERTISED_1000baseT_Full);
12072
12073         return err;
12074 }
12075
12076 static void __devinit tg3_read_partno(struct tg3 *tp)
12077 {
12078         unsigned char vpd_data[256];   /* in little-endian format */
12079         unsigned int i;
12080         u32 magic;
12081
12082         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12083             tg3_nvram_read(tp, 0x0, &magic))
12084                 goto out_not_found;
12085
12086         if (magic == TG3_EEPROM_MAGIC) {
12087                 for (i = 0; i < 256; i += 4) {
12088                         u32 tmp;
12089
12090                         /* The data is in little-endian format in NVRAM.
12091                          * Use the big-endian read routines to preserve
12092                          * the byte order as it exists in NVRAM.
12093                          */
12094                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12095                                 goto out_not_found;
12096
12097                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12098                 }
12099         } else {
12100                 int vpd_cap;
12101
12102                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12103                 for (i = 0; i < 256; i += 4) {
12104                         u32 tmp, j = 0;
12105                         __le32 v;
12106                         u16 tmp16;
12107
12108                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12109                                               i);
12110                         while (j++ < 100) {
12111                                 pci_read_config_word(tp->pdev, vpd_cap +
12112                                                      PCI_VPD_ADDR, &tmp16);
12113                                 if (tmp16 & 0x8000)
12114                                         break;
12115                                 msleep(1);
12116                         }
12117                         if (!(tmp16 & 0x8000))
12118                                 goto out_not_found;
12119
12120                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12121                                               &tmp);
12122                         v = cpu_to_le32(tmp);
12123                         memcpy(&vpd_data[i], &v, sizeof(v));
12124                 }
12125         }
12126
12127         /* Now parse and find the part number. */
12128         for (i = 0; i < 254; ) {
12129                 unsigned char val = vpd_data[i];
12130                 unsigned int block_end;
12131
12132                 if (val == 0x82 || val == 0x91) {
12133                         i = (i + 3 +
12134                              (vpd_data[i + 1] +
12135                               (vpd_data[i + 2] << 8)));
12136                         continue;
12137                 }
12138
12139                 if (val != 0x90)
12140                         goto out_not_found;
12141
12142                 block_end = (i + 3 +
12143                              (vpd_data[i + 1] +
12144                               (vpd_data[i + 2] << 8)));
12145                 i += 3;
12146
12147                 if (block_end > 256)
12148                         goto out_not_found;
12149
12150                 while (i < (block_end - 2)) {
12151                         if (vpd_data[i + 0] == 'P' &&
12152                             vpd_data[i + 1] == 'N') {
12153                                 int partno_len = vpd_data[i + 2];
12154
12155                                 i += 3;
12156                                 if (partno_len > 24 || (partno_len + i) > 256)
12157                                         goto out_not_found;
12158
12159                                 memcpy(tp->board_part_number,
12160                                        &vpd_data[i], partno_len);
12161
12162                                 /* Success. */
12163                                 return;
12164                         }
12165                         i += 3 + vpd_data[i + 2];
12166                 }
12167
12168                 /* Part number not found. */
12169                 goto out_not_found;
12170         }
12171
12172 out_not_found:
12173         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12174                 strcpy(tp->board_part_number, "BCM95906");
12175         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12176                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12177                 strcpy(tp->board_part_number, "BCM57780");
12178         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12179                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12180                 strcpy(tp->board_part_number, "BCM57760");
12181         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12182                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12183                 strcpy(tp->board_part_number, "BCM57790");
12184         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12185                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12186                 strcpy(tp->board_part_number, "BCM57788");
12187         else
12188                 strcpy(tp->board_part_number, "none");
12189 }
12190
12191 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12192 {
12193         u32 val;
12194
12195         if (tg3_nvram_read(tp, offset, &val) ||
12196             (val & 0xfc000000) != 0x0c000000 ||
12197             tg3_nvram_read(tp, offset + 4, &val) ||
12198             val != 0)
12199                 return 0;
12200
12201         return 1;
12202 }
12203
12204 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12205 {
12206         u32 val, offset, start, ver_offset;
12207         int i;
12208         bool newver = false;
12209
12210         if (tg3_nvram_read(tp, 0xc, &offset) ||
12211             tg3_nvram_read(tp, 0x4, &start))
12212                 return;
12213
12214         offset = tg3_nvram_logical_addr(tp, offset);
12215
12216         if (tg3_nvram_read(tp, offset, &val))
12217                 return;
12218
12219         if ((val & 0xfc000000) == 0x0c000000) {
12220                 if (tg3_nvram_read(tp, offset + 4, &val))
12221                         return;
12222
12223                 if (val == 0)
12224                         newver = true;
12225         }
12226
12227         if (newver) {
12228                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12229                         return;
12230
12231                 offset = offset + ver_offset - start;
12232                 for (i = 0; i < 16; i += 4) {
12233                         __be32 v;
12234                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12235                                 return;
12236
12237                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12238                 }
12239         } else {
12240                 u32 major, minor;
12241
12242                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12243                         return;
12244
12245                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12246                         TG3_NVM_BCVER_MAJSFT;
12247                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12248                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12249         }
12250 }
12251
12252 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12253 {
12254         u32 val, major, minor;
12255
12256         /* Use native endian representation */
12257         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12258                 return;
12259
12260         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12261                 TG3_NVM_HWSB_CFG1_MAJSFT;
12262         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12263                 TG3_NVM_HWSB_CFG1_MINSFT;
12264
12265         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12266 }
12267
12268 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12269 {
12270         u32 offset, major, minor, build;
12271
12272         tp->fw_ver[0] = 's';
12273         tp->fw_ver[1] = 'b';
12274         tp->fw_ver[2] = '\0';
12275
12276         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12277                 return;
12278
12279         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12280         case TG3_EEPROM_SB_REVISION_0:
12281                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12282                 break;
12283         case TG3_EEPROM_SB_REVISION_2:
12284                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12285                 break;
12286         case TG3_EEPROM_SB_REVISION_3:
12287                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12288                 break;
12289         default:
12290                 return;
12291         }
12292
12293         if (tg3_nvram_read(tp, offset, &val))
12294                 return;
12295
12296         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12297                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12298         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12299                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12300         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12301
12302         if (minor > 99 || build > 26)
12303                 return;
12304
12305         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12306
12307         if (build > 0) {
12308                 tp->fw_ver[8] = 'a' + build - 1;
12309                 tp->fw_ver[9] = '\0';
12310         }
12311 }
12312
12313 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12314 {
12315         u32 val, offset, start;
12316         int i, vlen;
12317
12318         for (offset = TG3_NVM_DIR_START;
12319              offset < TG3_NVM_DIR_END;
12320              offset += TG3_NVM_DIRENT_SIZE) {
12321                 if (tg3_nvram_read(tp, offset, &val))
12322                         return;
12323
12324                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12325                         break;
12326         }
12327
12328         if (offset == TG3_NVM_DIR_END)
12329                 return;
12330
12331         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12332                 start = 0x08000000;
12333         else if (tg3_nvram_read(tp, offset - 4, &start))
12334                 return;
12335
12336         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12337             !tg3_fw_img_is_valid(tp, offset) ||
12338             tg3_nvram_read(tp, offset + 8, &val))
12339                 return;
12340
12341         offset += val - start;
12342
12343         vlen = strlen(tp->fw_ver);
12344
12345         tp->fw_ver[vlen++] = ',';
12346         tp->fw_ver[vlen++] = ' ';
12347
12348         for (i = 0; i < 4; i++) {
12349                 __be32 v;
12350                 if (tg3_nvram_read_be32(tp, offset, &v))
12351                         return;
12352
12353                 offset += sizeof(v);
12354
12355                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12356                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12357                         break;
12358                 }
12359
12360                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12361                 vlen += sizeof(v);
12362         }
12363 }
12364
12365 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12366 {
12367         int vlen;
12368         u32 apedata;
12369
12370         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12371             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12372                 return;
12373
12374         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12375         if (apedata != APE_SEG_SIG_MAGIC)
12376                 return;
12377
12378         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12379         if (!(apedata & APE_FW_STATUS_READY))
12380                 return;
12381
12382         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12383
12384         vlen = strlen(tp->fw_ver);
12385
12386         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12387                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12388                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12389                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12390                  (apedata & APE_FW_VERSION_BLDMSK));
12391 }
12392
12393 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12394 {
12395         u32 val;
12396
12397         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12398                 tp->fw_ver[0] = 's';
12399                 tp->fw_ver[1] = 'b';
12400                 tp->fw_ver[2] = '\0';
12401
12402                 return;
12403         }
12404
12405         if (tg3_nvram_read(tp, 0, &val))
12406                 return;
12407
12408         if (val == TG3_EEPROM_MAGIC)
12409                 tg3_read_bc_ver(tp);
12410         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12411                 tg3_read_sb_ver(tp, val);
12412         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12413                 tg3_read_hwsb_ver(tp);
12414         else
12415                 return;
12416
12417         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12418              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12419                 return;
12420
12421         tg3_read_mgmtfw_ver(tp);
12422
12423         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12424 }
12425
12426 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12427
12428 static int __devinit tg3_get_invariants(struct tg3 *tp)
12429 {
12430         static struct pci_device_id write_reorder_chipsets[] = {
12431                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12432                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12433                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12434                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12435                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12436                              PCI_DEVICE_ID_VIA_8385_0) },
12437                 { },
12438         };
12439         u32 misc_ctrl_reg;
12440         u32 pci_state_reg, grc_misc_cfg;
12441         u32 val;
12442         u16 pci_cmd;
12443         int err;
12444
12445         /* Force memory write invalidate off.  If we leave it on,
12446          * then on 5700_BX chips we have to enable a workaround.
12447          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12448          * to match the cacheline size.  The Broadcom driver have this
12449          * workaround but turns MWI off all the times so never uses
12450          * it.  This seems to suggest that the workaround is insufficient.
12451          */
12452         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12453         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12454         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12455
12456         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12457          * has the register indirect write enable bit set before
12458          * we try to access any of the MMIO registers.  It is also
12459          * critical that the PCI-X hw workaround situation is decided
12460          * before that as well.
12461          */
12462         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12463                               &misc_ctrl_reg);
12464
12465         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12466                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12467         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12468                 u32 prod_id_asic_rev;
12469
12470                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12471                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12472                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12473                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12474                         pci_read_config_dword(tp->pdev,
12475                                               TG3PCI_GEN2_PRODID_ASICREV,
12476                                               &prod_id_asic_rev);
12477                 else
12478                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12479                                               &prod_id_asic_rev);
12480
12481                 tp->pci_chip_rev_id = prod_id_asic_rev;
12482         }
12483
12484         /* Wrong chip ID in 5752 A0. This code can be removed later
12485          * as A0 is not in production.
12486          */
12487         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12488                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12489
12490         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12491          * we need to disable memory and use config. cycles
12492          * only to access all registers. The 5702/03 chips
12493          * can mistakenly decode the special cycles from the
12494          * ICH chipsets as memory write cycles, causing corruption
12495          * of register and memory space. Only certain ICH bridges
12496          * will drive special cycles with non-zero data during the
12497          * address phase which can fall within the 5703's address
12498          * range. This is not an ICH bug as the PCI spec allows
12499          * non-zero address during special cycles. However, only
12500          * these ICH bridges are known to drive non-zero addresses
12501          * during special cycles.
12502          *
12503          * Since special cycles do not cross PCI bridges, we only
12504          * enable this workaround if the 5703 is on the secondary
12505          * bus of these ICH bridges.
12506          */
12507         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12508             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12509                 static struct tg3_dev_id {
12510                         u32     vendor;
12511                         u32     device;
12512                         u32     rev;
12513                 } ich_chipsets[] = {
12514                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12515                           PCI_ANY_ID },
12516                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12517                           PCI_ANY_ID },
12518                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12519                           0xa },
12520                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12521                           PCI_ANY_ID },
12522                         { },
12523                 };
12524                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12525                 struct pci_dev *bridge = NULL;
12526
12527                 while (pci_id->vendor != 0) {
12528                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12529                                                 bridge);
12530                         if (!bridge) {
12531                                 pci_id++;
12532                                 continue;
12533                         }
12534                         if (pci_id->rev != PCI_ANY_ID) {
12535                                 if (bridge->revision > pci_id->rev)
12536                                         continue;
12537                         }
12538                         if (bridge->subordinate &&
12539                             (bridge->subordinate->number ==
12540                              tp->pdev->bus->number)) {
12541
12542                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12543                                 pci_dev_put(bridge);
12544                                 break;
12545                         }
12546                 }
12547         }
12548
12549         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12550                 static struct tg3_dev_id {
12551                         u32     vendor;
12552                         u32     device;
12553                 } bridge_chipsets[] = {
12554                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12555                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12556                         { },
12557                 };
12558                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12559                 struct pci_dev *bridge = NULL;
12560
12561                 while (pci_id->vendor != 0) {
12562                         bridge = pci_get_device(pci_id->vendor,
12563                                                 pci_id->device,
12564                                                 bridge);
12565                         if (!bridge) {
12566                                 pci_id++;
12567                                 continue;
12568                         }
12569                         if (bridge->subordinate &&
12570                             (bridge->subordinate->number <=
12571                              tp->pdev->bus->number) &&
12572                             (bridge->subordinate->subordinate >=
12573                              tp->pdev->bus->number)) {
12574                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12575                                 pci_dev_put(bridge);
12576                                 break;
12577                         }
12578                 }
12579         }
12580
12581         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12582          * DMA addresses > 40-bit. This bridge may have other additional
12583          * 57xx devices behind it in some 4-port NIC designs for example.
12584          * Any tg3 device found behind the bridge will also need the 40-bit
12585          * DMA workaround.
12586          */
12587         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12588             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12589                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12590                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12591                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12592         }
12593         else {
12594                 struct pci_dev *bridge = NULL;
12595
12596                 do {
12597                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12598                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12599                                                 bridge);
12600                         if (bridge && bridge->subordinate &&
12601                             (bridge->subordinate->number <=
12602                              tp->pdev->bus->number) &&
12603                             (bridge->subordinate->subordinate >=
12604                              tp->pdev->bus->number)) {
12605                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12606                                 pci_dev_put(bridge);
12607                                 break;
12608                         }
12609                 } while (bridge);
12610         }
12611
12612         /* Initialize misc host control in PCI block. */
12613         tp->misc_host_ctrl |= (misc_ctrl_reg &
12614                                MISC_HOST_CTRL_CHIPREV);
12615         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12616                                tp->misc_host_ctrl);
12617
12618         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12619             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12620             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12621                 tp->pdev_peer = tg3_find_peer(tp);
12622
12623         /* Intentionally exclude ASIC_REV_5906 */
12624         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12625             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12626             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12627             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12628             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12629             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12630             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12631                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12632
12633         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12634             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12635             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12636             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12637             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12638                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12639
12640         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12641             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12642                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12643
12644         /* 5700 B0 chips do not support checksumming correctly due
12645          * to hardware bugs.
12646          */
12647         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12648                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12649         else {
12650                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12651                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12652                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12653                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12654         }
12655
12656         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12657                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12658                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12659                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12660                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12661                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12662                      tp->pdev_peer == tp->pdev))
12663                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12664
12665                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12666                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12667                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12668                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12669                 } else {
12670                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12671                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12672                                 ASIC_REV_5750 &&
12673                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12674                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12675                 }
12676         }
12677
12678         tp->irq_max = 1;
12679
12680         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12681                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12682                 tp->irq_max = TG3_IRQ_MAX_VECS;
12683         }
12684
12685         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12686                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12687                         tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12688                 else {
12689                         tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12690                         tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12691                 }
12692         }
12693
12694         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12695              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12696             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12697                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12698
12699         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12700                               &pci_state_reg);
12701
12702         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12703         if (tp->pcie_cap != 0) {
12704                 u16 lnkctl;
12705
12706                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12707
12708                 pcie_set_readrq(tp->pdev, 4096);
12709
12710                 pci_read_config_word(tp->pdev,
12711                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12712                                      &lnkctl);
12713                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12714                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12715                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12716                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12717                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12718                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12719                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12720                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12721                 }
12722         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12723                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12724         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12725                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12726                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12727                 if (!tp->pcix_cap) {
12728                         printk(KERN_ERR PFX "Cannot find PCI-X "
12729                                             "capability, aborting.\n");
12730                         return -EIO;
12731                 }
12732
12733                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12734                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12735         }
12736
12737         /* If we have an AMD 762 or VIA K8T800 chipset, write
12738          * reordering to the mailbox registers done by the host
12739          * controller can cause major troubles.  We read back from
12740          * every mailbox register write to force the writes to be
12741          * posted to the chip in order.
12742          */
12743         if (pci_dev_present(write_reorder_chipsets) &&
12744             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12745                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12746
12747         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12748                              &tp->pci_cacheline_sz);
12749         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12750                              &tp->pci_lat_timer);
12751         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12752             tp->pci_lat_timer < 64) {
12753                 tp->pci_lat_timer = 64;
12754                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12755                                       tp->pci_lat_timer);
12756         }
12757
12758         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12759                 /* 5700 BX chips need to have their TX producer index
12760                  * mailboxes written twice to workaround a bug.
12761                  */
12762                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12763
12764                 /* If we are in PCI-X mode, enable register write workaround.
12765                  *
12766                  * The workaround is to use indirect register accesses
12767                  * for all chip writes not to mailbox registers.
12768                  */
12769                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12770                         u32 pm_reg;
12771
12772                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12773
12774                         /* The chip can have it's power management PCI config
12775                          * space registers clobbered due to this bug.
12776                          * So explicitly force the chip into D0 here.
12777                          */
12778                         pci_read_config_dword(tp->pdev,
12779                                               tp->pm_cap + PCI_PM_CTRL,
12780                                               &pm_reg);
12781                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12782                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12783                         pci_write_config_dword(tp->pdev,
12784                                                tp->pm_cap + PCI_PM_CTRL,
12785                                                pm_reg);
12786
12787                         /* Also, force SERR#/PERR# in PCI command. */
12788                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12789                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12790                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12791                 }
12792         }
12793
12794         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12795                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12796         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12797                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12798
12799         /* Chip-specific fixup from Broadcom driver */
12800         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12801             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12802                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12803                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12804         }
12805
12806         /* Default fast path register access methods */
12807         tp->read32 = tg3_read32;
12808         tp->write32 = tg3_write32;
12809         tp->read32_mbox = tg3_read32;
12810         tp->write32_mbox = tg3_write32;
12811         tp->write32_tx_mbox = tg3_write32;
12812         tp->write32_rx_mbox = tg3_write32;
12813
12814         /* Various workaround register access methods */
12815         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12816                 tp->write32 = tg3_write_indirect_reg32;
12817         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12818                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12819                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12820                 /*
12821                  * Back to back register writes can cause problems on these
12822                  * chips, the workaround is to read back all reg writes
12823                  * except those to mailbox regs.
12824                  *
12825                  * See tg3_write_indirect_reg32().
12826                  */
12827                 tp->write32 = tg3_write_flush_reg32;
12828         }
12829
12830         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12831             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12832                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12833                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12834                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12835         }
12836
12837         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12838                 tp->read32 = tg3_read_indirect_reg32;
12839                 tp->write32 = tg3_write_indirect_reg32;
12840                 tp->read32_mbox = tg3_read_indirect_mbox;
12841                 tp->write32_mbox = tg3_write_indirect_mbox;
12842                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12843                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12844
12845                 iounmap(tp->regs);
12846                 tp->regs = NULL;
12847
12848                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12849                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12850                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12851         }
12852         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12853                 tp->read32_mbox = tg3_read32_mbox_5906;
12854                 tp->write32_mbox = tg3_write32_mbox_5906;
12855                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12856                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12857         }
12858
12859         if (tp->write32 == tg3_write_indirect_reg32 ||
12860             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12861              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12862               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12863                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12864
12865         /* Get eeprom hw config before calling tg3_set_power_state().
12866          * In particular, the TG3_FLG2_IS_NIC flag must be
12867          * determined before calling tg3_set_power_state() so that
12868          * we know whether or not to switch out of Vaux power.
12869          * When the flag is set, it means that GPIO1 is used for eeprom
12870          * write protect and also implies that it is a LOM where GPIOs
12871          * are not used to switch power.
12872          */
12873         tg3_get_eeprom_hw_cfg(tp);
12874
12875         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12876                 /* Allow reads and writes to the
12877                  * APE register and memory space.
12878                  */
12879                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12880                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12881                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12882                                        pci_state_reg);
12883         }
12884
12885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12886             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12887             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12888             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12889             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12890                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12891
12892         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12893          * GPIO1 driven high will bring 5700's external PHY out of reset.
12894          * It is also used as eeprom write protect on LOMs.
12895          */
12896         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12897         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12898             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12899                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12900                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12901         /* Unused GPIO3 must be driven as output on 5752 because there
12902          * are no pull-up resistors on unused GPIO pins.
12903          */
12904         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12905                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12906
12907         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12908             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12909                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12910
12911         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12912             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12913                 /* Turn off the debug UART. */
12914                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12915                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12916                         /* Keep VMain power. */
12917                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12918                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12919         }
12920
12921         /* Force the chip into D0. */
12922         err = tg3_set_power_state(tp, PCI_D0);
12923         if (err) {
12924                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12925                        pci_name(tp->pdev));
12926                 return err;
12927         }
12928
12929         /* Derive initial jumbo mode from MTU assigned in
12930          * ether_setup() via the alloc_etherdev() call
12931          */
12932         if (tp->dev->mtu > ETH_DATA_LEN &&
12933             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12934                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12935
12936         /* Determine WakeOnLan speed to use. */
12937         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12938             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12939             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12940             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12941                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12942         } else {
12943                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12944         }
12945
12946         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12947                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12948
12949         /* A few boards don't want Ethernet@WireSpeed phy feature */
12950         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12951             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12952              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12953              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12954             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12955             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12956                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12957
12958         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12959             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12960                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12961         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12962                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12963
12964         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12965             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12966             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12967             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12968             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12969                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12970                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12971                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12972                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12973                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12974                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12975                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12976                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12977                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12978                 } else
12979                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12980         }
12981
12982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12983             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12984                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12985                 if (tp->phy_otp == 0)
12986                         tp->phy_otp = TG3_OTP_DEFAULT;
12987         }
12988
12989         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12990                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12991         else
12992                 tp->mi_mode = MAC_MI_MODE_BASE;
12993
12994         tp->coalesce_mode = 0;
12995         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12996             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12997                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12998
12999         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13001                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13002
13003         err = tg3_mdio_init(tp);
13004         if (err)
13005                 return err;
13006
13007         /* Initialize data/descriptor byte/word swapping. */
13008         val = tr32(GRC_MODE);
13009         val &= GRC_MODE_HOST_STACKUP;
13010         tw32(GRC_MODE, val | tp->grc_mode);
13011
13012         tg3_switch_clocks(tp);
13013
13014         /* Clear this out for sanity. */
13015         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13016
13017         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13018                               &pci_state_reg);
13019         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13020             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13021                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13022
13023                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13024                     chiprevid == CHIPREV_ID_5701_B0 ||
13025                     chiprevid == CHIPREV_ID_5701_B2 ||
13026                     chiprevid == CHIPREV_ID_5701_B5) {
13027                         void __iomem *sram_base;
13028
13029                         /* Write some dummy words into the SRAM status block
13030                          * area, see if it reads back correctly.  If the return
13031                          * value is bad, force enable the PCIX workaround.
13032                          */
13033                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13034
13035                         writel(0x00000000, sram_base);
13036                         writel(0x00000000, sram_base + 4);
13037                         writel(0xffffffff, sram_base + 4);
13038                         if (readl(sram_base) != 0x00000000)
13039                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13040                 }
13041         }
13042
13043         udelay(50);
13044         tg3_nvram_init(tp);
13045
13046         grc_misc_cfg = tr32(GRC_MISC_CFG);
13047         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13048
13049         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13050             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13051              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13052                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13053
13054         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13055             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13056                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13057         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13058                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13059                                       HOSTCC_MODE_CLRTICK_TXBD);
13060
13061                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13062                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13063                                        tp->misc_host_ctrl);
13064         }
13065
13066         /* Preserve the APE MAC_MODE bits */
13067         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13068                 tp->mac_mode = tr32(MAC_MODE) |
13069                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13070         else
13071                 tp->mac_mode = TG3_DEF_MAC_MODE;
13072
13073         /* these are limited to 10/100 only */
13074         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13075              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13076             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13077              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13078              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13079               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13080               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13081             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13082              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13083               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13084               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13085             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13086             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13087                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13088
13089         err = tg3_phy_probe(tp);
13090         if (err) {
13091                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13092                        pci_name(tp->pdev), err);
13093                 /* ... but do not return immediately ... */
13094                 tg3_mdio_fini(tp);
13095         }
13096
13097         tg3_read_partno(tp);
13098         tg3_read_fw_ver(tp);
13099
13100         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13101                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13102         } else {
13103                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13104                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13105                 else
13106                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13107         }
13108
13109         /* 5700 {AX,BX} chips have a broken status block link
13110          * change bit implementation, so we must use the
13111          * status register in those cases.
13112          */
13113         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13114                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13115         else
13116                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13117
13118         /* The led_ctrl is set during tg3_phy_probe, here we might
13119          * have to force the link status polling mechanism based
13120          * upon subsystem IDs.
13121          */
13122         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13123             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13124             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13125                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13126                                   TG3_FLAG_USE_LINKCHG_REG);
13127         }
13128
13129         /* For all SERDES we poll the MAC status register. */
13130         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13131                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13132         else
13133                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13134
13135         tp->rx_offset = NET_IP_ALIGN;
13136         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13137             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13138                 tp->rx_offset = 0;
13139
13140         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13141
13142         /* Increment the rx prod index on the rx std ring by at most
13143          * 8 for these chips to workaround hw errata.
13144          */
13145         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13146             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13147             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13148                 tp->rx_std_max_post = 8;
13149
13150         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13151                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13152                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13153
13154         return err;
13155 }
13156
13157 #ifdef CONFIG_SPARC
13158 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13159 {
13160         struct net_device *dev = tp->dev;
13161         struct pci_dev *pdev = tp->pdev;
13162         struct device_node *dp = pci_device_to_OF_node(pdev);
13163         const unsigned char *addr;
13164         int len;
13165
13166         addr = of_get_property(dp, "local-mac-address", &len);
13167         if (addr && len == 6) {
13168                 memcpy(dev->dev_addr, addr, 6);
13169                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13170                 return 0;
13171         }
13172         return -ENODEV;
13173 }
13174
13175 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13176 {
13177         struct net_device *dev = tp->dev;
13178
13179         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13180         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13181         return 0;
13182 }
13183 #endif
13184
13185 static int __devinit tg3_get_device_address(struct tg3 *tp)
13186 {
13187         struct net_device *dev = tp->dev;
13188         u32 hi, lo, mac_offset;
13189         int addr_ok = 0;
13190
13191 #ifdef CONFIG_SPARC
13192         if (!tg3_get_macaddr_sparc(tp))
13193                 return 0;
13194 #endif
13195
13196         mac_offset = 0x7c;
13197         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13198             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13199                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13200                         mac_offset = 0xcc;
13201                 if (tg3_nvram_lock(tp))
13202                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13203                 else
13204                         tg3_nvram_unlock(tp);
13205         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13206                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13207                         mac_offset = 0xcc;
13208         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13209                 mac_offset = 0x10;
13210
13211         /* First try to get it from MAC address mailbox. */
13212         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13213         if ((hi >> 16) == 0x484b) {
13214                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13215                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13216
13217                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13218                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13219                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13220                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13221                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13222
13223                 /* Some old bootcode may report a 0 MAC address in SRAM */
13224                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13225         }
13226         if (!addr_ok) {
13227                 /* Next, try NVRAM. */
13228                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13229                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13230                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13231                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13232                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13233                 }
13234                 /* Finally just fetch it out of the MAC control regs. */
13235                 else {
13236                         hi = tr32(MAC_ADDR_0_HIGH);
13237                         lo = tr32(MAC_ADDR_0_LOW);
13238
13239                         dev->dev_addr[5] = lo & 0xff;
13240                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13241                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13242                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13243                         dev->dev_addr[1] = hi & 0xff;
13244                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13245                 }
13246         }
13247
13248         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13249 #ifdef CONFIG_SPARC
13250                 if (!tg3_get_default_macaddr_sparc(tp))
13251                         return 0;
13252 #endif
13253                 return -EINVAL;
13254         }
13255         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13256         return 0;
13257 }
13258
13259 #define BOUNDARY_SINGLE_CACHELINE       1
13260 #define BOUNDARY_MULTI_CACHELINE        2
13261
13262 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13263 {
13264         int cacheline_size;
13265         u8 byte;
13266         int goal;
13267
13268         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13269         if (byte == 0)
13270                 cacheline_size = 1024;
13271         else
13272                 cacheline_size = (int) byte * 4;
13273
13274         /* On 5703 and later chips, the boundary bits have no
13275          * effect.
13276          */
13277         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13278             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13279             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13280                 goto out;
13281
13282 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13283         goal = BOUNDARY_MULTI_CACHELINE;
13284 #else
13285 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13286         goal = BOUNDARY_SINGLE_CACHELINE;
13287 #else
13288         goal = 0;
13289 #endif
13290 #endif
13291
13292         if (!goal)
13293                 goto out;
13294
13295         /* PCI controllers on most RISC systems tend to disconnect
13296          * when a device tries to burst across a cache-line boundary.
13297          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13298          *
13299          * Unfortunately, for PCI-E there are only limited
13300          * write-side controls for this, and thus for reads
13301          * we will still get the disconnects.  We'll also waste
13302          * these PCI cycles for both read and write for chips
13303          * other than 5700 and 5701 which do not implement the
13304          * boundary bits.
13305          */
13306         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13307             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13308                 switch (cacheline_size) {
13309                 case 16:
13310                 case 32:
13311                 case 64:
13312                 case 128:
13313                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13314                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13315                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13316                         } else {
13317                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13318                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13319                         }
13320                         break;
13321
13322                 case 256:
13323                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13324                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13325                         break;
13326
13327                 default:
13328                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13329                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13330                         break;
13331                 }
13332         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13333                 switch (cacheline_size) {
13334                 case 16:
13335                 case 32:
13336                 case 64:
13337                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13338                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13339                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13340                                 break;
13341                         }
13342                         /* fallthrough */
13343                 case 128:
13344                 default:
13345                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13346                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13347                         break;
13348                 }
13349         } else {
13350                 switch (cacheline_size) {
13351                 case 16:
13352                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13353                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13354                                         DMA_RWCTRL_WRITE_BNDRY_16);
13355                                 break;
13356                         }
13357                         /* fallthrough */
13358                 case 32:
13359                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13360                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13361                                         DMA_RWCTRL_WRITE_BNDRY_32);
13362                                 break;
13363                         }
13364                         /* fallthrough */
13365                 case 64:
13366                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13367                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13368                                         DMA_RWCTRL_WRITE_BNDRY_64);
13369                                 break;
13370                         }
13371                         /* fallthrough */
13372                 case 128:
13373                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13374                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13375                                         DMA_RWCTRL_WRITE_BNDRY_128);
13376                                 break;
13377                         }
13378                         /* fallthrough */
13379                 case 256:
13380                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13381                                 DMA_RWCTRL_WRITE_BNDRY_256);
13382                         break;
13383                 case 512:
13384                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13385                                 DMA_RWCTRL_WRITE_BNDRY_512);
13386                         break;
13387                 case 1024:
13388                 default:
13389                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13390                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13391                         break;
13392                 }
13393         }
13394
13395 out:
13396         return val;
13397 }
13398
13399 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13400 {
13401         struct tg3_internal_buffer_desc test_desc;
13402         u32 sram_dma_descs;
13403         int i, ret;
13404
13405         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13406
13407         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13408         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13409         tw32(RDMAC_STATUS, 0);
13410         tw32(WDMAC_STATUS, 0);
13411
13412         tw32(BUFMGR_MODE, 0);
13413         tw32(FTQ_RESET, 0);
13414
13415         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13416         test_desc.addr_lo = buf_dma & 0xffffffff;
13417         test_desc.nic_mbuf = 0x00002100;
13418         test_desc.len = size;
13419
13420         /*
13421          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13422          * the *second* time the tg3 driver was getting loaded after an
13423          * initial scan.
13424          *
13425          * Broadcom tells me:
13426          *   ...the DMA engine is connected to the GRC block and a DMA
13427          *   reset may affect the GRC block in some unpredictable way...
13428          *   The behavior of resets to individual blocks has not been tested.
13429          *
13430          * Broadcom noted the GRC reset will also reset all sub-components.
13431          */
13432         if (to_device) {
13433                 test_desc.cqid_sqid = (13 << 8) | 2;
13434
13435                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13436                 udelay(40);
13437         } else {
13438                 test_desc.cqid_sqid = (16 << 8) | 7;
13439
13440                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13441                 udelay(40);
13442         }
13443         test_desc.flags = 0x00000005;
13444
13445         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13446                 u32 val;
13447
13448                 val = *(((u32 *)&test_desc) + i);
13449                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13450                                        sram_dma_descs + (i * sizeof(u32)));
13451                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13452         }
13453         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13454
13455         if (to_device) {
13456                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13457         } else {
13458                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13459         }
13460
13461         ret = -ENODEV;
13462         for (i = 0; i < 40; i++) {
13463                 u32 val;
13464
13465                 if (to_device)
13466                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13467                 else
13468                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13469                 if ((val & 0xffff) == sram_dma_descs) {
13470                         ret = 0;
13471                         break;
13472                 }
13473
13474                 udelay(100);
13475         }
13476
13477         return ret;
13478 }
13479
13480 #define TEST_BUFFER_SIZE        0x2000
13481
13482 static int __devinit tg3_test_dma(struct tg3 *tp)
13483 {
13484         dma_addr_t buf_dma;
13485         u32 *buf, saved_dma_rwctrl;
13486         int ret;
13487
13488         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13489         if (!buf) {
13490                 ret = -ENOMEM;
13491                 goto out_nofree;
13492         }
13493
13494         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13495                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13496
13497         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13498
13499         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13500                 /* DMA read watermark not used on PCIE */
13501                 tp->dma_rwctrl |= 0x00180000;
13502         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13503                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13504                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13505                         tp->dma_rwctrl |= 0x003f0000;
13506                 else
13507                         tp->dma_rwctrl |= 0x003f000f;
13508         } else {
13509                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13510                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13511                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13512                         u32 read_water = 0x7;
13513
13514                         /* If the 5704 is behind the EPB bridge, we can
13515                          * do the less restrictive ONE_DMA workaround for
13516                          * better performance.
13517                          */
13518                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13519                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13520                                 tp->dma_rwctrl |= 0x8000;
13521                         else if (ccval == 0x6 || ccval == 0x7)
13522                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13523
13524                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13525                                 read_water = 4;
13526                         /* Set bit 23 to enable PCIX hw bug fix */
13527                         tp->dma_rwctrl |=
13528                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13529                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13530                                 (1 << 23);
13531                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13532                         /* 5780 always in PCIX mode */
13533                         tp->dma_rwctrl |= 0x00144000;
13534                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13535                         /* 5714 always in PCIX mode */
13536                         tp->dma_rwctrl |= 0x00148000;
13537                 } else {
13538                         tp->dma_rwctrl |= 0x001b000f;
13539                 }
13540         }
13541
13542         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13543             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13544                 tp->dma_rwctrl &= 0xfffffff0;
13545
13546         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13547             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13548                 /* Remove this if it causes problems for some boards. */
13549                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13550
13551                 /* On 5700/5701 chips, we need to set this bit.
13552                  * Otherwise the chip will issue cacheline transactions
13553                  * to streamable DMA memory with not all the byte
13554                  * enables turned on.  This is an error on several
13555                  * RISC PCI controllers, in particular sparc64.
13556                  *
13557                  * On 5703/5704 chips, this bit has been reassigned
13558                  * a different meaning.  In particular, it is used
13559                  * on those chips to enable a PCI-X workaround.
13560                  */
13561                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13562         }
13563
13564         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13565
13566 #if 0
13567         /* Unneeded, already done by tg3_get_invariants.  */
13568         tg3_switch_clocks(tp);
13569 #endif
13570
13571         ret = 0;
13572         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13573             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13574                 goto out;
13575
13576         /* It is best to perform DMA test with maximum write burst size
13577          * to expose the 5700/5701 write DMA bug.
13578          */
13579         saved_dma_rwctrl = tp->dma_rwctrl;
13580         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13581         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13582
13583         while (1) {
13584                 u32 *p = buf, i;
13585
13586                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13587                         p[i] = i;
13588
13589                 /* Send the buffer to the chip. */
13590                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13591                 if (ret) {
13592                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13593                         break;
13594                 }
13595
13596 #if 0
13597                 /* validate data reached card RAM correctly. */
13598                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13599                         u32 val;
13600                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13601                         if (le32_to_cpu(val) != p[i]) {
13602                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13603                                 /* ret = -ENODEV here? */
13604                         }
13605                         p[i] = 0;
13606                 }
13607 #endif
13608                 /* Now read it back. */
13609                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13610                 if (ret) {
13611                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13612
13613                         break;
13614                 }
13615
13616                 /* Verify it. */
13617                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13618                         if (p[i] == i)
13619                                 continue;
13620
13621                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13622                             DMA_RWCTRL_WRITE_BNDRY_16) {
13623                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13624                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13625                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13626                                 break;
13627                         } else {
13628                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13629                                 ret = -ENODEV;
13630                                 goto out;
13631                         }
13632                 }
13633
13634                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13635                         /* Success. */
13636                         ret = 0;
13637                         break;
13638                 }
13639         }
13640         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13641             DMA_RWCTRL_WRITE_BNDRY_16) {
13642                 static struct pci_device_id dma_wait_state_chipsets[] = {
13643                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13644                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13645                         { },
13646                 };
13647
13648                 /* DMA test passed without adjusting DMA boundary,
13649                  * now look for chipsets that are known to expose the
13650                  * DMA bug without failing the test.
13651                  */
13652                 if (pci_dev_present(dma_wait_state_chipsets)) {
13653                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13654                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13655                 }
13656                 else
13657                         /* Safe to use the calculated DMA boundary. */
13658                         tp->dma_rwctrl = saved_dma_rwctrl;
13659
13660                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13661         }
13662
13663 out:
13664         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13665 out_nofree:
13666         return ret;
13667 }
13668
13669 static void __devinit tg3_init_link_config(struct tg3 *tp)
13670 {
13671         tp->link_config.advertising =
13672                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13673                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13674                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13675                  ADVERTISED_Autoneg | ADVERTISED_MII);
13676         tp->link_config.speed = SPEED_INVALID;
13677         tp->link_config.duplex = DUPLEX_INVALID;
13678         tp->link_config.autoneg = AUTONEG_ENABLE;
13679         tp->link_config.active_speed = SPEED_INVALID;
13680         tp->link_config.active_duplex = DUPLEX_INVALID;
13681         tp->link_config.phy_is_low_power = 0;
13682         tp->link_config.orig_speed = SPEED_INVALID;
13683         tp->link_config.orig_duplex = DUPLEX_INVALID;
13684         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13685 }
13686
13687 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13688 {
13689         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13690             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13691                 tp->bufmgr_config.mbuf_read_dma_low_water =
13692                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13693                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13694                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13695                 tp->bufmgr_config.mbuf_high_water =
13696                         DEFAULT_MB_HIGH_WATER_5705;
13697                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13698                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13699                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13700                         tp->bufmgr_config.mbuf_high_water =
13701                                 DEFAULT_MB_HIGH_WATER_5906;
13702                 }
13703
13704                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13705                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13706                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13707                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13708                 tp->bufmgr_config.mbuf_high_water_jumbo =
13709                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13710         } else {
13711                 tp->bufmgr_config.mbuf_read_dma_low_water =
13712                         DEFAULT_MB_RDMA_LOW_WATER;
13713                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13714                         DEFAULT_MB_MACRX_LOW_WATER;
13715                 tp->bufmgr_config.mbuf_high_water =
13716                         DEFAULT_MB_HIGH_WATER;
13717
13718                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13719                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13720                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13721                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13722                 tp->bufmgr_config.mbuf_high_water_jumbo =
13723                         DEFAULT_MB_HIGH_WATER_JUMBO;
13724         }
13725
13726         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13727         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13728 }
13729
13730 static char * __devinit tg3_phy_string(struct tg3 *tp)
13731 {
13732         switch (tp->phy_id & PHY_ID_MASK) {
13733         case PHY_ID_BCM5400:    return "5400";
13734         case PHY_ID_BCM5401:    return "5401";
13735         case PHY_ID_BCM5411:    return "5411";
13736         case PHY_ID_BCM5701:    return "5701";
13737         case PHY_ID_BCM5703:    return "5703";
13738         case PHY_ID_BCM5704:    return "5704";
13739         case PHY_ID_BCM5705:    return "5705";
13740         case PHY_ID_BCM5750:    return "5750";
13741         case PHY_ID_BCM5752:    return "5752";
13742         case PHY_ID_BCM5714:    return "5714";
13743         case PHY_ID_BCM5780:    return "5780";
13744         case PHY_ID_BCM5755:    return "5755";
13745         case PHY_ID_BCM5787:    return "5787";
13746         case PHY_ID_BCM5784:    return "5784";
13747         case PHY_ID_BCM5756:    return "5722/5756";
13748         case PHY_ID_BCM5906:    return "5906";
13749         case PHY_ID_BCM5761:    return "5761";
13750         case PHY_ID_BCM8002:    return "8002/serdes";
13751         case 0:                 return "serdes";
13752         default:                return "unknown";
13753         }
13754 }
13755
13756 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13757 {
13758         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13759                 strcpy(str, "PCI Express");
13760                 return str;
13761         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13762                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13763
13764                 strcpy(str, "PCIX:");
13765
13766                 if ((clock_ctrl == 7) ||
13767                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13768                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13769                         strcat(str, "133MHz");
13770                 else if (clock_ctrl == 0)
13771                         strcat(str, "33MHz");
13772                 else if (clock_ctrl == 2)
13773                         strcat(str, "50MHz");
13774                 else if (clock_ctrl == 4)
13775                         strcat(str, "66MHz");
13776                 else if (clock_ctrl == 6)
13777                         strcat(str, "100MHz");
13778         } else {
13779                 strcpy(str, "PCI:");
13780                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13781                         strcat(str, "66MHz");
13782                 else
13783                         strcat(str, "33MHz");
13784         }
13785         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13786                 strcat(str, ":32-bit");
13787         else
13788                 strcat(str, ":64-bit");
13789         return str;
13790 }
13791
13792 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13793 {
13794         struct pci_dev *peer;
13795         unsigned int func, devnr = tp->pdev->devfn & ~7;
13796
13797         for (func = 0; func < 8; func++) {
13798                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13799                 if (peer && peer != tp->pdev)
13800                         break;
13801                 pci_dev_put(peer);
13802         }
13803         /* 5704 can be configured in single-port mode, set peer to
13804          * tp->pdev in that case.
13805          */
13806         if (!peer) {
13807                 peer = tp->pdev;
13808                 return peer;
13809         }
13810
13811         /*
13812          * We don't need to keep the refcount elevated; there's no way
13813          * to remove one half of this device without removing the other
13814          */
13815         pci_dev_put(peer);
13816
13817         return peer;
13818 }
13819
13820 static void __devinit tg3_init_coal(struct tg3 *tp)
13821 {
13822         struct ethtool_coalesce *ec = &tp->coal;
13823
13824         memset(ec, 0, sizeof(*ec));
13825         ec->cmd = ETHTOOL_GCOALESCE;
13826         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13827         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13828         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13829         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13830         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13831         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13832         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13833         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13834         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13835
13836         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13837                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13838                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13839                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13840                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13841                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13842         }
13843
13844         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13845                 ec->rx_coalesce_usecs_irq = 0;
13846                 ec->tx_coalesce_usecs_irq = 0;
13847                 ec->stats_block_coalesce_usecs = 0;
13848         }
13849 }
13850
13851 static const struct net_device_ops tg3_netdev_ops = {
13852         .ndo_open               = tg3_open,
13853         .ndo_stop               = tg3_close,
13854         .ndo_start_xmit         = tg3_start_xmit,
13855         .ndo_get_stats          = tg3_get_stats,
13856         .ndo_validate_addr      = eth_validate_addr,
13857         .ndo_set_multicast_list = tg3_set_rx_mode,
13858         .ndo_set_mac_address    = tg3_set_mac_addr,
13859         .ndo_do_ioctl           = tg3_ioctl,
13860         .ndo_tx_timeout         = tg3_tx_timeout,
13861         .ndo_change_mtu         = tg3_change_mtu,
13862 #if TG3_VLAN_TAG_USED
13863         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13864 #endif
13865 #ifdef CONFIG_NET_POLL_CONTROLLER
13866         .ndo_poll_controller    = tg3_poll_controller,
13867 #endif
13868 };
13869
13870 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13871         .ndo_open               = tg3_open,
13872         .ndo_stop               = tg3_close,
13873         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13874         .ndo_get_stats          = tg3_get_stats,
13875         .ndo_validate_addr      = eth_validate_addr,
13876         .ndo_set_multicast_list = tg3_set_rx_mode,
13877         .ndo_set_mac_address    = tg3_set_mac_addr,
13878         .ndo_do_ioctl           = tg3_ioctl,
13879         .ndo_tx_timeout         = tg3_tx_timeout,
13880         .ndo_change_mtu         = tg3_change_mtu,
13881 #if TG3_VLAN_TAG_USED
13882         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13883 #endif
13884 #ifdef CONFIG_NET_POLL_CONTROLLER
13885         .ndo_poll_controller    = tg3_poll_controller,
13886 #endif
13887 };
13888
13889 static int __devinit tg3_init_one(struct pci_dev *pdev,
13890                                   const struct pci_device_id *ent)
13891 {
13892         static int tg3_version_printed = 0;
13893         struct net_device *dev;
13894         struct tg3 *tp;
13895         int i, err, pm_cap;
13896         u32 sndmbx, rcvmbx, intmbx;
13897         char str[40];
13898         u64 dma_mask, persist_dma_mask;
13899
13900         if (tg3_version_printed++ == 0)
13901                 printk(KERN_INFO "%s", version);
13902
13903         err = pci_enable_device(pdev);
13904         if (err) {
13905                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13906                        "aborting.\n");
13907                 return err;
13908         }
13909
13910         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13911         if (err) {
13912                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13913                        "aborting.\n");
13914                 goto err_out_disable_pdev;
13915         }
13916
13917         pci_set_master(pdev);
13918
13919         /* Find power-management capability. */
13920         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13921         if (pm_cap == 0) {
13922                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13923                        "aborting.\n");
13924                 err = -EIO;
13925                 goto err_out_free_res;
13926         }
13927
13928         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13929         if (!dev) {
13930                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13931                 err = -ENOMEM;
13932                 goto err_out_free_res;
13933         }
13934
13935         SET_NETDEV_DEV(dev, &pdev->dev);
13936
13937 #if TG3_VLAN_TAG_USED
13938         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13939 #endif
13940
13941         tp = netdev_priv(dev);
13942         tp->pdev = pdev;
13943         tp->dev = dev;
13944         tp->pm_cap = pm_cap;
13945         tp->rx_mode = TG3_DEF_RX_MODE;
13946         tp->tx_mode = TG3_DEF_TX_MODE;
13947
13948         if (tg3_debug > 0)
13949                 tp->msg_enable = tg3_debug;
13950         else
13951                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13952
13953         /* The word/byte swap controls here control register access byte
13954          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13955          * setting below.
13956          */
13957         tp->misc_host_ctrl =
13958                 MISC_HOST_CTRL_MASK_PCI_INT |
13959                 MISC_HOST_CTRL_WORD_SWAP |
13960                 MISC_HOST_CTRL_INDIR_ACCESS |
13961                 MISC_HOST_CTRL_PCISTATE_RW;
13962
13963         /* The NONFRM (non-frame) byte/word swap controls take effect
13964          * on descriptor entries, anything which isn't packet data.
13965          *
13966          * The StrongARM chips on the board (one for tx, one for rx)
13967          * are running in big-endian mode.
13968          */
13969         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13970                         GRC_MODE_WSWAP_NONFRM_DATA);
13971 #ifdef __BIG_ENDIAN
13972         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13973 #endif
13974         spin_lock_init(&tp->lock);
13975         spin_lock_init(&tp->indirect_lock);
13976         INIT_WORK(&tp->reset_task, tg3_reset_task);
13977
13978         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13979         if (!tp->regs) {
13980                 printk(KERN_ERR PFX "Cannot map device registers, "
13981                        "aborting.\n");
13982                 err = -ENOMEM;
13983                 goto err_out_free_dev;
13984         }
13985
13986         tg3_init_link_config(tp);
13987
13988         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13989         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13990
13991         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13992         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13993         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13994         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13995                 struct tg3_napi *tnapi = &tp->napi[i];
13996
13997                 tnapi->tp = tp;
13998                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13999
14000                 tnapi->int_mbox = intmbx;
14001                 if (i < 4)
14002                         intmbx += 0x8;
14003                 else
14004                         intmbx += 0x4;
14005
14006                 tnapi->consmbox = rcvmbx;
14007                 tnapi->prodmbox = sndmbx;
14008
14009                 if (i)
14010                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14011                 else
14012                         tnapi->coal_now = HOSTCC_MODE_NOW;
14013
14014                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14015                         break;
14016
14017                 /*
14018                  * If we support MSIX, we'll be using RSS.  If we're using
14019                  * RSS, the first vector only handles link interrupts and the
14020                  * remaining vectors handle rx and tx interrupts.  Reuse the
14021                  * mailbox values for the next iteration.  The values we setup
14022                  * above are still useful for the single vectored mode.
14023                  */
14024                 if (!i)
14025                         continue;
14026
14027                 rcvmbx += 0x8;
14028
14029                 if (sndmbx & 0x4)
14030                         sndmbx -= 0x4;
14031                 else
14032                         sndmbx += 0xc;
14033         }
14034
14035         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
14036         dev->ethtool_ops = &tg3_ethtool_ops;
14037         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14038         dev->irq = pdev->irq;
14039
14040         err = tg3_get_invariants(tp);
14041         if (err) {
14042                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14043                        "aborting.\n");
14044                 goto err_out_iounmap;
14045         }
14046
14047         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
14048                 dev->netdev_ops = &tg3_netdev_ops;
14049         else
14050                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14051
14052
14053         /* The EPB bridge inside 5714, 5715, and 5780 and any
14054          * device behind the EPB cannot support DMA addresses > 40-bit.
14055          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14056          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14057          * do DMA address check in tg3_start_xmit().
14058          */
14059         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14060                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14061         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14062                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14063 #ifdef CONFIG_HIGHMEM
14064                 dma_mask = DMA_BIT_MASK(64);
14065 #endif
14066         } else
14067                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14068
14069         /* Configure DMA attributes. */
14070         if (dma_mask > DMA_BIT_MASK(32)) {
14071                 err = pci_set_dma_mask(pdev, dma_mask);
14072                 if (!err) {
14073                         dev->features |= NETIF_F_HIGHDMA;
14074                         err = pci_set_consistent_dma_mask(pdev,
14075                                                           persist_dma_mask);
14076                         if (err < 0) {
14077                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14078                                        "DMA for consistent allocations\n");
14079                                 goto err_out_iounmap;
14080                         }
14081                 }
14082         }
14083         if (err || dma_mask == DMA_BIT_MASK(32)) {
14084                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14085                 if (err) {
14086                         printk(KERN_ERR PFX "No usable DMA configuration, "
14087                                "aborting.\n");
14088                         goto err_out_iounmap;
14089                 }
14090         }
14091
14092         tg3_init_bufmgr_config(tp);
14093
14094         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14095                 tp->fw_needed = FIRMWARE_TG3;
14096
14097         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14098                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14099         }
14100         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14101             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14102             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
14103             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14104             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14105                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14106         } else {
14107                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
14108                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14109                         tp->fw_needed = FIRMWARE_TG3TSO5;
14110                 else
14111                         tp->fw_needed = FIRMWARE_TG3TSO;
14112         }
14113
14114         /* TSO is on by default on chips that support hardware TSO.
14115          * Firmware TSO on older chips gives lower performance, so it
14116          * is off by default, but can be enabled using ethtool.
14117          */
14118         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14119                 if (dev->features & NETIF_F_IP_CSUM)
14120                         dev->features |= NETIF_F_TSO;
14121                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14122                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
14123                         dev->features |= NETIF_F_TSO6;
14124                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14125                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14126                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14127                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14128                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14129                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14130                         dev->features |= NETIF_F_TSO_ECN;
14131         }
14132
14133
14134         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14135             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14136             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14137                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14138                 tp->rx_pending = 63;
14139         }
14140
14141         err = tg3_get_device_address(tp);
14142         if (err) {
14143                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14144                        "aborting.\n");
14145                 goto err_out_fw;
14146         }
14147
14148         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14149                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14150                 if (!tp->aperegs) {
14151                         printk(KERN_ERR PFX "Cannot map APE registers, "
14152                                "aborting.\n");
14153                         err = -ENOMEM;
14154                         goto err_out_fw;
14155                 }
14156
14157                 tg3_ape_lock_init(tp);
14158
14159                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14160                         tg3_read_dash_ver(tp);
14161         }
14162
14163         /*
14164          * Reset chip in case UNDI or EFI driver did not shutdown
14165          * DMA self test will enable WDMAC and we'll see (spurious)
14166          * pending DMA on the PCI bus at that point.
14167          */
14168         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14169             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14170                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14171                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14172         }
14173
14174         err = tg3_test_dma(tp);
14175         if (err) {
14176                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14177                 goto err_out_apeunmap;
14178         }
14179
14180         /* flow control autonegotiation is default behavior */
14181         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14182         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14183
14184         tg3_init_coal(tp);
14185
14186         pci_set_drvdata(pdev, dev);
14187
14188         err = register_netdev(dev);
14189         if (err) {
14190                 printk(KERN_ERR PFX "Cannot register net device, "
14191                        "aborting.\n");
14192                 goto err_out_apeunmap;
14193         }
14194
14195         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14196                dev->name,
14197                tp->board_part_number,
14198                tp->pci_chip_rev_id,
14199                tg3_bus_string(tp, str),
14200                dev->dev_addr);
14201
14202         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14203                 struct phy_device *phydev;
14204                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14205                 printk(KERN_INFO
14206                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14207                        tp->dev->name, phydev->drv->name,
14208                        dev_name(&phydev->dev));
14209         } else
14210                 printk(KERN_INFO
14211                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14212                        tp->dev->name, tg3_phy_string(tp),
14213                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14214                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14215                          "10/100/1000Base-T")),
14216                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14217
14218         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14219                dev->name,
14220                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14221                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14222                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14223                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14224                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14225         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14226                dev->name, tp->dma_rwctrl,
14227                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14228                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14229
14230         return 0;
14231
14232 err_out_apeunmap:
14233         if (tp->aperegs) {
14234                 iounmap(tp->aperegs);
14235                 tp->aperegs = NULL;
14236         }
14237
14238 err_out_fw:
14239         if (tp->fw)
14240                 release_firmware(tp->fw);
14241
14242 err_out_iounmap:
14243         if (tp->regs) {
14244                 iounmap(tp->regs);
14245                 tp->regs = NULL;
14246         }
14247
14248 err_out_free_dev:
14249         free_netdev(dev);
14250
14251 err_out_free_res:
14252         pci_release_regions(pdev);
14253
14254 err_out_disable_pdev:
14255         pci_disable_device(pdev);
14256         pci_set_drvdata(pdev, NULL);
14257         return err;
14258 }
14259
14260 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14261 {
14262         struct net_device *dev = pci_get_drvdata(pdev);
14263
14264         if (dev) {
14265                 struct tg3 *tp = netdev_priv(dev);
14266
14267                 if (tp->fw)
14268                         release_firmware(tp->fw);
14269
14270                 flush_scheduled_work();
14271
14272                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14273                         tg3_phy_fini(tp);
14274                         tg3_mdio_fini(tp);
14275                 }
14276
14277                 unregister_netdev(dev);
14278                 if (tp->aperegs) {
14279                         iounmap(tp->aperegs);
14280                         tp->aperegs = NULL;
14281                 }
14282                 if (tp->regs) {
14283                         iounmap(tp->regs);
14284                         tp->regs = NULL;
14285                 }
14286                 free_netdev(dev);
14287                 pci_release_regions(pdev);
14288                 pci_disable_device(pdev);
14289                 pci_set_drvdata(pdev, NULL);
14290         }
14291 }
14292
14293 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14294 {
14295         struct net_device *dev = pci_get_drvdata(pdev);
14296         struct tg3 *tp = netdev_priv(dev);
14297         pci_power_t target_state;
14298         int err;
14299
14300         /* PCI register 4 needs to be saved whether netif_running() or not.
14301          * MSI address and data need to be saved if using MSI and
14302          * netif_running().
14303          */
14304         pci_save_state(pdev);
14305
14306         if (!netif_running(dev))
14307                 return 0;
14308
14309         flush_scheduled_work();
14310         tg3_phy_stop(tp);
14311         tg3_netif_stop(tp);
14312
14313         del_timer_sync(&tp->timer);
14314
14315         tg3_full_lock(tp, 1);
14316         tg3_disable_ints(tp);
14317         tg3_full_unlock(tp);
14318
14319         netif_device_detach(dev);
14320
14321         tg3_full_lock(tp, 0);
14322         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14323         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14324         tg3_full_unlock(tp);
14325
14326         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14327
14328         err = tg3_set_power_state(tp, target_state);
14329         if (err) {
14330                 int err2;
14331
14332                 tg3_full_lock(tp, 0);
14333
14334                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14335                 err2 = tg3_restart_hw(tp, 1);
14336                 if (err2)
14337                         goto out;
14338
14339                 tp->timer.expires = jiffies + tp->timer_offset;
14340                 add_timer(&tp->timer);
14341
14342                 netif_device_attach(dev);
14343                 tg3_netif_start(tp);
14344
14345 out:
14346                 tg3_full_unlock(tp);
14347
14348                 if (!err2)
14349                         tg3_phy_start(tp);
14350         }
14351
14352         return err;
14353 }
14354
14355 static int tg3_resume(struct pci_dev *pdev)
14356 {
14357         struct net_device *dev = pci_get_drvdata(pdev);
14358         struct tg3 *tp = netdev_priv(dev);
14359         int err;
14360
14361         pci_restore_state(tp->pdev);
14362
14363         if (!netif_running(dev))
14364                 return 0;
14365
14366         err = tg3_set_power_state(tp, PCI_D0);
14367         if (err)
14368                 return err;
14369
14370         netif_device_attach(dev);
14371
14372         tg3_full_lock(tp, 0);
14373
14374         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14375         err = tg3_restart_hw(tp, 1);
14376         if (err)
14377                 goto out;
14378
14379         tp->timer.expires = jiffies + tp->timer_offset;
14380         add_timer(&tp->timer);
14381
14382         tg3_netif_start(tp);
14383
14384 out:
14385         tg3_full_unlock(tp);
14386
14387         if (!err)
14388                 tg3_phy_start(tp);
14389
14390         return err;
14391 }
14392
14393 static struct pci_driver tg3_driver = {
14394         .name           = DRV_MODULE_NAME,
14395         .id_table       = tg3_pci_tbl,
14396         .probe          = tg3_init_one,
14397         .remove         = __devexit_p(tg3_remove_one),
14398         .suspend        = tg3_suspend,
14399         .resume         = tg3_resume
14400 };
14401
14402 static int __init tg3_init(void)
14403 {
14404         return pci_register_driver(&tg3_driver);
14405 }
14406
14407 static void __exit tg3_cleanup(void)
14408 {
14409         pci_unregister_driver(&tg3_driver);
14410 }
14411
14412 module_init(tg3_init);
14413 module_exit(tg3_cleanup);