drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.103"
  72 #define DRV_MODULE_RELDATE      "November 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         spin_lock_bh(&tp->lock);
 906
 907         if (tg3_readphy(tp, reg, &val))
 908                 val = -EIO;
 909
 910         spin_unlock_bh(&tp->lock);
 911
 912         return val;
 913 }
 914
 915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 ret = 0;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_writephy(tp, reg, val))
 923                 ret = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return ret;
 928 }
 929
 930 static int tg3_mdio_reset(struct mii_bus *bp)
 931 {
 932         return 0;
 933 }
 934
 935 static void tg3_mdio_config_5785(struct tg3 *tp)
 936 {
 937         u32 val;
 938         struct phy_device *phydev;
 939
 940         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 942         case TG3_PHY_ID_BCM50610:
 943         case TG3_PHY_ID_BCM50610M:
 944                 val = MAC_PHYCFG2_50610_LED_MODES;
 945                 break;
 946         case TG3_PHY_ID_BCMAC131:
 947                 val = MAC_PHYCFG2_AC131_LED_MODES;
 948                 break;
 949         case TG3_PHY_ID_RTL8211C:
 950                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 951                 break;
 952         case TG3_PHY_ID_RTL8201E:
 953                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 954                 break;
 955         default:
 956                 return;
 957         }
 958
 959         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 960                 tw32(MAC_PHYCFG2, val);
 961
 962                 val = tr32(MAC_PHYCFG1);
 963                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 964                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 965                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 966                 tw32(MAC_PHYCFG1, val);
 967
 968                 return;
 969         }
 970
 971         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 972                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 973                        MAC_PHYCFG2_FMODE_MASK_MASK |
 974                        MAC_PHYCFG2_GMODE_MASK_MASK |
 975                        MAC_PHYCFG2_ACT_MASK_MASK   |
 976                        MAC_PHYCFG2_QUAL_MASK_MASK |
 977                        MAC_PHYCFG2_INBAND_ENABLE;
 978
 979         tw32(MAC_PHYCFG2, val);
 980
 981         val = tr32(MAC_PHYCFG1);
 982         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 983                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 985                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 986                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 987                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 988                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 989         }
 990         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 991                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 992         tw32(MAC_PHYCFG1, val);
 993
 994         val = tr32(MAC_EXT_RGMII_MODE);
 995         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 996                  MAC_RGMII_MODE_RX_QUALITY |
 997                  MAC_RGMII_MODE_RX_ACTIVITY |
 998                  MAC_RGMII_MODE_RX_ENG_DET |
 999                  MAC_RGMII_MODE_TX_ENABLE |
1000                  MAC_RGMII_MODE_TX_LOWPWR |
1001                  MAC_RGMII_MODE_TX_RESET);
1002         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004                         val |= MAC_RGMII_MODE_RX_INT_B |
1005                                MAC_RGMII_MODE_RX_QUALITY |
1006                                MAC_RGMII_MODE_RX_ACTIVITY |
1007                                MAC_RGMII_MODE_RX_ENG_DET;
1008                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009                         val |= MAC_RGMII_MODE_TX_ENABLE |
1010                                MAC_RGMII_MODE_TX_LOWPWR |
1011                                MAC_RGMII_MODE_TX_RESET;
1012         }
1013         tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019         tw32_f(MAC_MI_MODE, tp->mi_mode);
1020         udelay(80);
1021
1022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023                 u32 funcnum, is_serdes;
1024
1025                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026                 if (funcnum)
1027                         tp->phy_addr = 2;
1028                 else
1029                         tp->phy_addr = 1;
1030
1031                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032                 if (is_serdes)
1033                         tp->phy_addr += 7;
1034         } else
1035                 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039                 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044         int i;
1045         u32 reg;
1046         struct phy_device *phydev;
1047
1048         tg3_mdio_start(tp);
1049
1050         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052                 return 0;
1053
1054         tp->mdio_bus = mdiobus_alloc();
1055         if (tp->mdio_bus == NULL)
1056                 return -ENOMEM;
1057
1058         tp->mdio_bus->name     = "tg3 mdio bus";
1059         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061         tp->mdio_bus->priv     = tp;
1062         tp->mdio_bus->parent   = &tp->pdev->dev;
1063         tp->mdio_bus->read     = &tg3_mdio_read;
1064         tp->mdio_bus->write    = &tg3_mdio_write;
1065         tp->mdio_bus->reset    = &tg3_mdio_reset;
1066         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1068
1069         for (i = 0; i < PHY_MAX_ADDR; i++)
1070                 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072         /* The bus registration will look for all the PHYs on the mdio bus.
1073          * Unfortunately, it does not ensure the PHY is powered up before
1074          * accessing the PHY ID registers.  A chip reset is the
1075          * quickest way to bring the device back to an operational state..
1076          */
1077         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078                 tg3_bmcr_reset(tp);
1079
1080         i = mdiobus_register(tp->mdio_bus);
1081         if (i) {
1082                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083                         tp->dev->name, i);
1084                 mdiobus_free(tp->mdio_bus);
1085                 return i;
1086         }
1087
1088         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090         if (!phydev || !phydev->drv) {
1091                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092                 mdiobus_unregister(tp->mdio_bus);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return -ENODEV;
1095         }
1096
1097         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098         case TG3_PHY_ID_BCM57780:
1099                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1101                 break;
1102         case TG3_PHY_ID_BCM50610:
1103         case TG3_PHY_ID_BCM50610M:
1104                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1105                                      PHY_BRCM_RX_REFCLK_UNUSED |
1106                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1107                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1108                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1109                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1110                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1111                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1112                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1114                 /* fallthru */
1115         case TG3_PHY_ID_RTL8211C:
1116                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1117                 break;
1118         case TG3_PHY_ID_RTL8201E:
1119         case TG3_PHY_ID_BCMAC131:
1120                 phydev->interface = PHY_INTERFACE_MODE_MII;
1121                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1123                 break;
1124         }
1125
1126         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1127
1128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1129                 tg3_mdio_config_5785(tp);
1130
1131         return 0;
1132 }
1133
1134 static void tg3_mdio_fini(struct tg3 *tp)
1135 {
1136         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1137                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1138                 mdiobus_unregister(tp->mdio_bus);
1139                 mdiobus_free(tp->mdio_bus);
1140         }
1141 }
1142
1143 /* tp->lock is held. */
1144 static inline void tg3_generate_fw_event(struct tg3 *tp)
1145 {
1146         u32 val;
1147
1148         val = tr32(GRC_RX_CPU_EVENT);
1149         val |= GRC_RX_CPU_DRIVER_EVENT;
1150         tw32_f(GRC_RX_CPU_EVENT, val);
1151
1152         tp->last_event_jiffies = jiffies;
1153 }
1154
1155 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1156
1157 /* tp->lock is held. */
1158 static void tg3_wait_for_event_ack(struct tg3 *tp)
1159 {
1160         int i;
1161         unsigned int delay_cnt;
1162         long time_remain;
1163
1164         /* If enough time has passed, no wait is necessary. */
1165         time_remain = (long)(tp->last_event_jiffies + 1 +
1166                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1167                       (long)jiffies;
1168         if (time_remain < 0)
1169                 return;
1170
1171         /* Check if we can shorten the wait time. */
1172         delay_cnt = jiffies_to_usecs(time_remain);
1173         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1174                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1175         delay_cnt = (delay_cnt >> 3) + 1;
1176
1177         for (i = 0; i < delay_cnt; i++) {
1178                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1179                         break;
1180                 udelay(8);
1181         }
1182 }
1183
1184 /* tp->lock is held. */
1185 static void tg3_ump_link_report(struct tg3 *tp)
1186 {
1187         u32 reg;
1188         u32 val;
1189
1190         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1191             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1192                 return;
1193
1194         tg3_wait_for_event_ack(tp);
1195
1196         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1197
1198         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1199
1200         val = 0;
1201         if (!tg3_readphy(tp, MII_BMCR, &reg))
1202                 val = reg << 16;
1203         if (!tg3_readphy(tp, MII_BMSR, &reg))
1204                 val |= (reg & 0xffff);
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1206
1207         val = 0;
1208         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1209                 val = reg << 16;
1210         if (!tg3_readphy(tp, MII_LPA, &reg))
1211                 val |= (reg & 0xffff);
1212         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1213
1214         val = 0;
1215         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1216                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1217                         val = reg << 16;
1218                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1219                         val |= (reg & 0xffff);
1220         }
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1222
1223         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1224                 val = reg << 16;
1225         else
1226                 val = 0;
1227         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1228
1229         tg3_generate_fw_event(tp);
1230 }
1231
1232 static void tg3_link_report(struct tg3 *tp)
1233 {
1234         if (!netif_carrier_ok(tp->dev)) {
1235                 if (netif_msg_link(tp))
1236                         printk(KERN_INFO PFX "%s: Link is down.\n",
1237                                tp->dev->name);
1238                 tg3_ump_link_report(tp);
1239         } else if (netif_msg_link(tp)) {
1240                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1241                        tp->dev->name,
1242                        (tp->link_config.active_speed == SPEED_1000 ?
1243                         1000 :
1244                         (tp->link_config.active_speed == SPEED_100 ?
1245                          100 : 10)),
1246                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1247                         "full" : "half"));
1248
1249                 printk(KERN_INFO PFX
1250                        "%s: Flow control is %s for TX and %s for RX.\n",
1251                        tp->dev->name,
1252                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1253                        "on" : "off",
1254                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1255                        "on" : "off");
1256                 tg3_ump_link_report(tp);
1257         }
1258 }
1259
1260 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1261 {
1262         u16 miireg;
1263
1264         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1265                 miireg = ADVERTISE_PAUSE_CAP;
1266         else if (flow_ctrl & FLOW_CTRL_TX)
1267                 miireg = ADVERTISE_PAUSE_ASYM;
1268         else if (flow_ctrl & FLOW_CTRL_RX)
1269                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1270         else
1271                 miireg = 0;
1272
1273         return miireg;
1274 }
1275
1276 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1277 {
1278         u16 miireg;
1279
1280         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1281                 miireg = ADVERTISE_1000XPAUSE;
1282         else if (flow_ctrl & FLOW_CTRL_TX)
1283                 miireg = ADVERTISE_1000XPSE_ASYM;
1284         else if (flow_ctrl & FLOW_CTRL_RX)
1285                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1286         else
1287                 miireg = 0;
1288
1289         return miireg;
1290 }
1291
1292 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1293 {
1294         u8 cap = 0;
1295
1296         if (lcladv & ADVERTISE_1000XPAUSE) {
1297                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1298                         if (rmtadv & LPA_1000XPAUSE)
1299                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1300                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1301                                 cap = FLOW_CTRL_RX;
1302                 } else {
1303                         if (rmtadv & LPA_1000XPAUSE)
1304                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1305                 }
1306         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1308                         cap = FLOW_CTRL_TX;
1309         }
1310
1311         return cap;
1312 }
1313
1314 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1315 {
1316         u8 autoneg;
1317         u8 flowctrl = 0;
1318         u32 old_rx_mode = tp->rx_mode;
1319         u32 old_tx_mode = tp->tx_mode;
1320
1321         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1322                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1323         else
1324                 autoneg = tp->link_config.autoneg;
1325
1326         if (autoneg == AUTONEG_ENABLE &&
1327             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1328                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1329                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1330                 else
1331                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1332         } else
1333                 flowctrl = tp->link_config.flowctrl;
1334
1335         tp->link_config.active_flowctrl = flowctrl;
1336
1337         if (flowctrl & FLOW_CTRL_RX)
1338                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1339         else
1340                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1341
1342         if (old_rx_mode != tp->rx_mode)
1343                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1344
1345         if (flowctrl & FLOW_CTRL_TX)
1346                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1347         else
1348                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1349
1350         if (old_tx_mode != tp->tx_mode)
1351                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1352 }
1353
1354 static void tg3_adjust_link(struct net_device *dev)
1355 {
1356         u8 oldflowctrl, linkmesg = 0;
1357         u32 mac_mode, lcl_adv, rmt_adv;
1358         struct tg3 *tp = netdev_priv(dev);
1359         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1360
1361         spin_lock_bh(&tp->lock);
1362
1363         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1364                                     MAC_MODE_HALF_DUPLEX);
1365
1366         oldflowctrl = tp->link_config.active_flowctrl;
1367
1368         if (phydev->link) {
1369                 lcl_adv = 0;
1370                 rmt_adv = 0;
1371
1372                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1373                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1374                 else if (phydev->speed == SPEED_1000 ||
1375                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1376                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1377                 else
1378                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1379
1380                 if (phydev->duplex == DUPLEX_HALF)
1381                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1382                 else {
1383                         lcl_adv = tg3_advert_flowctrl_1000T(
1384                                   tp->link_config.flowctrl);
1385
1386                         if (phydev->pause)
1387                                 rmt_adv = LPA_PAUSE_CAP;
1388                         if (phydev->asym_pause)
1389                                 rmt_adv |= LPA_PAUSE_ASYM;
1390                 }
1391
1392                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1393         } else
1394                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1395
1396         if (mac_mode != tp->mac_mode) {
1397                 tp->mac_mode = mac_mode;
1398                 tw32_f(MAC_MODE, tp->mac_mode);
1399                 udelay(40);
1400         }
1401
1402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1403                 if (phydev->speed == SPEED_10)
1404                         tw32(MAC_MI_STAT,
1405                              MAC_MI_STAT_10MBPS_MODE |
1406                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1407                 else
1408                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1409         }
1410
1411         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1412                 tw32(MAC_TX_LENGTHS,
1413                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414                       (6 << TX_LENGTHS_IPG_SHIFT) |
1415                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416         else
1417                 tw32(MAC_TX_LENGTHS,
1418                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419                       (6 << TX_LENGTHS_IPG_SHIFT) |
1420                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421
1422         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1423             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1424             phydev->speed != tp->link_config.active_speed ||
1425             phydev->duplex != tp->link_config.active_duplex ||
1426             oldflowctrl != tp->link_config.active_flowctrl)
1427             linkmesg = 1;
1428
1429         tp->link_config.active_speed = phydev->speed;
1430         tp->link_config.active_duplex = phydev->duplex;
1431
1432         spin_unlock_bh(&tp->lock);
1433
1434         if (linkmesg)
1435                 tg3_link_report(tp);
1436 }
1437
1438 static int tg3_phy_init(struct tg3 *tp)
1439 {
1440         struct phy_device *phydev;
1441
1442         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1443                 return 0;
1444
1445         /* Bring the PHY back to a known state. */
1446         tg3_bmcr_reset(tp);
1447
1448         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1449
1450         /* Attach the MAC to the PHY. */
1451         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1452                              phydev->dev_flags, phydev->interface);
1453         if (IS_ERR(phydev)) {
1454                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1455                 return PTR_ERR(phydev);
1456         }
1457
1458         /* Mask with MAC supported features. */
1459         switch (phydev->interface) {
1460         case PHY_INTERFACE_MODE_GMII:
1461         case PHY_INTERFACE_MODE_RGMII:
1462                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1463                         phydev->supported &= (PHY_GBIT_FEATURES |
1464                                               SUPPORTED_Pause |
1465                                               SUPPORTED_Asym_Pause);
1466                         break;
1467                 }
1468                 /* fallthru */
1469         case PHY_INTERFACE_MODE_MII:
1470                 phydev->supported &= (PHY_BASIC_FEATURES |
1471                                       SUPPORTED_Pause |
1472                                       SUPPORTED_Asym_Pause);
1473                 break;
1474         default:
1475                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1476                 return -EINVAL;
1477         }
1478
1479         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1480
1481         phydev->advertising = phydev->supported;
1482
1483         return 0;
1484 }
1485
1486 static void tg3_phy_start(struct tg3 *tp)
1487 {
1488         struct phy_device *phydev;
1489
1490         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1491                 return;
1492
1493         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1494
1495         if (tp->link_config.phy_is_low_power) {
1496                 tp->link_config.phy_is_low_power = 0;
1497                 phydev->speed = tp->link_config.orig_speed;
1498                 phydev->duplex = tp->link_config.orig_duplex;
1499                 phydev->autoneg = tp->link_config.orig_autoneg;
1500                 phydev->advertising = tp->link_config.orig_advertising;
1501         }
1502
1503         phy_start(phydev);
1504
1505         phy_start_aneg(phydev);
1506 }
1507
1508 static void tg3_phy_stop(struct tg3 *tp)
1509 {
1510         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511                 return;
1512
1513         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1514 }
1515
1516 static void tg3_phy_fini(struct tg3 *tp)
1517 {
1518         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1519                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1520                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1521         }
1522 }
1523
1524 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1525 {
1526         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1527         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1528 }
1529
1530 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1531 {
1532         u32 phytest;
1533
1534         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1535                 u32 phy;
1536
1537                 tg3_writephy(tp, MII_TG3_FET_TEST,
1538                              phytest | MII_TG3_FET_SHADOW_EN);
1539                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1540                         if (enable)
1541                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1542                         else
1543                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1544                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1545                 }
1546                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1547         }
1548 }
1549
1550 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552         u32 reg;
1553
1554         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1555                 return;
1556
1557         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1558                 tg3_phy_fet_toggle_apd(tp, enable);
1559                 return;
1560         }
1561
1562         reg = MII_TG3_MISC_SHDW_WREN |
1563               MII_TG3_MISC_SHDW_SCR5_SEL |
1564               MII_TG3_MISC_SHDW_SCR5_LPED |
1565               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1566               MII_TG3_MISC_SHDW_SCR5_SDTL |
1567               MII_TG3_MISC_SHDW_SCR5_C125OE;
1568         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1569                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1570
1571         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1572
1573
1574         reg = MII_TG3_MISC_SHDW_WREN |
1575               MII_TG3_MISC_SHDW_APD_SEL |
1576               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1577         if (enable)
1578                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1579
1580         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581 }
1582
1583 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1584 {
1585         u32 phy;
1586
1587         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1588             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1589                 return;
1590
1591         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1592                 u32 ephy;
1593
1594                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1595                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1596
1597                         tg3_writephy(tp, MII_TG3_FET_TEST,
1598                                      ephy | MII_TG3_FET_SHADOW_EN);
1599                         if (!tg3_readphy(tp, reg, &phy)) {
1600                                 if (enable)
1601                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1602                                 else
1603                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1604                                 tg3_writephy(tp, reg, phy);
1605                         }
1606                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1607                 }
1608         } else {
1609                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1610                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1611                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1612                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1613                         if (enable)
1614                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1615                         else
1616                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1617                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1618                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619                 }
1620         }
1621 }
1622
1623 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1624 {
1625         u32 val;
1626
1627         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1628                 return;
1629
1630         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1631             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1632                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1633                              (val | (1 << 15) | (1 << 4)));
1634 }
1635
1636 static void tg3_phy_apply_otp(struct tg3 *tp)
1637 {
1638         u32 otp, phy;
1639
1640         if (!tp->phy_otp)
1641                 return;
1642
1643         otp = tp->phy_otp;
1644
1645         /* Enable SM_DSP clock and tx 6dB coding. */
1646         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1647               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1648               MII_TG3_AUXCTL_ACTL_TX_6DB;
1649         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1650
1651         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1652         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1653         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1654
1655         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1656               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1657         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1658
1659         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1660         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1661         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1662
1663         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1664         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1665
1666         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1667         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1668
1669         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1670               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1671         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1672
1673         /* Turn off SM_DSP clock. */
1674         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1675               MII_TG3_AUXCTL_ACTL_TX_6DB;
1676         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1677 }
1678
1679 static int tg3_wait_macro_done(struct tg3 *tp)
1680 {
1681         int limit = 100;
1682
1683         while (limit--) {
1684                 u32 tmp32;
1685
1686                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1687                         if ((tmp32 & 0x1000) == 0)
1688                                 break;
1689                 }
1690         }
1691         if (limit < 0)
1692                 return -EBUSY;
1693
1694         return 0;
1695 }
1696
1697 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1698 {
1699         static const u32 test_pat[4][6] = {
1700         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1704         };
1705         int chan;
1706
1707         for (chan = 0; chan < 4; chan++) {
1708                 int i;
1709
1710                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1711                              (chan * 0x2000) | 0x0200);
1712                 tg3_writephy(tp, 0x16, 0x0002);
1713
1714                 for (i = 0; i < 6; i++)
1715                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1716                                      test_pat[chan][i]);
1717
1718                 tg3_writephy(tp, 0x16, 0x0202);
1719                 if (tg3_wait_macro_done(tp)) {
1720                         *resetp = 1;
1721                         return -EBUSY;
1722                 }
1723
1724                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1725                              (chan * 0x2000) | 0x0200);
1726                 tg3_writephy(tp, 0x16, 0x0082);
1727                 if (tg3_wait_macro_done(tp)) {
1728                         *resetp = 1;
1729                         return -EBUSY;
1730                 }
1731
1732                 tg3_writephy(tp, 0x16, 0x0802);
1733                 if (tg3_wait_macro_done(tp)) {
1734                         *resetp = 1;
1735                         return -EBUSY;
1736                 }
1737
1738                 for (i = 0; i < 6; i += 2) {
1739                         u32 low, high;
1740
1741                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1742                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1743                             tg3_wait_macro_done(tp)) {
1744                                 *resetp = 1;
1745                                 return -EBUSY;
1746                         }
1747                         low &= 0x7fff;
1748                         high &= 0x000f;
1749                         if (low != test_pat[chan][i] ||
1750                             high != test_pat[chan][i+1]) {
1751                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1752                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1753                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1754
1755                                 return -EBUSY;
1756                         }
1757                 }
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1764 {
1765         int chan;
1766
1767         for (chan = 0; chan < 4; chan++) {
1768                 int i;
1769
1770                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1771                              (chan * 0x2000) | 0x0200);
1772                 tg3_writephy(tp, 0x16, 0x0002);
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1775                 tg3_writephy(tp, 0x16, 0x0202);
1776                 if (tg3_wait_macro_done(tp))
1777                         return -EBUSY;
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1784 {
1785         u32 reg32, phy9_orig;
1786         int retries, do_phy_reset, err;
1787
1788         retries = 10;
1789         do_phy_reset = 1;
1790         do {
1791                 if (do_phy_reset) {
1792                         err = tg3_bmcr_reset(tp);
1793                         if (err)
1794                                 return err;
1795                         do_phy_reset = 0;
1796                 }
1797
1798                 /* Disable transmitter and interrupt.  */
1799                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1800                         continue;
1801
1802                 reg32 |= 0x3000;
1803                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1804
1805                 /* Set full-duplex, 1000 mbps.  */
1806                 tg3_writephy(tp, MII_BMCR,
1807                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1808
1809                 /* Set to master mode.  */
1810                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1811                         continue;
1812
1813                 tg3_writephy(tp, MII_TG3_CTRL,
1814                              (MII_TG3_CTRL_AS_MASTER |
1815                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1816
1817                 /* Enable SM_DSP_CLOCK and 6dB.  */
1818                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1819
1820                 /* Block the PHY control access.  */
1821                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1822                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1823
1824                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1825                 if (!err)
1826                         break;
1827         } while (--retries);
1828
1829         err = tg3_phy_reset_chanpat(tp);
1830         if (err)
1831                 return err;
1832
1833         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1834         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1835
1836         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1837         tg3_writephy(tp, 0x16, 0x0000);
1838
1839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1840             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1841                 /* Set Extended packet length bit for jumbo frames */
1842                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1843         }
1844         else {
1845                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1846         }
1847
1848         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1849
1850         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1851                 reg32 &= ~0x3000;
1852                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1853         } else if (!err)
1854                 err = -EBUSY;
1855
1856         return err;
1857 }
1858
1859 /* This will reset the tigon3 PHY if there is no valid
1860  * link unless the FORCE argument is non-zero.
1861  */
1862 static int tg3_phy_reset(struct tg3 *tp)
1863 {
1864         u32 cpmuctrl;
1865         u32 phy_status;
1866         int err;
1867
1868         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1869                 u32 val;
1870
1871                 val = tr32(GRC_MISC_CFG);
1872                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1873                 udelay(40);
1874         }
1875         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1876         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1877         if (err != 0)
1878                 return -EBUSY;
1879
1880         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1881                 netif_carrier_off(tp->dev);
1882                 tg3_link_report(tp);
1883         }
1884
1885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1886             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1887             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1888                 err = tg3_phy_reset_5703_4_5(tp);
1889                 if (err)
1890                         return err;
1891                 goto out;
1892         }
1893
1894         cpmuctrl = 0;
1895         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1896             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1897                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1898                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1899                         tw32(TG3_CPMU_CTRL,
1900                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1901         }
1902
1903         err = tg3_bmcr_reset(tp);
1904         if (err)
1905                 return err;
1906
1907         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1908                 u32 phy;
1909
1910                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1911                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1912
1913                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1914         }
1915
1916         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1917             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1918                 u32 val;
1919
1920                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1921                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1922                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1923                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1924                         udelay(40);
1925                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1926                 }
1927         }
1928
1929         tg3_phy_apply_otp(tp);
1930
1931         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1932                 tg3_phy_toggle_apd(tp, true);
1933         else
1934                 tg3_phy_toggle_apd(tp, false);
1935
1936 out:
1937         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1941                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1942                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1943                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1944         }
1945         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1946                 tg3_writephy(tp, 0x1c, 0x8d68);
1947                 tg3_writephy(tp, 0x1c, 0x8d68);
1948         }
1949         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1950                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1951                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1952                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1953                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1954                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1955                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1956                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1957                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958         }
1959         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1962                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1963                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1964                         tg3_writephy(tp, MII_TG3_TEST1,
1965                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1966                 } else
1967                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969         }
1970         /* Set Extended packet length bit (bit 14) on all chips that */
1971         /* support jumbo frames */
1972         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1973                 /* Cannot do read-modify-write on 5401 */
1974                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1975         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1976                 u32 phy_reg;
1977
1978                 /* Set bit 14 with read-modify-write to preserve other bits */
1979                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1980                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1981                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1982         }
1983
1984         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985          * jumbo frames transmission.
1986          */
1987         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1988                 u32 phy_reg;
1989
1990                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1991                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1992                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1993         }
1994
1995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1996                 /* adjust output voltage */
1997                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1998         }
1999
2000         tg3_phy_toggle_automdix(tp, 1);
2001         tg3_phy_set_wirespeed(tp);
2002         return 0;
2003 }
2004
2005 static void tg3_frob_aux_power(struct tg3 *tp)
2006 {
2007         struct tg3 *tp_peer = tp;
2008
2009         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2010                 return;
2011
2012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2015                 struct net_device *dev_peer;
2016
2017                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2018                 /* remove_one() may have been run on the peer. */
2019                 if (!dev_peer)
2020                         tp_peer = tp;
2021                 else
2022                         tp_peer = netdev_priv(dev_peer);
2023         }
2024
2025         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2026             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2027             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2028             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2029                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2030                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2031                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032                                     (GRC_LCLCTRL_GPIO_OE0 |
2033                                      GRC_LCLCTRL_GPIO_OE1 |
2034                                      GRC_LCLCTRL_GPIO_OE2 |
2035                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2036                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2037                                     100);
2038                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2039                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2040                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2042                                              GRC_LCLCTRL_GPIO_OE1 |
2043                                              GRC_LCLCTRL_GPIO_OE2 |
2044                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2045                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2046                                              tp->grc_local_ctrl;
2047                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2050                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051
2052                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2053                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2054                 } else {
2055                         u32 no_gpio2;
2056                         u32 grc_local_ctrl = 0;
2057
2058                         if (tp_peer != tp &&
2059                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060                                 return;
2061
2062                         /* Workaround to prevent overdrawing Amps. */
2063                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2064                             ASIC_REV_5714) {
2065                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2066                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                             grc_local_ctrl, 100);
2068                         }
2069
2070                         /* On 5753 and variants, GPIO2 cannot be used. */
2071                         no_gpio2 = tp->nic_sram_data_cfg &
2072                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2073
2074                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2075                                          GRC_LCLCTRL_GPIO_OE1 |
2076                                          GRC_LCLCTRL_GPIO_OE2 |
2077                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2078                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2079                         if (no_gpio2) {
2080                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2081                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2082                         }
2083                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084                                                     grc_local_ctrl, 100);
2085
2086                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2087
2088                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089                                                     grc_local_ctrl, 100);
2090
2091                         if (!no_gpio2) {
2092                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2093                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                             grc_local_ctrl, 100);
2095                         }
2096                 }
2097         } else {
2098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2099                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2100                         if (tp_peer != tp &&
2101                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102                                 return;
2103
2104                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105                                     (GRC_LCLCTRL_GPIO_OE1 |
2106                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2107
2108                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109                                     GRC_LCLCTRL_GPIO_OE1, 100);
2110
2111                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112                                     (GRC_LCLCTRL_GPIO_OE1 |
2113                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2114                 }
2115         }
2116 }
2117
2118 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2119 {
2120         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2121                 return 1;
2122         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2123                 if (speed != SPEED_10)
2124                         return 1;
2125         } else if (speed == SPEED_10)
2126                 return 1;
2127
2128         return 0;
2129 }
2130
2131 static int tg3_setup_phy(struct tg3 *, int);
2132
2133 #define RESET_KIND_SHUTDOWN     0
2134 #define RESET_KIND_INIT         1
2135 #define RESET_KIND_SUSPEND      2
2136
2137 static void tg3_write_sig_post_reset(struct tg3 *, int);
2138 static int tg3_halt_cpu(struct tg3 *, u32);
2139
2140 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2141 {
2142         u32 val;
2143
2144         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2146                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2147                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2148
2149                         sg_dig_ctrl |=
2150                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2151                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2152                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2153                 }
2154                 return;
2155         }
2156
2157         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2158                 tg3_bmcr_reset(tp);
2159                 val = tr32(GRC_MISC_CFG);
2160                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2161                 udelay(40);
2162                 return;
2163         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2164                 u32 phytest;
2165                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2166                         u32 phy;
2167
2168                         tg3_writephy(tp, MII_ADVERTISE, 0);
2169                         tg3_writephy(tp, MII_BMCR,
2170                                      BMCR_ANENABLE | BMCR_ANRESTART);
2171
2172                         tg3_writephy(tp, MII_TG3_FET_TEST,
2173                                      phytest | MII_TG3_FET_SHADOW_EN);
2174                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2175                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2176                                 tg3_writephy(tp,
2177                                              MII_TG3_FET_SHDW_AUXMODE4,
2178                                              phy);
2179                         }
2180                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2181                 }
2182                 return;
2183         } else if (do_low_power) {
2184                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2185                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2186
2187                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2188                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2189                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2190                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2191                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2192         }
2193
2194         /* The PHY should not be powered down on some chips because
2195          * of bugs.
2196          */
2197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2198             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2199             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2200              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2201                 return;
2202
2203         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2204             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2205                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2206                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2207                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2208                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2209         }
2210
2211         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2212 }
2213
2214 /* tp->lock is held. */
2215 static int tg3_nvram_lock(struct tg3 *tp)
2216 {
2217         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2218                 int i;
2219
2220                 if (tp->nvram_lock_cnt == 0) {
2221                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2222                         for (i = 0; i < 8000; i++) {
2223                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2224                                         break;
2225                                 udelay(20);
2226                         }
2227                         if (i == 8000) {
2228                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2229                                 return -ENODEV;
2230                         }
2231                 }
2232                 tp->nvram_lock_cnt++;
2233         }
2234         return 0;
2235 }
2236
2237 /* tp->lock is held. */
2238 static void tg3_nvram_unlock(struct tg3 *tp)
2239 {
2240         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241                 if (tp->nvram_lock_cnt > 0)
2242                         tp->nvram_lock_cnt--;
2243                 if (tp->nvram_lock_cnt == 0)
2244                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2245         }
2246 }
2247
2248 /* tp->lock is held. */
2249 static void tg3_enable_nvram_access(struct tg3 *tp)
2250 {
2251         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2252             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2253                 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2256         }
2257 }
2258
2259 /* tp->lock is held. */
2260 static void tg3_disable_nvram_access(struct tg3 *tp)
2261 {
2262         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2263             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2264                 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2267         }
2268 }
2269
2270 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2271                                         u32 offset, u32 *val)
2272 {
2273         u32 tmp;
2274         int i;
2275
2276         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2277                 return -EINVAL;
2278
2279         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2280                                         EEPROM_ADDR_DEVID_MASK |
2281                                         EEPROM_ADDR_READ);
2282         tw32(GRC_EEPROM_ADDR,
2283              tmp |
2284              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2285              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2286               EEPROM_ADDR_ADDR_MASK) |
2287              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2288
2289         for (i = 0; i < 1000; i++) {
2290                 tmp = tr32(GRC_EEPROM_ADDR);
2291
2292                 if (tmp & EEPROM_ADDR_COMPLETE)
2293                         break;
2294                 msleep(1);
2295         }
2296         if (!(tmp & EEPROM_ADDR_COMPLETE))
2297                 return -EBUSY;
2298
2299         tmp = tr32(GRC_EEPROM_DATA);
2300
2301         /*
2302          * The data will always be opposite the native endian
2303          * format.  Perform a blind byteswap to compensate.
2304          */
2305         *val = swab32(tmp);
2306
2307         return 0;
2308 }
2309
2310 #define NVRAM_CMD_TIMEOUT 10000
2311
2312 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2313 {
2314         int i;
2315
2316         tw32(NVRAM_CMD, nvram_cmd);
2317         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2318                 udelay(10);
2319                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2320                         udelay(10);
2321                         break;
2322                 }
2323         }
2324
2325         if (i == NVRAM_CMD_TIMEOUT)
2326                 return -EBUSY;
2327
2328         return 0;
2329 }
2330
2331 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2332 {
2333         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2334             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2335             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2336            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2337             (tp->nvram_jedecnum == JEDEC_ATMEL))
2338
2339                 addr = ((addr / tp->nvram_pagesize) <<
2340                         ATMEL_AT45DB0X1B_PAGE_POS) +
2341                        (addr % tp->nvram_pagesize);
2342
2343         return addr;
2344 }
2345
2346 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2347 {
2348         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352             (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2355                         tp->nvram_pagesize) +
2356                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2357
2358         return addr;
2359 }
2360
2361 /* NOTE: Data read in from NVRAM is byteswapped according to
2362  * the byteswapping settings for all other register accesses.
2363  * tg3 devices are BE devices, so on a BE machine, the data
2364  * returned will be exactly as it is seen in NVRAM.  On a LE
2365  * machine, the 32-bit value will be byteswapped.
2366  */
2367 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2368 {
2369         int ret;
2370
2371         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2372                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2373
2374         offset = tg3_nvram_phys_addr(tp, offset);
2375
2376         if (offset > NVRAM_ADDR_MSK)
2377                 return -EINVAL;
2378
2379         ret = tg3_nvram_lock(tp);
2380         if (ret)
2381                 return ret;
2382
2383         tg3_enable_nvram_access(tp);
2384
2385         tw32(NVRAM_ADDR, offset);
2386         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2387                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2388
2389         if (ret == 0)
2390                 *val = tr32(NVRAM_RDDATA);
2391
2392         tg3_disable_nvram_access(tp);
2393
2394         tg3_nvram_unlock(tp);
2395
2396         return ret;
2397 }
2398
2399 /* Ensures NVRAM data is in bytestream format. */
2400 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2401 {
2402         u32 v;
2403         int res = tg3_nvram_read(tp, offset, &v);
2404         if (!res)
2405                 *val = cpu_to_be32(v);
2406         return res;
2407 }
2408
2409 /* tp->lock is held. */
2410 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2411 {
2412         u32 addr_high, addr_low;
2413         int i;
2414
2415         addr_high = ((tp->dev->dev_addr[0] << 8) |
2416                      tp->dev->dev_addr[1]);
2417         addr_low = ((tp->dev->dev_addr[2] << 24) |
2418                     (tp->dev->dev_addr[3] << 16) |
2419                     (tp->dev->dev_addr[4] <<  8) |
2420                     (tp->dev->dev_addr[5] <<  0));
2421         for (i = 0; i < 4; i++) {
2422                 if (i == 1 && skip_mac_1)
2423                         continue;
2424                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2425                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2426         }
2427
2428         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2429             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2430                 for (i = 0; i < 12; i++) {
2431                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2432                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2433                 }
2434         }
2435
2436         addr_high = (tp->dev->dev_addr[0] +
2437                      tp->dev->dev_addr[1] +
2438                      tp->dev->dev_addr[2] +
2439                      tp->dev->dev_addr[3] +
2440                      tp->dev->dev_addr[4] +
2441                      tp->dev->dev_addr[5]) &
2442                 TX_BACKOFF_SEED_MASK;
2443         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2444 }
2445
2446 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2447 {
2448         u32 misc_host_ctrl;
2449         bool device_should_wake, do_low_power;
2450
2451         /* Make sure register accesses (indirect or otherwise)
2452          * will function correctly.
2453          */
2454         pci_write_config_dword(tp->pdev,
2455                                TG3PCI_MISC_HOST_CTRL,
2456                                tp->misc_host_ctrl);
2457
2458         switch (state) {
2459         case PCI_D0:
2460                 pci_enable_wake(tp->pdev, state, false);
2461                 pci_set_power_state(tp->pdev, PCI_D0);
2462
2463                 /* Switch out of Vaux if it is a NIC */
2464                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2465                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2466
2467                 return 0;
2468
2469         case PCI_D1:
2470         case PCI_D2:
2471         case PCI_D3hot:
2472                 break;
2473
2474         default:
2475                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2476                         tp->dev->name, state);
2477                 return -EINVAL;
2478         }
2479
2480         /* Restore the CLKREQ setting. */
2481         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2482                 u16 lnkctl;
2483
2484                 pci_read_config_word(tp->pdev,
2485                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2486                                      &lnkctl);
2487                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2488                 pci_write_config_word(tp->pdev,
2489                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2490                                       lnkctl);
2491         }
2492
2493         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2494         tw32(TG3PCI_MISC_HOST_CTRL,
2495              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2496
2497         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2498                              device_may_wakeup(&tp->pdev->dev) &&
2499                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2500
2501         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2502                 do_low_power = false;
2503                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2504                     !tp->link_config.phy_is_low_power) {
2505                         struct phy_device *phydev;
2506                         u32 phyid, advertising;
2507
2508                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2509
2510                         tp->link_config.phy_is_low_power = 1;
2511
2512                         tp->link_config.orig_speed = phydev->speed;
2513                         tp->link_config.orig_duplex = phydev->duplex;
2514                         tp->link_config.orig_autoneg = phydev->autoneg;
2515                         tp->link_config.orig_advertising = phydev->advertising;
2516
2517                         advertising = ADVERTISED_TP |
2518                                       ADVERTISED_Pause |
2519                                       ADVERTISED_Autoneg |
2520                                       ADVERTISED_10baseT_Half;
2521
2522                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2523                             device_should_wake) {
2524                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2525                                         advertising |=
2526                                                 ADVERTISED_100baseT_Half |
2527                                                 ADVERTISED_100baseT_Full |
2528                                                 ADVERTISED_10baseT_Full;
2529                                 else
2530                                         advertising |= ADVERTISED_10baseT_Full;
2531                         }
2532
2533                         phydev->advertising = advertising;
2534
2535                         phy_start_aneg(phydev);
2536
2537                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2538                         if (phyid != TG3_PHY_ID_BCMAC131) {
2539                                 phyid &= TG3_PHY_OUI_MASK;
2540                                 if (phyid == TG3_PHY_OUI_1 ||
2541                                     phyid == TG3_PHY_OUI_2 ||
2542                                     phyid == TG3_PHY_OUI_3)
2543                                         do_low_power = true;
2544                         }
2545                 }
2546         } else {
2547                 do_low_power = true;
2548
2549                 if (tp->link_config.phy_is_low_power == 0) {
2550                         tp->link_config.phy_is_low_power = 1;
2551                         tp->link_config.orig_speed = tp->link_config.speed;
2552                         tp->link_config.orig_duplex = tp->link_config.duplex;
2553                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2554                 }
2555
2556                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2557                         tp->link_config.speed = SPEED_10;
2558                         tp->link_config.duplex = DUPLEX_HALF;
2559                         tp->link_config.autoneg = AUTONEG_ENABLE;
2560                         tg3_setup_phy(tp, 0);
2561                 }
2562         }
2563
2564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2565                 u32 val;
2566
2567                 val = tr32(GRC_VCPU_EXT_CTRL);
2568                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2569         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2570                 int i;
2571                 u32 val;
2572
2573                 for (i = 0; i < 200; i++) {
2574                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2575                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2576                                 break;
2577                         msleep(1);
2578                 }
2579         }
2580         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2581                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2582                                                      WOL_DRV_STATE_SHUTDOWN |
2583                                                      WOL_DRV_WOL |
2584                                                      WOL_SET_MAGIC_PKT);
2585
2586         if (device_should_wake) {
2587                 u32 mac_mode;
2588
2589                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2590                         if (do_low_power) {
2591                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2592                                 udelay(40);
2593                         }
2594
2595                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2596                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2597                         else
2598                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2599
2600                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2601                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2602                             ASIC_REV_5700) {
2603                                 u32 speed = (tp->tg3_flags &
2604                                              TG3_FLAG_WOL_SPEED_100MB) ?
2605                                              SPEED_100 : SPEED_10;
2606                                 if (tg3_5700_link_polarity(tp, speed))
2607                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2608                                 else
2609                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2610                         }
2611                 } else {
2612                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2613                 }
2614
2615                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2616                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2617
2618                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2619                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2620                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2621                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2622                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2623                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2624
2625                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2626                         mac_mode |= tp->mac_mode &
2627                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2628                         if (mac_mode & MAC_MODE_APE_TX_EN)
2629                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2630                 }
2631
2632                 tw32_f(MAC_MODE, mac_mode);
2633                 udelay(100);
2634
2635                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2636                 udelay(10);
2637         }
2638
2639         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2640             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2641              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2642                 u32 base_val;
2643
2644                 base_val = tp->pci_clock_ctrl;
2645                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2646                              CLOCK_CTRL_TXCLK_DISABLE);
2647
2648                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2649                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2650         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2651                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2652                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2653                 /* do nothing */
2654         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2655                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2656                 u32 newbits1, newbits2;
2657
2658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2659                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2660                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2661                                     CLOCK_CTRL_TXCLK_DISABLE |
2662                                     CLOCK_CTRL_ALTCLK);
2663                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2665                         newbits1 = CLOCK_CTRL_625_CORE;
2666                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2667                 } else {
2668                         newbits1 = CLOCK_CTRL_ALTCLK;
2669                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670                 }
2671
2672                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2673                             40);
2674
2675                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2676                             40);
2677
2678                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2679                         u32 newbits3;
2680
2681                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2684                                             CLOCK_CTRL_TXCLK_DISABLE |
2685                                             CLOCK_CTRL_44MHZ_CORE);
2686                         } else {
2687                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2688                         }
2689
2690                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2691                                     tp->pci_clock_ctrl | newbits3, 40);
2692                 }
2693         }
2694
2695         if (!(device_should_wake) &&
2696             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2697                 tg3_power_down_phy(tp, do_low_power);
2698
2699         tg3_frob_aux_power(tp);
2700
2701         /* Workaround for unstable PLL clock */
2702         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2703             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2704                 u32 val = tr32(0x7d00);
2705
2706                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2707                 tw32(0x7d00, val);
2708                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2709                         int err;
2710
2711                         err = tg3_nvram_lock(tp);
2712                         tg3_halt_cpu(tp, RX_CPU_BASE);
2713                         if (!err)
2714                                 tg3_nvram_unlock(tp);
2715                 }
2716         }
2717
2718         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2719
2720         if (device_should_wake)
2721                 pci_enable_wake(tp->pdev, state, true);
2722
2723         /* Finally, set the new power state. */
2724         pci_set_power_state(tp->pdev, state);
2725
2726         return 0;
2727 }
2728
2729 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2730 {
2731         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2732         case MII_TG3_AUX_STAT_10HALF:
2733                 *speed = SPEED_10;
2734                 *duplex = DUPLEX_HALF;
2735                 break;
2736
2737         case MII_TG3_AUX_STAT_10FULL:
2738                 *speed = SPEED_10;
2739                 *duplex = DUPLEX_FULL;
2740                 break;
2741
2742         case MII_TG3_AUX_STAT_100HALF:
2743                 *speed = SPEED_100;
2744                 *duplex = DUPLEX_HALF;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_100FULL:
2748                 *speed = SPEED_100;
2749                 *duplex = DUPLEX_FULL;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_1000HALF:
2753                 *speed = SPEED_1000;
2754                 *duplex = DUPLEX_HALF;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_1000FULL:
2758                 *speed = SPEED_1000;
2759                 *duplex = DUPLEX_FULL;
2760                 break;
2761
2762         default:
2763                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2764                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2765                                  SPEED_10;
2766                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2767                                   DUPLEX_HALF;
2768                         break;
2769                 }
2770                 *speed = SPEED_INVALID;
2771                 *duplex = DUPLEX_INVALID;
2772                 break;
2773         }
2774 }
2775
2776 static void tg3_phy_copper_begin(struct tg3 *tp)
2777 {
2778         u32 new_adv;
2779         int i;
2780
2781         if (tp->link_config.phy_is_low_power) {
2782                 /* Entering low power mode.  Disable gigabit and
2783                  * 100baseT advertisements.
2784                  */
2785                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2786
2787                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2788                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2789                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2790                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2791
2792                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793         } else if (tp->link_config.speed == SPEED_INVALID) {
2794                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2795                         tp->link_config.advertising &=
2796                                 ~(ADVERTISED_1000baseT_Half |
2797                                   ADVERTISED_1000baseT_Full);
2798
2799                 new_adv = ADVERTISE_CSMA;
2800                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2801                         new_adv |= ADVERTISE_10HALF;
2802                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2803                         new_adv |= ADVERTISE_10FULL;
2804                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2805                         new_adv |= ADVERTISE_100HALF;
2806                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2807                         new_adv |= ADVERTISE_100FULL;
2808
2809                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2810
2811                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2812
2813                 if (tp->link_config.advertising &
2814                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2815                         new_adv = 0;
2816                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2817                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2818                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2819                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2820                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2821                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2822                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2823                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2824                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2825                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826                 } else {
2827                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2828                 }
2829         } else {
2830                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831                 new_adv |= ADVERTISE_CSMA;
2832
2833                 /* Asking for a specific link mode. */
2834                 if (tp->link_config.speed == SPEED_1000) {
2835                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837                         if (tp->link_config.duplex == DUPLEX_FULL)
2838                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2839                         else
2840                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2841                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2842                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2843                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2844                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2845                 } else {
2846                         if (tp->link_config.speed == SPEED_100) {
2847                                 if (tp->link_config.duplex == DUPLEX_FULL)
2848                                         new_adv |= ADVERTISE_100FULL;
2849                                 else
2850                                         new_adv |= ADVERTISE_100HALF;
2851                         } else {
2852                                 if (tp->link_config.duplex == DUPLEX_FULL)
2853                                         new_adv |= ADVERTISE_10FULL;
2854                                 else
2855                                         new_adv |= ADVERTISE_10HALF;
2856                         }
2857                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2858
2859                         new_adv = 0;
2860                 }
2861
2862                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2863         }
2864
2865         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2866             tp->link_config.speed != SPEED_INVALID) {
2867                 u32 bmcr, orig_bmcr;
2868
2869                 tp->link_config.active_speed = tp->link_config.speed;
2870                 tp->link_config.active_duplex = tp->link_config.duplex;
2871
2872                 bmcr = 0;
2873                 switch (tp->link_config.speed) {
2874                 default:
2875                 case SPEED_10:
2876                         break;
2877
2878                 case SPEED_100:
2879                         bmcr |= BMCR_SPEED100;
2880                         break;
2881
2882                 case SPEED_1000:
2883                         bmcr |= TG3_BMCR_SPEED1000;
2884                         break;
2885                 }
2886
2887                 if (tp->link_config.duplex == DUPLEX_FULL)
2888                         bmcr |= BMCR_FULLDPLX;
2889
2890                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2891                     (bmcr != orig_bmcr)) {
2892                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2893                         for (i = 0; i < 1500; i++) {
2894                                 u32 tmp;
2895
2896                                 udelay(10);
2897                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2898                                     tg3_readphy(tp, MII_BMSR, &tmp))
2899                                         continue;
2900                                 if (!(tmp & BMSR_LSTATUS)) {
2901                                         udelay(40);
2902                                         break;
2903                                 }
2904                         }
2905                         tg3_writephy(tp, MII_BMCR, bmcr);
2906                         udelay(40);
2907                 }
2908         } else {
2909                 tg3_writephy(tp, MII_BMCR,
2910                              BMCR_ANENABLE | BMCR_ANRESTART);
2911         }
2912 }
2913
2914 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2915 {
2916         int err;
2917
2918         /* Turn off tap power management. */
2919         /* Set Extended packet length bit */
2920         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2921
2922         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2923         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2924
2925         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2926         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2927
2928         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2936
2937         udelay(40);
2938
2939         return err;
2940 }
2941
2942 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2943 {
2944         u32 adv_reg, all_mask = 0;
2945
2946         if (mask & ADVERTISED_10baseT_Half)
2947                 all_mask |= ADVERTISE_10HALF;
2948         if (mask & ADVERTISED_10baseT_Full)
2949                 all_mask |= ADVERTISE_10FULL;
2950         if (mask & ADVERTISED_100baseT_Half)
2951                 all_mask |= ADVERTISE_100HALF;
2952         if (mask & ADVERTISED_100baseT_Full)
2953                 all_mask |= ADVERTISE_100FULL;
2954
2955         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2956                 return 0;
2957
2958         if ((adv_reg & all_mask) != all_mask)
2959                 return 0;
2960         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2961                 u32 tg3_ctrl;
2962
2963                 all_mask = 0;
2964                 if (mask & ADVERTISED_1000baseT_Half)
2965                         all_mask |= ADVERTISE_1000HALF;
2966                 if (mask & ADVERTISED_1000baseT_Full)
2967                         all_mask |= ADVERTISE_1000FULL;
2968
2969                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2970                         return 0;
2971
2972                 if ((tg3_ctrl & all_mask) != all_mask)
2973                         return 0;
2974         }
2975         return 1;
2976 }
2977
2978 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2979 {
2980         u32 curadv, reqadv;
2981
2982         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2983                 return 1;
2984
2985         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2986         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2987
2988         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2989                 if (curadv != reqadv)
2990                         return 0;
2991
2992                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2993                         tg3_readphy(tp, MII_LPA, rmtadv);
2994         } else {
2995                 /* Reprogram the advertisement register, even if it
2996                  * does not affect the current link.  If the link
2997                  * gets renegotiated in the future, we can save an
2998                  * additional renegotiation cycle by advertising
2999                  * it correctly in the first place.
3000                  */
3001                 if (curadv != reqadv) {
3002                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3003                                      ADVERTISE_PAUSE_ASYM);
3004                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3005                 }
3006         }
3007
3008         return 1;
3009 }
3010
3011 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3012 {
3013         int current_link_up;
3014         u32 bmsr, dummy;
3015         u32 lcl_adv, rmt_adv;
3016         u16 current_speed;
3017         u8 current_duplex;
3018         int i, err;
3019
3020         tw32(MAC_EVENT, 0);
3021
3022         tw32_f(MAC_STATUS,
3023              (MAC_STATUS_SYNC_CHANGED |
3024               MAC_STATUS_CFG_CHANGED |
3025               MAC_STATUS_MI_COMPLETION |
3026               MAC_STATUS_LNKSTATE_CHANGED));
3027         udelay(40);
3028
3029         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3030                 tw32_f(MAC_MI_MODE,
3031                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3032                 udelay(80);
3033         }
3034
3035         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3036
3037         /* Some third-party PHYs need to be reset on link going
3038          * down.
3039          */
3040         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3041              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3042              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3043             netif_carrier_ok(tp->dev)) {
3044                 tg3_readphy(tp, MII_BMSR, &bmsr);
3045                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3046                     !(bmsr & BMSR_LSTATUS))
3047                         force_reset = 1;
3048         }
3049         if (force_reset)
3050                 tg3_phy_reset(tp);
3051
3052         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3053                 tg3_readphy(tp, MII_BMSR, &bmsr);
3054                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3055                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3056                         bmsr = 0;
3057
3058                 if (!(bmsr & BMSR_LSTATUS)) {
3059                         err = tg3_init_5401phy_dsp(tp);
3060                         if (err)
3061                                 return err;
3062
3063                         tg3_readphy(tp, MII_BMSR, &bmsr);
3064                         for (i = 0; i < 1000; i++) {
3065                                 udelay(10);
3066                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067                                     (bmsr & BMSR_LSTATUS)) {
3068                                         udelay(40);
3069                                         break;
3070                                 }
3071                         }
3072
3073                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3074                             !(bmsr & BMSR_LSTATUS) &&
3075                             tp->link_config.active_speed == SPEED_1000) {
3076                                 err = tg3_phy_reset(tp);
3077                                 if (!err)
3078                                         err = tg3_init_5401phy_dsp(tp);
3079                                 if (err)
3080                                         return err;
3081                         }
3082                 }
3083         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3084                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3085                 /* 5701 {A0,B0} CRC bug workaround */
3086                 tg3_writephy(tp, 0x15, 0x0a75);
3087                 tg3_writephy(tp, 0x1c, 0x8c68);
3088                 tg3_writephy(tp, 0x1c, 0x8d68);
3089                 tg3_writephy(tp, 0x1c, 0x8c68);
3090         }
3091
3092         /* Clear pending interrupts... */
3093         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3095
3096         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3097                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3098         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3099                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3100
3101         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3102             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3103                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3104                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3106                 else
3107                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3108         }
3109
3110         current_link_up = 0;
3111         current_speed = SPEED_INVALID;
3112         current_duplex = DUPLEX_INVALID;
3113
3114         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3115                 u32 val;
3116
3117                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119                 if (!(val & (1 << 10))) {
3120                         val |= (1 << 10);
3121                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122                         goto relink;
3123                 }
3124         }
3125
3126         bmsr = 0;
3127         for (i = 0; i < 100; i++) {
3128                 tg3_readphy(tp, MII_BMSR, &bmsr);
3129                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                     (bmsr & BMSR_LSTATUS))
3131                         break;
3132                 udelay(40);
3133         }
3134
3135         if (bmsr & BMSR_LSTATUS) {
3136                 u32 aux_stat, bmcr;
3137
3138                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139                 for (i = 0; i < 2000; i++) {
3140                         udelay(10);
3141                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142                             aux_stat)
3143                                 break;
3144                 }
3145
3146                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147                                              &current_speed,
3148                                              &current_duplex);
3149
3150                 bmcr = 0;
3151                 for (i = 0; i < 200; i++) {
3152                         tg3_readphy(tp, MII_BMCR, &bmcr);
3153                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154                                 continue;
3155                         if (bmcr && bmcr != 0x7fff)
3156                                 break;
3157                         udelay(10);
3158                 }
3159
3160                 lcl_adv = 0;
3161                 rmt_adv = 0;
3162
3163                 tp->link_config.active_speed = current_speed;
3164                 tp->link_config.active_duplex = current_duplex;
3165
3166                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167                         if ((bmcr & BMCR_ANENABLE) &&
3168                             tg3_copper_is_advertising_all(tp,
3169                                                 tp->link_config.advertising)) {
3170                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171                                                                   &rmt_adv))
3172                                         current_link_up = 1;
3173                         }
3174                 } else {
3175                         if (!(bmcr & BMCR_ANENABLE) &&
3176                             tp->link_config.speed == current_speed &&
3177                             tp->link_config.duplex == current_duplex &&
3178                             tp->link_config.flowctrl ==
3179                             tp->link_config.active_flowctrl) {
3180                                 current_link_up = 1;
3181                         }
3182                 }
3183
3184                 if (current_link_up == 1 &&
3185                     tp->link_config.active_duplex == DUPLEX_FULL)
3186                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3187         }
3188
3189 relink:
3190         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3191                 u32 tmp;
3192
3193                 tg3_phy_copper_begin(tp);
3194
3195                 tg3_readphy(tp, MII_BMSR, &tmp);
3196                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3197                     (tmp & BMSR_LSTATUS))
3198                         current_link_up = 1;
3199         }
3200
3201         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3202         if (current_link_up == 1) {
3203                 if (tp->link_config.active_speed == SPEED_100 ||
3204                     tp->link_config.active_speed == SPEED_10)
3205                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206                 else
3207                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3208         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3209                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3210         else
3211                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3212
3213         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3214         if (tp->link_config.active_duplex == DUPLEX_HALF)
3215                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3216
3217         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3218                 if (current_link_up == 1 &&
3219                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3220                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3221                 else
3222                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3223         }
3224
3225         /* ??? Without this setting Netgear GA302T PHY does not
3226          * ??? send/receive packets...
3227          */
3228         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3229             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3230                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3231                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3232                 udelay(80);
3233         }
3234
3235         tw32_f(MAC_MODE, tp->mac_mode);
3236         udelay(40);
3237
3238         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3239                 /* Polled via timer. */
3240                 tw32_f(MAC_EVENT, 0);
3241         } else {
3242                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3243         }
3244         udelay(40);
3245
3246         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3247             current_link_up == 1 &&
3248             tp->link_config.active_speed == SPEED_1000 &&
3249             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3250              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251                 udelay(120);
3252                 tw32_f(MAC_STATUS,
3253                      (MAC_STATUS_SYNC_CHANGED |
3254                       MAC_STATUS_CFG_CHANGED));
3255                 udelay(40);
3256                 tg3_write_mem(tp,
3257                               NIC_SRAM_FIRMWARE_MBOX,
3258                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259         }
3260
3261         /* Prevent send BD corruption. */
3262         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3263                 u16 oldlnkctl, newlnkctl;
3264
3265                 pci_read_config_word(tp->pdev,
3266                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3267                                      &oldlnkctl);
3268                 if (tp->link_config.active_speed == SPEED_100 ||
3269                     tp->link_config.active_speed == SPEED_10)
3270                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3271                 else
3272                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3273                 if (newlnkctl != oldlnkctl)
3274                         pci_write_config_word(tp->pdev,
3275                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3276                                               newlnkctl);
3277         }
3278
3279         if (current_link_up != netif_carrier_ok(tp->dev)) {
3280                 if (current_link_up)
3281                         netif_carrier_on(tp->dev);
3282                 else
3283                         netif_carrier_off(tp->dev);
3284                 tg3_link_report(tp);
3285         }
3286
3287         return 0;
3288 }
3289
3290 struct tg3_fiber_aneginfo {
3291         int state;
3292 #define ANEG_STATE_UNKNOWN              0
3293 #define ANEG_STATE_AN_ENABLE            1
3294 #define ANEG_STATE_RESTART_INIT         2
3295 #define ANEG_STATE_RESTART              3
3296 #define ANEG_STATE_DISABLE_LINK_OK      4
3297 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3298 #define ANEG_STATE_ABILITY_DETECT       6
3299 #define ANEG_STATE_ACK_DETECT_INIT      7
3300 #define ANEG_STATE_ACK_DETECT           8
3301 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3302 #define ANEG_STATE_COMPLETE_ACK         10
3303 #define ANEG_STATE_IDLE_DETECT_INIT     11
3304 #define ANEG_STATE_IDLE_DETECT          12
3305 #define ANEG_STATE_LINK_OK              13
3306 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3307 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3308
3309         u32 flags;
3310 #define MR_AN_ENABLE            0x00000001
3311 #define MR_RESTART_AN           0x00000002
3312 #define MR_AN_COMPLETE          0x00000004
3313 #define MR_PAGE_RX              0x00000008
3314 #define MR_NP_LOADED            0x00000010
3315 #define MR_TOGGLE_TX            0x00000020
3316 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3317 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3318 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3319 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3320 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3323 #define MR_TOGGLE_RX            0x00002000
3324 #define MR_NP_RX                0x00004000
3325
3326 #define MR_LINK_OK              0x80000000
3327
3328         unsigned long link_time, cur_time;
3329
3330         u32 ability_match_cfg;
3331         int ability_match_count;
3332
3333         char ability_match, idle_match, ack_match;
3334
3335         u32 txconfig, rxconfig;
3336 #define ANEG_CFG_NP             0x00000080
3337 #define ANEG_CFG_ACK            0x00000040
3338 #define ANEG_CFG_RF2            0x00000020
3339 #define ANEG_CFG_RF1            0x00000010
3340 #define ANEG_CFG_PS2            0x00000001
3341 #define ANEG_CFG_PS1            0x00008000
3342 #define ANEG_CFG_HD             0x00004000
3343 #define ANEG_CFG_FD             0x00002000
3344 #define ANEG_CFG_INVAL          0x00001f06
3345
3346 };
3347 #define ANEG_OK         0
3348 #define ANEG_DONE       1
3349 #define ANEG_TIMER_ENAB 2
3350 #define ANEG_FAILED     -1
3351
3352 #define ANEG_STATE_SETTLE_TIME  10000
3353
3354 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3355                                    struct tg3_fiber_aneginfo *ap)
3356 {
3357         u16 flowctrl;
3358         unsigned long delta;
3359         u32 rx_cfg_reg;
3360         int ret;
3361
3362         if (ap->state == ANEG_STATE_UNKNOWN) {
3363                 ap->rxconfig = 0;
3364                 ap->link_time = 0;
3365                 ap->cur_time = 0;
3366                 ap->ability_match_cfg = 0;
3367                 ap->ability_match_count = 0;
3368                 ap->ability_match = 0;
3369                 ap->idle_match = 0;
3370                 ap->ack_match = 0;
3371         }
3372         ap->cur_time++;
3373
3374         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3375                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3376
3377                 if (rx_cfg_reg != ap->ability_match_cfg) {
3378                         ap->ability_match_cfg = rx_cfg_reg;
3379                         ap->ability_match = 0;
3380                         ap->ability_match_count = 0;
3381                 } else {
3382                         if (++ap->ability_match_count > 1) {
3383                                 ap->ability_match = 1;
3384                                 ap->ability_match_cfg = rx_cfg_reg;
3385                         }
3386                 }
3387                 if (rx_cfg_reg & ANEG_CFG_ACK)
3388                         ap->ack_match = 1;
3389                 else
3390                         ap->ack_match = 0;
3391
3392                 ap->idle_match = 0;
3393         } else {
3394                 ap->idle_match = 1;
3395                 ap->ability_match_cfg = 0;
3396                 ap->ability_match_count = 0;
3397                 ap->ability_match = 0;
3398                 ap->ack_match = 0;
3399
3400                 rx_cfg_reg = 0;
3401         }
3402
3403         ap->rxconfig = rx_cfg_reg;
3404         ret = ANEG_OK;
3405
3406         switch(ap->state) {
3407         case ANEG_STATE_UNKNOWN:
3408                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3409                         ap->state = ANEG_STATE_AN_ENABLE;
3410
3411                 /* fallthru */
3412         case ANEG_STATE_AN_ENABLE:
3413                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3414                 if (ap->flags & MR_AN_ENABLE) {
3415                         ap->link_time = 0;
3416                         ap->cur_time = 0;
3417                         ap->ability_match_cfg = 0;
3418                         ap->ability_match_count = 0;
3419                         ap->ability_match = 0;
3420                         ap->idle_match = 0;
3421                         ap->ack_match = 0;
3422
3423                         ap->state = ANEG_STATE_RESTART_INIT;
3424                 } else {
3425                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3426                 }
3427                 break;
3428
3429         case ANEG_STATE_RESTART_INIT:
3430                 ap->link_time = ap->cur_time;
3431                 ap->flags &= ~(MR_NP_LOADED);
3432                 ap->txconfig = 0;
3433                 tw32(MAC_TX_AUTO_NEG, 0);
3434                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3435                 tw32_f(MAC_MODE, tp->mac_mode);
3436                 udelay(40);
3437
3438                 ret = ANEG_TIMER_ENAB;
3439                 ap->state = ANEG_STATE_RESTART;
3440
3441                 /* fallthru */
3442         case ANEG_STATE_RESTART:
3443                 delta = ap->cur_time - ap->link_time;
3444                 if (delta > ANEG_STATE_SETTLE_TIME) {
3445                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3446                 } else {
3447                         ret = ANEG_TIMER_ENAB;
3448                 }
3449                 break;
3450
3451         case ANEG_STATE_DISABLE_LINK_OK:
3452                 ret = ANEG_DONE;
3453                 break;
3454
3455         case ANEG_STATE_ABILITY_DETECT_INIT:
3456                 ap->flags &= ~(MR_TOGGLE_TX);
3457                 ap->txconfig = ANEG_CFG_FD;
3458                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459                 if (flowctrl & ADVERTISE_1000XPAUSE)
3460                         ap->txconfig |= ANEG_CFG_PS1;
3461                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462                         ap->txconfig |= ANEG_CFG_PS2;
3463                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465                 tw32_f(MAC_MODE, tp->mac_mode);
3466                 udelay(40);
3467
3468                 ap->state = ANEG_STATE_ABILITY_DETECT;
3469                 break;
3470
3471         case ANEG_STATE_ABILITY_DETECT:
3472                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3473                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474                 }
3475                 break;
3476
3477         case ANEG_STATE_ACK_DETECT_INIT:
3478                 ap->txconfig |= ANEG_CFG_ACK;
3479                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3480                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3481                 tw32_f(MAC_MODE, tp->mac_mode);
3482                 udelay(40);
3483
3484                 ap->state = ANEG_STATE_ACK_DETECT;
3485
3486                 /* fallthru */
3487         case ANEG_STATE_ACK_DETECT:
3488                 if (ap->ack_match != 0) {
3489                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3490                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3491                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3492                         } else {
3493                                 ap->state = ANEG_STATE_AN_ENABLE;
3494                         }
3495                 } else if (ap->ability_match != 0 &&
3496                            ap->rxconfig == 0) {
3497                         ap->state = ANEG_STATE_AN_ENABLE;
3498                 }
3499                 break;
3500
3501         case ANEG_STATE_COMPLETE_ACK_INIT:
3502                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3503                         ret = ANEG_FAILED;
3504                         break;
3505                 }
3506                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3507                                MR_LP_ADV_HALF_DUPLEX |
3508                                MR_LP_ADV_SYM_PAUSE |
3509                                MR_LP_ADV_ASYM_PAUSE |
3510                                MR_LP_ADV_REMOTE_FAULT1 |
3511                                MR_LP_ADV_REMOTE_FAULT2 |
3512                                MR_LP_ADV_NEXT_PAGE |
3513                                MR_TOGGLE_RX |
3514                                MR_NP_RX);
3515                 if (ap->rxconfig & ANEG_CFG_FD)
3516                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3517                 if (ap->rxconfig & ANEG_CFG_HD)
3518                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3519                 if (ap->rxconfig & ANEG_CFG_PS1)
3520                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3521                 if (ap->rxconfig & ANEG_CFG_PS2)
3522                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3523                 if (ap->rxconfig & ANEG_CFG_RF1)
3524                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3525                 if (ap->rxconfig & ANEG_CFG_RF2)
3526                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3527                 if (ap->rxconfig & ANEG_CFG_NP)
3528                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3529
3530                 ap->link_time = ap->cur_time;
3531
3532                 ap->flags ^= (MR_TOGGLE_TX);
3533                 if (ap->rxconfig & 0x0008)
3534                         ap->flags |= MR_TOGGLE_RX;
3535                 if (ap->rxconfig & ANEG_CFG_NP)
3536                         ap->flags |= MR_NP_RX;
3537                 ap->flags |= MR_PAGE_RX;
3538
3539                 ap->state = ANEG_STATE_COMPLETE_ACK;
3540                 ret = ANEG_TIMER_ENAB;
3541                 break;
3542
3543         case ANEG_STATE_COMPLETE_ACK:
3544                 if (ap->ability_match != 0 &&
3545                     ap->rxconfig == 0) {
3546                         ap->state = ANEG_STATE_AN_ENABLE;
3547                         break;
3548                 }
3549                 delta = ap->cur_time - ap->link_time;
3550                 if (delta > ANEG_STATE_SETTLE_TIME) {
3551                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3552                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553                         } else {
3554                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3555                                     !(ap->flags & MR_NP_RX)) {
3556                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3557                                 } else {
3558                                         ret = ANEG_FAILED;
3559                                 }
3560                         }
3561                 }
3562                 break;
3563
3564         case ANEG_STATE_IDLE_DETECT_INIT:
3565                 ap->link_time = ap->cur_time;
3566                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3567                 tw32_f(MAC_MODE, tp->mac_mode);
3568                 udelay(40);
3569
3570                 ap->state = ANEG_STATE_IDLE_DETECT;
3571                 ret = ANEG_TIMER_ENAB;
3572                 break;
3573
3574         case ANEG_STATE_IDLE_DETECT:
3575                 if (ap->ability_match != 0 &&
3576                     ap->rxconfig == 0) {
3577                         ap->state = ANEG_STATE_AN_ENABLE;
3578                         break;
3579                 }
3580                 delta = ap->cur_time - ap->link_time;
3581                 if (delta > ANEG_STATE_SETTLE_TIME) {
3582                         /* XXX another gem from the Broadcom driver :( */
3583                         ap->state = ANEG_STATE_LINK_OK;
3584                 }
3585                 break;
3586
3587         case ANEG_STATE_LINK_OK:
3588                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3589                 ret = ANEG_DONE;
3590                 break;
3591
3592         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3593                 /* ??? unimplemented */
3594                 break;
3595
3596         case ANEG_STATE_NEXT_PAGE_WAIT:
3597                 /* ??? unimplemented */
3598                 break;
3599
3600         default:
3601                 ret = ANEG_FAILED;
3602                 break;
3603         }
3604
3605         return ret;
3606 }
3607
3608 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3609 {
3610         int res = 0;
3611         struct tg3_fiber_aneginfo aninfo;
3612         int status = ANEG_FAILED;
3613         unsigned int tick;
3614         u32 tmp;
3615
3616         tw32_f(MAC_TX_AUTO_NEG, 0);
3617
3618         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3619         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3620         udelay(40);
3621
3622         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3623         udelay(40);
3624
3625         memset(&aninfo, 0, sizeof(aninfo));
3626         aninfo.flags |= MR_AN_ENABLE;
3627         aninfo.state = ANEG_STATE_UNKNOWN;
3628         aninfo.cur_time = 0;
3629         tick = 0;
3630         while (++tick < 195000) {
3631                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3632                 if (status == ANEG_DONE || status == ANEG_FAILED)
3633                         break;
3634
3635                 udelay(1);
3636         }
3637
3638         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3639         tw32_f(MAC_MODE, tp->mac_mode);
3640         udelay(40);
3641
3642         *txflags = aninfo.txconfig;
3643         *rxflags = aninfo.flags;
3644
3645         if (status == ANEG_DONE &&
3646             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3647                              MR_LP_ADV_FULL_DUPLEX)))
3648                 res = 1;
3649
3650         return res;
3651 }
3652
3653 static void tg3_init_bcm8002(struct tg3 *tp)
3654 {
3655         u32 mac_status = tr32(MAC_STATUS);
3656         int i;
3657
3658         /* Reset when initting first time or we have a link. */
3659         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3660             !(mac_status & MAC_STATUS_PCS_SYNCED))
3661                 return;
3662
3663         /* Set PLL lock range. */
3664         tg3_writephy(tp, 0x16, 0x8007);
3665
3666         /* SW reset */
3667         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3668
3669         /* Wait for reset to complete. */
3670         /* XXX schedule_timeout() ... */
3671         for (i = 0; i < 500; i++)
3672                 udelay(10);
3673
3674         /* Config mode; select PMA/Ch 1 regs. */
3675         tg3_writephy(tp, 0x10, 0x8411);
3676
3677         /* Enable auto-lock and comdet, select txclk for tx. */
3678         tg3_writephy(tp, 0x11, 0x0a10);
3679
3680         tg3_writephy(tp, 0x18, 0x00a0);
3681         tg3_writephy(tp, 0x16, 0x41ff);
3682
3683         /* Assert and deassert POR. */
3684         tg3_writephy(tp, 0x13, 0x0400);
3685         udelay(40);
3686         tg3_writephy(tp, 0x13, 0x0000);
3687
3688         tg3_writephy(tp, 0x11, 0x0a50);
3689         udelay(40);
3690         tg3_writephy(tp, 0x11, 0x0a10);
3691
3692         /* Wait for signal to stabilize */
3693         /* XXX schedule_timeout() ... */
3694         for (i = 0; i < 15000; i++)
3695                 udelay(10);
3696
3697         /* Deselect the channel register so we can read the PHYID
3698          * later.
3699          */
3700         tg3_writephy(tp, 0x10, 0x8011);
3701 }
3702
3703 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3704 {
3705         u16 flowctrl;
3706         u32 sg_dig_ctrl, sg_dig_status;
3707         u32 serdes_cfg, expected_sg_dig_ctrl;
3708         int workaround, port_a;
3709         int current_link_up;
3710
3711         serdes_cfg = 0;
3712         expected_sg_dig_ctrl = 0;
3713         workaround = 0;
3714         port_a = 1;
3715         current_link_up = 0;
3716
3717         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3718             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3719                 workaround = 1;
3720                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3721                         port_a = 0;
3722
3723                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724                 /* preserve bits 20-23 for voltage regulator */
3725                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3726         }
3727
3728         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3729
3730         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3731                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3732                         if (workaround) {
3733                                 u32 val = serdes_cfg;
3734
3735                                 if (port_a)
3736                                         val |= 0xc010000;
3737                                 else
3738                                         val |= 0x4010000;
3739                                 tw32_f(MAC_SERDES_CFG, val);
3740                         }
3741
3742                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3743                 }
3744                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3745                         tg3_setup_flow_control(tp, 0, 0);
3746                         current_link_up = 1;
3747                 }
3748                 goto out;
3749         }
3750
3751         /* Want auto-negotiation.  */
3752         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3753
3754         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3755         if (flowctrl & ADVERTISE_1000XPAUSE)
3756                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3757         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3758                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3759
3760         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3761                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3762                     tp->serdes_counter &&
3763                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3764                                     MAC_STATUS_RCVD_CFG)) ==
3765                      MAC_STATUS_PCS_SYNCED)) {
3766                         tp->serdes_counter--;
3767                         current_link_up = 1;
3768                         goto out;
3769                 }
3770 restart_autoneg:
3771                 if (workaround)
3772                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3773                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3774                 udelay(5);
3775                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3776
3777                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3778                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3779         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3780                                  MAC_STATUS_SIGNAL_DET)) {
3781                 sg_dig_status = tr32(SG_DIG_STATUS);
3782                 mac_status = tr32(MAC_STATUS);
3783
3784                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3785                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3786                         u32 local_adv = 0, remote_adv = 0;
3787
3788                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3789                                 local_adv |= ADVERTISE_1000XPAUSE;
3790                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3791                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3792
3793                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3794                                 remote_adv |= LPA_1000XPAUSE;
3795                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3796                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3797
3798                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3799                         current_link_up = 1;
3800                         tp->serdes_counter = 0;
3801                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3802                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3803                         if (tp->serdes_counter)
3804                                 tp->serdes_counter--;
3805                         else {
3806                                 if (workaround) {
3807                                         u32 val = serdes_cfg;
3808
3809                                         if (port_a)
3810                                                 val |= 0xc010000;
3811                                         else
3812                                                 val |= 0x4010000;
3813
3814                                         tw32_f(MAC_SERDES_CFG, val);
3815                                 }
3816
3817                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3818                                 udelay(40);
3819
3820                                 /* Link parallel detection - link is up */
3821                                 /* only if we have PCS_SYNC and not */
3822                                 /* receiving config code words */
3823                                 mac_status = tr32(MAC_STATUS);
3824                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3825                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3826                                         tg3_setup_flow_control(tp, 0, 0);
3827                                         current_link_up = 1;
3828                                         tp->tg3_flags2 |=
3829                                                 TG3_FLG2_PARALLEL_DETECT;
3830                                         tp->serdes_counter =
3831                                                 SERDES_PARALLEL_DET_TIMEOUT;
3832                                 } else
3833                                         goto restart_autoneg;
3834                         }
3835                 }
3836         } else {
3837                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3838                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3839         }
3840
3841 out:
3842         return current_link_up;
3843 }
3844
3845 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3846 {
3847         int current_link_up = 0;
3848
3849         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3850                 goto out;
3851
3852         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3853                 u32 txflags, rxflags;
3854                 int i;
3855
3856                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3857                         u32 local_adv = 0, remote_adv = 0;
3858
3859                         if (txflags & ANEG_CFG_PS1)
3860                                 local_adv |= ADVERTISE_1000XPAUSE;
3861                         if (txflags & ANEG_CFG_PS2)
3862                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3863
3864                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3865                                 remote_adv |= LPA_1000XPAUSE;
3866                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3867                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3868
3869                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3870
3871                         current_link_up = 1;
3872                 }
3873                 for (i = 0; i < 30; i++) {
3874                         udelay(20);
3875                         tw32_f(MAC_STATUS,
3876                                (MAC_STATUS_SYNC_CHANGED |
3877                                 MAC_STATUS_CFG_CHANGED));
3878                         udelay(40);
3879                         if ((tr32(MAC_STATUS) &
3880                              (MAC_STATUS_SYNC_CHANGED |
3881                               MAC_STATUS_CFG_CHANGED)) == 0)
3882                                 break;
3883                 }
3884
3885                 mac_status = tr32(MAC_STATUS);
3886                 if (current_link_up == 0 &&
3887                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3888                     !(mac_status & MAC_STATUS_RCVD_CFG))
3889                         current_link_up = 1;
3890         } else {
3891                 tg3_setup_flow_control(tp, 0, 0);
3892
3893                 /* Forcing 1000FD link up. */
3894                 current_link_up = 1;
3895
3896                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3897                 udelay(40);
3898
3899                 tw32_f(MAC_MODE, tp->mac_mode);
3900                 udelay(40);
3901         }
3902
3903 out:
3904         return current_link_up;
3905 }
3906
3907 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3908 {
3909         u32 orig_pause_cfg;
3910         u16 orig_active_speed;
3911         u8 orig_active_duplex;
3912         u32 mac_status;
3913         int current_link_up;
3914         int i;
3915
3916         orig_pause_cfg = tp->link_config.active_flowctrl;
3917         orig_active_speed = tp->link_config.active_speed;
3918         orig_active_duplex = tp->link_config.active_duplex;
3919
3920         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3921             netif_carrier_ok(tp->dev) &&
3922             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3923                 mac_status = tr32(MAC_STATUS);
3924                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3925                                MAC_STATUS_SIGNAL_DET |
3926                                MAC_STATUS_CFG_CHANGED |
3927                                MAC_STATUS_RCVD_CFG);
3928                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3929                                    MAC_STATUS_SIGNAL_DET)) {
3930                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3931                                             MAC_STATUS_CFG_CHANGED));
3932                         return 0;
3933                 }
3934         }
3935
3936         tw32_f(MAC_TX_AUTO_NEG, 0);
3937
3938         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3939         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3940         tw32_f(MAC_MODE, tp->mac_mode);
3941         udelay(40);
3942
3943         if (tp->phy_id == PHY_ID_BCM8002)
3944                 tg3_init_bcm8002(tp);
3945
3946         /* Enable link change event even when serdes polling.  */
3947         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3948         udelay(40);
3949
3950         current_link_up = 0;
3951         mac_status = tr32(MAC_STATUS);
3952
3953         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3954                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3955         else
3956                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3957
3958         tp->napi[0].hw_status->status =
3959                 (SD_STATUS_UPDATED |
3960                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3961
3962         for (i = 0; i < 100; i++) {
3963                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964                                     MAC_STATUS_CFG_CHANGED));
3965                 udelay(5);
3966                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3967                                          MAC_STATUS_CFG_CHANGED |
3968                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3969                         break;
3970         }
3971
3972         mac_status = tr32(MAC_STATUS);
3973         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3974                 current_link_up = 0;
3975                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3976                     tp->serdes_counter == 0) {
3977                         tw32_f(MAC_MODE, (tp->mac_mode |
3978                                           MAC_MODE_SEND_CONFIGS));
3979                         udelay(1);
3980                         tw32_f(MAC_MODE, tp->mac_mode);
3981                 }
3982         }
3983
3984         if (current_link_up == 1) {
3985                 tp->link_config.active_speed = SPEED_1000;
3986                 tp->link_config.active_duplex = DUPLEX_FULL;
3987                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988                                     LED_CTRL_LNKLED_OVERRIDE |
3989                                     LED_CTRL_1000MBPS_ON));
3990         } else {
3991                 tp->link_config.active_speed = SPEED_INVALID;
3992                 tp->link_config.active_duplex = DUPLEX_INVALID;
3993                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994                                     LED_CTRL_LNKLED_OVERRIDE |
3995                                     LED_CTRL_TRAFFIC_OVERRIDE));
3996         }
3997
3998         if (current_link_up != netif_carrier_ok(tp->dev)) {
3999                 if (current_link_up)
4000                         netif_carrier_on(tp->dev);
4001                 else
4002                         netif_carrier_off(tp->dev);
4003                 tg3_link_report(tp);
4004         } else {
4005                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4006                 if (orig_pause_cfg != now_pause_cfg ||
4007                     orig_active_speed != tp->link_config.active_speed ||
4008                     orig_active_duplex != tp->link_config.active_duplex)
4009                         tg3_link_report(tp);
4010         }
4011
4012         return 0;
4013 }
4014
4015 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4016 {
4017         int current_link_up, err = 0;
4018         u32 bmsr, bmcr;
4019         u16 current_speed;
4020         u8 current_duplex;
4021         u32 local_adv, remote_adv;
4022
4023         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4024         tw32_f(MAC_MODE, tp->mac_mode);
4025         udelay(40);
4026
4027         tw32(MAC_EVENT, 0);
4028
4029         tw32_f(MAC_STATUS,
4030              (MAC_STATUS_SYNC_CHANGED |
4031               MAC_STATUS_CFG_CHANGED |
4032               MAC_STATUS_MI_COMPLETION |
4033               MAC_STATUS_LNKSTATE_CHANGED));
4034         udelay(40);
4035
4036         if (force_reset)
4037                 tg3_phy_reset(tp);
4038
4039         current_link_up = 0;
4040         current_speed = SPEED_INVALID;
4041         current_duplex = DUPLEX_INVALID;
4042
4043         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4045         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4046                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4047                         bmsr |= BMSR_LSTATUS;
4048                 else
4049                         bmsr &= ~BMSR_LSTATUS;
4050         }
4051
4052         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4053
4054         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4055             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4056                 /* do nothing, just check for link up at the end */
4057         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4058                 u32 adv, new_adv;
4059
4060                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4062                                   ADVERTISE_1000XPAUSE |
4063                                   ADVERTISE_1000XPSE_ASYM |
4064                                   ADVERTISE_SLCT);
4065
4066                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4067
4068                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4069                         new_adv |= ADVERTISE_1000XHALF;
4070                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4071                         new_adv |= ADVERTISE_1000XFULL;
4072
4073                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4074                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4075                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4076                         tg3_writephy(tp, MII_BMCR, bmcr);
4077
4078                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4079                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4080                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081
4082                         return err;
4083                 }
4084         } else {
4085                 u32 new_bmcr;
4086
4087                 bmcr &= ~BMCR_SPEED1000;
4088                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4089
4090                 if (tp->link_config.duplex == DUPLEX_FULL)
4091                         new_bmcr |= BMCR_FULLDPLX;
4092
4093                 if (new_bmcr != bmcr) {
4094                         /* BMCR_SPEED1000 is a reserved bit that needs
4095                          * to be set on write.
4096                          */
4097                         new_bmcr |= BMCR_SPEED1000;
4098
4099                         /* Force a linkdown */
4100                         if (netif_carrier_ok(tp->dev)) {
4101                                 u32 adv;
4102
4103                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4104                                 adv &= ~(ADVERTISE_1000XFULL |
4105                                          ADVERTISE_1000XHALF |
4106                                          ADVERTISE_SLCT);
4107                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4108                                 tg3_writephy(tp, MII_BMCR, bmcr |
4109                                                            BMCR_ANRESTART |
4110                                                            BMCR_ANENABLE);
4111                                 udelay(10);
4112                                 netif_carrier_off(tp->dev);
4113                         }
4114                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4115                         bmcr = new_bmcr;
4116                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4118                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4119                             ASIC_REV_5714) {
4120                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4121                                         bmsr |= BMSR_LSTATUS;
4122                                 else
4123                                         bmsr &= ~BMSR_LSTATUS;
4124                         }
4125                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126                 }
4127         }
4128
4129         if (bmsr & BMSR_LSTATUS) {
4130                 current_speed = SPEED_1000;
4131                 current_link_up = 1;
4132                 if (bmcr & BMCR_FULLDPLX)
4133                         current_duplex = DUPLEX_FULL;
4134                 else
4135                         current_duplex = DUPLEX_HALF;
4136
4137                 local_adv = 0;
4138                 remote_adv = 0;
4139
4140                 if (bmcr & BMCR_ANENABLE) {
4141                         u32 common;
4142
4143                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4144                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4145                         common = local_adv & remote_adv;
4146                         if (common & (ADVERTISE_1000XHALF |
4147                                       ADVERTISE_1000XFULL)) {
4148                                 if (common & ADVERTISE_1000XFULL)
4149                                         current_duplex = DUPLEX_FULL;
4150                                 else
4151                                         current_duplex = DUPLEX_HALF;
4152                         }
4153                         else
4154                                 current_link_up = 0;
4155                 }
4156         }
4157
4158         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4159                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4160
4161         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4162         if (tp->link_config.active_duplex == DUPLEX_HALF)
4163                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4164
4165         tw32_f(MAC_MODE, tp->mac_mode);
4166         udelay(40);
4167
4168         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4169
4170         tp->link_config.active_speed = current_speed;
4171         tp->link_config.active_duplex = current_duplex;
4172
4173         if (current_link_up != netif_carrier_ok(tp->dev)) {
4174                 if (current_link_up)
4175                         netif_carrier_on(tp->dev);
4176                 else {
4177                         netif_carrier_off(tp->dev);
4178                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179                 }
4180                 tg3_link_report(tp);
4181         }
4182         return err;
4183 }
4184
4185 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4186 {
4187         if (tp->serdes_counter) {
4188                 /* Give autoneg time to complete. */
4189                 tp->serdes_counter--;
4190                 return;
4191         }
4192         if (!netif_carrier_ok(tp->dev) &&
4193             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194                 u32 bmcr;
4195
4196                 tg3_readphy(tp, MII_BMCR, &bmcr);
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 phy1, phy2;
4199
4200                         /* Select shadow register 0x1f */
4201                         tg3_writephy(tp, 0x1c, 0x7c00);
4202                         tg3_readphy(tp, 0x1c, &phy1);
4203
4204                         /* Select expansion interrupt status register */
4205                         tg3_writephy(tp, 0x17, 0x0f01);
4206                         tg3_readphy(tp, 0x15, &phy2);
4207                         tg3_readphy(tp, 0x15, &phy2);
4208
4209                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210                                 /* We have signal detect and not receiving
4211                                  * config code words, link is up by parallel
4212                                  * detection.
4213                                  */
4214
4215                                 bmcr &= ~BMCR_ANENABLE;
4216                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217                                 tg3_writephy(tp, MII_BMCR, bmcr);
4218                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4219                         }
4220                 }
4221         }
4222         else if (netif_carrier_ok(tp->dev) &&
4223                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4225                 u32 phy2;
4226
4227                 /* Select expansion interrupt status register */
4228                 tg3_writephy(tp, 0x17, 0x0f01);
4229                 tg3_readphy(tp, 0x15, &phy2);
4230                 if (phy2 & 0x20) {
4231                         u32 bmcr;
4232
4233                         /* Config code words received, turn on autoneg. */
4234                         tg3_readphy(tp, MII_BMCR, &bmcr);
4235                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238
4239                 }
4240         }
4241 }
4242
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244 {
4245         int err;
4246
4247         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4248                 err = tg3_setup_fiber_phy(tp, force_reset);
4249         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4250                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4251         } else {
4252                 err = tg3_setup_copper_phy(tp, force_reset);
4253         }
4254
4255         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4256                 u32 val, scale;
4257
4258                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260                         scale = 65;
4261                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262                         scale = 6;
4263                 else
4264                         scale = 12;
4265
4266                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268                 tw32(GRC_MISC_CFG, val);
4269         }
4270
4271         if (tp->link_config.active_speed == SPEED_1000 &&
4272             tp->link_config.active_duplex == DUPLEX_HALF)
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277         else
4278                 tw32(MAC_TX_LENGTHS,
4279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280                       (6 << TX_LENGTHS_IPG_SHIFT) |
4281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284                 if (netif_carrier_ok(tp->dev)) {
4285                         tw32(HOSTCC_STAT_COAL_TICKS,
4286                              tp->coal.stats_block_coalesce_usecs);
4287                 } else {
4288                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289                 }
4290         }
4291
4292         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294                 if (!netif_carrier_ok(tp->dev))
4295                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296                               tp->pwrmgmt_thresh;
4297                 else
4298                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299                 tw32(PCIE_PWR_MGMT_THRESH, val);
4300         }
4301
4302         return err;
4303 }
4304
4305 /* This is called whenever we suspect that the system chipset is re-
4306  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307  * is bogus tx completions. We try to recover by setting the
4308  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4309  * in the workqueue.
4310  */
4311 static void tg3_tx_recover(struct tg3 *tp)
4312 {
4313         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4314                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4315
4316         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4317                "mapped I/O cycles to the network device, attempting to "
4318                "recover. Please report the problem to the driver maintainer "
4319                "and include system chipset information.\n", tp->dev->name);
4320
4321         spin_lock(&tp->lock);
4322         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4323         spin_unlock(&tp->lock);
4324 }
4325
4326 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4327 {
4328         smp_mb();
4329         return tnapi->tx_pending -
4330                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4331 }
4332
4333 /* Tigon3 never reports partial packet sends.  So we do not
4334  * need special logic to handle SKBs that have not had all
4335  * of their frags sent yet, like SunGEM does.
4336  */
4337 static void tg3_tx(struct tg3_napi *tnapi)
4338 {
4339         struct tg3 *tp = tnapi->tp;
4340         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4341         u32 sw_idx = tnapi->tx_cons;
4342         struct netdev_queue *txq;
4343         int index = tnapi - tp->napi;
4344
4345         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4346                 index--;
4347
4348         txq = netdev_get_tx_queue(tp->dev, index);
4349
4350         while (sw_idx != hw_idx) {
4351                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4352                 struct sk_buff *skb = ri->skb;
4353                 int i, tx_bug = 0;
4354
4355                 if (unlikely(skb == NULL)) {
4356                         tg3_tx_recover(tp);
4357                         return;
4358                 }
4359
4360                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4361
4362                 ri->skb = NULL;
4363
4364                 sw_idx = NEXT_TX(sw_idx);
4365
4366                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4367                         ri = &tnapi->tx_buffers[sw_idx];
4368                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4369                                 tx_bug = 1;
4370                         sw_idx = NEXT_TX(sw_idx);
4371                 }
4372
4373                 dev_kfree_skb(skb);
4374
4375                 if (unlikely(tx_bug)) {
4376                         tg3_tx_recover(tp);
4377                         return;
4378                 }
4379         }
4380
4381         tnapi->tx_cons = sw_idx;
4382
4383         /* Need to make the tx_cons update visible to tg3_start_xmit()
4384          * before checking for netif_queue_stopped().  Without the
4385          * memory barrier, there is a small possibility that tg3_start_xmit()
4386          * will miss it and cause the queue to be stopped forever.
4387          */
4388         smp_mb();
4389
4390         if (unlikely(netif_tx_queue_stopped(txq) &&
4391                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4392                 __netif_tx_lock(txq, smp_processor_id());
4393                 if (netif_tx_queue_stopped(txq) &&
4394                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4395                         netif_tx_wake_queue(txq);
4396                 __netif_tx_unlock(txq);
4397         }
4398 }
4399
4400 /* Returns size of skb allocated or < 0 on error.
4401  *
4402  * We only need to fill in the address because the other members
4403  * of the RX descriptor are invariant, see tg3_init_rings.
4404  *
4405  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4406  * posting buffers we only dirty the first cache line of the RX
4407  * descriptor (containing the address).  Whereas for the RX status
4408  * buffers the cpu only reads the last cacheline of the RX descriptor
4409  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4410  */
4411 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4412                             int src_idx, u32 dest_idx_unmasked)
4413 {
4414         struct tg3 *tp = tnapi->tp;
4415         struct tg3_rx_buffer_desc *desc;
4416         struct ring_info *map, *src_map;
4417         struct sk_buff *skb;
4418         dma_addr_t mapping;
4419         int skb_size, dest_idx;
4420         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4421
4422         src_map = NULL;
4423         switch (opaque_key) {
4424         case RXD_OPAQUE_RING_STD:
4425                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4426                 desc = &tpr->rx_std[dest_idx];
4427                 map = &tpr->rx_std_buffers[dest_idx];
4428                 if (src_idx >= 0)
4429                         src_map = &tpr->rx_std_buffers[src_idx];
4430                 skb_size = tp->rx_pkt_map_sz;
4431                 break;
4432
4433         case RXD_OPAQUE_RING_JUMBO:
4434                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4435                 desc = &tpr->rx_jmb[dest_idx].std;
4436                 map = &tpr->rx_jmb_buffers[dest_idx];
4437                 if (src_idx >= 0)
4438                         src_map = &tpr->rx_jmb_buffers[src_idx];
4439                 skb_size = TG3_RX_JMB_MAP_SZ;
4440                 break;
4441
4442         default:
4443                 return -EINVAL;
4444         }
4445
4446         /* Do not overwrite any of the map or rp information
4447          * until we are sure we can commit to a new buffer.
4448          *
4449          * Callers depend upon this behavior and assume that
4450          * we leave everything unchanged if we fail.
4451          */
4452         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4453         if (skb == NULL)
4454                 return -ENOMEM;
4455
4456         skb_reserve(skb, tp->rx_offset);
4457
4458         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4459                                  PCI_DMA_FROMDEVICE);
4460         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4461                 dev_kfree_skb(skb);
4462                 return -EIO;
4463         }
4464
4465         map->skb = skb;
4466         pci_unmap_addr_set(map, mapping, mapping);
4467
4468         if (src_map != NULL)
4469                 src_map->skb = NULL;
4470
4471         desc->addr_hi = ((u64)mapping >> 32);
4472         desc->addr_lo = ((u64)mapping & 0xffffffff);
4473
4474         return skb_size;
4475 }
4476
4477 /* We only need to move over in the address because the other
4478  * members of the RX descriptor are invariant.  See notes above
4479  * tg3_alloc_rx_skb for full details.
4480  */
4481 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4482                            int src_idx, u32 dest_idx_unmasked)
4483 {
4484         struct tg3 *tp = tnapi->tp;
4485         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4486         struct ring_info *src_map, *dest_map;
4487         int dest_idx;
4488         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4489
4490         switch (opaque_key) {
4491         case RXD_OPAQUE_RING_STD:
4492                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4493                 dest_desc = &tpr->rx_std[dest_idx];
4494                 dest_map = &tpr->rx_std_buffers[dest_idx];
4495                 src_desc = &tpr->rx_std[src_idx];
4496                 src_map = &tpr->rx_std_buffers[src_idx];
4497                 break;
4498
4499         case RXD_OPAQUE_RING_JUMBO:
4500                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4501                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4502                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4503                 src_desc = &tpr->rx_jmb[src_idx].std;
4504                 src_map = &tpr->rx_jmb_buffers[src_idx];
4505                 break;
4506
4507         default:
4508                 return;
4509         }
4510
4511         dest_map->skb = src_map->skb;
4512         pci_unmap_addr_set(dest_map, mapping,
4513                            pci_unmap_addr(src_map, mapping));
4514         dest_desc->addr_hi = src_desc->addr_hi;
4515         dest_desc->addr_lo = src_desc->addr_lo;
4516
4517         src_map->skb = NULL;
4518 }
4519
4520 /* The RX ring scheme is composed of multiple rings which post fresh
4521  * buffers to the chip, and one special ring the chip uses to report
4522  * status back to the host.
4523  *
4524  * The special ring reports the status of received packets to the
4525  * host.  The chip does not write into the original descriptor the
4526  * RX buffer was obtained from.  The chip simply takes the original
4527  * descriptor as provided by the host, updates the status and length
4528  * field, then writes this into the next status ring entry.
4529  *
4530  * Each ring the host uses to post buffers to the chip is described
4531  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4532  * it is first placed into the on-chip ram.  When the packet's length
4533  * is known, it walks down the TG3_BDINFO entries to select the ring.
4534  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4535  * which is within the range of the new packet's length is chosen.
4536  *
4537  * The "separate ring for rx status" scheme may sound queer, but it makes
4538  * sense from a cache coherency perspective.  If only the host writes
4539  * to the buffer post rings, and only the chip writes to the rx status
4540  * rings, then cache lines never move beyond shared-modified state.
4541  * If both the host and chip were to write into the same ring, cache line
4542  * eviction could occur since both entities want it in an exclusive state.
4543  */
4544 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4545 {
4546         struct tg3 *tp = tnapi->tp;
4547         u32 work_mask, rx_std_posted = 0;
4548         u32 sw_idx = tnapi->rx_rcb_ptr;
4549         u16 hw_idx;
4550         int received;
4551         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4552
4553         hw_idx = *(tnapi->rx_rcb_prod_idx);
4554         /*
4555          * We need to order the read of hw_idx and the read of
4556          * the opaque cookie.
4557          */
4558         rmb();
4559         work_mask = 0;
4560         received = 0;
4561         while (sw_idx != hw_idx && budget > 0) {
4562                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4563                 unsigned int len;
4564                 struct sk_buff *skb;
4565                 dma_addr_t dma_addr;
4566                 u32 opaque_key, desc_idx, *post_ptr;
4567
4568                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4569                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4570                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4571                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4572                         dma_addr = pci_unmap_addr(ri, mapping);
4573                         skb = ri->skb;
4574                         post_ptr = &tpr->rx_std_ptr;
4575                         rx_std_posted++;
4576                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4577                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4578                         dma_addr = pci_unmap_addr(ri, mapping);
4579                         skb = ri->skb;
4580                         post_ptr = &tpr->rx_jmb_ptr;
4581                 } else
4582                         goto next_pkt_nopost;
4583
4584                 work_mask |= opaque_key;
4585
4586                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4587                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4588                 drop_it:
4589                         tg3_recycle_rx(tnapi, opaque_key,
4590                                        desc_idx, *post_ptr);
4591                 drop_it_no_recycle:
4592                         /* Other statistics kept track of by card. */
4593                         tp->net_stats.rx_dropped++;
4594                         goto next_pkt;
4595                 }
4596
4597                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4598                       ETH_FCS_LEN;
4599
4600                 if (len > RX_COPY_THRESHOLD
4601                         && tp->rx_offset == NET_IP_ALIGN
4602                         /* rx_offset will likely not equal NET_IP_ALIGN
4603                          * if this is a 5701 card running in PCI-X mode
4604                          * [see tg3_get_invariants()]
4605                          */
4606                 ) {
4607                         int skb_size;
4608
4609                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4610                                                     desc_idx, *post_ptr);
4611                         if (skb_size < 0)
4612                                 goto drop_it;
4613
4614                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4615                                          PCI_DMA_FROMDEVICE);
4616
4617                         skb_put(skb, len);
4618                 } else {
4619                         struct sk_buff *copy_skb;
4620
4621                         tg3_recycle_rx(tnapi, opaque_key,
4622                                        desc_idx, *post_ptr);
4623
4624                         copy_skb = netdev_alloc_skb(tp->dev,
4625                                                     len + TG3_RAW_IP_ALIGN);
4626                         if (copy_skb == NULL)
4627                                 goto drop_it_no_recycle;
4628
4629                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4630                         skb_put(copy_skb, len);
4631                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4632                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4633                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4634
4635                         /* We'll reuse the original ring buffer. */
4636                         skb = copy_skb;
4637                 }
4638
4639                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4640                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4641                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4642                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4643                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4644                 else
4645                         skb->ip_summed = CHECKSUM_NONE;
4646
4647                 skb->protocol = eth_type_trans(skb, tp->dev);
4648
4649                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4650                     skb->protocol != htons(ETH_P_8021Q)) {
4651                         dev_kfree_skb(skb);
4652                         goto next_pkt;
4653                 }
4654
4655 #if TG3_VLAN_TAG_USED
4656                 if (tp->vlgrp != NULL &&
4657                     desc->type_flags & RXD_FLAG_VLAN) {
4658                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4659                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4660                 } else
4661 #endif
4662                         napi_gro_receive(&tnapi->napi, skb);
4663
4664                 received++;
4665                 budget--;
4666
4667 next_pkt:
4668                 (*post_ptr)++;
4669
4670                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4671                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4672
4673                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4674                                      TG3_64BIT_REG_LOW, idx);
4675                         work_mask &= ~RXD_OPAQUE_RING_STD;
4676                         rx_std_posted = 0;
4677                 }
4678 next_pkt_nopost:
4679                 sw_idx++;
4680                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4681
4682                 /* Refresh hw_idx to see if there is new work */
4683                 if (sw_idx == hw_idx) {
4684                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4685                         rmb();
4686                 }
4687         }
4688
4689         /* ACK the status ring. */
4690         tnapi->rx_rcb_ptr = sw_idx;
4691         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4692
4693         /* Refill RX ring(s). */
4694         if (work_mask & RXD_OPAQUE_RING_STD) {
4695                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4696                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4697                              sw_idx);
4698         }
4699         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4700                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4701                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4702                              sw_idx);
4703         }
4704         mmiowb();
4705
4706         return received;
4707 }
4708
4709 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4710 {
4711         struct tg3 *tp = tnapi->tp;
4712         struct tg3_hw_status *sblk = tnapi->hw_status;
4713
4714         /* handle link change and other phy events */
4715         if (!(tp->tg3_flags &
4716               (TG3_FLAG_USE_LINKCHG_REG |
4717                TG3_FLAG_POLL_SERDES))) {
4718                 if (sblk->status & SD_STATUS_LINK_CHG) {
4719                         sblk->status = SD_STATUS_UPDATED |
4720                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4721                         spin_lock(&tp->lock);
4722                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4723                                 tw32_f(MAC_STATUS,
4724                                      (MAC_STATUS_SYNC_CHANGED |
4725                                       MAC_STATUS_CFG_CHANGED |
4726                                       MAC_STATUS_MI_COMPLETION |
4727                                       MAC_STATUS_LNKSTATE_CHANGED));
4728                                 udelay(40);
4729                         } else
4730                                 tg3_setup_phy(tp, 0);
4731                         spin_unlock(&tp->lock);
4732                 }
4733         }
4734
4735         /* run TX completion thread */
4736         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4737                 tg3_tx(tnapi);
4738                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4739                         return work_done;
4740         }
4741
4742         /* run RX thread, within the bounds set by NAPI.
4743          * All RX "locking" is done by ensuring outside
4744          * code synchronizes with tg3->napi.poll()
4745          */
4746         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4747                 work_done += tg3_rx(tnapi, budget - work_done);
4748
4749         return work_done;
4750 }
4751
4752 static int tg3_poll(struct napi_struct *napi, int budget)
4753 {
4754         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4755         struct tg3 *tp = tnapi->tp;
4756         int work_done = 0;
4757         struct tg3_hw_status *sblk = tnapi->hw_status;
4758
4759         while (1) {
4760                 work_done = tg3_poll_work(tnapi, work_done, budget);
4761
4762                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4763                         goto tx_recovery;
4764
4765                 if (unlikely(work_done >= budget))
4766                         break;
4767
4768                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4769                         /* tp->last_tag is used in tg3_int_reenable() below
4770                          * to tell the hw how much work has been processed,
4771                          * so we must read it before checking for more work.
4772                          */
4773                         tnapi->last_tag = sblk->status_tag;
4774                         tnapi->last_irq_tag = tnapi->last_tag;
4775                         rmb();
4776                 } else
4777                         sblk->status &= ~SD_STATUS_UPDATED;
4778
4779                 if (likely(!tg3_has_work(tnapi))) {
4780                         napi_complete(napi);
4781                         tg3_int_reenable(tnapi);
4782                         break;
4783                 }
4784         }
4785
4786         return work_done;
4787
4788 tx_recovery:
4789         /* work_done is guaranteed to be less than budget. */
4790         napi_complete(napi);
4791         schedule_work(&tp->reset_task);
4792         return work_done;
4793 }
4794
4795 static void tg3_irq_quiesce(struct tg3 *tp)
4796 {
4797         int i;
4798
4799         BUG_ON(tp->irq_sync);
4800
4801         tp->irq_sync = 1;
4802         smp_mb();
4803
4804         for (i = 0; i < tp->irq_cnt; i++)
4805                 synchronize_irq(tp->napi[i].irq_vec);
4806 }
4807
4808 static inline int tg3_irq_sync(struct tg3 *tp)
4809 {
4810         return tp->irq_sync;
4811 }
4812
4813 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4814  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4815  * with as well.  Most of the time, this is not necessary except when
4816  * shutting down the device.
4817  */
4818 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4819 {
4820         spin_lock_bh(&tp->lock);
4821         if (irq_sync)
4822                 tg3_irq_quiesce(tp);
4823 }
4824
4825 static inline void tg3_full_unlock(struct tg3 *tp)
4826 {
4827         spin_unlock_bh(&tp->lock);
4828 }
4829
4830 /* One-shot MSI handler - Chip automatically disables interrupt
4831  * after sending MSI so driver doesn't have to do it.
4832  */
4833 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4834 {
4835         struct tg3_napi *tnapi = dev_id;
4836         struct tg3 *tp = tnapi->tp;
4837
4838         prefetch(tnapi->hw_status);
4839         if (tnapi->rx_rcb)
4840                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4841
4842         if (likely(!tg3_irq_sync(tp)))
4843                 napi_schedule(&tnapi->napi);
4844
4845         return IRQ_HANDLED;
4846 }
4847
4848 /* MSI ISR - No need to check for interrupt sharing and no need to
4849  * flush status block and interrupt mailbox. PCI ordering rules
4850  * guarantee that MSI will arrive after the status block.
4851  */
4852 static irqreturn_t tg3_msi(int irq, void *dev_id)
4853 {
4854         struct tg3_napi *tnapi = dev_id;
4855         struct tg3 *tp = tnapi->tp;
4856
4857         prefetch(tnapi->hw_status);
4858         if (tnapi->rx_rcb)
4859                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4860         /*
4861          * Writing any value to intr-mbox-0 clears PCI INTA# and
4862          * chip-internal interrupt pending events.
4863          * Writing non-zero to intr-mbox-0 additional tells the
4864          * NIC to stop sending us irqs, engaging "in-intr-handler"
4865          * event coalescing.
4866          */
4867         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4868         if (likely(!tg3_irq_sync(tp)))
4869                 napi_schedule(&tnapi->napi);
4870
4871         return IRQ_RETVAL(1);
4872 }
4873
4874 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4875 {
4876         struct tg3_napi *tnapi = dev_id;
4877         struct tg3 *tp = tnapi->tp;
4878         struct tg3_hw_status *sblk = tnapi->hw_status;
4879         unsigned int handled = 1;
4880
4881         /* In INTx mode, it is possible for the interrupt to arrive at
4882          * the CPU before the status block posted prior to the interrupt.
4883          * Reading the PCI State register will confirm whether the
4884          * interrupt is ours and will flush the status block.
4885          */
4886         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4887                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4888                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4889                         handled = 0;
4890                         goto out;
4891                 }
4892         }
4893
4894         /*
4895          * Writing any value to intr-mbox-0 clears PCI INTA# and
4896          * chip-internal interrupt pending events.
4897          * Writing non-zero to intr-mbox-0 additional tells the
4898          * NIC to stop sending us irqs, engaging "in-intr-handler"
4899          * event coalescing.
4900          *
4901          * Flush the mailbox to de-assert the IRQ immediately to prevent
4902          * spurious interrupts.  The flush impacts performance but
4903          * excessive spurious interrupts can be worse in some cases.
4904          */
4905         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4906         if (tg3_irq_sync(tp))
4907                 goto out;
4908         sblk->status &= ~SD_STATUS_UPDATED;
4909         if (likely(tg3_has_work(tnapi))) {
4910                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4911                 napi_schedule(&tnapi->napi);
4912         } else {
4913                 /* No work, shared interrupt perhaps?  re-enable
4914                  * interrupts, and flush that PCI write
4915                  */
4916                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4917                                0x00000000);
4918         }
4919 out:
4920         return IRQ_RETVAL(handled);
4921 }
4922
4923 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4924 {
4925         struct tg3_napi *tnapi = dev_id;
4926         struct tg3 *tp = tnapi->tp;
4927         struct tg3_hw_status *sblk = tnapi->hw_status;
4928         unsigned int handled = 1;
4929
4930         /* In INTx mode, it is possible for the interrupt to arrive at
4931          * the CPU before the status block posted prior to the interrupt.
4932          * Reading the PCI State register will confirm whether the
4933          * interrupt is ours and will flush the status block.
4934          */
4935         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4936                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4937                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4938                         handled = 0;
4939                         goto out;
4940                 }
4941         }
4942
4943         /*
4944          * writing any value to intr-mbox-0 clears PCI INTA# and
4945          * chip-internal interrupt pending events.
4946          * writing non-zero to intr-mbox-0 additional tells the
4947          * NIC to stop sending us irqs, engaging "in-intr-handler"
4948          * event coalescing.
4949          *
4950          * Flush the mailbox to de-assert the IRQ immediately to prevent
4951          * spurious interrupts.  The flush impacts performance but
4952          * excessive spurious interrupts can be worse in some cases.
4953          */
4954         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4955
4956         /*
4957          * In a shared interrupt configuration, sometimes other devices'
4958          * interrupts will scream.  We record the current status tag here
4959          * so that the above check can report that the screaming interrupts
4960          * are unhandled.  Eventually they will be silenced.
4961          */
4962         tnapi->last_irq_tag = sblk->status_tag;
4963
4964         if (tg3_irq_sync(tp))
4965                 goto out;
4966
4967         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4968
4969         napi_schedule(&tnapi->napi);
4970
4971 out:
4972         return IRQ_RETVAL(handled);
4973 }
4974
4975 /* ISR for interrupt test */
4976 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4977 {
4978         struct tg3_napi *tnapi = dev_id;
4979         struct tg3 *tp = tnapi->tp;
4980         struct tg3_hw_status *sblk = tnapi->hw_status;
4981
4982         if ((sblk->status & SD_STATUS_UPDATED) ||
4983             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4984                 tg3_disable_ints(tp);
4985                 return IRQ_RETVAL(1);
4986         }
4987         return IRQ_RETVAL(0);
4988 }
4989
4990 static int tg3_init_hw(struct tg3 *, int);
4991 static int tg3_halt(struct tg3 *, int, int);
4992
4993 /* Restart hardware after configuration changes, self-test, etc.
4994  * Invoked with tp->lock held.
4995  */
4996 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4997         __releases(tp->lock)
4998         __acquires(tp->lock)
4999 {
5000         int err;
5001
5002         err = tg3_init_hw(tp, reset_phy);
5003         if (err) {
5004                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5005                        "aborting.\n", tp->dev->name);
5006                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5007                 tg3_full_unlock(tp);
5008                 del_timer_sync(&tp->timer);
5009                 tp->irq_sync = 0;
5010                 tg3_napi_enable(tp);
5011                 dev_close(tp->dev);
5012                 tg3_full_lock(tp, 0);
5013         }
5014         return err;
5015 }
5016
5017 #ifdef CONFIG_NET_POLL_CONTROLLER
5018 static void tg3_poll_controller(struct net_device *dev)
5019 {
5020         int i;
5021         struct tg3 *tp = netdev_priv(dev);
5022
5023         for (i = 0; i < tp->irq_cnt; i++)
5024                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5025 }
5026 #endif
5027
5028 static void tg3_reset_task(struct work_struct *work)
5029 {
5030         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5031         int err;
5032         unsigned int restart_timer;
5033
5034         tg3_full_lock(tp, 0);
5035
5036         if (!netif_running(tp->dev)) {
5037                 tg3_full_unlock(tp);
5038                 return;
5039         }
5040
5041         tg3_full_unlock(tp);
5042
5043         tg3_phy_stop(tp);
5044
5045         tg3_netif_stop(tp);
5046
5047         tg3_full_lock(tp, 1);
5048
5049         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5050         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5051
5052         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5053                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5054                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5055                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5056                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5057         }
5058
5059         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5060         err = tg3_init_hw(tp, 1);
5061         if (err)
5062                 goto out;
5063
5064         tg3_netif_start(tp);
5065
5066         if (restart_timer)
5067                 mod_timer(&tp->timer, jiffies + 1);
5068
5069 out:
5070         tg3_full_unlock(tp);
5071
5072         if (!err)
5073                 tg3_phy_start(tp);
5074 }
5075
5076 static void tg3_dump_short_state(struct tg3 *tp)
5077 {
5078         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5079                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5080         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5081                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5082 }
5083
5084 static void tg3_tx_timeout(struct net_device *dev)
5085 {
5086         struct tg3 *tp = netdev_priv(dev);
5087
5088         if (netif_msg_tx_err(tp)) {
5089                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5090                        dev->name);
5091                 tg3_dump_short_state(tp);
5092         }
5093
5094         schedule_work(&tp->reset_task);
5095 }
5096
5097 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5098 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5099 {
5100         u32 base = (u32) mapping & 0xffffffff;
5101
5102         return ((base > 0xffffdcc0) &&
5103                 (base + len + 8 < base));
5104 }
5105
5106 /* Test for DMA addresses > 40-bit */
5107 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5108                                           int len)
5109 {
5110 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5111         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5112                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5113         return 0;
5114 #else
5115         return 0;
5116 #endif
5117 }
5118
5119 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5120
5121 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5122 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5123                                        struct sk_buff *skb, u32 last_plus_one,
5124                                        u32 *start, u32 base_flags, u32 mss)
5125 {
5126         struct tg3 *tp = tnapi->tp;
5127         struct sk_buff *new_skb;
5128         dma_addr_t new_addr = 0;
5129         u32 entry = *start;
5130         int i, ret = 0;
5131
5132         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5133                 new_skb = skb_copy(skb, GFP_ATOMIC);
5134         else {
5135                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5136
5137                 new_skb = skb_copy_expand(skb,
5138                                           skb_headroom(skb) + more_headroom,
5139                                           skb_tailroom(skb), GFP_ATOMIC);
5140         }
5141
5142         if (!new_skb) {
5143                 ret = -1;
5144         } else {
5145                 /* New SKB is guaranteed to be linear. */
5146                 entry = *start;
5147                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5148                 new_addr = skb_shinfo(new_skb)->dma_head;
5149
5150                 /* Make sure new skb does not cross any 4G boundaries.
5151                  * Drop the packet if it does.
5152                  */
5153                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5154                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5155                         if (!ret)
5156                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5157                                               DMA_TO_DEVICE);
5158                         ret = -1;
5159                         dev_kfree_skb(new_skb);
5160                         new_skb = NULL;
5161                 } else {
5162                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5163                                     base_flags, 1 | (mss << 1));
5164                         *start = NEXT_TX(entry);
5165                 }
5166         }
5167
5168         /* Now clean up the sw ring entries. */
5169         i = 0;
5170         while (entry != last_plus_one) {
5171                 if (i == 0)
5172                         tnapi->tx_buffers[entry].skb = new_skb;
5173                 else
5174                         tnapi->tx_buffers[entry].skb = NULL;
5175                 entry = NEXT_TX(entry);
5176                 i++;
5177         }
5178
5179         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5180         dev_kfree_skb(skb);
5181
5182         return ret;
5183 }
5184
5185 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5186                         dma_addr_t mapping, int len, u32 flags,
5187                         u32 mss_and_is_end)
5188 {
5189         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5190         int is_end = (mss_and_is_end & 0x1);
5191         u32 mss = (mss_and_is_end >> 1);
5192         u32 vlan_tag = 0;
5193
5194         if (is_end)
5195                 flags |= TXD_FLAG_END;
5196         if (flags & TXD_FLAG_VLAN) {
5197                 vlan_tag = flags >> 16;
5198                 flags &= 0xffff;
5199         }
5200         vlan_tag |= (mss << TXD_MSS_SHIFT);
5201
5202         txd->addr_hi = ((u64) mapping >> 32);
5203         txd->addr_lo = ((u64) mapping & 0xffffffff);
5204         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5205         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5206 }
5207
5208 /* hard_start_xmit for devices that don't have any bugs and
5209  * support TG3_FLG2_HW_TSO_2 only.
5210  */
5211 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5212                                   struct net_device *dev)
5213 {
5214         struct tg3 *tp = netdev_priv(dev);
5215         u32 len, entry, base_flags, mss;
5216         struct skb_shared_info *sp;
5217         dma_addr_t mapping;
5218         struct tg3_napi *tnapi;
5219         struct netdev_queue *txq;
5220
5221         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5222         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5223         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5224                 tnapi++;
5225
5226         /* We are running in BH disabled context with netif_tx_lock
5227          * and TX reclaim runs via tp->napi.poll inside of a software
5228          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5229          * no IRQ context deadlocks to worry about either.  Rejoice!
5230          */
5231         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5232                 if (!netif_tx_queue_stopped(txq)) {
5233                         netif_tx_stop_queue(txq);
5234
5235                         /* This is a hard error, log it. */
5236                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5237                                "queue awake!\n", dev->name);
5238                 }
5239                 return NETDEV_TX_BUSY;
5240         }
5241
5242         entry = tnapi->tx_prod;
5243         base_flags = 0;
5244         mss = 0;
5245         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5246                 int tcp_opt_len, ip_tcp_len;
5247                 u32 hdrlen;
5248
5249                 if (skb_header_cloned(skb) &&
5250                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5251                         dev_kfree_skb(skb);
5252                         goto out_unlock;
5253                 }
5254
5255                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5256                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5257                 else {
5258                         struct iphdr *iph = ip_hdr(skb);
5259
5260                         tcp_opt_len = tcp_optlen(skb);
5261                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5262
5263                         iph->check = 0;
5264                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5265                         hdrlen = ip_tcp_len + tcp_opt_len;
5266                 }
5267
5268                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5269                         mss |= (hdrlen & 0xc) << 12;
5270                         if (hdrlen & 0x10)
5271                                 base_flags |= 0x00000010;
5272                         base_flags |= (hdrlen & 0x3e0) << 5;
5273                 } else
5274                         mss |= hdrlen << 9;
5275
5276                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5277                                TXD_FLAG_CPU_POST_DMA);
5278
5279                 tcp_hdr(skb)->check = 0;
5280
5281         }
5282         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5283                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5284 #if TG3_VLAN_TAG_USED
5285         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5286                 base_flags |= (TXD_FLAG_VLAN |
5287                                (vlan_tx_tag_get(skb) << 16));
5288 #endif
5289
5290         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5291                 dev_kfree_skb(skb);
5292                 goto out_unlock;
5293         }
5294
5295         sp = skb_shinfo(skb);
5296
5297         mapping = sp->dma_head;
5298
5299         tnapi->tx_buffers[entry].skb = skb;
5300
5301         len = skb_headlen(skb);
5302
5303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5304             !mss && skb->len > ETH_DATA_LEN)
5305                 base_flags |= TXD_FLAG_JMB_PKT;
5306
5307         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5308                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5309
5310         entry = NEXT_TX(entry);
5311
5312         /* Now loop through additional data fragments, and queue them. */
5313         if (skb_shinfo(skb)->nr_frags > 0) {
5314                 unsigned int i, last;
5315
5316                 last = skb_shinfo(skb)->nr_frags - 1;
5317                 for (i = 0; i <= last; i++) {
5318                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5319
5320                         len = frag->size;
5321                         mapping = sp->dma_maps[i];
5322                         tnapi->tx_buffers[entry].skb = NULL;
5323
5324                         tg3_set_txd(tnapi, entry, mapping, len,
5325                                     base_flags, (i == last) | (mss << 1));
5326
5327                         entry = NEXT_TX(entry);
5328                 }
5329         }
5330
5331         /* Packets are ready, update Tx producer idx local and on card. */
5332         tw32_tx_mbox(tnapi->prodmbox, entry);
5333
5334         tnapi->tx_prod = entry;
5335         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5336                 netif_tx_stop_queue(txq);
5337                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5338                         netif_tx_wake_queue(txq);
5339         }
5340
5341 out_unlock:
5342         mmiowb();
5343
5344         return NETDEV_TX_OK;
5345 }
5346
5347 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5348                                           struct net_device *);
5349
5350 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5351  * TSO header is greater than 80 bytes.
5352  */
5353 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5354 {
5355         struct sk_buff *segs, *nskb;
5356         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5357
5358         /* Estimate the number of fragments in the worst case */
5359         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5360                 netif_stop_queue(tp->dev);
5361                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5362                         return NETDEV_TX_BUSY;
5363
5364                 netif_wake_queue(tp->dev);
5365         }
5366
5367         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5368         if (IS_ERR(segs))
5369                 goto tg3_tso_bug_end;
5370
5371         do {
5372                 nskb = segs;
5373                 segs = segs->next;
5374                 nskb->next = NULL;
5375                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5376         } while (segs);
5377
5378 tg3_tso_bug_end:
5379         dev_kfree_skb(skb);
5380
5381         return NETDEV_TX_OK;
5382 }
5383
5384 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5385  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5386  */
5387 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5388                                           struct net_device *dev)
5389 {
5390         struct tg3 *tp = netdev_priv(dev);
5391         u32 len, entry, base_flags, mss;
5392         struct skb_shared_info *sp;
5393         int would_hit_hwbug;
5394         dma_addr_t mapping;
5395         struct tg3_napi *tnapi;
5396         struct netdev_queue *txq;
5397
5398         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5399         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5400         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5401                 tnapi++;
5402
5403         /* We are running in BH disabled context with netif_tx_lock
5404          * and TX reclaim runs via tp->napi.poll inside of a software
5405          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5406          * no IRQ context deadlocks to worry about either.  Rejoice!
5407          */
5408         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5409                 if (!netif_tx_queue_stopped(txq)) {
5410                         netif_tx_stop_queue(txq);
5411
5412                         /* This is a hard error, log it. */
5413                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5414                                "queue awake!\n", dev->name);
5415                 }
5416                 return NETDEV_TX_BUSY;
5417         }
5418
5419         entry = tnapi->tx_prod;
5420         base_flags = 0;
5421         if (skb->ip_summed == CHECKSUM_PARTIAL)
5422                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5423
5424         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5425                 struct iphdr *iph;
5426                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5427
5428                 if (skb_header_cloned(skb) &&
5429                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5430                         dev_kfree_skb(skb);
5431                         goto out_unlock;
5432                 }
5433
5434                 tcp_opt_len = tcp_optlen(skb);
5435                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5436
5437                 hdr_len = ip_tcp_len + tcp_opt_len;
5438                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5439                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5440                         return (tg3_tso_bug(tp, skb));
5441
5442                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5443                                TXD_FLAG_CPU_POST_DMA);
5444
5445                 iph = ip_hdr(skb);
5446                 iph->check = 0;
5447                 iph->tot_len = htons(mss + hdr_len);
5448                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5449                         tcp_hdr(skb)->check = 0;
5450                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5451                 } else
5452                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5453                                                                  iph->daddr, 0,
5454                                                                  IPPROTO_TCP,
5455                                                                  0);
5456
5457                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5458                         mss |= hdr_len << 9;
5459                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5460                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5461                         if (tcp_opt_len || iph->ihl > 5) {
5462                                 int tsflags;
5463
5464                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5465                                 mss |= (tsflags << 11);
5466                         }
5467                 } else {
5468                         if (tcp_opt_len || iph->ihl > 5) {
5469                                 int tsflags;
5470
5471                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5472                                 base_flags |= tsflags << 12;
5473                         }
5474                 }
5475         }
5476 #if TG3_VLAN_TAG_USED
5477         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5478                 base_flags |= (TXD_FLAG_VLAN |
5479                                (vlan_tx_tag_get(skb) << 16));
5480 #endif
5481
5482         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5483                 dev_kfree_skb(skb);
5484                 goto out_unlock;
5485         }
5486
5487         sp = skb_shinfo(skb);
5488
5489         mapping = sp->dma_head;
5490
5491         tnapi->tx_buffers[entry].skb = skb;
5492
5493         would_hit_hwbug = 0;
5494
5495         len = skb_headlen(skb);
5496
5497         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5498                 would_hit_hwbug = 1;
5499
5500         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5501             tg3_4g_overflow_test(mapping, len))
5502                 would_hit_hwbug = 1;
5503
5504         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5505             tg3_40bit_overflow_test(tp, mapping, len))
5506                 would_hit_hwbug = 1;
5507
5508         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5509                 would_hit_hwbug = 1;
5510
5511         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5512                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5513
5514         entry = NEXT_TX(entry);
5515
5516         /* Now loop through additional data fragments, and queue them. */
5517         if (skb_shinfo(skb)->nr_frags > 0) {
5518                 unsigned int i, last;
5519
5520                 last = skb_shinfo(skb)->nr_frags - 1;
5521                 for (i = 0; i <= last; i++) {
5522                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5523
5524                         len = frag->size;
5525                         mapping = sp->dma_maps[i];
5526
5527                         tnapi->tx_buffers[entry].skb = NULL;
5528
5529                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5530                             len <= 8)
5531                                 would_hit_hwbug = 1;
5532
5533                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5534                             tg3_4g_overflow_test(mapping, len))
5535                                 would_hit_hwbug = 1;
5536
5537                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5538                             tg3_40bit_overflow_test(tp, mapping, len))
5539                                 would_hit_hwbug = 1;
5540
5541                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5542                                 tg3_set_txd(tnapi, entry, mapping, len,
5543                                             base_flags, (i == last)|(mss << 1));
5544                         else
5545                                 tg3_set_txd(tnapi, entry, mapping, len,
5546                                             base_flags, (i == last));
5547
5548                         entry = NEXT_TX(entry);
5549                 }
5550         }
5551
5552         if (would_hit_hwbug) {
5553                 u32 last_plus_one = entry;
5554                 u32 start;
5555
5556                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5557                 start &= (TG3_TX_RING_SIZE - 1);
5558
5559                 /* If the workaround fails due to memory/mapping
5560                  * failure, silently drop this packet.
5561                  */
5562                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5563                                                 &start, base_flags, mss))
5564                         goto out_unlock;
5565
5566                 entry = start;
5567         }
5568
5569         /* Packets are ready, update Tx producer idx local and on card. */
5570         tw32_tx_mbox(tnapi->prodmbox, entry);
5571
5572         tnapi->tx_prod = entry;
5573         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5574                 netif_tx_stop_queue(txq);
5575                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5576                         netif_tx_wake_queue(txq);
5577         }
5578
5579 out_unlock:
5580         mmiowb();
5581
5582         return NETDEV_TX_OK;
5583 }
5584
5585 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5586                                int new_mtu)
5587 {
5588         dev->mtu = new_mtu;
5589
5590         if (new_mtu > ETH_DATA_LEN) {
5591                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5592                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5593                         ethtool_op_set_tso(dev, 0);
5594                 }
5595                 else
5596                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5597         } else {
5598                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5599                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5600                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5601         }
5602 }
5603
5604 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5605 {
5606         struct tg3 *tp = netdev_priv(dev);
5607         int err;
5608
5609         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5610                 return -EINVAL;
5611
5612         if (!netif_running(dev)) {
5613                 /* We'll just catch it later when the
5614                  * device is up'd.
5615                  */
5616                 tg3_set_mtu(dev, tp, new_mtu);
5617                 return 0;
5618         }
5619
5620         tg3_phy_stop(tp);
5621
5622         tg3_netif_stop(tp);
5623
5624         tg3_full_lock(tp, 1);
5625
5626         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5627
5628         tg3_set_mtu(dev, tp, new_mtu);
5629
5630         err = tg3_restart_hw(tp, 0);
5631
5632         if (!err)
5633                 tg3_netif_start(tp);
5634
5635         tg3_full_unlock(tp);
5636
5637         if (!err)
5638                 tg3_phy_start(tp);
5639
5640         return err;
5641 }
5642
5643 static void tg3_rx_prodring_free(struct tg3 *tp,
5644                                  struct tg3_rx_prodring_set *tpr)
5645 {
5646         int i;
5647         struct ring_info *rxp;
5648
5649         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5650                 rxp = &tpr->rx_std_buffers[i];
5651
5652                 if (rxp->skb == NULL)
5653                         continue;
5654
5655                 pci_unmap_single(tp->pdev,
5656                                  pci_unmap_addr(rxp, mapping),
5657                                  tp->rx_pkt_map_sz,
5658                                  PCI_DMA_FROMDEVICE);
5659                 dev_kfree_skb_any(rxp->skb);
5660                 rxp->skb = NULL;
5661         }
5662
5663         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5664                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5665                         rxp = &tpr->rx_jmb_buffers[i];
5666
5667                         if (rxp->skb == NULL)
5668                                 continue;
5669
5670                         pci_unmap_single(tp->pdev,
5671                                          pci_unmap_addr(rxp, mapping),
5672                                          TG3_RX_JMB_MAP_SZ,
5673                                          PCI_DMA_FROMDEVICE);
5674                         dev_kfree_skb_any(rxp->skb);
5675                         rxp->skb = NULL;
5676                 }
5677         }
5678 }
5679
5680 /* Initialize tx/rx rings for packet processing.
5681  *
5682  * The chip has been shut down and the driver detached from
5683  * the networking, so no interrupts or new tx packets will
5684  * end up in the driver.  tp->{tx,}lock are held and thus
5685  * we may not sleep.
5686  */
5687 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5688                                  struct tg3_rx_prodring_set *tpr)
5689 {
5690         u32 i, rx_pkt_dma_sz;
5691         struct tg3_napi *tnapi = &tp->napi[0];
5692
5693         /* Zero out all descriptors. */
5694         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5695
5696         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5697         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5698             tp->dev->mtu > ETH_DATA_LEN)
5699                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5700         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5701
5702         /* Initialize invariants of the rings, we only set this
5703          * stuff once.  This works because the card does not
5704          * write into the rx buffer posting rings.
5705          */
5706         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5707                 struct tg3_rx_buffer_desc *rxd;
5708
5709                 rxd = &tpr->rx_std[i];
5710                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5711                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5712                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5713                                (i << RXD_OPAQUE_INDEX_SHIFT));
5714         }
5715
5716         /* Now allocate fresh SKBs for each rx ring. */
5717         for (i = 0; i < tp->rx_pending; i++) {
5718                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5719                         printk(KERN_WARNING PFX
5720                                "%s: Using a smaller RX standard ring, "
5721                                "only %d out of %d buffers were allocated "
5722                                "successfully.\n",
5723                                tp->dev->name, i, tp->rx_pending);
5724                         if (i == 0)
5725                                 goto initfail;
5726                         tp->rx_pending = i;
5727                         break;
5728                 }
5729         }
5730
5731         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5732                 goto done;
5733
5734         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5735
5736         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5737                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5738                         struct tg3_rx_buffer_desc *rxd;
5739
5740                         rxd = &tpr->rx_jmb[i].std;
5741                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5742                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5743                                 RXD_FLAG_JUMBO;
5744                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5745                                (i << RXD_OPAQUE_INDEX_SHIFT));
5746                 }
5747
5748                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5749                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5750                                              -1, i) < 0) {
5751                                 printk(KERN_WARNING PFX
5752                                        "%s: Using a smaller RX jumbo ring, "
5753                                        "only %d out of %d buffers were "
5754                                        "allocated successfully.\n",
5755                                        tp->dev->name, i, tp->rx_jumbo_pending);
5756                                 if (i == 0)
5757                                         goto initfail;
5758                                 tp->rx_jumbo_pending = i;
5759                                 break;
5760                         }
5761                 }
5762         }
5763
5764 done:
5765         return 0;
5766
5767 initfail:
5768         tg3_rx_prodring_free(tp, tpr);
5769         return -ENOMEM;
5770 }
5771
5772 static void tg3_rx_prodring_fini(struct tg3 *tp,
5773                                  struct tg3_rx_prodring_set *tpr)
5774 {
5775         kfree(tpr->rx_std_buffers);
5776         tpr->rx_std_buffers = NULL;
5777         kfree(tpr->rx_jmb_buffers);
5778         tpr->rx_jmb_buffers = NULL;
5779         if (tpr->rx_std) {
5780                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5781                                     tpr->rx_std, tpr->rx_std_mapping);
5782                 tpr->rx_std = NULL;
5783         }
5784         if (tpr->rx_jmb) {
5785                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5786                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5787                 tpr->rx_jmb = NULL;
5788         }
5789 }
5790
5791 static int tg3_rx_prodring_init(struct tg3 *tp,
5792                                 struct tg3_rx_prodring_set *tpr)
5793 {
5794         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5795                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5796         if (!tpr->rx_std_buffers)
5797                 return -ENOMEM;
5798
5799         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5800                                            &tpr->rx_std_mapping);
5801         if (!tpr->rx_std)
5802                 goto err_out;
5803
5804         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5805                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5806                                               TG3_RX_JUMBO_RING_SIZE,
5807                                               GFP_KERNEL);
5808                 if (!tpr->rx_jmb_buffers)
5809                         goto err_out;
5810
5811                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5812                                                    TG3_RX_JUMBO_RING_BYTES,
5813                                                    &tpr->rx_jmb_mapping);
5814                 if (!tpr->rx_jmb)
5815                         goto err_out;
5816         }
5817
5818         return 0;
5819
5820 err_out:
5821         tg3_rx_prodring_fini(tp, tpr);
5822         return -ENOMEM;
5823 }
5824
5825 /* Free up pending packets in all rx/tx rings.
5826  *
5827  * The chip has been shut down and the driver detached from
5828  * the networking, so no interrupts or new tx packets will
5829  * end up in the driver.  tp->{tx,}lock is not held and we are not
5830  * in an interrupt context and thus may sleep.
5831  */
5832 static void tg3_free_rings(struct tg3 *tp)
5833 {
5834         int i, j;
5835
5836         for (j = 0; j < tp->irq_cnt; j++) {
5837                 struct tg3_napi *tnapi = &tp->napi[j];
5838
5839                 if (!tnapi->tx_buffers)
5840                         continue;
5841
5842                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5843                         struct tx_ring_info *txp;
5844                         struct sk_buff *skb;
5845
5846                         txp = &tnapi->tx_buffers[i];
5847                         skb = txp->skb;
5848
5849                         if (skb == NULL) {
5850                                 i++;
5851                                 continue;
5852                         }
5853
5854                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5855
5856                         txp->skb = NULL;
5857
5858                         i += skb_shinfo(skb)->nr_frags + 1;
5859
5860                         dev_kfree_skb_any(skb);
5861                 }
5862         }
5863
5864         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5865 }
5866
5867 /* Initialize tx/rx rings for packet processing.
5868  *
5869  * The chip has been shut down and the driver detached from
5870  * the networking, so no interrupts or new tx packets will
5871  * end up in the driver.  tp->{tx,}lock are held and thus
5872  * we may not sleep.
5873  */
5874 static int tg3_init_rings(struct tg3 *tp)
5875 {
5876         int i;
5877
5878         /* Free up all the SKBs. */
5879         tg3_free_rings(tp);
5880
5881         for (i = 0; i < tp->irq_cnt; i++) {
5882                 struct tg3_napi *tnapi = &tp->napi[i];
5883
5884                 tnapi->last_tag = 0;
5885                 tnapi->last_irq_tag = 0;
5886                 tnapi->hw_status->status = 0;
5887                 tnapi->hw_status->status_tag = 0;
5888                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5889
5890                 tnapi->tx_prod = 0;
5891                 tnapi->tx_cons = 0;
5892                 if (tnapi->tx_ring)
5893                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5894
5895                 tnapi->rx_rcb_ptr = 0;
5896                 if (tnapi->rx_rcb)
5897                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5898         }
5899
5900         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5901 }
5902
5903 /*
5904  * Must not be invoked with interrupt sources disabled and
5905  * the hardware shutdown down.
5906  */
5907 static void tg3_free_consistent(struct tg3 *tp)
5908 {
5909         int i;
5910
5911         for (i = 0; i < tp->irq_cnt; i++) {
5912                 struct tg3_napi *tnapi = &tp->napi[i];
5913
5914                 if (tnapi->tx_ring) {
5915                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5916                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5917                         tnapi->tx_ring = NULL;
5918                 }
5919
5920                 kfree(tnapi->tx_buffers);
5921                 tnapi->tx_buffers = NULL;
5922
5923                 if (tnapi->rx_rcb) {
5924                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5925                                             tnapi->rx_rcb,
5926                                             tnapi->rx_rcb_mapping);
5927                         tnapi->rx_rcb = NULL;
5928                 }
5929
5930                 if (tnapi->hw_status) {
5931                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5932                                             tnapi->hw_status,
5933                                             tnapi->status_mapping);
5934                         tnapi->hw_status = NULL;
5935                 }
5936         }
5937
5938         if (tp->hw_stats) {
5939                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5940                                     tp->hw_stats, tp->stats_mapping);
5941                 tp->hw_stats = NULL;
5942         }
5943
5944         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5945 }
5946
5947 /*
5948  * Must not be invoked with interrupt sources disabled and
5949  * the hardware shutdown down.  Can sleep.
5950  */
5951 static int tg3_alloc_consistent(struct tg3 *tp)
5952 {
5953         int i;
5954
5955         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5956                 return -ENOMEM;
5957
5958         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5959                                             sizeof(struct tg3_hw_stats),
5960                                             &tp->stats_mapping);
5961         if (!tp->hw_stats)
5962                 goto err_out;
5963
5964         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5965
5966         for (i = 0; i < tp->irq_cnt; i++) {
5967                 struct tg3_napi *tnapi = &tp->napi[i];
5968                 struct tg3_hw_status *sblk;
5969
5970                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5971                                                         TG3_HW_STATUS_SIZE,
5972                                                         &tnapi->status_mapping);
5973                 if (!tnapi->hw_status)
5974                         goto err_out;
5975
5976                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5977                 sblk = tnapi->hw_status;
5978
5979                 /*
5980                  * When RSS is enabled, the status block format changes
5981                  * slightly.  The "rx_jumbo_consumer", "reserved",
5982                  * and "rx_mini_consumer" members get mapped to the
5983                  * other three rx return ring producer indexes.
5984                  */
5985                 switch (i) {
5986                 default:
5987                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5988                         break;
5989                 case 2:
5990                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5991                         break;
5992                 case 3:
5993                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
5994                         break;
5995                 case 4:
5996                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5997                         break;
5998                 }
5999
6000                 /*
6001                  * If multivector RSS is enabled, vector 0 does not handle
6002                  * rx or tx interrupts.  Don't allocate any resources for it.
6003                  */
6004                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6005                         continue;
6006
6007                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6008                                                      TG3_RX_RCB_RING_BYTES(tp),
6009                                                      &tnapi->rx_rcb_mapping);
6010                 if (!tnapi->rx_rcb)
6011                         goto err_out;
6012
6013                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6014
6015                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6016                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6017                 if (!tnapi->tx_buffers)
6018                         goto err_out;
6019
6020                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6021                                                       TG3_TX_RING_BYTES,
6022                                                       &tnapi->tx_desc_mapping);
6023                 if (!tnapi->tx_ring)
6024                         goto err_out;
6025         }
6026
6027         return 0;
6028
6029 err_out:
6030         tg3_free_consistent(tp);
6031         return -ENOMEM;
6032 }
6033
6034 #define MAX_WAIT_CNT 1000
6035
6036 /* To stop a block, clear the enable bit and poll till it
6037  * clears.  tp->lock is held.
6038  */
6039 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6040 {
6041         unsigned int i;
6042         u32 val;
6043
6044         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6045                 switch (ofs) {
6046                 case RCVLSC_MODE:
6047                 case DMAC_MODE:
6048                 case MBFREE_MODE:
6049                 case BUFMGR_MODE:
6050                 case MEMARB_MODE:
6051                         /* We can't enable/disable these bits of the
6052                          * 5705/5750, just say success.
6053                          */
6054                         return 0;
6055
6056                 default:
6057                         break;
6058                 }
6059         }
6060
6061         val = tr32(ofs);
6062         val &= ~enable_bit;
6063         tw32_f(ofs, val);
6064
6065         for (i = 0; i < MAX_WAIT_CNT; i++) {
6066                 udelay(100);
6067                 val = tr32(ofs);
6068                 if ((val & enable_bit) == 0)
6069                         break;
6070         }
6071
6072         if (i == MAX_WAIT_CNT && !silent) {
6073                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6074                        "ofs=%lx enable_bit=%x\n",
6075                        ofs, enable_bit);
6076                 return -ENODEV;
6077         }
6078
6079         return 0;
6080 }
6081
6082 /* tp->lock is held. */
6083 static int tg3_abort_hw(struct tg3 *tp, int silent)
6084 {
6085         int i, err;
6086
6087         tg3_disable_ints(tp);
6088
6089         tp->rx_mode &= ~RX_MODE_ENABLE;
6090         tw32_f(MAC_RX_MODE, tp->rx_mode);
6091         udelay(10);
6092
6093         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6094         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6095         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6096         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6097         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6098         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6099
6100         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6101         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6102         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6103         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6104         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6105         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6106         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6107
6108         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6109         tw32_f(MAC_MODE, tp->mac_mode);
6110         udelay(40);
6111
6112         tp->tx_mode &= ~TX_MODE_ENABLE;
6113         tw32_f(MAC_TX_MODE, tp->tx_mode);
6114
6115         for (i = 0; i < MAX_WAIT_CNT; i++) {
6116                 udelay(100);
6117                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6118                         break;
6119         }
6120         if (i >= MAX_WAIT_CNT) {
6121                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6122                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6123                        tp->dev->name, tr32(MAC_TX_MODE));
6124                 err |= -ENODEV;
6125         }
6126
6127         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6128         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6129         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6130
6131         tw32(FTQ_RESET, 0xffffffff);
6132         tw32(FTQ_RESET, 0x00000000);
6133
6134         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6135         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6136
6137         for (i = 0; i < tp->irq_cnt; i++) {
6138                 struct tg3_napi *tnapi = &tp->napi[i];
6139                 if (tnapi->hw_status)
6140                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6141         }
6142         if (tp->hw_stats)
6143                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6144
6145         return err;
6146 }
6147
6148 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6149 {
6150         int i;
6151         u32 apedata;
6152
6153         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6154         if (apedata != APE_SEG_SIG_MAGIC)
6155                 return;
6156
6157         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6158         if (!(apedata & APE_FW_STATUS_READY))
6159                 return;
6160
6161         /* Wait for up to 1 millisecond for APE to service previous event. */
6162         for (i = 0; i < 10; i++) {
6163                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6164                         return;
6165
6166                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6167
6168                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6169                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6170                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6171
6172                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6173
6174                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6175                         break;
6176
6177                 udelay(100);
6178         }
6179
6180         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6181                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6182 }
6183
6184 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6185 {
6186         u32 event;
6187         u32 apedata;
6188
6189         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6190                 return;
6191
6192         switch (kind) {
6193                 case RESET_KIND_INIT:
6194                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6195                                         APE_HOST_SEG_SIG_MAGIC);
6196                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6197                                         APE_HOST_SEG_LEN_MAGIC);
6198                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6199                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6200                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6201                                         APE_HOST_DRIVER_ID_MAGIC);
6202                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6203                                         APE_HOST_BEHAV_NO_PHYLOCK);
6204
6205                         event = APE_EVENT_STATUS_STATE_START;
6206                         break;
6207                 case RESET_KIND_SHUTDOWN:
6208                         /* With the interface we are currently using,
6209                          * APE does not track driver state.  Wiping
6210                          * out the HOST SEGMENT SIGNATURE forces
6211                          * the APE to assume OS absent status.
6212                          */
6213                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6214
6215                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6216                         break;
6217                 case RESET_KIND_SUSPEND:
6218                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6219                         break;
6220                 default:
6221                         return;
6222         }
6223
6224         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6225
6226         tg3_ape_send_event(tp, event);
6227 }
6228
6229 /* tp->lock is held. */
6230 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6231 {
6232         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6233                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6234
6235         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6236                 switch (kind) {
6237                 case RESET_KIND_INIT:
6238                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6239                                       DRV_STATE_START);
6240                         break;
6241
6242                 case RESET_KIND_SHUTDOWN:
6243                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6244                                       DRV_STATE_UNLOAD);
6245                         break;
6246
6247                 case RESET_KIND_SUSPEND:
6248                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6249                                       DRV_STATE_SUSPEND);
6250                         break;
6251
6252                 default:
6253                         break;
6254                 }
6255         }
6256
6257         if (kind == RESET_KIND_INIT ||
6258             kind == RESET_KIND_SUSPEND)
6259                 tg3_ape_driver_state_change(tp, kind);
6260 }
6261
6262 /* tp->lock is held. */
6263 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6264 {
6265         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6266                 switch (kind) {
6267                 case RESET_KIND_INIT:
6268                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6269                                       DRV_STATE_START_DONE);
6270                         break;
6271
6272                 case RESET_KIND_SHUTDOWN:
6273                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6274                                       DRV_STATE_UNLOAD_DONE);
6275                         break;
6276
6277                 default:
6278                         break;
6279                 }
6280         }
6281
6282         if (kind == RESET_KIND_SHUTDOWN)
6283                 tg3_ape_driver_state_change(tp, kind);
6284 }
6285
6286 /* tp->lock is held. */
6287 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6288 {
6289         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6290                 switch (kind) {
6291                 case RESET_KIND_INIT:
6292                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6293                                       DRV_STATE_START);
6294                         break;
6295
6296                 case RESET_KIND_SHUTDOWN:
6297                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6298                                       DRV_STATE_UNLOAD);
6299                         break;
6300
6301                 case RESET_KIND_SUSPEND:
6302                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6303                                       DRV_STATE_SUSPEND);
6304                         break;
6305
6306                 default:
6307                         break;
6308                 }
6309         }
6310 }
6311
6312 static int tg3_poll_fw(struct tg3 *tp)
6313 {
6314         int i;
6315         u32 val;
6316
6317         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6318                 /* Wait up to 20ms for init done. */
6319                 for (i = 0; i < 200; i++) {
6320                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6321                                 return 0;
6322                         udelay(100);
6323                 }
6324                 return -ENODEV;
6325         }
6326
6327         /* Wait for firmware initialization to complete. */
6328         for (i = 0; i < 100000; i++) {
6329                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6330                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6331                         break;
6332                 udelay(10);
6333         }
6334
6335         /* Chip might not be fitted with firmware.  Some Sun onboard
6336          * parts are configured like that.  So don't signal the timeout
6337          * of the above loop as an error, but do report the lack of
6338          * running firmware once.
6339          */
6340         if (i >= 100000 &&
6341             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6342                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6343
6344                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6345                        tp->dev->name);
6346         }
6347
6348         return 0;
6349 }
6350
6351 /* Save PCI command register before chip reset */
6352 static void tg3_save_pci_state(struct tg3 *tp)
6353 {
6354         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6355 }
6356
6357 /* Restore PCI state after chip reset */
6358 static void tg3_restore_pci_state(struct tg3 *tp)
6359 {
6360         u32 val;
6361
6362         /* Re-enable indirect register accesses. */
6363         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6364                                tp->misc_host_ctrl);
6365
6366         /* Set MAX PCI retry to zero. */
6367         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6368         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6369             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6370                 val |= PCISTATE_RETRY_SAME_DMA;
6371         /* Allow reads and writes to the APE register and memory space. */
6372         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6373                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6374                        PCISTATE_ALLOW_APE_SHMEM_WR;
6375         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6376
6377         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6378
6379         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6380                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6381                         pcie_set_readrq(tp->pdev, 4096);
6382                 else {
6383                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6384                                               tp->pci_cacheline_sz);
6385                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6386                                               tp->pci_lat_timer);
6387                 }
6388         }
6389
6390         /* Make sure PCI-X relaxed ordering bit is clear. */
6391         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6392                 u16 pcix_cmd;
6393
6394                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6395                                      &pcix_cmd);
6396                 pcix_cmd &= ~PCI_X_CMD_ERO;
6397                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6398                                       pcix_cmd);
6399         }
6400
6401         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6402
6403                 /* Chip reset on 5780 will reset MSI enable bit,
6404                  * so need to restore it.
6405                  */
6406                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6407                         u16 ctrl;
6408
6409                         pci_read_config_word(tp->pdev,
6410                                              tp->msi_cap + PCI_MSI_FLAGS,
6411                                              &ctrl);
6412                         pci_write_config_word(tp->pdev,
6413                                               tp->msi_cap + PCI_MSI_FLAGS,
6414                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6415                         val = tr32(MSGINT_MODE);
6416                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6417                 }
6418         }
6419 }
6420
6421 static void tg3_stop_fw(struct tg3 *);
6422
6423 /* tp->lock is held. */
6424 static int tg3_chip_reset(struct tg3 *tp)
6425 {
6426         u32 val;
6427         void (*write_op)(struct tg3 *, u32, u32);
6428         int i, err;
6429
6430         tg3_nvram_lock(tp);
6431
6432         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6433
6434         /* No matching tg3_nvram_unlock() after this because
6435          * chip reset below will undo the nvram lock.
6436          */
6437         tp->nvram_lock_cnt = 0;
6438
6439         /* GRC_MISC_CFG core clock reset will clear the memory
6440          * enable bit in PCI register 4 and the MSI enable bit
6441          * on some chips, so we save relevant registers here.
6442          */
6443         tg3_save_pci_state(tp);
6444
6445         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6446             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6447                 tw32(GRC_FASTBOOT_PC, 0);
6448
6449         /*
6450          * We must avoid the readl() that normally takes place.
6451          * It locks machines, causes machine checks, and other
6452          * fun things.  So, temporarily disable the 5701
6453          * hardware workaround, while we do the reset.
6454          */
6455         write_op = tp->write32;
6456         if (write_op == tg3_write_flush_reg32)
6457                 tp->write32 = tg3_write32;
6458
6459         /* Prevent the irq handler from reading or writing PCI registers
6460          * during chip reset when the memory enable bit in the PCI command
6461          * register may be cleared.  The chip does not generate interrupt
6462          * at this time, but the irq handler may still be called due to irq
6463          * sharing or irqpoll.
6464          */
6465         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6466         for (i = 0; i < tp->irq_cnt; i++) {
6467                 struct tg3_napi *tnapi = &tp->napi[i];
6468                 if (tnapi->hw_status) {
6469                         tnapi->hw_status->status = 0;
6470                         tnapi->hw_status->status_tag = 0;
6471                 }
6472                 tnapi->last_tag = 0;
6473                 tnapi->last_irq_tag = 0;
6474         }
6475         smp_mb();
6476
6477         for (i = 0; i < tp->irq_cnt; i++)
6478                 synchronize_irq(tp->napi[i].irq_vec);
6479
6480         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6481                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6482                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6483         }
6484
6485         /* do the reset */
6486         val = GRC_MISC_CFG_CORECLK_RESET;
6487
6488         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6489                 if (tr32(0x7e2c) == 0x60) {
6490                         tw32(0x7e2c, 0x20);
6491                 }
6492                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6493                         tw32(GRC_MISC_CFG, (1 << 29));
6494                         val |= (1 << 29);
6495                 }
6496         }
6497
6498         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6499                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6500                 tw32(GRC_VCPU_EXT_CTRL,
6501                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6502         }
6503
6504         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6505                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6506         tw32(GRC_MISC_CFG, val);
6507
6508         /* restore 5701 hardware bug workaround write method */
6509         tp->write32 = write_op;
6510
6511         /* Unfortunately, we have to delay before the PCI read back.
6512          * Some 575X chips even will not respond to a PCI cfg access
6513          * when the reset command is given to the chip.
6514          *
6515          * How do these hardware designers expect things to work
6516          * properly if the PCI write is posted for a long period
6517          * of time?  It is always necessary to have some method by
6518          * which a register read back can occur to push the write
6519          * out which does the reset.
6520          *
6521          * For most tg3 variants the trick below was working.
6522          * Ho hum...
6523          */
6524         udelay(120);
6525
6526         /* Flush PCI posted writes.  The normal MMIO registers
6527          * are inaccessible at this time so this is the only
6528          * way to make this reliably (actually, this is no longer
6529          * the case, see above).  I tried to use indirect
6530          * register read/write but this upset some 5701 variants.
6531          */
6532         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6533
6534         udelay(120);
6535
6536         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6537                 u16 val16;
6538
6539                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6540                         int i;
6541                         u32 cfg_val;
6542
6543                         /* Wait for link training to complete.  */
6544                         for (i = 0; i < 5000; i++)
6545                                 udelay(100);
6546
6547                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6548                         pci_write_config_dword(tp->pdev, 0xc4,
6549                                                cfg_val | (1 << 15));
6550                 }
6551
6552                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6553                 pci_read_config_word(tp->pdev,
6554                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6555                                      &val16);
6556                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6557                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6558                 /*
6559                  * Older PCIe devices only support the 128 byte
6560                  * MPS setting.  Enforce the restriction.
6561                  */
6562                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6563                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6564                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6565                 pci_write_config_word(tp->pdev,
6566                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6567                                       val16);
6568
6569                 pcie_set_readrq(tp->pdev, 4096);
6570
6571                 /* Clear error status */
6572                 pci_write_config_word(tp->pdev,
6573                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6574                                       PCI_EXP_DEVSTA_CED |
6575                                       PCI_EXP_DEVSTA_NFED |
6576                                       PCI_EXP_DEVSTA_FED |
6577                                       PCI_EXP_DEVSTA_URD);
6578         }
6579
6580         tg3_restore_pci_state(tp);
6581
6582         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6583
6584         val = 0;
6585         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6586                 val = tr32(MEMARB_MODE);
6587         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6588
6589         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6590                 tg3_stop_fw(tp);
6591                 tw32(0x5000, 0x400);
6592         }
6593
6594         tw32(GRC_MODE, tp->grc_mode);
6595
6596         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6597                 val = tr32(0xc4);
6598
6599                 tw32(0xc4, val | (1 << 15));
6600         }
6601
6602         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6603             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6604                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6605                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6606                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6607                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6608         }
6609
6610         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6611                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6612                 tw32_f(MAC_MODE, tp->mac_mode);
6613         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6614                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6615                 tw32_f(MAC_MODE, tp->mac_mode);
6616         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6617                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6618                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6619                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6620                 tw32_f(MAC_MODE, tp->mac_mode);
6621         } else
6622                 tw32_f(MAC_MODE, 0);
6623         udelay(40);
6624
6625         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6626
6627         err = tg3_poll_fw(tp);
6628         if (err)
6629                 return err;
6630
6631         tg3_mdio_start(tp);
6632
6633         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6634                 u8 phy_addr;
6635
6636                 phy_addr = tp->phy_addr;
6637                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6638
6639                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6640                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6641                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6642                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6643                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6644                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6645                 udelay(10);
6646
6647                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6648                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6649                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6650                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6651                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6652                 udelay(10);
6653
6654                 tp->phy_addr = phy_addr;
6655         }
6656
6657         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6658             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6659             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6660             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6661                 val = tr32(0x7c00);
6662
6663                 tw32(0x7c00, val | (1 << 25));
6664         }
6665
6666         /* Reprobe ASF enable state.  */
6667         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6668         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6669         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6670         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6671                 u32 nic_cfg;
6672
6673                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6674                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6675                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6676                         tp->last_event_jiffies = jiffies;
6677                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6678                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6679                 }
6680         }
6681
6682         return 0;
6683 }
6684
6685 /* tp->lock is held. */
6686 static void tg3_stop_fw(struct tg3 *tp)
6687 {
6688         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6689            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6690                 /* Wait for RX cpu to ACK the previous event. */
6691                 tg3_wait_for_event_ack(tp);
6692
6693                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6694
6695                 tg3_generate_fw_event(tp);
6696
6697                 /* Wait for RX cpu to ACK this event. */
6698                 tg3_wait_for_event_ack(tp);
6699         }
6700 }
6701
6702 /* tp->lock is held. */
6703 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6704 {
6705         int err;
6706
6707         tg3_stop_fw(tp);
6708
6709         tg3_write_sig_pre_reset(tp, kind);
6710
6711         tg3_abort_hw(tp, silent);
6712         err = tg3_chip_reset(tp);
6713
6714         __tg3_set_mac_addr(tp, 0);
6715
6716         tg3_write_sig_legacy(tp, kind);
6717         tg3_write_sig_post_reset(tp, kind);
6718
6719         if (err)
6720                 return err;
6721
6722         return 0;
6723 }
6724
6725 #define RX_CPU_SCRATCH_BASE     0x30000
6726 #define RX_CPU_SCRATCH_SIZE     0x04000
6727 #define TX_CPU_SCRATCH_BASE     0x34000
6728 #define TX_CPU_SCRATCH_SIZE     0x04000
6729
6730 /* tp->lock is held. */
6731 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6732 {
6733         int i;
6734
6735         BUG_ON(offset == TX_CPU_BASE &&
6736             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6737
6738         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6739                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6740
6741                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6742                 return 0;
6743         }
6744         if (offset == RX_CPU_BASE) {
6745                 for (i = 0; i < 10000; i++) {
6746                         tw32(offset + CPU_STATE, 0xffffffff);
6747                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6748                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6749                                 break;
6750                 }
6751
6752                 tw32(offset + CPU_STATE, 0xffffffff);
6753                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6754                 udelay(10);
6755         } else {
6756                 for (i = 0; i < 10000; i++) {
6757                         tw32(offset + CPU_STATE, 0xffffffff);
6758                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6759                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6760                                 break;
6761                 }
6762         }
6763
6764         if (i >= 10000) {
6765                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6766                        "and %s CPU\n",
6767                        tp->dev->name,
6768                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6769                 return -ENODEV;
6770         }
6771
6772         /* Clear firmware's nvram arbitration. */
6773         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6774                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6775         return 0;
6776 }
6777
6778 struct fw_info {
6779         unsigned int fw_base;
6780         unsigned int fw_len;
6781         const __be32 *fw_data;
6782 };
6783
6784 /* tp->lock is held. */
6785 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6786                                  int cpu_scratch_size, struct fw_info *info)
6787 {
6788         int err, lock_err, i;
6789         void (*write_op)(struct tg3 *, u32, u32);
6790
6791         if (cpu_base == TX_CPU_BASE &&
6792             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6793                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6794                        "TX cpu firmware on %s which is 5705.\n",
6795                        tp->dev->name);
6796                 return -EINVAL;
6797         }
6798
6799         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6800                 write_op = tg3_write_mem;
6801         else
6802                 write_op = tg3_write_indirect_reg32;
6803
6804         /* It is possible that bootcode is still loading at this point.
6805          * Get the nvram lock first before halting the cpu.
6806          */
6807         lock_err = tg3_nvram_lock(tp);
6808         err = tg3_halt_cpu(tp, cpu_base);
6809         if (!lock_err)
6810                 tg3_nvram_unlock(tp);
6811         if (err)
6812                 goto out;
6813
6814         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6815                 write_op(tp, cpu_scratch_base + i, 0);
6816         tw32(cpu_base + CPU_STATE, 0xffffffff);
6817         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6818         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6819                 write_op(tp, (cpu_scratch_base +
6820                               (info->fw_base & 0xffff) +
6821                               (i * sizeof(u32))),
6822                               be32_to_cpu(info->fw_data[i]));
6823
6824         err = 0;
6825
6826 out:
6827         return err;
6828 }
6829
6830 /* tp->lock is held. */
6831 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6832 {
6833         struct fw_info info;
6834         const __be32 *fw_data;
6835         int err, i;
6836
6837         fw_data = (void *)tp->fw->data;
6838
6839         /* Firmware blob starts with version numbers, followed by
6840            start address and length. We are setting complete length.
6841            length = end_address_of_bss - start_address_of_text.
6842            Remainder is the blob to be loaded contiguously
6843            from start address. */
6844
6845         info.fw_base = be32_to_cpu(fw_data[1]);
6846         info.fw_len = tp->fw->size - 12;
6847         info.fw_data = &fw_data[3];
6848
6849         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6850                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6851                                     &info);
6852         if (err)
6853                 return err;
6854
6855         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6856                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6857                                     &info);
6858         if (err)
6859                 return err;
6860
6861         /* Now startup only the RX cpu. */
6862         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6863         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6864
6865         for (i = 0; i < 5; i++) {
6866                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6867                         break;
6868                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6869                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6870                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6871                 udelay(1000);
6872         }
6873         if (i >= 5) {
6874                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6875                        "to set RX CPU PC, is %08x should be %08x\n",
6876                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6877                        info.fw_base);
6878                 return -ENODEV;
6879         }
6880         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6881         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6882
6883         return 0;
6884 }
6885
6886 /* 5705 needs a special version of the TSO firmware.  */
6887
6888 /* tp->lock is held. */
6889 static int tg3_load_tso_firmware(struct tg3 *tp)
6890 {
6891         struct fw_info info;
6892         const __be32 *fw_data;
6893         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6894         int err, i;
6895
6896         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6897                 return 0;
6898
6899         fw_data = (void *)tp->fw->data;
6900
6901         /* Firmware blob starts with version numbers, followed by
6902            start address and length. We are setting complete length.
6903            length = end_address_of_bss - start_address_of_text.
6904            Remainder is the blob to be loaded contiguously
6905            from start address. */
6906
6907         info.fw_base = be32_to_cpu(fw_data[1]);
6908         cpu_scratch_size = tp->fw_len;
6909         info.fw_len = tp->fw->size - 12;
6910         info.fw_data = &fw_data[3];
6911
6912         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6913                 cpu_base = RX_CPU_BASE;
6914                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6915         } else {
6916                 cpu_base = TX_CPU_BASE;
6917                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6918                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6919         }
6920
6921         err = tg3_load_firmware_cpu(tp, cpu_base,
6922                                     cpu_scratch_base, cpu_scratch_size,
6923                                     &info);
6924         if (err)
6925                 return err;
6926
6927         /* Now startup the cpu. */
6928         tw32(cpu_base + CPU_STATE, 0xffffffff);
6929         tw32_f(cpu_base + CPU_PC, info.fw_base);
6930
6931         for (i = 0; i < 5; i++) {
6932                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6933                         break;
6934                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6935                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6936                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6937                 udelay(1000);
6938         }
6939         if (i >= 5) {
6940                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6941                        "to set CPU PC, is %08x should be %08x\n",
6942                        tp->dev->name, tr32(cpu_base + CPU_PC),
6943                        info.fw_base);
6944                 return -ENODEV;
6945         }
6946         tw32(cpu_base + CPU_STATE, 0xffffffff);
6947         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6948         return 0;
6949 }
6950
6951
6952 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6953 {
6954         struct tg3 *tp = netdev_priv(dev);
6955         struct sockaddr *addr = p;
6956         int err = 0, skip_mac_1 = 0;
6957
6958         if (!is_valid_ether_addr(addr->sa_data))
6959                 return -EINVAL;
6960
6961         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6962
6963         if (!netif_running(dev))
6964                 return 0;
6965
6966         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6967                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6968
6969                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6970                 addr0_low = tr32(MAC_ADDR_0_LOW);
6971                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6972                 addr1_low = tr32(MAC_ADDR_1_LOW);
6973
6974                 /* Skip MAC addr 1 if ASF is using it. */
6975                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6976                     !(addr1_high == 0 && addr1_low == 0))
6977                         skip_mac_1 = 1;
6978         }
6979         spin_lock_bh(&tp->lock);
6980         __tg3_set_mac_addr(tp, skip_mac_1);
6981         spin_unlock_bh(&tp->lock);
6982
6983         return err;
6984 }
6985
6986 /* tp->lock is held. */
6987 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6988                            dma_addr_t mapping, u32 maxlen_flags,
6989                            u32 nic_addr)
6990 {
6991         tg3_write_mem(tp,
6992                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6993                       ((u64) mapping >> 32));
6994         tg3_write_mem(tp,
6995                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6996                       ((u64) mapping & 0xffffffff));
6997         tg3_write_mem(tp,
6998                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6999                        maxlen_flags);
7000
7001         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7002                 tg3_write_mem(tp,
7003                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7004                               nic_addr);
7005 }
7006
7007 static void __tg3_set_rx_mode(struct net_device *);
7008 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7009 {
7010         int i;
7011
7012         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7013                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7014                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7015                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7016
7017                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7018                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7019                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7020         } else {
7021                 tw32(HOSTCC_TXCOL_TICKS, 0);
7022                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7023                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7024
7025                 tw32(HOSTCC_RXCOL_TICKS, 0);
7026                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7027                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7028         }
7029
7030         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7031                 u32 val = ec->stats_block_coalesce_usecs;
7032
7033                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7034                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7035
7036                 if (!netif_carrier_ok(tp->dev))
7037                         val = 0;
7038
7039                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7040         }
7041
7042         for (i = 0; i < tp->irq_cnt - 1; i++) {
7043                 u32 reg;
7044
7045                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7046                 tw32(reg, ec->rx_coalesce_usecs);
7047                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7048                 tw32(reg, ec->tx_coalesce_usecs);
7049                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7050                 tw32(reg, ec->rx_max_coalesced_frames);
7051                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7052                 tw32(reg, ec->tx_max_coalesced_frames);
7053                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7054                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7055                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7056                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7057         }
7058
7059         for (; i < tp->irq_max - 1; i++) {
7060                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7061                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7062                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7063                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7064                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7065                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7066         }
7067 }
7068
7069 /* tp->lock is held. */
7070 static void tg3_rings_reset(struct tg3 *tp)
7071 {
7072         int i;
7073         u32 stblk, txrcb, rxrcb, limit;
7074         struct tg3_napi *tnapi = &tp->napi[0];
7075
7076         /* Disable all transmit rings but the first. */
7077         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7078                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7079         else
7080                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7081
7082         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7083              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7084                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7085                               BDINFO_FLAGS_DISABLED);
7086
7087
7088         /* Disable all receive return rings but the first. */
7089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7090                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7091         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7092                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7093         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7094                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7095         else
7096                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7097
7098         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7099              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7100                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7101                               BDINFO_FLAGS_DISABLED);
7102
7103         /* Disable interrupts */
7104         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7105
7106         /* Zero mailbox registers. */
7107         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7108                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7109                         tp->napi[i].tx_prod = 0;
7110                         tp->napi[i].tx_cons = 0;
7111                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7112                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7113                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7114                 }
7115         } else {
7116                 tp->napi[0].tx_prod = 0;
7117                 tp->napi[0].tx_cons = 0;
7118                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7119                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7120         }
7121
7122         /* Make sure the NIC-based send BD rings are disabled. */
7123         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7124                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7125                 for (i = 0; i < 16; i++)
7126                         tw32_tx_mbox(mbox + i * 8, 0);
7127         }
7128
7129         txrcb = NIC_SRAM_SEND_RCB;
7130         rxrcb = NIC_SRAM_RCV_RET_RCB;
7131
7132         /* Clear status block in ram. */
7133         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7134
7135         /* Set status block DMA address */
7136         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7137              ((u64) tnapi->status_mapping >> 32));
7138         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7139              ((u64) tnapi->status_mapping & 0xffffffff));
7140
7141         if (tnapi->tx_ring) {
7142                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7143                                (TG3_TX_RING_SIZE <<
7144                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7145                                NIC_SRAM_TX_BUFFER_DESC);
7146                 txrcb += TG3_BDINFO_SIZE;
7147         }
7148
7149         if (tnapi->rx_rcb) {
7150                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7151                                (TG3_RX_RCB_RING_SIZE(tp) <<
7152                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7153                 rxrcb += TG3_BDINFO_SIZE;
7154         }
7155
7156         stblk = HOSTCC_STATBLCK_RING1;
7157
7158         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7159                 u64 mapping = (u64)tnapi->status_mapping;
7160                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7161                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7162
7163                 /* Clear status block in ram. */
7164                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7165
7166                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7167                                (TG3_TX_RING_SIZE <<
7168                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7169                                NIC_SRAM_TX_BUFFER_DESC);
7170
7171                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7172                                (TG3_RX_RCB_RING_SIZE(tp) <<
7173                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7174
7175                 stblk += 8;
7176                 txrcb += TG3_BDINFO_SIZE;
7177                 rxrcb += TG3_BDINFO_SIZE;
7178         }
7179 }
7180
7181 /* tp->lock is held. */
7182 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7183 {
7184         u32 val, rdmac_mode;
7185         int i, err, limit;
7186         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7187
7188         tg3_disable_ints(tp);
7189
7190         tg3_stop_fw(tp);
7191
7192         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7193
7194         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7195                 tg3_abort_hw(tp, 1);
7196         }
7197
7198         if (reset_phy &&
7199             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7200                 tg3_phy_reset(tp);
7201
7202         err = tg3_chip_reset(tp);
7203         if (err)
7204                 return err;
7205
7206         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7207
7208         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7209                 val = tr32(TG3_CPMU_CTRL);
7210                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7211                 tw32(TG3_CPMU_CTRL, val);
7212
7213                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7214                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7215                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7216                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7217
7218                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7219                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7220                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7221                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7222
7223                 val = tr32(TG3_CPMU_HST_ACC);
7224                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7225                 val |= CPMU_HST_ACC_MACCLK_6_25;
7226                 tw32(TG3_CPMU_HST_ACC, val);
7227         }
7228
7229         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7230                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7231                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7232                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7233                 tw32(PCIE_PWR_MGMT_THRESH, val);
7234
7235                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7236                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7237
7238                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7239
7240                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7241                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7242         }
7243
7244         /* This works around an issue with Athlon chipsets on
7245          * B3 tigon3 silicon.  This bit has no effect on any
7246          * other revision.  But do not set this on PCI Express
7247          * chips and don't even touch the clocks if the CPMU is present.
7248          */
7249         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7250                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7251                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7252                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7253         }
7254
7255         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7256             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7257                 val = tr32(TG3PCI_PCISTATE);
7258                 val |= PCISTATE_RETRY_SAME_DMA;
7259                 tw32(TG3PCI_PCISTATE, val);
7260         }
7261
7262         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7263                 /* Allow reads and writes to the
7264                  * APE register and memory space.
7265                  */
7266                 val = tr32(TG3PCI_PCISTATE);
7267                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7268                        PCISTATE_ALLOW_APE_SHMEM_WR;
7269                 tw32(TG3PCI_PCISTATE, val);
7270         }
7271
7272         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7273                 /* Enable some hw fixes.  */
7274                 val = tr32(TG3PCI_MSI_DATA);
7275                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7276                 tw32(TG3PCI_MSI_DATA, val);
7277         }
7278
7279         /* Descriptor ring init may make accesses to the
7280          * NIC SRAM area to setup the TX descriptors, so we
7281          * can only do this after the hardware has been
7282          * successfully reset.
7283          */
7284         err = tg3_init_rings(tp);
7285         if (err)
7286                 return err;
7287
7288         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7289             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7290             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7291                 /* This value is determined during the probe time DMA
7292                  * engine test, tg3_test_dma.
7293                  */
7294                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7295         }
7296
7297         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7298                           GRC_MODE_4X_NIC_SEND_RINGS |
7299                           GRC_MODE_NO_TX_PHDR_CSUM |
7300                           GRC_MODE_NO_RX_PHDR_CSUM);
7301         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7302
7303         /* Pseudo-header checksum is done by hardware logic and not
7304          * the offload processers, so make the chip do the pseudo-
7305          * header checksums on receive.  For transmit it is more
7306          * convenient to do the pseudo-header checksum in software
7307          * as Linux does that on transmit for us in all cases.
7308          */
7309         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7310
7311         tw32(GRC_MODE,
7312              tp->grc_mode |
7313              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7314
7315         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7316         val = tr32(GRC_MISC_CFG);
7317         val &= ~0xff;
7318         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7319         tw32(GRC_MISC_CFG, val);
7320
7321         /* Initialize MBUF/DESC pool. */
7322         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7323                 /* Do nothing.  */
7324         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7325                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7326                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7327                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7328                 else
7329                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7330                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7331                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7332         }
7333         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7334                 int fw_len;
7335
7336                 fw_len = tp->fw_len;
7337                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7338                 tw32(BUFMGR_MB_POOL_ADDR,
7339                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7340                 tw32(BUFMGR_MB_POOL_SIZE,
7341                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7342         }
7343
7344         if (tp->dev->mtu <= ETH_DATA_LEN) {
7345                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7346                      tp->bufmgr_config.mbuf_read_dma_low_water);
7347                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7348                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7349                 tw32(BUFMGR_MB_HIGH_WATER,
7350                      tp->bufmgr_config.mbuf_high_water);
7351         } else {
7352                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7353                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7354                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7355                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7356                 tw32(BUFMGR_MB_HIGH_WATER,
7357                      tp->bufmgr_config.mbuf_high_water_jumbo);
7358         }
7359         tw32(BUFMGR_DMA_LOW_WATER,
7360              tp->bufmgr_config.dma_low_water);
7361         tw32(BUFMGR_DMA_HIGH_WATER,
7362              tp->bufmgr_config.dma_high_water);
7363
7364         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7365         for (i = 0; i < 2000; i++) {
7366                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7367                         break;
7368                 udelay(10);
7369         }
7370         if (i >= 2000) {
7371                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7372                        tp->dev->name);
7373                 return -ENODEV;
7374         }
7375
7376         /* Setup replenish threshold. */
7377         val = tp->rx_pending / 8;
7378         if (val == 0)
7379                 val = 1;
7380         else if (val > tp->rx_std_max_post)
7381                 val = tp->rx_std_max_post;
7382         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7383                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7384                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7385
7386                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7387                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7388         }
7389
7390         tw32(RCVBDI_STD_THRESH, val);
7391
7392         /* Initialize TG3_BDINFO's at:
7393          *  RCVDBDI_STD_BD:     standard eth size rx ring
7394          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7395          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7396          *
7397          * like so:
7398          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7399          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7400          *                              ring attribute flags
7401          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7402          *
7403          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7404          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7405          *
7406          * The size of each ring is fixed in the firmware, but the location is
7407          * configurable.
7408          */
7409         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7410              ((u64) tpr->rx_std_mapping >> 32));
7411         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7412              ((u64) tpr->rx_std_mapping & 0xffffffff));
7413         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7414                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7415                      NIC_SRAM_RX_BUFFER_DESC);
7416
7417         /* Disable the mini ring */
7418         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7419                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7420                      BDINFO_FLAGS_DISABLED);
7421
7422         /* Program the jumbo buffer descriptor ring control
7423          * blocks on those devices that have them.
7424          */
7425         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7426             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7427                 /* Setup replenish threshold. */
7428                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7429
7430                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7431                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7432                              ((u64) tpr->rx_jmb_mapping >> 32));
7433                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7434                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7435                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7436                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7437                              BDINFO_FLAGS_USE_EXT_RECV);
7438                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7439                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7440                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7441                 } else {
7442                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7443                              BDINFO_FLAGS_DISABLED);
7444                 }
7445
7446                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7447                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7448                               (RX_STD_MAX_SIZE << 2);
7449                 else
7450                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7451         } else
7452                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7453
7454         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7455
7456         tpr->rx_std_ptr = tp->rx_pending;
7457         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7458                      tpr->rx_std_ptr);
7459
7460         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7461                           tp->rx_jumbo_pending : 0;
7462         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7463                      tpr->rx_jmb_ptr);
7464
7465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7466                 tw32(STD_REPLENISH_LWM, 32);
7467                 tw32(JMB_REPLENISH_LWM, 16);
7468         }
7469
7470         tg3_rings_reset(tp);
7471
7472         /* Initialize MAC address and backoff seed. */
7473         __tg3_set_mac_addr(tp, 0);
7474
7475         /* MTU + ethernet header + FCS + optional VLAN tag */
7476         tw32(MAC_RX_MTU_SIZE,
7477              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7478
7479         /* The slot time is changed by tg3_setup_phy if we
7480          * run at gigabit with half duplex.
7481          */
7482         tw32(MAC_TX_LENGTHS,
7483              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7484              (6 << TX_LENGTHS_IPG_SHIFT) |
7485              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7486
7487         /* Receive rules. */
7488         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7489         tw32(RCVLPC_CONFIG, 0x0181);
7490
7491         /* Calculate RDMAC_MODE setting early, we need it to determine
7492          * the RCVLPC_STATE_ENABLE mask.
7493          */
7494         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7495                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7496                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7497                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7498                       RDMAC_MODE_LNGREAD_ENAB);
7499
7500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7501             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7502             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7503                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7504                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7505                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7506
7507         /* If statement applies to 5705 and 5750 PCI devices only */
7508         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7509              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7510             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7511                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7512                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7513                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7514                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7515                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7516                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7517                 }
7518         }
7519
7520         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7521                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7522
7523         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7524                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7525
7526         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7527             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7528                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7529
7530         /* Receive/send statistics. */
7531         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7532                 val = tr32(RCVLPC_STATS_ENABLE);
7533                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7534                 tw32(RCVLPC_STATS_ENABLE, val);
7535         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7536                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7537                 val = tr32(RCVLPC_STATS_ENABLE);
7538                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7539                 tw32(RCVLPC_STATS_ENABLE, val);
7540         } else {
7541                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7542         }
7543         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7544         tw32(SNDDATAI_STATSENAB, 0xffffff);
7545         tw32(SNDDATAI_STATSCTRL,
7546              (SNDDATAI_SCTRL_ENABLE |
7547               SNDDATAI_SCTRL_FASTUPD));
7548
7549         /* Setup host coalescing engine. */
7550         tw32(HOSTCC_MODE, 0);
7551         for (i = 0; i < 2000; i++) {
7552                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7553                         break;
7554                 udelay(10);
7555         }
7556
7557         __tg3_set_coalesce(tp, &tp->coal);
7558
7559         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7560                 /* Status/statistics block address.  See tg3_timer,
7561                  * the tg3_periodic_fetch_stats call there, and
7562                  * tg3_get_stats to see how this works for 5705/5750 chips.
7563                  */
7564                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7565                      ((u64) tp->stats_mapping >> 32));
7566                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7567                      ((u64) tp->stats_mapping & 0xffffffff));
7568                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7569
7570                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7571
7572                 /* Clear statistics and status block memory areas */
7573                 for (i = NIC_SRAM_STATS_BLK;
7574                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7575                      i += sizeof(u32)) {
7576                         tg3_write_mem(tp, i, 0);
7577                         udelay(40);
7578                 }
7579         }
7580
7581         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7582
7583         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7584         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7585         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7586                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7587
7588         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7589                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7590                 /* reset to prevent losing 1st rx packet intermittently */
7591                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7592                 udelay(10);
7593         }
7594
7595         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7596                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7597         else
7598                 tp->mac_mode = 0;
7599         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7600                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7601         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7602             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7603             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7604                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7605         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7606         udelay(40);
7607
7608         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7609          * If TG3_FLG2_IS_NIC is zero, we should read the
7610          * register to preserve the GPIO settings for LOMs. The GPIOs,
7611          * whether used as inputs or outputs, are set by boot code after
7612          * reset.
7613          */
7614         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7615                 u32 gpio_mask;
7616
7617                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7618                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7619                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7620
7621                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7622                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7623                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7624
7625                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7626                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7627
7628                 tp->grc_local_ctrl &= ~gpio_mask;
7629                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7630
7631                 /* GPIO1 must be driven high for eeprom write protect */
7632                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7633                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7634                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7635         }
7636         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7637         udelay(100);
7638
7639         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7640                 val = tr32(MSGINT_MODE);
7641                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7642                 tw32(MSGINT_MODE, val);
7643         }
7644
7645         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7646                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7647                 udelay(40);
7648         }
7649
7650         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7651                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7652                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7653                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7654                WDMAC_MODE_LNGREAD_ENAB);
7655
7656         /* If statement applies to 5705 and 5750 PCI devices only */
7657         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7658              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7659             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7660                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7661                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7662                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7663                         /* nothing */
7664                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7665                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7666                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7667                         val |= WDMAC_MODE_RX_ACCEL;
7668                 }
7669         }
7670
7671         /* Enable host coalescing bug fix */
7672         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7673                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7674
7675         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7676                 val |= WDMAC_MODE_BURST_ALL_DATA;
7677
7678         tw32_f(WDMAC_MODE, val);
7679         udelay(40);
7680
7681         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7682                 u16 pcix_cmd;
7683
7684                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7685                                      &pcix_cmd);
7686                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7687                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7688                         pcix_cmd |= PCI_X_CMD_READ_2K;
7689                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7690                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7691                         pcix_cmd |= PCI_X_CMD_READ_2K;
7692                 }
7693                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7694                                       pcix_cmd);
7695         }
7696
7697         tw32_f(RDMAC_MODE, rdmac_mode);
7698         udelay(40);
7699
7700         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7701         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7702                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7703
7704         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7705                 tw32(SNDDATAC_MODE,
7706                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7707         else
7708                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7709
7710         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7711         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7712         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7713         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7714         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7715                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7716         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7717         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7718                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7719         tw32(SNDBDI_MODE, val);
7720         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7721
7722         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7723                 err = tg3_load_5701_a0_firmware_fix(tp);
7724                 if (err)
7725                         return err;
7726         }
7727
7728         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7729                 err = tg3_load_tso_firmware(tp);
7730                 if (err)
7731                         return err;
7732         }
7733
7734         tp->tx_mode = TX_MODE_ENABLE;
7735         tw32_f(MAC_TX_MODE, tp->tx_mode);
7736         udelay(100);
7737
7738         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7739                 u32 reg = MAC_RSS_INDIR_TBL_0;
7740                 u8 *ent = (u8 *)&val;
7741
7742                 /* Setup the indirection table */
7743                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7744                         int idx = i % sizeof(val);
7745
7746                         ent[idx] = i % (tp->irq_cnt - 1);
7747                         if (idx == sizeof(val) - 1) {
7748                                 tw32(reg, val);
7749                                 reg += 4;
7750                         }
7751                 }
7752
7753                 /* Setup the "secret" hash key. */
7754                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7755                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7756                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7757                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7758                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7759                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7760                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7761                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7762                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7763                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7764         }
7765
7766         tp->rx_mode = RX_MODE_ENABLE;
7767         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7768                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7769
7770         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7771                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7772                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7773                                RX_MODE_RSS_IPV6_HASH_EN |
7774                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7775                                RX_MODE_RSS_IPV4_HASH_EN |
7776                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7777
7778         tw32_f(MAC_RX_MODE, tp->rx_mode);
7779         udelay(10);
7780
7781         tw32(MAC_LED_CTRL, tp->led_ctrl);
7782
7783         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7784         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7785                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7786                 udelay(10);
7787         }
7788         tw32_f(MAC_RX_MODE, tp->rx_mode);
7789         udelay(10);
7790
7791         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7792                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7793                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7794                         /* Set drive transmission level to 1.2V  */
7795                         /* only if the signal pre-emphasis bit is not set  */
7796                         val = tr32(MAC_SERDES_CFG);
7797                         val &= 0xfffff000;
7798                         val |= 0x880;
7799                         tw32(MAC_SERDES_CFG, val);
7800                 }
7801                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7802                         tw32(MAC_SERDES_CFG, 0x616000);
7803         }
7804
7805         /* Prevent chip from dropping frames when flow control
7806          * is enabled.
7807          */
7808         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7809
7810         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7811             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7812                 /* Use hardware link auto-negotiation */
7813                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7814         }
7815
7816         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7817             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7818                 u32 tmp;
7819
7820                 tmp = tr32(SERDES_RX_CTRL);
7821                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7822                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7823                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7824                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7825         }
7826
7827         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7828                 if (tp->link_config.phy_is_low_power) {
7829                         tp->link_config.phy_is_low_power = 0;
7830                         tp->link_config.speed = tp->link_config.orig_speed;
7831                         tp->link_config.duplex = tp->link_config.orig_duplex;
7832                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7833                 }
7834
7835                 err = tg3_setup_phy(tp, 0);
7836                 if (err)
7837                         return err;
7838
7839                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7840                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7841                         u32 tmp;
7842
7843                         /* Clear CRC stats. */
7844                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7845                                 tg3_writephy(tp, MII_TG3_TEST1,
7846                                              tmp | MII_TG3_TEST1_CRC_EN);
7847                                 tg3_readphy(tp, 0x14, &tmp);
7848                         }
7849                 }
7850         }
7851
7852         __tg3_set_rx_mode(tp->dev);
7853
7854         /* Initialize receive rules. */
7855         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7856         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7857         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7858         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7859
7860         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7861             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7862                 limit = 8;
7863         else
7864                 limit = 16;
7865         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7866                 limit -= 4;
7867         switch (limit) {
7868         case 16:
7869                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7870         case 15:
7871                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7872         case 14:
7873                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7874         case 13:
7875                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7876         case 12:
7877                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7878         case 11:
7879                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7880         case 10:
7881                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7882         case 9:
7883                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7884         case 8:
7885                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7886         case 7:
7887                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7888         case 6:
7889                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7890         case 5:
7891                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7892         case 4:
7893                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7894         case 3:
7895                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7896         case 2:
7897         case 1:
7898
7899         default:
7900                 break;
7901         }
7902
7903         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7904                 /* Write our heartbeat update interval to APE. */
7905                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7906                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7907
7908         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7909
7910         return 0;
7911 }
7912
7913 /* Called at device open time to get the chip ready for
7914  * packet processing.  Invoked with tp->lock held.
7915  */
7916 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7917 {
7918         tg3_switch_clocks(tp);
7919
7920         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7921
7922         return tg3_reset_hw(tp, reset_phy);
7923 }
7924
7925 #define TG3_STAT_ADD32(PSTAT, REG) \
7926 do {    u32 __val = tr32(REG); \
7927         (PSTAT)->low += __val; \
7928         if ((PSTAT)->low < __val) \
7929                 (PSTAT)->high += 1; \
7930 } while (0)
7931
7932 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7933 {
7934         struct tg3_hw_stats *sp = tp->hw_stats;
7935
7936         if (!netif_carrier_ok(tp->dev))
7937                 return;
7938
7939         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7940         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7941         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7942         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7943         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7944         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7945         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7946         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7947         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7948         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7949         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7950         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7951         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7952
7953         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7954         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7955         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7956         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7957         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7958         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7959         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7960         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7961         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7962         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7963         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7964         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7965         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7966         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7967
7968         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7969         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7970         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7971 }
7972
7973 static void tg3_timer(unsigned long __opaque)
7974 {
7975         struct tg3 *tp = (struct tg3 *) __opaque;
7976
7977         if (tp->irq_sync)
7978                 goto restart_timer;
7979
7980         spin_lock(&tp->lock);
7981
7982         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7983                 /* All of this garbage is because when using non-tagged
7984                  * IRQ status the mailbox/status_block protocol the chip
7985                  * uses with the cpu is race prone.
7986                  */
7987                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7988                         tw32(GRC_LOCAL_CTRL,
7989                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7990                 } else {
7991                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7992                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7993                 }
7994
7995                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7996                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7997                         spin_unlock(&tp->lock);
7998                         schedule_work(&tp->reset_task);
7999                         return;
8000                 }
8001         }
8002
8003         /* This part only runs once per second. */
8004         if (!--tp->timer_counter) {
8005                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8006                         tg3_periodic_fetch_stats(tp);
8007
8008                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8009                         u32 mac_stat;
8010                         int phy_event;
8011
8012                         mac_stat = tr32(MAC_STATUS);
8013
8014                         phy_event = 0;
8015                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8016                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8017                                         phy_event = 1;
8018                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8019                                 phy_event = 1;
8020
8021                         if (phy_event)
8022                                 tg3_setup_phy(tp, 0);
8023                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8024                         u32 mac_stat = tr32(MAC_STATUS);
8025                         int need_setup = 0;
8026
8027                         if (netif_carrier_ok(tp->dev) &&
8028                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8029                                 need_setup = 1;
8030                         }
8031                         if (! netif_carrier_ok(tp->dev) &&
8032                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8033                                          MAC_STATUS_SIGNAL_DET))) {
8034                                 need_setup = 1;
8035                         }
8036                         if (need_setup) {
8037                                 if (!tp->serdes_counter) {
8038                                         tw32_f(MAC_MODE,
8039                                              (tp->mac_mode &
8040                                               ~MAC_MODE_PORT_MODE_MASK));
8041                                         udelay(40);
8042                                         tw32_f(MAC_MODE, tp->mac_mode);
8043                                         udelay(40);
8044                                 }
8045                                 tg3_setup_phy(tp, 0);
8046                         }
8047                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8048                         tg3_serdes_parallel_detect(tp);
8049
8050                 tp->timer_counter = tp->timer_multiplier;
8051         }
8052
8053         /* Heartbeat is only sent once every 2 seconds.
8054          *
8055          * The heartbeat is to tell the ASF firmware that the host
8056          * driver is still alive.  In the event that the OS crashes,
8057          * ASF needs to reset the hardware to free up the FIFO space
8058          * that may be filled with rx packets destined for the host.
8059          * If the FIFO is full, ASF will no longer function properly.
8060          *
8061          * Unintended resets have been reported on real time kernels
8062          * where the timer doesn't run on time.  Netpoll will also have
8063          * same problem.
8064          *
8065          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8066          * to check the ring condition when the heartbeat is expiring
8067          * before doing the reset.  This will prevent most unintended
8068          * resets.
8069          */
8070         if (!--tp->asf_counter) {
8071                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8072                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8073                         tg3_wait_for_event_ack(tp);
8074
8075                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8076                                       FWCMD_NICDRV_ALIVE3);
8077                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8078                         /* 5 seconds timeout */
8079                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8080
8081                         tg3_generate_fw_event(tp);
8082                 }
8083                 tp->asf_counter = tp->asf_multiplier;
8084         }
8085
8086         spin_unlock(&tp->lock);
8087
8088 restart_timer:
8089         tp->timer.expires = jiffies + tp->timer_offset;
8090         add_timer(&tp->timer);
8091 }
8092
8093 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8094 {
8095         irq_handler_t fn;
8096         unsigned long flags;
8097         char *name;
8098         struct tg3_napi *tnapi = &tp->napi[irq_num];
8099
8100         if (tp->irq_cnt == 1)
8101                 name = tp->dev->name;
8102         else {
8103                 name = &tnapi->irq_lbl[0];
8104                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8105                 name[IFNAMSIZ-1] = 0;
8106         }
8107
8108         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8109                 fn = tg3_msi;
8110                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8111                         fn = tg3_msi_1shot;
8112                 flags = IRQF_SAMPLE_RANDOM;
8113         } else {
8114                 fn = tg3_interrupt;
8115                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8116                         fn = tg3_interrupt_tagged;
8117                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8118         }
8119
8120         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8121 }
8122
8123 static int tg3_test_interrupt(struct tg3 *tp)
8124 {
8125         struct tg3_napi *tnapi = &tp->napi[0];
8126         struct net_device *dev = tp->dev;
8127         int err, i, intr_ok = 0;
8128         u32 val;
8129
8130         if (!netif_running(dev))
8131                 return -ENODEV;
8132
8133         tg3_disable_ints(tp);
8134
8135         free_irq(tnapi->irq_vec, tnapi);
8136
8137         /*
8138          * Turn off MSI one shot mode.  Otherwise this test has no
8139          * observable way to know whether the interrupt was delivered.
8140          */
8141         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8142             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8143                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8144                 tw32(MSGINT_MODE, val);
8145         }
8146
8147         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8148                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8149         if (err)
8150                 return err;
8151
8152         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8153         tg3_enable_ints(tp);
8154
8155         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8156                tnapi->coal_now);
8157
8158         for (i = 0; i < 5; i++) {
8159                 u32 int_mbox, misc_host_ctrl;
8160
8161                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8162                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8163
8164                 if ((int_mbox != 0) ||
8165                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8166                         intr_ok = 1;
8167                         break;
8168                 }
8169
8170                 msleep(10);
8171         }
8172
8173         tg3_disable_ints(tp);
8174
8175         free_irq(tnapi->irq_vec, tnapi);
8176
8177         err = tg3_request_irq(tp, 0);
8178
8179         if (err)
8180                 return err;
8181
8182         if (intr_ok) {
8183                 /* Reenable MSI one shot mode. */
8184                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8185                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8186                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8187                         tw32(MSGINT_MODE, val);
8188                 }
8189                 return 0;
8190         }
8191
8192         return -EIO;
8193 }
8194
8195 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8196  * successfully restored
8197  */
8198 static int tg3_test_msi(struct tg3 *tp)
8199 {
8200         int err;
8201         u16 pci_cmd;
8202
8203         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8204                 return 0;
8205
8206         /* Turn off SERR reporting in case MSI terminates with Master
8207          * Abort.
8208          */
8209         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8210         pci_write_config_word(tp->pdev, PCI_COMMAND,
8211                               pci_cmd & ~PCI_COMMAND_SERR);
8212
8213         err = tg3_test_interrupt(tp);
8214
8215         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8216
8217         if (!err)
8218                 return 0;
8219
8220         /* other failures */
8221         if (err != -EIO)
8222                 return err;
8223
8224         /* MSI test failed, go back to INTx mode */
8225         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8226                "switching to INTx mode. Please report this failure to "
8227                "the PCI maintainer and include system chipset information.\n",
8228                        tp->dev->name);
8229
8230         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8231
8232         pci_disable_msi(tp->pdev);
8233
8234         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8235
8236         err = tg3_request_irq(tp, 0);
8237         if (err)
8238                 return err;
8239
8240         /* Need to reset the chip because the MSI cycle may have terminated
8241          * with Master Abort.
8242          */
8243         tg3_full_lock(tp, 1);
8244
8245         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8246         err = tg3_init_hw(tp, 1);
8247
8248         tg3_full_unlock(tp);
8249
8250         if (err)
8251                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8252
8253         return err;
8254 }
8255
8256 static int tg3_request_firmware(struct tg3 *tp)
8257 {
8258         const __be32 *fw_data;
8259
8260         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8261                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8262                        tp->dev->name, tp->fw_needed);
8263                 return -ENOENT;
8264         }
8265
8266         fw_data = (void *)tp->fw->data;
8267
8268         /* Firmware blob starts with version numbers, followed by
8269          * start address and _full_ length including BSS sections
8270          * (which must be longer than the actual data, of course
8271          */
8272
8273         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8274         if (tp->fw_len < (tp->fw->size - 12)) {
8275                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8276                        tp->dev->name, tp->fw_len, tp->fw_needed);
8277                 release_firmware(tp->fw);
8278                 tp->fw = NULL;
8279                 return -EINVAL;
8280         }
8281
8282         /* We no longer need firmware; we have it. */
8283         tp->fw_needed = NULL;
8284         return 0;
8285 }
8286
8287 static bool tg3_enable_msix(struct tg3 *tp)
8288 {
8289         int i, rc, cpus = num_online_cpus();
8290         struct msix_entry msix_ent[tp->irq_max];
8291
8292         if (cpus == 1)
8293                 /* Just fallback to the simpler MSI mode. */
8294                 return false;
8295
8296         /*
8297          * We want as many rx rings enabled as there are cpus.
8298          * The first MSIX vector only deals with link interrupts, etc,
8299          * so we add one to the number of vectors we are requesting.
8300          */
8301         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8302
8303         for (i = 0; i < tp->irq_max; i++) {
8304                 msix_ent[i].entry  = i;
8305                 msix_ent[i].vector = 0;
8306         }
8307
8308         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8309         if (rc != 0) {
8310                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8311                         return false;
8312                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8313                         return false;
8314                 printk(KERN_NOTICE
8315                        "%s: Requested %d MSI-X vectors, received %d\n",
8316                        tp->dev->name, tp->irq_cnt, rc);
8317                 tp->irq_cnt = rc;
8318         }
8319
8320         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8321
8322         for (i = 0; i < tp->irq_max; i++)
8323                 tp->napi[i].irq_vec = msix_ent[i].vector;
8324
8325         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8326
8327         return true;
8328 }
8329
8330 static void tg3_ints_init(struct tg3 *tp)
8331 {
8332         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8333             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8334                 /* All MSI supporting chips should support tagged
8335                  * status.  Assert that this is the case.
8336                  */
8337                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8338                        "Not using MSI.\n", tp->dev->name);
8339                 goto defcfg;
8340         }
8341
8342         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8343                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8344         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8345                  pci_enable_msi(tp->pdev) == 0)
8346                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8347
8348         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8349                 u32 msi_mode = tr32(MSGINT_MODE);
8350                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8351                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8352                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8353         }
8354 defcfg:
8355         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8356                 tp->irq_cnt = 1;
8357                 tp->napi[0].irq_vec = tp->pdev->irq;
8358                 tp->dev->real_num_tx_queues = 1;
8359         }
8360 }
8361
8362 static void tg3_ints_fini(struct tg3 *tp)
8363 {
8364         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8365                 pci_disable_msix(tp->pdev);
8366         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8367                 pci_disable_msi(tp->pdev);
8368         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8369         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8370 }
8371
8372 static int tg3_open(struct net_device *dev)
8373 {
8374         struct tg3 *tp = netdev_priv(dev);
8375         int i, err;
8376
8377         if (tp->fw_needed) {
8378                 err = tg3_request_firmware(tp);
8379                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8380                         if (err)
8381                                 return err;
8382                 } else if (err) {
8383                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8384                                tp->dev->name);
8385                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8386                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8387                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8388                                tp->dev->name);
8389                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8390                 }
8391         }
8392
8393         netif_carrier_off(tp->dev);
8394
8395         err = tg3_set_power_state(tp, PCI_D0);
8396         if (err)
8397                 return err;
8398
8399         tg3_full_lock(tp, 0);
8400
8401         tg3_disable_ints(tp);
8402         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8403
8404         tg3_full_unlock(tp);
8405
8406         /*
8407          * Setup interrupts first so we know how
8408          * many NAPI resources to allocate
8409          */
8410         tg3_ints_init(tp);
8411
8412         /* The placement of this call is tied
8413          * to the setup and use of Host TX descriptors.
8414          */
8415         err = tg3_alloc_consistent(tp);
8416         if (err)
8417                 goto err_out1;
8418
8419         tg3_napi_enable(tp);
8420
8421         for (i = 0; i < tp->irq_cnt; i++) {
8422                 struct tg3_napi *tnapi = &tp->napi[i];
8423                 err = tg3_request_irq(tp, i);
8424                 if (err) {
8425                         for (i--; i >= 0; i--)
8426                                 free_irq(tnapi->irq_vec, tnapi);
8427                         break;
8428                 }
8429         }
8430
8431         if (err)
8432                 goto err_out2;
8433
8434         tg3_full_lock(tp, 0);
8435
8436         err = tg3_init_hw(tp, 1);
8437         if (err) {
8438                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8439                 tg3_free_rings(tp);
8440         } else {
8441                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8442                         tp->timer_offset = HZ;
8443                 else
8444                         tp->timer_offset = HZ / 10;
8445
8446                 BUG_ON(tp->timer_offset > HZ);
8447                 tp->timer_counter = tp->timer_multiplier =
8448                         (HZ / tp->timer_offset);
8449                 tp->asf_counter = tp->asf_multiplier =
8450                         ((HZ / tp->timer_offset) * 2);
8451
8452                 init_timer(&tp->timer);
8453                 tp->timer.expires = jiffies + tp->timer_offset;
8454                 tp->timer.data = (unsigned long) tp;
8455                 tp->timer.function = tg3_timer;
8456         }
8457
8458         tg3_full_unlock(tp);
8459
8460         if (err)
8461                 goto err_out3;
8462
8463         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8464                 err = tg3_test_msi(tp);
8465
8466                 if (err) {
8467                         tg3_full_lock(tp, 0);
8468                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8469                         tg3_free_rings(tp);
8470                         tg3_full_unlock(tp);
8471
8472                         goto err_out2;
8473                 }
8474
8475                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8476                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8477                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8478                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8479
8480                         tw32(PCIE_TRANSACTION_CFG,
8481                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8482                 }
8483         }
8484
8485         tg3_phy_start(tp);
8486
8487         tg3_full_lock(tp, 0);
8488
8489         add_timer(&tp->timer);
8490         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8491         tg3_enable_ints(tp);
8492
8493         tg3_full_unlock(tp);
8494
8495         netif_tx_start_all_queues(dev);
8496
8497         return 0;
8498
8499 err_out3:
8500         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8501                 struct tg3_napi *tnapi = &tp->napi[i];
8502                 free_irq(tnapi->irq_vec, tnapi);
8503         }
8504
8505 err_out2:
8506         tg3_napi_disable(tp);
8507         tg3_free_consistent(tp);
8508
8509 err_out1:
8510         tg3_ints_fini(tp);
8511         return err;
8512 }
8513
8514 #if 0
8515 /*static*/ void tg3_dump_state(struct tg3 *tp)
8516 {
8517         u32 val32, val32_2, val32_3, val32_4, val32_5;
8518         u16 val16;
8519         int i;
8520         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8521
8522         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8523         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8524         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8525                val16, val32);
8526
8527         /* MAC block */
8528         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8529                tr32(MAC_MODE), tr32(MAC_STATUS));
8530         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8531                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8532         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8533                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8534         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8535                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8536
8537         /* Send data initiator control block */
8538         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8539                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8540         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8541                tr32(SNDDATAI_STATSCTRL));
8542
8543         /* Send data completion control block */
8544         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8545
8546         /* Send BD ring selector block */
8547         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8548                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8549
8550         /* Send BD initiator control block */
8551         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8552                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8553
8554         /* Send BD completion control block */
8555         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8556
8557         /* Receive list placement control block */
8558         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8559                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8560         printk("       RCVLPC_STATSCTRL[%08x]\n",
8561                tr32(RCVLPC_STATSCTRL));
8562
8563         /* Receive data and receive BD initiator control block */
8564         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8565                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8566
8567         /* Receive data completion control block */
8568         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8569                tr32(RCVDCC_MODE));
8570
8571         /* Receive BD initiator control block */
8572         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8573                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8574
8575         /* Receive BD completion control block */
8576         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8577                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8578
8579         /* Receive list selector control block */
8580         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8581                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8582
8583         /* Mbuf cluster free block */
8584         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8585                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8586
8587         /* Host coalescing control block */
8588         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8589                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8590         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8591                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8592                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8593         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8594                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8595                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8596         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8597                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8598         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8599                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8600
8601         /* Memory arbiter control block */
8602         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8603                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8604
8605         /* Buffer manager control block */
8606         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8607                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8608         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8609                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8610         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8611                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8612                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8613                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8614
8615         /* Read DMA control block */
8616         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8617                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8618
8619         /* Write DMA control block */
8620         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8621                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8622
8623         /* DMA completion block */
8624         printk("DEBUG: DMAC_MODE[%08x]\n",
8625                tr32(DMAC_MODE));
8626
8627         /* GRC block */
8628         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8629                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8630         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8631                tr32(GRC_LOCAL_CTRL));
8632
8633         /* TG3_BDINFOs */
8634         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8635                tr32(RCVDBDI_JUMBO_BD + 0x0),
8636                tr32(RCVDBDI_JUMBO_BD + 0x4),
8637                tr32(RCVDBDI_JUMBO_BD + 0x8),
8638                tr32(RCVDBDI_JUMBO_BD + 0xc));
8639         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8640                tr32(RCVDBDI_STD_BD + 0x0),
8641                tr32(RCVDBDI_STD_BD + 0x4),
8642                tr32(RCVDBDI_STD_BD + 0x8),
8643                tr32(RCVDBDI_STD_BD + 0xc));
8644         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8645                tr32(RCVDBDI_MINI_BD + 0x0),
8646                tr32(RCVDBDI_MINI_BD + 0x4),
8647                tr32(RCVDBDI_MINI_BD + 0x8),
8648                tr32(RCVDBDI_MINI_BD + 0xc));
8649
8650         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8651         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8652         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8653         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8654         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8655                val32, val32_2, val32_3, val32_4);
8656
8657         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8658         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8659         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8660         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8661         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8662                val32, val32_2, val32_3, val32_4);
8663
8664         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8665         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8666         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8667         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8668         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8669         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8670                val32, val32_2, val32_3, val32_4, val32_5);
8671
8672         /* SW status block */
8673         printk(KERN_DEBUG
8674          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8675                sblk->status,
8676                sblk->status_tag,
8677                sblk->rx_jumbo_consumer,
8678                sblk->rx_consumer,
8679                sblk->rx_mini_consumer,
8680                sblk->idx[0].rx_producer,
8681                sblk->idx[0].tx_consumer);
8682
8683         /* SW statistics block */
8684         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8685                ((u32 *)tp->hw_stats)[0],
8686                ((u32 *)tp->hw_stats)[1],
8687                ((u32 *)tp->hw_stats)[2],
8688                ((u32 *)tp->hw_stats)[3]);
8689
8690         /* Mailboxes */
8691         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8692                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8693                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8694                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8695                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8696
8697         /* NIC side send descriptors. */
8698         for (i = 0; i < 6; i++) {
8699                 unsigned long txd;
8700
8701                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8702                         + (i * sizeof(struct tg3_tx_buffer_desc));
8703                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8704                        i,
8705                        readl(txd + 0x0), readl(txd + 0x4),
8706                        readl(txd + 0x8), readl(txd + 0xc));
8707         }
8708
8709         /* NIC side RX descriptors. */
8710         for (i = 0; i < 6; i++) {
8711                 unsigned long rxd;
8712
8713                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8714                         + (i * sizeof(struct tg3_rx_buffer_desc));
8715                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8716                        i,
8717                        readl(rxd + 0x0), readl(rxd + 0x4),
8718                        readl(rxd + 0x8), readl(rxd + 0xc));
8719                 rxd += (4 * sizeof(u32));
8720                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8721                        i,
8722                        readl(rxd + 0x0), readl(rxd + 0x4),
8723                        readl(rxd + 0x8), readl(rxd + 0xc));
8724         }
8725
8726         for (i = 0; i < 6; i++) {
8727                 unsigned long rxd;
8728
8729                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8730                         + (i * sizeof(struct tg3_rx_buffer_desc));
8731                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8732                        i,
8733                        readl(rxd + 0x0), readl(rxd + 0x4),
8734                        readl(rxd + 0x8), readl(rxd + 0xc));
8735                 rxd += (4 * sizeof(u32));
8736                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8737                        i,
8738                        readl(rxd + 0x0), readl(rxd + 0x4),
8739                        readl(rxd + 0x8), readl(rxd + 0xc));
8740         }
8741 }
8742 #endif
8743
8744 static struct net_device_stats *tg3_get_stats(struct net_device *);
8745 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8746
8747 static int tg3_close(struct net_device *dev)
8748 {
8749         int i;
8750         struct tg3 *tp = netdev_priv(dev);
8751
8752         tg3_napi_disable(tp);
8753         cancel_work_sync(&tp->reset_task);
8754
8755         netif_tx_stop_all_queues(dev);
8756
8757         del_timer_sync(&tp->timer);
8758
8759         tg3_phy_stop(tp);
8760
8761         tg3_full_lock(tp, 1);
8762 #if 0
8763         tg3_dump_state(tp);
8764 #endif
8765
8766         tg3_disable_ints(tp);
8767
8768         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8769         tg3_free_rings(tp);
8770         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8771
8772         tg3_full_unlock(tp);
8773
8774         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8775                 struct tg3_napi *tnapi = &tp->napi[i];
8776                 free_irq(tnapi->irq_vec, tnapi);
8777         }
8778
8779         tg3_ints_fini(tp);
8780
8781         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8782                sizeof(tp->net_stats_prev));
8783         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8784                sizeof(tp->estats_prev));
8785
8786         tg3_free_consistent(tp);
8787
8788         tg3_set_power_state(tp, PCI_D3hot);
8789
8790         netif_carrier_off(tp->dev);
8791
8792         return 0;
8793 }
8794
8795 static inline unsigned long get_stat64(tg3_stat64_t *val)
8796 {
8797         unsigned long ret;
8798
8799 #if (BITS_PER_LONG == 32)
8800         ret = val->low;
8801 #else
8802         ret = ((u64)val->high << 32) | ((u64)val->low);
8803 #endif
8804         return ret;
8805 }
8806
8807 static inline u64 get_estat64(tg3_stat64_t *val)
8808 {
8809        return ((u64)val->high << 32) | ((u64)val->low);
8810 }
8811
8812 static unsigned long calc_crc_errors(struct tg3 *tp)
8813 {
8814         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8815
8816         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8817             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8818              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8819                 u32 val;
8820
8821                 spin_lock_bh(&tp->lock);
8822                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8823                         tg3_writephy(tp, MII_TG3_TEST1,
8824                                      val | MII_TG3_TEST1_CRC_EN);
8825                         tg3_readphy(tp, 0x14, &val);
8826                 } else
8827                         val = 0;
8828                 spin_unlock_bh(&tp->lock);
8829
8830                 tp->phy_crc_errors += val;
8831
8832                 return tp->phy_crc_errors;
8833         }
8834
8835         return get_stat64(&hw_stats->rx_fcs_errors);
8836 }
8837
8838 #define ESTAT_ADD(member) \
8839         estats->member =        old_estats->member + \
8840                                 get_estat64(&hw_stats->member)
8841
8842 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8843 {
8844         struct tg3_ethtool_stats *estats = &tp->estats;
8845         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8846         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8847
8848         if (!hw_stats)
8849                 return old_estats;
8850
8851         ESTAT_ADD(rx_octets);
8852         ESTAT_ADD(rx_fragments);
8853         ESTAT_ADD(rx_ucast_packets);
8854         ESTAT_ADD(rx_mcast_packets);
8855         ESTAT_ADD(rx_bcast_packets);
8856         ESTAT_ADD(rx_fcs_errors);
8857         ESTAT_ADD(rx_align_errors);
8858         ESTAT_ADD(rx_xon_pause_rcvd);
8859         ESTAT_ADD(rx_xoff_pause_rcvd);
8860         ESTAT_ADD(rx_mac_ctrl_rcvd);
8861         ESTAT_ADD(rx_xoff_entered);
8862         ESTAT_ADD(rx_frame_too_long_errors);
8863         ESTAT_ADD(rx_jabbers);
8864         ESTAT_ADD(rx_undersize_packets);
8865         ESTAT_ADD(rx_in_length_errors);
8866         ESTAT_ADD(rx_out_length_errors);
8867         ESTAT_ADD(rx_64_or_less_octet_packets);
8868         ESTAT_ADD(rx_65_to_127_octet_packets);
8869         ESTAT_ADD(rx_128_to_255_octet_packets);
8870         ESTAT_ADD(rx_256_to_511_octet_packets);
8871         ESTAT_ADD(rx_512_to_1023_octet_packets);
8872         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8873         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8874         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8875         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8876         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8877
8878         ESTAT_ADD(tx_octets);
8879         ESTAT_ADD(tx_collisions);
8880         ESTAT_ADD(tx_xon_sent);
8881         ESTAT_ADD(tx_xoff_sent);
8882         ESTAT_ADD(tx_flow_control);
8883         ESTAT_ADD(tx_mac_errors);
8884         ESTAT_ADD(tx_single_collisions);
8885         ESTAT_ADD(tx_mult_collisions);
8886         ESTAT_ADD(tx_deferred);
8887         ESTAT_ADD(tx_excessive_collisions);
8888         ESTAT_ADD(tx_late_collisions);
8889         ESTAT_ADD(tx_collide_2times);
8890         ESTAT_ADD(tx_collide_3times);
8891         ESTAT_ADD(tx_collide_4times);
8892         ESTAT_ADD(tx_collide_5times);
8893         ESTAT_ADD(tx_collide_6times);
8894         ESTAT_ADD(tx_collide_7times);
8895         ESTAT_ADD(tx_collide_8times);
8896         ESTAT_ADD(tx_collide_9times);
8897         ESTAT_ADD(tx_collide_10times);
8898         ESTAT_ADD(tx_collide_11times);
8899         ESTAT_ADD(tx_collide_12times);
8900         ESTAT_ADD(tx_collide_13times);
8901         ESTAT_ADD(tx_collide_14times);
8902         ESTAT_ADD(tx_collide_15times);
8903         ESTAT_ADD(tx_ucast_packets);
8904         ESTAT_ADD(tx_mcast_packets);
8905         ESTAT_ADD(tx_bcast_packets);
8906         ESTAT_ADD(tx_carrier_sense_errors);
8907         ESTAT_ADD(tx_discards);
8908         ESTAT_ADD(tx_errors);
8909
8910         ESTAT_ADD(dma_writeq_full);
8911         ESTAT_ADD(dma_write_prioq_full);
8912         ESTAT_ADD(rxbds_empty);
8913         ESTAT_ADD(rx_discards);
8914         ESTAT_ADD(rx_errors);
8915         ESTAT_ADD(rx_threshold_hit);
8916
8917         ESTAT_ADD(dma_readq_full);
8918         ESTAT_ADD(dma_read_prioq_full);
8919         ESTAT_ADD(tx_comp_queue_full);
8920
8921         ESTAT_ADD(ring_set_send_prod_index);
8922         ESTAT_ADD(ring_status_update);
8923         ESTAT_ADD(nic_irqs);
8924         ESTAT_ADD(nic_avoided_irqs);
8925         ESTAT_ADD(nic_tx_threshold_hit);
8926
8927         return estats;
8928 }
8929
8930 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8931 {
8932         struct tg3 *tp = netdev_priv(dev);
8933         struct net_device_stats *stats = &tp->net_stats;
8934         struct net_device_stats *old_stats = &tp->net_stats_prev;
8935         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8936
8937         if (!hw_stats)
8938                 return old_stats;
8939
8940         stats->rx_packets = old_stats->rx_packets +
8941                 get_stat64(&hw_stats->rx_ucast_packets) +
8942                 get_stat64(&hw_stats->rx_mcast_packets) +
8943                 get_stat64(&hw_stats->rx_bcast_packets);
8944
8945         stats->tx_packets = old_stats->tx_packets +
8946                 get_stat64(&hw_stats->tx_ucast_packets) +
8947                 get_stat64(&hw_stats->tx_mcast_packets) +
8948                 get_stat64(&hw_stats->tx_bcast_packets);
8949
8950         stats->rx_bytes = old_stats->rx_bytes +
8951                 get_stat64(&hw_stats->rx_octets);
8952         stats->tx_bytes = old_stats->tx_bytes +
8953                 get_stat64(&hw_stats->tx_octets);
8954
8955         stats->rx_errors = old_stats->rx_errors +
8956                 get_stat64(&hw_stats->rx_errors);
8957         stats->tx_errors = old_stats->tx_errors +
8958                 get_stat64(&hw_stats->tx_errors) +
8959                 get_stat64(&hw_stats->tx_mac_errors) +
8960                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8961                 get_stat64(&hw_stats->tx_discards);
8962
8963         stats->multicast = old_stats->multicast +
8964                 get_stat64(&hw_stats->rx_mcast_packets);
8965         stats->collisions = old_stats->collisions +
8966                 get_stat64(&hw_stats->tx_collisions);
8967
8968         stats->rx_length_errors = old_stats->rx_length_errors +
8969                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8970                 get_stat64(&hw_stats->rx_undersize_packets);
8971
8972         stats->rx_over_errors = old_stats->rx_over_errors +
8973                 get_stat64(&hw_stats->rxbds_empty);
8974         stats->rx_frame_errors = old_stats->rx_frame_errors +
8975                 get_stat64(&hw_stats->rx_align_errors);
8976         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8977                 get_stat64(&hw_stats->tx_discards);
8978         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8979                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8980
8981         stats->rx_crc_errors = old_stats->rx_crc_errors +
8982                 calc_crc_errors(tp);
8983
8984         stats->rx_missed_errors = old_stats->rx_missed_errors +
8985                 get_stat64(&hw_stats->rx_discards);
8986
8987         return stats;
8988 }
8989
8990 static inline u32 calc_crc(unsigned char *buf, int len)
8991 {
8992         u32 reg;
8993         u32 tmp;
8994         int j, k;
8995
8996         reg = 0xffffffff;
8997
8998         for (j = 0; j < len; j++) {
8999                 reg ^= buf[j];
9000
9001                 for (k = 0; k < 8; k++) {
9002                         tmp = reg & 0x01;
9003
9004                         reg >>= 1;
9005
9006                         if (tmp) {
9007                                 reg ^= 0xedb88320;
9008                         }
9009                 }
9010         }
9011
9012         return ~reg;
9013 }
9014
9015 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9016 {
9017         /* accept or reject all multicast frames */
9018         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9019         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9020         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9021         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9022 }
9023
9024 static void __tg3_set_rx_mode(struct net_device *dev)
9025 {
9026         struct tg3 *tp = netdev_priv(dev);
9027         u32 rx_mode;
9028
9029         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9030                                   RX_MODE_KEEP_VLAN_TAG);
9031
9032         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9033          * flag clear.
9034          */
9035 #if TG3_VLAN_TAG_USED
9036         if (!tp->vlgrp &&
9037             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9038                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9039 #else
9040         /* By definition, VLAN is disabled always in this
9041          * case.
9042          */
9043         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9044                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9045 #endif
9046
9047         if (dev->flags & IFF_PROMISC) {
9048                 /* Promiscuous mode. */
9049                 rx_mode |= RX_MODE_PROMISC;
9050         } else if (dev->flags & IFF_ALLMULTI) {
9051                 /* Accept all multicast. */
9052                 tg3_set_multi (tp, 1);
9053         } else if (dev->mc_count < 1) {
9054                 /* Reject all multicast. */
9055                 tg3_set_multi (tp, 0);
9056         } else {
9057                 /* Accept one or more multicast(s). */
9058                 struct dev_mc_list *mclist;
9059                 unsigned int i;
9060                 u32 mc_filter[4] = { 0, };
9061                 u32 regidx;
9062                 u32 bit;
9063                 u32 crc;
9064
9065                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9066                      i++, mclist = mclist->next) {
9067
9068                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9069                         bit = ~crc & 0x7f;
9070                         regidx = (bit & 0x60) >> 5;
9071                         bit &= 0x1f;
9072                         mc_filter[regidx] |= (1 << bit);
9073                 }
9074
9075                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9076                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9077                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9078                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9079         }
9080
9081         if (rx_mode != tp->rx_mode) {
9082                 tp->rx_mode = rx_mode;
9083                 tw32_f(MAC_RX_MODE, rx_mode);
9084                 udelay(10);
9085         }
9086 }
9087
9088 static void tg3_set_rx_mode(struct net_device *dev)
9089 {
9090         struct tg3 *tp = netdev_priv(dev);
9091
9092         if (!netif_running(dev))
9093                 return;
9094
9095         tg3_full_lock(tp, 0);
9096         __tg3_set_rx_mode(dev);
9097         tg3_full_unlock(tp);
9098 }
9099
9100 #define TG3_REGDUMP_LEN         (32 * 1024)
9101
9102 static int tg3_get_regs_len(struct net_device *dev)
9103 {
9104         return TG3_REGDUMP_LEN;
9105 }
9106
9107 static void tg3_get_regs(struct net_device *dev,
9108                 struct ethtool_regs *regs, void *_p)
9109 {
9110         u32 *p = _p;
9111         struct tg3 *tp = netdev_priv(dev);
9112         u8 *orig_p = _p;
9113         int i;
9114
9115         regs->version = 0;
9116
9117         memset(p, 0, TG3_REGDUMP_LEN);
9118
9119         if (tp->link_config.phy_is_low_power)
9120                 return;
9121
9122         tg3_full_lock(tp, 0);
9123
9124 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9125 #define GET_REG32_LOOP(base,len)                \
9126 do {    p = (u32 *)(orig_p + (base));           \
9127         for (i = 0; i < len; i += 4)            \
9128                 __GET_REG32((base) + i);        \
9129 } while (0)
9130 #define GET_REG32_1(reg)                        \
9131 do {    p = (u32 *)(orig_p + (reg));            \
9132         __GET_REG32((reg));                     \
9133 } while (0)
9134
9135         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9136         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9137         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9138         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9139         GET_REG32_1(SNDDATAC_MODE);
9140         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9141         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9142         GET_REG32_1(SNDBDC_MODE);
9143         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9144         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9145         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9146         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9147         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9148         GET_REG32_1(RCVDCC_MODE);
9149         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9150         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9151         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9152         GET_REG32_1(MBFREE_MODE);
9153         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9154         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9155         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9156         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9157         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9158         GET_REG32_1(RX_CPU_MODE);
9159         GET_REG32_1(RX_CPU_STATE);
9160         GET_REG32_1(RX_CPU_PGMCTR);
9161         GET_REG32_1(RX_CPU_HWBKPT);
9162         GET_REG32_1(TX_CPU_MODE);
9163         GET_REG32_1(TX_CPU_STATE);
9164         GET_REG32_1(TX_CPU_PGMCTR);
9165         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9166         GET_REG32_LOOP(FTQ_RESET, 0x120);
9167         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9168         GET_REG32_1(DMAC_MODE);
9169         GET_REG32_LOOP(GRC_MODE, 0x4c);
9170         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9171                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9172
9173 #undef __GET_REG32
9174 #undef GET_REG32_LOOP
9175 #undef GET_REG32_1
9176
9177         tg3_full_unlock(tp);
9178 }
9179
9180 static int tg3_get_eeprom_len(struct net_device *dev)
9181 {
9182         struct tg3 *tp = netdev_priv(dev);
9183
9184         return tp->nvram_size;
9185 }
9186
9187 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9188 {
9189         struct tg3 *tp = netdev_priv(dev);
9190         int ret;
9191         u8  *pd;
9192         u32 i, offset, len, b_offset, b_count;
9193         __be32 val;
9194
9195         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9196                 return -EINVAL;
9197
9198         if (tp->link_config.phy_is_low_power)
9199                 return -EAGAIN;
9200
9201         offset = eeprom->offset;
9202         len = eeprom->len;
9203         eeprom->len = 0;
9204
9205         eeprom->magic = TG3_EEPROM_MAGIC;
9206
9207         if (offset & 3) {
9208                 /* adjustments to start on required 4 byte boundary */
9209                 b_offset = offset & 3;
9210                 b_count = 4 - b_offset;
9211                 if (b_count > len) {
9212                         /* i.e. offset=1 len=2 */
9213                         b_count = len;
9214                 }
9215                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9216                 if (ret)
9217                         return ret;
9218                 memcpy(data, ((char*)&val) + b_offset, b_count);
9219                 len -= b_count;
9220                 offset += b_count;
9221                 eeprom->len += b_count;
9222         }
9223
9224         /* read bytes upto the last 4 byte boundary */
9225         pd = &data[eeprom->len];
9226         for (i = 0; i < (len - (len & 3)); i += 4) {
9227                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9228                 if (ret) {
9229                         eeprom->len += i;
9230                         return ret;
9231                 }
9232                 memcpy(pd + i, &val, 4);
9233         }
9234         eeprom->len += i;
9235
9236         if (len & 3) {
9237                 /* read last bytes not ending on 4 byte boundary */
9238                 pd = &data[eeprom->len];
9239                 b_count = len & 3;
9240                 b_offset = offset + len - b_count;
9241                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9242                 if (ret)
9243                         return ret;
9244                 memcpy(pd, &val, b_count);
9245                 eeprom->len += b_count;
9246         }
9247         return 0;
9248 }
9249
9250 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9251
9252 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9253 {
9254         struct tg3 *tp = netdev_priv(dev);
9255         int ret;
9256         u32 offset, len, b_offset, odd_len;
9257         u8 *buf;
9258         __be32 start, end;
9259
9260         if (tp->link_config.phy_is_low_power)
9261                 return -EAGAIN;
9262
9263         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9264             eeprom->magic != TG3_EEPROM_MAGIC)
9265                 return -EINVAL;
9266
9267         offset = eeprom->offset;
9268         len = eeprom->len;
9269
9270         if ((b_offset = (offset & 3))) {
9271                 /* adjustments to start on required 4 byte boundary */
9272                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9273                 if (ret)
9274                         return ret;
9275                 len += b_offset;
9276                 offset &= ~3;
9277                 if (len < 4)
9278                         len = 4;
9279         }
9280
9281         odd_len = 0;
9282         if (len & 3) {
9283                 /* adjustments to end on required 4 byte boundary */
9284                 odd_len = 1;
9285                 len = (len + 3) & ~3;
9286                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9287                 if (ret)
9288                         return ret;
9289         }
9290
9291         buf = data;
9292         if (b_offset || odd_len) {
9293                 buf = kmalloc(len, GFP_KERNEL);
9294                 if (!buf)
9295                         return -ENOMEM;
9296                 if (b_offset)
9297                         memcpy(buf, &start, 4);
9298                 if (odd_len)
9299                         memcpy(buf+len-4, &end, 4);
9300                 memcpy(buf + b_offset, data, eeprom->len);
9301         }
9302
9303         ret = tg3_nvram_write_block(tp, offset, len, buf);
9304
9305         if (buf != data)
9306                 kfree(buf);
9307
9308         return ret;
9309 }
9310
9311 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9312 {
9313         struct tg3 *tp = netdev_priv(dev);
9314
9315         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9316                 struct phy_device *phydev;
9317                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9318                         return -EAGAIN;
9319                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9320                 return phy_ethtool_gset(phydev, cmd);
9321         }
9322
9323         cmd->supported = (SUPPORTED_Autoneg);
9324
9325         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9326                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9327                                    SUPPORTED_1000baseT_Full);
9328
9329         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9330                 cmd->supported |= (SUPPORTED_100baseT_Half |
9331                                   SUPPORTED_100baseT_Full |
9332                                   SUPPORTED_10baseT_Half |
9333                                   SUPPORTED_10baseT_Full |
9334                                   SUPPORTED_TP);
9335                 cmd->port = PORT_TP;
9336         } else {
9337                 cmd->supported |= SUPPORTED_FIBRE;
9338                 cmd->port = PORT_FIBRE;
9339         }
9340
9341         cmd->advertising = tp->link_config.advertising;
9342         if (netif_running(dev)) {
9343                 cmd->speed = tp->link_config.active_speed;
9344                 cmd->duplex = tp->link_config.active_duplex;
9345         }
9346         cmd->phy_address = tp->phy_addr;
9347         cmd->transceiver = XCVR_INTERNAL;
9348         cmd->autoneg = tp->link_config.autoneg;
9349         cmd->maxtxpkt = 0;
9350         cmd->maxrxpkt = 0;
9351         return 0;
9352 }
9353
9354 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9355 {
9356         struct tg3 *tp = netdev_priv(dev);
9357
9358         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9359                 struct phy_device *phydev;
9360                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9361                         return -EAGAIN;
9362                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9363                 return phy_ethtool_sset(phydev, cmd);
9364         }
9365
9366         if (cmd->autoneg != AUTONEG_ENABLE &&
9367             cmd->autoneg != AUTONEG_DISABLE)
9368                 return -EINVAL;
9369
9370         if (cmd->autoneg == AUTONEG_DISABLE &&
9371             cmd->duplex != DUPLEX_FULL &&
9372             cmd->duplex != DUPLEX_HALF)
9373                 return -EINVAL;
9374
9375         if (cmd->autoneg == AUTONEG_ENABLE) {
9376                 u32 mask = ADVERTISED_Autoneg |
9377                            ADVERTISED_Pause |
9378                            ADVERTISED_Asym_Pause;
9379
9380                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9381                         mask |= ADVERTISED_1000baseT_Half |
9382                                 ADVERTISED_1000baseT_Full;
9383
9384                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9385                         mask |= ADVERTISED_100baseT_Half |
9386                                 ADVERTISED_100baseT_Full |
9387                                 ADVERTISED_10baseT_Half |
9388                                 ADVERTISED_10baseT_Full |
9389                                 ADVERTISED_TP;
9390                 else
9391                         mask |= ADVERTISED_FIBRE;
9392
9393                 if (cmd->advertising & ~mask)
9394                         return -EINVAL;
9395
9396                 mask &= (ADVERTISED_1000baseT_Half |
9397                          ADVERTISED_1000baseT_Full |
9398                          ADVERTISED_100baseT_Half |
9399                          ADVERTISED_100baseT_Full |
9400                          ADVERTISED_10baseT_Half |
9401                          ADVERTISED_10baseT_Full);
9402
9403                 cmd->advertising &= mask;
9404         } else {
9405                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9406                         if (cmd->speed != SPEED_1000)
9407                                 return -EINVAL;
9408
9409                         if (cmd->duplex != DUPLEX_FULL)
9410                                 return -EINVAL;
9411                 } else {
9412                         if (cmd->speed != SPEED_100 &&
9413                             cmd->speed != SPEED_10)
9414                                 return -EINVAL;
9415                 }
9416         }
9417
9418         tg3_full_lock(tp, 0);
9419
9420         tp->link_config.autoneg = cmd->autoneg;
9421         if (cmd->autoneg == AUTONEG_ENABLE) {
9422                 tp->link_config.advertising = (cmd->advertising |
9423                                               ADVERTISED_Autoneg);
9424                 tp->link_config.speed = SPEED_INVALID;
9425                 tp->link_config.duplex = DUPLEX_INVALID;
9426         } else {
9427                 tp->link_config.advertising = 0;
9428                 tp->link_config.speed = cmd->speed;
9429                 tp->link_config.duplex = cmd->duplex;
9430         }
9431
9432         tp->link_config.orig_speed = tp->link_config.speed;
9433         tp->link_config.orig_duplex = tp->link_config.duplex;
9434         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9435
9436         if (netif_running(dev))
9437                 tg3_setup_phy(tp, 1);
9438
9439         tg3_full_unlock(tp);
9440
9441         return 0;
9442 }
9443
9444 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9445 {
9446         struct tg3 *tp = netdev_priv(dev);
9447
9448         strcpy(info->driver, DRV_MODULE_NAME);
9449         strcpy(info->version, DRV_MODULE_VERSION);
9450         strcpy(info->fw_version, tp->fw_ver);
9451         strcpy(info->bus_info, pci_name(tp->pdev));
9452 }
9453
9454 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9455 {
9456         struct tg3 *tp = netdev_priv(dev);
9457
9458         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9459             device_can_wakeup(&tp->pdev->dev))
9460                 wol->supported = WAKE_MAGIC;
9461         else
9462                 wol->supported = 0;
9463         wol->wolopts = 0;
9464         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9465             device_can_wakeup(&tp->pdev->dev))
9466                 wol->wolopts = WAKE_MAGIC;
9467         memset(&wol->sopass, 0, sizeof(wol->sopass));
9468 }
9469
9470 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9471 {
9472         struct tg3 *tp = netdev_priv(dev);
9473         struct device *dp = &tp->pdev->dev;
9474
9475         if (wol->wolopts & ~WAKE_MAGIC)
9476                 return -EINVAL;
9477         if ((wol->wolopts & WAKE_MAGIC) &&
9478             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9479                 return -EINVAL;
9480
9481         spin_lock_bh(&tp->lock);
9482         if (wol->wolopts & WAKE_MAGIC) {
9483                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9484                 device_set_wakeup_enable(dp, true);
9485         } else {
9486                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9487                 device_set_wakeup_enable(dp, false);
9488         }
9489         spin_unlock_bh(&tp->lock);
9490
9491         return 0;
9492 }
9493
9494 static u32 tg3_get_msglevel(struct net_device *dev)
9495 {
9496         struct tg3 *tp = netdev_priv(dev);
9497         return tp->msg_enable;
9498 }
9499
9500 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9501 {
9502         struct tg3 *tp = netdev_priv(dev);
9503         tp->msg_enable = value;
9504 }
9505
9506 static int tg3_set_tso(struct net_device *dev, u32 value)
9507 {
9508         struct tg3 *tp = netdev_priv(dev);
9509
9510         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9511                 if (value)
9512                         return -EINVAL;
9513                 return 0;
9514         }
9515         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9516             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9517                 if (value) {
9518                         dev->features |= NETIF_F_TSO6;
9519                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9520                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9521                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9522                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9523                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9524                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9525                                 dev->features |= NETIF_F_TSO_ECN;
9526                 } else
9527                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9528         }
9529         return ethtool_op_set_tso(dev, value);
9530 }
9531
9532 static int tg3_nway_reset(struct net_device *dev)
9533 {
9534         struct tg3 *tp = netdev_priv(dev);
9535         int r;
9536
9537         if (!netif_running(dev))
9538                 return -EAGAIN;
9539
9540         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9541                 return -EINVAL;
9542
9543         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9544                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9545                         return -EAGAIN;
9546                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9547         } else {
9548                 u32 bmcr;
9549
9550                 spin_lock_bh(&tp->lock);
9551                 r = -EINVAL;
9552                 tg3_readphy(tp, MII_BMCR, &bmcr);
9553                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9554                     ((bmcr & BMCR_ANENABLE) ||
9555                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9556                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9557                                                    BMCR_ANENABLE);
9558                         r = 0;
9559                 }
9560                 spin_unlock_bh(&tp->lock);
9561         }
9562
9563         return r;
9564 }
9565
9566 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9567 {
9568         struct tg3 *tp = netdev_priv(dev);
9569
9570         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9571         ering->rx_mini_max_pending = 0;
9572         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9573                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9574         else
9575                 ering->rx_jumbo_max_pending = 0;
9576
9577         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9578
9579         ering->rx_pending = tp->rx_pending;
9580         ering->rx_mini_pending = 0;
9581         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9582                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9583         else
9584                 ering->rx_jumbo_pending = 0;
9585
9586         ering->tx_pending = tp->napi[0].tx_pending;
9587 }
9588
9589 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9590 {
9591         struct tg3 *tp = netdev_priv(dev);
9592         int i, irq_sync = 0, err = 0;
9593
9594         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9595             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9596             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9597             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9598             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9599              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9600                 return -EINVAL;
9601
9602         if (netif_running(dev)) {
9603                 tg3_phy_stop(tp);
9604                 tg3_netif_stop(tp);
9605                 irq_sync = 1;
9606         }
9607
9608         tg3_full_lock(tp, irq_sync);
9609
9610         tp->rx_pending = ering->rx_pending;
9611
9612         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9613             tp->rx_pending > 63)
9614                 tp->rx_pending = 63;
9615         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9616
9617         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9618                 tp->napi[i].tx_pending = ering->tx_pending;
9619
9620         if (netif_running(dev)) {
9621                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9622                 err = tg3_restart_hw(tp, 1);
9623                 if (!err)
9624                         tg3_netif_start(tp);
9625         }
9626
9627         tg3_full_unlock(tp);
9628
9629         if (irq_sync && !err)
9630                 tg3_phy_start(tp);
9631
9632         return err;
9633 }
9634
9635 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9636 {
9637         struct tg3 *tp = netdev_priv(dev);
9638
9639         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9640
9641         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9642                 epause->rx_pause = 1;
9643         else
9644                 epause->rx_pause = 0;
9645
9646         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9647                 epause->tx_pause = 1;
9648         else
9649                 epause->tx_pause = 0;
9650 }
9651
9652 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9653 {
9654         struct tg3 *tp = netdev_priv(dev);
9655         int err = 0;
9656
9657         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9658                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9659                         return -EAGAIN;
9660
9661                 if (epause->autoneg) {
9662                         u32 newadv;
9663                         struct phy_device *phydev;
9664
9665                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9666
9667                         if (epause->rx_pause) {
9668                                 if (epause->tx_pause)
9669                                         newadv = ADVERTISED_Pause;
9670                                 else
9671                                         newadv = ADVERTISED_Pause |
9672                                                  ADVERTISED_Asym_Pause;
9673                         } else if (epause->tx_pause) {
9674                                 newadv = ADVERTISED_Asym_Pause;
9675                         } else
9676                                 newadv = 0;
9677
9678                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9679                                 u32 oldadv = phydev->advertising &
9680                                              (ADVERTISED_Pause |
9681                                               ADVERTISED_Asym_Pause);
9682                                 if (oldadv != newadv) {
9683                                         phydev->advertising &=
9684                                                 ~(ADVERTISED_Pause |
9685                                                   ADVERTISED_Asym_Pause);
9686                                         phydev->advertising |= newadv;
9687                                         err = phy_start_aneg(phydev);
9688                                 }
9689                         } else {
9690                                 tp->link_config.advertising &=
9691                                                 ~(ADVERTISED_Pause |
9692                                                   ADVERTISED_Asym_Pause);
9693                                 tp->link_config.advertising |= newadv;
9694                         }
9695                 } else {
9696                         if (epause->rx_pause)
9697                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9698                         else
9699                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9700
9701                         if (epause->tx_pause)
9702                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9703                         else
9704                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9705
9706                         if (netif_running(dev))
9707                                 tg3_setup_flow_control(tp, 0, 0);
9708                 }
9709         } else {
9710                 int irq_sync = 0;
9711
9712                 if (netif_running(dev)) {
9713                         tg3_netif_stop(tp);
9714                         irq_sync = 1;
9715                 }
9716
9717                 tg3_full_lock(tp, irq_sync);
9718
9719                 if (epause->autoneg)
9720                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9721                 else
9722                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9723                 if (epause->rx_pause)
9724                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9725                 else
9726                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9727                 if (epause->tx_pause)
9728                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9729                 else
9730                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9731
9732                 if (netif_running(dev)) {
9733                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9734                         err = tg3_restart_hw(tp, 1);
9735                         if (!err)
9736                                 tg3_netif_start(tp);
9737                 }
9738
9739                 tg3_full_unlock(tp);
9740         }
9741
9742         return err;
9743 }
9744
9745 static u32 tg3_get_rx_csum(struct net_device *dev)
9746 {
9747         struct tg3 *tp = netdev_priv(dev);
9748         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9749 }
9750
9751 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9752 {
9753         struct tg3 *tp = netdev_priv(dev);
9754
9755         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9756                 if (data != 0)
9757                         return -EINVAL;
9758                 return 0;
9759         }
9760
9761         spin_lock_bh(&tp->lock);
9762         if (data)
9763                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9764         else
9765                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9766         spin_unlock_bh(&tp->lock);
9767
9768         return 0;
9769 }
9770
9771 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9772 {
9773         struct tg3 *tp = netdev_priv(dev);
9774
9775         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9776                 if (data != 0)
9777                         return -EINVAL;
9778                 return 0;
9779         }
9780
9781         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9782                 ethtool_op_set_tx_ipv6_csum(dev, data);
9783         else
9784                 ethtool_op_set_tx_csum(dev, data);
9785
9786         return 0;
9787 }
9788
9789 static int tg3_get_sset_count (struct net_device *dev, int sset)
9790 {
9791         switch (sset) {
9792         case ETH_SS_TEST:
9793                 return TG3_NUM_TEST;
9794         case ETH_SS_STATS:
9795                 return TG3_NUM_STATS;
9796         default:
9797                 return -EOPNOTSUPP;
9798         }
9799 }
9800
9801 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9802 {
9803         switch (stringset) {
9804         case ETH_SS_STATS:
9805                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9806                 break;
9807         case ETH_SS_TEST:
9808                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9809                 break;
9810         default:
9811                 WARN_ON(1);     /* we need a WARN() */
9812                 break;
9813         }
9814 }
9815
9816 static int tg3_phys_id(struct net_device *dev, u32 data)
9817 {
9818         struct tg3 *tp = netdev_priv(dev);
9819         int i;
9820
9821         if (!netif_running(tp->dev))
9822                 return -EAGAIN;
9823
9824         if (data == 0)
9825                 data = UINT_MAX / 2;
9826
9827         for (i = 0; i < (data * 2); i++) {
9828                 if ((i % 2) == 0)
9829                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9830                                            LED_CTRL_1000MBPS_ON |
9831                                            LED_CTRL_100MBPS_ON |
9832                                            LED_CTRL_10MBPS_ON |
9833                                            LED_CTRL_TRAFFIC_OVERRIDE |
9834                                            LED_CTRL_TRAFFIC_BLINK |
9835                                            LED_CTRL_TRAFFIC_LED);
9836
9837                 else
9838                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9839                                            LED_CTRL_TRAFFIC_OVERRIDE);
9840
9841                 if (msleep_interruptible(500))
9842                         break;
9843         }
9844         tw32(MAC_LED_CTRL, tp->led_ctrl);
9845         return 0;
9846 }
9847
9848 static void tg3_get_ethtool_stats (struct net_device *dev,
9849                                    struct ethtool_stats *estats, u64 *tmp_stats)
9850 {
9851         struct tg3 *tp = netdev_priv(dev);
9852         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9853 }
9854
9855 #define NVRAM_TEST_SIZE 0x100
9856 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9857 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9858 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9859 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9860 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9861
9862 static int tg3_test_nvram(struct tg3 *tp)
9863 {
9864         u32 csum, magic;
9865         __be32 *buf;
9866         int i, j, k, err = 0, size;
9867
9868         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9869                 return 0;
9870
9871         if (tg3_nvram_read(tp, 0, &magic) != 0)
9872                 return -EIO;
9873
9874         if (magic == TG3_EEPROM_MAGIC)
9875                 size = NVRAM_TEST_SIZE;
9876         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9877                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9878                     TG3_EEPROM_SB_FORMAT_1) {
9879                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9880                         case TG3_EEPROM_SB_REVISION_0:
9881                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9882                                 break;
9883                         case TG3_EEPROM_SB_REVISION_2:
9884                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9885                                 break;
9886                         case TG3_EEPROM_SB_REVISION_3:
9887                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9888                                 break;
9889                         default:
9890                                 return 0;
9891                         }
9892                 } else
9893                         return 0;
9894         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9895                 size = NVRAM_SELFBOOT_HW_SIZE;
9896         else
9897                 return -EIO;
9898
9899         buf = kmalloc(size, GFP_KERNEL);
9900         if (buf == NULL)
9901                 return -ENOMEM;
9902
9903         err = -EIO;
9904         for (i = 0, j = 0; i < size; i += 4, j++) {
9905                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9906                 if (err)
9907                         break;
9908         }
9909         if (i < size)
9910                 goto out;
9911
9912         /* Selfboot format */
9913         magic = be32_to_cpu(buf[0]);
9914         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9915             TG3_EEPROM_MAGIC_FW) {
9916                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9917
9918                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9919                     TG3_EEPROM_SB_REVISION_2) {
9920                         /* For rev 2, the csum doesn't include the MBA. */
9921                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9922                                 csum8 += buf8[i];
9923                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9924                                 csum8 += buf8[i];
9925                 } else {
9926                         for (i = 0; i < size; i++)
9927                                 csum8 += buf8[i];
9928                 }
9929
9930                 if (csum8 == 0) {
9931                         err = 0;
9932                         goto out;
9933                 }
9934
9935                 err = -EIO;
9936                 goto out;
9937         }
9938
9939         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9940             TG3_EEPROM_MAGIC_HW) {
9941                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9942                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9943                 u8 *buf8 = (u8 *) buf;
9944
9945                 /* Separate the parity bits and the data bytes.  */
9946                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9947                         if ((i == 0) || (i == 8)) {
9948                                 int l;
9949                                 u8 msk;
9950
9951                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9952                                         parity[k++] = buf8[i] & msk;
9953                                 i++;
9954                         }
9955                         else if (i == 16) {
9956                                 int l;
9957                                 u8 msk;
9958
9959                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9960                                         parity[k++] = buf8[i] & msk;
9961                                 i++;
9962
9963                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9964                                         parity[k++] = buf8[i] & msk;
9965                                 i++;
9966                         }
9967                         data[j++] = buf8[i];
9968                 }
9969
9970                 err = -EIO;
9971                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9972                         u8 hw8 = hweight8(data[i]);
9973
9974                         if ((hw8 & 0x1) && parity[i])
9975                                 goto out;
9976                         else if (!(hw8 & 0x1) && !parity[i])
9977                                 goto out;
9978                 }
9979                 err = 0;
9980                 goto out;
9981         }
9982
9983         /* Bootstrap checksum at offset 0x10 */
9984         csum = calc_crc((unsigned char *) buf, 0x10);
9985         if (csum != be32_to_cpu(buf[0x10/4]))
9986                 goto out;
9987
9988         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9989         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9990         if (csum != be32_to_cpu(buf[0xfc/4]))
9991                 goto out;
9992
9993         err = 0;
9994
9995 out:
9996         kfree(buf);
9997         return err;
9998 }
9999
10000 #define TG3_SERDES_TIMEOUT_SEC  2
10001 #define TG3_COPPER_TIMEOUT_SEC  6
10002
10003 static int tg3_test_link(struct tg3 *tp)
10004 {
10005         int i, max;
10006
10007         if (!netif_running(tp->dev))
10008                 return -ENODEV;
10009
10010         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10011                 max = TG3_SERDES_TIMEOUT_SEC;
10012         else
10013                 max = TG3_COPPER_TIMEOUT_SEC;
10014
10015         for (i = 0; i < max; i++) {
10016                 if (netif_carrier_ok(tp->dev))
10017                         return 0;
10018
10019                 if (msleep_interruptible(1000))
10020                         break;
10021         }
10022
10023         return -EIO;
10024 }
10025
10026 /* Only test the commonly used registers */
10027 static int tg3_test_registers(struct tg3 *tp)
10028 {
10029         int i, is_5705, is_5750;
10030         u32 offset, read_mask, write_mask, val, save_val, read_val;
10031         static struct {
10032                 u16 offset;
10033                 u16 flags;
10034 #define TG3_FL_5705     0x1
10035 #define TG3_FL_NOT_5705 0x2
10036 #define TG3_FL_NOT_5788 0x4
10037 #define TG3_FL_NOT_5750 0x8
10038                 u32 read_mask;
10039                 u32 write_mask;
10040         } reg_tbl[] = {
10041                 /* MAC Control Registers */
10042                 { MAC_MODE, TG3_FL_NOT_5705,
10043                         0x00000000, 0x00ef6f8c },
10044                 { MAC_MODE, TG3_FL_5705,
10045                         0x00000000, 0x01ef6b8c },
10046                 { MAC_STATUS, TG3_FL_NOT_5705,
10047                         0x03800107, 0x00000000 },
10048                 { MAC_STATUS, TG3_FL_5705,
10049                         0x03800100, 0x00000000 },
10050                 { MAC_ADDR_0_HIGH, 0x0000,
10051                         0x00000000, 0x0000ffff },
10052                 { MAC_ADDR_0_LOW, 0x0000,
10053                         0x00000000, 0xffffffff },
10054                 { MAC_RX_MTU_SIZE, 0x0000,
10055                         0x00000000, 0x0000ffff },
10056                 { MAC_TX_MODE, 0x0000,
10057                         0x00000000, 0x00000070 },
10058                 { MAC_TX_LENGTHS, 0x0000,
10059                         0x00000000, 0x00003fff },
10060                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10061                         0x00000000, 0x000007fc },
10062                 { MAC_RX_MODE, TG3_FL_5705,
10063                         0x00000000, 0x000007dc },
10064                 { MAC_HASH_REG_0, 0x0000,
10065                         0x00000000, 0xffffffff },
10066                 { MAC_HASH_REG_1, 0x0000,
10067                         0x00000000, 0xffffffff },
10068                 { MAC_HASH_REG_2, 0x0000,
10069                         0x00000000, 0xffffffff },
10070                 { MAC_HASH_REG_3, 0x0000,
10071                         0x00000000, 0xffffffff },
10072
10073                 /* Receive Data and Receive BD Initiator Control Registers. */
10074                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10075                         0x00000000, 0xffffffff },
10076                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10077                         0x00000000, 0xffffffff },
10078                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10079                         0x00000000, 0x00000003 },
10080                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10081                         0x00000000, 0xffffffff },
10082                 { RCVDBDI_STD_BD+0, 0x0000,
10083                         0x00000000, 0xffffffff },
10084                 { RCVDBDI_STD_BD+4, 0x0000,
10085                         0x00000000, 0xffffffff },
10086                 { RCVDBDI_STD_BD+8, 0x0000,
10087                         0x00000000, 0xffff0002 },
10088                 { RCVDBDI_STD_BD+0xc, 0x0000,
10089                         0x00000000, 0xffffffff },
10090
10091                 /* Receive BD Initiator Control Registers. */
10092                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10093                         0x00000000, 0xffffffff },
10094                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10095                         0x00000000, 0x000003ff },
10096                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10097                         0x00000000, 0xffffffff },
10098
10099                 /* Host Coalescing Control Registers. */
10100                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10101                         0x00000000, 0x00000004 },
10102                 { HOSTCC_MODE, TG3_FL_5705,
10103                         0x00000000, 0x000000f6 },
10104                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10105                         0x00000000, 0xffffffff },
10106                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10107                         0x00000000, 0x000003ff },
10108                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10109                         0x00000000, 0xffffffff },
10110                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10111                         0x00000000, 0x000003ff },
10112                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10113                         0x00000000, 0xffffffff },
10114                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10115                         0x00000000, 0x000000ff },
10116                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10117                         0x00000000, 0xffffffff },
10118                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10119                         0x00000000, 0x000000ff },
10120                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10121                         0x00000000, 0xffffffff },
10122                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10123                         0x00000000, 0xffffffff },
10124                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10125                         0x00000000, 0xffffffff },
10126                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10127                         0x00000000, 0x000000ff },
10128                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10129                         0x00000000, 0xffffffff },
10130                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10131                         0x00000000, 0x000000ff },
10132                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10133                         0x00000000, 0xffffffff },
10134                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10135                         0x00000000, 0xffffffff },
10136                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10137                         0x00000000, 0xffffffff },
10138                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10139                         0x00000000, 0xffffffff },
10140                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10141                         0x00000000, 0xffffffff },
10142                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10143                         0xffffffff, 0x00000000 },
10144                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10145                         0xffffffff, 0x00000000 },
10146
10147                 /* Buffer Manager Control Registers. */
10148                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10149                         0x00000000, 0x007fff80 },
10150                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10151                         0x00000000, 0x007fffff },
10152                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10153                         0x00000000, 0x0000003f },
10154                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10155                         0x00000000, 0x000001ff },
10156                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10157                         0x00000000, 0x000001ff },
10158                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10159                         0xffffffff, 0x00000000 },
10160                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10161                         0xffffffff, 0x00000000 },
10162
10163                 /* Mailbox Registers */
10164                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10165                         0x00000000, 0x000001ff },
10166                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10167                         0x00000000, 0x000001ff },
10168                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10169                         0x00000000, 0x000007ff },
10170                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10171                         0x00000000, 0x000001ff },
10172
10173                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10174         };
10175
10176         is_5705 = is_5750 = 0;
10177         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10178                 is_5705 = 1;
10179                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10180                         is_5750 = 1;
10181         }
10182
10183         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10184                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10185                         continue;
10186
10187                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10188                         continue;
10189
10190                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10191                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10192                         continue;
10193
10194                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10195                         continue;
10196
10197                 offset = (u32) reg_tbl[i].offset;
10198                 read_mask = reg_tbl[i].read_mask;
10199                 write_mask = reg_tbl[i].write_mask;
10200
10201                 /* Save the original register content */
10202                 save_val = tr32(offset);
10203
10204                 /* Determine the read-only value. */
10205                 read_val = save_val & read_mask;
10206
10207                 /* Write zero to the register, then make sure the read-only bits
10208                  * are not changed and the read/write bits are all zeros.
10209                  */
10210                 tw32(offset, 0);
10211
10212                 val = tr32(offset);
10213
10214                 /* Test the read-only and read/write bits. */
10215                 if (((val & read_mask) != read_val) || (val & write_mask))
10216                         goto out;
10217
10218                 /* Write ones to all the bits defined by RdMask and WrMask, then
10219                  * make sure the read-only bits are not changed and the
10220                  * read/write bits are all ones.
10221                  */
10222                 tw32(offset, read_mask | write_mask);
10223
10224                 val = tr32(offset);
10225
10226                 /* Test the read-only bits. */
10227                 if ((val & read_mask) != read_val)
10228                         goto out;
10229
10230                 /* Test the read/write bits. */
10231                 if ((val & write_mask) != write_mask)
10232                         goto out;
10233
10234                 tw32(offset, save_val);
10235         }
10236
10237         return 0;
10238
10239 out:
10240         if (netif_msg_hw(tp))
10241                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10242                        offset);
10243         tw32(offset, save_val);
10244         return -EIO;
10245 }
10246
10247 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10248 {
10249         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10250         int i;
10251         u32 j;
10252
10253         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10254                 for (j = 0; j < len; j += 4) {
10255                         u32 val;
10256
10257                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10258                         tg3_read_mem(tp, offset + j, &val);
10259                         if (val != test_pattern[i])
10260                                 return -EIO;
10261                 }
10262         }
10263         return 0;
10264 }
10265
10266 static int tg3_test_memory(struct tg3 *tp)
10267 {
10268         static struct mem_entry {
10269                 u32 offset;
10270                 u32 len;
10271         } mem_tbl_570x[] = {
10272                 { 0x00000000, 0x00b50},
10273                 { 0x00002000, 0x1c000},
10274                 { 0xffffffff, 0x00000}
10275         }, mem_tbl_5705[] = {
10276                 { 0x00000100, 0x0000c},
10277                 { 0x00000200, 0x00008},
10278                 { 0x00004000, 0x00800},
10279                 { 0x00006000, 0x01000},
10280                 { 0x00008000, 0x02000},
10281                 { 0x00010000, 0x0e000},
10282                 { 0xffffffff, 0x00000}
10283         }, mem_tbl_5755[] = {
10284                 { 0x00000200, 0x00008},
10285                 { 0x00004000, 0x00800},
10286                 { 0x00006000, 0x00800},
10287                 { 0x00008000, 0x02000},
10288                 { 0x00010000, 0x0c000},
10289                 { 0xffffffff, 0x00000}
10290         }, mem_tbl_5906[] = {
10291                 { 0x00000200, 0x00008},
10292                 { 0x00004000, 0x00400},
10293                 { 0x00006000, 0x00400},
10294                 { 0x00008000, 0x01000},
10295                 { 0x00010000, 0x01000},
10296                 { 0xffffffff, 0x00000}
10297         };
10298         struct mem_entry *mem_tbl;
10299         int err = 0;
10300         int i;
10301
10302         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10303                 mem_tbl = mem_tbl_5755;
10304         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10305                 mem_tbl = mem_tbl_5906;
10306         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10307                 mem_tbl = mem_tbl_5705;
10308         else
10309                 mem_tbl = mem_tbl_570x;
10310
10311         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10312                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10313                     mem_tbl[i].len)) != 0)
10314                         break;
10315         }
10316
10317         return err;
10318 }
10319
10320 #define TG3_MAC_LOOPBACK        0
10321 #define TG3_PHY_LOOPBACK        1
10322
10323 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10324 {
10325         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10326         u32 desc_idx, coal_now;
10327         struct sk_buff *skb, *rx_skb;
10328         u8 *tx_data;
10329         dma_addr_t map;
10330         int num_pkts, tx_len, rx_len, i, err;
10331         struct tg3_rx_buffer_desc *desc;
10332         struct tg3_napi *tnapi, *rnapi;
10333         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10334
10335         if (tp->irq_cnt > 1) {
10336                 tnapi = &tp->napi[1];
10337                 rnapi = &tp->napi[1];
10338         } else {
10339                 tnapi = &tp->napi[0];
10340                 rnapi = &tp->napi[0];
10341         }
10342         coal_now = tnapi->coal_now | rnapi->coal_now;
10343
10344         if (loopback_mode == TG3_MAC_LOOPBACK) {
10345                 /* HW errata - mac loopback fails in some cases on 5780.
10346                  * Normal traffic and PHY loopback are not affected by
10347                  * errata.
10348                  */
10349                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10350                         return 0;
10351
10352                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10353                            MAC_MODE_PORT_INT_LPBACK;
10354                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10355                         mac_mode |= MAC_MODE_LINK_POLARITY;
10356                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10357                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10358                 else
10359                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10360                 tw32(MAC_MODE, mac_mode);
10361         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10362                 u32 val;
10363
10364                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10365                         tg3_phy_fet_toggle_apd(tp, false);
10366                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10367                 } else
10368                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10369
10370                 tg3_phy_toggle_automdix(tp, 0);
10371
10372                 tg3_writephy(tp, MII_BMCR, val);
10373                 udelay(40);
10374
10375                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10376                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10377                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10378                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10379                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10380                 } else
10381                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10382
10383                 /* reset to prevent losing 1st rx packet intermittently */
10384                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10385                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10386                         udelay(10);
10387                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10388                 }
10389                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10390                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10391                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10392                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10393                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10394                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10395                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10396                 }
10397                 tw32(MAC_MODE, mac_mode);
10398         }
10399         else
10400                 return -EINVAL;
10401
10402         err = -EIO;
10403
10404         tx_len = 1514;
10405         skb = netdev_alloc_skb(tp->dev, tx_len);
10406         if (!skb)
10407                 return -ENOMEM;
10408
10409         tx_data = skb_put(skb, tx_len);
10410         memcpy(tx_data, tp->dev->dev_addr, 6);
10411         memset(tx_data + 6, 0x0, 8);
10412
10413         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10414
10415         for (i = 14; i < tx_len; i++)
10416                 tx_data[i] = (u8) (i & 0xff);
10417
10418         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10419                 dev_kfree_skb(skb);
10420                 return -EIO;
10421         }
10422
10423         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10424                rnapi->coal_now);
10425
10426         udelay(10);
10427
10428         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10429
10430         num_pkts = 0;
10431
10432         tg3_set_txd(tnapi, tnapi->tx_prod,
10433                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10434
10435         tnapi->tx_prod++;
10436         num_pkts++;
10437
10438         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10439         tr32_mailbox(tnapi->prodmbox);
10440
10441         udelay(10);
10442
10443         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10444         for (i = 0; i < 35; i++) {
10445                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10446                        coal_now);
10447
10448                 udelay(10);
10449
10450                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10451                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10452                 if ((tx_idx == tnapi->tx_prod) &&
10453                     (rx_idx == (rx_start_idx + num_pkts)))
10454                         break;
10455         }
10456
10457         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10458         dev_kfree_skb(skb);
10459
10460         if (tx_idx != tnapi->tx_prod)
10461                 goto out;
10462
10463         if (rx_idx != rx_start_idx + num_pkts)
10464                 goto out;
10465
10466         desc = &rnapi->rx_rcb[rx_start_idx];
10467         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10468         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10469         if (opaque_key != RXD_OPAQUE_RING_STD)
10470                 goto out;
10471
10472         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10473             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10474                 goto out;
10475
10476         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10477         if (rx_len != tx_len)
10478                 goto out;
10479
10480         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10481
10482         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10483         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10484
10485         for (i = 14; i < tx_len; i++) {
10486                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10487                         goto out;
10488         }
10489         err = 0;
10490
10491         /* tg3_free_rings will unmap and free the rx_skb */
10492 out:
10493         return err;
10494 }
10495
10496 #define TG3_MAC_LOOPBACK_FAILED         1
10497 #define TG3_PHY_LOOPBACK_FAILED         2
10498 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10499                                          TG3_PHY_LOOPBACK_FAILED)
10500
10501 static int tg3_test_loopback(struct tg3 *tp)
10502 {
10503         int err = 0;
10504         u32 cpmuctrl = 0;
10505
10506         if (!netif_running(tp->dev))
10507                 return TG3_LOOPBACK_FAILED;
10508
10509         err = tg3_reset_hw(tp, 1);
10510         if (err)
10511                 return TG3_LOOPBACK_FAILED;
10512
10513         /* Turn off gphy autopowerdown. */
10514         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10515                 tg3_phy_toggle_apd(tp, false);
10516
10517         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10518                 int i;
10519                 u32 status;
10520
10521                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10522
10523                 /* Wait for up to 40 microseconds to acquire lock. */
10524                 for (i = 0; i < 4; i++) {
10525                         status = tr32(TG3_CPMU_MUTEX_GNT);
10526                         if (status == CPMU_MUTEX_GNT_DRIVER)
10527                                 break;
10528                         udelay(10);
10529                 }
10530
10531                 if (status != CPMU_MUTEX_GNT_DRIVER)
10532                         return TG3_LOOPBACK_FAILED;
10533
10534                 /* Turn off link-based power management. */
10535                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10536                 tw32(TG3_CPMU_CTRL,
10537                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10538                                   CPMU_CTRL_LINK_AWARE_MODE));
10539         }
10540
10541         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10542                 err |= TG3_MAC_LOOPBACK_FAILED;
10543
10544         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10545                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10546
10547                 /* Release the mutex */
10548                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10549         }
10550
10551         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10552             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10553                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10554                         err |= TG3_PHY_LOOPBACK_FAILED;
10555         }
10556
10557         /* Re-enable gphy autopowerdown. */
10558         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10559                 tg3_phy_toggle_apd(tp, true);
10560
10561         return err;
10562 }
10563
10564 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10565                           u64 *data)
10566 {
10567         struct tg3 *tp = netdev_priv(dev);
10568
10569         if (tp->link_config.phy_is_low_power)
10570                 tg3_set_power_state(tp, PCI_D0);
10571
10572         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10573
10574         if (tg3_test_nvram(tp) != 0) {
10575                 etest->flags |= ETH_TEST_FL_FAILED;
10576                 data[0] = 1;
10577         }
10578         if (tg3_test_link(tp) != 0) {
10579                 etest->flags |= ETH_TEST_FL_FAILED;
10580                 data[1] = 1;
10581         }
10582         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10583                 int err, err2 = 0, irq_sync = 0;
10584
10585                 if (netif_running(dev)) {
10586                         tg3_phy_stop(tp);
10587                         tg3_netif_stop(tp);
10588                         irq_sync = 1;
10589                 }
10590
10591                 tg3_full_lock(tp, irq_sync);
10592
10593                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10594                 err = tg3_nvram_lock(tp);
10595                 tg3_halt_cpu(tp, RX_CPU_BASE);
10596                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10597                         tg3_halt_cpu(tp, TX_CPU_BASE);
10598                 if (!err)
10599                         tg3_nvram_unlock(tp);
10600
10601                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10602                         tg3_phy_reset(tp);
10603
10604                 if (tg3_test_registers(tp) != 0) {
10605                         etest->flags |= ETH_TEST_FL_FAILED;
10606                         data[2] = 1;
10607                 }
10608                 if (tg3_test_memory(tp) != 0) {
10609                         etest->flags |= ETH_TEST_FL_FAILED;
10610                         data[3] = 1;
10611                 }
10612                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10613                         etest->flags |= ETH_TEST_FL_FAILED;
10614
10615                 tg3_full_unlock(tp);
10616
10617                 if (tg3_test_interrupt(tp) != 0) {
10618                         etest->flags |= ETH_TEST_FL_FAILED;
10619                         data[5] = 1;
10620                 }
10621
10622                 tg3_full_lock(tp, 0);
10623
10624                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10625                 if (netif_running(dev)) {
10626                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10627                         err2 = tg3_restart_hw(tp, 1);
10628                         if (!err2)
10629                                 tg3_netif_start(tp);
10630                 }
10631
10632                 tg3_full_unlock(tp);
10633
10634                 if (irq_sync && !err2)
10635                         tg3_phy_start(tp);
10636         }
10637         if (tp->link_config.phy_is_low_power)
10638                 tg3_set_power_state(tp, PCI_D3hot);
10639
10640 }
10641
10642 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10643 {
10644         struct mii_ioctl_data *data = if_mii(ifr);
10645         struct tg3 *tp = netdev_priv(dev);
10646         int err;
10647
10648         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10649                 struct phy_device *phydev;
10650                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10651                         return -EAGAIN;
10652                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10653                 return phy_mii_ioctl(phydev, data, cmd);
10654         }
10655
10656         switch(cmd) {
10657         case SIOCGMIIPHY:
10658                 data->phy_id = tp->phy_addr;
10659
10660                 /* fallthru */
10661         case SIOCGMIIREG: {
10662                 u32 mii_regval;
10663
10664                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10665                         break;                  /* We have no PHY */
10666
10667                 if (tp->link_config.phy_is_low_power)
10668                         return -EAGAIN;
10669
10670                 spin_lock_bh(&tp->lock);
10671                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10672                 spin_unlock_bh(&tp->lock);
10673
10674                 data->val_out = mii_regval;
10675
10676                 return err;
10677         }
10678
10679         case SIOCSMIIREG:
10680                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10681                         break;                  /* We have no PHY */
10682
10683                 if (tp->link_config.phy_is_low_power)
10684                         return -EAGAIN;
10685
10686                 spin_lock_bh(&tp->lock);
10687                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10688                 spin_unlock_bh(&tp->lock);
10689
10690                 return err;
10691
10692         default:
10693                 /* do nothing */
10694                 break;
10695         }
10696         return -EOPNOTSUPP;
10697 }
10698
10699 #if TG3_VLAN_TAG_USED
10700 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10701 {
10702         struct tg3 *tp = netdev_priv(dev);
10703
10704         if (!netif_running(dev)) {
10705                 tp->vlgrp = grp;
10706                 return;
10707         }
10708
10709         tg3_netif_stop(tp);
10710
10711         tg3_full_lock(tp, 0);
10712
10713         tp->vlgrp = grp;
10714
10715         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10716         __tg3_set_rx_mode(dev);
10717
10718         tg3_netif_start(tp);
10719
10720         tg3_full_unlock(tp);
10721 }
10722 #endif
10723
10724 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10725 {
10726         struct tg3 *tp = netdev_priv(dev);
10727
10728         memcpy(ec, &tp->coal, sizeof(*ec));
10729         return 0;
10730 }
10731
10732 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10733 {
10734         struct tg3 *tp = netdev_priv(dev);
10735         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10736         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10737
10738         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10739                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10740                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10741                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10742                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10743         }
10744
10745         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10746             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10747             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10748             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10749             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10750             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10751             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10752             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10753             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10754             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10755                 return -EINVAL;
10756
10757         /* No rx interrupts will be generated if both are zero */
10758         if ((ec->rx_coalesce_usecs == 0) &&
10759             (ec->rx_max_coalesced_frames == 0))
10760                 return -EINVAL;
10761
10762         /* No tx interrupts will be generated if both are zero */
10763         if ((ec->tx_coalesce_usecs == 0) &&
10764             (ec->tx_max_coalesced_frames == 0))
10765                 return -EINVAL;
10766
10767         /* Only copy relevant parameters, ignore all others. */
10768         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10769         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10770         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10771         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10772         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10773         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10774         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10775         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10776         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10777
10778         if (netif_running(dev)) {
10779                 tg3_full_lock(tp, 0);
10780                 __tg3_set_coalesce(tp, &tp->coal);
10781                 tg3_full_unlock(tp);
10782         }
10783         return 0;
10784 }
10785
10786 static const struct ethtool_ops tg3_ethtool_ops = {
10787         .get_settings           = tg3_get_settings,
10788         .set_settings           = tg3_set_settings,
10789         .get_drvinfo            = tg3_get_drvinfo,
10790         .get_regs_len           = tg3_get_regs_len,
10791         .get_regs               = tg3_get_regs,
10792         .get_wol                = tg3_get_wol,
10793         .set_wol                = tg3_set_wol,
10794         .get_msglevel           = tg3_get_msglevel,
10795         .set_msglevel           = tg3_set_msglevel,
10796         .nway_reset             = tg3_nway_reset,
10797         .get_link               = ethtool_op_get_link,
10798         .get_eeprom_len         = tg3_get_eeprom_len,
10799         .get_eeprom             = tg3_get_eeprom,
10800         .set_eeprom             = tg3_set_eeprom,
10801         .get_ringparam          = tg3_get_ringparam,
10802         .set_ringparam          = tg3_set_ringparam,
10803         .get_pauseparam         = tg3_get_pauseparam,
10804         .set_pauseparam         = tg3_set_pauseparam,
10805         .get_rx_csum            = tg3_get_rx_csum,
10806         .set_rx_csum            = tg3_set_rx_csum,
10807         .set_tx_csum            = tg3_set_tx_csum,
10808         .set_sg                 = ethtool_op_set_sg,
10809         .set_tso                = tg3_set_tso,
10810         .self_test              = tg3_self_test,
10811         .get_strings            = tg3_get_strings,
10812         .phys_id                = tg3_phys_id,
10813         .get_ethtool_stats      = tg3_get_ethtool_stats,
10814         .get_coalesce           = tg3_get_coalesce,
10815         .set_coalesce           = tg3_set_coalesce,
10816         .get_sset_count         = tg3_get_sset_count,
10817 };
10818
10819 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10820 {
10821         u32 cursize, val, magic;
10822
10823         tp->nvram_size = EEPROM_CHIP_SIZE;
10824
10825         if (tg3_nvram_read(tp, 0, &magic) != 0)
10826                 return;
10827
10828         if ((magic != TG3_EEPROM_MAGIC) &&
10829             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10830             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10831                 return;
10832
10833         /*
10834          * Size the chip by reading offsets at increasing powers of two.
10835          * When we encounter our validation signature, we know the addressing
10836          * has wrapped around, and thus have our chip size.
10837          */
10838         cursize = 0x10;
10839
10840         while (cursize < tp->nvram_size) {
10841                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10842                         return;
10843
10844                 if (val == magic)
10845                         break;
10846
10847                 cursize <<= 1;
10848         }
10849
10850         tp->nvram_size = cursize;
10851 }
10852
10853 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10854 {
10855         u32 val;
10856
10857         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10858             tg3_nvram_read(tp, 0, &val) != 0)
10859                 return;
10860
10861         /* Selfboot format */
10862         if (val != TG3_EEPROM_MAGIC) {
10863                 tg3_get_eeprom_size(tp);
10864                 return;
10865         }
10866
10867         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10868                 if (val != 0) {
10869                         /* This is confusing.  We want to operate on the
10870                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10871                          * call will read from NVRAM and byteswap the data
10872                          * according to the byteswapping settings for all
10873                          * other register accesses.  This ensures the data we
10874                          * want will always reside in the lower 16-bits.
10875                          * However, the data in NVRAM is in LE format, which
10876                          * means the data from the NVRAM read will always be
10877                          * opposite the endianness of the CPU.  The 16-bit
10878                          * byteswap then brings the data to CPU endianness.
10879                          */
10880                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10881                         return;
10882                 }
10883         }
10884         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10885 }
10886
10887 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10888 {
10889         u32 nvcfg1;
10890
10891         nvcfg1 = tr32(NVRAM_CFG1);
10892         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10893                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10894         } else {
10895                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10896                 tw32(NVRAM_CFG1, nvcfg1);
10897         }
10898
10899         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10900             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10901                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10902                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10903                         tp->nvram_jedecnum = JEDEC_ATMEL;
10904                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10905                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10906                         break;
10907                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10908                         tp->nvram_jedecnum = JEDEC_ATMEL;
10909                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10910                         break;
10911                 case FLASH_VENDOR_ATMEL_EEPROM:
10912                         tp->nvram_jedecnum = JEDEC_ATMEL;
10913                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10914                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10915                         break;
10916                 case FLASH_VENDOR_ST:
10917                         tp->nvram_jedecnum = JEDEC_ST;
10918                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10919                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10920                         break;
10921                 case FLASH_VENDOR_SAIFUN:
10922                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10923                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10924                         break;
10925                 case FLASH_VENDOR_SST_SMALL:
10926                 case FLASH_VENDOR_SST_LARGE:
10927                         tp->nvram_jedecnum = JEDEC_SST;
10928                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10929                         break;
10930                 }
10931         } else {
10932                 tp->nvram_jedecnum = JEDEC_ATMEL;
10933                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10934                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10935         }
10936 }
10937
10938 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10939 {
10940         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10941         case FLASH_5752PAGE_SIZE_256:
10942                 tp->nvram_pagesize = 256;
10943                 break;
10944         case FLASH_5752PAGE_SIZE_512:
10945                 tp->nvram_pagesize = 512;
10946                 break;
10947         case FLASH_5752PAGE_SIZE_1K:
10948                 tp->nvram_pagesize = 1024;
10949                 break;
10950         case FLASH_5752PAGE_SIZE_2K:
10951                 tp->nvram_pagesize = 2048;
10952                 break;
10953         case FLASH_5752PAGE_SIZE_4K:
10954                 tp->nvram_pagesize = 4096;
10955                 break;
10956         case FLASH_5752PAGE_SIZE_264:
10957                 tp->nvram_pagesize = 264;
10958                 break;
10959         case FLASH_5752PAGE_SIZE_528:
10960                 tp->nvram_pagesize = 528;
10961                 break;
10962         }
10963 }
10964
10965 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10966 {
10967         u32 nvcfg1;
10968
10969         nvcfg1 = tr32(NVRAM_CFG1);
10970
10971         /* NVRAM protection for TPM */
10972         if (nvcfg1 & (1 << 27))
10973                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
10974
10975         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10976         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10977         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10978                 tp->nvram_jedecnum = JEDEC_ATMEL;
10979                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10980                 break;
10981         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10982                 tp->nvram_jedecnum = JEDEC_ATMEL;
10983                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10984                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10985                 break;
10986         case FLASH_5752VENDOR_ST_M45PE10:
10987         case FLASH_5752VENDOR_ST_M45PE20:
10988         case FLASH_5752VENDOR_ST_M45PE40:
10989                 tp->nvram_jedecnum = JEDEC_ST;
10990                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10991                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10992                 break;
10993         }
10994
10995         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10996                 tg3_nvram_get_pagesize(tp, nvcfg1);
10997         } else {
10998                 /* For eeprom, set pagesize to maximum eeprom size */
10999                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11000
11001                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11002                 tw32(NVRAM_CFG1, nvcfg1);
11003         }
11004 }
11005
11006 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11007 {
11008         u32 nvcfg1, protect = 0;
11009
11010         nvcfg1 = tr32(NVRAM_CFG1);
11011
11012         /* NVRAM protection for TPM */
11013         if (nvcfg1 & (1 << 27)) {
11014                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11015                 protect = 1;
11016         }
11017
11018         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11019         switch (nvcfg1) {
11020         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11021         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11022         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11023         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11024                 tp->nvram_jedecnum = JEDEC_ATMEL;
11025                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11026                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11027                 tp->nvram_pagesize = 264;
11028                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11029                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11030                         tp->nvram_size = (protect ? 0x3e200 :
11031                                           TG3_NVRAM_SIZE_512KB);
11032                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11033                         tp->nvram_size = (protect ? 0x1f200 :
11034                                           TG3_NVRAM_SIZE_256KB);
11035                 else
11036                         tp->nvram_size = (protect ? 0x1f200 :
11037                                           TG3_NVRAM_SIZE_128KB);
11038                 break;
11039         case FLASH_5752VENDOR_ST_M45PE10:
11040         case FLASH_5752VENDOR_ST_M45PE20:
11041         case FLASH_5752VENDOR_ST_M45PE40:
11042                 tp->nvram_jedecnum = JEDEC_ST;
11043                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11044                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11045                 tp->nvram_pagesize = 256;
11046                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11047                         tp->nvram_size = (protect ?
11048                                           TG3_NVRAM_SIZE_64KB :
11049                                           TG3_NVRAM_SIZE_128KB);
11050                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11051                         tp->nvram_size = (protect ?
11052                                           TG3_NVRAM_SIZE_64KB :
11053                                           TG3_NVRAM_SIZE_256KB);
11054                 else
11055                         tp->nvram_size = (protect ?
11056                                           TG3_NVRAM_SIZE_128KB :
11057                                           TG3_NVRAM_SIZE_512KB);
11058                 break;
11059         }
11060 }
11061
11062 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11063 {
11064         u32 nvcfg1;
11065
11066         nvcfg1 = tr32(NVRAM_CFG1);
11067
11068         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11069         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11070         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11071         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11072         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11073                 tp->nvram_jedecnum = JEDEC_ATMEL;
11074                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11075                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11076
11077                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11078                 tw32(NVRAM_CFG1, nvcfg1);
11079                 break;
11080         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11081         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11082         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11083         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11084                 tp->nvram_jedecnum = JEDEC_ATMEL;
11085                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11086                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11087                 tp->nvram_pagesize = 264;
11088                 break;
11089         case FLASH_5752VENDOR_ST_M45PE10:
11090         case FLASH_5752VENDOR_ST_M45PE20:
11091         case FLASH_5752VENDOR_ST_M45PE40:
11092                 tp->nvram_jedecnum = JEDEC_ST;
11093                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11094                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11095                 tp->nvram_pagesize = 256;
11096                 break;
11097         }
11098 }
11099
11100 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11101 {
11102         u32 nvcfg1, protect = 0;
11103
11104         nvcfg1 = tr32(NVRAM_CFG1);
11105
11106         /* NVRAM protection for TPM */
11107         if (nvcfg1 & (1 << 27)) {
11108                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11109                 protect = 1;
11110         }
11111
11112         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11113         switch (nvcfg1) {
11114         case FLASH_5761VENDOR_ATMEL_ADB021D:
11115         case FLASH_5761VENDOR_ATMEL_ADB041D:
11116         case FLASH_5761VENDOR_ATMEL_ADB081D:
11117         case FLASH_5761VENDOR_ATMEL_ADB161D:
11118         case FLASH_5761VENDOR_ATMEL_MDB021D:
11119         case FLASH_5761VENDOR_ATMEL_MDB041D:
11120         case FLASH_5761VENDOR_ATMEL_MDB081D:
11121         case FLASH_5761VENDOR_ATMEL_MDB161D:
11122                 tp->nvram_jedecnum = JEDEC_ATMEL;
11123                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11124                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11125                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11126                 tp->nvram_pagesize = 256;
11127                 break;
11128         case FLASH_5761VENDOR_ST_A_M45PE20:
11129         case FLASH_5761VENDOR_ST_A_M45PE40:
11130         case FLASH_5761VENDOR_ST_A_M45PE80:
11131         case FLASH_5761VENDOR_ST_A_M45PE16:
11132         case FLASH_5761VENDOR_ST_M_M45PE20:
11133         case FLASH_5761VENDOR_ST_M_M45PE40:
11134         case FLASH_5761VENDOR_ST_M_M45PE80:
11135         case FLASH_5761VENDOR_ST_M_M45PE16:
11136                 tp->nvram_jedecnum = JEDEC_ST;
11137                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11138                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11139                 tp->nvram_pagesize = 256;
11140                 break;
11141         }
11142
11143         if (protect) {
11144                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11145         } else {
11146                 switch (nvcfg1) {
11147                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11148                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11149                 case FLASH_5761VENDOR_ST_A_M45PE16:
11150                 case FLASH_5761VENDOR_ST_M_M45PE16:
11151                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11152                         break;
11153                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11154                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11155                 case FLASH_5761VENDOR_ST_A_M45PE80:
11156                 case FLASH_5761VENDOR_ST_M_M45PE80:
11157                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11158                         break;
11159                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11160                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11161                 case FLASH_5761VENDOR_ST_A_M45PE40:
11162                 case FLASH_5761VENDOR_ST_M_M45PE40:
11163                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11164                         break;
11165                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11166                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11167                 case FLASH_5761VENDOR_ST_A_M45PE20:
11168                 case FLASH_5761VENDOR_ST_M_M45PE20:
11169                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11170                         break;
11171                 }
11172         }
11173 }
11174
11175 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11176 {
11177         tp->nvram_jedecnum = JEDEC_ATMEL;
11178         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11179         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11180 }
11181
11182 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11183 {
11184         u32 nvcfg1;
11185
11186         nvcfg1 = tr32(NVRAM_CFG1);
11187
11188         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11189         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11190         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11191                 tp->nvram_jedecnum = JEDEC_ATMEL;
11192                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11193                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11194
11195                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11196                 tw32(NVRAM_CFG1, nvcfg1);
11197                 return;
11198         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11199         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11200         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11201         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11202         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11203         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11204         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11205                 tp->nvram_jedecnum = JEDEC_ATMEL;
11206                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11207                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11208
11209                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11210                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11211                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11212                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11213                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11214                         break;
11215                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11216                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11217                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11218                         break;
11219                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11220                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11221                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11222                         break;
11223                 }
11224                 break;
11225         case FLASH_5752VENDOR_ST_M45PE10:
11226         case FLASH_5752VENDOR_ST_M45PE20:
11227         case FLASH_5752VENDOR_ST_M45PE40:
11228                 tp->nvram_jedecnum = JEDEC_ST;
11229                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11230                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11231
11232                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11233                 case FLASH_5752VENDOR_ST_M45PE10:
11234                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11235                         break;
11236                 case FLASH_5752VENDOR_ST_M45PE20:
11237                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11238                         break;
11239                 case FLASH_5752VENDOR_ST_M45PE40:
11240                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11241                         break;
11242                 }
11243                 break;
11244         default:
11245                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11246                 return;
11247         }
11248
11249         tg3_nvram_get_pagesize(tp, nvcfg1);
11250         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11251                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11252 }
11253
11254
11255 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11256 {
11257         u32 nvcfg1;
11258
11259         nvcfg1 = tr32(NVRAM_CFG1);
11260
11261         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11262         case FLASH_5717VENDOR_ATMEL_EEPROM:
11263         case FLASH_5717VENDOR_MICRO_EEPROM:
11264                 tp->nvram_jedecnum = JEDEC_ATMEL;
11265                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11266                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11267
11268                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11269                 tw32(NVRAM_CFG1, nvcfg1);
11270                 return;
11271         case FLASH_5717VENDOR_ATMEL_MDB011D:
11272         case FLASH_5717VENDOR_ATMEL_ADB011B:
11273         case FLASH_5717VENDOR_ATMEL_ADB011D:
11274         case FLASH_5717VENDOR_ATMEL_MDB021D:
11275         case FLASH_5717VENDOR_ATMEL_ADB021B:
11276         case FLASH_5717VENDOR_ATMEL_ADB021D:
11277         case FLASH_5717VENDOR_ATMEL_45USPT:
11278                 tp->nvram_jedecnum = JEDEC_ATMEL;
11279                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11280                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11281
11282                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11283                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11284                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11285                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11286                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11287                         break;
11288                 default:
11289                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11290                         break;
11291                 }
11292                 break;
11293         case FLASH_5717VENDOR_ST_M_M25PE10:
11294         case FLASH_5717VENDOR_ST_A_M25PE10:
11295         case FLASH_5717VENDOR_ST_M_M45PE10:
11296         case FLASH_5717VENDOR_ST_A_M45PE10:
11297         case FLASH_5717VENDOR_ST_M_M25PE20:
11298         case FLASH_5717VENDOR_ST_A_M25PE20:
11299         case FLASH_5717VENDOR_ST_M_M45PE20:
11300         case FLASH_5717VENDOR_ST_A_M45PE20:
11301         case FLASH_5717VENDOR_ST_25USPT:
11302         case FLASH_5717VENDOR_ST_45USPT:
11303                 tp->nvram_jedecnum = JEDEC_ST;
11304                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11305                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11306
11307                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11308                 case FLASH_5717VENDOR_ST_M_M25PE20:
11309                 case FLASH_5717VENDOR_ST_A_M25PE20:
11310                 case FLASH_5717VENDOR_ST_M_M45PE20:
11311                 case FLASH_5717VENDOR_ST_A_M45PE20:
11312                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11313                         break;
11314                 default:
11315                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11316                         break;
11317                 }
11318                 break;
11319         default:
11320                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11321                 return;
11322         }
11323
11324         tg3_nvram_get_pagesize(tp, nvcfg1);
11325         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11326                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11327 }
11328
11329 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11330 static void __devinit tg3_nvram_init(struct tg3 *tp)
11331 {
11332         tw32_f(GRC_EEPROM_ADDR,
11333              (EEPROM_ADDR_FSM_RESET |
11334               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11335                EEPROM_ADDR_CLKPERD_SHIFT)));
11336
11337         msleep(1);
11338
11339         /* Enable seeprom accesses. */
11340         tw32_f(GRC_LOCAL_CTRL,
11341              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11342         udelay(100);
11343
11344         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11345             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11346                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11347
11348                 if (tg3_nvram_lock(tp)) {
11349                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11350                                "tg3_nvram_init failed.\n", tp->dev->name);
11351                         return;
11352                 }
11353                 tg3_enable_nvram_access(tp);
11354
11355                 tp->nvram_size = 0;
11356
11357                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11358                         tg3_get_5752_nvram_info(tp);
11359                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11360                         tg3_get_5755_nvram_info(tp);
11361                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11362                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11363                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11364                         tg3_get_5787_nvram_info(tp);
11365                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11366                         tg3_get_5761_nvram_info(tp);
11367                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11368                         tg3_get_5906_nvram_info(tp);
11369                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11370                         tg3_get_57780_nvram_info(tp);
11371                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11372                         tg3_get_5717_nvram_info(tp);
11373                 else
11374                         tg3_get_nvram_info(tp);
11375
11376                 if (tp->nvram_size == 0)
11377                         tg3_get_nvram_size(tp);
11378
11379                 tg3_disable_nvram_access(tp);
11380                 tg3_nvram_unlock(tp);
11381
11382         } else {
11383                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11384
11385                 tg3_get_eeprom_size(tp);
11386         }
11387 }
11388
11389 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11390                                     u32 offset, u32 len, u8 *buf)
11391 {
11392         int i, j, rc = 0;
11393         u32 val;
11394
11395         for (i = 0; i < len; i += 4) {
11396                 u32 addr;
11397                 __be32 data;
11398
11399                 addr = offset + i;
11400
11401                 memcpy(&data, buf + i, 4);
11402
11403                 /*
11404                  * The SEEPROM interface expects the data to always be opposite
11405                  * the native endian format.  We accomplish this by reversing
11406                  * all the operations that would have been performed on the
11407                  * data from a call to tg3_nvram_read_be32().
11408                  */
11409                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11410
11411                 val = tr32(GRC_EEPROM_ADDR);
11412                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11413
11414                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11415                         EEPROM_ADDR_READ);
11416                 tw32(GRC_EEPROM_ADDR, val |
11417                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11418                         (addr & EEPROM_ADDR_ADDR_MASK) |
11419                         EEPROM_ADDR_START |
11420                         EEPROM_ADDR_WRITE);
11421
11422                 for (j = 0; j < 1000; j++) {
11423                         val = tr32(GRC_EEPROM_ADDR);
11424
11425                         if (val & EEPROM_ADDR_COMPLETE)
11426                                 break;
11427                         msleep(1);
11428                 }
11429                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11430                         rc = -EBUSY;
11431                         break;
11432                 }
11433         }
11434
11435         return rc;
11436 }
11437
11438 /* offset and length are dword aligned */
11439 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11440                 u8 *buf)
11441 {
11442         int ret = 0;
11443         u32 pagesize = tp->nvram_pagesize;
11444         u32 pagemask = pagesize - 1;
11445         u32 nvram_cmd;
11446         u8 *tmp;
11447
11448         tmp = kmalloc(pagesize, GFP_KERNEL);
11449         if (tmp == NULL)
11450                 return -ENOMEM;
11451
11452         while (len) {
11453                 int j;
11454                 u32 phy_addr, page_off, size;
11455
11456                 phy_addr = offset & ~pagemask;
11457
11458                 for (j = 0; j < pagesize; j += 4) {
11459                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11460                                                   (__be32 *) (tmp + j));
11461                         if (ret)
11462                                 break;
11463                 }
11464                 if (ret)
11465                         break;
11466
11467                 page_off = offset & pagemask;
11468                 size = pagesize;
11469                 if (len < size)
11470                         size = len;
11471
11472                 len -= size;
11473
11474                 memcpy(tmp + page_off, buf, size);
11475
11476                 offset = offset + (pagesize - page_off);
11477
11478                 tg3_enable_nvram_access(tp);
11479
11480                 /*
11481                  * Before we can erase the flash page, we need
11482                  * to issue a special "write enable" command.
11483                  */
11484                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11485
11486                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11487                         break;
11488
11489                 /* Erase the target page */
11490                 tw32(NVRAM_ADDR, phy_addr);
11491
11492                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11493                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11494
11495                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11496                         break;
11497
11498                 /* Issue another write enable to start the write. */
11499                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11500
11501                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11502                         break;
11503
11504                 for (j = 0; j < pagesize; j += 4) {
11505                         __be32 data;
11506
11507                         data = *((__be32 *) (tmp + j));
11508
11509                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11510
11511                         tw32(NVRAM_ADDR, phy_addr + j);
11512
11513                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11514                                 NVRAM_CMD_WR;
11515
11516                         if (j == 0)
11517                                 nvram_cmd |= NVRAM_CMD_FIRST;
11518                         else if (j == (pagesize - 4))
11519                                 nvram_cmd |= NVRAM_CMD_LAST;
11520
11521                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11522                                 break;
11523                 }
11524                 if (ret)
11525                         break;
11526         }
11527
11528         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11529         tg3_nvram_exec_cmd(tp, nvram_cmd);
11530
11531         kfree(tmp);
11532
11533         return ret;
11534 }
11535
11536 /* offset and length are dword aligned */
11537 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11538                 u8 *buf)
11539 {
11540         int i, ret = 0;
11541
11542         for (i = 0; i < len; i += 4, offset += 4) {
11543                 u32 page_off, phy_addr, nvram_cmd;
11544                 __be32 data;
11545
11546                 memcpy(&data, buf + i, 4);
11547                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11548
11549                 page_off = offset % tp->nvram_pagesize;
11550
11551                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11552
11553                 tw32(NVRAM_ADDR, phy_addr);
11554
11555                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11556
11557                 if ((page_off == 0) || (i == 0))
11558                         nvram_cmd |= NVRAM_CMD_FIRST;
11559                 if (page_off == (tp->nvram_pagesize - 4))
11560                         nvram_cmd |= NVRAM_CMD_LAST;
11561
11562                 if (i == (len - 4))
11563                         nvram_cmd |= NVRAM_CMD_LAST;
11564
11565                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11566                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11567                     (tp->nvram_jedecnum == JEDEC_ST) &&
11568                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11569
11570                         if ((ret = tg3_nvram_exec_cmd(tp,
11571                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11572                                 NVRAM_CMD_DONE)))
11573
11574                                 break;
11575                 }
11576                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11577                         /* We always do complete word writes to eeprom. */
11578                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11579                 }
11580
11581                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11582                         break;
11583         }
11584         return ret;
11585 }
11586
11587 /* offset and length are dword aligned */
11588 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11589 {
11590         int ret;
11591
11592         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11593                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11594                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11595                 udelay(40);
11596         }
11597
11598         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11599                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11600         }
11601         else {
11602                 u32 grc_mode;
11603
11604                 ret = tg3_nvram_lock(tp);
11605                 if (ret)
11606                         return ret;
11607
11608                 tg3_enable_nvram_access(tp);
11609                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11610                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11611                         tw32(NVRAM_WRITE1, 0x406);
11612
11613                 grc_mode = tr32(GRC_MODE);
11614                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11615
11616                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11617                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11618
11619                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11620                                 buf);
11621                 }
11622                 else {
11623                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11624                                 buf);
11625                 }
11626
11627                 grc_mode = tr32(GRC_MODE);
11628                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11629
11630                 tg3_disable_nvram_access(tp);
11631                 tg3_nvram_unlock(tp);
11632         }
11633
11634         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11635                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11636                 udelay(40);
11637         }
11638
11639         return ret;
11640 }
11641
11642 struct subsys_tbl_ent {
11643         u16 subsys_vendor, subsys_devid;
11644         u32 phy_id;
11645 };
11646
11647 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11648         /* Broadcom boards. */
11649         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11650         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11651         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11652         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11653         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11654         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11655         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11656         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11657         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11658         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11659         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11660
11661         /* 3com boards. */
11662         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11663         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11664         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11665         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11666         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11667
11668         /* DELL boards. */
11669         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11670         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11671         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11672         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11673
11674         /* Compaq boards. */
11675         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11676         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11677         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11678         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11679         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11680
11681         /* IBM boards. */
11682         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11683 };
11684
11685 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11686 {
11687         int i;
11688
11689         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11690                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11691                      tp->pdev->subsystem_vendor) &&
11692                     (subsys_id_to_phy_id[i].subsys_devid ==
11693                      tp->pdev->subsystem_device))
11694                         return &subsys_id_to_phy_id[i];
11695         }
11696         return NULL;
11697 }
11698
11699 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11700 {
11701         u32 val;
11702         u16 pmcsr;
11703
11704         /* On some early chips the SRAM cannot be accessed in D3hot state,
11705          * so need make sure we're in D0.
11706          */
11707         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11708         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11709         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11710         msleep(1);
11711
11712         /* Make sure register accesses (indirect or otherwise)
11713          * will function correctly.
11714          */
11715         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11716                                tp->misc_host_ctrl);
11717
11718         /* The memory arbiter has to be enabled in order for SRAM accesses
11719          * to succeed.  Normally on powerup the tg3 chip firmware will make
11720          * sure it is enabled, but other entities such as system netboot
11721          * code might disable it.
11722          */
11723         val = tr32(MEMARB_MODE);
11724         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11725
11726         tp->phy_id = PHY_ID_INVALID;
11727         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11728
11729         /* Assume an onboard device and WOL capable by default.  */
11730         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11731
11732         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11733                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11734                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11735                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11736                 }
11737                 val = tr32(VCPU_CFGSHDW);
11738                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11739                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11740                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11741                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11742                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11743                 goto done;
11744         }
11745
11746         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11747         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11748                 u32 nic_cfg, led_cfg;
11749                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11750                 int eeprom_phy_serdes = 0;
11751
11752                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11753                 tp->nic_sram_data_cfg = nic_cfg;
11754
11755                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11756                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11757                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11758                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11759                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11760                     (ver > 0) && (ver < 0x100))
11761                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11762
11763                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11764                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11765
11766                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11767                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11768                         eeprom_phy_serdes = 1;
11769
11770                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11771                 if (nic_phy_id != 0) {
11772                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11773                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11774
11775                         eeprom_phy_id  = (id1 >> 16) << 10;
11776                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11777                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11778                 } else
11779                         eeprom_phy_id = 0;
11780
11781                 tp->phy_id = eeprom_phy_id;
11782                 if (eeprom_phy_serdes) {
11783                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11784                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11785                         else
11786                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11787                 }
11788
11789                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11790                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11791                                     SHASTA_EXT_LED_MODE_MASK);
11792                 else
11793                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11794
11795                 switch (led_cfg) {
11796                 default:
11797                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11798                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11799                         break;
11800
11801                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11802                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11803                         break;
11804
11805                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11806                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11807
11808                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11809                          * read on some older 5700/5701 bootcode.
11810                          */
11811                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11812                             ASIC_REV_5700 ||
11813                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11814                             ASIC_REV_5701)
11815                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11816
11817                         break;
11818
11819                 case SHASTA_EXT_LED_SHARED:
11820                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11821                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11822                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11823                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11824                                                  LED_CTRL_MODE_PHY_2);
11825                         break;
11826
11827                 case SHASTA_EXT_LED_MAC:
11828                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11829                         break;
11830
11831                 case SHASTA_EXT_LED_COMBO:
11832                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11833                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11834                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11835                                                  LED_CTRL_MODE_PHY_2);
11836                         break;
11837
11838                 }
11839
11840                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11841                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11842                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11843                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11844
11845                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11846                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11847
11848                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11849                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11850                         if ((tp->pdev->subsystem_vendor ==
11851                              PCI_VENDOR_ID_ARIMA) &&
11852                             (tp->pdev->subsystem_device == 0x205a ||
11853                              tp->pdev->subsystem_device == 0x2063))
11854                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11855                 } else {
11856                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11857                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11858                 }
11859
11860                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11861                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11862                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11863                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11864                 }
11865
11866                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11867                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11868                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11869
11870                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11871                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11872                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11873
11874                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11875                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11876                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11877
11878                 if (cfg2 & (1 << 17))
11879                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11880
11881                 /* serdes signal pre-emphasis in register 0x590 set by */
11882                 /* bootcode if bit 18 is set */
11883                 if (cfg2 & (1 << 18))
11884                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11885
11886                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11887                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11888                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11889                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11890
11891                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11892                         u32 cfg3;
11893
11894                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11895                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11896                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11897                 }
11898
11899                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11900                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11901                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11902                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11903                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11904                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11905         }
11906 done:
11907         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11908         device_set_wakeup_enable(&tp->pdev->dev,
11909                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11910 }
11911
11912 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11913 {
11914         int i;
11915         u32 val;
11916
11917         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11918         tw32(OTP_CTRL, cmd);
11919
11920         /* Wait for up to 1 ms for command to execute. */
11921         for (i = 0; i < 100; i++) {
11922                 val = tr32(OTP_STATUS);
11923                 if (val & OTP_STATUS_CMD_DONE)
11924                         break;
11925                 udelay(10);
11926         }
11927
11928         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11929 }
11930
11931 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11932  * configuration is a 32-bit value that straddles the alignment boundary.
11933  * We do two 32-bit reads and then shift and merge the results.
11934  */
11935 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11936 {
11937         u32 bhalf_otp, thalf_otp;
11938
11939         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11940
11941         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11942                 return 0;
11943
11944         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11945
11946         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11947                 return 0;
11948
11949         thalf_otp = tr32(OTP_READ_DATA);
11950
11951         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11952
11953         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11954                 return 0;
11955
11956         bhalf_otp = tr32(OTP_READ_DATA);
11957
11958         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11959 }
11960
11961 static int __devinit tg3_phy_probe(struct tg3 *tp)
11962 {
11963         u32 hw_phy_id_1, hw_phy_id_2;
11964         u32 hw_phy_id, hw_phy_id_masked;
11965         int err;
11966
11967         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11968                 return tg3_phy_init(tp);
11969
11970         /* Reading the PHY ID register can conflict with ASF
11971          * firmware access to the PHY hardware.
11972          */
11973         err = 0;
11974         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11975             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11976                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11977         } else {
11978                 /* Now read the physical PHY_ID from the chip and verify
11979                  * that it is sane.  If it doesn't look good, we fall back
11980                  * to either the hard-coded table based PHY_ID and failing
11981                  * that the value found in the eeprom area.
11982                  */
11983                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11984                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11985
11986                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11987                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11988                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11989
11990                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11991         }
11992
11993         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11994                 tp->phy_id = hw_phy_id;
11995                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11996                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11997                 else
11998                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11999         } else {
12000                 if (tp->phy_id != PHY_ID_INVALID) {
12001                         /* Do nothing, phy ID already set up in
12002                          * tg3_get_eeprom_hw_cfg().
12003                          */
12004                 } else {
12005                         struct subsys_tbl_ent *p;
12006
12007                         /* No eeprom signature?  Try the hardcoded
12008                          * subsys device table.
12009                          */
12010                         p = lookup_by_subsys(tp);
12011                         if (!p)
12012                                 return -ENODEV;
12013
12014                         tp->phy_id = p->phy_id;
12015                         if (!tp->phy_id ||
12016                             tp->phy_id == PHY_ID_BCM8002)
12017                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12018                 }
12019         }
12020
12021         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12022             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12023             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12024                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12025
12026                 tg3_readphy(tp, MII_BMSR, &bmsr);
12027                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12028                     (bmsr & BMSR_LSTATUS))
12029                         goto skip_phy_reset;
12030
12031                 err = tg3_phy_reset(tp);
12032                 if (err)
12033                         return err;
12034
12035                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12036                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12037                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12038                 tg3_ctrl = 0;
12039                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12040                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12041                                     MII_TG3_CTRL_ADV_1000_FULL);
12042                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12043                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12044                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12045                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12046                 }
12047
12048                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12049                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12050                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12051                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12052                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12053
12054                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12055                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12056
12057                         tg3_writephy(tp, MII_BMCR,
12058                                      BMCR_ANENABLE | BMCR_ANRESTART);
12059                 }
12060                 tg3_phy_set_wirespeed(tp);
12061
12062                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12063                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12064                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12065         }
12066
12067 skip_phy_reset:
12068         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12069                 err = tg3_init_5401phy_dsp(tp);
12070                 if (err)
12071                         return err;
12072         }
12073
12074         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12075                 err = tg3_init_5401phy_dsp(tp);
12076         }
12077
12078         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12079                 tp->link_config.advertising =
12080                         (ADVERTISED_1000baseT_Half |
12081                          ADVERTISED_1000baseT_Full |
12082                          ADVERTISED_Autoneg |
12083                          ADVERTISED_FIBRE);
12084         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12085                 tp->link_config.advertising &=
12086                         ~(ADVERTISED_1000baseT_Half |
12087                           ADVERTISED_1000baseT_Full);
12088
12089         return err;
12090 }
12091
12092 static void __devinit tg3_read_partno(struct tg3 *tp)
12093 {
12094         unsigned char vpd_data[256];   /* in little-endian format */
12095         unsigned int i;
12096         u32 magic;
12097
12098         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12099             tg3_nvram_read(tp, 0x0, &magic))
12100                 goto out_not_found;
12101
12102         if (magic == TG3_EEPROM_MAGIC) {
12103                 for (i = 0; i < 256; i += 4) {
12104                         u32 tmp;
12105
12106                         /* The data is in little-endian format in NVRAM.
12107                          * Use the big-endian read routines to preserve
12108                          * the byte order as it exists in NVRAM.
12109                          */
12110                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12111                                 goto out_not_found;
12112
12113                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12114                 }
12115         } else {
12116                 int vpd_cap;
12117
12118                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12119                 for (i = 0; i < 256; i += 4) {
12120                         u32 tmp, j = 0;
12121                         __le32 v;
12122                         u16 tmp16;
12123
12124                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12125                                               i);
12126                         while (j++ < 100) {
12127                                 pci_read_config_word(tp->pdev, vpd_cap +
12128                                                      PCI_VPD_ADDR, &tmp16);
12129                                 if (tmp16 & 0x8000)
12130                                         break;
12131                                 msleep(1);
12132                         }
12133                         if (!(tmp16 & 0x8000))
12134                                 goto out_not_found;
12135
12136                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12137                                               &tmp);
12138                         v = cpu_to_le32(tmp);
12139                         memcpy(&vpd_data[i], &v, sizeof(v));
12140                 }
12141         }
12142
12143         /* Now parse and find the part number. */
12144         for (i = 0; i < 254; ) {
12145                 unsigned char val = vpd_data[i];
12146                 unsigned int block_end;
12147
12148                 if (val == 0x82 || val == 0x91) {
12149                         i = (i + 3 +
12150                              (vpd_data[i + 1] +
12151                               (vpd_data[i + 2] << 8)));
12152                         continue;
12153                 }
12154
12155                 if (val != 0x90)
12156                         goto out_not_found;
12157
12158                 block_end = (i + 3 +
12159                              (vpd_data[i + 1] +
12160                               (vpd_data[i + 2] << 8)));
12161                 i += 3;
12162
12163                 if (block_end > 256)
12164                         goto out_not_found;
12165
12166                 while (i < (block_end - 2)) {
12167                         if (vpd_data[i + 0] == 'P' &&
12168                             vpd_data[i + 1] == 'N') {
12169                                 int partno_len = vpd_data[i + 2];
12170
12171                                 i += 3;
12172                                 if (partno_len > 24 || (partno_len + i) > 256)
12173                                         goto out_not_found;
12174
12175                                 memcpy(tp->board_part_number,
12176                                        &vpd_data[i], partno_len);
12177
12178                                 /* Success. */
12179                                 return;
12180                         }
12181                         i += 3 + vpd_data[i + 2];
12182                 }
12183
12184                 /* Part number not found. */
12185                 goto out_not_found;
12186         }
12187
12188 out_not_found:
12189         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12190                 strcpy(tp->board_part_number, "BCM95906");
12191         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12192                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12193                 strcpy(tp->board_part_number, "BCM57780");
12194         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12195                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12196                 strcpy(tp->board_part_number, "BCM57760");
12197         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12198                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12199                 strcpy(tp->board_part_number, "BCM57790");
12200         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12201                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12202                 strcpy(tp->board_part_number, "BCM57788");
12203         else
12204                 strcpy(tp->board_part_number, "none");
12205 }
12206
12207 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12208 {
12209         u32 val;
12210
12211         if (tg3_nvram_read(tp, offset, &val) ||
12212             (val & 0xfc000000) != 0x0c000000 ||
12213             tg3_nvram_read(tp, offset + 4, &val) ||
12214             val != 0)
12215                 return 0;
12216
12217         return 1;
12218 }
12219
12220 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12221 {
12222         u32 val, offset, start, ver_offset;
12223         int i;
12224         bool newver = false;
12225
12226         if (tg3_nvram_read(tp, 0xc, &offset) ||
12227             tg3_nvram_read(tp, 0x4, &start))
12228                 return;
12229
12230         offset = tg3_nvram_logical_addr(tp, offset);
12231
12232         if (tg3_nvram_read(tp, offset, &val))
12233                 return;
12234
12235         if ((val & 0xfc000000) == 0x0c000000) {
12236                 if (tg3_nvram_read(tp, offset + 4, &val))
12237                         return;
12238
12239                 if (val == 0)
12240                         newver = true;
12241         }
12242
12243         if (newver) {
12244                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12245                         return;
12246
12247                 offset = offset + ver_offset - start;
12248                 for (i = 0; i < 16; i += 4) {
12249                         __be32 v;
12250                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12251                                 return;
12252
12253                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12254                 }
12255         } else {
12256                 u32 major, minor;
12257
12258                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12259                         return;
12260
12261                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12262                         TG3_NVM_BCVER_MAJSFT;
12263                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12264                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12265         }
12266 }
12267
12268 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12269 {
12270         u32 val, major, minor;
12271
12272         /* Use native endian representation */
12273         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12274                 return;
12275
12276         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12277                 TG3_NVM_HWSB_CFG1_MAJSFT;
12278         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12279                 TG3_NVM_HWSB_CFG1_MINSFT;
12280
12281         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12282 }
12283
12284 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12285 {
12286         u32 offset, major, minor, build;
12287
12288         tp->fw_ver[0] = 's';
12289         tp->fw_ver[1] = 'b';
12290         tp->fw_ver[2] = '\0';
12291
12292         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12293                 return;
12294
12295         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12296         case TG3_EEPROM_SB_REVISION_0:
12297                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12298                 break;
12299         case TG3_EEPROM_SB_REVISION_2:
12300                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12301                 break;
12302         case TG3_EEPROM_SB_REVISION_3:
12303                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12304                 break;
12305         default:
12306                 return;
12307         }
12308
12309         if (tg3_nvram_read(tp, offset, &val))
12310                 return;
12311
12312         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12313                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12314         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12315                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12316         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12317
12318         if (minor > 99 || build > 26)
12319                 return;
12320
12321         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12322
12323         if (build > 0) {
12324                 tp->fw_ver[8] = 'a' + build - 1;
12325                 tp->fw_ver[9] = '\0';
12326         }
12327 }
12328
12329 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12330 {
12331         u32 val, offset, start;
12332         int i, vlen;
12333
12334         for (offset = TG3_NVM_DIR_START;
12335              offset < TG3_NVM_DIR_END;
12336              offset += TG3_NVM_DIRENT_SIZE) {
12337                 if (tg3_nvram_read(tp, offset, &val))
12338                         return;
12339
12340                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12341                         break;
12342         }
12343
12344         if (offset == TG3_NVM_DIR_END)
12345                 return;
12346
12347         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12348                 start = 0x08000000;
12349         else if (tg3_nvram_read(tp, offset - 4, &start))
12350                 return;
12351
12352         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12353             !tg3_fw_img_is_valid(tp, offset) ||
12354             tg3_nvram_read(tp, offset + 8, &val))
12355                 return;
12356
12357         offset += val - start;
12358
12359         vlen = strlen(tp->fw_ver);
12360
12361         tp->fw_ver[vlen++] = ',';
12362         tp->fw_ver[vlen++] = ' ';
12363
12364         for (i = 0; i < 4; i++) {
12365                 __be32 v;
12366                 if (tg3_nvram_read_be32(tp, offset, &v))
12367                         return;
12368
12369                 offset += sizeof(v);
12370
12371                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12372                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12373                         break;
12374                 }
12375
12376                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12377                 vlen += sizeof(v);
12378         }
12379 }
12380
12381 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12382 {
12383         int vlen;
12384         u32 apedata;
12385
12386         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12387             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12388                 return;
12389
12390         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12391         if (apedata != APE_SEG_SIG_MAGIC)
12392                 return;
12393
12394         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12395         if (!(apedata & APE_FW_STATUS_READY))
12396                 return;
12397
12398         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12399
12400         vlen = strlen(tp->fw_ver);
12401
12402         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12403                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12404                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12405                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12406                  (apedata & APE_FW_VERSION_BLDMSK));
12407 }
12408
12409 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12410 {
12411         u32 val;
12412
12413         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12414                 tp->fw_ver[0] = 's';
12415                 tp->fw_ver[1] = 'b';
12416                 tp->fw_ver[2] = '\0';
12417
12418                 return;
12419         }
12420
12421         if (tg3_nvram_read(tp, 0, &val))
12422                 return;
12423
12424         if (val == TG3_EEPROM_MAGIC)
12425                 tg3_read_bc_ver(tp);
12426         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12427                 tg3_read_sb_ver(tp, val);
12428         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12429                 tg3_read_hwsb_ver(tp);
12430         else
12431                 return;
12432
12433         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12434              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12435                 return;
12436
12437         tg3_read_mgmtfw_ver(tp);
12438
12439         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12440 }
12441
12442 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12443
12444 static int __devinit tg3_get_invariants(struct tg3 *tp)
12445 {
12446         static struct pci_device_id write_reorder_chipsets[] = {
12447                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12448                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12449                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12450                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12451                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12452                              PCI_DEVICE_ID_VIA_8385_0) },
12453                 { },
12454         };
12455         u32 misc_ctrl_reg;
12456         u32 pci_state_reg, grc_misc_cfg;
12457         u32 val;
12458         u16 pci_cmd;
12459         int err;
12460
12461         /* Force memory write invalidate off.  If we leave it on,
12462          * then on 5700_BX chips we have to enable a workaround.
12463          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12464          * to match the cacheline size.  The Broadcom driver have this
12465          * workaround but turns MWI off all the times so never uses
12466          * it.  This seems to suggest that the workaround is insufficient.
12467          */
12468         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12469         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12470         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12471
12472         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12473          * has the register indirect write enable bit set before
12474          * we try to access any of the MMIO registers.  It is also
12475          * critical that the PCI-X hw workaround situation is decided
12476          * before that as well.
12477          */
12478         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12479                               &misc_ctrl_reg);
12480
12481         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12482                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12483         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12484                 u32 prod_id_asic_rev;
12485
12486                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12487                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12488                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12489                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12490                         pci_read_config_dword(tp->pdev,
12491                                               TG3PCI_GEN2_PRODID_ASICREV,
12492                                               &prod_id_asic_rev);
12493                 else
12494                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12495                                               &prod_id_asic_rev);
12496
12497                 tp->pci_chip_rev_id = prod_id_asic_rev;
12498         }
12499
12500         /* Wrong chip ID in 5752 A0. This code can be removed later
12501          * as A0 is not in production.
12502          */
12503         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12504                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12505
12506         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12507          * we need to disable memory and use config. cycles
12508          * only to access all registers. The 5702/03 chips
12509          * can mistakenly decode the special cycles from the
12510          * ICH chipsets as memory write cycles, causing corruption
12511          * of register and memory space. Only certain ICH bridges
12512          * will drive special cycles with non-zero data during the
12513          * address phase which can fall within the 5703's address
12514          * range. This is not an ICH bug as the PCI spec allows
12515          * non-zero address during special cycles. However, only
12516          * these ICH bridges are known to drive non-zero addresses
12517          * during special cycles.
12518          *
12519          * Since special cycles do not cross PCI bridges, we only
12520          * enable this workaround if the 5703 is on the secondary
12521          * bus of these ICH bridges.
12522          */
12523         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12524             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12525                 static struct tg3_dev_id {
12526                         u32     vendor;
12527                         u32     device;
12528                         u32     rev;
12529                 } ich_chipsets[] = {
12530                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12531                           PCI_ANY_ID },
12532                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12533                           PCI_ANY_ID },
12534                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12535                           0xa },
12536                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12537                           PCI_ANY_ID },
12538                         { },
12539                 };
12540                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12541                 struct pci_dev *bridge = NULL;
12542
12543                 while (pci_id->vendor != 0) {
12544                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12545                                                 bridge);
12546                         if (!bridge) {
12547                                 pci_id++;
12548                                 continue;
12549                         }
12550                         if (pci_id->rev != PCI_ANY_ID) {
12551                                 if (bridge->revision > pci_id->rev)
12552                                         continue;
12553                         }
12554                         if (bridge->subordinate &&
12555                             (bridge->subordinate->number ==
12556                              tp->pdev->bus->number)) {
12557
12558                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12559                                 pci_dev_put(bridge);
12560                                 break;
12561                         }
12562                 }
12563         }
12564
12565         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12566                 static struct tg3_dev_id {
12567                         u32     vendor;
12568                         u32     device;
12569                 } bridge_chipsets[] = {
12570                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12571                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12572                         { },
12573                 };
12574                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12575                 struct pci_dev *bridge = NULL;
12576
12577                 while (pci_id->vendor != 0) {
12578                         bridge = pci_get_device(pci_id->vendor,
12579                                                 pci_id->device,
12580                                                 bridge);
12581                         if (!bridge) {
12582                                 pci_id++;
12583                                 continue;
12584                         }
12585                         if (bridge->subordinate &&
12586                             (bridge->subordinate->number <=
12587                              tp->pdev->bus->number) &&
12588                             (bridge->subordinate->subordinate >=
12589                              tp->pdev->bus->number)) {
12590                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12591                                 pci_dev_put(bridge);
12592                                 break;
12593                         }
12594                 }
12595         }
12596
12597         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12598          * DMA addresses > 40-bit. This bridge may have other additional
12599          * 57xx devices behind it in some 4-port NIC designs for example.
12600          * Any tg3 device found behind the bridge will also need the 40-bit
12601          * DMA workaround.
12602          */
12603         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12604             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12605                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12606                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12607                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12608         }
12609         else {
12610                 struct pci_dev *bridge = NULL;
12611
12612                 do {
12613                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12614                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12615                                                 bridge);
12616                         if (bridge && bridge->subordinate &&
12617                             (bridge->subordinate->number <=
12618                              tp->pdev->bus->number) &&
12619                             (bridge->subordinate->subordinate >=
12620                              tp->pdev->bus->number)) {
12621                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12622                                 pci_dev_put(bridge);
12623                                 break;
12624                         }
12625                 } while (bridge);
12626         }
12627
12628         /* Initialize misc host control in PCI block. */
12629         tp->misc_host_ctrl |= (misc_ctrl_reg &
12630                                MISC_HOST_CTRL_CHIPREV);
12631         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12632                                tp->misc_host_ctrl);
12633
12634         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12635             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12636             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12637                 tp->pdev_peer = tg3_find_peer(tp);
12638
12639         /* Intentionally exclude ASIC_REV_5906 */
12640         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12641             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12642             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12643             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12644             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12645             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12646             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12647                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12648
12649         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12650             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12651             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12652             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12653             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12654                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12655
12656         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12657             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12658                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12659
12660         /* 5700 B0 chips do not support checksumming correctly due
12661          * to hardware bugs.
12662          */
12663         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12664                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12665         else {
12666                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12667                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12668                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12669                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12670         }
12671
12672         /* Determine TSO capabilities */
12673         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12674             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12675                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12676         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12677                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12678                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12679                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12680                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12681         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12682                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12683                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12684                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12685                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12686                         tp->fw_needed = FIRMWARE_TG3TSO5;
12687                 else
12688                         tp->fw_needed = FIRMWARE_TG3TSO;
12689         }
12690
12691         tp->irq_max = 1;
12692
12693         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12694                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12695                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12696                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12697                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12698                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12699                      tp->pdev_peer == tp->pdev))
12700                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12701
12702                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12703                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12704                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12705                 }
12706
12707                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12708                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12709                         tp->irq_max = TG3_IRQ_MAX_VECS;
12710                 }
12711         }
12712
12713         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12714                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12715                         tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12716                 else {
12717                         tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12718                         tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12719                 }
12720         }
12721
12722         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12723              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12724             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12725                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12726
12727         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12728                               &pci_state_reg);
12729
12730         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12731         if (tp->pcie_cap != 0) {
12732                 u16 lnkctl;
12733
12734                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12735
12736                 pcie_set_readrq(tp->pdev, 4096);
12737
12738                 pci_read_config_word(tp->pdev,
12739                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12740                                      &lnkctl);
12741                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12742                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12743                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12744                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12745                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12746                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12747                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12748                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12749                 }
12750         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12751                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12752         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12753                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12754                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12755                 if (!tp->pcix_cap) {
12756                         printk(KERN_ERR PFX "Cannot find PCI-X "
12757                                             "capability, aborting.\n");
12758                         return -EIO;
12759                 }
12760
12761                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12762                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12763         }
12764
12765         /* If we have an AMD 762 or VIA K8T800 chipset, write
12766          * reordering to the mailbox registers done by the host
12767          * controller can cause major troubles.  We read back from
12768          * every mailbox register write to force the writes to be
12769          * posted to the chip in order.
12770          */
12771         if (pci_dev_present(write_reorder_chipsets) &&
12772             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12773                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12774
12775         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12776                              &tp->pci_cacheline_sz);
12777         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12778                              &tp->pci_lat_timer);
12779         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12780             tp->pci_lat_timer < 64) {
12781                 tp->pci_lat_timer = 64;
12782                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12783                                       tp->pci_lat_timer);
12784         }
12785
12786         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12787                 /* 5700 BX chips need to have their TX producer index
12788                  * mailboxes written twice to workaround a bug.
12789                  */
12790                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12791
12792                 /* If we are in PCI-X mode, enable register write workaround.
12793                  *
12794                  * The workaround is to use indirect register accesses
12795                  * for all chip writes not to mailbox registers.
12796                  */
12797                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12798                         u32 pm_reg;
12799
12800                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12801
12802                         /* The chip can have it's power management PCI config
12803                          * space registers clobbered due to this bug.
12804                          * So explicitly force the chip into D0 here.
12805                          */
12806                         pci_read_config_dword(tp->pdev,
12807                                               tp->pm_cap + PCI_PM_CTRL,
12808                                               &pm_reg);
12809                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12810                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12811                         pci_write_config_dword(tp->pdev,
12812                                                tp->pm_cap + PCI_PM_CTRL,
12813                                                pm_reg);
12814
12815                         /* Also, force SERR#/PERR# in PCI command. */
12816                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12817                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12818                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12819                 }
12820         }
12821
12822         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12823                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12824         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12825                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12826
12827         /* Chip-specific fixup from Broadcom driver */
12828         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12829             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12830                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12831                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12832         }
12833
12834         /* Default fast path register access methods */
12835         tp->read32 = tg3_read32;
12836         tp->write32 = tg3_write32;
12837         tp->read32_mbox = tg3_read32;
12838         tp->write32_mbox = tg3_write32;
12839         tp->write32_tx_mbox = tg3_write32;
12840         tp->write32_rx_mbox = tg3_write32;
12841
12842         /* Various workaround register access methods */
12843         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12844                 tp->write32 = tg3_write_indirect_reg32;
12845         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12846                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12847                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12848                 /*
12849                  * Back to back register writes can cause problems on these
12850                  * chips, the workaround is to read back all reg writes
12851                  * except those to mailbox regs.
12852                  *
12853                  * See tg3_write_indirect_reg32().
12854                  */
12855                 tp->write32 = tg3_write_flush_reg32;
12856         }
12857
12858         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12859             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12860                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12861                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12862                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12863         }
12864
12865         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12866                 tp->read32 = tg3_read_indirect_reg32;
12867                 tp->write32 = tg3_write_indirect_reg32;
12868                 tp->read32_mbox = tg3_read_indirect_mbox;
12869                 tp->write32_mbox = tg3_write_indirect_mbox;
12870                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12871                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12872
12873                 iounmap(tp->regs);
12874                 tp->regs = NULL;
12875
12876                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12877                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12878                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12879         }
12880         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12881                 tp->read32_mbox = tg3_read32_mbox_5906;
12882                 tp->write32_mbox = tg3_write32_mbox_5906;
12883                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12884                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12885         }
12886
12887         if (tp->write32 == tg3_write_indirect_reg32 ||
12888             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12889              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12890               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12891                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12892
12893         /* Get eeprom hw config before calling tg3_set_power_state().
12894          * In particular, the TG3_FLG2_IS_NIC flag must be
12895          * determined before calling tg3_set_power_state() so that
12896          * we know whether or not to switch out of Vaux power.
12897          * When the flag is set, it means that GPIO1 is used for eeprom
12898          * write protect and also implies that it is a LOM where GPIOs
12899          * are not used to switch power.
12900          */
12901         tg3_get_eeprom_hw_cfg(tp);
12902
12903         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12904                 /* Allow reads and writes to the
12905                  * APE register and memory space.
12906                  */
12907                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12908                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12909                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12910                                        pci_state_reg);
12911         }
12912
12913         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12914             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12915             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12916             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12917             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12918                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12919
12920         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12921          * GPIO1 driven high will bring 5700's external PHY out of reset.
12922          * It is also used as eeprom write protect on LOMs.
12923          */
12924         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12925         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12926             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12927                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12928                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12929         /* Unused GPIO3 must be driven as output on 5752 because there
12930          * are no pull-up resistors on unused GPIO pins.
12931          */
12932         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12933                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12934
12935         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12936             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12937                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12938
12939         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12940             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12941                 /* Turn off the debug UART. */
12942                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12943                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12944                         /* Keep VMain power. */
12945                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12946                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12947         }
12948
12949         /* Force the chip into D0. */
12950         err = tg3_set_power_state(tp, PCI_D0);
12951         if (err) {
12952                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12953                        pci_name(tp->pdev));
12954                 return err;
12955         }
12956
12957         /* Derive initial jumbo mode from MTU assigned in
12958          * ether_setup() via the alloc_etherdev() call
12959          */
12960         if (tp->dev->mtu > ETH_DATA_LEN &&
12961             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12962                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12963
12964         /* Determine WakeOnLan speed to use. */
12965         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12966             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12967             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12968             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12969                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12970         } else {
12971                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12972         }
12973
12974         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12975                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12976
12977         /* A few boards don't want Ethernet@WireSpeed phy feature */
12978         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12979             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12980              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12981              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12982             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12983             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12984                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12985
12986         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12987             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12988                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12989         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12990                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12991
12992         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12993             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12994             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12995             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12996             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12997                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12998                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12999                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13000                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13001                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13002                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13003                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13004                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13005                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13006                 } else
13007                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13008         }
13009
13010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13011             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13012                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13013                 if (tp->phy_otp == 0)
13014                         tp->phy_otp = TG3_OTP_DEFAULT;
13015         }
13016
13017         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13018                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13019         else
13020                 tp->mi_mode = MAC_MI_MODE_BASE;
13021
13022         tp->coalesce_mode = 0;
13023         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13024             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13025                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13026
13027         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13029                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13030
13031         err = tg3_mdio_init(tp);
13032         if (err)
13033                 return err;
13034
13035         /* Initialize data/descriptor byte/word swapping. */
13036         val = tr32(GRC_MODE);
13037         val &= GRC_MODE_HOST_STACKUP;
13038         tw32(GRC_MODE, val | tp->grc_mode);
13039
13040         tg3_switch_clocks(tp);
13041
13042         /* Clear this out for sanity. */
13043         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13044
13045         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13046                               &pci_state_reg);
13047         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13048             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13049                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13050
13051                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13052                     chiprevid == CHIPREV_ID_5701_B0 ||
13053                     chiprevid == CHIPREV_ID_5701_B2 ||
13054                     chiprevid == CHIPREV_ID_5701_B5) {
13055                         void __iomem *sram_base;
13056
13057                         /* Write some dummy words into the SRAM status block
13058                          * area, see if it reads back correctly.  If the return
13059                          * value is bad, force enable the PCIX workaround.
13060                          */
13061                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13062
13063                         writel(0x00000000, sram_base);
13064                         writel(0x00000000, sram_base + 4);
13065                         writel(0xffffffff, sram_base + 4);
13066                         if (readl(sram_base) != 0x00000000)
13067                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13068                 }
13069         }
13070
13071         udelay(50);
13072         tg3_nvram_init(tp);
13073
13074         grc_misc_cfg = tr32(GRC_MISC_CFG);
13075         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13076
13077         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13078             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13079              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13080                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13081
13082         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13083             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13084                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13085         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13086                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13087                                       HOSTCC_MODE_CLRTICK_TXBD);
13088
13089                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13090                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13091                                        tp->misc_host_ctrl);
13092         }
13093
13094         /* Preserve the APE MAC_MODE bits */
13095         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13096                 tp->mac_mode = tr32(MAC_MODE) |
13097                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13098         else
13099                 tp->mac_mode = TG3_DEF_MAC_MODE;
13100
13101         /* these are limited to 10/100 only */
13102         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13103              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13104             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13105              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13106              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13107               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13108               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13109             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13110              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13111               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13112               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13113             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13114             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13115                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13116
13117         err = tg3_phy_probe(tp);
13118         if (err) {
13119                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13120                        pci_name(tp->pdev), err);
13121                 /* ... but do not return immediately ... */
13122                 tg3_mdio_fini(tp);
13123         }
13124
13125         tg3_read_partno(tp);
13126         tg3_read_fw_ver(tp);
13127
13128         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13129                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13130         } else {
13131                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13132                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13133                 else
13134                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13135         }
13136
13137         /* 5700 {AX,BX} chips have a broken status block link
13138          * change bit implementation, so we must use the
13139          * status register in those cases.
13140          */
13141         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13142                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13143         else
13144                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13145
13146         /* The led_ctrl is set during tg3_phy_probe, here we might
13147          * have to force the link status polling mechanism based
13148          * upon subsystem IDs.
13149          */
13150         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13151             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13152             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13153                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13154                                   TG3_FLAG_USE_LINKCHG_REG);
13155         }
13156
13157         /* For all SERDES we poll the MAC status register. */
13158         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13159                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13160         else
13161                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13162
13163         tp->rx_offset = NET_IP_ALIGN;
13164         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13165             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13166                 tp->rx_offset = 0;
13167
13168         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13169
13170         /* Increment the rx prod index on the rx std ring by at most
13171          * 8 for these chips to workaround hw errata.
13172          */
13173         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13174             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13175             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13176                 tp->rx_std_max_post = 8;
13177
13178         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13179                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13180                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13181
13182         return err;
13183 }
13184
13185 #ifdef CONFIG_SPARC
13186 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13187 {
13188         struct net_device *dev = tp->dev;
13189         struct pci_dev *pdev = tp->pdev;
13190         struct device_node *dp = pci_device_to_OF_node(pdev);
13191         const unsigned char *addr;
13192         int len;
13193
13194         addr = of_get_property(dp, "local-mac-address", &len);
13195         if (addr && len == 6) {
13196                 memcpy(dev->dev_addr, addr, 6);
13197                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13198                 return 0;
13199         }
13200         return -ENODEV;
13201 }
13202
13203 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13204 {
13205         struct net_device *dev = tp->dev;
13206
13207         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13208         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13209         return 0;
13210 }
13211 #endif
13212
13213 static int __devinit tg3_get_device_address(struct tg3 *tp)
13214 {
13215         struct net_device *dev = tp->dev;
13216         u32 hi, lo, mac_offset;
13217         int addr_ok = 0;
13218
13219 #ifdef CONFIG_SPARC
13220         if (!tg3_get_macaddr_sparc(tp))
13221                 return 0;
13222 #endif
13223
13224         mac_offset = 0x7c;
13225         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13226             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13227                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13228                         mac_offset = 0xcc;
13229                 if (tg3_nvram_lock(tp))
13230                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13231                 else
13232                         tg3_nvram_unlock(tp);
13233         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13234                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13235                         mac_offset = 0xcc;
13236         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13237                 mac_offset = 0x10;
13238
13239         /* First try to get it from MAC address mailbox. */
13240         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13241         if ((hi >> 16) == 0x484b) {
13242                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13243                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13244
13245                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13246                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13247                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13248                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13249                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13250
13251                 /* Some old bootcode may report a 0 MAC address in SRAM */
13252                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13253         }
13254         if (!addr_ok) {
13255                 /* Next, try NVRAM. */
13256                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13257                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13258                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13259                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13260                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13261                 }
13262                 /* Finally just fetch it out of the MAC control regs. */
13263                 else {
13264                         hi = tr32(MAC_ADDR_0_HIGH);
13265                         lo = tr32(MAC_ADDR_0_LOW);
13266
13267                         dev->dev_addr[5] = lo & 0xff;
13268                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13269                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13270                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13271                         dev->dev_addr[1] = hi & 0xff;
13272                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13273                 }
13274         }
13275
13276         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13277 #ifdef CONFIG_SPARC
13278                 if (!tg3_get_default_macaddr_sparc(tp))
13279                         return 0;
13280 #endif
13281                 return -EINVAL;
13282         }
13283         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13284         return 0;
13285 }
13286
13287 #define BOUNDARY_SINGLE_CACHELINE       1
13288 #define BOUNDARY_MULTI_CACHELINE        2
13289
13290 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13291 {
13292         int cacheline_size;
13293         u8 byte;
13294         int goal;
13295
13296         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13297         if (byte == 0)
13298                 cacheline_size = 1024;
13299         else
13300                 cacheline_size = (int) byte * 4;
13301
13302         /* On 5703 and later chips, the boundary bits have no
13303          * effect.
13304          */
13305         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13306             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13307             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13308                 goto out;
13309
13310 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13311         goal = BOUNDARY_MULTI_CACHELINE;
13312 #else
13313 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13314         goal = BOUNDARY_SINGLE_CACHELINE;
13315 #else
13316         goal = 0;
13317 #endif
13318 #endif
13319
13320         if (!goal)
13321                 goto out;
13322
13323         /* PCI controllers on most RISC systems tend to disconnect
13324          * when a device tries to burst across a cache-line boundary.
13325          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13326          *
13327          * Unfortunately, for PCI-E there are only limited
13328          * write-side controls for this, and thus for reads
13329          * we will still get the disconnects.  We'll also waste
13330          * these PCI cycles for both read and write for chips
13331          * other than 5700 and 5701 which do not implement the
13332          * boundary bits.
13333          */
13334         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13335             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13336                 switch (cacheline_size) {
13337                 case 16:
13338                 case 32:
13339                 case 64:
13340                 case 128:
13341                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13342                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13343                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13344                         } else {
13345                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13346                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13347                         }
13348                         break;
13349
13350                 case 256:
13351                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13352                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13353                         break;
13354
13355                 default:
13356                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13357                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13358                         break;
13359                 }
13360         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13361                 switch (cacheline_size) {
13362                 case 16:
13363                 case 32:
13364                 case 64:
13365                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13366                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13367                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13368                                 break;
13369                         }
13370                         /* fallthrough */
13371                 case 128:
13372                 default:
13373                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13374                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13375                         break;
13376                 }
13377         } else {
13378                 switch (cacheline_size) {
13379                 case 16:
13380                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13381                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13382                                         DMA_RWCTRL_WRITE_BNDRY_16);
13383                                 break;
13384                         }
13385                         /* fallthrough */
13386                 case 32:
13387                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13388                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13389                                         DMA_RWCTRL_WRITE_BNDRY_32);
13390                                 break;
13391                         }
13392                         /* fallthrough */
13393                 case 64:
13394                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13395                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13396                                         DMA_RWCTRL_WRITE_BNDRY_64);
13397                                 break;
13398                         }
13399                         /* fallthrough */
13400                 case 128:
13401                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13402                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13403                                         DMA_RWCTRL_WRITE_BNDRY_128);
13404                                 break;
13405                         }
13406                         /* fallthrough */
13407                 case 256:
13408                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13409                                 DMA_RWCTRL_WRITE_BNDRY_256);
13410                         break;
13411                 case 512:
13412                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13413                                 DMA_RWCTRL_WRITE_BNDRY_512);
13414                         break;
13415                 case 1024:
13416                 default:
13417                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13418                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13419                         break;
13420                 }
13421         }
13422
13423 out:
13424         return val;
13425 }
13426
13427 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13428 {
13429         struct tg3_internal_buffer_desc test_desc;
13430         u32 sram_dma_descs;
13431         int i, ret;
13432
13433         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13434
13435         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13436         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13437         tw32(RDMAC_STATUS, 0);
13438         tw32(WDMAC_STATUS, 0);
13439
13440         tw32(BUFMGR_MODE, 0);
13441         tw32(FTQ_RESET, 0);
13442
13443         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13444         test_desc.addr_lo = buf_dma & 0xffffffff;
13445         test_desc.nic_mbuf = 0x00002100;
13446         test_desc.len = size;
13447
13448         /*
13449          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13450          * the *second* time the tg3 driver was getting loaded after an
13451          * initial scan.
13452          *
13453          * Broadcom tells me:
13454          *   ...the DMA engine is connected to the GRC block and a DMA
13455          *   reset may affect the GRC block in some unpredictable way...
13456          *   The behavior of resets to individual blocks has not been tested.
13457          *
13458          * Broadcom noted the GRC reset will also reset all sub-components.
13459          */
13460         if (to_device) {
13461                 test_desc.cqid_sqid = (13 << 8) | 2;
13462
13463                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13464                 udelay(40);
13465         } else {
13466                 test_desc.cqid_sqid = (16 << 8) | 7;
13467
13468                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13469                 udelay(40);
13470         }
13471         test_desc.flags = 0x00000005;
13472
13473         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13474                 u32 val;
13475
13476                 val = *(((u32 *)&test_desc) + i);
13477                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13478                                        sram_dma_descs + (i * sizeof(u32)));
13479                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13480         }
13481         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13482
13483         if (to_device) {
13484                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13485         } else {
13486                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13487         }
13488
13489         ret = -ENODEV;
13490         for (i = 0; i < 40; i++) {
13491                 u32 val;
13492
13493                 if (to_device)
13494                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13495                 else
13496                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13497                 if ((val & 0xffff) == sram_dma_descs) {
13498                         ret = 0;
13499                         break;
13500                 }
13501
13502                 udelay(100);
13503         }
13504
13505         return ret;
13506 }
13507
13508 #define TEST_BUFFER_SIZE        0x2000
13509
13510 static int __devinit tg3_test_dma(struct tg3 *tp)
13511 {
13512         dma_addr_t buf_dma;
13513         u32 *buf, saved_dma_rwctrl;
13514         int ret;
13515
13516         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13517         if (!buf) {
13518                 ret = -ENOMEM;
13519                 goto out_nofree;
13520         }
13521
13522         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13523                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13524
13525         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13526
13527         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13528                 /* DMA read watermark not used on PCIE */
13529                 tp->dma_rwctrl |= 0x00180000;
13530         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13531                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13532                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13533                         tp->dma_rwctrl |= 0x003f0000;
13534                 else
13535                         tp->dma_rwctrl |= 0x003f000f;
13536         } else {
13537                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13538                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13539                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13540                         u32 read_water = 0x7;
13541
13542                         /* If the 5704 is behind the EPB bridge, we can
13543                          * do the less restrictive ONE_DMA workaround for
13544                          * better performance.
13545                          */
13546                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13547                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13548                                 tp->dma_rwctrl |= 0x8000;
13549                         else if (ccval == 0x6 || ccval == 0x7)
13550                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13551
13552                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13553                                 read_water = 4;
13554                         /* Set bit 23 to enable PCIX hw bug fix */
13555                         tp->dma_rwctrl |=
13556                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13557                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13558                                 (1 << 23);
13559                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13560                         /* 5780 always in PCIX mode */
13561                         tp->dma_rwctrl |= 0x00144000;
13562                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13563                         /* 5714 always in PCIX mode */
13564                         tp->dma_rwctrl |= 0x00148000;
13565                 } else {
13566                         tp->dma_rwctrl |= 0x001b000f;
13567                 }
13568         }
13569
13570         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13571             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13572                 tp->dma_rwctrl &= 0xfffffff0;
13573
13574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13575             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13576                 /* Remove this if it causes problems for some boards. */
13577                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13578
13579                 /* On 5700/5701 chips, we need to set this bit.
13580                  * Otherwise the chip will issue cacheline transactions
13581                  * to streamable DMA memory with not all the byte
13582                  * enables turned on.  This is an error on several
13583                  * RISC PCI controllers, in particular sparc64.
13584                  *
13585                  * On 5703/5704 chips, this bit has been reassigned
13586                  * a different meaning.  In particular, it is used
13587                  * on those chips to enable a PCI-X workaround.
13588                  */
13589                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13590         }
13591
13592         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13593
13594 #if 0
13595         /* Unneeded, already done by tg3_get_invariants.  */
13596         tg3_switch_clocks(tp);
13597 #endif
13598
13599         ret = 0;
13600         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13601             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13602                 goto out;
13603
13604         /* It is best to perform DMA test with maximum write burst size
13605          * to expose the 5700/5701 write DMA bug.
13606          */
13607         saved_dma_rwctrl = tp->dma_rwctrl;
13608         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13609         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13610
13611         while (1) {
13612                 u32 *p = buf, i;
13613
13614                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13615                         p[i] = i;
13616
13617                 /* Send the buffer to the chip. */
13618                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13619                 if (ret) {
13620                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13621                         break;
13622                 }
13623
13624 #if 0
13625                 /* validate data reached card RAM correctly. */
13626                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13627                         u32 val;
13628                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13629                         if (le32_to_cpu(val) != p[i]) {
13630                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13631                                 /* ret = -ENODEV here? */
13632                         }
13633                         p[i] = 0;
13634                 }
13635 #endif
13636                 /* Now read it back. */
13637                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13638                 if (ret) {
13639                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13640
13641                         break;
13642                 }
13643
13644                 /* Verify it. */
13645                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13646                         if (p[i] == i)
13647                                 continue;
13648
13649                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13650                             DMA_RWCTRL_WRITE_BNDRY_16) {
13651                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13652                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13653                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13654                                 break;
13655                         } else {
13656                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13657                                 ret = -ENODEV;
13658                                 goto out;
13659                         }
13660                 }
13661
13662                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13663                         /* Success. */
13664                         ret = 0;
13665                         break;
13666                 }
13667         }
13668         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13669             DMA_RWCTRL_WRITE_BNDRY_16) {
13670                 static struct pci_device_id dma_wait_state_chipsets[] = {
13671                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13672                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13673                         { },
13674                 };
13675
13676                 /* DMA test passed without adjusting DMA boundary,
13677                  * now look for chipsets that are known to expose the
13678                  * DMA bug without failing the test.
13679                  */
13680                 if (pci_dev_present(dma_wait_state_chipsets)) {
13681                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13682                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13683                 }
13684                 else
13685                         /* Safe to use the calculated DMA boundary. */
13686                         tp->dma_rwctrl = saved_dma_rwctrl;
13687
13688                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13689         }
13690
13691 out:
13692         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13693 out_nofree:
13694         return ret;
13695 }
13696
13697 static void __devinit tg3_init_link_config(struct tg3 *tp)
13698 {
13699         tp->link_config.advertising =
13700                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13701                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13702                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13703                  ADVERTISED_Autoneg | ADVERTISED_MII);
13704         tp->link_config.speed = SPEED_INVALID;
13705         tp->link_config.duplex = DUPLEX_INVALID;
13706         tp->link_config.autoneg = AUTONEG_ENABLE;
13707         tp->link_config.active_speed = SPEED_INVALID;
13708         tp->link_config.active_duplex = DUPLEX_INVALID;
13709         tp->link_config.phy_is_low_power = 0;
13710         tp->link_config.orig_speed = SPEED_INVALID;
13711         tp->link_config.orig_duplex = DUPLEX_INVALID;
13712         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13713 }
13714
13715 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13716 {
13717         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13718             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13719                 tp->bufmgr_config.mbuf_read_dma_low_water =
13720                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13721                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13722                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13723                 tp->bufmgr_config.mbuf_high_water =
13724                         DEFAULT_MB_HIGH_WATER_5705;
13725                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13726                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13727                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13728                         tp->bufmgr_config.mbuf_high_water =
13729                                 DEFAULT_MB_HIGH_WATER_5906;
13730                 }
13731
13732                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13733                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13734                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13735                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13736                 tp->bufmgr_config.mbuf_high_water_jumbo =
13737                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13738         } else {
13739                 tp->bufmgr_config.mbuf_read_dma_low_water =
13740                         DEFAULT_MB_RDMA_LOW_WATER;
13741                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13742                         DEFAULT_MB_MACRX_LOW_WATER;
13743                 tp->bufmgr_config.mbuf_high_water =
13744                         DEFAULT_MB_HIGH_WATER;
13745
13746                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13747                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13748                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13749                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13750                 tp->bufmgr_config.mbuf_high_water_jumbo =
13751                         DEFAULT_MB_HIGH_WATER_JUMBO;
13752         }
13753
13754         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13755         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13756 }
13757
13758 static char * __devinit tg3_phy_string(struct tg3 *tp)
13759 {
13760         switch (tp->phy_id & PHY_ID_MASK) {
13761         case PHY_ID_BCM5400:    return "5400";
13762         case PHY_ID_BCM5401:    return "5401";
13763         case PHY_ID_BCM5411:    return "5411";
13764         case PHY_ID_BCM5701:    return "5701";
13765         case PHY_ID_BCM5703:    return "5703";
13766         case PHY_ID_BCM5704:    return "5704";
13767         case PHY_ID_BCM5705:    return "5705";
13768         case PHY_ID_BCM5750:    return "5750";
13769         case PHY_ID_BCM5752:    return "5752";
13770         case PHY_ID_BCM5714:    return "5714";
13771         case PHY_ID_BCM5780:    return "5780";
13772         case PHY_ID_BCM5755:    return "5755";
13773         case PHY_ID_BCM5787:    return "5787";
13774         case PHY_ID_BCM5784:    return "5784";
13775         case PHY_ID_BCM5756:    return "5722/5756";
13776         case PHY_ID_BCM5906:    return "5906";
13777         case PHY_ID_BCM5761:    return "5761";
13778         case PHY_ID_BCM5717:    return "5717";
13779         case PHY_ID_BCM8002:    return "8002/serdes";
13780         case 0:                 return "serdes";
13781         default:                return "unknown";
13782         }
13783 }
13784
13785 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13786 {
13787         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13788                 strcpy(str, "PCI Express");
13789                 return str;
13790         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13791                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13792
13793                 strcpy(str, "PCIX:");
13794
13795                 if ((clock_ctrl == 7) ||
13796                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13797                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13798                         strcat(str, "133MHz");
13799                 else if (clock_ctrl == 0)
13800                         strcat(str, "33MHz");
13801                 else if (clock_ctrl == 2)
13802                         strcat(str, "50MHz");
13803                 else if (clock_ctrl == 4)
13804                         strcat(str, "66MHz");
13805                 else if (clock_ctrl == 6)
13806                         strcat(str, "100MHz");
13807         } else {
13808                 strcpy(str, "PCI:");
13809                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13810                         strcat(str, "66MHz");
13811                 else
13812                         strcat(str, "33MHz");
13813         }
13814         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13815                 strcat(str, ":32-bit");
13816         else
13817                 strcat(str, ":64-bit");
13818         return str;
13819 }
13820
13821 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13822 {
13823         struct pci_dev *peer;
13824         unsigned int func, devnr = tp->pdev->devfn & ~7;
13825
13826         for (func = 0; func < 8; func++) {
13827                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13828                 if (peer && peer != tp->pdev)
13829                         break;
13830                 pci_dev_put(peer);
13831         }
13832         /* 5704 can be configured in single-port mode, set peer to
13833          * tp->pdev in that case.
13834          */
13835         if (!peer) {
13836                 peer = tp->pdev;
13837                 return peer;
13838         }
13839
13840         /*
13841          * We don't need to keep the refcount elevated; there's no way
13842          * to remove one half of this device without removing the other
13843          */
13844         pci_dev_put(peer);
13845
13846         return peer;
13847 }
13848
13849 static void __devinit tg3_init_coal(struct tg3 *tp)
13850 {
13851         struct ethtool_coalesce *ec = &tp->coal;
13852
13853         memset(ec, 0, sizeof(*ec));
13854         ec->cmd = ETHTOOL_GCOALESCE;
13855         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13856         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13857         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13858         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13859         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13860         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13861         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13862         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13863         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13864
13865         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13866                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13867                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13868                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13869                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13870                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13871         }
13872
13873         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13874                 ec->rx_coalesce_usecs_irq = 0;
13875                 ec->tx_coalesce_usecs_irq = 0;
13876                 ec->stats_block_coalesce_usecs = 0;
13877         }
13878 }
13879
13880 static const struct net_device_ops tg3_netdev_ops = {
13881         .ndo_open               = tg3_open,
13882         .ndo_stop               = tg3_close,
13883         .ndo_start_xmit         = tg3_start_xmit,
13884         .ndo_get_stats          = tg3_get_stats,
13885         .ndo_validate_addr      = eth_validate_addr,
13886         .ndo_set_multicast_list = tg3_set_rx_mode,
13887         .ndo_set_mac_address    = tg3_set_mac_addr,
13888         .ndo_do_ioctl           = tg3_ioctl,
13889         .ndo_tx_timeout         = tg3_tx_timeout,
13890         .ndo_change_mtu         = tg3_change_mtu,
13891 #if TG3_VLAN_TAG_USED
13892         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13893 #endif
13894 #ifdef CONFIG_NET_POLL_CONTROLLER
13895         .ndo_poll_controller    = tg3_poll_controller,
13896 #endif
13897 };
13898
13899 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13900         .ndo_open               = tg3_open,
13901         .ndo_stop               = tg3_close,
13902         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13903         .ndo_get_stats          = tg3_get_stats,
13904         .ndo_validate_addr      = eth_validate_addr,
13905         .ndo_set_multicast_list = tg3_set_rx_mode,
13906         .ndo_set_mac_address    = tg3_set_mac_addr,
13907         .ndo_do_ioctl           = tg3_ioctl,
13908         .ndo_tx_timeout         = tg3_tx_timeout,
13909         .ndo_change_mtu         = tg3_change_mtu,
13910 #if TG3_VLAN_TAG_USED
13911         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13912 #endif
13913 #ifdef CONFIG_NET_POLL_CONTROLLER
13914         .ndo_poll_controller    = tg3_poll_controller,
13915 #endif
13916 };
13917
13918 static int __devinit tg3_init_one(struct pci_dev *pdev,
13919                                   const struct pci_device_id *ent)
13920 {
13921         static int tg3_version_printed = 0;
13922         struct net_device *dev;
13923         struct tg3 *tp;
13924         int i, err, pm_cap;
13925         u32 sndmbx, rcvmbx, intmbx;
13926         char str[40];
13927         u64 dma_mask, persist_dma_mask;
13928
13929         if (tg3_version_printed++ == 0)
13930                 printk(KERN_INFO "%s", version);
13931
13932         err = pci_enable_device(pdev);
13933         if (err) {
13934                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13935                        "aborting.\n");
13936                 return err;
13937         }
13938
13939         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13940         if (err) {
13941                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13942                        "aborting.\n");
13943                 goto err_out_disable_pdev;
13944         }
13945
13946         pci_set_master(pdev);
13947
13948         /* Find power-management capability. */
13949         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13950         if (pm_cap == 0) {
13951                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13952                        "aborting.\n");
13953                 err = -EIO;
13954                 goto err_out_free_res;
13955         }
13956
13957         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13958         if (!dev) {
13959                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13960                 err = -ENOMEM;
13961                 goto err_out_free_res;
13962         }
13963
13964         SET_NETDEV_DEV(dev, &pdev->dev);
13965
13966 #if TG3_VLAN_TAG_USED
13967         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13968 #endif
13969
13970         tp = netdev_priv(dev);
13971         tp->pdev = pdev;
13972         tp->dev = dev;
13973         tp->pm_cap = pm_cap;
13974         tp->rx_mode = TG3_DEF_RX_MODE;
13975         tp->tx_mode = TG3_DEF_TX_MODE;
13976
13977         if (tg3_debug > 0)
13978                 tp->msg_enable = tg3_debug;
13979         else
13980                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13981
13982         /* The word/byte swap controls here control register access byte
13983          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13984          * setting below.
13985          */
13986         tp->misc_host_ctrl =
13987                 MISC_HOST_CTRL_MASK_PCI_INT |
13988                 MISC_HOST_CTRL_WORD_SWAP |
13989                 MISC_HOST_CTRL_INDIR_ACCESS |
13990                 MISC_HOST_CTRL_PCISTATE_RW;
13991
13992         /* The NONFRM (non-frame) byte/word swap controls take effect
13993          * on descriptor entries, anything which isn't packet data.
13994          *
13995          * The StrongARM chips on the board (one for tx, one for rx)
13996          * are running in big-endian mode.
13997          */
13998         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13999                         GRC_MODE_WSWAP_NONFRM_DATA);
14000 #ifdef __BIG_ENDIAN
14001         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14002 #endif
14003         spin_lock_init(&tp->lock);
14004         spin_lock_init(&tp->indirect_lock);
14005         INIT_WORK(&tp->reset_task, tg3_reset_task);
14006
14007         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14008         if (!tp->regs) {
14009                 printk(KERN_ERR PFX "Cannot map device registers, "
14010                        "aborting.\n");
14011                 err = -ENOMEM;
14012                 goto err_out_free_dev;
14013         }
14014
14015         tg3_init_link_config(tp);
14016
14017         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14018         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14019
14020         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14021         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14022         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14023         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14024                 struct tg3_napi *tnapi = &tp->napi[i];
14025
14026                 tnapi->tp = tp;
14027                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14028
14029                 tnapi->int_mbox = intmbx;
14030                 if (i < 4)
14031                         intmbx += 0x8;
14032                 else
14033                         intmbx += 0x4;
14034
14035                 tnapi->consmbox = rcvmbx;
14036                 tnapi->prodmbox = sndmbx;
14037
14038                 if (i)
14039                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14040                 else
14041                         tnapi->coal_now = HOSTCC_MODE_NOW;
14042
14043                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14044                         break;
14045
14046                 /*
14047                  * If we support MSIX, we'll be using RSS.  If we're using
14048                  * RSS, the first vector only handles link interrupts and the
14049                  * remaining vectors handle rx and tx interrupts.  Reuse the
14050                  * mailbox values for the next iteration.  The values we setup
14051                  * above are still useful for the single vectored mode.
14052                  */
14053                 if (!i)
14054                         continue;
14055
14056                 rcvmbx += 0x8;
14057
14058                 if (sndmbx & 0x4)
14059                         sndmbx -= 0x4;
14060                 else
14061                         sndmbx += 0xc;
14062         }
14063
14064         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
14065         dev->ethtool_ops = &tg3_ethtool_ops;
14066         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14067         dev->irq = pdev->irq;
14068
14069         err = tg3_get_invariants(tp);
14070         if (err) {
14071                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14072                        "aborting.\n");
14073                 goto err_out_iounmap;
14074         }
14075
14076         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
14077                 dev->netdev_ops = &tg3_netdev_ops;
14078         else
14079                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14080
14081
14082         /* The EPB bridge inside 5714, 5715, and 5780 and any
14083          * device behind the EPB cannot support DMA addresses > 40-bit.
14084          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14085          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14086          * do DMA address check in tg3_start_xmit().
14087          */
14088         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14089                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14090         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14091                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14092 #ifdef CONFIG_HIGHMEM
14093                 dma_mask = DMA_BIT_MASK(64);
14094 #endif
14095         } else
14096                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14097
14098         /* Configure DMA attributes. */
14099         if (dma_mask > DMA_BIT_MASK(32)) {
14100                 err = pci_set_dma_mask(pdev, dma_mask);
14101                 if (!err) {
14102                         dev->features |= NETIF_F_HIGHDMA;
14103                         err = pci_set_consistent_dma_mask(pdev,
14104                                                           persist_dma_mask);
14105                         if (err < 0) {
14106                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14107                                        "DMA for consistent allocations\n");
14108                                 goto err_out_iounmap;
14109                         }
14110                 }
14111         }
14112         if (err || dma_mask == DMA_BIT_MASK(32)) {
14113                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14114                 if (err) {
14115                         printk(KERN_ERR PFX "No usable DMA configuration, "
14116                                "aborting.\n");
14117                         goto err_out_iounmap;
14118                 }
14119         }
14120
14121         tg3_init_bufmgr_config(tp);
14122
14123         /* Selectively allow TSO based on operating conditions */
14124         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14125             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14126                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14127         else {
14128                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14129                 tp->fw_needed = NULL;
14130         }
14131
14132         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14133                 tp->fw_needed = FIRMWARE_TG3;
14134
14135         /* TSO is on by default on chips that support hardware TSO.
14136          * Firmware TSO on older chips gives lower performance, so it
14137          * is off by default, but can be enabled using ethtool.
14138          */
14139         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14140                 if (dev->features & NETIF_F_IP_CSUM)
14141                         dev->features |= NETIF_F_TSO;
14142                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14143                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
14144                         dev->features |= NETIF_F_TSO6;
14145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14146                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14147                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14148                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14149                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14150                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14151                         dev->features |= NETIF_F_TSO_ECN;
14152         }
14153
14154
14155         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14156             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14157             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14158                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14159                 tp->rx_pending = 63;
14160         }
14161
14162         err = tg3_get_device_address(tp);
14163         if (err) {
14164                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14165                        "aborting.\n");
14166                 goto err_out_fw;
14167         }
14168
14169         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14170                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14171                 if (!tp->aperegs) {
14172                         printk(KERN_ERR PFX "Cannot map APE registers, "
14173                                "aborting.\n");
14174                         err = -ENOMEM;
14175                         goto err_out_fw;
14176                 }
14177
14178                 tg3_ape_lock_init(tp);
14179
14180                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14181                         tg3_read_dash_ver(tp);
14182         }
14183
14184         /*
14185          * Reset chip in case UNDI or EFI driver did not shutdown
14186          * DMA self test will enable WDMAC and we'll see (spurious)
14187          * pending DMA on the PCI bus at that point.
14188          */
14189         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14190             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14191                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14192                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14193         }
14194
14195         err = tg3_test_dma(tp);
14196         if (err) {
14197                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14198                 goto err_out_apeunmap;
14199         }
14200
14201         /* flow control autonegotiation is default behavior */
14202         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14203         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14204
14205         tg3_init_coal(tp);
14206
14207         pci_set_drvdata(pdev, dev);
14208
14209         err = register_netdev(dev);
14210         if (err) {
14211                 printk(KERN_ERR PFX "Cannot register net device, "
14212                        "aborting.\n");
14213                 goto err_out_apeunmap;
14214         }
14215
14216         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14217                dev->name,
14218                tp->board_part_number,
14219                tp->pci_chip_rev_id,
14220                tg3_bus_string(tp, str),
14221                dev->dev_addr);
14222
14223         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14224                 struct phy_device *phydev;
14225                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14226                 printk(KERN_INFO
14227                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14228                        tp->dev->name, phydev->drv->name,
14229                        dev_name(&phydev->dev));
14230         } else
14231                 printk(KERN_INFO
14232                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14233                        tp->dev->name, tg3_phy_string(tp),
14234                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14235                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14236                          "10/100/1000Base-T")),
14237                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14238
14239         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14240                dev->name,
14241                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14242                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14243                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14244                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14245                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14246         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14247                dev->name, tp->dma_rwctrl,
14248                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14249                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14250
14251         return 0;
14252
14253 err_out_apeunmap:
14254         if (tp->aperegs) {
14255                 iounmap(tp->aperegs);
14256                 tp->aperegs = NULL;
14257         }
14258
14259 err_out_fw:
14260         if (tp->fw)
14261                 release_firmware(tp->fw);
14262
14263 err_out_iounmap:
14264         if (tp->regs) {
14265                 iounmap(tp->regs);
14266                 tp->regs = NULL;
14267         }
14268
14269 err_out_free_dev:
14270         free_netdev(dev);
14271
14272 err_out_free_res:
14273         pci_release_regions(pdev);
14274
14275 err_out_disable_pdev:
14276         pci_disable_device(pdev);
14277         pci_set_drvdata(pdev, NULL);
14278         return err;
14279 }
14280
14281 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14282 {
14283         struct net_device *dev = pci_get_drvdata(pdev);
14284
14285         if (dev) {
14286                 struct tg3 *tp = netdev_priv(dev);
14287
14288                 if (tp->fw)
14289                         release_firmware(tp->fw);
14290
14291                 flush_scheduled_work();
14292
14293                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14294                         tg3_phy_fini(tp);
14295                         tg3_mdio_fini(tp);
14296                 }
14297
14298                 unregister_netdev(dev);
14299                 if (tp->aperegs) {
14300                         iounmap(tp->aperegs);
14301                         tp->aperegs = NULL;
14302                 }
14303                 if (tp->regs) {
14304                         iounmap(tp->regs);
14305                         tp->regs = NULL;
14306                 }
14307                 free_netdev(dev);
14308                 pci_release_regions(pdev);
14309                 pci_disable_device(pdev);
14310                 pci_set_drvdata(pdev, NULL);
14311         }
14312 }
14313
14314 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14315 {
14316         struct net_device *dev = pci_get_drvdata(pdev);
14317         struct tg3 *tp = netdev_priv(dev);
14318         pci_power_t target_state;
14319         int err;
14320
14321         /* PCI register 4 needs to be saved whether netif_running() or not.
14322          * MSI address and data need to be saved if using MSI and
14323          * netif_running().
14324          */
14325         pci_save_state(pdev);
14326
14327         if (!netif_running(dev))
14328                 return 0;
14329
14330         flush_scheduled_work();
14331         tg3_phy_stop(tp);
14332         tg3_netif_stop(tp);
14333
14334         del_timer_sync(&tp->timer);
14335
14336         tg3_full_lock(tp, 1);
14337         tg3_disable_ints(tp);
14338         tg3_full_unlock(tp);
14339
14340         netif_device_detach(dev);
14341
14342         tg3_full_lock(tp, 0);
14343         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14344         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14345         tg3_full_unlock(tp);
14346
14347         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14348
14349         err = tg3_set_power_state(tp, target_state);
14350         if (err) {
14351                 int err2;
14352
14353                 tg3_full_lock(tp, 0);
14354
14355                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14356                 err2 = tg3_restart_hw(tp, 1);
14357                 if (err2)
14358                         goto out;
14359
14360                 tp->timer.expires = jiffies + tp->timer_offset;
14361                 add_timer(&tp->timer);
14362
14363                 netif_device_attach(dev);
14364                 tg3_netif_start(tp);
14365
14366 out:
14367                 tg3_full_unlock(tp);
14368
14369                 if (!err2)
14370                         tg3_phy_start(tp);
14371         }
14372
14373         return err;
14374 }
14375
14376 static int tg3_resume(struct pci_dev *pdev)
14377 {
14378         struct net_device *dev = pci_get_drvdata(pdev);
14379         struct tg3 *tp = netdev_priv(dev);
14380         int err;
14381
14382         pci_restore_state(tp->pdev);
14383
14384         if (!netif_running(dev))
14385                 return 0;
14386
14387         err = tg3_set_power_state(tp, PCI_D0);
14388         if (err)
14389                 return err;
14390
14391         netif_device_attach(dev);
14392
14393         tg3_full_lock(tp, 0);
14394
14395         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14396         err = tg3_restart_hw(tp, 1);
14397         if (err)
14398                 goto out;
14399
14400         tp->timer.expires = jiffies + tp->timer_offset;
14401         add_timer(&tp->timer);
14402
14403         tg3_netif_start(tp);
14404
14405 out:
14406         tg3_full_unlock(tp);
14407
14408         if (!err)
14409                 tg3_phy_start(tp);
14410
14411         return err;
14412 }
14413
14414 static struct pci_driver tg3_driver = {
14415         .name           = DRV_MODULE_NAME,
14416         .id_table       = tg3_pci_tbl,
14417         .probe          = tg3_init_one,
14418         .remove         = __devexit_p(tg3_remove_one),
14419         .suspend        = tg3_suspend,
14420         .resume         = tg3_resume
14421 };
14422
14423 static int __init tg3_init(void)
14424 {
14425         return pci_register_driver(&tg3_driver);
14426 }
14427
14428 static void __exit tg3_cleanup(void)
14429 {
14430         pci_unregister_driver(&tg3_driver);
14431 }
14432
14433 module_init(tg3_init);
14434 module_exit(tg3_cleanup);