1 /***************************************************************************
3 * Copyright (C) 2007,2008 SMSC
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 ***************************************************************************
22 #include <linux/kernel.h>
23 #include <linux/netdevice.h>
24 #include <linux/phy.h>
25 #include <linux/pci.h>
26 #include <linux/if_vlan.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/crc32.h>
29 #include <asm/unaligned.h>
32 #define DRV_NAME "smsc9420"
33 #define PFX DRV_NAME ": "
34 #define DRV_MDIONAME "smsc9420-mdio"
35 #define DRV_DESCRIPTION "SMSC LAN9420 driver"
36 #define DRV_VERSION "1.01"
38 MODULE_LICENSE("GPL");
39 MODULE_VERSION(DRV_VERSION);
41 struct smsc9420_dma_desc {
48 struct smsc9420_ring_info {
53 struct smsc9420_pdata {
54 void __iomem *base_addr;
56 struct net_device *dev;
58 struct smsc9420_dma_desc *rx_ring;
59 struct smsc9420_dma_desc *tx_ring;
60 struct smsc9420_ring_info *tx_buffers;
61 struct smsc9420_ring_info *rx_buffers;
62 dma_addr_t rx_dma_addr;
63 dma_addr_t tx_dma_addr;
64 int tx_ring_head, tx_ring_tail;
65 int rx_ring_head, rx_ring_tail;
70 struct napi_struct napi;
72 bool software_irq_signal;
76 struct phy_device *phy_dev;
77 struct mii_bus *mii_bus;
78 int phy_irq[PHY_MAX_ADDR];
83 static const struct pci_device_id smsc9420_id_table[] = {
84 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
88 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
90 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
92 static uint smsc_debug;
93 static uint debug = -1;
94 module_param(debug, uint, 0);
95 MODULE_PARM_DESC(debug, "debug level");
97 #define smsc_dbg(TYPE, f, a...) \
98 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
99 printk(KERN_DEBUG PFX f "\n", ## a); \
102 #define smsc_info(TYPE, f, a...) \
103 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
104 printk(KERN_INFO PFX f "\n", ## a); \
107 #define smsc_warn(TYPE, f, a...) \
108 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
109 printk(KERN_WARNING PFX f "\n", ## a); \
112 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
114 return ioread32(pd->base_addr + offset);
118 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
120 iowrite32(value, pd->base_addr + offset);
123 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
125 /* to ensure PCI write completion, we must perform a PCI read */
126 smsc9420_reg_read(pd, ID_REV);
129 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
131 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
136 spin_lock_irqsave(&pd->phy_lock, flags);
138 /* confirm MII not busy */
139 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
140 smsc_warn(DRV, "MII is busy???");
144 /* set the address, index & direction (read from PHY) */
145 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
146 MII_ACCESS_MII_READ_;
147 smsc9420_reg_write(pd, MII_ACCESS, addr);
149 /* wait for read to complete with 50us timeout */
150 for (i = 0; i < 5; i++) {
151 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
152 MII_ACCESS_MII_BUSY_)) {
153 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
159 smsc_warn(DRV, "MII busy timeout!");
162 spin_unlock_irqrestore(&pd->phy_lock, flags);
166 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
169 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
174 spin_lock_irqsave(&pd->phy_lock, flags);
176 /* confirm MII not busy */
177 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
178 smsc_warn(DRV, "MII is busy???");
182 /* put the data to write in the MAC */
183 smsc9420_reg_write(pd, MII_DATA, (u32)val);
185 /* set the address, index & direction (write to PHY) */
186 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
187 MII_ACCESS_MII_WRITE_;
188 smsc9420_reg_write(pd, MII_ACCESS, addr);
190 /* wait for write to complete with 50us timeout */
191 for (i = 0; i < 5; i++) {
192 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
193 MII_ACCESS_MII_BUSY_)) {
200 smsc_warn(DRV, "MII busy timeout!");
203 spin_unlock_irqrestore(&pd->phy_lock, flags);
207 /* Returns hash bit number for given MAC address
209 * 01 00 5E 00 00 01 -> returns bit number 31 */
210 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
212 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
215 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
217 int timeout = 100000;
221 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
222 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
226 smsc9420_reg_write(pd, E2P_CMD,
227 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
231 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
235 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
239 /* Standard ioctls for mii-tool */
240 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
242 struct smsc9420_pdata *pd = netdev_priv(dev);
244 if (!netif_running(dev) || !pd->phy_dev)
247 return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd);
250 static int smsc9420_ethtool_get_settings(struct net_device *dev,
251 struct ethtool_cmd *cmd)
253 struct smsc9420_pdata *pd = netdev_priv(dev);
257 return phy_ethtool_gset(pd->phy_dev, cmd);
260 static int smsc9420_ethtool_set_settings(struct net_device *dev,
261 struct ethtool_cmd *cmd)
263 struct smsc9420_pdata *pd = netdev_priv(dev);
265 return phy_ethtool_sset(pd->phy_dev, cmd);
268 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
269 struct ethtool_drvinfo *drvinfo)
271 struct smsc9420_pdata *pd = netdev_priv(netdev);
273 strcpy(drvinfo->driver, DRV_NAME);
274 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
275 strcpy(drvinfo->version, DRV_VERSION);
278 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
280 struct smsc9420_pdata *pd = netdev_priv(netdev);
281 return pd->msg_enable;
284 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
286 struct smsc9420_pdata *pd = netdev_priv(netdev);
287 pd->msg_enable = data;
290 static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
292 struct smsc9420_pdata *pd = netdev_priv(netdev);
293 return phy_start_aneg(pd->phy_dev);
296 static const struct ethtool_ops smsc9420_ethtool_ops = {
297 .get_settings = smsc9420_ethtool_get_settings,
298 .set_settings = smsc9420_ethtool_set_settings,
299 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
300 .get_msglevel = smsc9420_ethtool_get_msglevel,
301 .set_msglevel = smsc9420_ethtool_set_msglevel,
302 .nway_reset = smsc9420_ethtool_nway_reset,
303 .get_link = ethtool_op_get_link,
306 /* Sets the device MAC address to dev_addr */
307 static void smsc9420_set_mac_address(struct net_device *dev)
309 struct smsc9420_pdata *pd = netdev_priv(dev);
310 u8 *dev_addr = dev->dev_addr;
311 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
312 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
313 (dev_addr[1] << 8) | dev_addr[0];
315 smsc9420_reg_write(pd, ADDRH, mac_high16);
316 smsc9420_reg_write(pd, ADDRL, mac_low32);
319 static void smsc9420_check_mac_address(struct net_device *dev)
321 struct smsc9420_pdata *pd = netdev_priv(dev);
323 /* Check if mac address has been specified when bringing interface up */
324 if (is_valid_ether_addr(dev->dev_addr)) {
325 smsc9420_set_mac_address(dev);
326 smsc_dbg(PROBE, "MAC Address is specified by configuration");
328 /* Try reading mac address from device. if EEPROM is present
329 * it will already have been set */
330 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
331 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
332 dev->dev_addr[0] = (u8)(mac_low32);
333 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
334 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
335 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
336 dev->dev_addr[4] = (u8)(mac_high16);
337 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
339 if (is_valid_ether_addr(dev->dev_addr)) {
340 /* eeprom values are valid so use them */
341 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
343 /* eeprom values are invalid, generate random MAC */
344 random_ether_addr(dev->dev_addr);
345 smsc9420_set_mac_address(dev);
347 "MAC Address is set to random_ether_addr");
352 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
354 u32 dmac_control, mac_cr, dma_intr_ena;
357 /* disable TX DMAC */
358 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
359 dmac_control &= (~DMAC_CONTROL_ST_);
360 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
362 /* Wait max 10ms for transmit process to stop */
364 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
370 smsc_warn(IFDOWN, "TX DMAC failed to stop");
372 /* ACK Tx DMAC stop bit */
373 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
375 /* mask TX DMAC interrupts */
376 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
377 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
378 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
379 smsc9420_pci_flush_write(pd);
382 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
383 smsc9420_reg_write(pd, MAC_CR, mac_cr);
384 smsc9420_pci_flush_write(pd);
387 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
391 BUG_ON(!pd->tx_ring);
396 for (i = 0; i < TX_RING_SIZE; i++) {
397 struct sk_buff *skb = pd->tx_buffers[i].skb;
400 BUG_ON(!pd->tx_buffers[i].mapping);
401 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
402 skb->len, PCI_DMA_TODEVICE);
403 dev_kfree_skb_any(skb);
406 pd->tx_ring[i].status = 0;
407 pd->tx_ring[i].length = 0;
408 pd->tx_ring[i].buffer1 = 0;
409 pd->tx_ring[i].buffer2 = 0;
413 kfree(pd->tx_buffers);
414 pd->tx_buffers = NULL;
416 pd->tx_ring_head = 0;
417 pd->tx_ring_tail = 0;
420 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
424 BUG_ON(!pd->rx_ring);
429 for (i = 0; i < RX_RING_SIZE; i++) {
430 if (pd->rx_buffers[i].skb)
431 dev_kfree_skb_any(pd->rx_buffers[i].skb);
433 if (pd->rx_buffers[i].mapping)
434 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
435 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
437 pd->rx_ring[i].status = 0;
438 pd->rx_ring[i].length = 0;
439 pd->rx_ring[i].buffer1 = 0;
440 pd->rx_ring[i].buffer2 = 0;
444 kfree(pd->rx_buffers);
445 pd->rx_buffers = NULL;
447 pd->rx_ring_head = 0;
448 pd->rx_ring_tail = 0;
451 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
454 u32 mac_cr, dmac_control, dma_intr_ena;
456 /* mask RX DMAC interrupts */
457 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
458 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
459 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
460 smsc9420_pci_flush_write(pd);
462 /* stop RX MAC prior to stoping DMA */
463 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
464 smsc9420_reg_write(pd, MAC_CR, mac_cr);
465 smsc9420_pci_flush_write(pd);
468 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
469 dmac_control &= (~DMAC_CONTROL_SR_);
470 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
471 smsc9420_pci_flush_write(pd);
473 /* wait up to 10ms for receive to stop */
475 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
481 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
483 /* ACK the Rx DMAC stop bit */
484 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
487 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
489 struct smsc9420_pdata *pd = dev_id;
490 u32 int_cfg, int_sts, int_ctl;
491 irqreturn_t ret = IRQ_NONE;
495 BUG_ON(!pd->base_addr);
497 int_cfg = smsc9420_reg_read(pd, INT_CFG);
499 /* check if it's our interrupt */
500 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
501 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
504 int_sts = smsc9420_reg_read(pd, INT_STAT);
506 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
507 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
508 u32 ints_to_clear = 0;
510 if (status & DMAC_STS_TX_) {
511 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
512 netif_wake_queue(pd->dev);
515 if (status & DMAC_STS_RX_) {
516 /* mask RX DMAC interrupts */
517 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
518 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
519 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
520 smsc9420_pci_flush_write(pd);
522 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
523 netif_rx_schedule(pd->dev, &pd->napi);
527 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
532 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
533 /* mask software interrupt */
534 spin_lock_irqsave(&pd->int_lock, flags);
535 int_ctl = smsc9420_reg_read(pd, INT_CTL);
536 int_ctl &= (~INT_CTL_SW_INT_EN_);
537 smsc9420_reg_write(pd, INT_CTL, int_ctl);
538 spin_unlock_irqrestore(&pd->int_lock, flags);
540 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
541 pd->software_irq_signal = true;
547 /* to ensure PCI write completion, we must perform a PCI read */
548 smsc9420_pci_flush_write(pd);
553 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
555 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
556 smsc9420_reg_read(pd, BUS_MODE);
558 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
559 smsc_warn(DRV, "Software reset not cleared");
562 static int smsc9420_stop(struct net_device *dev)
564 struct smsc9420_pdata *pd = netdev_priv(dev);
569 BUG_ON(!pd->phy_dev);
571 /* disable master interrupt */
572 spin_lock_irqsave(&pd->int_lock, flags);
573 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
574 smsc9420_reg_write(pd, INT_CFG, int_cfg);
575 spin_unlock_irqrestore(&pd->int_lock, flags);
577 netif_tx_disable(dev);
578 napi_disable(&pd->napi);
580 smsc9420_stop_tx(pd);
581 smsc9420_free_tx_ring(pd);
583 smsc9420_stop_rx(pd);
584 smsc9420_free_rx_ring(pd);
586 free_irq(dev->irq, pd);
588 smsc9420_dmac_soft_reset(pd);
590 phy_stop(pd->phy_dev);
592 phy_disconnect(pd->phy_dev);
594 mdiobus_unregister(pd->mii_bus);
595 mdiobus_free(pd->mii_bus);
600 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
602 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
603 dev->stats.rx_errors++;
604 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
605 dev->stats.rx_over_errors++;
606 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
607 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
608 dev->stats.rx_frame_errors++;
609 else if (desc_status & RDES0_CRC_ERROR_)
610 dev->stats.rx_crc_errors++;
613 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
614 dev->stats.rx_length_errors++;
616 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
617 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
618 dev->stats.rx_length_errors++;
620 if (desc_status & RDES0_MULTICAST_FRAME_)
621 dev->stats.multicast++;
624 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
627 struct net_device *dev = pd->dev;
629 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
630 >> RDES0_FRAME_LENGTH_SHFT_;
632 /* remove crc from packet lendth */
638 dev->stats.rx_packets++;
639 dev->stats.rx_bytes += packet_length;
641 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
642 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
643 pd->rx_buffers[index].mapping = 0;
645 skb = pd->rx_buffers[index].skb;
646 pd->rx_buffers[index].skb = NULL;
649 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
650 NET_IP_ALIGN + packet_length + 4);
651 put_unaligned_le16(cpu_to_le16(hw_csum), &skb->csum);
652 skb->ip_summed = CHECKSUM_COMPLETE;
655 skb_reserve(skb, NET_IP_ALIGN);
656 skb_put(skb, packet_length);
658 skb->protocol = eth_type_trans(skb, dev);
660 netif_receive_skb(skb);
661 dev->last_rx = jiffies;
664 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
666 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
669 BUG_ON(pd->rx_buffers[index].skb);
670 BUG_ON(pd->rx_buffers[index].mapping);
672 if (unlikely(!skb)) {
673 smsc_warn(RX_ERR, "Failed to allocate new skb!");
679 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
680 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
681 if (pci_dma_mapping_error(pd->pdev, mapping)) {
682 dev_kfree_skb_any(skb);
683 smsc_warn(RX_ERR, "pci_map_single failed!");
687 pd->rx_buffers[index].skb = skb;
688 pd->rx_buffers[index].mapping = mapping;
689 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
690 pd->rx_ring[index].status = RDES0_OWN_;
696 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
698 while (pd->rx_ring_tail != pd->rx_ring_head) {
699 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
702 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
706 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
708 struct smsc9420_pdata *pd =
709 container_of(napi, struct smsc9420_pdata, napi);
710 struct net_device *dev = pd->dev;
711 u32 drop_frame_cnt, dma_intr_ena, status;
714 for (work_done = 0; work_done < budget; work_done++) {
716 status = pd->rx_ring[pd->rx_ring_head].status;
718 /* stop if DMAC owns this dma descriptor */
719 if (status & RDES0_OWN_)
722 smsc9420_rx_count_stats(dev, status);
723 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
724 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
725 smsc9420_alloc_new_rx_buffers(pd);
728 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
729 dev->stats.rx_dropped +=
730 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
733 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
734 smsc9420_pci_flush_write(pd);
736 if (work_done < budget) {
737 netif_rx_complete(dev, &pd->napi);
739 /* re-enable RX DMA interrupts */
740 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
741 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
742 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
743 smsc9420_pci_flush_write(pd);
749 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
751 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
752 dev->stats.tx_errors++;
753 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
754 TDES0_EXCESSIVE_COLLISIONS_))
755 dev->stats.tx_aborted_errors++;
757 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
758 dev->stats.tx_carrier_errors++;
760 dev->stats.tx_packets++;
761 dev->stats.tx_bytes += (length & 0x7FF);
764 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
765 dev->stats.collisions += 16;
767 dev->stats.collisions +=
768 (status & TDES0_COLLISION_COUNT_MASK_) >>
769 TDES0_COLLISION_COUNT_SHFT_;
772 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
773 dev->stats.tx_heartbeat_errors++;
776 /* Check for completed dma transfers, update stats and free skbs */
777 static void smsc9420_complete_tx(struct net_device *dev)
779 struct smsc9420_pdata *pd = netdev_priv(dev);
781 while (pd->tx_ring_tail != pd->tx_ring_head) {
782 int index = pd->tx_ring_tail;
786 status = pd->tx_ring[index].status;
787 length = pd->tx_ring[index].length;
789 /* Check if DMA still owns this descriptor */
790 if (unlikely(TDES0_OWN_ & status))
793 smsc9420_tx_update_stats(dev, status, length);
795 BUG_ON(!pd->tx_buffers[index].skb);
796 BUG_ON(!pd->tx_buffers[index].mapping);
798 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
799 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
800 pd->tx_buffers[index].mapping = 0;
802 dev_kfree_skb_any(pd->tx_buffers[index].skb);
803 pd->tx_buffers[index].skb = NULL;
805 pd->tx_ring[index].buffer1 = 0;
808 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
812 static int smsc9420_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
814 struct smsc9420_pdata *pd = netdev_priv(dev);
816 int index = pd->tx_ring_head;
818 bool about_to_take_last_desc =
819 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
821 smsc9420_complete_tx(dev);
824 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
825 BUG_ON(pd->tx_buffers[index].skb);
826 BUG_ON(pd->tx_buffers[index].mapping);
828 mapping = pci_map_single(pd->pdev, skb->data,
829 skb->len, PCI_DMA_TODEVICE);
830 if (pci_dma_mapping_error(pd->pdev, mapping)) {
831 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
832 return NETDEV_TX_BUSY;
835 pd->tx_buffers[index].skb = skb;
836 pd->tx_buffers[index].mapping = mapping;
838 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
839 if (unlikely(about_to_take_last_desc)) {
840 tmp_desc1 |= TDES1_IC_;
841 netif_stop_queue(pd->dev);
844 /* check if we are at the last descriptor and need to set EOR */
845 if (unlikely(index == (TX_RING_SIZE - 1)))
846 tmp_desc1 |= TDES1_TER_;
848 pd->tx_ring[index].buffer1 = mapping;
849 pd->tx_ring[index].length = tmp_desc1;
853 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
855 /* assign ownership to DMAC */
856 pd->tx_ring[index].status = TDES0_OWN_;
860 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
861 smsc9420_pci_flush_write(pd);
863 dev->trans_start = jiffies;
868 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
870 struct smsc9420_pdata *pd = netdev_priv(dev);
871 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
872 dev->stats.rx_dropped +=
873 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
877 static void smsc9420_set_multicast_list(struct net_device *dev)
879 struct smsc9420_pdata *pd = netdev_priv(dev);
880 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
882 if (dev->flags & IFF_PROMISC) {
883 smsc_dbg(HW, "Promiscuous Mode Enabled");
884 mac_cr |= MAC_CR_PRMS_;
885 mac_cr &= (~MAC_CR_MCPAS_);
886 mac_cr &= (~MAC_CR_HPFILT_);
887 } else if (dev->flags & IFF_ALLMULTI) {
888 smsc_dbg(HW, "Receive all Multicast Enabled");
889 mac_cr &= (~MAC_CR_PRMS_);
890 mac_cr |= MAC_CR_MCPAS_;
891 mac_cr &= (~MAC_CR_HPFILT_);
892 } else if (dev->mc_count > 0) {
893 struct dev_mc_list *mc_list = dev->mc_list;
894 u32 hash_lo = 0, hash_hi = 0;
896 smsc_dbg(HW, "Multicast filter enabled");
898 u32 bit_num = smsc9420_hash(mc_list->dmi_addr);
899 u32 mask = 1 << (bit_num & 0x1F);
906 mc_list = mc_list->next;
908 smsc9420_reg_write(pd, HASHH, hash_hi);
909 smsc9420_reg_write(pd, HASHL, hash_lo);
911 mac_cr &= (~MAC_CR_PRMS_);
912 mac_cr &= (~MAC_CR_MCPAS_);
913 mac_cr |= MAC_CR_HPFILT_;
915 smsc_dbg(HW, "Receive own packets only.");
916 smsc9420_reg_write(pd, HASHH, 0);
917 smsc9420_reg_write(pd, HASHL, 0);
919 mac_cr &= (~MAC_CR_PRMS_);
920 mac_cr &= (~MAC_CR_MCPAS_);
921 mac_cr &= (~MAC_CR_HPFILT_);
924 smsc9420_reg_write(pd, MAC_CR, mac_cr);
925 smsc9420_pci_flush_write(pd);
928 static u8 smsc9420_resolve_flowctrl_fulldplx(u16 lcladv, u16 rmtadv)
932 if (lcladv & ADVERTISE_PAUSE_CAP) {
933 if (lcladv & ADVERTISE_PAUSE_ASYM) {
934 if (rmtadv & LPA_PAUSE_CAP)
935 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
936 else if (rmtadv & LPA_PAUSE_ASYM)
939 if (rmtadv & LPA_PAUSE_CAP)
940 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
942 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
943 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
950 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
952 struct phy_device *phy_dev = pd->phy_dev;
955 if (phy_dev->duplex == DUPLEX_FULL) {
956 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
957 u16 rmtadv = phy_read(phy_dev, MII_LPA);
958 u8 cap = smsc9420_resolve_flowctrl_fulldplx(lcladv, rmtadv);
960 if (cap & FLOW_CTRL_RX)
965 smsc_info(LINK, "rx pause %s, tx pause %s",
966 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
967 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
969 smsc_info(LINK, "half duplex");
973 smsc9420_reg_write(pd, FLOW, flow);
976 /* Update link mode if anything has changed. Called periodically when the
977 * PHY is in polling mode, even if nothing has changed. */
978 static void smsc9420_phy_adjust_link(struct net_device *dev)
980 struct smsc9420_pdata *pd = netdev_priv(dev);
981 struct phy_device *phy_dev = pd->phy_dev;
984 if (phy_dev->duplex != pd->last_duplex) {
985 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
986 if (phy_dev->duplex) {
987 smsc_dbg(LINK, "full duplex mode");
988 mac_cr |= MAC_CR_FDPX_;
990 smsc_dbg(LINK, "half duplex mode");
991 mac_cr &= ~MAC_CR_FDPX_;
993 smsc9420_reg_write(pd, MAC_CR, mac_cr);
995 smsc9420_phy_update_flowcontrol(pd);
996 pd->last_duplex = phy_dev->duplex;
999 carrier = netif_carrier_ok(dev);
1000 if (carrier != pd->last_carrier) {
1002 smsc_dbg(LINK, "carrier OK");
1004 smsc_dbg(LINK, "no carrier");
1005 pd->last_carrier = carrier;
1009 static int smsc9420_mii_probe(struct net_device *dev)
1011 struct smsc9420_pdata *pd = netdev_priv(dev);
1012 struct phy_device *phydev = NULL;
1014 BUG_ON(pd->phy_dev);
1016 /* Device only supports internal PHY at address 1 */
1017 if (!pd->mii_bus->phy_map[1]) {
1018 pr_err("%s: no PHY found at address 1\n", dev->name);
1022 phydev = pd->mii_bus->phy_map[1];
1023 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1026 phydev = phy_connect(dev, phydev->dev.bus_id,
1027 &smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1029 if (IS_ERR(phydev)) {
1030 pr_err("%s: Could not attach to PHY\n", dev->name);
1031 return PTR_ERR(phydev);
1034 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1035 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
1037 /* mask with MAC supported features */
1038 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1039 SUPPORTED_Asym_Pause);
1040 phydev->advertising = phydev->supported;
1042 pd->phy_dev = phydev;
1043 pd->last_duplex = -1;
1044 pd->last_carrier = -1;
1049 static int smsc9420_mii_init(struct net_device *dev)
1051 struct smsc9420_pdata *pd = netdev_priv(dev);
1052 int err = -ENXIO, i;
1054 pd->mii_bus = mdiobus_alloc();
1059 pd->mii_bus->name = DRV_MDIONAME;
1060 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1061 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1062 pd->mii_bus->priv = pd;
1063 pd->mii_bus->read = smsc9420_mii_read;
1064 pd->mii_bus->write = smsc9420_mii_write;
1065 pd->mii_bus->irq = pd->phy_irq;
1066 for (i = 0; i < PHY_MAX_ADDR; ++i)
1067 pd->mii_bus->irq[i] = PHY_POLL;
1069 /* Mask all PHYs except ID 1 (internal) */
1070 pd->mii_bus->phy_mask = ~(1 << 1);
1072 if (mdiobus_register(pd->mii_bus)) {
1073 smsc_warn(PROBE, "Error registering mii bus");
1074 goto err_out_free_bus_2;
1077 if (smsc9420_mii_probe(dev) < 0) {
1078 smsc_warn(PROBE, "Error probing mii bus");
1079 goto err_out_unregister_bus_3;
1084 err_out_unregister_bus_3:
1085 mdiobus_unregister(pd->mii_bus);
1087 mdiobus_free(pd->mii_bus);
1092 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1096 BUG_ON(!pd->tx_ring);
1098 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1099 TX_RING_SIZE), GFP_KERNEL);
1100 if (!pd->tx_buffers) {
1101 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1105 /* Initialize the TX Ring */
1106 for (i = 0; i < TX_RING_SIZE; i++) {
1107 pd->tx_buffers[i].skb = NULL;
1108 pd->tx_buffers[i].mapping = 0;
1109 pd->tx_ring[i].status = 0;
1110 pd->tx_ring[i].length = 0;
1111 pd->tx_ring[i].buffer1 = 0;
1112 pd->tx_ring[i].buffer2 = 0;
1114 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1117 pd->tx_ring_head = 0;
1118 pd->tx_ring_tail = 0;
1120 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1121 smsc9420_pci_flush_write(pd);
1126 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1130 BUG_ON(!pd->rx_ring);
1132 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1133 RX_RING_SIZE), GFP_KERNEL);
1134 if (pd->rx_buffers == NULL) {
1135 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1139 /* initialize the rx ring */
1140 for (i = 0; i < RX_RING_SIZE; i++) {
1141 pd->rx_ring[i].status = 0;
1142 pd->rx_ring[i].length = PKT_BUF_SZ;
1143 pd->rx_ring[i].buffer2 = 0;
1144 pd->rx_buffers[i].skb = NULL;
1145 pd->rx_buffers[i].mapping = 0;
1147 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1149 /* now allocate the entire ring of skbs */
1150 for (i = 0; i < RX_RING_SIZE; i++) {
1151 if (smsc9420_alloc_rx_buffer(pd, i)) {
1152 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1153 goto out_free_rx_skbs;
1157 pd->rx_ring_head = 0;
1158 pd->rx_ring_tail = 0;
1160 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1161 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1165 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1166 smsc9420_reg_write(pd, COE_CR, coe);
1167 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1170 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1171 smsc9420_pci_flush_write(pd);
1176 smsc9420_free_rx_ring(pd);
1181 static int smsc9420_open(struct net_device *dev)
1183 struct smsc9420_pdata *pd;
1184 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1185 unsigned long flags;
1186 int result = 0, timeout;
1189 pd = netdev_priv(dev);
1192 if (!is_valid_ether_addr(dev->dev_addr)) {
1193 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1194 result = -EADDRNOTAVAIL;
1198 netif_carrier_off(dev);
1200 /* disable, mask and acknowlege all interrupts */
1201 spin_lock_irqsave(&pd->int_lock, flags);
1202 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1203 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1204 smsc9420_reg_write(pd, INT_CTL, 0);
1205 spin_unlock_irqrestore(&pd->int_lock, flags);
1206 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1207 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1208 smsc9420_pci_flush_write(pd);
1210 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1212 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1217 smsc9420_dmac_soft_reset(pd);
1219 /* make sure MAC_CR is sane */
1220 smsc9420_reg_write(pd, MAC_CR, 0);
1222 smsc9420_set_mac_address(dev);
1224 /* Configure GPIO pins to drive LEDs */
1225 smsc9420_reg_write(pd, GPIO_CFG,
1226 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1228 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1231 bus_mode |= BUS_MODE_DBO_;
1234 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1236 smsc9420_pci_flush_write(pd);
1238 /* set bus master bridge arbitration priority for Rx and TX DMA */
1239 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1241 smsc9420_reg_write(pd, DMAC_CONTROL,
1242 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1244 smsc9420_pci_flush_write(pd);
1246 /* test the IRQ connection to the ISR */
1247 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
1249 spin_lock_irqsave(&pd->int_lock, flags);
1250 /* configure interrupt deassertion timer and enable interrupts */
1251 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1252 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1253 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1254 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1256 /* unmask software interrupt */
1257 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1258 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1259 spin_unlock_irqrestore(&pd->int_lock, flags);
1260 smsc9420_pci_flush_write(pd);
1263 pd->software_irq_signal = false;
1266 if (pd->software_irq_signal)
1271 /* disable interrupts */
1272 spin_lock_irqsave(&pd->int_lock, flags);
1273 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1274 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1275 spin_unlock_irqrestore(&pd->int_lock, flags);
1277 if (!pd->software_irq_signal) {
1278 smsc_warn(IFUP, "ISR failed signaling test");
1280 goto out_free_irq_1;
1283 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1285 result = smsc9420_alloc_tx_ring(pd);
1287 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1289 goto out_free_irq_1;
1292 result = smsc9420_alloc_rx_ring(pd);
1294 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1296 goto out_free_tx_ring_2;
1299 result = smsc9420_mii_init(dev);
1301 smsc_warn(IFUP, "Failed to initialize Phy");
1303 goto out_free_rx_ring_3;
1306 /* Bring the PHY up */
1307 phy_start(pd->phy_dev);
1309 napi_enable(&pd->napi);
1311 /* start tx and rx */
1312 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1313 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1315 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1316 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1317 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1318 smsc9420_pci_flush_write(pd);
1320 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1322 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1323 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1324 smsc9420_pci_flush_write(pd);
1326 netif_wake_queue(dev);
1328 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1330 /* enable interrupts */
1331 spin_lock_irqsave(&pd->int_lock, flags);
1332 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1333 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1334 spin_unlock_irqrestore(&pd->int_lock, flags);
1339 smsc9420_free_rx_ring(pd);
1341 smsc9420_free_tx_ring(pd);
1343 free_irq(dev->irq, pd);
1350 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1352 struct net_device *dev = pci_get_drvdata(pdev);
1353 struct smsc9420_pdata *pd = netdev_priv(dev);
1357 /* disable interrupts */
1358 spin_lock_irqsave(&pd->int_lock, flags);
1359 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1360 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1361 spin_unlock_irqrestore(&pd->int_lock, flags);
1363 if (netif_running(dev)) {
1364 netif_tx_disable(dev);
1365 smsc9420_stop_tx(pd);
1366 smsc9420_free_tx_ring(pd);
1368 napi_disable(&pd->napi);
1369 smsc9420_stop_rx(pd);
1370 smsc9420_free_rx_ring(pd);
1372 free_irq(dev->irq, pd);
1374 netif_device_detach(dev);
1377 pci_save_state(pdev);
1378 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1379 pci_disable_device(pdev);
1380 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1385 static int smsc9420_resume(struct pci_dev *pdev)
1387 struct net_device *dev = pci_get_drvdata(pdev);
1388 struct smsc9420_pdata *pd = netdev_priv(dev);
1391 pci_set_power_state(pdev, PCI_D0);
1392 pci_restore_state(pdev);
1394 err = pci_enable_device(pdev);
1398 pci_set_master(pdev);
1400 err = pci_enable_wake(pdev, 0, 0);
1402 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1404 if (netif_running(dev)) {
1405 err = smsc9420_open(dev);
1406 netif_device_attach(dev);
1411 #endif /* CONFIG_PM */
1413 static const struct net_device_ops smsc9420_netdev_ops = {
1414 .ndo_open = smsc9420_open,
1415 .ndo_stop = smsc9420_stop,
1416 .ndo_start_xmit = smsc9420_hard_start_xmit,
1417 .ndo_get_stats = smsc9420_get_stats,
1418 .ndo_set_multicast_list = smsc9420_set_multicast_list,
1419 .ndo_do_ioctl = smsc9420_do_ioctl,
1420 .ndo_validate_addr = eth_validate_addr,
1423 static int __devinit
1424 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1426 struct net_device *dev;
1427 struct smsc9420_pdata *pd;
1428 void __iomem *virt_addr;
1432 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1434 /* First do the PCI initialisation */
1435 result = pci_enable_device(pdev);
1436 if (unlikely(result)) {
1437 printk(KERN_ERR "Cannot enable smsc9420\n");
1441 pci_set_master(pdev);
1443 dev = alloc_etherdev(sizeof(*pd));
1445 printk(KERN_ERR "ether device alloc failed\n");
1446 goto out_disable_pci_device_1;
1449 SET_NETDEV_DEV(dev, &pdev->dev);
1451 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1452 printk(KERN_ERR "Cannot find PCI device base address\n");
1453 goto out_free_netdev_2;
1456 if ((pci_request_regions(pdev, DRV_NAME))) {
1457 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1458 goto out_free_netdev_2;
1461 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1462 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1463 goto out_free_regions_3;
1466 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1467 pci_resource_len(pdev, SMSC_BAR));
1469 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1470 goto out_free_regions_3;
1473 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1474 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1476 dev->base_addr = (ulong)virt_addr;
1478 pd = netdev_priv(dev);
1480 /* pci descriptors are created in the PCI consistent area */
1481 pd->rx_ring = pci_alloc_consistent(pdev,
1482 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1483 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1489 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1490 pd->tx_ring = (struct smsc9420_dma_desc *)
1491 (pd->rx_ring + RX_RING_SIZE);
1492 pd->tx_dma_addr = pd->rx_dma_addr +
1493 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1497 pd->base_addr = virt_addr;
1498 pd->msg_enable = smsc_debug;
1501 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1503 id_rev = smsc9420_reg_read(pd, ID_REV);
1504 switch (id_rev & 0xFFFF0000) {
1506 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1509 smsc_warn(PROBE, "LAN9420 NOT identified");
1510 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1511 goto out_free_dmadesc_5;
1514 smsc9420_dmac_soft_reset(pd);
1515 smsc9420_eeprom_reload(pd);
1516 smsc9420_check_mac_address(dev);
1518 dev->netdev_ops = &smsc9420_netdev_ops;
1519 dev->ethtool_ops = &smsc9420_ethtool_ops;
1520 dev->irq = pdev->irq;
1522 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1524 result = register_netdev(dev);
1526 smsc_warn(PROBE, "error %i registering device", result);
1527 goto out_free_dmadesc_5;
1530 pci_set_drvdata(pdev, dev);
1532 spin_lock_init(&pd->int_lock);
1533 spin_lock_init(&pd->phy_lock);
1535 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1540 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1541 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1543 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1545 pci_release_regions(pdev);
1548 out_disable_pci_device_1:
1549 pci_disable_device(pdev);
1554 static void __devexit smsc9420_remove(struct pci_dev *pdev)
1556 struct net_device *dev;
1557 struct smsc9420_pdata *pd;
1559 dev = pci_get_drvdata(pdev);
1563 pci_set_drvdata(pdev, NULL);
1565 pd = netdev_priv(dev);
1566 unregister_netdev(dev);
1568 /* tx_buffers and rx_buffers are freed in stop */
1569 BUG_ON(pd->tx_buffers);
1570 BUG_ON(pd->rx_buffers);
1572 BUG_ON(!pd->tx_ring);
1573 BUG_ON(!pd->rx_ring);
1575 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1576 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1578 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1579 pci_release_regions(pdev);
1581 pci_disable_device(pdev);
1584 static struct pci_driver smsc9420_driver = {
1586 .id_table = smsc9420_id_table,
1587 .probe = smsc9420_probe,
1588 .remove = __devexit_p(smsc9420_remove),
1590 .suspend = smsc9420_suspend,
1591 .resume = smsc9420_resume,
1592 #endif /* CONFIG_PM */
1595 static int __init smsc9420_init_module(void)
1597 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1599 return pci_register_driver(&smsc9420_driver);
1602 static void __exit smsc9420_exit_module(void)
1604 pci_unregister_driver(&smsc9420_driver);
1607 module_init(smsc9420_init_module);
1608 module_exit(smsc9420_exit_module);