2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
29 #define MASK(n) ((1ULL<<(n))-1)
30 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
32 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
34 #define CRB_BLK(off) ((off >> 20) & 0x3f)
35 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
36 #define CRB_WINDOW_2M (0x130060)
37 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
38 #define CRB_INDIRECT_2M (0x1e0000UL)
42 static inline u64 readq(void __iomem *addr)
44 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
49 static inline void writeq(u64 val, void __iomem *addr)
51 writel(((u32) (val)), (addr));
52 writel(((u32) (val >> 32)), (addr + 4));
56 #define ADDR_IN_RANGE(addr, low, high) \
57 (((addr) < (high)) && ((addr) >= (low)))
59 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
60 ((adapter)->ahw.pci_base0 + (off))
62 static void __iomem *pci_base_offset(struct qlcnic_adapter *adapter,
65 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
66 return PCI_OFFSET_FIRST_RANGE(adapter, off);
71 static const struct crb_128M_2M_block_map
72 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
73 {{{0, 0, 0, 0} } }, /* 0: PCI */
74 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
75 {1, 0x0110000, 0x0120000, 0x130000},
76 {1, 0x0120000, 0x0122000, 0x124000},
77 {1, 0x0130000, 0x0132000, 0x126000},
78 {1, 0x0140000, 0x0142000, 0x128000},
79 {1, 0x0150000, 0x0152000, 0x12a000},
80 {1, 0x0160000, 0x0170000, 0x110000},
81 {1, 0x0170000, 0x0172000, 0x12e000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {1, 0x01e0000, 0x01e0800, 0x122000},
89 {0, 0x0000000, 0x0000000, 0x000000} } },
90 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
91 {{{0, 0, 0, 0} } }, /* 3: */
92 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
93 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
94 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
95 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
96 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {1, 0x08f0000, 0x08f2000, 0x172000} } },
112 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x09f0000, 0x09f2000, 0x176000} } },
128 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
144 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
160 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
161 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
162 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
163 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
164 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
165 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
166 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
167 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
168 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
169 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
170 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
171 {{{0, 0, 0, 0} } }, /* 23: */
172 {{{0, 0, 0, 0} } }, /* 24: */
173 {{{0, 0, 0, 0} } }, /* 25: */
174 {{{0, 0, 0, 0} } }, /* 26: */
175 {{{0, 0, 0, 0} } }, /* 27: */
176 {{{0, 0, 0, 0} } }, /* 28: */
177 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
178 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
179 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
180 {{{0} } }, /* 32: PCI */
181 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
182 {1, 0x2110000, 0x2120000, 0x130000},
183 {1, 0x2120000, 0x2122000, 0x124000},
184 {1, 0x2130000, 0x2132000, 0x126000},
185 {1, 0x2140000, 0x2142000, 0x128000},
186 {1, 0x2150000, 0x2152000, 0x12a000},
187 {1, 0x2160000, 0x2170000, 0x110000},
188 {1, 0x2170000, 0x2172000, 0x12e000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000} } },
197 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
203 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
204 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
205 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
206 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
207 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
208 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
209 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
210 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
211 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
212 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
213 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
214 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
216 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
217 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
218 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
219 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
220 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
221 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
222 {{{0} } }, /* 59: I2C0 */
223 {{{0} } }, /* 60: I2C1 */
224 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
225 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
226 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
230 * top 12 bits of crb internal address (hub, agent)
232 static const unsigned crb_hub_agt[64] = {
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
240 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
249 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
251 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
254 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
276 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
277 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
278 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
279 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
280 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
281 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
282 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
283 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
284 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
286 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
287 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
288 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
289 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
291 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
292 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
293 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
295 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
299 /* PCI Windowing for DDR regions. */
301 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
304 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
306 int done = 0, timeout = 0;
309 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
312 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT)
318 QLCWR32(adapter, id_reg, adapter->portnum);
324 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
326 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
330 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
331 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
333 u32 i, producer, consumer;
334 struct qlcnic_cmd_buffer *pbuf;
335 struct cmd_desc_type0 *cmd_desc;
336 struct qlcnic_host_tx_ring *tx_ring;
340 if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
343 tx_ring = adapter->tx_ring;
344 __netif_tx_lock_bh(tx_ring->txq);
346 producer = tx_ring->producer;
347 consumer = tx_ring->sw_consumer;
349 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
350 netif_tx_stop_queue(tx_ring->txq);
351 __netif_tx_unlock_bh(tx_ring->txq);
356 cmd_desc = &cmd_desc_arr[i];
358 pbuf = &tx_ring->cmd_buf_arr[producer];
360 pbuf->frag_count = 0;
362 memcpy(&tx_ring->desc_head[producer],
363 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
365 producer = get_next_index(producer, tx_ring->num_desc);
368 } while (i != nr_desc);
370 tx_ring->producer = producer;
372 qlcnic_update_cmd_producer(adapter, tx_ring);
374 __netif_tx_unlock_bh(tx_ring->txq);
380 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
383 struct qlcnic_nic_req req;
384 struct qlcnic_mac_req *mac_req;
387 memset(&req, 0, sizeof(struct qlcnic_nic_req));
388 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
390 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
391 req.req_hdr = cpu_to_le64(word);
393 mac_req = (struct qlcnic_mac_req *)&req.words[0];
395 memcpy(mac_req->mac_addr, addr, 6);
397 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
400 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter,
401 u8 *addr, struct list_head *del_list)
403 struct list_head *head;
404 struct qlcnic_mac_list_s *cur;
406 /* look up if already exists */
407 list_for_each(head, del_list) {
408 cur = list_entry(head, struct qlcnic_mac_list_s, list);
410 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
411 list_move_tail(head, &adapter->mac_list);
416 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
418 dev_err(&adapter->netdev->dev,
419 "failed to add mac address filter\n");
422 memcpy(cur->mac_addr, addr, ETH_ALEN);
423 list_add_tail(&cur->list, &adapter->mac_list);
425 return qlcnic_sre_macaddr_change(adapter,
426 cur->mac_addr, QLCNIC_MAC_ADD);
429 void qlcnic_set_multi(struct net_device *netdev)
431 struct qlcnic_adapter *adapter = netdev_priv(netdev);
432 struct dev_mc_list *mc_ptr;
433 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
434 u32 mode = VPORT_MISS_MODE_DROP;
436 struct list_head *head;
437 struct qlcnic_mac_list_s *cur;
439 list_splice_tail_init(&adapter->mac_list, &del_list);
441 qlcnic_nic_add_mac(adapter, adapter->mac_addr, &del_list);
442 qlcnic_nic_add_mac(adapter, bcast_addr, &del_list);
444 if (netdev->flags & IFF_PROMISC) {
445 mode = VPORT_MISS_MODE_ACCEPT_ALL;
449 if ((netdev->flags & IFF_ALLMULTI) ||
450 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
451 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
455 if (!netdev_mc_empty(netdev)) {
456 netdev_for_each_mc_addr(mc_ptr, netdev) {
457 qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr,
463 qlcnic_nic_set_promisc(adapter, mode);
465 while (!list_empty(head)) {
466 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
468 qlcnic_sre_macaddr_change(adapter,
469 cur->mac_addr, QLCNIC_MAC_DEL);
470 list_del(&cur->list);
475 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
477 struct qlcnic_nic_req req;
480 memset(&req, 0, sizeof(struct qlcnic_nic_req));
482 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
484 word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
485 ((u64)adapter->portnum << 16);
486 req.req_hdr = cpu_to_le64(word);
488 req.words[0] = cpu_to_le64(mode);
490 return qlcnic_send_cmd_descs(adapter,
491 (struct cmd_desc_type0 *)&req, 1);
494 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
496 struct qlcnic_mac_list_s *cur;
497 struct list_head *head = &adapter->mac_list;
499 while (!list_empty(head)) {
500 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
501 qlcnic_sre_macaddr_change(adapter,
502 cur->mac_addr, QLCNIC_MAC_DEL);
503 list_del(&cur->list);
508 #define QLCNIC_CONFIG_INTR_COALESCE 3
511 * Send the interrupt coalescing parameter set by ethtool to the card.
513 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
515 struct qlcnic_nic_req req;
519 memset(&req, 0, sizeof(struct qlcnic_nic_req));
521 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
523 word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
524 req.req_hdr = cpu_to_le64(word[0]);
526 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
527 for (i = 0; i < 6; i++)
528 req.words[i] = cpu_to_le64(word[i]);
530 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
532 dev_err(&adapter->netdev->dev,
533 "Could not send interrupt coalescing parameters\n");
538 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
540 struct qlcnic_nic_req req;
544 if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
547 memset(&req, 0, sizeof(struct qlcnic_nic_req));
549 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
551 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
552 req.req_hdr = cpu_to_le64(word);
554 req.words[0] = cpu_to_le64(enable);
556 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
558 dev_err(&adapter->netdev->dev,
559 "Could not send configure hw lro request\n");
561 adapter->flags ^= QLCNIC_LRO_ENABLED;
566 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable)
568 struct qlcnic_nic_req req;
572 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
575 memset(&req, 0, sizeof(struct qlcnic_nic_req));
577 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
579 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
580 ((u64)adapter->portnum << 16);
581 req.req_hdr = cpu_to_le64(word);
583 req.words[0] = cpu_to_le64(enable);
585 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
587 dev_err(&adapter->netdev->dev,
588 "Could not send configure bridge mode request\n");
590 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
596 #define RSS_HASHTYPE_IP_TCP 0x3
598 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
600 struct qlcnic_nic_req req;
604 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
605 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
606 0x255b0ec26d5a56daULL };
609 memset(&req, 0, sizeof(struct qlcnic_nic_req));
610 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
612 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
613 req.req_hdr = cpu_to_le64(word);
617 * bits 3-0: hash_method
618 * 5-4: hash_type_ipv4
619 * 7-6: hash_type_ipv6
621 * 9: use indirection table
623 * 63-48: indirection table mask
625 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
626 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
627 ((u64)(enable & 0x1) << 8) |
629 req.words[0] = cpu_to_le64(word);
630 for (i = 0; i < 5; i++)
631 req.words[i+1] = cpu_to_le64(key[i]);
633 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
635 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
640 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
642 struct qlcnic_nic_req req;
646 memset(&req, 0, sizeof(struct qlcnic_nic_req));
647 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
649 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
650 req.req_hdr = cpu_to_le64(word);
652 req.words[0] = cpu_to_le64(cmd);
653 req.words[1] = cpu_to_le64(ip);
655 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
657 dev_err(&adapter->netdev->dev,
658 "could not notify %s IP 0x%x reuqest\n",
659 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
664 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
666 struct qlcnic_nic_req req;
670 memset(&req, 0, sizeof(struct qlcnic_nic_req));
671 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
673 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
674 req.req_hdr = cpu_to_le64(word);
675 req.words[0] = cpu_to_le64(enable | (enable << 8));
677 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
679 dev_err(&adapter->netdev->dev,
680 "could not configure link notification\n");
685 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
687 struct qlcnic_nic_req req;
691 memset(&req, 0, sizeof(struct qlcnic_nic_req));
692 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
694 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
695 ((u64)adapter->portnum << 16) |
696 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
698 req.req_hdr = cpu_to_le64(word);
700 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
702 dev_err(&adapter->netdev->dev,
703 "could not cleanup lro flows\n");
709 * qlcnic_change_mtu - Change the Maximum Transfer Unit
710 * @returns 0 on success, negative on failure
713 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
715 struct qlcnic_adapter *adapter = netdev_priv(netdev);
718 if (mtu > P3_MAX_MTU) {
719 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
724 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
732 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac)
734 u32 crbaddr, mac_hi, mac_lo;
735 int pci_func = adapter->ahw.pci_func;
737 crbaddr = CRB_MAC_BLOCK_START +
738 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
740 mac_lo = QLCRD32(adapter, crbaddr);
741 mac_hi = QLCRD32(adapter, crbaddr+4);
744 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
746 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
752 * Changes the CRB window to the specified window.
754 /* Returns < 0 if off is not valid,
755 * 1 if window access is needed. 'off' is set to offset from
756 * CRB space in 128M pci map
757 * 0 if no window access is needed. 'off' is set to 2M addr
758 * In: 'off' is offset from base in 128M pci map
761 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
762 ulong off, void __iomem **addr)
764 const struct crb_128M_2M_sub_block_map *m;
766 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
769 off -= QLCNIC_PCI_CRBSPACE;
774 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
776 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
777 *addr = adapter->ahw.pci_base0 + m->start_2M +
778 (off - m->start_128M);
783 * Not in direct map, use crb window
785 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
790 * In: 'off' is offset from CRB space in 128M pci map
791 * Out: 'off' is 2M pci map addr
792 * side effect: lock crb window
795 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
798 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
800 off -= QLCNIC_PCI_CRBSPACE;
802 window = CRB_HI(off);
804 if (adapter->ahw.crb_win == window)
807 writel(window, addr);
808 if (readl(addr) != window) {
809 if (printk_ratelimit())
810 dev_warn(&adapter->pdev->dev,
811 "failed to set CRB window to %d off 0x%lx\n",
814 adapter->ahw.crb_win = window;
818 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
822 void __iomem *addr = NULL;
824 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
832 /* indirect access */
833 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
834 crb_win_lock(adapter);
835 qlcnic_pci_set_crbwindow_2M(adapter, off);
837 crb_win_unlock(adapter);
838 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
842 dev_err(&adapter->pdev->dev,
843 "%s: invalid offset: 0x%016lx\n", __func__, off);
849 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
854 void __iomem *addr = NULL;
856 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
862 /* indirect access */
863 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
864 crb_win_lock(adapter);
865 qlcnic_pci_set_crbwindow_2M(adapter, off);
867 crb_win_unlock(adapter);
868 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
872 dev_err(&adapter->pdev->dev,
873 "%s: invalid offset: 0x%016lx\n", __func__, off);
880 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
882 void __iomem *addr = NULL;
884 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
891 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
892 u64 addr, u32 *start)
895 struct pci_dev *pdev = adapter->pdev;
897 if ((addr & 0x00ff800) == 0xff800) {
898 if (printk_ratelimit())
899 dev_warn(&pdev->dev, "QM access not handled\n");
903 window = OCM_WIN_P3P(addr);
905 writel(window, adapter->ahw.ocm_win_crb);
906 /* read back to flush */
907 readl(adapter->ahw.ocm_win_crb);
909 adapter->ahw.ocm_win = window;
910 *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
915 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
918 void __iomem *addr, *mem_ptr = NULL;
919 resource_size_t mem_base;
923 mutex_lock(&adapter->ahw.mem_lock);
925 ret = qlcnic_pci_set_window_2M(adapter, off, &start);
929 addr = pci_base_offset(adapter, start);
933 mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
935 mem_ptr = ioremap(mem_base, PAGE_SIZE);
936 if (mem_ptr == NULL) {
941 addr = mem_ptr + (start & (PAGE_SIZE - 1));
944 if (op == 0) /* read */
950 mutex_unlock(&adapter->ahw.mem_lock);
957 #define MAX_CTL_CHECK 1000
960 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
966 void __iomem *mem_crb;
968 /* Only 64-bit aligned access */
972 /* P3 onward, test agent base for MIU and SIU is same */
973 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
974 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
975 mem_crb = qlcnic_get_ioaddr(adapter,
976 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
980 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
981 mem_crb = qlcnic_get_ioaddr(adapter,
982 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
986 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
987 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
992 stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
994 off8 = off & ~(stride-1);
996 mutex_lock(&adapter->ahw.mem_lock);
998 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
999 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1003 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1004 writel((TA_CTL_START | TA_CTL_ENABLE),
1005 (mem_crb + TEST_AGT_CTRL));
1007 for (j = 0; j < MAX_CTL_CHECK; j++) {
1008 temp = readl(mem_crb + TEST_AGT_CTRL);
1009 if ((temp & TA_CTL_BUSY) == 0)
1013 if (j >= MAX_CTL_CHECK) {
1018 i = (off & 0xf) ? 0 : 2;
1019 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1020 mem_crb + MIU_TEST_AGT_WRDATA(i));
1021 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1022 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1023 i = (off & 0xf) ? 2 : 0;
1026 writel(data & 0xffffffff,
1027 mem_crb + MIU_TEST_AGT_WRDATA(i));
1028 writel((data >> 32) & 0xffffffff,
1029 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1031 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1032 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1033 (mem_crb + TEST_AGT_CTRL));
1035 for (j = 0; j < MAX_CTL_CHECK; j++) {
1036 temp = readl(mem_crb + TEST_AGT_CTRL);
1037 if ((temp & TA_CTL_BUSY) == 0)
1041 if (j >= MAX_CTL_CHECK) {
1042 if (printk_ratelimit())
1043 dev_err(&adapter->pdev->dev,
1044 "failed to write through agent\n");
1050 mutex_unlock(&adapter->ahw.mem_lock);
1056 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1062 void __iomem *mem_crb;
1064 /* Only 64-bit aligned access */
1068 /* P3 onward, test agent base for MIU and SIU is same */
1069 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1070 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
1071 mem_crb = qlcnic_get_ioaddr(adapter,
1072 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1076 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1077 mem_crb = qlcnic_get_ioaddr(adapter,
1078 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1082 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1083 return qlcnic_pci_mem_access_direct(adapter,
1090 stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1092 off8 = off & ~(stride-1);
1094 mutex_lock(&adapter->ahw.mem_lock);
1096 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1097 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1098 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1099 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1101 for (j = 0; j < MAX_CTL_CHECK; j++) {
1102 temp = readl(mem_crb + TEST_AGT_CTRL);
1103 if ((temp & TA_CTL_BUSY) == 0)
1107 if (j >= MAX_CTL_CHECK) {
1108 if (printk_ratelimit())
1109 dev_err(&adapter->pdev->dev,
1110 "failed to read through agent\n");
1113 off8 = MIU_TEST_AGT_RDDATA_LO;
1114 if ((stride == 16) && (off & 0xf))
1115 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1117 temp = readl(mem_crb + off8 + 4);
1118 val = (u64)temp << 32;
1119 val |= readl(mem_crb + off8);
1124 mutex_unlock(&adapter->ahw.mem_lock);
1129 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1131 int offset, board_type, magic;
1132 struct pci_dev *pdev = adapter->pdev;
1134 offset = QLCNIC_FW_MAGIC_OFFSET;
1135 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1138 if (magic != QLCNIC_BDINFO_MAGIC) {
1139 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1144 offset = QLCNIC_BRDTYPE_OFFSET;
1145 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1148 adapter->ahw.board_type = board_type;
1150 if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1151 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1152 if ((gpio & 0x8000) == 0)
1153 board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1156 switch (board_type) {
1157 case QLCNIC_BRDTYPE_P3_HMEZ:
1158 case QLCNIC_BRDTYPE_P3_XG_LOM:
1159 case QLCNIC_BRDTYPE_P3_10G_CX4:
1160 case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1161 case QLCNIC_BRDTYPE_P3_IMEZ:
1162 case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1163 case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1164 case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1165 case QLCNIC_BRDTYPE_P3_10G_XFP:
1166 case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1167 adapter->ahw.port_type = QLCNIC_XGBE;
1169 case QLCNIC_BRDTYPE_P3_REF_QG:
1170 case QLCNIC_BRDTYPE_P3_4_GB:
1171 case QLCNIC_BRDTYPE_P3_4_GB_MM:
1172 adapter->ahw.port_type = QLCNIC_GBE;
1174 case QLCNIC_BRDTYPE_P3_10G_TP:
1175 adapter->ahw.port_type = (adapter->portnum < 2) ?
1176 QLCNIC_XGBE : QLCNIC_GBE;
1179 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1180 adapter->ahw.port_type = QLCNIC_XGBE;
1188 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1192 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1193 if (wol_cfg & (1UL << adapter->portnum)) {
1194 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1195 if (wol_cfg & (1 << adapter->portnum))
1202 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1204 struct qlcnic_nic_req req;
1208 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1209 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1211 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1212 req.req_hdr = cpu_to_le64(word);
1214 req.words[0] = cpu_to_le64((u64)rate << 32);
1215 req.words[1] = cpu_to_le64(state);
1217 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1219 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1224 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1226 struct qlcnic_nic_req req;
1230 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1231 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1233 word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1234 ((u64)adapter->portnum << 16);
1235 req.req_hdr = cpu_to_le64(word);
1236 req.words[0] = cpu_to_le64(flag);
1238 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1240 dev_err(&adapter->pdev->dev,
1241 "%sting loopback mode failed.\n",
1242 flag ? "Set" : "Reset");
1246 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1248 if (qlcnic_set_fw_loopback(adapter, 1))
1251 if (qlcnic_nic_set_promisc(adapter,
1252 VPORT_MISS_MODE_ACCEPT_ALL)) {
1253 qlcnic_set_fw_loopback(adapter, 0);
1261 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1263 int mode = VPORT_MISS_MODE_DROP;
1264 struct net_device *netdev = adapter->netdev;
1266 qlcnic_set_fw_loopback(adapter, 0);
1268 if (netdev->flags & IFF_PROMISC)
1269 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1270 else if (netdev->flags & IFF_ALLMULTI)
1271 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1273 qlcnic_nic_set_promisc(adapter, mode);