drivers/net/qlcnic/qlcnic_hw.c

   1 /*
   2  * Copyright (C) 2009 - QLogic Corporation.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called "COPYING".
  22  *
  23  */
  24
  25 #include "qlcnic.h"
  26
  27 #include <linux/slab.h>
  28 #include <net/ip.h>
  29
  30 #define MASK(n) ((1ULL<<(n))-1)
  31 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  32
  33 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  34
  35 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  36 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  37 #define CRB_WINDOW_2M   (0x130060)
  38 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  39 #define CRB_INDIRECT_2M (0x1e0000UL)
  40
  41
  42 #ifndef readq
  43 static inline u64 readq(void __iomem *addr)
  44 {
  45         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  46 }
  47 #endif
  48
  49 #ifndef writeq
  50 static inline void writeq(u64 val, void __iomem *addr)
  51 {
  52         writel(((u32) (val)), (addr));
  53         writel(((u32) (val >> 32)), (addr + 4));
  54 }
  55 #endif
  56
  57 static const struct crb_128M_2M_block_map
  58 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  59     {{{0, 0,         0,         0} } },         /* 0: PCI */
  60     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  61           {1, 0x0110000, 0x0120000, 0x130000},
  62           {1, 0x0120000, 0x0122000, 0x124000},
  63           {1, 0x0130000, 0x0132000, 0x126000},
  64           {1, 0x0140000, 0x0142000, 0x128000},
  65           {1, 0x0150000, 0x0152000, 0x12a000},
  66           {1, 0x0160000, 0x0170000, 0x110000},
  67           {1, 0x0170000, 0x0172000, 0x12e000},
  68           {0, 0x0000000, 0x0000000, 0x000000},
  69           {0, 0x0000000, 0x0000000, 0x000000},
  70           {0, 0x0000000, 0x0000000, 0x000000},
  71           {0, 0x0000000, 0x0000000, 0x000000},
  72           {0, 0x0000000, 0x0000000, 0x000000},
  73           {0, 0x0000000, 0x0000000, 0x000000},
  74           {1, 0x01e0000, 0x01e0800, 0x122000},
  75           {0, 0x0000000, 0x0000000, 0x000000} } },
  76         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  77     {{{0, 0,         0,         0} } },     /* 3: */
  78     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  79     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  80     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  81     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  82     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {0, 0x0000000, 0x0000000, 0x000000},
  92       {0, 0x0000000, 0x0000000, 0x000000},
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  98     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {0, 0x0000000, 0x0000000, 0x000000},
 108       {0, 0x0000000, 0x0000000, 0x000000},
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 114     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {0, 0x0000000, 0x0000000, 0x000000},
 124       {0, 0x0000000, 0x0000000, 0x000000},
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 130     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {0, 0x0000000, 0x0000000, 0x000000},
 140       {0, 0x0000000, 0x0000000, 0x000000},
 141       {0, 0x0000000, 0x0000000, 0x000000},
 142       {0, 0x0000000, 0x0000000, 0x000000},
 143       {0, 0x0000000, 0x0000000, 0x000000},
 144       {0, 0x0000000, 0x0000000, 0x000000},
 145       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 146         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 147         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 148         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 149         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 150         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 151         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 152         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 153         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 154         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 155         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 156         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 157         {{{0, 0,         0,         0} } },     /* 23: */
 158         {{{0, 0,         0,         0} } },     /* 24: */
 159         {{{0, 0,         0,         0} } },     /* 25: */
 160         {{{0, 0,         0,         0} } },     /* 26: */
 161         {{{0, 0,         0,         0} } },     /* 27: */
 162         {{{0, 0,         0,         0} } },     /* 28: */
 163         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 164     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 165     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 166         {{{0} } },                              /* 32: PCI */
 167         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 168           {1, 0x2110000, 0x2120000, 0x130000},
 169           {1, 0x2120000, 0x2122000, 0x124000},
 170           {1, 0x2130000, 0x2132000, 0x126000},
 171           {1, 0x2140000, 0x2142000, 0x128000},
 172           {1, 0x2150000, 0x2152000, 0x12a000},
 173           {1, 0x2160000, 0x2170000, 0x110000},
 174           {1, 0x2170000, 0x2172000, 0x12e000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000},
 177           {0, 0x0000000, 0x0000000, 0x000000},
 178           {0, 0x0000000, 0x0000000, 0x000000},
 179           {0, 0x0000000, 0x0000000, 0x000000},
 180           {0, 0x0000000, 0x0000000, 0x000000},
 181           {0, 0x0000000, 0x0000000, 0x000000},
 182           {0, 0x0000000, 0x0000000, 0x000000} } },
 183         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 184         {{{0} } },                              /* 35: */
 185         {{{0} } },                              /* 36: */
 186         {{{0} } },                              /* 37: */
 187         {{{0} } },                              /* 38: */
 188         {{{0} } },                              /* 39: */
 189         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 190         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 191         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 192         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 193         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 194         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 195         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 196         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 197         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 198         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 199         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 200         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 201         {{{0} } },                              /* 52: */
 202         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 203         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 204         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 205         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 206         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 207         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 208         {{{0} } },                              /* 59: I2C0 */
 209         {{{0} } },                              /* 60: I2C1 */
 210         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 211         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 212         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 213 };
 214
 215 /*
 216  * top 12 bits of crb internal address (hub, agent)
 217  */
 218 static const unsigned crb_hub_agt[64] = {
 219         0,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 223         0,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 240         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 243         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 245         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 246         0,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 248         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 249         0,
 250         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 251         0,
 252         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 254         0,
 255         0,
 256         0,
 257         0,
 258         0,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 260         0,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 265         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 270         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 271         0,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 274         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 276         0,
 277         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 278         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 279         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 280         0,
 281         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 282         0,
 283 };
 284
 285 /*  PCI Windowing for DDR regions.  */
 286
 287 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 288
 289 int
 290 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 291 {
 292         int done = 0, timeout = 0;
 293
 294         while (!done) {
 295                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 296                 if (done == 1)
 297                         break;
 298                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 299                         dev_err(&adapter->pdev->dev,
 300                                 "Failed to acquire sem=%d lock; holdby=%d\n",
 301                                 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
 302                         return -EIO;
 303                 }
 304                 msleep(1);
 305         }
 306
 307         if (id_reg)
 308                 QLCWR32(adapter, id_reg, adapter->portnum);
 309
 310         return 0;
 311 }
 312
 313 void
 314 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 315 {
 316         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 317 }
 318
 319 static int
 320 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 321                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 322 {
 323         u32 i, producer, consumer;
 324         struct qlcnic_cmd_buffer *pbuf;
 325         struct cmd_desc_type0 *cmd_desc;
 326         struct qlcnic_host_tx_ring *tx_ring;
 327
 328         i = 0;
 329
 330         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 331                 return -EIO;
 332
 333         tx_ring = adapter->tx_ring;
 334         __netif_tx_lock_bh(tx_ring->txq);
 335
 336         producer = tx_ring->producer;
 337         consumer = tx_ring->sw_consumer;
 338
 339         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 340                 netif_tx_stop_queue(tx_ring->txq);
 341                 smp_mb();
 342                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 343                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 344                                 netif_tx_wake_queue(tx_ring->txq);
 345                 } else {
 346                         adapter->stats.xmit_off++;
 347                         __netif_tx_unlock_bh(tx_ring->txq);
 348                         return -EBUSY;
 349                 }
 350         }
 351
 352         do {
 353                 cmd_desc = &cmd_desc_arr[i];
 354
 355                 pbuf = &tx_ring->cmd_buf_arr[producer];
 356                 pbuf->skb = NULL;
 357                 pbuf->frag_count = 0;
 358
 359                 memcpy(&tx_ring->desc_head[producer],
 360                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
 361
 362                 producer = get_next_index(producer, tx_ring->num_desc);
 363                 i++;
 364
 365         } while (i != nr_desc);
 366
 367         tx_ring->producer = producer;
 368
 369         qlcnic_update_cmd_producer(adapter, tx_ring);
 370
 371         __netif_tx_unlock_bh(tx_ring->txq);
 372
 373         return 0;
 374 }
 375
 376 static int
 377 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 378                                 u16 vlan_id, unsigned op)
 379 {
 380         struct qlcnic_nic_req req;
 381         struct qlcnic_mac_req *mac_req;
 382         u64 word;
 383
 384         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 385         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 386
 387         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 388         req.req_hdr = cpu_to_le64(word);
 389
 390         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 391         mac_req->op = op;
 392         memcpy(mac_req->mac_addr, addr, 6);
 393
 394         req.words[1] = cpu_to_le64(vlan_id);
 395
 396         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 397 }
 398
 399 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
 400 {
 401         struct list_head *head;
 402         struct qlcnic_mac_list_s *cur;
 403
 404         /* look up if already exists */
 405         list_for_each(head, &adapter->mac_list) {
 406                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 407                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 408                         return 0;
 409         }
 410
 411         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 412         if (cur == NULL) {
 413                 dev_err(&adapter->netdev->dev,
 414                         "failed to add mac address filter\n");
 415                 return -ENOMEM;
 416         }
 417         memcpy(cur->mac_addr, addr, ETH_ALEN);
 418
 419         if (qlcnic_sre_macaddr_change(adapter,
 420                                 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
 421                 kfree(cur);
 422                 return -EIO;
 423         }
 424
 425         list_add_tail(&cur->list, &adapter->mac_list);
 426         return 0;
 427 }
 428
 429 void qlcnic_set_multi(struct net_device *netdev)
 430 {
 431         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 432         struct netdev_hw_addr *ha;
 433         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 434         u32 mode = VPORT_MISS_MODE_DROP;
 435
 436         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 437                 return;
 438
 439         qlcnic_nic_add_mac(adapter, adapter->mac_addr);
 440         qlcnic_nic_add_mac(adapter, bcast_addr);
 441
 442         if (netdev->flags & IFF_PROMISC) {
 443                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 444                 goto send_fw_cmd;
 445         }
 446
 447         if ((netdev->flags & IFF_ALLMULTI) ||
 448             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
 449                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 450                 goto send_fw_cmd;
 451         }
 452
 453         if (!netdev_mc_empty(netdev)) {
 454                 netdev_for_each_mc_addr(ha, netdev) {
 455                         qlcnic_nic_add_mac(adapter, ha->addr);
 456                 }
 457         }
 458
 459 send_fw_cmd:
 460         qlcnic_nic_set_promisc(adapter, mode);
 461 }
 462
 463 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 464 {
 465         struct qlcnic_nic_req req;
 466         u64 word;
 467
 468         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 469
 470         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 471
 472         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
 473                         ((u64)adapter->portnum << 16);
 474         req.req_hdr = cpu_to_le64(word);
 475
 476         req.words[0] = cpu_to_le64(mode);
 477
 478         return qlcnic_send_cmd_descs(adapter,
 479                                 (struct cmd_desc_type0 *)&req, 1);
 480 }
 481
 482 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
 483 {
 484         struct qlcnic_mac_list_s *cur;
 485         struct list_head *head = &adapter->mac_list;
 486
 487         while (!list_empty(head)) {
 488                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 489                 qlcnic_sre_macaddr_change(adapter,
 490                                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
 491                 list_del(&cur->list);
 492                 kfree(cur);
 493         }
 494 }
 495
 496 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 497 {
 498         struct qlcnic_filter *tmp_fil;
 499         struct hlist_node *tmp_hnode, *n;
 500         struct hlist_head *head;
 501         int i;
 502
 503         for (i = 0; i < adapter->fhash.fmax; i++) {
 504                 head = &(adapter->fhash.fhead[i]);
 505
 506                 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
 507                 {
 508                         if (jiffies >
 509                                 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
 510                                 qlcnic_sre_macaddr_change(adapter,
 511                                         tmp_fil->faddr, tmp_fil->vlan_id,
 512                                         tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 513                                         QLCNIC_MAC_DEL);
 514                                 spin_lock_bh(&adapter->mac_learn_lock);
 515                                 adapter->fhash.fnum--;
 516                                 hlist_del(&tmp_fil->fnode);
 517                                 spin_unlock_bh(&adapter->mac_learn_lock);
 518                                 kfree(tmp_fil);
 519                         }
 520                 }
 521         }
 522 }
 523
 524 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 525 {
 526         struct qlcnic_filter *tmp_fil;
 527         struct hlist_node *tmp_hnode, *n;
 528         struct hlist_head *head;
 529         int i;
 530
 531         for (i = 0; i < adapter->fhash.fmax; i++) {
 532                 head = &(adapter->fhash.fhead[i]);
 533
 534                 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
 535                         qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
 536                                 tmp_fil->vlan_id, tmp_fil->vlan_id ?
 537                                 QLCNIC_MAC_VLAN_DEL :  QLCNIC_MAC_DEL);
 538                         spin_lock_bh(&adapter->mac_learn_lock);
 539                         adapter->fhash.fnum--;
 540                         hlist_del(&tmp_fil->fnode);
 541                         spin_unlock_bh(&adapter->mac_learn_lock);
 542                         kfree(tmp_fil);
 543                 }
 544         }
 545 }
 546
 547 #define QLCNIC_CONFIG_INTR_COALESCE     3
 548
 549 /*
 550  * Send the interrupt coalescing parameter set by ethtool to the card.
 551  */
 552 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
 553 {
 554         struct qlcnic_nic_req req;
 555         u64 word[6];
 556         int rv, i;
 557
 558         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 559
 560         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 561
 562         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
 563         req.req_hdr = cpu_to_le64(word[0]);
 564
 565         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
 566         for (i = 0; i < 6; i++)
 567                 req.words[i] = cpu_to_le64(word[i]);
 568
 569         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 570         if (rv != 0)
 571                 dev_err(&adapter->netdev->dev,
 572                         "Could not send interrupt coalescing parameters\n");
 573
 574         return rv;
 575 }
 576
 577 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 578 {
 579         struct qlcnic_nic_req req;
 580         u64 word;
 581         int rv;
 582
 583         if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
 584                 return 0;
 585
 586         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 587
 588         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 589
 590         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 591         req.req_hdr = cpu_to_le64(word);
 592
 593         req.words[0] = cpu_to_le64(enable);
 594
 595         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 596         if (rv != 0)
 597                 dev_err(&adapter->netdev->dev,
 598                         "Could not send configure hw lro request\n");
 599
 600         adapter->flags ^= QLCNIC_LRO_ENABLED;
 601
 602         return rv;
 603 }
 604
 605 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 606 {
 607         struct qlcnic_nic_req req;
 608         u64 word;
 609         int rv;
 610
 611         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 612                 return 0;
 613
 614         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 615
 616         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 617
 618         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 619                 ((u64)adapter->portnum << 16);
 620         req.req_hdr = cpu_to_le64(word);
 621
 622         req.words[0] = cpu_to_le64(enable);
 623
 624         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 625         if (rv != 0)
 626                 dev_err(&adapter->netdev->dev,
 627                         "Could not send configure bridge mode request\n");
 628
 629         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 630
 631         return rv;
 632 }
 633
 634
 635 #define RSS_HASHTYPE_IP_TCP     0x3
 636
 637 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
 638 {
 639         struct qlcnic_nic_req req;
 640         u64 word;
 641         int i, rv;
 642
 643         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 644                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 645                         0x255b0ec26d5a56daULL };
 646
 647
 648         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 649         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 650
 651         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 652         req.req_hdr = cpu_to_le64(word);
 653
 654         /*
 655          * RSS request:
 656          * bits 3-0: hash_method
 657          *      5-4: hash_type_ipv4
 658          *      7-6: hash_type_ipv6
 659          *        8: enable
 660          *        9: use indirection table
 661          *    47-10: reserved
 662          *    63-48: indirection table mask
 663          */
 664         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 665                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 666                 ((u64)(enable & 0x1) << 8) |
 667                 ((0x7ULL) << 48);
 668         req.words[0] = cpu_to_le64(word);
 669         for (i = 0; i < 5; i++)
 670                 req.words[i+1] = cpu_to_le64(key[i]);
 671
 672         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 673         if (rv != 0)
 674                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 675
 676         return rv;
 677 }
 678
 679 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
 680 {
 681         struct qlcnic_nic_req req;
 682         struct qlcnic_ipaddr *ipa;
 683         u64 word;
 684         int rv;
 685
 686         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 687         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 688
 689         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 690         req.req_hdr = cpu_to_le64(word);
 691
 692         req.words[0] = cpu_to_le64(cmd);
 693         ipa = (struct qlcnic_ipaddr *)&req.words[1];
 694         ipa->ipv4 = ip;
 695
 696         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 697         if (rv != 0)
 698                 dev_err(&adapter->netdev->dev,
 699                                 "could not notify %s IP 0x%x reuqest\n",
 700                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 701
 702         return rv;
 703 }
 704
 705 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 706 {
 707         struct qlcnic_nic_req req;
 708         u64 word;
 709         int rv;
 710
 711         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 712         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 713
 714         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 715         req.req_hdr = cpu_to_le64(word);
 716         req.words[0] = cpu_to_le64(enable | (enable << 8));
 717
 718         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 719         if (rv != 0)
 720                 dev_err(&adapter->netdev->dev,
 721                                 "could not configure link notification\n");
 722
 723         return rv;
 724 }
 725
 726 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 727 {
 728         struct qlcnic_nic_req req;
 729         u64 word;
 730         int rv;
 731
 732         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 733         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 734
 735         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 736                 ((u64)adapter->portnum << 16) |
 737                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 738
 739         req.req_hdr = cpu_to_le64(word);
 740
 741         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 742         if (rv != 0)
 743                 dev_err(&adapter->netdev->dev,
 744                                  "could not cleanup lro flows\n");
 745
 746         return rv;
 747 }
 748
 749 /*
 750  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 751  * @returns 0 on success, negative on failure
 752  */
 753
 754 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 755 {
 756         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 757         int rc = 0;
 758
 759         if (mtu > P3_MAX_MTU) {
 760                 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
 761                                                 P3_MAX_MTU);
 762                 return -EINVAL;
 763         }
 764
 765         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 766
 767         if (!rc)
 768                 netdev->mtu = mtu;
 769
 770         return rc;
 771 }
 772
 773 /*
 774  * Changes the CRB window to the specified window.
 775  */
 776  /* Returns < 0 if off is not valid,
 777  *       1 if window access is needed. 'off' is set to offset from
 778  *         CRB space in 128M pci map
 779  *       0 if no window access is needed. 'off' is set to 2M addr
 780  * In: 'off' is offset from base in 128M pci map
 781  */
 782 static int
 783 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
 784                 ulong off, void __iomem **addr)
 785 {
 786         const struct crb_128M_2M_sub_block_map *m;
 787
 788         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
 789                 return -EINVAL;
 790
 791         off -= QLCNIC_PCI_CRBSPACE;
 792
 793         /*
 794          * Try direct map
 795          */
 796         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
 797
 798         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
 799                 *addr = adapter->ahw.pci_base0 + m->start_2M +
 800                         (off - m->start_128M);
 801                 return 0;
 802         }
 803
 804         /*
 805          * Not in direct map, use crb window
 806          */
 807         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
 808         return 1;
 809 }
 810
 811 /*
 812  * In: 'off' is offset from CRB space in 128M pci map
 813  * Out: 'off' is 2M pci map addr
 814  * side effect: lock crb window
 815  */
 816 static int
 817 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
 818 {
 819         u32 window;
 820         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
 821
 822         off -= QLCNIC_PCI_CRBSPACE;
 823
 824         window = CRB_HI(off);
 825         if (window == 0) {
 826                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
 827                 return -EIO;
 828         }
 829
 830         writel(window, addr);
 831         if (readl(addr) != window) {
 832                 if (printk_ratelimit())
 833                         dev_warn(&adapter->pdev->dev,
 834                                 "failed to set CRB window to %d off 0x%lx\n",
 835                                 window, off);
 836                 return -EIO;
 837         }
 838         return 0;
 839 }
 840
 841 int
 842 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
 843 {
 844         unsigned long flags;
 845         int rv;
 846         void __iomem *addr = NULL;
 847
 848         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 849
 850         if (rv == 0) {
 851                 writel(data, addr);
 852                 return 0;
 853         }
 854
 855         if (rv > 0) {
 856                 /* indirect access */
 857                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 858                 crb_win_lock(adapter);
 859                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
 860                 if (!rv)
 861                         writel(data, addr);
 862                 crb_win_unlock(adapter);
 863                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 864                 return rv;
 865         }
 866
 867         dev_err(&adapter->pdev->dev,
 868                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 869         dump_stack();
 870         return -EIO;
 871 }
 872
 873 u32
 874 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
 875 {
 876         unsigned long flags;
 877         int rv;
 878         u32 data = -1;
 879         void __iomem *addr = NULL;
 880
 881         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 882
 883         if (rv == 0)
 884                 return readl(addr);
 885
 886         if (rv > 0) {
 887                 /* indirect access */
 888                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 889                 crb_win_lock(adapter);
 890                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
 891                         data = readl(addr);
 892                 crb_win_unlock(adapter);
 893                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 894                 return data;
 895         }
 896
 897         dev_err(&adapter->pdev->dev,
 898                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 899         dump_stack();
 900         return -1;
 901 }
 902
 903
 904 void __iomem *
 905 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
 906 {
 907         void __iomem *addr = NULL;
 908
 909         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
 910
 911         return addr;
 912 }
 913
 914
 915 static int
 916 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
 917                 u64 addr, u32 *start)
 918 {
 919         u32 window;
 920
 921         window = OCM_WIN_P3P(addr);
 922
 923         writel(window, adapter->ahw.ocm_win_crb);
 924         /* read back to flush */
 925         readl(adapter->ahw.ocm_win_crb);
 926
 927         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
 928         return 0;
 929 }
 930
 931 static int
 932 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
 933                 u64 *data, int op)
 934 {
 935         void __iomem *addr;
 936         int ret;
 937         u32 start;
 938
 939         mutex_lock(&adapter->ahw.mem_lock);
 940
 941         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
 942         if (ret != 0)
 943                 goto unlock;
 944
 945         addr = adapter->ahw.pci_base0 + start;
 946
 947         if (op == 0)    /* read */
 948                 *data = readq(addr);
 949         else            /* write */
 950                 writeq(*data, addr);
 951
 952 unlock:
 953         mutex_unlock(&adapter->ahw.mem_lock);
 954
 955         return ret;
 956 }
 957
 958 void
 959 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
 960 {
 961         void __iomem *addr = adapter->ahw.pci_base0 +
 962                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 963
 964         mutex_lock(&adapter->ahw.mem_lock);
 965         *data = readq(addr);
 966         mutex_unlock(&adapter->ahw.mem_lock);
 967 }
 968
 969 void
 970 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
 971 {
 972         void __iomem *addr = adapter->ahw.pci_base0 +
 973                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 974
 975         mutex_lock(&adapter->ahw.mem_lock);
 976         writeq(data, addr);
 977         mutex_unlock(&adapter->ahw.mem_lock);
 978 }
 979
 980 #define MAX_CTL_CHECK   1000
 981
 982 int
 983 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
 984                 u64 off, u64 data)
 985 {
 986         int i, j, ret;
 987         u32 temp, off8;
 988         void __iomem *mem_crb;
 989
 990         /* Only 64-bit aligned access */
 991         if (off & 7)
 992                 return -EIO;
 993
 994         /* P3 onward, test agent base for MIU and SIU is same */
 995         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
 996                                 QLCNIC_ADDR_QDR_NET_MAX)) {
 997                 mem_crb = qlcnic_get_ioaddr(adapter,
 998                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
 999                 goto correct;
1000         }
1001
1002         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1003                 mem_crb = qlcnic_get_ioaddr(adapter,
1004                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1005                 goto correct;
1006         }
1007
1008         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1009                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
1010
1011         return -EIO;
1012
1013 correct:
1014         off8 = off & ~0xf;
1015
1016         mutex_lock(&adapter->ahw.mem_lock);
1017
1018         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1019         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1020
1021         i = 0;
1022         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1023         writel((TA_CTL_START | TA_CTL_ENABLE),
1024                         (mem_crb + TEST_AGT_CTRL));
1025
1026         for (j = 0; j < MAX_CTL_CHECK; j++) {
1027                 temp = readl(mem_crb + TEST_AGT_CTRL);
1028                 if ((temp & TA_CTL_BUSY) == 0)
1029                         break;
1030         }
1031
1032         if (j >= MAX_CTL_CHECK) {
1033                 ret = -EIO;
1034                 goto done;
1035         }
1036
1037         i = (off & 0xf) ? 0 : 2;
1038         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1039                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1040         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1041                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1042         i = (off & 0xf) ? 2 : 0;
1043
1044         writel(data & 0xffffffff,
1045                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1046         writel((data >> 32) & 0xffffffff,
1047                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1048
1049         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1050         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1051                         (mem_crb + TEST_AGT_CTRL));
1052
1053         for (j = 0; j < MAX_CTL_CHECK; j++) {
1054                 temp = readl(mem_crb + TEST_AGT_CTRL);
1055                 if ((temp & TA_CTL_BUSY) == 0)
1056                         break;
1057         }
1058
1059         if (j >= MAX_CTL_CHECK) {
1060                 if (printk_ratelimit())
1061                         dev_err(&adapter->pdev->dev,
1062                                         "failed to write through agent\n");
1063                 ret = -EIO;
1064         } else
1065                 ret = 0;
1066
1067 done:
1068         mutex_unlock(&adapter->ahw.mem_lock);
1069
1070         return ret;
1071 }
1072
1073 int
1074 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1075                 u64 off, u64 *data)
1076 {
1077         int j, ret;
1078         u32 temp, off8;
1079         u64 val;
1080         void __iomem *mem_crb;
1081
1082         /* Only 64-bit aligned access */
1083         if (off & 7)
1084                 return -EIO;
1085
1086         /* P3 onward, test agent base for MIU and SIU is same */
1087         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1088                                 QLCNIC_ADDR_QDR_NET_MAX)) {
1089                 mem_crb = qlcnic_get_ioaddr(adapter,
1090                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1091                 goto correct;
1092         }
1093
1094         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1095                 mem_crb = qlcnic_get_ioaddr(adapter,
1096                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1097                 goto correct;
1098         }
1099
1100         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1101                 return qlcnic_pci_mem_access_direct(adapter,
1102                                 off, data, 0);
1103         }
1104
1105         return -EIO;
1106
1107 correct:
1108         off8 = off & ~0xf;
1109
1110         mutex_lock(&adapter->ahw.mem_lock);
1111
1112         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1113         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1114         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1115         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1116
1117         for (j = 0; j < MAX_CTL_CHECK; j++) {
1118                 temp = readl(mem_crb + TEST_AGT_CTRL);
1119                 if ((temp & TA_CTL_BUSY) == 0)
1120                         break;
1121         }
1122
1123         if (j >= MAX_CTL_CHECK) {
1124                 if (printk_ratelimit())
1125                         dev_err(&adapter->pdev->dev,
1126                                         "failed to read through agent\n");
1127                 ret = -EIO;
1128         } else {
1129                 off8 = MIU_TEST_AGT_RDDATA_LO;
1130                 if (off & 0xf)
1131                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1132
1133                 temp = readl(mem_crb + off8 + 4);
1134                 val = (u64)temp << 32;
1135                 val |= readl(mem_crb + off8);
1136                 *data = val;
1137                 ret = 0;
1138         }
1139
1140         mutex_unlock(&adapter->ahw.mem_lock);
1141
1142         return ret;
1143 }
1144
1145 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1146 {
1147         int offset, board_type, magic;
1148         struct pci_dev *pdev = adapter->pdev;
1149
1150         offset = QLCNIC_FW_MAGIC_OFFSET;
1151         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1152                 return -EIO;
1153
1154         if (magic != QLCNIC_BDINFO_MAGIC) {
1155                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1156                         magic);
1157                 return -EIO;
1158         }
1159
1160         offset = QLCNIC_BRDTYPE_OFFSET;
1161         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1162                 return -EIO;
1163
1164         adapter->ahw.board_type = board_type;
1165
1166         if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1167                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1168                 if ((gpio & 0x8000) == 0)
1169                         board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1170         }
1171
1172         switch (board_type) {
1173         case QLCNIC_BRDTYPE_P3_HMEZ:
1174         case QLCNIC_BRDTYPE_P3_XG_LOM:
1175         case QLCNIC_BRDTYPE_P3_10G_CX4:
1176         case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1177         case QLCNIC_BRDTYPE_P3_IMEZ:
1178         case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1179         case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1180         case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1181         case QLCNIC_BRDTYPE_P3_10G_XFP:
1182         case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1183                 adapter->ahw.port_type = QLCNIC_XGBE;
1184                 break;
1185         case QLCNIC_BRDTYPE_P3_REF_QG:
1186         case QLCNIC_BRDTYPE_P3_4_GB:
1187         case QLCNIC_BRDTYPE_P3_4_GB_MM:
1188                 adapter->ahw.port_type = QLCNIC_GBE;
1189                 break;
1190         case QLCNIC_BRDTYPE_P3_10G_TP:
1191                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1192                         QLCNIC_XGBE : QLCNIC_GBE;
1193                 break;
1194         default:
1195                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1196                 adapter->ahw.port_type = QLCNIC_XGBE;
1197                 break;
1198         }
1199
1200         return 0;
1201 }
1202
1203 int
1204 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1205 {
1206         u32 wol_cfg;
1207
1208         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1209         if (wol_cfg & (1UL << adapter->portnum)) {
1210                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1211                 if (wol_cfg & (1 << adapter->portnum))
1212                         return 1;
1213         }
1214
1215         return 0;
1216 }
1217
1218 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1219 {
1220         struct qlcnic_nic_req   req;
1221         int rv;
1222         u64 word;
1223
1224         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1225         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1226
1227         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1228         req.req_hdr = cpu_to_le64(word);
1229
1230         req.words[0] = cpu_to_le64((u64)rate << 32);
1231         req.words[1] = cpu_to_le64(state);
1232
1233         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1234         if (rv)
1235                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1236
1237         return rv;
1238 }
1239
1240 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1241 {
1242         struct qlcnic_nic_req   req;
1243         int                     rv;
1244         u64                     word;
1245
1246         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1247         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1248
1249         word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1250                         ((u64)adapter->portnum << 16);
1251         req.req_hdr = cpu_to_le64(word);
1252         req.words[0] = cpu_to_le64(flag);
1253
1254         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1255         if (rv)
1256                 dev_err(&adapter->pdev->dev,
1257                         "%sting loopback mode failed.\n",
1258                                         flag ? "Set" : "Reset");
1259         return rv;
1260 }
1261
1262 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1263 {
1264         if (qlcnic_set_fw_loopback(adapter, 1))
1265                 return -EIO;
1266
1267         if (qlcnic_nic_set_promisc(adapter,
1268                                 VPORT_MISS_MODE_ACCEPT_ALL)) {
1269                 qlcnic_set_fw_loopback(adapter, 0);
1270                 return -EIO;
1271         }
1272
1273         msleep(1000);
1274         return 0;
1275 }
1276
1277 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1278 {
1279         int mode = VPORT_MISS_MODE_DROP;
1280         struct net_device *netdev = adapter->netdev;
1281
1282         qlcnic_set_fw_loopback(adapter, 0);
1283
1284         if (netdev->flags & IFF_PROMISC)
1285                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1286         else if (netdev->flags & IFF_ALLMULTI)
1287                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1288
1289         qlcnic_nic_set_promisc(adapter, mode);
1290         msleep(1000);
1291 }