2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 * Source file for NIC routines to access the Phantom hardware
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #define DEFINE_GLOBAL_RECV_CRB
37 #include "netxen_nic_phan_reg.h"
42 struct netxen_recv_crb recv_crb_registers[] = {
50 /* crb_rcv_producer_offset: */
51 NETXEN_NIC_REG(0x100),
52 /* crb_rcv_consumer_offset: */
53 NETXEN_NIC_REG(0x104),
54 /* crb_gloablrcv_ring: */
55 NETXEN_NIC_REG(0x108),
56 /* crb_rcv_ring_size */
57 NETXEN_NIC_REG(0x10c),
62 /* crb_rcv_producer_offset: */
63 NETXEN_NIC_REG(0x110),
64 /* crb_rcv_consumer_offset: */
65 NETXEN_NIC_REG(0x114),
66 /* crb_gloablrcv_ring: */
67 NETXEN_NIC_REG(0x118),
68 /* crb_rcv_ring_size */
69 NETXEN_NIC_REG(0x11c),
73 /* crb_rcv_producer_offset: */
74 NETXEN_NIC_REG(0x120),
75 /* crb_rcv_consumer_offset: */
76 NETXEN_NIC_REG(0x124),
77 /* crb_gloablrcv_ring: */
78 NETXEN_NIC_REG(0x128),
79 /* crb_rcv_ring_size */
80 NETXEN_NIC_REG(0x12c),
83 /* crb_rcvstatus_ring: */
84 NETXEN_NIC_REG(0x130),
85 /* crb_rcv_status_producer: */
86 NETXEN_NIC_REG(0x134),
87 /* crb_rcv_status_consumer: */
88 NETXEN_NIC_REG(0x138),
89 /* crb_rcvpeg_state: */
90 NETXEN_NIC_REG(0x13c),
91 /* crb_status_ring_size */
92 NETXEN_NIC_REG(0x140),
102 /* crb_rcv_producer_offset: */
103 NETXEN_NIC_REG(0x144),
104 /* crb_rcv_consumer_offset: */
105 NETXEN_NIC_REG(0x148),
106 /* crb_globalrcv_ring: */
107 NETXEN_NIC_REG(0x14c),
108 /* crb_rcv_ring_size */
109 NETXEN_NIC_REG(0x150),
114 /* crb_rcv_producer_offset: */
115 NETXEN_NIC_REG(0x154),
116 /* crb_rcv_consumer_offset: */
117 NETXEN_NIC_REG(0x158),
118 /* crb_globalrcv_ring: */
119 NETXEN_NIC_REG(0x15c),
120 /* crb_rcv_ring_size */
121 NETXEN_NIC_REG(0x160),
125 /* crb_rcv_producer_offset: */
126 NETXEN_NIC_REG(0x164),
127 /* crb_rcv_consumer_offset: */
128 NETXEN_NIC_REG(0x168),
129 /* crb_globalrcv_ring: */
130 NETXEN_NIC_REG(0x16c),
131 /* crb_rcv_ring_size */
132 NETXEN_NIC_REG(0x170),
136 /* crb_rcvstatus_ring: */
137 NETXEN_NIC_REG(0x174),
138 /* crb_rcv_status_producer: */
139 NETXEN_NIC_REG(0x178),
140 /* crb_rcv_status_consumer: */
141 NETXEN_NIC_REG(0x17c),
142 /* crb_rcvpeg_state: */
143 NETXEN_NIC_REG(0x180),
144 /* crb_status_ring_size */
145 NETXEN_NIC_REG(0x184),
153 /* crb_rcv_producer_offset: */
154 NETXEN_NIC_REG(0x1d8),
155 /* crb_rcv_consumer_offset: */
156 NETXEN_NIC_REG(0x1dc),
157 /* crb_gloablrcv_ring: */
158 NETXEN_NIC_REG(0x1f0),
159 /* crb_rcv_ring_size */
160 NETXEN_NIC_REG(0x1f4),
164 /* crb_rcv_producer_offset: */
165 NETXEN_NIC_REG(0x1f8),
166 /* crb_rcv_consumer_offset: */
167 NETXEN_NIC_REG(0x1fc),
168 /* crb_gloablrcv_ring: */
169 NETXEN_NIC_REG(0x200),
170 /* crb_rcv_ring_size */
171 NETXEN_NIC_REG(0x204),
175 /* crb_rcv_producer_offset: */
176 NETXEN_NIC_REG(0x208),
177 /* crb_rcv_consumer_offset: */
178 NETXEN_NIC_REG(0x20c),
179 /* crb_gloablrcv_ring: */
180 NETXEN_NIC_REG(0x210),
181 /* crb_rcv_ring_size */
182 NETXEN_NIC_REG(0x214),
185 /* crb_rcvstatus_ring: */
186 NETXEN_NIC_REG(0x218),
187 /* crb_rcv_status_producer: */
188 NETXEN_NIC_REG(0x21c),
189 /* crb_rcv_status_consumer: */
190 NETXEN_NIC_REG(0x220),
191 /* crb_rcvpeg_state: */
192 NETXEN_NIC_REG(0x224),
193 /* crb_status_ring_size */
194 NETXEN_NIC_REG(0x228),
202 /* crb_rcv_producer_offset: */
203 NETXEN_NIC_REG(0x22c),
204 /* crb_rcv_consumer_offset: */
205 NETXEN_NIC_REG(0x230),
206 /* crb_gloablrcv_ring: */
207 NETXEN_NIC_REG(0x234),
208 /* crb_rcv_ring_size */
209 NETXEN_NIC_REG(0x238),
213 /* crb_rcv_producer_offset: */
214 NETXEN_NIC_REG(0x23c),
215 /* crb_rcv_consumer_offset: */
216 NETXEN_NIC_REG(0x240),
217 /* crb_gloablrcv_ring: */
218 NETXEN_NIC_REG(0x244),
219 /* crb_rcv_ring_size */
220 NETXEN_NIC_REG(0x248),
224 /* crb_rcv_producer_offset: */
225 NETXEN_NIC_REG(0x24c),
226 /* crb_rcv_consumer_offset: */
227 NETXEN_NIC_REG(0x250),
228 /* crb_gloablrcv_ring: */
229 NETXEN_NIC_REG(0x254),
230 /* crb_rcv_ring_size */
231 NETXEN_NIC_REG(0x258),
234 /* crb_rcvstatus_ring: */
235 NETXEN_NIC_REG(0x25c),
236 /* crb_rcv_status_producer: */
237 NETXEN_NIC_REG(0x260),
238 /* crb_rcv_status_consumer: */
239 NETXEN_NIC_REG(0x264),
240 /* crb_rcvpeg_state: */
241 NETXEN_NIC_REG(0x268),
242 /* crb_status_ring_size */
243 NETXEN_NIC_REG(0x26c),
247 u64 ctx_addr_sig_regs[][3] = {
248 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
249 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
250 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
251 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
255 /* PCI Windowing for DDR regions. */
257 #define ADDR_IN_RANGE(addr, low, high) \
258 (((addr) <= (high)) && ((addr) >= (low)))
260 #define NETXEN_FLASH_BASE (BOOTLD_START)
261 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
262 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
263 #define NETXEN_MIN_MTU 64
264 #define NETXEN_ETH_FCS_SIZE 4
265 #define NETXEN_ENET_HEADER_SIZE 14
266 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
267 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
268 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
269 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
271 #define lower32(x) ((u32)((x) & 0xffffffff))
273 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
275 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
276 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
277 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
278 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
280 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
282 unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
283 unsigned long long addr);
284 void netxen_free_hw_resources(struct netxen_adapter *adapter);
286 int netxen_nic_set_mac(struct net_device *netdev, void *p)
288 struct netxen_adapter *adapter = netdev_priv(netdev);
289 struct sockaddr *addr = p;
291 if (netif_running(netdev))
294 if (!is_valid_ether_addr(addr->sa_data))
295 return -EADDRNOTAVAIL;
297 DPRINTK(INFO, "valid ether addr\n");
298 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
300 if (adapter->macaddr_set)
301 adapter->macaddr_set(adapter, addr->sa_data);
307 * netxen_nic_set_multi - Multicast
309 void netxen_nic_set_multi(struct net_device *netdev)
311 struct netxen_adapter *adapter = netdev_priv(netdev);
312 struct dev_mc_list *mc_ptr;
313 __u32 netxen_mac_addr_cntl_data = 0;
315 mc_ptr = netdev->mc_list;
316 if (netdev->flags & IFF_PROMISC) {
317 if (adapter->set_promisc)
318 adapter->set_promisc(adapter,
319 NETXEN_NIU_PROMISC_MODE);
321 if (adapter->unset_promisc &&
322 adapter->ahw.boardcfg.board_type
323 != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
324 adapter->unset_promisc(adapter,
325 NETXEN_NIU_NON_PROMISC_MODE);
327 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
328 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
329 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
330 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00);
331 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00);
332 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00);
333 netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data);
334 netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data);
335 netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data);
336 netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data);
338 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00);
339 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
340 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01);
341 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02);
342 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03);
344 writel(netxen_mac_addr_cntl_data,
345 NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG));
346 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
347 writel(netxen_mac_addr_cntl_data,
348 NETXEN_CRB_NORMALIZE(adapter,
349 NETXEN_MULTICAST_ADDR_HI_0));
351 writel(netxen_mac_addr_cntl_data,
352 NETXEN_CRB_NORMALIZE(adapter,
353 NETXEN_MULTICAST_ADDR_HI_1));
355 netxen_mac_addr_cntl_data = 0;
356 writel(netxen_mac_addr_cntl_data,
357 NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR));
361 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
362 * @returns 0 on success, negative on failure
364 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
366 struct netxen_adapter *adapter = netdev_priv(netdev);
367 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
369 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
370 printk(KERN_ERR "%s: %s %d is not supported.\n",
371 netxen_nic_driver_name, netdev->name, mtu);
375 if (adapter->set_mtu)
376 adapter->set_mtu(adapter, mtu);
383 * check if the firmware has been downloaded and ready to run and
384 * setup the address for the descriptors in the adapter
386 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
388 struct netxen_hardware_context *hw = &adapter->ahw;
391 int loops = 0, err = 0;
393 u32 card_cmdring = 0;
394 struct netxen_recv_context *recv_ctx;
395 struct netxen_rcv_desc_ctx *rcv_desc;
396 int func_id = adapter->portnum;
398 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
399 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
400 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
401 pci_base_offset(adapter, NETXEN_CRB_CAM));
402 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
403 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
406 card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
408 DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n",
411 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
412 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
416 state = readl(NETXEN_CRB_NORMALIZE(adapter,
417 recv_crb_registers[ctx].
419 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
422 state = readl(NETXEN_CRB_NORMALIZE(adapter,
429 printk(KERN_ERR "Rcv Peg initialization not complete:"
435 DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
437 addr = netxen_alloc(adapter->ahw.pdev,
438 sizeof(struct netxen_ring_ctx) +
440 (dma_addr_t *) & adapter->ctx_desc_phys_addr,
441 &adapter->ctx_desc_pdev);
443 printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
444 (unsigned long long) adapter->ctx_desc_phys_addr);
446 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
450 memset(addr, 0, sizeof(struct netxen_ring_ctx));
451 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
452 adapter->ctx_desc->ctx_id = adapter->portnum;
453 adapter->ctx_desc->cmd_consumer_offset =
454 cpu_to_le64(adapter->ctx_desc_phys_addr +
455 sizeof(struct netxen_ring_ctx));
456 adapter->cmd_consumer = (uint32_t *) (((char *)addr) +
457 sizeof(struct netxen_ring_ctx));
459 addr = netxen_alloc(adapter->ahw.pdev,
460 sizeof(struct cmd_desc_type0) *
461 adapter->max_tx_desc_count,
462 (dma_addr_t *) & hw->cmd_desc_phys_addr,
463 &adapter->ahw.cmd_desc_pdev);
464 printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
465 (unsigned long long) hw->cmd_desc_phys_addr);
468 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
469 netxen_free_hw_resources(adapter);
473 adapter->ctx_desc->cmd_ring_addr =
474 cpu_to_le64(hw->cmd_desc_phys_addr);
475 adapter->ctx_desc->cmd_ring_size =
476 cpu_to_le32(adapter->max_tx_desc_count);
478 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
480 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
481 recv_ctx = &adapter->recv_ctx[ctx];
483 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
484 rcv_desc = &recv_ctx->rcv_desc[ring];
485 addr = netxen_alloc(adapter->ahw.pdev,
487 &rcv_desc->phys_addr,
488 &rcv_desc->phys_pdev);
490 DPRINTK(ERR, "bad return from "
491 "pci_alloc_consistent\n");
492 netxen_free_hw_resources(adapter);
496 rcv_desc->desc_head = (struct rcv_desc *)addr;
497 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
498 cpu_to_le64(rcv_desc->phys_addr);
499 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
500 cpu_to_le32(rcv_desc->max_rx_desc_count);
503 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
504 &recv_ctx->rcv_status_desc_phys_addr,
505 &recv_ctx->rcv_status_desc_pdev);
507 DPRINTK(ERR, "bad return from"
508 " pci_alloc_consistent\n");
509 netxen_free_hw_resources(adapter);
513 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
514 adapter->ctx_desc->sts_ring_addr =
515 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
516 adapter->ctx_desc->sts_ring_size =
517 cpu_to_le32(adapter->max_rx_desc_count);
522 writel(lower32(adapter->ctx_desc_phys_addr),
523 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
524 writel(upper32(adapter->ctx_desc_phys_addr),
525 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
526 writel(NETXEN_CTX_SIGNATURE | func_id,
527 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
531 void netxen_free_hw_resources(struct netxen_adapter *adapter)
533 struct netxen_recv_context *recv_ctx;
534 struct netxen_rcv_desc_ctx *rcv_desc;
537 if (adapter->ctx_desc != NULL) {
538 pci_free_consistent(adapter->ctx_desc_pdev,
539 sizeof(struct netxen_ring_ctx) +
542 adapter->ctx_desc_phys_addr);
543 adapter->ctx_desc = NULL;
546 if (adapter->ahw.cmd_desc_head != NULL) {
547 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
548 sizeof(struct cmd_desc_type0) *
549 adapter->max_tx_desc_count,
550 adapter->ahw.cmd_desc_head,
551 adapter->ahw.cmd_desc_phys_addr);
552 adapter->ahw.cmd_desc_head = NULL;
554 /* Special handling: there are 2 ports on this board */
555 if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
556 adapter->ahw.max_ports = 2;
559 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
560 recv_ctx = &adapter->recv_ctx[ctx];
561 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
562 rcv_desc = &recv_ctx->rcv_desc[ring];
564 if (rcv_desc->desc_head != NULL) {
565 pci_free_consistent(rcv_desc->phys_pdev,
568 rcv_desc->phys_addr);
569 rcv_desc->desc_head = NULL;
573 if (recv_ctx->rcv_status_desc_head != NULL) {
574 pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
575 STATUS_DESC_RINGSIZE,
576 recv_ctx->rcv_status_desc_head,
578 rcv_status_desc_phys_addr);
579 recv_ctx->rcv_status_desc_head = NULL;
584 void netxen_tso_check(struct netxen_adapter *adapter,
585 struct cmd_desc_type0 *desc, struct sk_buff *skb)
588 desc->total_hdr_length = (sizeof(struct ethhdr) +
589 ip_hdrlen(skb) + tcp_hdrlen(skb));
590 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
591 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
592 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
593 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
594 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
595 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
600 desc->tcp_hdr_offset = skb_transport_offset(skb);
601 desc->ip_hdr_offset = skb_network_offset(skb);
604 int netxen_is_flash_supported(struct netxen_adapter *adapter)
606 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
607 int addr, val01, val02, i, j;
609 /* if the flash size less than 4Mb, make huge war cry and die */
610 for (j = 1; j < 4; j++) {
611 addr = j * NETXEN_NIC_WINDOW_MARGIN;
612 for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
613 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
614 && netxen_rom_fast_read(adapter, (addr + locs[i]),
626 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
634 for (i = 0; i < size / sizeof(u32); i++) {
635 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
637 *ptr32 = cpu_to_le32(*ptr32);
641 if ((char *)buf + size > (char *)ptr32) {
644 if (netxen_rom_fast_read(adapter, addr, &local) == -1)
646 local = cpu_to_le32(local);
647 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
653 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
655 u32 *pmac = (u32 *) & mac[0];
657 if (netxen_get_flash_block(adapter,
659 offsetof(struct netxen_new_user_info,
661 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
665 if (netxen_get_flash_block(adapter,
667 offsetof(struct netxen_user_old_info,
669 FLASH_NUM_PORTS * sizeof(u64),
679 * Changes the CRB window to the specified window.
681 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
683 void __iomem *offset;
687 if (adapter->curr_window == wndw)
689 switch(adapter->ahw.pci_func) {
691 offset = PCI_OFFSET_SECOND_RANGE(adapter,
692 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
695 offset = PCI_OFFSET_SECOND_RANGE(adapter,
696 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
699 offset = PCI_OFFSET_SECOND_RANGE(adapter,
700 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
703 offset = PCI_OFFSET_SECOND_RANGE(adapter,
704 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
707 printk(KERN_INFO "Changing the window for PCI function"
708 "%d\n", adapter->ahw.pci_func);
709 offset = PCI_OFFSET_SECOND_RANGE(adapter,
710 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
714 * Move the CRB window.
715 * We need to write to the "direct access" region of PCI
716 * to avoid a race condition where the window register has
717 * not been successfully written across CRB before the target
718 * register address is received by PCI. The direct region bypasses
723 wndw = NETXEN_WINDOW_ONE;
725 writel(wndw, offset);
727 /* MUST make sure window is set before we forge on... */
728 while ((tmp = readl(offset)) != wndw) {
729 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
730 "registered properly: 0x%08x.\n",
731 netxen_nic_driver_name, __FUNCTION__, tmp);
738 adapter->curr_window = wndw;
741 void netxen_load_firmware(struct netxen_adapter *adapter)
745 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
749 size = NETXEN_FIRMWARE_LEN;
750 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
752 for (i = 0; i < size; i++) {
753 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
755 "Error in netxen_rom_fast_read(). Will skip"
756 "loading flash image\n");
759 off = netxen_nic_pci_set_window(adapter, memaddr);
760 addr = pci_base_offset(adapter, off);
766 /* make sure Casper is powered on */
768 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
769 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
775 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
780 if (ADDR_IN_WINDOW1(off)) {
781 addr = NETXEN_CRB_NORMALIZE(adapter, off);
782 } else { /* Window 0 */
783 addr = pci_base_offset(adapter, off);
784 netxen_nic_pci_change_crbwindow(adapter, 0);
787 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
788 " data %llx len %d\n",
789 pci_base(adapter, off), off, addr,
790 *(unsigned long long *)data, len);
792 netxen_nic_pci_change_crbwindow(adapter, 1);
798 writeb(*(u8 *) data, addr);
801 writew(*(u16 *) data, addr);
804 writel(*(u32 *) data, addr);
807 writeq(*(u64 *) data, addr);
811 "writing data %lx to offset %llx, num words=%d\n",
812 *(unsigned long *)data, off, (len >> 3));
814 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
818 if (!ADDR_IN_WINDOW1(off))
819 netxen_nic_pci_change_crbwindow(adapter, 1);
825 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
830 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
831 addr = NETXEN_CRB_NORMALIZE(adapter, off);
832 } else { /* Window 0 */
833 addr = pci_base_offset(adapter, off);
834 netxen_nic_pci_change_crbwindow(adapter, 0);
837 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
838 pci_base(adapter, off), off, addr);
840 netxen_nic_pci_change_crbwindow(adapter, 1);
845 *(u8 *) data = readb(addr);
848 *(u16 *) data = readw(addr);
851 *(u32 *) data = readl(addr);
854 *(u64 *) data = readq(addr);
857 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
861 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
863 if (!ADDR_IN_WINDOW1(off))
864 netxen_nic_pci_change_crbwindow(adapter, 1);
869 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
870 { /* Only for window 1 */
873 addr = NETXEN_CRB_NORMALIZE(adapter, off);
874 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
875 pci_base(adapter, off), off, addr, val);
880 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
881 { /* Only for window 1 */
885 addr = NETXEN_CRB_NORMALIZE(adapter, off);
886 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
887 pci_base(adapter, off), off, addr);
894 /* Change the window to 0, write and change back to window 1. */
895 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
899 netxen_nic_pci_change_crbwindow(adapter, 0);
900 addr = pci_base_offset(adapter, index);
902 netxen_nic_pci_change_crbwindow(adapter, 1);
905 /* Change the window to 0, read and change back to window 1. */
906 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
910 addr = pci_base_offset(adapter, index);
912 netxen_nic_pci_change_crbwindow(adapter, 0);
913 *value = readl(addr);
914 netxen_nic_pci_change_crbwindow(adapter, 1);
917 int netxen_pci_set_window_warning_count = 0;
920 netxen_nic_pci_set_window(struct netxen_adapter *adapter,
921 unsigned long long addr)
923 static int ddr_mn_window = -1;
924 static int qdr_sn_window = -1;
927 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
928 /* DDR network side */
929 addr -= NETXEN_ADDR_DDR_NET;
930 window = (addr >> 25) & 0x3ff;
931 if (ddr_mn_window != window) {
932 ddr_mn_window = window;
933 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
936 /* MUST make sure window is set before we forge on... */
937 readl(PCI_OFFSET_SECOND_RANGE(adapter,
941 addr -= (window * NETXEN_WINDOW_ONE);
942 addr += NETXEN_PCI_DDR_NET;
943 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
944 addr -= NETXEN_ADDR_OCM0;
945 addr += NETXEN_PCI_OCM0;
946 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
947 addr -= NETXEN_ADDR_OCM1;
948 addr += NETXEN_PCI_OCM1;
951 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
952 /* QDR network side */
953 addr -= NETXEN_ADDR_QDR_NET;
954 window = (addr >> 22) & 0x3f;
955 if (qdr_sn_window != window) {
956 qdr_sn_window = window;
957 writel((window << 22),
958 PCI_OFFSET_SECOND_RANGE(adapter,
961 /* MUST make sure window is set before we forge on... */
962 readl(PCI_OFFSET_SECOND_RANGE(adapter,
966 addr -= (window * 0x400000);
967 addr += NETXEN_PCI_QDR_NET;
970 * peg gdb frequently accesses memory that doesn't exist,
971 * this limits the chit chat so debugging isn't slowed down.
973 if ((netxen_pci_set_window_warning_count++ < 8)
974 || (netxen_pci_set_window_warning_count % 64 == 0))
975 printk("%s: Warning:netxen_nic_pci_set_window()"
976 " Unknown address range!\n",
977 netxen_nic_driver_name);
984 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
986 if (netxen_rom_fast_write(adapter, PXE_START, 0) == -1) {
987 printk(KERN_ERR "%s: erase pxe failed\n",
988 netxen_nic_driver_name);
994 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
997 int addr = BRDCFG_START;
998 struct netxen_board_info *boardinfo;
1002 boardinfo = &adapter->ahw.boardcfg;
1003 ptr32 = (u32 *) boardinfo;
1005 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
1007 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1011 addr += sizeof(u32);
1013 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
1014 printk("%s: ERROR reading %s board config."
1015 " Read %x, expected %x\n", netxen_nic_driver_name,
1016 netxen_nic_driver_name,
1017 boardinfo->magic, NETXEN_BDINFO_MAGIC);
1020 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
1021 printk("%s: Unknown board config version."
1022 " Read %x, expected %x\n", netxen_nic_driver_name,
1023 boardinfo->header_version, NETXEN_BDINFO_VERSION);
1027 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
1028 switch ((netxen_brdtype_t) boardinfo->board_type) {
1029 case NETXEN_BRDTYPE_P2_SB35_4G:
1030 adapter->ahw.board_type = NETXEN_NIC_GBE;
1032 case NETXEN_BRDTYPE_P2_SB31_10G:
1033 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1034 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1035 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1036 adapter->ahw.board_type = NETXEN_NIC_XGBE;
1038 case NETXEN_BRDTYPE_P1_BD:
1039 case NETXEN_BRDTYPE_P1_SB:
1040 case NETXEN_BRDTYPE_P1_SMAX:
1041 case NETXEN_BRDTYPE_P1_SOCK:
1042 adapter->ahw.board_type = NETXEN_NIC_GBE;
1045 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
1046 boardinfo->board_type);
1053 /* NIU access sections */
1055 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1057 netxen_nic_write_w0(adapter,
1058 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->portnum),
1063 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1065 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
1066 if (adapter->portnum == 0)
1067 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
1069 else if (adapter->portnum == 1)
1070 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
1075 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1077 netxen_niu_gbe_init_port(adapter, adapter->portnum);
1081 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
1086 if (ADDR_IN_WINDOW1(off)) {
1087 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1089 netxen_nic_pci_change_crbwindow(adapter, 0);
1090 addr = pci_base_offset(adapter, off);
1092 netxen_nic_pci_change_crbwindow(adapter, 1);
1096 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1102 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
1103 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
1104 if (adapter->phy_read
1107 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1109 if (netxen_get_phy_link(status)) {
1110 switch (netxen_get_phy_speed(status)) {
1112 adapter->link_speed = SPEED_10;
1115 adapter->link_speed = SPEED_100;
1118 adapter->link_speed = SPEED_1000;
1121 adapter->link_speed = -1;
1124 switch (netxen_get_phy_duplex(status)) {
1126 adapter->link_duplex = DUPLEX_HALF;
1129 adapter->link_duplex = DUPLEX_FULL;
1132 adapter->link_duplex = -1;
1135 if (adapter->phy_read
1138 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1140 adapter->link_autoneg = autoneg;
1145 adapter->link_speed = -1;
1146 adapter->link_duplex = -1;
1151 void netxen_nic_flash_print(struct netxen_adapter *adapter)
1157 char brd_name[NETXEN_MAX_SHORT_NAME];
1158 struct netxen_new_user_info user_info;
1159 int i, addr = USER_START;
1162 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
1163 if (board_info->magic != NETXEN_BDINFO_MAGIC) {
1165 ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
1166 board_info->magic, NETXEN_BDINFO_MAGIC);
1169 if (board_info->header_version != NETXEN_BDINFO_VERSION) {
1170 printk("NetXen Unknown board config version."
1171 " Read %x, expected %x\n",
1172 board_info->header_version, NETXEN_BDINFO_VERSION);
1176 ptr32 = (u32 *) & user_info;
1178 i < sizeof(struct netxen_new_user_info) / sizeof(u32);
1180 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1181 printk("%s: ERROR reading %s board userarea.\n",
1182 netxen_nic_driver_name,
1183 netxen_nic_driver_name);
1186 *ptr32 = le32_to_cpu(*ptr32);
1188 addr += sizeof(u32);
1190 get_brd_name_by_type(board_info->board_type, brd_name);
1192 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1193 brd_name, user_info.serial_num, board_info->chip_id);
1195 printk("NetXen %s Board #%d, Chip id 0x%x\n",
1196 board_info->board_type == 0x0b ? "XGB" : "GBE",
1197 board_info->board_num, board_info->chip_id);
1198 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1199 NETXEN_FW_VERSION_MAJOR));
1200 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1201 NETXEN_FW_VERSION_MINOR));
1203 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1205 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
1208 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1209 printk(KERN_ERR "The mismatch in driver version and firmware "
1210 "version major number\n"
1211 "Driver version major number = %d \t"
1212 "Firmware version major number = %d \n",
1213 _NETXEN_NIC_LINUX_MAJOR, fw_major);
1214 adapter->driver_mismatch = 1;
1216 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1217 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
1218 printk(KERN_ERR "The mismatch in driver version and firmware "
1219 "version minor number\n"
1220 "Driver version minor number = %d \t"
1221 "Firmware version minor number = %d \n",
1222 _NETXEN_NIC_LINUX_MINOR, fw_minor);
1223 adapter->driver_mismatch = 1;
1225 if (adapter->driver_mismatch)
1226 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
1227 fw_major, fw_minor);