1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
136 #endif /* CONFIG_PCI_IOV */
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION);
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
147 struct ixgbe_hw *hw = &adapter->hw;
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
170 /* take a breather then clean up driver data */
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
180 struct ixgbe_reg_info {
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
213 /* List Terminator */
219 * ixgbe_regdump - register printout routine
221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
319 if (!netif_msg_hw(adapter))
322 /* Print netdevice Info */
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
367 /* Transmit Descriptor Formats
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
408 printk(KERN_CONT "\n");
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
419 /* Print RX Rings Summary */
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
430 if (!netif_msg_rx_status(adapter))
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
435 /* Advanced Receive Descriptor (Read) Format
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
444 * Advanced Receive Descriptor (Write-Back) Format
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
478 rx_buffer_info->skb);
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
510 printk(KERN_CONT "\n");
519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
604 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
605 struct ixgbe_tx_buffer
608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
610 dma_unmap_page(&adapter->pdev->dev,
612 tx_buffer_info->length,
615 dma_unmap_single(&adapter->pdev->dev,
617 tx_buffer_info->length,
619 tx_buffer_info->dma = 0;
621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
625 tx_buffer_info->time_stamp = 0;
626 /* tx_buffer_info must be completely set up in the transmit path */
630 * ixgbe_tx_xon_state - check the tx ring xon state
631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
637 * Returns : true if in xon state (currently not paused)
639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
640 struct ixgbe_ring *tx_ring)
642 u32 txoff = IXGBE_TFCS_TXOFF;
644 #ifdef CONFIG_IXGBE_DCB
645 if (adapter->dcb_cfg.pfc_mode_enable) {
647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
653 txoff = IXGBE_TFCS_TXOFF0;
655 case ixgbe_mac_82599EB:
657 txoff = IXGBE_TFCS_TXOFF;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
685 struct ixgbe_ring *tx_ring,
688 struct ixgbe_hw *hw = &adapter->hw;
690 /* Detect a transmit hang in hardware, this serializes the
691 * check with the clearing of time_stamp and movement of eop */
692 adapter->detect_tx_hung = false;
693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
695 ixgbe_tx_xon_state(adapter, tx_ring)) {
696 /* detected Tx unit hang */
697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
699 e_err(drv, "Detected Tx Unit Hang\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
718 #define IXGBE_MAX_TXD_PWR 14
719 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
721 /* Tx Descriptors needed, worst case */
722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
727 static void ixgbe_tx_timeout(struct net_device *netdev);
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
731 * @q_vector: structure containing interrupt and ring information
732 * @tx_ring: tx ring to clean
734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
735 struct ixgbe_ring *tx_ring)
737 struct ixgbe_adapter *adapter = q_vector->adapter;
738 struct net_device *netdev = adapter->netdev;
739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
742 unsigned int total_bytes = 0, total_packets = 0;
744 i = tx_ring->next_to_clean;
745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
749 (count < tx_ring->work_limit)) {
750 bool cleaned = false;
751 rmb(); /* read buffer_info after eop_desc */
752 for ( ; !cleaned; count++) {
754 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
756 cleaned = (i == eop);
757 skb = tx_buffer_info->skb;
759 if (cleaned && skb) {
760 unsigned int segs, bytecount;
761 unsigned int hlen = skb_headlen(skb);
763 /* gso_segs is currently only valid for tcp */
764 segs = skb_shinfo(skb)->gso_segs ?: 1;
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
776 #endif /* IXGBE_FCOE */
777 /* multiply data chunks by size of headers */
778 bytecount = ((segs - 1) * hlen) + skb->len;
779 total_packets += segs;
780 total_bytes += bytecount;
783 ixgbe_unmap_and_free_tx_resource(adapter,
786 tx_desc->wb.status = 0;
789 if (i == tx_ring->count)
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
797 tx_ring->next_to_clean = i;
799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
809 ++tx_ring->restart_queue;
813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
818 ixgbe_tx_timeout(adapter->netdev);
822 /* re-arm the interrupt */
823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
828 tx_ring->stats.packets += total_packets;
829 tx_ring->stats.bytes += total_bytes;
830 return (count < tx_ring->work_limit);
833 #ifdef CONFIG_IXGBE_DCA
834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
835 struct ixgbe_ring *rx_ring)
839 int q = rx_ring->reg_idx;
841 if (rx_ring->cpu != cpu) {
842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
863 struct ixgbe_ring *tx_ring)
867 int q = tx_ring->reg_idx;
868 struct ixgbe_hw *hw = &adapter->hw;
870 if (tx_ring->cpu != cpu) {
871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
900 for (i = 0; i < adapter->num_tx_queues; i++) {
901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
904 for (i = 0; i < adapter->num_rx_queues; i++) {
905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
910 static int __ixgbe_notify_dca(struct device *dev, void *data)
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
917 case DCA_PROVIDER_ADD:
918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
921 if (dca_add_requester(dev) == 0) {
922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
923 ixgbe_setup_dca(adapter);
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
939 #endif /* CONFIG_IXGBE_DCA */
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
949 struct sk_buff *skb, u8 status,
950 struct ixgbe_ring *ring,
951 union ixgbe_adv_rx_desc *rx_desc)
953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
958 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
959 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
960 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
962 napi_gro_receive(napi, skb);
964 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
965 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
978 union ixgbe_adv_rx_desc *rx_desc,
981 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
983 skb_checksum_none_assert(skb);
985 /* Rx csum disabled */
986 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
989 /* if IP and error */
990 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
991 (status_err & IXGBE_RXDADV_ERR_IPE)) {
992 adapter->hw_csum_rx_error++;
996 if (!(status_err & IXGBE_RXD_STAT_L4CS))
999 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1000 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1006 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1010 adapter->hw_csum_rx_error++;
1014 /* It must be a TCP or UDP packet with a valid checksum */
1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019 struct ixgbe_ring *rx_ring, u32 val)
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1028 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1035 void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1036 struct ixgbe_ring *rx_ring,
1039 struct net_device *netdev = adapter->netdev;
1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
1042 struct ixgbe_rx_buffer *bi;
1044 unsigned int bufsz = rx_ring->rx_buf_len;
1046 i = rx_ring->next_to_use;
1047 bi = &rx_ring->rx_buffer_info[i];
1049 while (cleaned_count--) {
1050 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1052 if (!bi->page_dma &&
1053 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1055 bi->page = netdev_alloc_page(netdev);
1057 adapter->alloc_rx_page_failed++;
1060 bi->page_offset = 0;
1062 /* use a half page if we're re-using */
1063 bi->page_offset ^= (PAGE_SIZE / 2);
1066 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1073 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1078 adapter->alloc_rx_buff_failed++;
1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb, rx_ring->queue_index);
1086 bi->dma = dma_map_single(&pdev->dev,
1088 rx_ring->rx_buf_len,
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098 rx_desc->read.hdr_addr = 0;
1102 if (i == rx_ring->count)
1104 bi = &rx_ring->rx_buffer_info[i];
1108 if (rx_ring->next_to_use != i) {
1109 rx_ring->next_to_use = i;
1111 i = (rx_ring->count - 1);
1113 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1117 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1119 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1122 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1124 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1127 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1129 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1130 IXGBE_RXDADV_RSCCNT_MASK) >>
1131 IXGBE_RXDADV_RSCCNT_SHIFT;
1135 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1136 * @skb: pointer to the last skb in the rsc queue
1137 * @count: pointer to number of packets coalesced in this context
1139 * This function changes a queue full of hw rsc buffers into a completed
1140 * packet. It uses the ->prev pointers to find the first packet and then
1141 * turns it into the frag list owner.
1143 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1146 unsigned int frag_list_size = 0;
1149 struct sk_buff *prev = skb->prev;
1150 frag_list_size += skb->len;
1156 skb_shinfo(skb)->frag_list = skb->next;
1158 skb->len += frag_list_size;
1159 skb->data_len += frag_list_size;
1160 skb->truesize += frag_list_size;
1164 struct ixgbe_rsc_cb {
1169 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1171 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1172 struct ixgbe_ring *rx_ring,
1173 int *work_done, int work_to_do)
1175 struct ixgbe_adapter *adapter = q_vector->adapter;
1176 struct net_device *netdev = adapter->netdev;
1177 struct pci_dev *pdev = adapter->pdev;
1178 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1179 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1180 struct sk_buff *skb;
1181 unsigned int i, rsc_count = 0;
1184 bool cleaned = false;
1185 int cleaned_count = 0;
1186 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1189 #endif /* IXGBE_FCOE */
1191 i = rx_ring->next_to_clean;
1192 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1193 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1194 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1196 while (staterr & IXGBE_RXD_STAT_DD) {
1198 if (*work_done >= work_to_do)
1202 rmb(); /* read descriptor and rx_buffer_info after status DD */
1203 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1204 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1205 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1206 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1207 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1208 if ((len > IXGBE_RX_HDR_SIZE) ||
1209 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1210 len = IXGBE_RX_HDR_SIZE;
1212 len = le16_to_cpu(rx_desc->wb.upper.length);
1216 skb = rx_buffer_info->skb;
1217 prefetch(skb->data);
1218 rx_buffer_info->skb = NULL;
1220 if (rx_buffer_info->dma) {
1221 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1222 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1225 * When HWRSC is enabled, delay unmapping
1226 * of the first packet. It carries the
1227 * header information, HW may still
1228 * access the header after the writeback.
1229 * Only unmap it when EOP is reached
1231 IXGBE_RSC_CB(skb)->delay_unmap = true;
1232 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1234 dma_unmap_single(&pdev->dev,
1235 rx_buffer_info->dma,
1236 rx_ring->rx_buf_len,
1239 rx_buffer_info->dma = 0;
1244 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1245 PAGE_SIZE / 2, DMA_FROM_DEVICE);
1246 rx_buffer_info->page_dma = 0;
1247 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1248 rx_buffer_info->page,
1249 rx_buffer_info->page_offset,
1252 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1253 (page_count(rx_buffer_info->page) != 1))
1254 rx_buffer_info->page = NULL;
1256 get_page(rx_buffer_info->page);
1258 skb->len += upper_len;
1259 skb->data_len += upper_len;
1260 skb->truesize += upper_len;
1264 if (i == rx_ring->count)
1267 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1271 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1272 rsc_count = ixgbe_get_rsc_count(rx_desc);
1275 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1276 IXGBE_RXDADV_NEXTP_SHIFT;
1277 next_buffer = &rx_ring->rx_buffer_info[nextp];
1279 next_buffer = &rx_ring->rx_buffer_info[i];
1282 if (staterr & IXGBE_RXD_STAT_EOP) {
1284 skb = ixgbe_transform_rsc_queue(skb,
1285 &(rx_ring->rsc_count));
1286 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1287 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1288 dma_unmap_single(&pdev->dev,
1289 IXGBE_RSC_CB(skb)->dma,
1290 rx_ring->rx_buf_len,
1292 IXGBE_RSC_CB(skb)->dma = 0;
1293 IXGBE_RSC_CB(skb)->delay_unmap = false;
1295 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1296 rx_ring->rsc_count +=
1297 skb_shinfo(skb)->nr_frags;
1299 rx_ring->rsc_count++;
1300 rx_ring->rsc_flush++;
1302 rx_ring->stats.packets++;
1303 rx_ring->stats.bytes += skb->len;
1305 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1306 rx_buffer_info->skb = next_buffer->skb;
1307 rx_buffer_info->dma = next_buffer->dma;
1308 next_buffer->skb = skb;
1309 next_buffer->dma = 0;
1311 skb->next = next_buffer->skb;
1312 skb->next->prev = skb;
1314 rx_ring->non_eop_descs++;
1318 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1319 dev_kfree_skb_irq(skb);
1323 ixgbe_rx_checksum(adapter, rx_desc, skb);
1325 /* probably a little skewed due to removing CRC */
1326 total_rx_bytes += skb->len;
1329 skb->protocol = eth_type_trans(skb, adapter->netdev);
1331 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1332 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1333 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1337 #endif /* IXGBE_FCOE */
1338 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1341 rx_desc->wb.upper.status_error = 0;
1343 /* return some buffers to hardware, one at a time is too slow */
1344 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1345 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1349 /* use prefetched values */
1351 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1353 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1356 rx_ring->next_to_clean = i;
1357 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1360 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1363 /* include DDPed FCoE data */
1364 if (ddp_bytes > 0) {
1367 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1368 sizeof(struct fc_frame_header) -
1369 sizeof(struct fcoe_crc_eof);
1372 total_rx_bytes += ddp_bytes;
1373 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1375 #endif /* IXGBE_FCOE */
1377 rx_ring->total_packets += total_rx_packets;
1378 rx_ring->total_bytes += total_rx_bytes;
1379 netdev->stats.rx_bytes += total_rx_bytes;
1380 netdev->stats.rx_packets += total_rx_packets;
1385 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1387 * ixgbe_configure_msix - Configure MSI-X hardware
1388 * @adapter: board private structure
1390 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1393 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1395 struct ixgbe_q_vector *q_vector;
1396 int i, j, q_vectors, v_idx, r_idx;
1399 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1402 * Populate the IVAR table and set the ITR values to the
1403 * corresponding register.
1405 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1406 q_vector = adapter->q_vector[v_idx];
1407 /* XXX for_each_set_bit(...) */
1408 r_idx = find_first_bit(q_vector->rxr_idx,
1409 adapter->num_rx_queues);
1411 for (i = 0; i < q_vector->rxr_count; i++) {
1412 j = adapter->rx_ring[r_idx]->reg_idx;
1413 ixgbe_set_ivar(adapter, 0, j, v_idx);
1414 r_idx = find_next_bit(q_vector->rxr_idx,
1415 adapter->num_rx_queues,
1418 r_idx = find_first_bit(q_vector->txr_idx,
1419 adapter->num_tx_queues);
1421 for (i = 0; i < q_vector->txr_count; i++) {
1422 j = adapter->tx_ring[r_idx]->reg_idx;
1423 ixgbe_set_ivar(adapter, 1, j, v_idx);
1424 r_idx = find_next_bit(q_vector->txr_idx,
1425 adapter->num_tx_queues,
1429 if (q_vector->txr_count && !q_vector->rxr_count)
1431 q_vector->eitr = adapter->tx_eitr_param;
1432 else if (q_vector->rxr_count)
1434 q_vector->eitr = adapter->rx_eitr_param;
1436 ixgbe_write_eitr(q_vector);
1439 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1440 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1442 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1443 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1446 /* set up to autoclear timer, and the vectors */
1447 mask = IXGBE_EIMS_ENABLE_MASK;
1448 if (adapter->num_vfs)
1449 mask &= ~(IXGBE_EIMS_OTHER |
1450 IXGBE_EIMS_MAILBOX |
1453 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1454 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1457 enum latency_range {
1461 latency_invalid = 255
1465 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1466 * @adapter: pointer to adapter
1467 * @eitr: eitr setting (ints per sec) to give last timeslice
1468 * @itr_setting: current throttle rate in ints/second
1469 * @packets: the number of packets during this measurement interval
1470 * @bytes: the number of bytes during this measurement interval
1472 * Stores a new ITR value based on packets and byte
1473 * counts during the last interrupt. The advantage of per interrupt
1474 * computation is faster updates and more accurate ITR for the current
1475 * traffic pattern. Constants in this function were computed
1476 * based on theoretical maximum wire speed and thresholds were set based
1477 * on testing data as well as attempting to minimize response time
1478 * while increasing bulk throughput.
1479 * this functionality is controlled by the InterruptThrottleRate module
1480 * parameter (see ixgbe_param.c)
1482 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1483 u32 eitr, u8 itr_setting,
1484 int packets, int bytes)
1486 unsigned int retval = itr_setting;
1491 goto update_itr_done;
1494 /* simple throttlerate management
1495 * 0-20MB/s lowest (100000 ints/s)
1496 * 20-100MB/s low (20000 ints/s)
1497 * 100-1249MB/s bulk (8000 ints/s)
1499 /* what was last interrupt timeslice? */
1500 timepassed_us = 1000000/eitr;
1501 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1503 switch (itr_setting) {
1504 case lowest_latency:
1505 if (bytes_perint > adapter->eitr_low)
1506 retval = low_latency;
1509 if (bytes_perint > adapter->eitr_high)
1510 retval = bulk_latency;
1511 else if (bytes_perint <= adapter->eitr_low)
1512 retval = lowest_latency;
1515 if (bytes_perint <= adapter->eitr_high)
1516 retval = low_latency;
1525 * ixgbe_write_eitr - write EITR register in hardware specific way
1526 * @q_vector: structure containing interrupt and ring information
1528 * This function is made to be called by ethtool and by the driver
1529 * when it needs to update EITR registers at runtime. Hardware
1530 * specific quirks/differences are taken care of here.
1532 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1534 struct ixgbe_adapter *adapter = q_vector->adapter;
1535 struct ixgbe_hw *hw = &adapter->hw;
1536 int v_idx = q_vector->v_idx;
1537 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1539 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1540 /* must write high and low 16 bits to reset counter */
1541 itr_reg |= (itr_reg << 16);
1542 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1544 * 82599 can support a value of zero, so allow it for
1545 * max interrupt rate, but there is an errata where it can
1546 * not be zero with RSC
1549 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1553 * set the WDIS bit to not clear the timer bits and cause an
1554 * immediate assertion of the interrupt
1556 itr_reg |= IXGBE_EITR_CNT_WDIS;
1558 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1561 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1563 struct ixgbe_adapter *adapter = q_vector->adapter;
1565 u8 current_itr, ret_itr;
1567 struct ixgbe_ring *rx_ring, *tx_ring;
1569 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1570 for (i = 0; i < q_vector->txr_count; i++) {
1571 tx_ring = adapter->tx_ring[r_idx];
1572 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1574 tx_ring->total_packets,
1575 tx_ring->total_bytes);
1576 /* if the result for this queue would decrease interrupt
1577 * rate for this vector then use that result */
1578 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1579 q_vector->tx_itr - 1 : ret_itr);
1580 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1584 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1585 for (i = 0; i < q_vector->rxr_count; i++) {
1586 rx_ring = adapter->rx_ring[r_idx];
1587 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1589 rx_ring->total_packets,
1590 rx_ring->total_bytes);
1591 /* if the result for this queue would decrease interrupt
1592 * rate for this vector then use that result */
1593 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1594 q_vector->rx_itr - 1 : ret_itr);
1595 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1599 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1601 switch (current_itr) {
1602 /* counts and packets in update_itr are dependent on these numbers */
1603 case lowest_latency:
1607 new_itr = 20000; /* aka hwitr = ~200 */
1615 if (new_itr != q_vector->eitr) {
1616 /* do an exponential smoothing */
1617 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1619 /* save the algorithm value here, not the smoothed one */
1620 q_vector->eitr = new_itr;
1622 ixgbe_write_eitr(q_vector);
1627 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1628 * @work: pointer to work_struct containing our data
1630 static void ixgbe_check_overtemp_task(struct work_struct *work)
1632 struct ixgbe_adapter *adapter = container_of(work,
1633 struct ixgbe_adapter,
1634 check_overtemp_task);
1635 struct ixgbe_hw *hw = &adapter->hw;
1636 u32 eicr = adapter->interrupt_event;
1638 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1639 switch (hw->device_id) {
1640 case IXGBE_DEV_ID_82599_T3_LOM: {
1642 bool link_up = false;
1644 if (hw->mac.ops.check_link)
1645 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1647 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1648 (eicr & IXGBE_EICR_LSC))
1649 /* Check if this is due to overtemp */
1650 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1655 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1659 e_crit(drv, "Network adapter has been stopped because it has "
1660 "over heated. Restart the computer. If the problem "
1661 "persists, power off the system and replace the "
1663 /* write to clear the interrupt */
1664 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1668 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1670 struct ixgbe_hw *hw = &adapter->hw;
1672 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1673 (eicr & IXGBE_EICR_GPI_SDP1)) {
1674 e_crit(probe, "Fan has stopped, replace the adapter\n");
1675 /* write to clear the interrupt */
1676 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1680 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1682 struct ixgbe_hw *hw = &adapter->hw;
1684 if (eicr & IXGBE_EICR_GPI_SDP1) {
1685 /* Clear the interrupt */
1686 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1687 schedule_work(&adapter->multispeed_fiber_task);
1688 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1689 /* Clear the interrupt */
1690 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1691 schedule_work(&adapter->sfp_config_module_task);
1693 /* Interrupt isn't for us... */
1698 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1700 struct ixgbe_hw *hw = &adapter->hw;
1703 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1704 adapter->link_check_timeout = jiffies;
1705 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1706 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1707 IXGBE_WRITE_FLUSH(hw);
1708 schedule_work(&adapter->watchdog_task);
1712 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1714 struct net_device *netdev = data;
1715 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1716 struct ixgbe_hw *hw = &adapter->hw;
1720 * Workaround for Silicon errata. Use clear-by-write instead
1721 * of clear-by-read. Reading with EICS will return the
1722 * interrupt causes without clearing, which later be done
1723 * with the write to EICR.
1725 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1726 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1728 if (eicr & IXGBE_EICR_LSC)
1729 ixgbe_check_lsc(adapter);
1731 if (eicr & IXGBE_EICR_MAILBOX)
1732 ixgbe_msg_task(adapter);
1734 if (hw->mac.type == ixgbe_mac_82598EB)
1735 ixgbe_check_fan_failure(adapter, eicr);
1737 if (hw->mac.type == ixgbe_mac_82599EB) {
1738 ixgbe_check_sfp_event(adapter, eicr);
1739 adapter->interrupt_event = eicr;
1740 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1741 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1742 schedule_work(&adapter->check_overtemp_task);
1744 /* Handle Flow Director Full threshold interrupt */
1745 if (eicr & IXGBE_EICR_FLOW_DIR) {
1747 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1748 /* Disable transmits before FDIR Re-initialization */
1749 netif_tx_stop_all_queues(netdev);
1750 for (i = 0; i < adapter->num_tx_queues; i++) {
1751 struct ixgbe_ring *tx_ring =
1752 adapter->tx_ring[i];
1753 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1754 &tx_ring->reinit_state))
1755 schedule_work(&adapter->fdir_reinit_task);
1759 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1760 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1765 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1770 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1771 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1774 mask = (qmask & 0xFFFFFFFF);
1775 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1776 mask = (qmask >> 32);
1777 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1779 /* skip the flush */
1782 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1787 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1788 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1791 mask = (qmask & 0xFFFFFFFF);
1792 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1793 mask = (qmask >> 32);
1794 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1796 /* skip the flush */
1799 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1801 struct ixgbe_q_vector *q_vector = data;
1802 struct ixgbe_adapter *adapter = q_vector->adapter;
1803 struct ixgbe_ring *tx_ring;
1806 if (!q_vector->txr_count)
1809 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1810 for (i = 0; i < q_vector->txr_count; i++) {
1811 tx_ring = adapter->tx_ring[r_idx];
1812 tx_ring->total_bytes = 0;
1813 tx_ring->total_packets = 0;
1814 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1818 /* EIAM disabled interrupts (on this vector) for us */
1819 napi_schedule(&q_vector->napi);
1825 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1827 * @data: pointer to our q_vector struct for this interrupt vector
1829 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1831 struct ixgbe_q_vector *q_vector = data;
1832 struct ixgbe_adapter *adapter = q_vector->adapter;
1833 struct ixgbe_ring *rx_ring;
1837 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1838 for (i = 0; i < q_vector->rxr_count; i++) {
1839 rx_ring = adapter->rx_ring[r_idx];
1840 rx_ring->total_bytes = 0;
1841 rx_ring->total_packets = 0;
1842 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1846 if (!q_vector->rxr_count)
1849 /* disable interrupts on this vector only */
1850 /* EIAM disabled interrupts (on this vector) for us */
1851 napi_schedule(&q_vector->napi);
1856 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1858 struct ixgbe_q_vector *q_vector = data;
1859 struct ixgbe_adapter *adapter = q_vector->adapter;
1860 struct ixgbe_ring *ring;
1864 if (!q_vector->txr_count && !q_vector->rxr_count)
1867 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1868 for (i = 0; i < q_vector->txr_count; i++) {
1869 ring = adapter->tx_ring[r_idx];
1870 ring->total_bytes = 0;
1871 ring->total_packets = 0;
1872 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1876 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1877 for (i = 0; i < q_vector->rxr_count; i++) {
1878 ring = adapter->rx_ring[r_idx];
1879 ring->total_bytes = 0;
1880 ring->total_packets = 0;
1881 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1885 /* EIAM disabled interrupts (on this vector) for us */
1886 napi_schedule(&q_vector->napi);
1892 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1893 * @napi: napi struct with our devices info in it
1894 * @budget: amount of work driver is allowed to do this pass, in packets
1896 * This function is optimized for cleaning one queue only on a single
1899 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1901 struct ixgbe_q_vector *q_vector =
1902 container_of(napi, struct ixgbe_q_vector, napi);
1903 struct ixgbe_adapter *adapter = q_vector->adapter;
1904 struct ixgbe_ring *rx_ring = NULL;
1908 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1909 rx_ring = adapter->rx_ring[r_idx];
1910 #ifdef CONFIG_IXGBE_DCA
1911 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1912 ixgbe_update_rx_dca(adapter, rx_ring);
1915 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1917 /* If all Rx work done, exit the polling mode */
1918 if (work_done < budget) {
1919 napi_complete(napi);
1920 if (adapter->rx_itr_setting & 1)
1921 ixgbe_set_itr_msix(q_vector);
1922 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1923 ixgbe_irq_enable_queues(adapter,
1924 ((u64)1 << q_vector->v_idx));
1931 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1932 * @napi: napi struct with our devices info in it
1933 * @budget: amount of work driver is allowed to do this pass, in packets
1935 * This function will clean more than one rx queue associated with a
1938 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1940 struct ixgbe_q_vector *q_vector =
1941 container_of(napi, struct ixgbe_q_vector, napi);
1942 struct ixgbe_adapter *adapter = q_vector->adapter;
1943 struct ixgbe_ring *ring = NULL;
1944 int work_done = 0, i;
1946 bool tx_clean_complete = true;
1948 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1949 for (i = 0; i < q_vector->txr_count; i++) {
1950 ring = adapter->tx_ring[r_idx];
1951 #ifdef CONFIG_IXGBE_DCA
1952 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1953 ixgbe_update_tx_dca(adapter, ring);
1955 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1956 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1960 /* attempt to distribute budget to each queue fairly, but don't allow
1961 * the budget to go below 1 because we'll exit polling */
1962 budget /= (q_vector->rxr_count ?: 1);
1963 budget = max(budget, 1);
1964 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1965 for (i = 0; i < q_vector->rxr_count; i++) {
1966 ring = adapter->rx_ring[r_idx];
1967 #ifdef CONFIG_IXGBE_DCA
1968 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1969 ixgbe_update_rx_dca(adapter, ring);
1971 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1972 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1976 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1977 ring = adapter->rx_ring[r_idx];
1978 /* If all Rx work done, exit the polling mode */
1979 if (work_done < budget) {
1980 napi_complete(napi);
1981 if (adapter->rx_itr_setting & 1)
1982 ixgbe_set_itr_msix(q_vector);
1983 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1984 ixgbe_irq_enable_queues(adapter,
1985 ((u64)1 << q_vector->v_idx));
1993 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1994 * @napi: napi struct with our devices info in it
1995 * @budget: amount of work driver is allowed to do this pass, in packets
1997 * This function is optimized for cleaning one queue only on a single
2000 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2002 struct ixgbe_q_vector *q_vector =
2003 container_of(napi, struct ixgbe_q_vector, napi);
2004 struct ixgbe_adapter *adapter = q_vector->adapter;
2005 struct ixgbe_ring *tx_ring = NULL;
2009 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2010 tx_ring = adapter->tx_ring[r_idx];
2011 #ifdef CONFIG_IXGBE_DCA
2012 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2013 ixgbe_update_tx_dca(adapter, tx_ring);
2016 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2019 /* If all Tx work done, exit the polling mode */
2020 if (work_done < budget) {
2021 napi_complete(napi);
2022 if (adapter->tx_itr_setting & 1)
2023 ixgbe_set_itr_msix(q_vector);
2024 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2025 ixgbe_irq_enable_queues(adapter,
2026 ((u64)1 << q_vector->v_idx));
2032 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2035 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2037 set_bit(r_idx, q_vector->rxr_idx);
2038 q_vector->rxr_count++;
2041 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2044 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2046 set_bit(t_idx, q_vector->txr_idx);
2047 q_vector->txr_count++;
2051 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2052 * @adapter: board private structure to initialize
2053 * @vectors: allotted vector count for descriptor rings
2055 * This function maps descriptor rings to the queue-specific vectors
2056 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2057 * one vector per ring/queue, but on a constrained vector budget, we
2058 * group the rings as "efficiently" as possible. You would add new
2059 * mapping configurations in here.
2061 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2065 int rxr_idx = 0, txr_idx = 0;
2066 int rxr_remaining = adapter->num_rx_queues;
2067 int txr_remaining = adapter->num_tx_queues;
2072 /* No mapping required if MSI-X is disabled. */
2073 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2077 * The ideal configuration...
2078 * We have enough vectors to map one per queue.
2080 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2081 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2082 map_vector_to_rxq(adapter, v_start, rxr_idx);
2084 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2085 map_vector_to_txq(adapter, v_start, txr_idx);
2091 * If we don't have enough vectors for a 1-to-1
2092 * mapping, we'll have to group them so there are
2093 * multiple queues per vector.
2095 /* Re-adjusting *qpv takes care of the remainder. */
2096 for (i = v_start; i < vectors; i++) {
2097 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2098 for (j = 0; j < rqpv; j++) {
2099 map_vector_to_rxq(adapter, i, rxr_idx);
2104 for (i = v_start; i < vectors; i++) {
2105 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2106 for (j = 0; j < tqpv; j++) {
2107 map_vector_to_txq(adapter, i, txr_idx);
2118 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2119 * @adapter: board private structure
2121 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2122 * interrupts from the kernel.
2124 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2126 struct net_device *netdev = adapter->netdev;
2127 irqreturn_t (*handler)(int, void *);
2128 int i, vector, q_vectors, err;
2131 /* Decrement for Other and TCP Timer vectors */
2132 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2134 /* Map the Tx/Rx rings to the vectors we were allotted. */
2135 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2139 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2140 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2141 &ixgbe_msix_clean_many)
2142 for (vector = 0; vector < q_vectors; vector++) {
2143 handler = SET_HANDLER(adapter->q_vector[vector]);
2145 if (handler == &ixgbe_msix_clean_rx) {
2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "rx", ri++);
2148 } else if (handler == &ixgbe_msix_clean_tx) {
2149 sprintf(adapter->name[vector], "%s-%s-%d",
2150 netdev->name, "tx", ti++);
2152 sprintf(adapter->name[vector], "%s-%s-%d",
2153 netdev->name, "TxRx", vector);
2155 err = request_irq(adapter->msix_entries[vector].vector,
2156 handler, 0, adapter->name[vector],
2157 adapter->q_vector[vector]);
2159 e_err(probe, "request_irq failed for MSIX interrupt "
2160 "Error: %d\n", err);
2161 goto free_queue_irqs;
2165 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2166 err = request_irq(adapter->msix_entries[vector].vector,
2167 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2169 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2170 goto free_queue_irqs;
2176 for (i = vector - 1; i >= 0; i--)
2177 free_irq(adapter->msix_entries[--vector].vector,
2178 adapter->q_vector[i]);
2179 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2180 pci_disable_msix(adapter->pdev);
2181 kfree(adapter->msix_entries);
2182 adapter->msix_entries = NULL;
2187 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2189 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2191 u32 new_itr = q_vector->eitr;
2192 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2193 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2195 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2197 tx_ring->total_packets,
2198 tx_ring->total_bytes);
2199 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2201 rx_ring->total_packets,
2202 rx_ring->total_bytes);
2204 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2206 switch (current_itr) {
2207 /* counts and packets in update_itr are dependent on these numbers */
2208 case lowest_latency:
2212 new_itr = 20000; /* aka hwitr = ~200 */
2221 if (new_itr != q_vector->eitr) {
2222 /* do an exponential smoothing */
2223 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2225 /* save the algorithm value here, not the smoothed one */
2226 q_vector->eitr = new_itr;
2228 ixgbe_write_eitr(q_vector);
2233 * ixgbe_irq_enable - Enable default interrupt generation settings
2234 * @adapter: board private structure
2236 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2240 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2241 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP0;
2243 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2244 mask |= IXGBE_EIMS_GPI_SDP1;
2245 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2246 mask |= IXGBE_EIMS_ECC;
2247 mask |= IXGBE_EIMS_GPI_SDP1;
2248 mask |= IXGBE_EIMS_GPI_SDP2;
2249 if (adapter->num_vfs)
2250 mask |= IXGBE_EIMS_MAILBOX;
2252 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2253 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2254 mask |= IXGBE_EIMS_FLOW_DIR;
2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2257 ixgbe_irq_enable_queues(adapter, ~0);
2258 IXGBE_WRITE_FLUSH(&adapter->hw);
2260 if (adapter->num_vfs > 32) {
2261 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2262 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2267 * ixgbe_intr - legacy mode Interrupt Handler
2268 * @irq: interrupt number
2269 * @data: pointer to a network interface device structure
2271 static irqreturn_t ixgbe_intr(int irq, void *data)
2273 struct net_device *netdev = data;
2274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2275 struct ixgbe_hw *hw = &adapter->hw;
2276 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2280 * Workaround for silicon errata. Mask the interrupts
2281 * before the read of EICR.
2283 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2285 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2286 * therefore no explict interrupt disable is necessary */
2287 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2289 /* shared interrupt alert!
2290 * make sure interrupts are enabled because the read will
2291 * have disabled interrupts due to EIAM */
2292 ixgbe_irq_enable(adapter);
2293 return IRQ_NONE; /* Not our interrupt */
2296 if (eicr & IXGBE_EICR_LSC)
2297 ixgbe_check_lsc(adapter);
2299 if (hw->mac.type == ixgbe_mac_82599EB)
2300 ixgbe_check_sfp_event(adapter, eicr);
2302 ixgbe_check_fan_failure(adapter, eicr);
2303 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2304 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2305 schedule_work(&adapter->check_overtemp_task);
2307 if (napi_schedule_prep(&(q_vector->napi))) {
2308 adapter->tx_ring[0]->total_packets = 0;
2309 adapter->tx_ring[0]->total_bytes = 0;
2310 adapter->rx_ring[0]->total_packets = 0;
2311 adapter->rx_ring[0]->total_bytes = 0;
2312 /* would disable interrupts here but EIAM disabled it */
2313 __napi_schedule(&(q_vector->napi));
2319 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2321 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2323 for (i = 0; i < q_vectors; i++) {
2324 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2325 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2326 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2327 q_vector->rxr_count = 0;
2328 q_vector->txr_count = 0;
2333 * ixgbe_request_irq - initialize interrupts
2334 * @adapter: board private structure
2336 * Attempts to configure interrupts using the best available
2337 * capabilities of the hardware and kernel.
2339 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2341 struct net_device *netdev = adapter->netdev;
2344 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2345 err = ixgbe_request_msix_irqs(adapter);
2346 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2347 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2348 netdev->name, netdev);
2350 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2351 netdev->name, netdev);
2355 e_err(probe, "request_irq failed, Error %d\n", err);
2360 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2362 struct net_device *netdev = adapter->netdev;
2364 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2367 q_vectors = adapter->num_msix_vectors;
2370 free_irq(adapter->msix_entries[i].vector, netdev);
2373 for (; i >= 0; i--) {
2374 free_irq(adapter->msix_entries[i].vector,
2375 adapter->q_vector[i]);
2378 ixgbe_reset_q_vectors(adapter);
2380 free_irq(adapter->pdev->irq, netdev);
2385 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2386 * @adapter: board private structure
2388 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2390 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2396 if (adapter->num_vfs > 32)
2397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2399 IXGBE_WRITE_FLUSH(&adapter->hw);
2400 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2402 for (i = 0; i < adapter->num_msix_vectors; i++)
2403 synchronize_irq(adapter->msix_entries[i].vector);
2405 synchronize_irq(adapter->pdev->irq);
2410 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2413 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2415 struct ixgbe_hw *hw = &adapter->hw;
2417 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2418 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2420 ixgbe_set_ivar(adapter, 0, 0, 0);
2421 ixgbe_set_ivar(adapter, 1, 0, 0);
2423 map_vector_to_rxq(adapter, 0, 0);
2424 map_vector_to_txq(adapter, 0, 0);
2426 e_info(hw, "Legacy interrupt IVAR setup done\n");
2430 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2431 * @adapter: board private structure
2432 * @ring: structure containing ring specific data
2434 * Configure the Tx descriptor ring after a reset.
2436 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2437 struct ixgbe_ring *ring)
2439 struct ixgbe_hw *hw = &adapter->hw;
2440 u64 tdba = ring->dma;
2443 u16 reg_idx = ring->reg_idx;
2445 /* disable queue to avoid issues while updating state */
2446 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2447 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2448 txdctl & ~IXGBE_TXDCTL_ENABLE);
2449 IXGBE_WRITE_FLUSH(hw);
2451 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2452 (tdba & DMA_BIT_MASK(32)));
2453 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2454 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2455 ring->count * sizeof(union ixgbe_adv_tx_desc));
2456 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2457 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2458 ring->head = IXGBE_TDH(reg_idx);
2459 ring->tail = IXGBE_TDT(reg_idx);
2461 /* configure fetching thresholds */
2462 if (adapter->rx_itr_setting == 0) {
2463 /* cannot set wthresh when itr==0 */
2464 txdctl &= ~0x007F0000;
2466 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2467 txdctl |= (8 << 16);
2469 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2470 /* PThresh workaround for Tx hang with DFP enabled. */
2474 /* reinitialize flowdirector state */
2475 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2478 txdctl |= IXGBE_TXDCTL_ENABLE;
2479 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2481 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2482 if (hw->mac.type == ixgbe_mac_82598EB &&
2483 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2486 /* poll to verify queue is enabled */
2489 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2490 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2492 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2495 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2497 struct ixgbe_hw *hw = &adapter->hw;
2501 if (hw->mac.type == ixgbe_mac_82598EB)
2504 /* disable the arbiter while setting MTQC */
2505 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2506 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2507 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2509 /* set transmit pool layout */
2510 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2511 switch (adapter->flags & mask) {
2513 case (IXGBE_FLAG_SRIOV_ENABLED):
2514 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2515 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2518 case (IXGBE_FLAG_DCB_ENABLED):
2519 /* We enable 8 traffic classes, DCB only */
2520 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2521 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2525 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2529 /* re-enable the arbiter */
2530 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2531 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2535 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2536 * @adapter: board private structure
2538 * Configure the Tx unit of the MAC after a reset.
2540 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2542 struct ixgbe_hw *hw = &adapter->hw;
2546 ixgbe_setup_mtqc(adapter);
2548 if (hw->mac.type != ixgbe_mac_82598EB) {
2549 /* DMATXCTL.EN must be before Tx queues are enabled */
2550 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2551 dmatxctl |= IXGBE_DMATXCTL_TE;
2552 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2555 /* Setup the HW Tx Head and Tail descriptor pointers */
2556 for (i = 0; i < adapter->num_tx_queues; i++)
2557 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2560 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2562 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2563 struct ixgbe_ring *rx_ring)
2567 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2569 index = rx_ring->reg_idx;
2570 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2572 mask = (unsigned long) feature[RING_F_RSS].mask;
2573 index = index & mask;
2575 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2577 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2578 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2579 if (adapter->num_vfs)
2580 srrctl |= IXGBE_SRRCTL_DROP_EN;
2582 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2583 IXGBE_SRRCTL_BSIZEHDR_MASK;
2585 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2586 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2587 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2589 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2591 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2593 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2594 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2595 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2601 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2603 struct ixgbe_hw *hw = &adapter->hw;
2604 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2605 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2606 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2607 u32 mrqc = 0, reta = 0;
2612 /* Fill out hash function seeds */
2613 for (i = 0; i < 10; i++)
2614 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2616 /* Fill out redirection table */
2617 for (i = 0, j = 0; i < 128; i++, j++) {
2618 if (j == adapter->ring_feature[RING_F_RSS].indices)
2620 /* reta = 4-byte sliding window of
2621 * 0x00..(indices-1)(indices-1)00..etc. */
2622 reta = (reta << 8) | (j * 0x11);
2624 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2627 /* Disable indicating checksum in descriptor, enables RSS hash */
2628 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2629 rxcsum |= IXGBE_RXCSUM_PCSD;
2630 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2632 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2633 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2635 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2636 #ifdef CONFIG_IXGBE_DCB
2637 | IXGBE_FLAG_DCB_ENABLED
2639 | IXGBE_FLAG_SRIOV_ENABLED
2643 case (IXGBE_FLAG_RSS_ENABLED):
2644 mrqc = IXGBE_MRQC_RSSEN;
2646 case (IXGBE_FLAG_SRIOV_ENABLED):
2647 mrqc = IXGBE_MRQC_VMDQEN;
2649 #ifdef CONFIG_IXGBE_DCB
2650 case (IXGBE_FLAG_DCB_ENABLED):
2651 mrqc = IXGBE_MRQC_RT8TCEN;
2653 #endif /* CONFIG_IXGBE_DCB */
2658 /* Perform hash on these packet types */
2659 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2660 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2661 | IXGBE_MRQC_RSS_FIELD_IPV6
2662 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2664 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2668 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2669 * @adapter: address of board private structure
2670 * @index: index of ring to set
2672 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2673 struct ixgbe_ring *ring)
2675 struct ixgbe_hw *hw = &adapter->hw;
2678 u16 reg_idx = ring->reg_idx;
2680 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2683 rx_buf_len = ring->rx_buf_len;
2684 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2685 rscctrl |= IXGBE_RSCCTL_RSCEN;
2687 * we must limit the number of descriptors so that the
2688 * total size of max desc * buf_len is not greater
2691 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2692 #if (MAX_SKB_FRAGS > 16)
2693 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2694 #elif (MAX_SKB_FRAGS > 8)
2695 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2696 #elif (MAX_SKB_FRAGS > 4)
2697 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2699 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2702 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2703 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2704 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2705 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2707 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2709 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2713 * ixgbe_set_uta - Set unicast filter table address
2714 * @adapter: board private structure
2716 * The unicast table address is a register array of 32-bit registers.
2717 * The table is meant to be used in a way similar to how the MTA is used
2718 * however due to certain limitations in the hardware it is necessary to
2719 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2720 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2722 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2724 struct ixgbe_hw *hw = &adapter->hw;
2727 /* The UTA table only exists on 82599 hardware and newer */
2728 if (hw->mac.type < ixgbe_mac_82599EB)
2731 /* we only need to do this if VMDq is enabled */
2732 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2735 for (i = 0; i < 128; i++)
2736 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2739 #define IXGBE_MAX_RX_DESC_POLL 10
2740 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2741 struct ixgbe_ring *ring)
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 int reg_idx = ring->reg_idx;
2745 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2748 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2749 if (hw->mac.type == ixgbe_mac_82598EB &&
2750 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2755 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2756 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2759 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2760 "the polling period\n", reg_idx);
2764 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2765 struct ixgbe_ring *ring)
2767 struct ixgbe_hw *hw = &adapter->hw;
2768 u64 rdba = ring->dma;
2770 u16 reg_idx = ring->reg_idx;
2772 /* disable queue to avoid issues while updating state */
2773 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2774 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2775 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2776 IXGBE_WRITE_FLUSH(hw);
2778 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2779 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2780 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2781 ring->count * sizeof(union ixgbe_adv_rx_desc));
2782 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2783 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2784 ring->head = IXGBE_RDH(reg_idx);
2785 ring->tail = IXGBE_RDT(reg_idx);
2787 ixgbe_configure_srrctl(adapter, ring);
2788 ixgbe_configure_rscctl(adapter, ring);
2790 if (hw->mac.type == ixgbe_mac_82598EB) {
2792 * enable cache line friendly hardware writes:
2793 * PTHRESH=32 descriptors (half the internal cache),
2794 * this also removes ugly rx_no_buffer_count increment
2795 * HTHRESH=4 descriptors (to minimize latency on fetch)
2796 * WTHRESH=8 burst writeback up to two cache lines
2798 rxdctl &= ~0x3FFFFF;
2802 /* enable receive descriptor ring */
2803 rxdctl |= IXGBE_RXDCTL_ENABLE;
2804 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2806 ixgbe_rx_desc_queue_enable(adapter, ring);
2807 ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
2810 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2812 struct ixgbe_hw *hw = &adapter->hw;
2815 /* PSRTYPE must be initialized in non 82598 adapters */
2816 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2817 IXGBE_PSRTYPE_UDPHDR |
2818 IXGBE_PSRTYPE_IPV4HDR |
2819 IXGBE_PSRTYPE_L2HDR |
2820 IXGBE_PSRTYPE_IPV6HDR;
2822 if (hw->mac.type == ixgbe_mac_82598EB)
2825 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2826 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2828 for (p = 0; p < adapter->num_rx_pools; p++)
2829 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2833 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2835 struct ixgbe_hw *hw = &adapter->hw;
2838 u32 reg_offset, vf_shift;
2841 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2844 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2845 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2846 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2847 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2849 vf_shift = adapter->num_vfs % 32;
2850 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2852 /* Enable only the PF's pool for Tx/Rx */
2853 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2854 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2855 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2856 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2857 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2859 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2860 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2863 * Set up VF register offsets for selected VT Mode,
2864 * i.e. 32 or 64 VFs for SR-IOV
2866 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2867 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2868 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2869 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2871 /* enable Tx loopback for VF/PF communication */
2872 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2875 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2877 struct ixgbe_hw *hw = &adapter->hw;
2878 struct net_device *netdev = adapter->netdev;
2879 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2881 struct ixgbe_ring *rx_ring;
2885 /* Decide whether to use packet split mode or not */
2886 /* Do not use packet split if we're in SR-IOV Mode */
2887 if (!adapter->num_vfs)
2888 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2890 /* Set the RX buffer length according to the mode */
2891 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2892 rx_buf_len = IXGBE_RX_HDR_SIZE;
2894 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2895 (netdev->mtu <= ETH_DATA_LEN))
2896 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2898 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2902 /* adjust max frame to be able to do baby jumbo for FCoE */
2903 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2904 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2905 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2907 #endif /* IXGBE_FCOE */
2908 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2909 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2910 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2911 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2913 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2916 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2917 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2918 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2919 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2922 * Setup the HW Rx Head and Tail Descriptor Pointers and
2923 * the Base and Length of the Rx Descriptor Ring
2925 for (i = 0; i < adapter->num_rx_queues; i++) {
2926 rx_ring = adapter->rx_ring[i];
2927 rx_ring->rx_buf_len = rx_buf_len;
2929 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2930 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2932 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2935 if (netdev->features & NETIF_F_FCOE_MTU) {
2936 struct ixgbe_ring_feature *f;
2937 f = &adapter->ring_feature[RING_F_FCOE];
2938 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2939 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2940 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2941 rx_ring->rx_buf_len =
2942 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2945 #endif /* IXGBE_FCOE */
2950 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2952 struct ixgbe_hw *hw = &adapter->hw;
2953 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2955 switch (hw->mac.type) {
2956 case ixgbe_mac_82598EB:
2958 * For VMDq support of different descriptor types or
2959 * buffer sizes through the use of multiple SRRCTL
2960 * registers, RDRXCTL.MVMEN must be set to 1
2962 * also, the manual doesn't mention it clearly but DCA hints
2963 * will only use queue 0's tags unless this bit is set. Side
2964 * effects of setting this bit are only that SRRCTL must be
2965 * fully programmed [0..15]
2967 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2969 case ixgbe_mac_82599EB:
2970 /* Disable RSC for ACK packets */
2971 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2972 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2973 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2974 /* hardware requires some bits to be set by default */
2975 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2976 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2979 /* We should do nothing since we don't know this hardware */
2983 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2987 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2988 * @adapter: board private structure
2990 * Configure the Rx unit of the MAC after a reset.
2992 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2994 struct ixgbe_hw *hw = &adapter->hw;
2998 /* disable receives while setting up the descriptors */
2999 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3000 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3002 ixgbe_setup_psrtype(adapter);
3003 ixgbe_setup_rdrxctl(adapter);
3005 /* Program registers for the distribution of queues */
3006 ixgbe_setup_mrqc(adapter);
3008 ixgbe_set_uta(adapter);
3010 /* set_rx_buffer_len must be called before ring initialization */
3011 ixgbe_set_rx_buffer_len(adapter);
3014 * Setup the HW Rx Head and Tail Descriptor Pointers and
3015 * the Base and Length of the Rx Descriptor Ring
3017 for (i = 0; i < adapter->num_rx_queues; i++)
3018 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3020 /* disable drop enable for 82598 parts */
3021 if (hw->mac.type == ixgbe_mac_82598EB)
3022 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3024 /* enable all receives */
3025 rxctrl |= IXGBE_RXCTRL_RXEN;
3026 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3029 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3031 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3032 struct ixgbe_hw *hw = &adapter->hw;
3033 int pool_ndx = adapter->num_vfs;
3035 /* add VID to filter table */
3036 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3039 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3042 struct ixgbe_hw *hw = &adapter->hw;
3043 int pool_ndx = adapter->num_vfs;
3045 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3046 ixgbe_irq_disable(adapter);
3048 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3050 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3051 ixgbe_irq_enable(adapter);
3053 /* remove VID from filter table */
3054 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3058 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3059 * @adapter: driver data
3061 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3063 struct ixgbe_hw *hw = &adapter->hw;
3064 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3067 switch (hw->mac.type) {
3068 case ixgbe_mac_82598EB:
3069 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
3070 #ifdef CONFIG_IXGBE_DCB
3071 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3072 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3074 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3075 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3077 case ixgbe_mac_82599EB:
3078 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
3079 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3080 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3081 #ifdef CONFIG_IXGBE_DCB
3082 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
3085 for (i = 0; i < adapter->num_rx_queues; i++) {
3086 j = adapter->rx_ring[i]->reg_idx;
3087 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3088 vlnctrl &= ~IXGBE_RXDCTL_VME;
3089 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3098 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3099 * @adapter: driver data
3101 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3103 struct ixgbe_hw *hw = &adapter->hw;
3104 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3107 switch (hw->mac.type) {
3108 case ixgbe_mac_82598EB:
3109 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
3110 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3111 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3113 case ixgbe_mac_82599EB:
3114 vlnctrl |= IXGBE_VLNCTRL_VFE;
3115 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3117 for (i = 0; i < adapter->num_rx_queues; i++) {
3118 j = adapter->rx_ring[i]->reg_idx;
3119 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3120 vlnctrl |= IXGBE_RXDCTL_VME;
3121 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3129 static void ixgbe_vlan_rx_register(struct net_device *netdev,
3130 struct vlan_group *grp)
3132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3134 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3135 ixgbe_irq_disable(adapter);
3136 adapter->vlgrp = grp;
3139 * For a DCB driver, always enable VLAN tag stripping so we can
3140 * still receive traffic from a DCB-enabled host even if we're
3143 ixgbe_vlan_filter_enable(adapter);
3145 ixgbe_vlan_rx_add_vid(netdev, 0);
3147 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3148 ixgbe_irq_enable(adapter);
3151 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3153 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3155 if (adapter->vlgrp) {
3157 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3158 if (!vlan_group_get_device(adapter->vlgrp, vid))
3160 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3166 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3167 * @netdev: network interface device structure
3169 * Writes unicast address list to the RAR table.
3170 * Returns: -ENOMEM on failure/insufficient address space
3171 * 0 on no addresses written
3172 * X on writing X addresses to the RAR table
3174 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3177 struct ixgbe_hw *hw = &adapter->hw;
3178 unsigned int vfn = adapter->num_vfs;
3179 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3182 /* return ENOMEM indicating insufficient memory for addresses */
3183 if (netdev_uc_count(netdev) > rar_entries)
3186 if (!netdev_uc_empty(netdev) && rar_entries) {
3187 struct netdev_hw_addr *ha;
3188 /* return error if we do not support writing to RAR table */
3189 if (!hw->mac.ops.set_rar)
3192 netdev_for_each_uc_addr(ha, netdev) {
3195 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3200 /* write the addresses in reverse order to avoid write combining */
3201 for (; rar_entries > 0 ; rar_entries--)
3202 hw->mac.ops.clear_rar(hw, rar_entries);
3208 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3209 * @netdev: network interface device structure
3211 * The set_rx_method entry point is called whenever the unicast/multicast
3212 * address list or the network interface flags are updated. This routine is
3213 * responsible for configuring the hardware for proper unicast, multicast and
3216 void ixgbe_set_rx_mode(struct net_device *netdev)
3218 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3219 struct ixgbe_hw *hw = &adapter->hw;
3220 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3223 /* Check for Promiscuous and All Multicast modes */
3225 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3227 /* set all bits that we expect to always be set */
3228 fctrl |= IXGBE_FCTRL_BAM;
3229 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3230 fctrl |= IXGBE_FCTRL_PMCF;
3232 /* clear the bits we are changing the status of */
3233 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3235 if (netdev->flags & IFF_PROMISC) {
3236 hw->addr_ctrl.user_set_promisc = true;
3237 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3238 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3239 /* don't hardware filter vlans in promisc mode */
3240 ixgbe_vlan_filter_disable(adapter);
3242 if (netdev->flags & IFF_ALLMULTI) {
3243 fctrl |= IXGBE_FCTRL_MPE;
3244 vmolr |= IXGBE_VMOLR_MPE;
3247 * Write addresses to the MTA, if the attempt fails
3248 * then we should just turn on promiscous mode so
3249 * that we can at least receive multicast traffic
3251 hw->mac.ops.update_mc_addr_list(hw, netdev);
3252 vmolr |= IXGBE_VMOLR_ROMPE;
3254 ixgbe_vlan_filter_enable(adapter);
3255 hw->addr_ctrl.user_set_promisc = false;
3257 * Write addresses to available RAR registers, if there is not
3258 * sufficient space to store all the addresses then enable
3259 * unicast promiscous mode
3261 count = ixgbe_write_uc_addr_list(netdev);
3263 fctrl |= IXGBE_FCTRL_UPE;
3264 vmolr |= IXGBE_VMOLR_ROPE;
3268 if (adapter->num_vfs) {
3269 ixgbe_restore_vf_multicasts(adapter);
3270 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3271 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3273 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3276 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3279 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3282 struct ixgbe_q_vector *q_vector;
3283 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3285 /* legacy and MSI only use one vector */
3286 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3289 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3290 struct napi_struct *napi;
3291 q_vector = adapter->q_vector[q_idx];
3292 napi = &q_vector->napi;
3293 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3294 if (!q_vector->rxr_count || !q_vector->txr_count) {
3295 if (q_vector->txr_count == 1)
3296 napi->poll = &ixgbe_clean_txonly;
3297 else if (q_vector->rxr_count == 1)
3298 napi->poll = &ixgbe_clean_rxonly;
3306 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3309 struct ixgbe_q_vector *q_vector;
3310 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3312 /* legacy and MSI only use one vector */
3313 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3316 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3317 q_vector = adapter->q_vector[q_idx];
3318 napi_disable(&q_vector->napi);
3322 #ifdef CONFIG_IXGBE_DCB
3324 * ixgbe_configure_dcb - Configure DCB hardware
3325 * @adapter: ixgbe adapter struct
3327 * This is called by the driver on open to configure the DCB hardware.
3328 * This is also called by the gennetlink interface when reconfiguring
3331 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3333 struct ixgbe_hw *hw = &adapter->hw;
3337 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3338 if (hw->mac.type == ixgbe_mac_82598EB)
3339 netif_set_gso_max_size(adapter->netdev, 65536);
3343 if (hw->mac.type == ixgbe_mac_82598EB)
3344 netif_set_gso_max_size(adapter->netdev, 32768);
3346 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3347 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3348 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3350 /* reconfigure the hardware */
3351 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3353 for (i = 0; i < adapter->num_tx_queues; i++) {
3354 j = adapter->tx_ring[i]->reg_idx;
3355 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3356 /* PThresh workaround for Tx hang with DFP enabled. */
3358 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3360 /* Enable VLAN tag insert/strip */
3361 ixgbe_vlan_filter_enable(adapter);
3363 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3367 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3369 struct net_device *netdev = adapter->netdev;
3370 struct ixgbe_hw *hw = &adapter->hw;
3373 ixgbe_set_rx_mode(netdev);
3375 ixgbe_restore_vlan(adapter);
3376 #ifdef CONFIG_IXGBE_DCB
3377 ixgbe_configure_dcb(adapter);
3381 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3382 ixgbe_configure_fcoe(adapter);
3384 #endif /* IXGBE_FCOE */
3385 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3386 for (i = 0; i < adapter->num_tx_queues; i++)
3387 adapter->tx_ring[i]->atr_sample_rate =
3388 adapter->atr_sample_rate;
3389 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3390 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3391 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3393 ixgbe_configure_virtualization(adapter);
3395 ixgbe_configure_tx(adapter);
3396 ixgbe_configure_rx(adapter);
3399 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3401 switch (hw->phy.type) {
3402 case ixgbe_phy_sfp_avago:
3403 case ixgbe_phy_sfp_ftl:
3404 case ixgbe_phy_sfp_intel:
3405 case ixgbe_phy_sfp_unknown:
3406 case ixgbe_phy_sfp_passive_tyco:
3407 case ixgbe_phy_sfp_passive_unknown:
3408 case ixgbe_phy_sfp_active_unknown:
3409 case ixgbe_phy_sfp_ftl_active:
3417 * ixgbe_sfp_link_config - set up SFP+ link
3418 * @adapter: pointer to private adapter struct
3420 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3422 struct ixgbe_hw *hw = &adapter->hw;
3424 if (hw->phy.multispeed_fiber) {
3426 * In multispeed fiber setups, the device may not have
3427 * had a physical connection when the driver loaded.
3428 * If that's the case, the initial link configuration
3429 * couldn't get the MAC into 10G or 1G mode, so we'll
3430 * never have a link status change interrupt fire.
3431 * We need to try and force an autonegotiation
3432 * session, then bring up link.
3434 hw->mac.ops.setup_sfp(hw);
3435 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3436 schedule_work(&adapter->multispeed_fiber_task);
3439 * Direct Attach Cu and non-multispeed fiber modules
3440 * still need to be configured properly prior to
3443 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3444 schedule_work(&adapter->sfp_config_module_task);
3449 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3450 * @hw: pointer to private hardware struct
3452 * Returns 0 on success, negative on failure
3454 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3457 bool negotiation, link_up = false;
3458 u32 ret = IXGBE_ERR_LINK_SETUP;
3460 if (hw->mac.ops.check_link)
3461 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3466 if (hw->mac.ops.get_link_capabilities)
3467 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3472 if (hw->mac.ops.setup_link)
3473 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3478 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3480 struct ixgbe_hw *hw = &adapter->hw;
3483 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3484 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3486 gpie |= IXGBE_GPIE_EIAME;
3488 * use EIAM to auto-mask when MSI-X interrupt is asserted
3489 * this saves a register write for every interrupt
3491 switch (hw->mac.type) {
3492 case ixgbe_mac_82598EB:
3493 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3496 case ixgbe_mac_82599EB:
3497 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3498 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3502 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3503 * specifically only auto mask tx and rx interrupts */
3504 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3507 /* XXX: to interrupt immediately for EICS writes, enable this */
3508 /* gpie |= IXGBE_GPIE_EIMEN; */
3510 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3511 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3512 gpie |= IXGBE_GPIE_VTMODE_64;
3515 /* Enable fan failure interrupt */
3516 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3517 gpie |= IXGBE_SDP1_GPIEN;
3519 if (hw->mac.type == ixgbe_mac_82599EB)
3520 gpie |= IXGBE_SDP1_GPIEN;
3521 gpie |= IXGBE_SDP2_GPIEN;
3523 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3526 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3528 struct ixgbe_hw *hw = &adapter->hw;
3532 ixgbe_get_hw_control(adapter);
3533 ixgbe_setup_gpie(adapter);
3535 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3536 ixgbe_configure_msix(adapter);
3538 ixgbe_configure_msi_and_legacy(adapter);
3540 /* enable the optics */
3541 if (hw->phy.multispeed_fiber)
3542 hw->mac.ops.enable_tx_laser(hw);
3544 clear_bit(__IXGBE_DOWN, &adapter->state);
3545 ixgbe_napi_enable_all(adapter);
3547 /* clear any pending interrupts, may auto mask */
3548 IXGBE_READ_REG(hw, IXGBE_EICR);
3549 ixgbe_irq_enable(adapter);
3552 * If this adapter has a fan, check to see if we had a failure
3553 * before we enabled the interrupt.
3555 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3556 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3557 if (esdp & IXGBE_ESDP_SDP1)
3558 e_crit(drv, "Fan has stopped, replace the adapter\n");
3562 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3563 * arrived before interrupts were enabled but after probe. Such
3564 * devices wouldn't have their type identified yet. We need to
3565 * kick off the SFP+ module setup first, then try to bring up link.
3566 * If we're not hot-pluggable SFP+, we just need to configure link
3569 if (hw->phy.type == ixgbe_phy_unknown) {
3570 err = hw->phy.ops.identify(hw);
3571 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3573 * Take the device down and schedule the sfp tasklet
3574 * which will unregister_netdev and log it.
3576 ixgbe_down(adapter);
3577 schedule_work(&adapter->sfp_config_module_task);
3582 if (ixgbe_is_sfp(hw)) {
3583 ixgbe_sfp_link_config(adapter);
3585 err = ixgbe_non_sfp_link_config(hw);
3587 e_err(probe, "link_config FAILED %d\n", err);
3590 /* enable transmits */
3591 netif_tx_start_all_queues(adapter->netdev);
3593 /* bring the link up in the watchdog, this could race with our first
3594 * link up interrupt but shouldn't be a problem */
3595 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3596 adapter->link_check_timeout = jiffies;
3597 mod_timer(&adapter->watchdog_timer, jiffies);
3599 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3600 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3601 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3602 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3607 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3609 WARN_ON(in_interrupt());
3610 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3612 ixgbe_down(adapter);
3614 * If SR-IOV enabled then wait a bit before bringing the adapter
3615 * back up to give the VFs time to respond to the reset. The
3616 * two second wait is based upon the watchdog timer cycle in
3619 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3622 clear_bit(__IXGBE_RESETTING, &adapter->state);
3625 int ixgbe_up(struct ixgbe_adapter *adapter)
3627 /* hardware has been reset, we need to reload some things */
3628 ixgbe_configure(adapter);
3630 return ixgbe_up_complete(adapter);
3633 void ixgbe_reset(struct ixgbe_adapter *adapter)
3635 struct ixgbe_hw *hw = &adapter->hw;
3638 err = hw->mac.ops.init_hw(hw);
3641 case IXGBE_ERR_SFP_NOT_PRESENT:
3643 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3644 e_dev_err("master disable timed out\n");
3646 case IXGBE_ERR_EEPROM_VERSION:
3647 /* We are running on a pre-production device, log a warning */
3648 e_dev_warn("This device is a pre-production adapter/LOM. "
3649 "Please be aware there may be issuesassociated with "
3650 "your hardware. If you are experiencing problems "
3651 "please contact your Intel or hardware "
3652 "representative who provided you with this "
3656 e_dev_err("Hardware Error: %d\n", err);
3659 /* reprogram the RAR[0] in case user changed it. */
3660 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3665 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3666 * @adapter: board private structure
3667 * @rx_ring: ring to free buffers from
3669 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3670 struct ixgbe_ring *rx_ring)
3672 struct pci_dev *pdev = adapter->pdev;
3676 /* ring already cleared, nothing to do */
3677 if (!rx_ring->rx_buffer_info)
3680 /* Free all the Rx ring sk_buffs */
3681 for (i = 0; i < rx_ring->count; i++) {
3682 struct ixgbe_rx_buffer *rx_buffer_info;
3684 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3685 if (rx_buffer_info->dma) {
3686 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3687 rx_ring->rx_buf_len,
3689 rx_buffer_info->dma = 0;
3691 if (rx_buffer_info->skb) {
3692 struct sk_buff *skb = rx_buffer_info->skb;
3693 rx_buffer_info->skb = NULL;
3695 struct sk_buff *this = skb;
3696 if (IXGBE_RSC_CB(this)->delay_unmap) {
3697 dma_unmap_single(&pdev->dev,
3698 IXGBE_RSC_CB(this)->dma,
3699 rx_ring->rx_buf_len,
3701 IXGBE_RSC_CB(this)->dma = 0;
3702 IXGBE_RSC_CB(skb)->delay_unmap = false;
3705 dev_kfree_skb(this);
3708 if (!rx_buffer_info->page)
3710 if (rx_buffer_info->page_dma) {
3711 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3712 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3713 rx_buffer_info->page_dma = 0;
3715 put_page(rx_buffer_info->page);
3716 rx_buffer_info->page = NULL;
3717 rx_buffer_info->page_offset = 0;
3720 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3721 memset(rx_ring->rx_buffer_info, 0, size);
3723 /* Zero out the descriptor ring */
3724 memset(rx_ring->desc, 0, rx_ring->size);
3726 rx_ring->next_to_clean = 0;
3727 rx_ring->next_to_use = 0;
3730 writel(0, adapter->hw.hw_addr + rx_ring->head);
3732 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3736 * ixgbe_clean_tx_ring - Free Tx Buffers
3737 * @adapter: board private structure
3738 * @tx_ring: ring to be cleaned
3740 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3741 struct ixgbe_ring *tx_ring)
3743 struct ixgbe_tx_buffer *tx_buffer_info;
3747 /* ring already cleared, nothing to do */
3748 if (!tx_ring->tx_buffer_info)
3751 /* Free all the Tx ring sk_buffs */
3752 for (i = 0; i < tx_ring->count; i++) {
3753 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3754 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3757 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3758 memset(tx_ring->tx_buffer_info, 0, size);
3760 /* Zero out the descriptor ring */
3761 memset(tx_ring->desc, 0, tx_ring->size);
3763 tx_ring->next_to_use = 0;
3764 tx_ring->next_to_clean = 0;
3767 writel(0, adapter->hw.hw_addr + tx_ring->head);
3769 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3773 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3774 * @adapter: board private structure
3776 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3780 for (i = 0; i < adapter->num_rx_queues; i++)
3781 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3785 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3786 * @adapter: board private structure
3788 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3792 for (i = 0; i < adapter->num_tx_queues; i++)
3793 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3796 void ixgbe_down(struct ixgbe_adapter *adapter)
3798 struct net_device *netdev = adapter->netdev;
3799 struct ixgbe_hw *hw = &adapter->hw;
3804 /* signal that we are down to the interrupt handler */
3805 set_bit(__IXGBE_DOWN, &adapter->state);
3807 /* disable receive for all VFs and wait one second */
3808 if (adapter->num_vfs) {
3809 /* ping all the active vfs to let them know we are going down */
3810 ixgbe_ping_all_vfs(adapter);
3812 /* Disable all VFTE/VFRE TX/RX */
3813 ixgbe_disable_tx_rx(adapter);
3815 /* Mark all the VFs as inactive */
3816 for (i = 0 ; i < adapter->num_vfs; i++)
3817 adapter->vfinfo[i].clear_to_send = 0;
3820 /* disable receives */
3821 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3822 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3824 IXGBE_WRITE_FLUSH(hw);
3827 netif_tx_stop_all_queues(netdev);
3829 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3830 del_timer_sync(&adapter->sfp_timer);
3831 del_timer_sync(&adapter->watchdog_timer);
3832 cancel_work_sync(&adapter->watchdog_task);
3834 netif_carrier_off(netdev);
3835 netif_tx_disable(netdev);
3837 ixgbe_irq_disable(adapter);
3839 ixgbe_napi_disable_all(adapter);
3841 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3842 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3843 cancel_work_sync(&adapter->fdir_reinit_task);
3845 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3846 cancel_work_sync(&adapter->check_overtemp_task);
3848 /* disable transmits in the hardware now that interrupts are off */
3849 for (i = 0; i < adapter->num_tx_queues; i++) {
3850 j = adapter->tx_ring[i]->reg_idx;
3851 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3852 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3853 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3855 /* Disable the Tx DMA engine on 82599 */
3856 if (hw->mac.type == ixgbe_mac_82599EB)
3857 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3858 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3859 ~IXGBE_DMATXCTL_TE));
3861 /* power down the optics */
3862 if (hw->phy.multispeed_fiber)
3863 hw->mac.ops.disable_tx_laser(hw);
3865 /* clear n-tuple filters that are cached */
3866 ethtool_ntuple_flush(netdev);
3868 if (!pci_channel_offline(adapter->pdev))
3869 ixgbe_reset(adapter);
3870 ixgbe_clean_all_tx_rings(adapter);
3871 ixgbe_clean_all_rx_rings(adapter);
3873 #ifdef CONFIG_IXGBE_DCA
3874 /* since we reset the hardware DCA settings were cleared */
3875 ixgbe_setup_dca(adapter);
3880 * ixgbe_poll - NAPI Rx polling callback
3881 * @napi: structure for representing this polling device
3882 * @budget: how many packets driver is allowed to clean
3884 * This function is used for legacy and MSI, NAPI mode
3886 static int ixgbe_poll(struct napi_struct *napi, int budget)
3888 struct ixgbe_q_vector *q_vector =
3889 container_of(napi, struct ixgbe_q_vector, napi);
3890 struct ixgbe_adapter *adapter = q_vector->adapter;
3891 int tx_clean_complete, work_done = 0;
3893 #ifdef CONFIG_IXGBE_DCA
3894 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3895 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3896 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3900 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3901 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3903 if (!tx_clean_complete)
3906 /* If budget not fully consumed, exit the polling mode */
3907 if (work_done < budget) {
3908 napi_complete(napi);
3909 if (adapter->rx_itr_setting & 1)
3910 ixgbe_set_itr(adapter);
3911 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3912 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3918 * ixgbe_tx_timeout - Respond to a Tx Hang
3919 * @netdev: network interface device structure
3921 static void ixgbe_tx_timeout(struct net_device *netdev)
3923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3925 /* Do the reset outside of interrupt context */
3926 schedule_work(&adapter->reset_task);
3929 static void ixgbe_reset_task(struct work_struct *work)
3931 struct ixgbe_adapter *adapter;
3932 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3934 /* If we're already down or resetting, just bail */
3935 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3936 test_bit(__IXGBE_RESETTING, &adapter->state))
3939 adapter->tx_timeout_count++;
3941 ixgbe_dump(adapter);
3942 netdev_err(adapter->netdev, "Reset adapter\n");
3943 ixgbe_reinit_locked(adapter);
3946 #ifdef CONFIG_IXGBE_DCB
3947 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3950 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3952 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3956 adapter->num_rx_queues = f->indices;
3957 adapter->num_tx_queues = f->indices;
3965 * ixgbe_set_rss_queues: Allocate queues for RSS
3966 * @adapter: board private structure to initialize
3968 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3969 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3972 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3975 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3977 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3979 adapter->num_rx_queues = f->indices;
3980 adapter->num_tx_queues = f->indices;
3990 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3991 * @adapter: board private structure to initialize
3993 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3994 * to the original CPU that initiated the Tx session. This runs in addition
3995 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3996 * Rx load across CPUs using RSS.
3999 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4002 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4004 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4007 /* Flow Director must have RSS enabled */
4008 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4009 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4010 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4011 adapter->num_tx_queues = f_fdir->indices;
4012 adapter->num_rx_queues = f_fdir->indices;
4015 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4016 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4023 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4024 * @adapter: board private structure to initialize
4026 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4027 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4028 * rx queues out of the max number of rx queues, instead, it is used as the
4029 * index of the first rx queue used by FCoE.
4032 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4035 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4037 f->indices = min((int)num_online_cpus(), f->indices);
4038 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4039 adapter->num_rx_queues = 1;
4040 adapter->num_tx_queues = 1;
4041 #ifdef CONFIG_IXGBE_DCB
4042 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4043 e_info(probe, "FCoE enabled with DCB\n");
4044 ixgbe_set_dcb_queues(adapter);
4047 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4048 e_info(probe, "FCoE enabled with RSS\n");
4049 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4050 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4051 ixgbe_set_fdir_queues(adapter);
4053 ixgbe_set_rss_queues(adapter);
4055 /* adding FCoE rx rings to the end */
4056 f->mask = adapter->num_rx_queues;
4057 adapter->num_rx_queues += f->indices;
4058 adapter->num_tx_queues += f->indices;
4066 #endif /* IXGBE_FCOE */
4068 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4069 * @adapter: board private structure to initialize
4071 * IOV doesn't actually use anything, so just NAK the
4072 * request for now and let the other queue routines
4073 * figure out what to do.
4075 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4081 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4082 * @adapter: board private structure to initialize
4084 * This is the top level queue allocation routine. The order here is very
4085 * important, starting with the "most" number of features turned on at once,
4086 * and ending with the smallest set of features. This way large combinations
4087 * can be allocated if they're turned on, and smaller combinations are the
4088 * fallthrough conditions.
4091 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4093 /* Start with base case */
4094 adapter->num_rx_queues = 1;
4095 adapter->num_tx_queues = 1;
4096 adapter->num_rx_pools = adapter->num_rx_queues;
4097 adapter->num_rx_queues_per_pool = 1;
4099 if (ixgbe_set_sriov_queues(adapter))
4103 if (ixgbe_set_fcoe_queues(adapter))
4106 #endif /* IXGBE_FCOE */
4107 #ifdef CONFIG_IXGBE_DCB
4108 if (ixgbe_set_dcb_queues(adapter))
4112 if (ixgbe_set_fdir_queues(adapter))
4115 if (ixgbe_set_rss_queues(adapter))
4118 /* fallback to base case */
4119 adapter->num_rx_queues = 1;
4120 adapter->num_tx_queues = 1;
4123 /* Notify the stack of the (possibly) reduced Tx Queue count. */
4124 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4127 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4130 int err, vector_threshold;
4132 /* We'll want at least 3 (vector_threshold):
4135 * 3) Other (Link Status Change, etc.)
4136 * 4) TCP Timer (optional)
4138 vector_threshold = MIN_MSIX_COUNT;
4140 /* The more we get, the more we will assign to Tx/Rx Cleanup
4141 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4142 * Right now, we simply care about how many we'll get; we'll
4143 * set them up later while requesting irq's.
4145 while (vectors >= vector_threshold) {
4146 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4148 if (!err) /* Success in acquiring all requested vectors. */
4151 vectors = 0; /* Nasty failure, quit now */
4152 else /* err == number of vectors we should try again with */
4156 if (vectors < vector_threshold) {
4157 /* Can't allocate enough MSI-X interrupts? Oh well.
4158 * This just means we'll go with either a single MSI
4159 * vector or fall back to legacy interrupts.
4161 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4162 "Unable to allocate MSI-X interrupts\n");
4163 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4164 kfree(adapter->msix_entries);
4165 adapter->msix_entries = NULL;
4167 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4169 * Adjust for only the vectors we'll use, which is minimum
4170 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4171 * vectors we were allocated.
4173 adapter->num_msix_vectors = min(vectors,
4174 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4179 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4180 * @adapter: board private structure to initialize
4182 * Cache the descriptor ring offsets for RSS to the assigned rings.
4185 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4190 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4191 for (i = 0; i < adapter->num_rx_queues; i++)
4192 adapter->rx_ring[i]->reg_idx = i;
4193 for (i = 0; i < adapter->num_tx_queues; i++)
4194 adapter->tx_ring[i]->reg_idx = i;
4203 #ifdef CONFIG_IXGBE_DCB
4205 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4206 * @adapter: board private structure to initialize
4208 * Cache the descriptor ring offsets for DCB to the assigned rings.
4211 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4215 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4217 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4218 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4219 /* the number of queues is assumed to be symmetric */
4220 for (i = 0; i < dcb_i; i++) {
4221 adapter->rx_ring[i]->reg_idx = i << 3;
4222 adapter->tx_ring[i]->reg_idx = i << 2;
4225 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4228 * Tx TC0 starts at: descriptor queue 0
4229 * Tx TC1 starts at: descriptor queue 32
4230 * Tx TC2 starts at: descriptor queue 64
4231 * Tx TC3 starts at: descriptor queue 80
4232 * Tx TC4 starts at: descriptor queue 96
4233 * Tx TC5 starts at: descriptor queue 104
4234 * Tx TC6 starts at: descriptor queue 112
4235 * Tx TC7 starts at: descriptor queue 120
4237 * Rx TC0-TC7 are offset by 16 queues each
4239 for (i = 0; i < 3; i++) {
4240 adapter->tx_ring[i]->reg_idx = i << 5;
4241 adapter->rx_ring[i]->reg_idx = i << 4;
4243 for ( ; i < 5; i++) {
4244 adapter->tx_ring[i]->reg_idx =
4246 adapter->rx_ring[i]->reg_idx = i << 4;
4248 for ( ; i < dcb_i; i++) {
4249 adapter->tx_ring[i]->reg_idx =
4251 adapter->rx_ring[i]->reg_idx = i << 4;
4255 } else if (dcb_i == 4) {
4257 * Tx TC0 starts at: descriptor queue 0
4258 * Tx TC1 starts at: descriptor queue 64
4259 * Tx TC2 starts at: descriptor queue 96
4260 * Tx TC3 starts at: descriptor queue 112
4262 * Rx TC0-TC3 are offset by 32 queues each
4264 adapter->tx_ring[0]->reg_idx = 0;
4265 adapter->tx_ring[1]->reg_idx = 64;
4266 adapter->tx_ring[2]->reg_idx = 96;
4267 adapter->tx_ring[3]->reg_idx = 112;
4268 for (i = 0 ; i < dcb_i; i++)
4269 adapter->rx_ring[i]->reg_idx = i << 5;
4287 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4288 * @adapter: board private structure to initialize
4290 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4293 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4298 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4299 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4300 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4301 for (i = 0; i < adapter->num_rx_queues; i++)
4302 adapter->rx_ring[i]->reg_idx = i;
4303 for (i = 0; i < adapter->num_tx_queues; i++)
4304 adapter->tx_ring[i]->reg_idx = i;
4313 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4314 * @adapter: board private structure to initialize
4316 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4319 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4321 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4323 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4325 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4326 #ifdef CONFIG_IXGBE_DCB
4327 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4328 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4330 ixgbe_cache_ring_dcb(adapter);
4331 /* find out queues in TC for FCoE */
4332 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4333 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4335 * In 82599, the number of Tx queues for each traffic
4336 * class for both 8-TC and 4-TC modes are:
4337 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4338 * 8 TCs: 32 32 16 16 8 8 8 8
4339 * 4 TCs: 64 64 32 32
4340 * We have max 8 queues for FCoE, where 8 the is
4341 * FCoE redirection table size. If TC for FCoE is
4342 * less than or equal to TC3, we have enough queues
4343 * to add max of 8 queues for FCoE, so we start FCoE
4344 * tx descriptor from the next one, i.e., reg_idx + 1.
4345 * If TC for FCoE is above TC3, implying 8 TC mode,
4346 * and we need 8 for FCoE, we have to take all queues
4347 * in that traffic class for FCoE.
4349 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4352 #endif /* CONFIG_IXGBE_DCB */
4353 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4354 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4355 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4356 ixgbe_cache_ring_fdir(adapter);
4358 ixgbe_cache_ring_rss(adapter);
4360 fcoe_rx_i = f->mask;
4361 fcoe_tx_i = f->mask;
4363 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4364 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4365 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4372 #endif /* IXGBE_FCOE */
4374 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4375 * @adapter: board private structure to initialize
4377 * SR-IOV doesn't use any descriptor rings but changes the default if
4378 * no other mapping is used.
4381 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4383 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4384 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4385 if (adapter->num_vfs)
4392 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4393 * @adapter: board private structure to initialize
4395 * Once we know the feature-set enabled for the device, we'll cache
4396 * the register offset the descriptor ring is assigned to.
4398 * Note, the order the various feature calls is important. It must start with
4399 * the "most" features enabled at the same time, then trickle down to the
4400 * least amount of features turned on at once.
4402 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4404 /* start with default case */
4405 adapter->rx_ring[0]->reg_idx = 0;
4406 adapter->tx_ring[0]->reg_idx = 0;
4408 if (ixgbe_cache_ring_sriov(adapter))
4412 if (ixgbe_cache_ring_fcoe(adapter))
4415 #endif /* IXGBE_FCOE */
4416 #ifdef CONFIG_IXGBE_DCB
4417 if (ixgbe_cache_ring_dcb(adapter))
4421 if (ixgbe_cache_ring_fdir(adapter))
4424 if (ixgbe_cache_ring_rss(adapter))
4429 * ixgbe_alloc_queues - Allocate memory for all rings
4430 * @adapter: board private structure to initialize
4432 * We allocate one ring per queue at run-time since we don't know the
4433 * number of queues at compile-time. The polling_netdev array is
4434 * intended for Multiqueue, but should work fine with a single queue.
4436 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4439 int orig_node = adapter->node;
4441 for (i = 0; i < adapter->num_tx_queues; i++) {
4442 struct ixgbe_ring *ring = adapter->tx_ring[i];
4443 if (orig_node == -1) {
4444 int cur_node = next_online_node(adapter->node);
4445 if (cur_node == MAX_NUMNODES)
4446 cur_node = first_online_node;
4447 adapter->node = cur_node;
4449 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4452 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4454 goto err_tx_ring_allocation;
4455 ring->count = adapter->tx_ring_count;
4456 ring->queue_index = i;
4457 ring->numa_node = adapter->node;
4459 adapter->tx_ring[i] = ring;
4462 /* Restore the adapter's original node */
4463 adapter->node = orig_node;
4465 for (i = 0; i < adapter->num_rx_queues; i++) {
4466 struct ixgbe_ring *ring = adapter->rx_ring[i];
4467 if (orig_node == -1) {
4468 int cur_node = next_online_node(adapter->node);
4469 if (cur_node == MAX_NUMNODES)
4470 cur_node = first_online_node;
4471 adapter->node = cur_node;
4473 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4476 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4478 goto err_rx_ring_allocation;
4479 ring->count = adapter->rx_ring_count;
4480 ring->queue_index = i;
4481 ring->numa_node = adapter->node;
4483 adapter->rx_ring[i] = ring;
4486 /* Restore the adapter's original node */
4487 adapter->node = orig_node;
4489 ixgbe_cache_ring_register(adapter);
4493 err_rx_ring_allocation:
4494 for (i = 0; i < adapter->num_tx_queues; i++)
4495 kfree(adapter->tx_ring[i]);
4496 err_tx_ring_allocation:
4501 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4502 * @adapter: board private structure to initialize
4504 * Attempt to configure the interrupts using the best available
4505 * capabilities of the hardware and the kernel.
4507 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4509 struct ixgbe_hw *hw = &adapter->hw;
4511 int vector, v_budget;
4514 * It's easy to be greedy for MSI-X vectors, but it really
4515 * doesn't do us much good if we have a lot more vectors
4516 * than CPU's. So let's be conservative and only ask for
4517 * (roughly) the same number of vectors as there are CPU's.
4519 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4520 (int)num_online_cpus()) + NON_Q_VECTORS;
4523 * At the same time, hardware can only support a maximum of
4524 * hw.mac->max_msix_vectors vectors. With features
4525 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4526 * descriptor queues supported by our device. Thus, we cap it off in
4527 * those rare cases where the cpu count also exceeds our vector limit.
4529 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4531 /* A failure in MSI-X entry allocation isn't fatal, but it does
4532 * mean we disable MSI-X capabilities of the adapter. */
4533 adapter->msix_entries = kcalloc(v_budget,
4534 sizeof(struct msix_entry), GFP_KERNEL);
4535 if (adapter->msix_entries) {
4536 for (vector = 0; vector < v_budget; vector++)
4537 adapter->msix_entries[vector].entry = vector;
4539 ixgbe_acquire_msix_vectors(adapter, v_budget);
4541 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4545 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4546 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4547 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4548 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4549 adapter->atr_sample_rate = 0;
4550 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4551 ixgbe_disable_sriov(adapter);
4553 ixgbe_set_num_queues(adapter);
4555 err = pci_enable_msi(adapter->pdev);
4557 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4559 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4560 "Unable to allocate MSI interrupt, "
4561 "falling back to legacy. Error: %d\n", err);
4571 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4572 * @adapter: board private structure to initialize
4574 * We allocate one q_vector per queue interrupt. If allocation fails we
4577 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4579 int q_idx, num_q_vectors;
4580 struct ixgbe_q_vector *q_vector;
4582 int (*poll)(struct napi_struct *, int);
4584 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4585 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4586 napi_vectors = adapter->num_rx_queues;
4587 poll = &ixgbe_clean_rxtx_many;
4594 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4595 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4596 GFP_KERNEL, adapter->node);
4598 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4602 q_vector->adapter = adapter;
4603 if (q_vector->txr_count && !q_vector->rxr_count)
4604 q_vector->eitr = adapter->tx_eitr_param;
4606 q_vector->eitr = adapter->rx_eitr_param;
4607 q_vector->v_idx = q_idx;
4608 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4609 adapter->q_vector[q_idx] = q_vector;
4617 q_vector = adapter->q_vector[q_idx];
4618 netif_napi_del(&q_vector->napi);
4620 adapter->q_vector[q_idx] = NULL;
4626 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4627 * @adapter: board private structure to initialize
4629 * This function frees the memory allocated to the q_vectors. In addition if
4630 * NAPI is enabled it will delete any references to the NAPI struct prior
4631 * to freeing the q_vector.
4633 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4635 int q_idx, num_q_vectors;
4637 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4638 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4642 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4643 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4644 adapter->q_vector[q_idx] = NULL;
4645 netif_napi_del(&q_vector->napi);
4650 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4652 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4653 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4654 pci_disable_msix(adapter->pdev);
4655 kfree(adapter->msix_entries);
4656 adapter->msix_entries = NULL;
4657 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4658 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4659 pci_disable_msi(adapter->pdev);
4664 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4665 * @adapter: board private structure to initialize
4667 * We determine which interrupt scheme to use based on...
4668 * - Kernel support (MSI, MSI-X)
4669 * - which can be user-defined (via MODULE_PARAM)
4670 * - Hardware queue count (num_*_queues)
4671 * - defined by miscellaneous hardware support/features (RSS, etc.)
4673 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4677 /* Number of supported queues */
4678 ixgbe_set_num_queues(adapter);
4680 err = ixgbe_set_interrupt_capability(adapter);
4682 e_dev_err("Unable to setup interrupt capabilities\n");
4683 goto err_set_interrupt;
4686 err = ixgbe_alloc_q_vectors(adapter);
4688 e_dev_err("Unable to allocate memory for queue vectors\n");
4689 goto err_alloc_q_vectors;
4692 err = ixgbe_alloc_queues(adapter);
4694 e_dev_err("Unable to allocate memory for queues\n");
4695 goto err_alloc_queues;
4698 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4699 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4700 adapter->num_rx_queues, adapter->num_tx_queues);
4702 set_bit(__IXGBE_DOWN, &adapter->state);
4707 ixgbe_free_q_vectors(adapter);
4708 err_alloc_q_vectors:
4709 ixgbe_reset_interrupt_capability(adapter);
4715 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4716 * @adapter: board private structure to clear interrupt scheme on
4718 * We go through and clear interrupt specific resources and reset the structure
4719 * to pre-load conditions
4721 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4725 for (i = 0; i < adapter->num_tx_queues; i++) {
4726 kfree(adapter->tx_ring[i]);
4727 adapter->tx_ring[i] = NULL;
4729 for (i = 0; i < adapter->num_rx_queues; i++) {
4730 kfree(adapter->rx_ring[i]);
4731 adapter->rx_ring[i] = NULL;
4734 ixgbe_free_q_vectors(adapter);
4735 ixgbe_reset_interrupt_capability(adapter);
4739 * ixgbe_sfp_timer - worker thread to find a missing module
4740 * @data: pointer to our adapter struct
4742 static void ixgbe_sfp_timer(unsigned long data)
4744 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4747 * Do the sfp_timer outside of interrupt context due to the
4748 * delays that sfp+ detection requires
4750 schedule_work(&adapter->sfp_task);
4754 * ixgbe_sfp_task - worker thread to find a missing module
4755 * @work: pointer to work_struct containing our data
4757 static void ixgbe_sfp_task(struct work_struct *work)
4759 struct ixgbe_adapter *adapter = container_of(work,
4760 struct ixgbe_adapter,
4762 struct ixgbe_hw *hw = &adapter->hw;
4764 if ((hw->phy.type == ixgbe_phy_nl) &&
4765 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4766 s32 ret = hw->phy.ops.identify_sfp(hw);
4767 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4769 ret = hw->phy.ops.reset(hw);
4770 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4771 e_dev_err("failed to initialize because an unsupported "
4772 "SFP+ module type was detected.\n");
4773 e_dev_err("Reload the driver after installing a "
4774 "supported module.\n");
4775 unregister_netdev(adapter->netdev);
4777 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4779 /* don't need this routine any more */
4780 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4784 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4785 mod_timer(&adapter->sfp_timer,
4786 round_jiffies(jiffies + (2 * HZ)));
4790 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4791 * @adapter: board private structure to initialize
4793 * ixgbe_sw_init initializes the Adapter private data structure.
4794 * Fields are initialized based on PCI device information and
4795 * OS network device settings (MTU size).
4797 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4799 struct ixgbe_hw *hw = &adapter->hw;
4800 struct pci_dev *pdev = adapter->pdev;
4801 struct net_device *dev = adapter->netdev;
4803 #ifdef CONFIG_IXGBE_DCB
4805 struct tc_configuration *tc;
4808 /* PCI config space info */
4810 hw->vendor_id = pdev->vendor;
4811 hw->device_id = pdev->device;
4812 hw->revision_id = pdev->revision;
4813 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4814 hw->subsystem_device_id = pdev->subsystem_device;
4816 /* Set capability flags */
4817 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4818 adapter->ring_feature[RING_F_RSS].indices = rss;
4819 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4820 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4821 if (hw->mac.type == ixgbe_mac_82598EB) {
4822 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4823 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4824 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4825 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4826 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4827 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4828 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4829 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4830 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4831 if (dev->features & NETIF_F_NTUPLE) {
4832 /* Flow Director perfect filter enabled */
4833 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4834 adapter->atr_sample_rate = 0;
4835 spin_lock_init(&adapter->fdir_perfect_lock);
4837 /* Flow Director hash filters enabled */
4838 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4839 adapter->atr_sample_rate = 20;
4841 adapter->ring_feature[RING_F_FDIR].indices =
4842 IXGBE_MAX_FDIR_INDICES;
4843 adapter->fdir_pballoc = 0;
4845 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4846 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4847 adapter->ring_feature[RING_F_FCOE].indices = 0;
4848 #ifdef CONFIG_IXGBE_DCB
4849 /* Default traffic class to use for FCoE */
4850 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4851 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4853 #endif /* IXGBE_FCOE */
4856 #ifdef CONFIG_IXGBE_DCB
4857 /* Configure DCB traffic classes */
4858 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4859 tc = &adapter->dcb_cfg.tc_config[j];
4860 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4861 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4862 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4863 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4864 tc->dcb_pfc = pfc_disabled;
4866 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4867 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4868 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4869 adapter->dcb_cfg.pfc_mode_enable = false;
4870 adapter->dcb_cfg.round_robin_enable = false;
4871 adapter->dcb_set_bitmap = 0x00;
4872 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4873 adapter->ring_feature[RING_F_DCB].indices);
4877 /* default flow control settings */
4878 hw->fc.requested_mode = ixgbe_fc_full;
4879 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4881 adapter->last_lfc_mode = hw->fc.current_mode;
4883 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4884 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4885 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4886 hw->fc.send_xon = true;
4887 hw->fc.disable_fc_autoneg = false;
4889 /* enable itr by default in dynamic mode */
4890 adapter->rx_itr_setting = 1;
4891 adapter->rx_eitr_param = 20000;
4892 adapter->tx_itr_setting = 1;
4893 adapter->tx_eitr_param = 10000;
4895 /* set defaults for eitr in MegaBytes */
4896 adapter->eitr_low = 10;
4897 adapter->eitr_high = 20;
4899 /* set default ring sizes */
4900 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4901 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4903 /* initialize eeprom parameters */
4904 if (ixgbe_init_eeprom_params_generic(hw)) {
4905 e_dev_err("EEPROM initialization failed\n");
4909 /* enable rx csum by default */
4910 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4912 /* get assigned NUMA node */
4913 adapter->node = dev_to_node(&pdev->dev);
4915 set_bit(__IXGBE_DOWN, &adapter->state);
4921 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4922 * @adapter: board private structure
4923 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4925 * Return 0 on success, negative on failure
4927 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4928 struct ixgbe_ring *tx_ring)
4930 struct pci_dev *pdev = adapter->pdev;
4933 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4934 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4935 if (!tx_ring->tx_buffer_info)
4936 tx_ring->tx_buffer_info = vmalloc(size);
4937 if (!tx_ring->tx_buffer_info)
4939 memset(tx_ring->tx_buffer_info, 0, size);
4941 /* round up to nearest 4K */
4942 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4943 tx_ring->size = ALIGN(tx_ring->size, 4096);
4945 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4946 &tx_ring->dma, GFP_KERNEL);
4950 tx_ring->next_to_use = 0;
4951 tx_ring->next_to_clean = 0;
4952 tx_ring->work_limit = tx_ring->count;
4956 vfree(tx_ring->tx_buffer_info);
4957 tx_ring->tx_buffer_info = NULL;
4958 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4963 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4964 * @adapter: board private structure
4966 * If this function returns with an error, then it's possible one or
4967 * more of the rings is populated (while the rest are not). It is the
4968 * callers duty to clean those orphaned rings.
4970 * Return 0 on success, negative on failure
4972 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4976 for (i = 0; i < adapter->num_tx_queues; i++) {
4977 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4980 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4988 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4989 * @adapter: board private structure
4990 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4992 * Returns 0 on success, negative on failure
4994 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4995 struct ixgbe_ring *rx_ring)
4997 struct pci_dev *pdev = adapter->pdev;
5000 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5001 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5002 if (!rx_ring->rx_buffer_info)
5003 rx_ring->rx_buffer_info = vmalloc(size);
5004 if (!rx_ring->rx_buffer_info) {
5005 e_err(probe, "vmalloc allocation failed for the Rx "
5006 "descriptor ring\n");
5009 memset(rx_ring->rx_buffer_info, 0, size);
5011 /* Round up to nearest 4K */
5012 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5013 rx_ring->size = ALIGN(rx_ring->size, 4096);
5015 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5016 &rx_ring->dma, GFP_KERNEL);
5018 if (!rx_ring->desc) {
5019 e_err(probe, "Memory allocation failed for the Rx "
5020 "descriptor ring\n");
5021 vfree(rx_ring->rx_buffer_info);
5025 rx_ring->next_to_clean = 0;
5026 rx_ring->next_to_use = 0;
5035 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5036 * @adapter: board private structure
5038 * If this function returns with an error, then it's possible one or
5039 * more of the rings is populated (while the rest are not). It is the
5040 * callers duty to clean those orphaned rings.
5042 * Return 0 on success, negative on failure
5045 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5049 for (i = 0; i < adapter->num_rx_queues; i++) {
5050 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
5053 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5061 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5062 * @adapter: board private structure
5063 * @tx_ring: Tx descriptor ring for a specific queue
5065 * Free all transmit software resources
5067 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5068 struct ixgbe_ring *tx_ring)
5070 struct pci_dev *pdev = adapter->pdev;
5072 ixgbe_clean_tx_ring(adapter, tx_ring);
5074 vfree(tx_ring->tx_buffer_info);
5075 tx_ring->tx_buffer_info = NULL;
5077 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5080 tx_ring->desc = NULL;
5084 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5085 * @adapter: board private structure
5087 * Free all transmit software resources
5089 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5093 for (i = 0; i < adapter->num_tx_queues; i++)
5094 if (adapter->tx_ring[i]->desc)
5095 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5099 * ixgbe_free_rx_resources - Free Rx Resources
5100 * @adapter: board private structure
5101 * @rx_ring: ring to clean the resources from
5103 * Free all receive software resources
5105 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5106 struct ixgbe_ring *rx_ring)
5108 struct pci_dev *pdev = adapter->pdev;
5110 ixgbe_clean_rx_ring(adapter, rx_ring);
5112 vfree(rx_ring->rx_buffer_info);
5113 rx_ring->rx_buffer_info = NULL;
5115 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5118 rx_ring->desc = NULL;
5122 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5123 * @adapter: board private structure
5125 * Free all receive software resources
5127 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5131 for (i = 0; i < adapter->num_rx_queues; i++)
5132 if (adapter->rx_ring[i]->desc)
5133 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5137 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5138 * @netdev: network interface device structure
5139 * @new_mtu: new value for maximum frame size
5141 * Returns 0 on success, negative on failure
5143 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5145 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5146 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5148 /* MTU < 68 is an error and causes problems on some kernels */
5149 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5152 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5153 /* must set new MTU before calling down or up */
5154 netdev->mtu = new_mtu;
5156 if (netif_running(netdev))
5157 ixgbe_reinit_locked(adapter);
5163 * ixgbe_open - Called when a network interface is made active
5164 * @netdev: network interface device structure
5166 * Returns 0 on success, negative value on failure
5168 * The open entry point is called when a network interface is made
5169 * active by the system (IFF_UP). At this point all resources needed
5170 * for transmit and receive operations are allocated, the interrupt
5171 * handler is registered with the OS, the watchdog timer is started,
5172 * and the stack is notified that the interface is ready.
5174 static int ixgbe_open(struct net_device *netdev)
5176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5179 /* disallow open during test */
5180 if (test_bit(__IXGBE_TESTING, &adapter->state))
5183 netif_carrier_off(netdev);
5185 /* allocate transmit descriptors */
5186 err = ixgbe_setup_all_tx_resources(adapter);
5190 /* allocate receive descriptors */
5191 err = ixgbe_setup_all_rx_resources(adapter);
5195 ixgbe_configure(adapter);
5197 err = ixgbe_request_irq(adapter);
5201 err = ixgbe_up_complete(adapter);
5205 netif_tx_start_all_queues(netdev);
5210 ixgbe_release_hw_control(adapter);
5211 ixgbe_free_irq(adapter);
5214 ixgbe_free_all_rx_resources(adapter);
5216 ixgbe_free_all_tx_resources(adapter);
5217 ixgbe_reset(adapter);
5223 * ixgbe_close - Disables a network interface
5224 * @netdev: network interface device structure
5226 * Returns 0, this is not allowed to fail
5228 * The close entry point is called when an interface is de-activated
5229 * by the OS. The hardware is still under the drivers control, but
5230 * needs to be disabled. A global MAC reset is issued to stop the
5231 * hardware, and all transmit and receive resources are freed.
5233 static int ixgbe_close(struct net_device *netdev)
5235 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5237 ixgbe_down(adapter);
5238 ixgbe_free_irq(adapter);
5240 ixgbe_free_all_tx_resources(adapter);
5241 ixgbe_free_all_rx_resources(adapter);
5243 ixgbe_release_hw_control(adapter);
5249 static int ixgbe_resume(struct pci_dev *pdev)
5251 struct net_device *netdev = pci_get_drvdata(pdev);
5252 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5255 pci_set_power_state(pdev, PCI_D0);
5256 pci_restore_state(pdev);
5258 * pci_restore_state clears dev->state_saved so call
5259 * pci_save_state to restore it.
5261 pci_save_state(pdev);
5263 err = pci_enable_device_mem(pdev);
5265 e_dev_err("Cannot enable PCI device from suspend\n");
5268 pci_set_master(pdev);
5270 pci_wake_from_d3(pdev, false);
5272 err = ixgbe_init_interrupt_scheme(adapter);
5274 e_dev_err("Cannot initialize interrupts for device\n");
5278 ixgbe_reset(adapter);
5280 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5282 if (netif_running(netdev)) {
5283 err = ixgbe_open(adapter->netdev);
5288 netif_device_attach(netdev);
5292 #endif /* CONFIG_PM */
5294 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5296 struct net_device *netdev = pci_get_drvdata(pdev);
5297 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5298 struct ixgbe_hw *hw = &adapter->hw;
5300 u32 wufc = adapter->wol;
5305 netif_device_detach(netdev);
5307 if (netif_running(netdev)) {
5308 ixgbe_down(adapter);
5309 ixgbe_free_irq(adapter);
5310 ixgbe_free_all_tx_resources(adapter);
5311 ixgbe_free_all_rx_resources(adapter);
5315 retval = pci_save_state(pdev);
5321 ixgbe_set_rx_mode(netdev);
5323 /* turn on all-multi mode if wake on multicast is enabled */
5324 if (wufc & IXGBE_WUFC_MC) {
5325 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5326 fctrl |= IXGBE_FCTRL_MPE;
5327 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5330 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5331 ctrl |= IXGBE_CTRL_GIO_DIS;
5332 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5334 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5336 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5337 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5340 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5341 pci_wake_from_d3(pdev, true);
5343 pci_wake_from_d3(pdev, false);
5345 *enable_wake = !!wufc;
5347 ixgbe_clear_interrupt_scheme(adapter);
5349 ixgbe_release_hw_control(adapter);
5351 pci_disable_device(pdev);
5357 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5362 retval = __ixgbe_shutdown(pdev, &wake);
5367 pci_prepare_to_sleep(pdev);
5369 pci_wake_from_d3(pdev, false);
5370 pci_set_power_state(pdev, PCI_D3hot);
5375 #endif /* CONFIG_PM */
5377 static void ixgbe_shutdown(struct pci_dev *pdev)
5381 __ixgbe_shutdown(pdev, &wake);
5383 if (system_state == SYSTEM_POWER_OFF) {
5384 pci_wake_from_d3(pdev, wake);
5385 pci_set_power_state(pdev, PCI_D3hot);
5390 * ixgbe_update_stats - Update the board statistics counters.
5391 * @adapter: board private structure
5393 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5395 struct net_device *netdev = adapter->netdev;
5396 struct ixgbe_hw *hw = &adapter->hw;
5398 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5399 u64 non_eop_descs = 0, restart_queue = 0;
5401 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5402 test_bit(__IXGBE_RESETTING, &adapter->state))
5405 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5408 for (i = 0; i < 16; i++)
5409 adapter->hw_rx_no_dma_resources +=
5410 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5411 for (i = 0; i < adapter->num_rx_queues; i++) {
5412 rsc_count += adapter->rx_ring[i]->rsc_count;
5413 rsc_flush += adapter->rx_ring[i]->rsc_flush;
5415 adapter->rsc_total_count = rsc_count;
5416 adapter->rsc_total_flush = rsc_flush;
5419 /* gather some stats to the adapter struct that are per queue */
5420 for (i = 0; i < adapter->num_tx_queues; i++)
5421 restart_queue += adapter->tx_ring[i]->restart_queue;
5422 adapter->restart_queue = restart_queue;
5424 for (i = 0; i < adapter->num_rx_queues; i++)
5425 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5426 adapter->non_eop_descs = non_eop_descs;
5428 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5429 for (i = 0; i < 8; i++) {
5430 /* for packet buffers not used, the register should read 0 */
5431 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5433 adapter->stats.mpc[i] += mpc;
5434 total_mpc += adapter->stats.mpc[i];
5435 if (hw->mac.type == ixgbe_mac_82598EB)
5436 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5437 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5438 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5439 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5440 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5441 if (hw->mac.type == ixgbe_mac_82599EB) {
5442 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5443 IXGBE_PXONRXCNT(i));
5444 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5445 IXGBE_PXOFFRXCNT(i));
5446 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5448 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5450 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5453 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5455 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5458 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5459 /* work around hardware counting issue */
5460 adapter->stats.gprc -= missed_rx;
5462 /* 82598 hardware only has a 32 bit counter in the high register */
5463 if (hw->mac.type == ixgbe_mac_82599EB) {
5465 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5466 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5467 /* 4 high bits of GORC */
5468 adapter->stats.gorc += (tmp << 32);
5469 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5470 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5471 /* 4 high bits of GOTC */
5472 adapter->stats.gotc += (tmp << 32);
5473 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5474 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5475 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5476 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5477 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5478 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5480 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5481 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5482 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5483 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5484 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5485 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5486 #endif /* IXGBE_FCOE */
5488 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5489 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5490 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5491 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5492 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5494 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5495 adapter->stats.bprc += bprc;
5496 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5497 if (hw->mac.type == ixgbe_mac_82598EB)
5498 adapter->stats.mprc -= bprc;
5499 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5500 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5501 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5502 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5503 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5504 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5505 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5506 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5507 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5508 adapter->stats.lxontxc += lxon;
5509 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5510 adapter->stats.lxofftxc += lxoff;
5511 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5512 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5513 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5515 * 82598 errata - tx of flow control packets is included in tx counters
5517 xon_off_tot = lxon + lxoff;
5518 adapter->stats.gptc -= xon_off_tot;
5519 adapter->stats.mptc -= xon_off_tot;
5520 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5521 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5522 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5523 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5524 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5525 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5526 adapter->stats.ptc64 -= xon_off_tot;
5527 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5528 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5529 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5530 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5531 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5532 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5534 /* Fill out the OS statistics structure */
5535 netdev->stats.multicast = adapter->stats.mprc;
5538 netdev->stats.rx_errors = adapter->stats.crcerrs +
5539 adapter->stats.rlec;
5540 netdev->stats.rx_dropped = 0;
5541 netdev->stats.rx_length_errors = adapter->stats.rlec;
5542 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5543 netdev->stats.rx_missed_errors = total_mpc;
5547 * ixgbe_watchdog - Timer Call-back
5548 * @data: pointer to adapter cast into an unsigned long
5550 static void ixgbe_watchdog(unsigned long data)
5552 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5553 struct ixgbe_hw *hw = &adapter->hw;
5558 * Do the watchdog outside of interrupt context due to the lovely
5559 * delays that some of the newer hardware requires
5562 if (test_bit(__IXGBE_DOWN, &adapter->state))
5563 goto watchdog_short_circuit;
5565 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5567 * for legacy and MSI interrupts don't set any bits
5568 * that are enabled for EIAM, because this operation
5569 * would set *both* EIMS and EICS for any bit in EIAM
5571 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5572 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5573 goto watchdog_reschedule;
5576 /* get one bit for every active tx/rx interrupt vector */
5577 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5578 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5579 if (qv->rxr_count || qv->txr_count)
5580 eics |= ((u64)1 << i);
5583 /* Cause software interrupt to ensure rx rings are cleaned */
5584 ixgbe_irq_rearm_queues(adapter, eics);
5586 watchdog_reschedule:
5587 /* Reset the timer */
5588 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5590 watchdog_short_circuit:
5591 schedule_work(&adapter->watchdog_task);
5595 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5596 * @work: pointer to work_struct containing our data
5598 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5600 struct ixgbe_adapter *adapter = container_of(work,
5601 struct ixgbe_adapter,
5602 multispeed_fiber_task);
5603 struct ixgbe_hw *hw = &adapter->hw;
5607 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5608 autoneg = hw->phy.autoneg_advertised;
5609 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5610 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5611 hw->mac.autotry_restart = false;
5612 if (hw->mac.ops.setup_link)
5613 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5614 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5615 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5619 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5620 * @work: pointer to work_struct containing our data
5622 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5624 struct ixgbe_adapter *adapter = container_of(work,
5625 struct ixgbe_adapter,
5626 sfp_config_module_task);
5627 struct ixgbe_hw *hw = &adapter->hw;
5630 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5632 /* Time for electrical oscillations to settle down */
5634 err = hw->phy.ops.identify_sfp(hw);
5636 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5637 e_dev_err("failed to initialize because an unsupported SFP+ "
5638 "module type was detected.\n");
5639 e_dev_err("Reload the driver after installing a supported "
5641 unregister_netdev(adapter->netdev);
5644 hw->mac.ops.setup_sfp(hw);
5646 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5647 /* This will also work for DA Twinax connections */
5648 schedule_work(&adapter->multispeed_fiber_task);
5649 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5653 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5654 * @work: pointer to work_struct containing our data
5656 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5658 struct ixgbe_adapter *adapter = container_of(work,
5659 struct ixgbe_adapter,
5661 struct ixgbe_hw *hw = &adapter->hw;
5664 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5665 for (i = 0; i < adapter->num_tx_queues; i++)
5666 set_bit(__IXGBE_FDIR_INIT_DONE,
5667 &(adapter->tx_ring[i]->reinit_state));
5669 e_err(probe, "failed to finish FDIR re-initialization, "
5670 "ignored adding FDIR ATR filters\n");
5672 /* Done FDIR Re-initialization, enable transmits */
5673 netif_tx_start_all_queues(adapter->netdev);
5676 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5679 * ixgbe_watchdog_task - worker thread to bring link up
5680 * @work: pointer to work_struct containing our data
5682 static void ixgbe_watchdog_task(struct work_struct *work)
5684 struct ixgbe_adapter *adapter = container_of(work,
5685 struct ixgbe_adapter,
5687 struct net_device *netdev = adapter->netdev;
5688 struct ixgbe_hw *hw = &adapter->hw;
5692 struct ixgbe_ring *tx_ring;
5693 int some_tx_pending = 0;
5695 mutex_lock(&ixgbe_watchdog_lock);
5697 link_up = adapter->link_up;
5698 link_speed = adapter->link_speed;
5700 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5701 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5704 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5705 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5706 hw->mac.ops.fc_enable(hw, i);
5708 hw->mac.ops.fc_enable(hw, 0);
5711 hw->mac.ops.fc_enable(hw, 0);
5716 time_after(jiffies, (adapter->link_check_timeout +
5717 IXGBE_TRY_LINK_TIMEOUT))) {
5718 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5719 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5721 adapter->link_up = link_up;
5722 adapter->link_speed = link_speed;
5726 if (!netif_carrier_ok(netdev)) {
5727 bool flow_rx, flow_tx;
5729 if (hw->mac.type == ixgbe_mac_82599EB) {
5730 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5731 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5732 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5733 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5735 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5736 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5737 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5738 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5741 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5742 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5744 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5745 "1 Gbps" : "unknown speed")),
5746 ((flow_rx && flow_tx) ? "RX/TX" :
5748 (flow_tx ? "TX" : "None"))));
5750 netif_carrier_on(netdev);
5752 /* Force detection of hung controller */
5753 adapter->detect_tx_hung = true;
5756 adapter->link_up = false;
5757 adapter->link_speed = 0;
5758 if (netif_carrier_ok(netdev)) {
5759 e_info(drv, "NIC Link is Down\n");
5760 netif_carrier_off(netdev);
5764 if (!netif_carrier_ok(netdev)) {
5765 for (i = 0; i < adapter->num_tx_queues; i++) {
5766 tx_ring = adapter->tx_ring[i];
5767 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5768 some_tx_pending = 1;
5773 if (some_tx_pending) {
5774 /* We've lost link, so the controller stops DMA,
5775 * but we've got queued Tx work that's never going
5776 * to get done, so reset controller to flush Tx.
5777 * (Do the reset outside of interrupt context).
5779 schedule_work(&adapter->reset_task);
5783 ixgbe_update_stats(adapter);
5784 mutex_unlock(&ixgbe_watchdog_lock);
5787 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5788 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5789 u32 tx_flags, u8 *hdr_len)
5791 struct ixgbe_adv_tx_context_desc *context_desc;
5794 struct ixgbe_tx_buffer *tx_buffer_info;
5795 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5796 u32 mss_l4len_idx, l4len;
5798 if (skb_is_gso(skb)) {
5799 if (skb_header_cloned(skb)) {
5800 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5804 l4len = tcp_hdrlen(skb);
5807 if (skb->protocol == htons(ETH_P_IP)) {
5808 struct iphdr *iph = ip_hdr(skb);
5811 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5815 } else if (skb_is_gso_v6(skb)) {
5816 ipv6_hdr(skb)->payload_len = 0;
5817 tcp_hdr(skb)->check =
5818 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5819 &ipv6_hdr(skb)->daddr,
5823 i = tx_ring->next_to_use;
5825 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5826 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5828 /* VLAN MACLEN IPLEN */
5829 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5831 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5832 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5833 IXGBE_ADVTXD_MACLEN_SHIFT);
5834 *hdr_len += skb_network_offset(skb);
5836 (skb_transport_header(skb) - skb_network_header(skb));
5838 (skb_transport_header(skb) - skb_network_header(skb));
5839 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5840 context_desc->seqnum_seed = 0;
5842 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5843 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5844 IXGBE_ADVTXD_DTYP_CTXT);
5846 if (skb->protocol == htons(ETH_P_IP))
5847 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5848 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5849 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5853 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5854 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5855 /* use index 1 for TSO */
5856 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5857 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5859 tx_buffer_info->time_stamp = jiffies;
5860 tx_buffer_info->next_to_watch = i;
5863 if (i == tx_ring->count)
5865 tx_ring->next_to_use = i;
5872 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5873 struct ixgbe_ring *tx_ring,
5874 struct sk_buff *skb, u32 tx_flags)
5876 struct ixgbe_adv_tx_context_desc *context_desc;
5878 struct ixgbe_tx_buffer *tx_buffer_info;
5879 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5881 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5882 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5883 i = tx_ring->next_to_use;
5884 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5885 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5887 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5889 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5890 vlan_macip_lens |= (skb_network_offset(skb) <<
5891 IXGBE_ADVTXD_MACLEN_SHIFT);
5892 if (skb->ip_summed == CHECKSUM_PARTIAL)
5893 vlan_macip_lens |= (skb_transport_header(skb) -
5894 skb_network_header(skb));
5896 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5897 context_desc->seqnum_seed = 0;
5899 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5900 IXGBE_ADVTXD_DTYP_CTXT);
5902 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5905 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5906 const struct vlan_ethhdr *vhdr =
5907 (const struct vlan_ethhdr *)skb->data;
5909 protocol = vhdr->h_vlan_encapsulated_proto;
5911 protocol = skb->protocol;
5915 case cpu_to_be16(ETH_P_IP):
5916 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5917 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5919 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5920 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5922 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5924 case cpu_to_be16(ETH_P_IPV6):
5925 /* XXX what about other V6 headers?? */
5926 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5928 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5929 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5931 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5934 if (unlikely(net_ratelimit())) {
5935 e_warn(probe, "partial checksum "
5943 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5944 /* use index zero for tx checksum offload */
5945 context_desc->mss_l4len_idx = 0;
5947 tx_buffer_info->time_stamp = jiffies;
5948 tx_buffer_info->next_to_watch = i;
5951 if (i == tx_ring->count)
5953 tx_ring->next_to_use = i;
5961 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5962 struct ixgbe_ring *tx_ring,
5963 struct sk_buff *skb, u32 tx_flags,
5966 struct pci_dev *pdev = adapter->pdev;
5967 struct ixgbe_tx_buffer *tx_buffer_info;
5969 unsigned int total = skb->len;
5970 unsigned int offset = 0, size, count = 0, i;
5971 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5974 i = tx_ring->next_to_use;
5976 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5977 /* excluding fcoe_crc_eof for FCoE */
5978 total -= sizeof(struct fcoe_crc_eof);
5980 len = min(skb_headlen(skb), total);
5982 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5983 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5985 tx_buffer_info->length = size;
5986 tx_buffer_info->mapped_as_page = false;
5987 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5989 size, DMA_TO_DEVICE);
5990 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5992 tx_buffer_info->time_stamp = jiffies;
5993 tx_buffer_info->next_to_watch = i;
6002 if (i == tx_ring->count)
6007 for (f = 0; f < nr_frags; f++) {
6008 struct skb_frag_struct *frag;
6010 frag = &skb_shinfo(skb)->frags[f];
6011 len = min((unsigned int)frag->size, total);
6012 offset = frag->page_offset;
6016 if (i == tx_ring->count)
6019 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6020 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6022 tx_buffer_info->length = size;
6023 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
6027 tx_buffer_info->mapped_as_page = true;
6028 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
6030 tx_buffer_info->time_stamp = jiffies;
6031 tx_buffer_info->next_to_watch = i;
6042 tx_ring->tx_buffer_info[i].skb = skb;
6043 tx_ring->tx_buffer_info[first].next_to_watch = i;
6048 e_dev_err("TX DMA map failed\n");
6050 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6051 tx_buffer_info->dma = 0;
6052 tx_buffer_info->time_stamp = 0;
6053 tx_buffer_info->next_to_watch = 0;
6057 /* clear timestamp and dma mappings for remaining portion of packet */
6060 i += tx_ring->count;
6062 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6063 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6069 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6070 struct ixgbe_ring *tx_ring,
6071 int tx_flags, int count, u32 paylen, u8 hdr_len)
6073 union ixgbe_adv_tx_desc *tx_desc = NULL;
6074 struct ixgbe_tx_buffer *tx_buffer_info;
6075 u32 olinfo_status = 0, cmd_type_len = 0;
6077 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6079 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6081 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6083 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6084 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6086 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6087 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6089 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6090 IXGBE_ADVTXD_POPTS_SHIFT;
6092 /* use index 1 context for tso */
6093 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6094 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6095 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6096 IXGBE_ADVTXD_POPTS_SHIFT;
6098 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6099 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6100 IXGBE_ADVTXD_POPTS_SHIFT;
6102 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6103 olinfo_status |= IXGBE_ADVTXD_CC;
6104 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6105 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6106 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6109 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6111 i = tx_ring->next_to_use;
6113 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6114 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6115 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6116 tx_desc->read.cmd_type_len =
6117 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6118 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6120 if (i == tx_ring->count)
6124 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6127 * Force memory writes to complete before letting h/w
6128 * know there are new descriptors to fetch. (Only
6129 * applicable for weak-ordered memory model archs,
6134 tx_ring->next_to_use = i;
6135 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6138 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6139 int queue, u32 tx_flags)
6141 struct ixgbe_atr_input atr_input;
6143 struct iphdr *iph = ip_hdr(skb);
6144 struct ethhdr *eth = (struct ethhdr *)skb->data;
6145 u16 vlan_id, src_port, dst_port, flex_bytes;
6146 u32 src_ipv4_addr, dst_ipv4_addr;
6149 /* Right now, we support IPv4 only */
6150 if (skb->protocol != htons(ETH_P_IP))
6152 /* check if we're UDP or TCP */
6153 if (iph->protocol == IPPROTO_TCP) {
6155 src_port = th->source;
6156 dst_port = th->dest;
6157 l4type |= IXGBE_ATR_L4TYPE_TCP;
6158 /* l4type IPv4 type is 0, no need to assign */
6160 /* Unsupported L4 header, just bail here */
6164 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6166 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6167 IXGBE_TX_FLAGS_VLAN_SHIFT;
6168 src_ipv4_addr = iph->saddr;
6169 dst_ipv4_addr = iph->daddr;
6170 flex_bytes = eth->h_proto;
6172 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6173 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6174 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6175 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6176 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6177 /* src and dst are inverted, think how the receiver sees them */
6178 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6179 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6181 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6182 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6185 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6186 struct ixgbe_ring *tx_ring, int size)
6188 netif_stop_subqueue(netdev, tx_ring->queue_index);
6189 /* Herbert's original patch had:
6190 * smp_mb__after_netif_stop_queue();
6191 * but since that doesn't exist yet, just open code it. */
6194 /* We need to check again in a case another CPU has just
6195 * made room available. */
6196 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6199 /* A reprieve! - use start_queue because it doesn't call schedule */
6200 netif_start_subqueue(netdev, tx_ring->queue_index);
6201 ++tx_ring->restart_queue;
6205 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6206 struct ixgbe_ring *tx_ring, int size)
6208 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6210 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6213 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6215 struct ixgbe_adapter *adapter = netdev_priv(dev);
6216 int txq = smp_processor_id();
6219 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6220 (skb->protocol == htons(ETH_P_FIP))) {
6221 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6222 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6223 txq += adapter->ring_feature[RING_F_FCOE].mask;
6225 #ifdef CONFIG_IXGBE_DCB
6226 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6227 txq = adapter->fcoe.up;
6234 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6235 while (unlikely(txq >= dev->real_num_tx_queues))
6236 txq -= dev->real_num_tx_queues;
6240 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6241 if (skb->priority == TC_PRIO_CONTROL)
6242 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6244 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6249 return skb_tx_hash(dev, skb);
6252 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6253 struct ixgbe_adapter *adapter,
6254 struct ixgbe_ring *tx_ring)
6256 struct netdev_queue *txq;
6258 unsigned int tx_flags = 0;
6264 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6265 tx_flags |= vlan_tx_tag_get(skb);
6266 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6267 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6268 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6270 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6271 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6272 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6273 skb->priority != TC_PRIO_CONTROL) {
6274 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6275 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6276 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6280 /* for FCoE with DCB, we force the priority to what
6281 * was specified by the switch */
6282 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6283 (skb->protocol == htons(ETH_P_FCOE) ||
6284 skb->protocol == htons(ETH_P_FIP))) {
6285 #ifdef CONFIG_IXGBE_DCB
6286 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6287 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6288 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6289 tx_flags |= ((adapter->fcoe.up << 13)
6290 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6293 /* flag for FCoE offloads */
6294 if (skb->protocol == htons(ETH_P_FCOE))
6295 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6299 /* four things can cause us to need a context descriptor */
6300 if (skb_is_gso(skb) ||
6301 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6302 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6303 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6306 count += TXD_USE_COUNT(skb_headlen(skb));
6307 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6308 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6310 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6312 return NETDEV_TX_BUSY;
6315 first = tx_ring->next_to_use;
6316 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6318 /* setup tx offload for FCoE */
6319 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6321 dev_kfree_skb_any(skb);
6322 return NETDEV_TX_OK;
6325 tx_flags |= IXGBE_TX_FLAGS_FSO;
6326 #endif /* IXGBE_FCOE */
6328 if (skb->protocol == htons(ETH_P_IP))
6329 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6330 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6332 dev_kfree_skb_any(skb);
6333 return NETDEV_TX_OK;
6337 tx_flags |= IXGBE_TX_FLAGS_TSO;
6338 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6339 (skb->ip_summed == CHECKSUM_PARTIAL))
6340 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6343 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6345 /* add the ATR filter if ATR is on */
6346 if (tx_ring->atr_sample_rate) {
6347 ++tx_ring->atr_count;
6348 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6349 test_bit(__IXGBE_FDIR_INIT_DONE,
6350 &tx_ring->reinit_state)) {
6351 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6353 tx_ring->atr_count = 0;
6356 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6357 txq->tx_bytes += skb->len;
6359 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6361 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6364 dev_kfree_skb_any(skb);
6365 tx_ring->tx_buffer_info[first].time_stamp = 0;
6366 tx_ring->next_to_use = first;
6369 return NETDEV_TX_OK;
6372 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6374 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6375 struct ixgbe_ring *tx_ring;
6377 tx_ring = adapter->tx_ring[skb->queue_mapping];
6378 return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6382 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6383 * @netdev: network interface device structure
6384 * @p: pointer to an address structure
6386 * Returns 0 on success, negative on failure
6388 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6390 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6391 struct ixgbe_hw *hw = &adapter->hw;
6392 struct sockaddr *addr = p;
6394 if (!is_valid_ether_addr(addr->sa_data))
6395 return -EADDRNOTAVAIL;
6397 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6398 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6400 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6407 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6410 struct ixgbe_hw *hw = &adapter->hw;
6414 if (prtad != hw->phy.mdio.prtad)
6416 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6422 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6423 u16 addr, u16 value)
6425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6426 struct ixgbe_hw *hw = &adapter->hw;
6428 if (prtad != hw->phy.mdio.prtad)
6430 return hw->phy.ops.write_reg(hw, addr, devad, value);
6433 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6437 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6441 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6443 * @netdev: network interface device structure
6445 * Returns non-zero on failure
6447 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6450 struct ixgbe_adapter *adapter = netdev_priv(dev);
6451 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6453 if (is_valid_ether_addr(mac->san_addr)) {
6455 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6462 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6464 * @netdev: network interface device structure
6466 * Returns non-zero on failure
6468 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6471 struct ixgbe_adapter *adapter = netdev_priv(dev);
6472 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6474 if (is_valid_ether_addr(mac->san_addr)) {
6476 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6482 #ifdef CONFIG_NET_POLL_CONTROLLER
6484 * Polling 'interrupt' - used by things like netconsole to send skbs
6485 * without having to re-enable interrupts. It's not called while
6486 * the interrupt routine is executing.
6488 static void ixgbe_netpoll(struct net_device *netdev)
6490 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6493 /* if interface is down do nothing */
6494 if (test_bit(__IXGBE_DOWN, &adapter->state))
6497 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6498 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6499 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6500 for (i = 0; i < num_q_vectors; i++) {
6501 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6502 ixgbe_msix_clean_many(0, q_vector);
6505 ixgbe_intr(adapter->pdev->irq, netdev);
6507 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6511 static const struct net_device_ops ixgbe_netdev_ops = {
6512 .ndo_open = ixgbe_open,
6513 .ndo_stop = ixgbe_close,
6514 .ndo_start_xmit = ixgbe_xmit_frame,
6515 .ndo_select_queue = ixgbe_select_queue,
6516 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6517 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6518 .ndo_validate_addr = eth_validate_addr,
6519 .ndo_set_mac_address = ixgbe_set_mac,
6520 .ndo_change_mtu = ixgbe_change_mtu,
6521 .ndo_tx_timeout = ixgbe_tx_timeout,
6522 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6523 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6524 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6525 .ndo_do_ioctl = ixgbe_ioctl,
6526 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6527 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6528 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6529 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6530 #ifdef CONFIG_NET_POLL_CONTROLLER
6531 .ndo_poll_controller = ixgbe_netpoll,
6534 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6535 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6536 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6537 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6538 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6539 #endif /* IXGBE_FCOE */
6542 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6543 const struct ixgbe_info *ii)
6545 #ifdef CONFIG_PCI_IOV
6546 struct ixgbe_hw *hw = &adapter->hw;
6549 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6552 /* The 82599 supports up to 64 VFs per physical function
6553 * but this implementation limits allocation to 63 so that
6554 * basic networking resources are still available to the
6557 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6558 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6559 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6561 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6564 /* If call to enable VFs succeeded then allocate memory
6565 * for per VF control structures.
6568 kcalloc(adapter->num_vfs,
6569 sizeof(struct vf_data_storage), GFP_KERNEL);
6570 if (adapter->vfinfo) {
6571 /* Now that we're sure SR-IOV is enabled
6572 * and memory allocated set up the mailbox parameters
6574 ixgbe_init_mbx_params_pf(hw);
6575 memcpy(&hw->mbx.ops, ii->mbx_ops,
6576 sizeof(hw->mbx.ops));
6578 /* Disable RSC when in SR-IOV mode */
6579 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6580 IXGBE_FLAG2_RSC_ENABLED);
6585 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6586 "SRIOV disabled\n");
6587 pci_disable_sriov(adapter->pdev);
6590 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6591 adapter->num_vfs = 0;
6592 #endif /* CONFIG_PCI_IOV */
6596 * ixgbe_probe - Device Initialization Routine
6597 * @pdev: PCI device information struct
6598 * @ent: entry in ixgbe_pci_tbl
6600 * Returns 0 on success, negative on failure
6602 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6603 * The OS initialization, configuring of the adapter private structure,
6604 * and a hardware reset occur.
6606 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6607 const struct pci_device_id *ent)
6609 struct net_device *netdev;
6610 struct ixgbe_adapter *adapter = NULL;
6611 struct ixgbe_hw *hw;
6612 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6613 static int cards_found;
6614 int i, err, pci_using_dac;
6615 unsigned int indices = num_possible_cpus();
6621 /* Catch broken hardware that put the wrong VF device ID in
6622 * the PCIe SR-IOV capability.
6624 if (pdev->is_virtfn) {
6625 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6626 pci_name(pdev), pdev->vendor, pdev->device);
6630 err = pci_enable_device_mem(pdev);
6634 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6635 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6638 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6640 err = dma_set_coherent_mask(&pdev->dev,
6644 "No usable DMA configuration, aborting\n");
6651 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6652 IORESOURCE_MEM), ixgbe_driver_name);
6655 "pci_request_selected_regions failed 0x%x\n", err);
6659 pci_enable_pcie_error_reporting(pdev);
6661 pci_set_master(pdev);
6662 pci_save_state(pdev);
6664 if (ii->mac == ixgbe_mac_82598EB)
6665 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6667 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6669 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6671 indices += min_t(unsigned int, num_possible_cpus(),
6672 IXGBE_MAX_FCOE_INDICES);
6674 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6677 goto err_alloc_etherdev;
6680 SET_NETDEV_DEV(netdev, &pdev->dev);
6682 pci_set_drvdata(pdev, netdev);
6683 adapter = netdev_priv(netdev);
6685 adapter->netdev = netdev;
6686 adapter->pdev = pdev;
6689 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6691 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6692 pci_resource_len(pdev, 0));
6698 for (i = 1; i <= 5; i++) {
6699 if (pci_resource_len(pdev, i) == 0)
6703 netdev->netdev_ops = &ixgbe_netdev_ops;
6704 ixgbe_set_ethtool_ops(netdev);
6705 netdev->watchdog_timeo = 5 * HZ;
6706 strcpy(netdev->name, pci_name(pdev));
6708 adapter->bd_number = cards_found;
6711 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6712 hw->mac.type = ii->mac;
6715 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6716 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6717 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6718 if (!(eec & (1 << 8)))
6719 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6722 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6723 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6724 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6725 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6726 hw->phy.mdio.mmds = 0;
6727 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6728 hw->phy.mdio.dev = netdev;
6729 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6730 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6732 /* set up this timer and work struct before calling get_invariants
6733 * which might start the timer
6735 init_timer(&adapter->sfp_timer);
6736 adapter->sfp_timer.function = ixgbe_sfp_timer;
6737 adapter->sfp_timer.data = (unsigned long) adapter;
6739 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6741 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6742 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6744 /* a new SFP+ module arrival, called from GPI SDP2 context */
6745 INIT_WORK(&adapter->sfp_config_module_task,
6746 ixgbe_sfp_config_module_task);
6748 ii->get_invariants(hw);
6750 /* setup the private structure */
6751 err = ixgbe_sw_init(adapter);
6755 /* Make it possible the adapter to be woken up via WOL */
6756 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6760 * If there is a fan on this device and it has failed log the
6763 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6764 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6765 if (esdp & IXGBE_ESDP_SDP1)
6766 e_crit(probe, "Fan has stopped, replace the adapter\n");
6769 /* reset_hw fills in the perm_addr as well */
6770 hw->phy.reset_if_overtemp = true;
6771 err = hw->mac.ops.reset_hw(hw);
6772 hw->phy.reset_if_overtemp = false;
6773 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6774 hw->mac.type == ixgbe_mac_82598EB) {
6776 * Start a kernel thread to watch for a module to arrive.
6777 * Only do this for 82598, since 82599 will generate
6778 * interrupts on module arrival.
6780 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6781 mod_timer(&adapter->sfp_timer,
6782 round_jiffies(jiffies + (2 * HZ)));
6784 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6785 e_dev_err("failed to initialize because an unsupported SFP+ "
6786 "module type was detected.\n");
6787 e_dev_err("Reload the driver after installing a supported "
6791 e_dev_err("HW Init failed: %d\n", err);
6795 ixgbe_probe_vf(adapter, ii);
6797 netdev->features = NETIF_F_SG |
6799 NETIF_F_HW_VLAN_TX |
6800 NETIF_F_HW_VLAN_RX |
6801 NETIF_F_HW_VLAN_FILTER;
6803 netdev->features |= NETIF_F_IPV6_CSUM;
6804 netdev->features |= NETIF_F_TSO;
6805 netdev->features |= NETIF_F_TSO6;
6806 netdev->features |= NETIF_F_GRO;
6808 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6809 netdev->features |= NETIF_F_SCTP_CSUM;
6811 netdev->vlan_features |= NETIF_F_TSO;
6812 netdev->vlan_features |= NETIF_F_TSO6;
6813 netdev->vlan_features |= NETIF_F_IP_CSUM;
6814 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6815 netdev->vlan_features |= NETIF_F_SG;
6817 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6818 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6819 IXGBE_FLAG_DCB_ENABLED);
6820 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6821 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6823 #ifdef CONFIG_IXGBE_DCB
6824 netdev->dcbnl_ops = &dcbnl_ops;
6828 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6829 if (hw->mac.ops.get_device_caps) {
6830 hw->mac.ops.get_device_caps(hw, &device_caps);
6831 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6832 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6835 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6836 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6837 netdev->vlan_features |= NETIF_F_FSO;
6838 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6840 #endif /* IXGBE_FCOE */
6842 netdev->features |= NETIF_F_HIGHDMA;
6844 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6845 netdev->features |= NETIF_F_LRO;
6847 /* make sure the EEPROM is good */
6848 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6849 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6854 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6855 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6857 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6858 e_dev_err("invalid MAC address\n");
6863 /* power down the optics */
6864 if (hw->phy.multispeed_fiber)
6865 hw->mac.ops.disable_tx_laser(hw);
6867 init_timer(&adapter->watchdog_timer);
6868 adapter->watchdog_timer.function = ixgbe_watchdog;
6869 adapter->watchdog_timer.data = (unsigned long)adapter;
6871 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6872 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6874 err = ixgbe_init_interrupt_scheme(adapter);
6878 switch (pdev->device) {
6879 case IXGBE_DEV_ID_82599_KX4:
6880 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6881 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6887 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6889 /* pick up the PCI bus settings for reporting later */
6890 hw->mac.ops.get_bus_info(hw);
6892 /* print bus type/speed/width info */
6893 e_dev_info("(PCI Express:%s:%s) %pM\n",
6894 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6895 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6897 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6898 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6899 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6902 ixgbe_read_pba_num_generic(hw, &part_num);
6903 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6904 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6905 "PBA No: %06x-%03x\n",
6906 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6907 (part_num >> 8), (part_num & 0xff));
6909 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6910 hw->mac.type, hw->phy.type,
6911 (part_num >> 8), (part_num & 0xff));
6913 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6914 e_dev_warn("PCI-Express bandwidth available for this card is "
6915 "not sufficient for optimal performance.\n");
6916 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6920 /* save off EEPROM version number */
6921 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6923 /* reset the hardware with the new settings */
6924 err = hw->mac.ops.start_hw(hw);
6926 if (err == IXGBE_ERR_EEPROM_VERSION) {
6927 /* We are running on a pre-production device, log a warning */
6928 e_dev_warn("This device is a pre-production adapter/LOM. "
6929 "Please be aware there may be issues associated "
6930 "with your hardware. If you are experiencing "
6931 "problems please contact your Intel or hardware "
6932 "representative who provided you with this "
6935 strcpy(netdev->name, "eth%d");
6936 err = register_netdev(netdev);
6940 /* carrier off reporting is important to ethtool even BEFORE open */
6941 netif_carrier_off(netdev);
6943 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6944 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6945 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6947 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6948 INIT_WORK(&adapter->check_overtemp_task,
6949 ixgbe_check_overtemp_task);
6950 #ifdef CONFIG_IXGBE_DCA
6951 if (dca_add_requester(&pdev->dev) == 0) {
6952 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6953 ixgbe_setup_dca(adapter);
6956 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6957 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6958 for (i = 0; i < adapter->num_vfs; i++)
6959 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6962 /* add san mac addr to netdev */
6963 ixgbe_add_sanmac_netdev(netdev);
6965 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6970 ixgbe_release_hw_control(adapter);
6971 ixgbe_clear_interrupt_scheme(adapter);
6974 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6975 ixgbe_disable_sriov(adapter);
6976 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6977 del_timer_sync(&adapter->sfp_timer);
6978 cancel_work_sync(&adapter->sfp_task);
6979 cancel_work_sync(&adapter->multispeed_fiber_task);
6980 cancel_work_sync(&adapter->sfp_config_module_task);
6981 iounmap(hw->hw_addr);
6983 free_netdev(netdev);
6985 pci_release_selected_regions(pdev,
6986 pci_select_bars(pdev, IORESOURCE_MEM));
6989 pci_disable_device(pdev);
6994 * ixgbe_remove - Device Removal Routine
6995 * @pdev: PCI device information struct
6997 * ixgbe_remove is called by the PCI subsystem to alert the driver
6998 * that it should release a PCI device. The could be caused by a
6999 * Hot-Plug event, or because the driver is going to be removed from
7002 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7004 struct net_device *netdev = pci_get_drvdata(pdev);
7005 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7007 set_bit(__IXGBE_DOWN, &adapter->state);
7008 /* clear the module not found bit to make sure the worker won't
7011 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7012 del_timer_sync(&adapter->watchdog_timer);
7014 del_timer_sync(&adapter->sfp_timer);
7015 cancel_work_sync(&adapter->watchdog_task);
7016 cancel_work_sync(&adapter->sfp_task);
7017 cancel_work_sync(&adapter->multispeed_fiber_task);
7018 cancel_work_sync(&adapter->sfp_config_module_task);
7019 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7020 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7021 cancel_work_sync(&adapter->fdir_reinit_task);
7022 flush_scheduled_work();
7024 #ifdef CONFIG_IXGBE_DCA
7025 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7026 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7027 dca_remove_requester(&pdev->dev);
7028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7033 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7034 ixgbe_cleanup_fcoe(adapter);
7036 #endif /* IXGBE_FCOE */
7038 /* remove the added san mac */
7039 ixgbe_del_sanmac_netdev(netdev);
7041 if (netdev->reg_state == NETREG_REGISTERED)
7042 unregister_netdev(netdev);
7044 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7045 ixgbe_disable_sriov(adapter);
7047 ixgbe_clear_interrupt_scheme(adapter);
7049 ixgbe_release_hw_control(adapter);
7051 iounmap(adapter->hw.hw_addr);
7052 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7055 e_dev_info("complete\n");
7057 free_netdev(netdev);
7059 pci_disable_pcie_error_reporting(pdev);
7061 pci_disable_device(pdev);
7065 * ixgbe_io_error_detected - called when PCI error is detected
7066 * @pdev: Pointer to PCI device
7067 * @state: The current pci connection state
7069 * This function is called after a PCI bus error affecting
7070 * this device has been detected.
7072 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7073 pci_channel_state_t state)
7075 struct net_device *netdev = pci_get_drvdata(pdev);
7076 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7078 netif_device_detach(netdev);
7080 if (state == pci_channel_io_perm_failure)
7081 return PCI_ERS_RESULT_DISCONNECT;
7083 if (netif_running(netdev))
7084 ixgbe_down(adapter);
7085 pci_disable_device(pdev);
7087 /* Request a slot reset. */
7088 return PCI_ERS_RESULT_NEED_RESET;
7092 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7093 * @pdev: Pointer to PCI device
7095 * Restart the card from scratch, as if from a cold-boot.
7097 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7099 struct net_device *netdev = pci_get_drvdata(pdev);
7100 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7101 pci_ers_result_t result;
7104 if (pci_enable_device_mem(pdev)) {
7105 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7106 result = PCI_ERS_RESULT_DISCONNECT;
7108 pci_set_master(pdev);
7109 pci_restore_state(pdev);
7110 pci_save_state(pdev);
7112 pci_wake_from_d3(pdev, false);
7114 ixgbe_reset(adapter);
7115 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7116 result = PCI_ERS_RESULT_RECOVERED;
7119 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7121 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7122 "failed 0x%0x\n", err);
7123 /* non-fatal, continue */
7130 * ixgbe_io_resume - called when traffic can start flowing again.
7131 * @pdev: Pointer to PCI device
7133 * This callback is called when the error recovery driver tells us that
7134 * its OK to resume normal operation.
7136 static void ixgbe_io_resume(struct pci_dev *pdev)
7138 struct net_device *netdev = pci_get_drvdata(pdev);
7139 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7141 if (netif_running(netdev)) {
7142 if (ixgbe_up(adapter)) {
7143 e_info(probe, "ixgbe_up failed after reset\n");
7148 netif_device_attach(netdev);
7151 static struct pci_error_handlers ixgbe_err_handler = {
7152 .error_detected = ixgbe_io_error_detected,
7153 .slot_reset = ixgbe_io_slot_reset,
7154 .resume = ixgbe_io_resume,
7157 static struct pci_driver ixgbe_driver = {
7158 .name = ixgbe_driver_name,
7159 .id_table = ixgbe_pci_tbl,
7160 .probe = ixgbe_probe,
7161 .remove = __devexit_p(ixgbe_remove),
7163 .suspend = ixgbe_suspend,
7164 .resume = ixgbe_resume,
7166 .shutdown = ixgbe_shutdown,
7167 .err_handler = &ixgbe_err_handler
7171 * ixgbe_init_module - Driver Registration Routine
7173 * ixgbe_init_module is the first routine called when the driver is
7174 * loaded. All it does is register with the PCI subsystem.
7176 static int __init ixgbe_init_module(void)
7179 pr_info("%s - version %s\n", ixgbe_driver_string,
7180 ixgbe_driver_version);
7181 pr_info("%s\n", ixgbe_copyright);
7183 #ifdef CONFIG_IXGBE_DCA
7184 dca_register_notify(&dca_notifier);
7187 ret = pci_register_driver(&ixgbe_driver);
7191 module_init(ixgbe_init_module);
7194 * ixgbe_exit_module - Driver Exit Cleanup Routine
7196 * ixgbe_exit_module is called just before the driver is removed
7199 static void __exit ixgbe_exit_module(void)
7201 #ifdef CONFIG_IXGBE_DCA
7202 dca_unregister_notify(&dca_notifier);
7204 pci_unregister_driver(&ixgbe_driver);
7207 #ifdef CONFIG_IXGBE_DCA
7208 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7213 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7214 __ixgbe_notify_dca);
7216 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7219 #endif /* CONFIG_IXGBE_DCA */
7222 * ixgbe_get_hw_dev return device
7223 * used by hardware layer to print debugging information
7225 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7227 struct ixgbe_adapter *adapter = hw->back;
7228 return adapter->netdev;
7231 module_exit(ixgbe_exit_module);