drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  * This program is free software; you can redistribute  it and/or modify it
  17  * under  the terms of  the GNU General  Public License as published by the
  18  * Free Software Foundation;  either version 2 of the  License, or (at your
  19  * option) any later version.
  20  *
  21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  22  *  RA 11 31 24.2
  23  *  Dec +69 19 52
  24  *  V 3.84
  25  *  B-V +1.62
  26  *
  27  *  Theory of operation
  28  *
  29  *  The driver is initialized through of_device. Configuration information
  30  *  is therefore conveyed through an OF-style device tree.
  31  *
  32  *  The Gianfar Ethernet Controller uses a ring of buffer
  33  *  descriptors.  The beginning is indicated by a register
  34  *  pointing to the physical address of the start of the ring.
  35  *  The end is determined by a "wrap" bit being set in the
  36  *  last descriptor of the ring.
  37  *
  38  *  When a packet is received, the RXF bit in the
  39  *  IEVENT register is set, triggering an interrupt when the
  40  *  corresponding bit in the IMASK register is also set (if
  41  *  interrupt coalescing is active, then the interrupt may not
  42  *  happen immediately, but will wait until either a set number
  43  *  of frames or amount of time have passed).  In NAPI, the
  44  *  interrupt handler will signal there is work to be done, and
  45  *  exit. This method will start at the last known empty
  46  *  descriptor, and process every subsequent descriptor until there
  47  *  are none left with data (NAPI will stop after a set number of
  48  *  packets to give time to other tasks, but will eventually
  49  *  process all the packets).  The data arrives inside a
  50  *  pre-allocated skb, and so after the skb is passed up to the
  51  *  stack, a new skb must be allocated, and the address field in
  52  *  the buffer descriptor must be updated to indicate this new
  53  *  skb.
  54  *
  55  *  When the kernel requests that a packet be transmitted, the
  56  *  driver starts where it left off last time, and points the
  57  *  descriptor at the buffer which was passed in.  The driver
  58  *  then informs the DMA engine that there are packets ready to
  59  *  be transmitted.  Once the controller is finished transmitting
  60  *  the packet, an interrupt may be triggered (under the same
  61  *  conditions as for reception, but depending on the TXF bit).
  62  *  The driver then cleans up the buffer.
  63  */
  64
  65 #include <linux/kernel.h>
  66 #include <linux/string.h>
  67 #include <linux/errno.h>
  68 #include <linux/unistd.h>
  69 #include <linux/slab.h>
  70 #include <linux/interrupt.h>
  71 #include <linux/init.h>
  72 #include <linux/delay.h>
  73 #include <linux/netdevice.h>
  74 #include <linux/etherdevice.h>
  75 #include <linux/skbuff.h>
  76 #include <linux/if_vlan.h>
  77 #include <linux/spinlock.h>
  78 #include <linux/mm.h>
  79 #include <linux/of_mdio.h>
  80 #include <linux/of_platform.h>
  81 #include <linux/ip.h>
  82 #include <linux/tcp.h>
  83 #include <linux/udp.h>
  84 #include <linux/in.h>
  85 #include <linux/net_tstamp.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/irq.h>
  89 #include <asm/uaccess.h>
  90 #include <linux/module.h>
  91 #include <linux/dma-mapping.h>
  92 #include <linux/crc32.h>
  93 #include <linux/mii.h>
  94 #include <linux/phy.h>
  95 #include <linux/phy_fixed.h>
  96 #include <linux/of.h>
  97
  98 #include "gianfar.h"
  99 #include "fsl_pq_mdio.h"
 100
 101 #define TX_TIMEOUT      (1*HZ)
 102 #undef BRIEF_GFAR_ERRORS
 103 #undef VERBOSE_GFAR_ERRORS
 104
 105 const char gfar_driver_name[] = "Gianfar Ethernet";
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                 struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct of_device *ofdev,
 125                 const struct of_device_id *match);
 126 static int gfar_remove(struct of_device *ofdev);
 127 static void free_skb_resources(struct gfar_private *priv);
 128 static void gfar_set_multi(struct net_device *dev);
 129 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 130 static void gfar_configure_serdes(struct net_device *dev);
 131 static int gfar_poll(struct napi_struct *napi, int budget);
 132 #ifdef CONFIG_NET_POLL_CONTROLLER
 133 static void gfar_netpoll(struct net_device *dev);
 134 #endif
 135 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 136 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 137 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 138                               int amount_pull);
 139 static void gfar_vlan_rx_register(struct net_device *netdev,
 140                                 struct vlan_group *grp);
 141 void gfar_halt(struct net_device *dev);
 142 static void gfar_halt_nodisable(struct net_device *dev);
 143 void gfar_start(struct net_device *dev);
 144 static void gfar_clear_exact_match(struct net_device *dev);
 145 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 146 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 147
 148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 150 MODULE_LICENSE("GPL");
 151
 152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 153                             dma_addr_t buf)
 154 {
 155         u32 lstatus;
 156
 157         bdp->bufPtr = buf;
 158
 159         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 160         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 161                 lstatus |= BD_LFLAG(RXBD_WRAP);
 162
 163         eieio();
 164
 165         bdp->lstatus = lstatus;
 166 }
 167
 168 static int gfar_init_bds(struct net_device *ndev)
 169 {
 170         struct gfar_private *priv = netdev_priv(ndev);
 171         struct gfar_priv_tx_q *tx_queue = NULL;
 172         struct gfar_priv_rx_q *rx_queue = NULL;
 173         struct txbd8 *txbdp;
 174         struct rxbd8 *rxbdp;
 175         int i, j;
 176
 177         for (i = 0; i < priv->num_tx_queues; i++) {
 178                 tx_queue = priv->tx_queue[i];
 179                 /* Initialize some variables in our dev structure */
 180                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 181                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 182                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 183                 tx_queue->skb_curtx = 0;
 184                 tx_queue->skb_dirtytx = 0;
 185
 186                 /* Initialize Transmit Descriptor Ring */
 187                 txbdp = tx_queue->tx_bd_base;
 188                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 189                         txbdp->lstatus = 0;
 190                         txbdp->bufPtr = 0;
 191                         txbdp++;
 192                 }
 193
 194                 /* Set the last descriptor in the ring to indicate wrap */
 195                 txbdp--;
 196                 txbdp->status |= TXBD_WRAP;
 197         }
 198
 199         for (i = 0; i < priv->num_rx_queues; i++) {
 200                 rx_queue = priv->rx_queue[i];
 201                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 202                 rx_queue->skb_currx = 0;
 203                 rxbdp = rx_queue->rx_bd_base;
 204
 205                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 206                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 207
 208                         if (skb) {
 209                                 gfar_init_rxbdp(rx_queue, rxbdp,
 210                                                 rxbdp->bufPtr);
 211                         } else {
 212                                 skb = gfar_new_skb(ndev);
 213                                 if (!skb) {
 214                                         pr_err("%s: Can't allocate RX buffers\n",
 215                                                         ndev->name);
 216                                         goto err_rxalloc_fail;
 217                                 }
 218                                 rx_queue->rx_skbuff[j] = skb;
 219
 220                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 221                         }
 222
 223                         rxbdp++;
 224                 }
 225
 226         }
 227
 228         return 0;
 229
 230 err_rxalloc_fail:
 231         free_skb_resources(priv);
 232         return -ENOMEM;
 233 }
 234
 235 static int gfar_alloc_skb_resources(struct net_device *ndev)
 236 {
 237         void *vaddr;
 238         dma_addr_t addr;
 239         int i, j, k;
 240         struct gfar_private *priv = netdev_priv(ndev);
 241         struct device *dev = &priv->ofdev->dev;
 242         struct gfar_priv_tx_q *tx_queue = NULL;
 243         struct gfar_priv_rx_q *rx_queue = NULL;
 244
 245         priv->total_tx_ring_size = 0;
 246         for (i = 0; i < priv->num_tx_queues; i++)
 247                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 248
 249         priv->total_rx_ring_size = 0;
 250         for (i = 0; i < priv->num_rx_queues; i++)
 251                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 252
 253         /* Allocate memory for the buffer descriptors */
 254         vaddr = dma_alloc_coherent(dev,
 255                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 256                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 257                         &addr, GFP_KERNEL);
 258         if (!vaddr) {
 259                 if (netif_msg_ifup(priv))
 260                         pr_err("%s: Could not allocate buffer descriptors!\n",
 261                                ndev->name);
 262                 return -ENOMEM;
 263         }
 264
 265         for (i = 0; i < priv->num_tx_queues; i++) {
 266                 tx_queue = priv->tx_queue[i];
 267                 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
 268                 tx_queue->tx_bd_dma_base = addr;
 269                 tx_queue->dev = ndev;
 270                 /* enet DMA only understands physical addresses */
 271                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 272                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 273         }
 274
 275         /* Start the rx descriptor ring where the tx ring leaves off */
 276         for (i = 0; i < priv->num_rx_queues; i++) {
 277                 rx_queue = priv->rx_queue[i];
 278                 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
 279                 rx_queue->rx_bd_dma_base = addr;
 280                 rx_queue->dev = ndev;
 281                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 282                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 283         }
 284
 285         /* Setup the skbuff rings */
 286         for (i = 0; i < priv->num_tx_queues; i++) {
 287                 tx_queue = priv->tx_queue[i];
 288                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 289                                   tx_queue->tx_ring_size, GFP_KERNEL);
 290                 if (!tx_queue->tx_skbuff) {
 291                         if (netif_msg_ifup(priv))
 292                                 pr_err("%s: Could not allocate tx_skbuff\n",
 293                                                 ndev->name);
 294                         goto cleanup;
 295                 }
 296
 297                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 298                         tx_queue->tx_skbuff[k] = NULL;
 299         }
 300
 301         for (i = 0; i < priv->num_rx_queues; i++) {
 302                 rx_queue = priv->rx_queue[i];
 303                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 304                                   rx_queue->rx_ring_size, GFP_KERNEL);
 305
 306                 if (!rx_queue->rx_skbuff) {
 307                         if (netif_msg_ifup(priv))
 308                                 pr_err("%s: Could not allocate rx_skbuff\n",
 309                                        ndev->name);
 310                         goto cleanup;
 311                 }
 312
 313                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 314                         rx_queue->rx_skbuff[j] = NULL;
 315         }
 316
 317         if (gfar_init_bds(ndev))
 318                 goto cleanup;
 319
 320         return 0;
 321
 322 cleanup:
 323         free_skb_resources(priv);
 324         return -ENOMEM;
 325 }
 326
 327 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 328 {
 329         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 330         u32 __iomem *baddr;
 331         int i;
 332
 333         baddr = &regs->tbase0;
 334         for(i = 0; i < priv->num_tx_queues; i++) {
 335                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 336                 baddr   += 2;
 337         }
 338
 339         baddr = &regs->rbase0;
 340         for(i = 0; i < priv->num_rx_queues; i++) {
 341                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 342                 baddr   += 2;
 343         }
 344 }
 345
 346 static void gfar_init_mac(struct net_device *ndev)
 347 {
 348         struct gfar_private *priv = netdev_priv(ndev);
 349         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 350         u32 rctrl = 0;
 351         u32 tctrl = 0;
 352         u32 attrs = 0;
 353
 354         /* write the tx/rx base registers */
 355         gfar_init_tx_rx_base(priv);
 356
 357         /* Configure the coalescing support */
 358         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 359
 360         if (priv->rx_filer_enable) {
 361                 rctrl |= RCTRL_FILREN;
 362                 /* Program the RIR0 reg with the required distribution */
 363                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 364         }
 365
 366         if (priv->rx_csum_enable)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash) {
 370                 rctrl |= RCTRL_EXTHASH;
 371
 372                 gfar_clear_exact_match(ndev);
 373                 rctrl |= RCTRL_EMEN;
 374         }
 375
 376         if (priv->padding) {
 377                 rctrl &= ~RCTRL_PAL_MASK;
 378                 rctrl |= RCTRL_PADDING(priv->padding);
 379         }
 380
 381         /* Insert receive time stamps into padding alignment bytes */
 382         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 383                 rctrl &= ~RCTRL_PAL_MASK;
 384                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE | RCTRL_PADDING(8);
 385                 priv->padding = 8;
 386         }
 387
 388         /* keep vlan related bits if it's enabled */
 389         if (priv->vlgrp) {
 390                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 391                 tctrl |= TCTRL_VLINS;
 392         }
 393
 394         /* Init rctrl based on our settings */
 395         gfar_write(&regs->rctrl, rctrl);
 396
 397         if (ndev->features & NETIF_F_IP_CSUM)
 398                 tctrl |= TCTRL_INIT_CSUM;
 399
 400         tctrl |= TCTRL_TXSCHED_PRIO;
 401
 402         gfar_write(&regs->tctrl, tctrl);
 403
 404         /* Set the extraction length and index */
 405         attrs = ATTRELI_EL(priv->rx_stash_size) |
 406                 ATTRELI_EI(priv->rx_stash_index);
 407
 408         gfar_write(&regs->attreli, attrs);
 409
 410         /* Start with defaults, and add stashing or locking
 411          * depending on the approprate variables */
 412         attrs = ATTR_INIT_SETTINGS;
 413
 414         if (priv->bd_stash_en)
 415                 attrs |= ATTR_BDSTASH;
 416
 417         if (priv->rx_stash_size != 0)
 418                 attrs |= ATTR_BUFSTASH;
 419
 420         gfar_write(&regs->attr, attrs);
 421
 422         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 423         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 424         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 425 }
 426
 427 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 428 {
 429         struct gfar_private *priv = netdev_priv(dev);
 430         struct netdev_queue *txq;
 431         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 432         unsigned long tx_packets = 0, tx_bytes = 0;
 433         int i = 0;
 434
 435         for (i = 0; i < priv->num_rx_queues; i++) {
 436                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 437                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
 438                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 439         }
 440
 441         dev->stats.rx_packets = rx_packets;
 442         dev->stats.rx_bytes = rx_bytes;
 443         dev->stats.rx_dropped = rx_dropped;
 444
 445         for (i = 0; i < priv->num_tx_queues; i++) {
 446                 txq = netdev_get_tx_queue(dev, i);
 447                 tx_bytes += txq->tx_bytes;
 448                 tx_packets += txq->tx_packets;
 449         }
 450
 451         dev->stats.tx_bytes = tx_bytes;
 452         dev->stats.tx_packets = tx_packets;
 453
 454         return &dev->stats;
 455 }
 456
 457 static const struct net_device_ops gfar_netdev_ops = {
 458         .ndo_open = gfar_enet_open,
 459         .ndo_start_xmit = gfar_start_xmit,
 460         .ndo_stop = gfar_close,
 461         .ndo_change_mtu = gfar_change_mtu,
 462         .ndo_set_multicast_list = gfar_set_multi,
 463         .ndo_tx_timeout = gfar_timeout,
 464         .ndo_do_ioctl = gfar_ioctl,
 465         .ndo_get_stats = gfar_get_stats,
 466         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 467         .ndo_set_mac_address = eth_mac_addr,
 468         .ndo_validate_addr = eth_validate_addr,
 469 #ifdef CONFIG_NET_POLL_CONTROLLER
 470         .ndo_poll_controller = gfar_netpoll,
 471 #endif
 472 };
 473
 474 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
 475 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
 476
 477 void lock_rx_qs(struct gfar_private *priv)
 478 {
 479         int i = 0x0;
 480
 481         for (i = 0; i < priv->num_rx_queues; i++)
 482                 spin_lock(&priv->rx_queue[i]->rxlock);
 483 }
 484
 485 void lock_tx_qs(struct gfar_private *priv)
 486 {
 487         int i = 0x0;
 488
 489         for (i = 0; i < priv->num_tx_queues; i++)
 490                 spin_lock(&priv->tx_queue[i]->txlock);
 491 }
 492
 493 void unlock_rx_qs(struct gfar_private *priv)
 494 {
 495         int i = 0x0;
 496
 497         for (i = 0; i < priv->num_rx_queues; i++)
 498                 spin_unlock(&priv->rx_queue[i]->rxlock);
 499 }
 500
 501 void unlock_tx_qs(struct gfar_private *priv)
 502 {
 503         int i = 0x0;
 504
 505         for (i = 0; i < priv->num_tx_queues; i++)
 506                 spin_unlock(&priv->tx_queue[i]->txlock);
 507 }
 508
 509 /* Returns 1 if incoming frames use an FCB */
 510 static inline int gfar_uses_fcb(struct gfar_private *priv)
 511 {
 512         return priv->vlgrp || priv->rx_csum_enable ||
 513                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 514 }
 515
 516 static void free_tx_pointers(struct gfar_private *priv)
 517 {
 518         int i = 0;
 519
 520         for (i = 0; i < priv->num_tx_queues; i++)
 521                 kfree(priv->tx_queue[i]);
 522 }
 523
 524 static void free_rx_pointers(struct gfar_private *priv)
 525 {
 526         int i = 0;
 527
 528         for (i = 0; i < priv->num_rx_queues; i++)
 529                 kfree(priv->rx_queue[i]);
 530 }
 531
 532 static void unmap_group_regs(struct gfar_private *priv)
 533 {
 534         int i = 0;
 535
 536         for (i = 0; i < MAXGROUPS; i++)
 537                 if (priv->gfargrp[i].regs)
 538                         iounmap(priv->gfargrp[i].regs);
 539 }
 540
 541 static void disable_napi(struct gfar_private *priv)
 542 {
 543         int i = 0;
 544
 545         for (i = 0; i < priv->num_grps; i++)
 546                 napi_disable(&priv->gfargrp[i].napi);
 547 }
 548
 549 static void enable_napi(struct gfar_private *priv)
 550 {
 551         int i = 0;
 552
 553         for (i = 0; i < priv->num_grps; i++)
 554                 napi_enable(&priv->gfargrp[i].napi);
 555 }
 556
 557 static int gfar_parse_group(struct device_node *np,
 558                 struct gfar_private *priv, const char *model)
 559 {
 560         u32 *queue_mask;
 561         u64 addr, size;
 562
 563         addr = of_translate_address(np,
 564                         of_get_address(np, 0, &size, NULL));
 565         priv->gfargrp[priv->num_grps].regs = ioremap(addr, size);
 566
 567         if (!priv->gfargrp[priv->num_grps].regs)
 568                 return -ENOMEM;
 569
 570         priv->gfargrp[priv->num_grps].interruptTransmit =
 571                         irq_of_parse_and_map(np, 0);
 572
 573         /* If we aren't the FEC we have multiple interrupts */
 574         if (model && strcasecmp(model, "FEC")) {
 575                 priv->gfargrp[priv->num_grps].interruptReceive =
 576                         irq_of_parse_and_map(np, 1);
 577                 priv->gfargrp[priv->num_grps].interruptError =
 578                         irq_of_parse_and_map(np,2);
 579                 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
 580                         priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
 581                         priv->gfargrp[priv->num_grps].interruptError < 0) {
 582                         return -EINVAL;
 583                 }
 584         }
 585
 586         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 587         priv->gfargrp[priv->num_grps].priv = priv;
 588         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 589         if(priv->mode == MQ_MG_MODE) {
 590                 queue_mask = (u32 *)of_get_property(np,
 591                                         "fsl,rx-bit-map", NULL);
 592                 priv->gfargrp[priv->num_grps].rx_bit_map =
 593                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 594                 queue_mask = (u32 *)of_get_property(np,
 595                                         "fsl,tx-bit-map", NULL);
 596                 priv->gfargrp[priv->num_grps].tx_bit_map =
 597                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 598         } else {
 599                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 600                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 601         }
 602         priv->num_grps++;
 603
 604         return 0;
 605 }
 606
 607 static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
 608 {
 609         const char *model;
 610         const char *ctype;
 611         const void *mac_addr;
 612         int err = 0, i;
 613         struct net_device *dev = NULL;
 614         struct gfar_private *priv = NULL;
 615         struct device_node *np = ofdev->node;
 616         struct device_node *child = NULL;
 617         const u32 *stash;
 618         const u32 *stash_len;
 619         const u32 *stash_idx;
 620         unsigned int num_tx_qs, num_rx_qs;
 621         u32 *tx_queues, *rx_queues;
 622
 623         if (!np || !of_device_is_available(np))
 624                 return -ENODEV;
 625
 626         /* parse the num of tx and rx queues */
 627         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 628         num_tx_qs = tx_queues ? *tx_queues : 1;
 629
 630         if (num_tx_qs > MAX_TX_QS) {
 631                 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 632                                 num_tx_qs, MAX_TX_QS);
 633                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 634                 return -EINVAL;
 635         }
 636
 637         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 638         num_rx_qs = rx_queues ? *rx_queues : 1;
 639
 640         if (num_rx_qs > MAX_RX_QS) {
 641                 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 642                                 num_tx_qs, MAX_TX_QS);
 643                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 644                 return -EINVAL;
 645         }
 646
 647         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 648         dev = *pdev;
 649         if (NULL == dev)
 650                 return -ENOMEM;
 651
 652         priv = netdev_priv(dev);
 653         priv->node = ofdev->node;
 654         priv->ndev = dev;
 655
 656         dev->num_tx_queues = num_tx_qs;
 657         dev->real_num_tx_queues = num_tx_qs;
 658         priv->num_tx_queues = num_tx_qs;
 659         priv->num_rx_queues = num_rx_qs;
 660         priv->num_grps = 0x0;
 661
 662         model = of_get_property(np, "model", NULL);
 663
 664         for (i = 0; i < MAXGROUPS; i++)
 665                 priv->gfargrp[i].regs = NULL;
 666
 667         /* Parse and initialize group specific information */
 668         if (of_device_is_compatible(np, "fsl,etsec2")) {
 669                 priv->mode = MQ_MG_MODE;
 670                 for_each_child_of_node(np, child) {
 671                         err = gfar_parse_group(child, priv, model);
 672                         if (err)
 673                                 goto err_grp_init;
 674                 }
 675         } else {
 676                 priv->mode = SQ_SG_MODE;
 677                 err = gfar_parse_group(np, priv, model);
 678                 if(err)
 679                         goto err_grp_init;
 680         }
 681
 682         for (i = 0; i < priv->num_tx_queues; i++)
 683                priv->tx_queue[i] = NULL;
 684         for (i = 0; i < priv->num_rx_queues; i++)
 685                 priv->rx_queue[i] = NULL;
 686
 687         for (i = 0; i < priv->num_tx_queues; i++) {
 688                 priv->tx_queue[i] =  (struct gfar_priv_tx_q *)kzalloc(
 689                                 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
 690                 if (!priv->tx_queue[i]) {
 691                         err = -ENOMEM;
 692                         goto tx_alloc_failed;
 693                 }
 694                 priv->tx_queue[i]->tx_skbuff = NULL;
 695                 priv->tx_queue[i]->qindex = i;
 696                 priv->tx_queue[i]->dev = dev;
 697                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 698         }
 699
 700         for (i = 0; i < priv->num_rx_queues; i++) {
 701                 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kzalloc(
 702                                         sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
 703                 if (!priv->rx_queue[i]) {
 704                         err = -ENOMEM;
 705                         goto rx_alloc_failed;
 706                 }
 707                 priv->rx_queue[i]->rx_skbuff = NULL;
 708                 priv->rx_queue[i]->qindex = i;
 709                 priv->rx_queue[i]->dev = dev;
 710                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 711         }
 712
 713
 714         stash = of_get_property(np, "bd-stash", NULL);
 715
 716         if (stash) {
 717                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 718                 priv->bd_stash_en = 1;
 719         }
 720
 721         stash_len = of_get_property(np, "rx-stash-len", NULL);
 722
 723         if (stash_len)
 724                 priv->rx_stash_size = *stash_len;
 725
 726         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 727
 728         if (stash_idx)
 729                 priv->rx_stash_index = *stash_idx;
 730
 731         if (stash_len || stash_idx)
 732                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 733
 734         mac_addr = of_get_mac_address(np);
 735         if (mac_addr)
 736                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 737
 738         if (model && !strcasecmp(model, "TSEC"))
 739                 priv->device_flags =
 740                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 741                         FSL_GIANFAR_DEV_HAS_COALESCE |
 742                         FSL_GIANFAR_DEV_HAS_RMON |
 743                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 744         if (model && !strcasecmp(model, "eTSEC"))
 745                 priv->device_flags =
 746                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 747                         FSL_GIANFAR_DEV_HAS_COALESCE |
 748                         FSL_GIANFAR_DEV_HAS_RMON |
 749                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 750                         FSL_GIANFAR_DEV_HAS_PADDING |
 751                         FSL_GIANFAR_DEV_HAS_CSUM |
 752                         FSL_GIANFAR_DEV_HAS_VLAN |
 753                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 754                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 755                         FSL_GIANFAR_DEV_HAS_TIMER;
 756
 757         ctype = of_get_property(np, "phy-connection-type", NULL);
 758
 759         /* We only care about rgmii-id.  The rest are autodetected */
 760         if (ctype && !strcmp(ctype, "rgmii-id"))
 761                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 762         else
 763                 priv->interface = PHY_INTERFACE_MODE_MII;
 764
 765         if (of_get_property(np, "fsl,magic-packet", NULL))
 766                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 767
 768         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 769
 770         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 771         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 772
 773         return 0;
 774
 775 rx_alloc_failed:
 776         free_rx_pointers(priv);
 777 tx_alloc_failed:
 778         free_tx_pointers(priv);
 779 err_grp_init:
 780         unmap_group_regs(priv);
 781         free_netdev(dev);
 782         return err;
 783 }
 784
 785 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 786                         struct ifreq *ifr, int cmd)
 787 {
 788         struct hwtstamp_config config;
 789         struct gfar_private *priv = netdev_priv(netdev);
 790
 791         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 792                 return -EFAULT;
 793
 794         /* reserved for future extensions */
 795         if (config.flags)
 796                 return -EINVAL;
 797
 798         if (config.tx_type)
 799                 return -ERANGE;
 800
 801         switch (config.rx_filter) {
 802         case HWTSTAMP_FILTER_NONE:
 803                 priv->hwts_rx_en = 0;
 804                 break;
 805         default:
 806                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 807                         return -ERANGE;
 808                 priv->hwts_rx_en = 1;
 809                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 810                 break;
 811         }
 812
 813         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 814                 -EFAULT : 0;
 815 }
 816
 817 /* Ioctl MII Interface */
 818 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 819 {
 820         struct gfar_private *priv = netdev_priv(dev);
 821
 822         if (!netif_running(dev))
 823                 return -EINVAL;
 824
 825         if (cmd == SIOCSHWTSTAMP)
 826                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 827
 828         if (!priv->phydev)
 829                 return -ENODEV;
 830
 831         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
 832 }
 833
 834 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 835 {
 836         unsigned int new_bit_map = 0x0;
 837         int mask = 0x1 << (max_qs - 1), i;
 838         for (i = 0; i < max_qs; i++) {
 839                 if (bit_map & mask)
 840                         new_bit_map = new_bit_map + (1 << i);
 841                 mask = mask >> 0x1;
 842         }
 843         return new_bit_map;
 844 }
 845
 846 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 847                                    u32 class)
 848 {
 849         u32 rqfpr = FPR_FILER_MASK;
 850         u32 rqfcr = 0x0;
 851
 852         rqfar--;
 853         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 854         ftp_rqfpr[rqfar] = rqfpr;
 855         ftp_rqfcr[rqfar] = rqfcr;
 856         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 857
 858         rqfar--;
 859         rqfcr = RQFCR_CMP_NOMATCH;
 860         ftp_rqfpr[rqfar] = rqfpr;
 861         ftp_rqfcr[rqfar] = rqfcr;
 862         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 863
 864         rqfar--;
 865         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 866         rqfpr = class;
 867         ftp_rqfcr[rqfar] = rqfcr;
 868         ftp_rqfpr[rqfar] = rqfpr;
 869         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 870
 871         rqfar--;
 872         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 873         rqfpr = class;
 874         ftp_rqfcr[rqfar] = rqfcr;
 875         ftp_rqfpr[rqfar] = rqfpr;
 876         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 877
 878         return rqfar;
 879 }
 880
 881 static void gfar_init_filer_table(struct gfar_private *priv)
 882 {
 883         int i = 0x0;
 884         u32 rqfar = MAX_FILER_IDX;
 885         u32 rqfcr = 0x0;
 886         u32 rqfpr = FPR_FILER_MASK;
 887
 888         /* Default rule */
 889         rqfcr = RQFCR_CMP_MATCH;
 890         ftp_rqfcr[rqfar] = rqfcr;
 891         ftp_rqfpr[rqfar] = rqfpr;
 892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 893
 894         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 895         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 896         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 897         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 898         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 899         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 900
 901         /* cur_filer_idx indicated the fisrt non-masked rule */
 902         priv->cur_filer_idx = rqfar;
 903
 904         /* Rest are masked rules */
 905         rqfcr = RQFCR_CMP_NOMATCH;
 906         for (i = 0; i < rqfar; i++) {
 907                 ftp_rqfcr[i] = rqfcr;
 908                 ftp_rqfpr[i] = rqfpr;
 909                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 910         }
 911 }
 912
 913 /* Set up the ethernet device structure, private data,
 914  * and anything else we need before we start */
 915 static int gfar_probe(struct of_device *ofdev,
 916                 const struct of_device_id *match)
 917 {
 918         u32 tempval;
 919         struct net_device *dev = NULL;
 920         struct gfar_private *priv = NULL;
 921         struct gfar __iomem *regs = NULL;
 922         int err = 0, i, grp_idx = 0;
 923         int len_devname;
 924         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 925         u32 isrg = 0;
 926         u32 __iomem *baddr;
 927
 928         err = gfar_of_init(ofdev, &dev);
 929
 930         if (err)
 931                 return err;
 932
 933         priv = netdev_priv(dev);
 934         priv->ndev = dev;
 935         priv->ofdev = ofdev;
 936         priv->node = ofdev->node;
 937         SET_NETDEV_DEV(dev, &ofdev->dev);
 938
 939         spin_lock_init(&priv->bflock);
 940         INIT_WORK(&priv->reset_task, gfar_reset_task);
 941
 942         dev_set_drvdata(&ofdev->dev, priv);
 943         regs = priv->gfargrp[0].regs;
 944
 945         /* Stop the DMA engine now, in case it was running before */
 946         /* (The firmware could have used it, and left it running). */
 947         gfar_halt(dev);
 948
 949         /* Reset MAC layer */
 950         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
 951
 952         /* We need to delay at least 3 TX clocks */
 953         udelay(2);
 954
 955         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 956         gfar_write(&regs->maccfg1, tempval);
 957
 958         /* Initialize MACCFG2. */
 959         gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
 960
 961         /* Initialize ECNTRL */
 962         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
 963
 964         /* Set the dev->base_addr to the gfar reg region */
 965         dev->base_addr = (unsigned long) regs;
 966
 967         SET_NETDEV_DEV(dev, &ofdev->dev);
 968
 969         /* Fill in the dev structure */
 970         dev->watchdog_timeo = TX_TIMEOUT;
 971         dev->mtu = 1500;
 972         dev->netdev_ops = &gfar_netdev_ops;
 973         dev->ethtool_ops = &gfar_ethtool_ops;
 974
 975         /* Register for napi ...We are registering NAPI for each grp */
 976         for (i = 0; i < priv->num_grps; i++)
 977                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
 978
 979         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 980                 priv->rx_csum_enable = 1;
 981                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
 982         } else
 983                 priv->rx_csum_enable = 0;
 984
 985         priv->vlgrp = NULL;
 986
 987         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
 988                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 989
 990         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 991                 priv->extended_hash = 1;
 992                 priv->hash_width = 9;
 993
 994                 priv->hash_regs[0] = &regs->igaddr0;
 995                 priv->hash_regs[1] = &regs->igaddr1;
 996                 priv->hash_regs[2] = &regs->igaddr2;
 997                 priv->hash_regs[3] = &regs->igaddr3;
 998                 priv->hash_regs[4] = &regs->igaddr4;
 999                 priv->hash_regs[5] = &regs->igaddr5;
1000                 priv->hash_regs[6] = &regs->igaddr6;
1001                 priv->hash_regs[7] = &regs->igaddr7;
1002                 priv->hash_regs[8] = &regs->gaddr0;
1003                 priv->hash_regs[9] = &regs->gaddr1;
1004                 priv->hash_regs[10] = &regs->gaddr2;
1005                 priv->hash_regs[11] = &regs->gaddr3;
1006                 priv->hash_regs[12] = &regs->gaddr4;
1007                 priv->hash_regs[13] = &regs->gaddr5;
1008                 priv->hash_regs[14] = &regs->gaddr6;
1009                 priv->hash_regs[15] = &regs->gaddr7;
1010
1011         } else {
1012                 priv->extended_hash = 0;
1013                 priv->hash_width = 8;
1014
1015                 priv->hash_regs[0] = &regs->gaddr0;
1016                 priv->hash_regs[1] = &regs->gaddr1;
1017                 priv->hash_regs[2] = &regs->gaddr2;
1018                 priv->hash_regs[3] = &regs->gaddr3;
1019                 priv->hash_regs[4] = &regs->gaddr4;
1020                 priv->hash_regs[5] = &regs->gaddr5;
1021                 priv->hash_regs[6] = &regs->gaddr6;
1022                 priv->hash_regs[7] = &regs->gaddr7;
1023         }
1024
1025         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1026                 priv->padding = DEFAULT_PADDING;
1027         else
1028                 priv->padding = 0;
1029
1030         if (dev->features & NETIF_F_IP_CSUM ||
1031                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1032                 dev->hard_header_len += GMAC_FCB_LEN;
1033
1034         /* Program the isrg regs only if number of grps > 1 */
1035         if (priv->num_grps > 1) {
1036                 baddr = &regs->isrg0;
1037                 for (i = 0; i < priv->num_grps; i++) {
1038                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1039                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1040                         gfar_write(baddr, isrg);
1041                         baddr++;
1042                         isrg = 0x0;
1043                 }
1044         }
1045
1046         /* Need to reverse the bit maps as  bit_map's MSB is q0
1047          * but, for_each_set_bit parses from right to left, which
1048          * basically reverses the queue numbers */
1049         for (i = 0; i< priv->num_grps; i++) {
1050                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1051                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1052                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1053                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1054         }
1055
1056         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1057          * also assign queues to groups */
1058         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1059                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1060                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1061                                 priv->num_rx_queues) {
1062                         priv->gfargrp[grp_idx].num_rx_queues++;
1063                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1064                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1065                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1066                 }
1067                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1068                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1069                                 priv->num_tx_queues) {
1070                         priv->gfargrp[grp_idx].num_tx_queues++;
1071                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1072                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1073                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1074                 }
1075                 priv->gfargrp[grp_idx].rstat = rstat;
1076                 priv->gfargrp[grp_idx].tstat = tstat;
1077                 rstat = tstat =0;
1078         }
1079
1080         gfar_write(&regs->rqueue, rqueue);
1081         gfar_write(&regs->tqueue, tqueue);
1082
1083         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1084
1085         /* Initializing some of the rx/tx queue level parameters */
1086         for (i = 0; i < priv->num_tx_queues; i++) {
1087                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1088                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1089                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1090                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1091         }
1092
1093         for (i = 0; i < priv->num_rx_queues; i++) {
1094                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1095                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1096                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1097         }
1098
1099         /* enable filer if using multiple RX queues*/
1100         if(priv->num_rx_queues > 1)
1101                 priv->rx_filer_enable = 1;
1102         /* Enable most messages by default */
1103         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1104
1105         /* Carrier starts down, phylib will bring it up */
1106         netif_carrier_off(dev);
1107
1108         err = register_netdev(dev);
1109
1110         if (err) {
1111                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1112                                 dev->name);
1113                 goto register_fail;
1114         }
1115
1116         device_init_wakeup(&dev->dev,
1117                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1118
1119         /* fill out IRQ number and name fields */
1120         len_devname = strlen(dev->name);
1121         for (i = 0; i < priv->num_grps; i++) {
1122                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1123                                 len_devname);
1124                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1125                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1126                                 "_g", sizeof("_g"));
1127                         priv->gfargrp[i].int_name_tx[
1128                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1129                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1130                                 priv->gfargrp[i].int_name_tx)],
1131                                 "_tx", sizeof("_tx") + 1);
1132
1133                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1134                                         len_devname);
1135                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1136                                         "_g", sizeof("_g"));
1137                         priv->gfargrp[i].int_name_rx[
1138                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1139                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1140                                 priv->gfargrp[i].int_name_rx)],
1141                                 "_rx", sizeof("_rx") + 1);
1142
1143                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1144                                         len_devname);
1145                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1146                                 "_g", sizeof("_g"));
1147                         priv->gfargrp[i].int_name_er[strlen(
1148                                         priv->gfargrp[i].int_name_er)] = i+48;
1149                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1150                                 priv->gfargrp[i].int_name_er)],
1151                                 "_er", sizeof("_er") + 1);
1152                 } else
1153                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1154         }
1155
1156         /* Initialize the filer table */
1157         gfar_init_filer_table(priv);
1158
1159         /* Create all the sysfs files */
1160         gfar_init_sysfs(dev);
1161
1162         /* Print out the device info */
1163         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1164
1165         /* Even more device info helps when determining which kernel */
1166         /* provided which set of benchmarks. */
1167         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1168         for (i = 0; i < priv->num_rx_queues; i++)
1169                 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
1170                         dev->name, i, priv->rx_queue[i]->rx_ring_size);
1171         for(i = 0; i < priv->num_tx_queues; i++)
1172                  printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
1173                         dev->name, i, priv->tx_queue[i]->tx_ring_size);
1174
1175         return 0;
1176
1177 register_fail:
1178         unmap_group_regs(priv);
1179         free_tx_pointers(priv);
1180         free_rx_pointers(priv);
1181         if (priv->phy_node)
1182                 of_node_put(priv->phy_node);
1183         if (priv->tbi_node)
1184                 of_node_put(priv->tbi_node);
1185         free_netdev(dev);
1186         return err;
1187 }
1188
1189 static int gfar_remove(struct of_device *ofdev)
1190 {
1191         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1192
1193         if (priv->phy_node)
1194                 of_node_put(priv->phy_node);
1195         if (priv->tbi_node)
1196                 of_node_put(priv->tbi_node);
1197
1198         dev_set_drvdata(&ofdev->dev, NULL);
1199
1200         unregister_netdev(priv->ndev);
1201         unmap_group_regs(priv);
1202         free_netdev(priv->ndev);
1203
1204         return 0;
1205 }
1206
1207 #ifdef CONFIG_PM
1208
1209 static int gfar_suspend(struct device *dev)
1210 {
1211         struct gfar_private *priv = dev_get_drvdata(dev);
1212         struct net_device *ndev = priv->ndev;
1213         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1214         unsigned long flags;
1215         u32 tempval;
1216
1217         int magic_packet = priv->wol_en &&
1218                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1219
1220         netif_device_detach(ndev);
1221
1222         if (netif_running(ndev)) {
1223
1224                 local_irq_save(flags);
1225                 lock_tx_qs(priv);
1226                 lock_rx_qs(priv);
1227
1228                 gfar_halt_nodisable(ndev);
1229
1230                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1231                 tempval = gfar_read(&regs->maccfg1);
1232
1233                 tempval &= ~MACCFG1_TX_EN;
1234
1235                 if (!magic_packet)
1236                         tempval &= ~MACCFG1_RX_EN;
1237
1238                 gfar_write(&regs->maccfg1, tempval);
1239
1240                 unlock_rx_qs(priv);
1241                 unlock_tx_qs(priv);
1242                 local_irq_restore(flags);
1243
1244                 disable_napi(priv);
1245
1246                 if (magic_packet) {
1247                         /* Enable interrupt on Magic Packet */
1248                         gfar_write(&regs->imask, IMASK_MAG);
1249
1250                         /* Enable Magic Packet mode */
1251                         tempval = gfar_read(&regs->maccfg2);
1252                         tempval |= MACCFG2_MPEN;
1253                         gfar_write(&regs->maccfg2, tempval);
1254                 } else {
1255                         phy_stop(priv->phydev);
1256                 }
1257         }
1258
1259         return 0;
1260 }
1261
1262 static int gfar_resume(struct device *dev)
1263 {
1264         struct gfar_private *priv = dev_get_drvdata(dev);
1265         struct net_device *ndev = priv->ndev;
1266         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1267         unsigned long flags;
1268         u32 tempval;
1269         int magic_packet = priv->wol_en &&
1270                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1271
1272         if (!netif_running(ndev)) {
1273                 netif_device_attach(ndev);
1274                 return 0;
1275         }
1276
1277         if (!magic_packet && priv->phydev)
1278                 phy_start(priv->phydev);
1279
1280         /* Disable Magic Packet mode, in case something
1281          * else woke us up.
1282          */
1283         local_irq_save(flags);
1284         lock_tx_qs(priv);
1285         lock_rx_qs(priv);
1286
1287         tempval = gfar_read(&regs->maccfg2);
1288         tempval &= ~MACCFG2_MPEN;
1289         gfar_write(&regs->maccfg2, tempval);
1290
1291         gfar_start(ndev);
1292
1293         unlock_rx_qs(priv);
1294         unlock_tx_qs(priv);
1295         local_irq_restore(flags);
1296
1297         netif_device_attach(ndev);
1298
1299         enable_napi(priv);
1300
1301         return 0;
1302 }
1303
1304 static int gfar_restore(struct device *dev)
1305 {
1306         struct gfar_private *priv = dev_get_drvdata(dev);
1307         struct net_device *ndev = priv->ndev;
1308
1309         if (!netif_running(ndev))
1310                 return 0;
1311
1312         gfar_init_bds(ndev);
1313         init_registers(ndev);
1314         gfar_set_mac_address(ndev);
1315         gfar_init_mac(ndev);
1316         gfar_start(ndev);
1317
1318         priv->oldlink = 0;
1319         priv->oldspeed = 0;
1320         priv->oldduplex = -1;
1321
1322         if (priv->phydev)
1323                 phy_start(priv->phydev);
1324
1325         netif_device_attach(ndev);
1326         enable_napi(priv);
1327
1328         return 0;
1329 }
1330
1331 static struct dev_pm_ops gfar_pm_ops = {
1332         .suspend = gfar_suspend,
1333         .resume = gfar_resume,
1334         .freeze = gfar_suspend,
1335         .thaw = gfar_resume,
1336         .restore = gfar_restore,
1337 };
1338
1339 #define GFAR_PM_OPS (&gfar_pm_ops)
1340
1341 static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
1342 {
1343         return gfar_suspend(&ofdev->dev);
1344 }
1345
1346 static int gfar_legacy_resume(struct of_device *ofdev)
1347 {
1348         return gfar_resume(&ofdev->dev);
1349 }
1350
1351 #else
1352
1353 #define GFAR_PM_OPS NULL
1354 #define gfar_legacy_suspend NULL
1355 #define gfar_legacy_resume NULL
1356
1357 #endif
1358
1359 /* Reads the controller's registers to determine what interface
1360  * connects it to the PHY.
1361  */
1362 static phy_interface_t gfar_get_interface(struct net_device *dev)
1363 {
1364         struct gfar_private *priv = netdev_priv(dev);
1365         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1366         u32 ecntrl;
1367
1368         ecntrl = gfar_read(&regs->ecntrl);
1369
1370         if (ecntrl & ECNTRL_SGMII_MODE)
1371                 return PHY_INTERFACE_MODE_SGMII;
1372
1373         if (ecntrl & ECNTRL_TBI_MODE) {
1374                 if (ecntrl & ECNTRL_REDUCED_MODE)
1375                         return PHY_INTERFACE_MODE_RTBI;
1376                 else
1377                         return PHY_INTERFACE_MODE_TBI;
1378         }
1379
1380         if (ecntrl & ECNTRL_REDUCED_MODE) {
1381                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1382                         return PHY_INTERFACE_MODE_RMII;
1383                 else {
1384                         phy_interface_t interface = priv->interface;
1385
1386                         /*
1387                          * This isn't autodetected right now, so it must
1388                          * be set by the device tree or platform code.
1389                          */
1390                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1391                                 return PHY_INTERFACE_MODE_RGMII_ID;
1392
1393                         return PHY_INTERFACE_MODE_RGMII;
1394                 }
1395         }
1396
1397         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1398                 return PHY_INTERFACE_MODE_GMII;
1399
1400         return PHY_INTERFACE_MODE_MII;
1401 }
1402
1403
1404 /* Initializes driver's PHY state, and attaches to the PHY.
1405  * Returns 0 on success.
1406  */
1407 static int init_phy(struct net_device *dev)
1408 {
1409         struct gfar_private *priv = netdev_priv(dev);
1410         uint gigabit_support =
1411                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1412                 SUPPORTED_1000baseT_Full : 0;
1413         phy_interface_t interface;
1414
1415         priv->oldlink = 0;
1416         priv->oldspeed = 0;
1417         priv->oldduplex = -1;
1418
1419         interface = gfar_get_interface(dev);
1420
1421         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1422                                       interface);
1423         if (!priv->phydev)
1424                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1425                                                          interface);
1426         if (!priv->phydev) {
1427                 dev_err(&dev->dev, "could not attach to PHY\n");
1428                 return -ENODEV;
1429         }
1430
1431         if (interface == PHY_INTERFACE_MODE_SGMII)
1432                 gfar_configure_serdes(dev);
1433
1434         /* Remove any features not supported by the controller */
1435         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1436         priv->phydev->advertising = priv->phydev->supported;
1437
1438         return 0;
1439 }
1440
1441 /*
1442  * Initialize TBI PHY interface for communicating with the
1443  * SERDES lynx PHY on the chip.  We communicate with this PHY
1444  * through the MDIO bus on each controller, treating it as a
1445  * "normal" PHY at the address found in the TBIPA register.  We assume
1446  * that the TBIPA register is valid.  Either the MDIO bus code will set
1447  * it to a value that doesn't conflict with other PHYs on the bus, or the
1448  * value doesn't matter, as there are no other PHYs on the bus.
1449  */
1450 static void gfar_configure_serdes(struct net_device *dev)
1451 {
1452         struct gfar_private *priv = netdev_priv(dev);
1453         struct phy_device *tbiphy;
1454
1455         if (!priv->tbi_node) {
1456                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1457                                     "device tree specify a tbi-handle\n");
1458                 return;
1459         }
1460
1461         tbiphy = of_phy_find_device(priv->tbi_node);
1462         if (!tbiphy) {
1463                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1464                 return;
1465         }
1466
1467         /*
1468          * If the link is already up, we must already be ok, and don't need to
1469          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1470          * everything for us?  Resetting it takes the link down and requires
1471          * several seconds for it to come back.
1472          */
1473         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1474                 return;
1475
1476         /* Single clk mode, mii mode off(for serdes communication) */
1477         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1478
1479         phy_write(tbiphy, MII_ADVERTISE,
1480                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1481                         ADVERTISE_1000XPSE_ASYM);
1482
1483         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1484                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1485 }
1486
1487 static void init_registers(struct net_device *dev)
1488 {
1489         struct gfar_private *priv = netdev_priv(dev);
1490         struct gfar __iomem *regs = NULL;
1491         int i = 0;
1492
1493         for (i = 0; i < priv->num_grps; i++) {
1494                 regs = priv->gfargrp[i].regs;
1495                 /* Clear IEVENT */
1496                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1497
1498                 /* Initialize IMASK */
1499                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1500         }
1501
1502         regs = priv->gfargrp[0].regs;
1503         /* Init hash registers to zero */
1504         gfar_write(&regs->igaddr0, 0);
1505         gfar_write(&regs->igaddr1, 0);
1506         gfar_write(&regs->igaddr2, 0);
1507         gfar_write(&regs->igaddr3, 0);
1508         gfar_write(&regs->igaddr4, 0);
1509         gfar_write(&regs->igaddr5, 0);
1510         gfar_write(&regs->igaddr6, 0);
1511         gfar_write(&regs->igaddr7, 0);
1512
1513         gfar_write(&regs->gaddr0, 0);
1514         gfar_write(&regs->gaddr1, 0);
1515         gfar_write(&regs->gaddr2, 0);
1516         gfar_write(&regs->gaddr3, 0);
1517         gfar_write(&regs->gaddr4, 0);
1518         gfar_write(&regs->gaddr5, 0);
1519         gfar_write(&regs->gaddr6, 0);
1520         gfar_write(&regs->gaddr7, 0);
1521
1522         /* Zero out the rmon mib registers if it has them */
1523         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1524                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1525
1526                 /* Mask off the CAM interrupts */
1527                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1528                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1529         }
1530
1531         /* Initialize the max receive buffer length */
1532         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1533
1534         /* Initialize the Minimum Frame Length Register */
1535         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1536 }
1537
1538
1539 /* Halt the receive and transmit queues */
1540 static void gfar_halt_nodisable(struct net_device *dev)
1541 {
1542         struct gfar_private *priv = netdev_priv(dev);
1543         struct gfar __iomem *regs = NULL;
1544         u32 tempval;
1545         int i = 0;
1546
1547         for (i = 0; i < priv->num_grps; i++) {
1548                 regs = priv->gfargrp[i].regs;
1549                 /* Mask all interrupts */
1550                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1551
1552                 /* Clear all interrupts */
1553                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1554         }
1555
1556         regs = priv->gfargrp[0].regs;
1557         /* Stop the DMA, and wait for it to stop */
1558         tempval = gfar_read(&regs->dmactrl);
1559         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1560             != (DMACTRL_GRS | DMACTRL_GTS)) {
1561                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1562                 gfar_write(&regs->dmactrl, tempval);
1563
1564                 while (!(gfar_read(&regs->ievent) &
1565                          (IEVENT_GRSC | IEVENT_GTSC)))
1566                         cpu_relax();
1567         }
1568 }
1569
1570 /* Halt the receive and transmit queues */
1571 void gfar_halt(struct net_device *dev)
1572 {
1573         struct gfar_private *priv = netdev_priv(dev);
1574         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1575         u32 tempval;
1576
1577         gfar_halt_nodisable(dev);
1578
1579         /* Disable Rx and Tx */
1580         tempval = gfar_read(&regs->maccfg1);
1581         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1582         gfar_write(&regs->maccfg1, tempval);
1583 }
1584
1585 static void free_grp_irqs(struct gfar_priv_grp *grp)
1586 {
1587         free_irq(grp->interruptError, grp);
1588         free_irq(grp->interruptTransmit, grp);
1589         free_irq(grp->interruptReceive, grp);
1590 }
1591
1592 void stop_gfar(struct net_device *dev)
1593 {
1594         struct gfar_private *priv = netdev_priv(dev);
1595         unsigned long flags;
1596         int i;
1597
1598         phy_stop(priv->phydev);
1599
1600
1601         /* Lock it down */
1602         local_irq_save(flags);
1603         lock_tx_qs(priv);
1604         lock_rx_qs(priv);
1605
1606         gfar_halt(dev);
1607
1608         unlock_rx_qs(priv);
1609         unlock_tx_qs(priv);
1610         local_irq_restore(flags);
1611
1612         /* Free the IRQs */
1613         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1614                 for (i = 0; i < priv->num_grps; i++)
1615                         free_grp_irqs(&priv->gfargrp[i]);
1616         } else {
1617                 for (i = 0; i < priv->num_grps; i++)
1618                         free_irq(priv->gfargrp[i].interruptTransmit,
1619                                         &priv->gfargrp[i]);
1620         }
1621
1622         free_skb_resources(priv);
1623 }
1624
1625 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1626 {
1627         struct txbd8 *txbdp;
1628         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1629         int i, j;
1630
1631         txbdp = tx_queue->tx_bd_base;
1632
1633         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1634                 if (!tx_queue->tx_skbuff[i])
1635                         continue;
1636
1637                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1638                                 txbdp->length, DMA_TO_DEVICE);
1639                 txbdp->lstatus = 0;
1640                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1641                                 j++) {
1642                         txbdp++;
1643                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1644                                         txbdp->length, DMA_TO_DEVICE);
1645                 }
1646                 txbdp++;
1647                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1648                 tx_queue->tx_skbuff[i] = NULL;
1649         }
1650         kfree(tx_queue->tx_skbuff);
1651 }
1652
1653 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1654 {
1655         struct rxbd8 *rxbdp;
1656         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1657         int i;
1658
1659         rxbdp = rx_queue->rx_bd_base;
1660
1661         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1662                 if (rx_queue->rx_skbuff[i]) {
1663                         dma_unmap_single(&priv->ofdev->dev,
1664                                         rxbdp->bufPtr, priv->rx_buffer_size,
1665                                         DMA_FROM_DEVICE);
1666                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1667                         rx_queue->rx_skbuff[i] = NULL;
1668                 }
1669                 rxbdp->lstatus = 0;
1670                 rxbdp->bufPtr = 0;
1671                 rxbdp++;
1672         }
1673         kfree(rx_queue->rx_skbuff);
1674 }
1675
1676 /* If there are any tx skbs or rx skbs still around, free them.
1677  * Then free tx_skbuff and rx_skbuff */
1678 static void free_skb_resources(struct gfar_private *priv)
1679 {
1680         struct gfar_priv_tx_q *tx_queue = NULL;
1681         struct gfar_priv_rx_q *rx_queue = NULL;
1682         int i;
1683
1684         /* Go through all the buffer descriptors and free their data buffers */
1685         for (i = 0; i < priv->num_tx_queues; i++) {
1686                 tx_queue = priv->tx_queue[i];
1687                 if(tx_queue->tx_skbuff)
1688                         free_skb_tx_queue(tx_queue);
1689         }
1690
1691         for (i = 0; i < priv->num_rx_queues; i++) {
1692                 rx_queue = priv->rx_queue[i];
1693                 if(rx_queue->rx_skbuff)
1694                         free_skb_rx_queue(rx_queue);
1695         }
1696
1697         dma_free_coherent(&priv->ofdev->dev,
1698                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1699                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1700                         priv->tx_queue[0]->tx_bd_base,
1701                         priv->tx_queue[0]->tx_bd_dma_base);
1702 }
1703
1704 void gfar_start(struct net_device *dev)
1705 {
1706         struct gfar_private *priv = netdev_priv(dev);
1707         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1708         u32 tempval;
1709         int i = 0;
1710
1711         /* Enable Rx and Tx in MACCFG1 */
1712         tempval = gfar_read(&regs->maccfg1);
1713         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1714         gfar_write(&regs->maccfg1, tempval);
1715
1716         /* Initialize DMACTRL to have WWR and WOP */
1717         tempval = gfar_read(&regs->dmactrl);
1718         tempval |= DMACTRL_INIT_SETTINGS;
1719         gfar_write(&regs->dmactrl, tempval);
1720
1721         /* Make sure we aren't stopped */
1722         tempval = gfar_read(&regs->dmactrl);
1723         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1724         gfar_write(&regs->dmactrl, tempval);
1725
1726         for (i = 0; i < priv->num_grps; i++) {
1727                 regs = priv->gfargrp[i].regs;
1728                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1729                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1730                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1731                 /* Unmask the interrupts we look for */
1732                 gfar_write(&regs->imask, IMASK_DEFAULT);
1733         }
1734
1735         dev->trans_start = jiffies;
1736 }
1737
1738 void gfar_configure_coalescing(struct gfar_private *priv,
1739         unsigned long tx_mask, unsigned long rx_mask)
1740 {
1741         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1742         u32 __iomem *baddr;
1743         int i = 0;
1744
1745         /* Backward compatible case ---- even if we enable
1746          * multiple queues, there's only single reg to program
1747          */
1748         gfar_write(&regs->txic, 0);
1749         if(likely(priv->tx_queue[0]->txcoalescing))
1750                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1751
1752         gfar_write(&regs->rxic, 0);
1753         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1754                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1755
1756         if (priv->mode == MQ_MG_MODE) {
1757                 baddr = &regs->txic0;
1758                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1759                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1760                                 gfar_write(baddr + i, 0);
1761                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1762                         }
1763                 }
1764
1765                 baddr = &regs->rxic0;
1766                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1767                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1768                                 gfar_write(baddr + i, 0);
1769                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1770                         }
1771                 }
1772         }
1773 }
1774
1775 static int register_grp_irqs(struct gfar_priv_grp *grp)
1776 {
1777         struct gfar_private *priv = grp->priv;
1778         struct net_device *dev = priv->ndev;
1779         int err;
1780
1781         /* If the device has multiple interrupts, register for
1782          * them.  Otherwise, only register for the one */
1783         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1784                 /* Install our interrupt handlers for Error,
1785                  * Transmit, and Receive */
1786                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1787                                 grp->int_name_er,grp)) < 0) {
1788                         if (netif_msg_intr(priv))
1789                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1790                                         dev->name, grp->interruptError);
1791
1792                                 goto err_irq_fail;
1793                 }
1794
1795                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1796                                 0, grp->int_name_tx, grp)) < 0) {
1797                         if (netif_msg_intr(priv))
1798                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1799                                         dev->name, grp->interruptTransmit);
1800                         goto tx_irq_fail;
1801                 }
1802
1803                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1804                                 grp->int_name_rx, grp)) < 0) {
1805                         if (netif_msg_intr(priv))
1806                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1807                                         dev->name, grp->interruptReceive);
1808                         goto rx_irq_fail;
1809                 }
1810         } else {
1811                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1812                                 grp->int_name_tx, grp)) < 0) {
1813                         if (netif_msg_intr(priv))
1814                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1815                                         dev->name, grp->interruptTransmit);
1816                         goto err_irq_fail;
1817                 }
1818         }
1819
1820         return 0;
1821
1822 rx_irq_fail:
1823         free_irq(grp->interruptTransmit, grp);
1824 tx_irq_fail:
1825         free_irq(grp->interruptError, grp);
1826 err_irq_fail:
1827         return err;
1828
1829 }
1830
1831 /* Bring the controller up and running */
1832 int startup_gfar(struct net_device *ndev)
1833 {
1834         struct gfar_private *priv = netdev_priv(ndev);
1835         struct gfar __iomem *regs = NULL;
1836         int err, i, j;
1837
1838         for (i = 0; i < priv->num_grps; i++) {
1839                 regs= priv->gfargrp[i].regs;
1840                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1841         }
1842
1843         regs= priv->gfargrp[0].regs;
1844         err = gfar_alloc_skb_resources(ndev);
1845         if (err)
1846                 return err;
1847
1848         gfar_init_mac(ndev);
1849
1850         for (i = 0; i < priv->num_grps; i++) {
1851                 err = register_grp_irqs(&priv->gfargrp[i]);
1852                 if (err) {
1853                         for (j = 0; j < i; j++)
1854                                 free_grp_irqs(&priv->gfargrp[j]);
1855                                 goto irq_fail;
1856                 }
1857         }
1858
1859         /* Start the controller */
1860         gfar_start(ndev);
1861
1862         phy_start(priv->phydev);
1863
1864         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1865
1866         return 0;
1867
1868 irq_fail:
1869         free_skb_resources(priv);
1870         return err;
1871 }
1872
1873 /* Called when something needs to use the ethernet device */
1874 /* Returns 0 for success. */
1875 static int gfar_enet_open(struct net_device *dev)
1876 {
1877         struct gfar_private *priv = netdev_priv(dev);
1878         int err;
1879
1880         enable_napi(priv);
1881
1882         skb_queue_head_init(&priv->rx_recycle);
1883
1884         /* Initialize a bunch of registers */
1885         init_registers(dev);
1886
1887         gfar_set_mac_address(dev);
1888
1889         err = init_phy(dev);
1890
1891         if (err) {
1892                 disable_napi(priv);
1893                 return err;
1894         }
1895
1896         err = startup_gfar(dev);
1897         if (err) {
1898                 disable_napi(priv);
1899                 return err;
1900         }
1901
1902         netif_tx_start_all_queues(dev);
1903
1904         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1905
1906         return err;
1907 }
1908
1909 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1910 {
1911         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1912
1913         memset(fcb, 0, GMAC_FCB_LEN);
1914
1915         return fcb;
1916 }
1917
1918 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1919 {
1920         u8 flags = 0;
1921
1922         /* If we're here, it's a IP packet with a TCP or UDP
1923          * payload.  We set it to checksum, using a pseudo-header
1924          * we provide
1925          */
1926         flags = TXFCB_DEFAULT;
1927
1928         /* Tell the controller what the protocol is */
1929         /* And provide the already calculated phcs */
1930         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1931                 flags |= TXFCB_UDP;
1932                 fcb->phcs = udp_hdr(skb)->check;
1933         } else
1934                 fcb->phcs = tcp_hdr(skb)->check;
1935
1936         /* l3os is the distance between the start of the
1937          * frame (skb->data) and the start of the IP hdr.
1938          * l4os is the distance between the start of the
1939          * l3 hdr and the l4 hdr */
1940         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1941         fcb->l4os = skb_network_header_len(skb);
1942
1943         fcb->flags = flags;
1944 }
1945
1946 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1947 {
1948         fcb->flags |= TXFCB_VLN;
1949         fcb->vlctl = vlan_tx_tag_get(skb);
1950 }
1951
1952 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1953                                struct txbd8 *base, int ring_size)
1954 {
1955         struct txbd8 *new_bd = bdp + stride;
1956
1957         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1958 }
1959
1960 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1961                 int ring_size)
1962 {
1963         return skip_txbd(bdp, 1, base, ring_size);
1964 }
1965
1966 /* This is called by the kernel when a frame is ready for transmission. */
1967 /* It is pointed to by the dev->hard_start_xmit function pointer */
1968 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1969 {
1970         struct gfar_private *priv = netdev_priv(dev);
1971         struct gfar_priv_tx_q *tx_queue = NULL;
1972         struct netdev_queue *txq;
1973         struct gfar __iomem *regs = NULL;
1974         struct txfcb *fcb = NULL;
1975         struct txbd8 *txbdp, *txbdp_start, *base;
1976         u32 lstatus;
1977         int i, rq = 0;
1978         u32 bufaddr;
1979         unsigned long flags;
1980         unsigned int nr_frags, length;
1981
1982
1983         rq = skb->queue_mapping;
1984         tx_queue = priv->tx_queue[rq];
1985         txq = netdev_get_tx_queue(dev, rq);
1986         base = tx_queue->tx_bd_base;
1987         regs = tx_queue->grp->regs;
1988
1989         /* make space for additional header when fcb is needed */
1990         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1991                         (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1992                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1993                 struct sk_buff *skb_new;
1994
1995                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1996                 if (!skb_new) {
1997                         dev->stats.tx_errors++;
1998                         kfree_skb(skb);
1999                         return NETDEV_TX_OK;
2000                 }
2001                 kfree_skb(skb);
2002                 skb = skb_new;
2003         }
2004
2005         /* total number of fragments in the SKB */
2006         nr_frags = skb_shinfo(skb)->nr_frags;
2007
2008         /* check if there is space to queue this packet */
2009         if ((nr_frags+1) > tx_queue->num_txbdfree) {
2010                 /* no space, stop the queue */
2011                 netif_tx_stop_queue(txq);
2012                 dev->stats.tx_fifo_errors++;
2013                 return NETDEV_TX_BUSY;
2014         }
2015
2016         /* Update transmit stats */
2017         txq->tx_bytes += skb->len;
2018         txq->tx_packets ++;
2019
2020         txbdp = txbdp_start = tx_queue->cur_tx;
2021
2022         if (nr_frags == 0) {
2023                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2024         } else {
2025                 /* Place the fragment addresses and lengths into the TxBDs */
2026                 for (i = 0; i < nr_frags; i++) {
2027                         /* Point at the next BD, wrapping as needed */
2028                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2029
2030                         length = skb_shinfo(skb)->frags[i].size;
2031
2032                         lstatus = txbdp->lstatus | length |
2033                                 BD_LFLAG(TXBD_READY);
2034
2035                         /* Handle the last BD specially */
2036                         if (i == nr_frags - 1)
2037                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2038
2039                         bufaddr = dma_map_page(&priv->ofdev->dev,
2040                                         skb_shinfo(skb)->frags[i].page,
2041                                         skb_shinfo(skb)->frags[i].page_offset,
2042                                         length,
2043                                         DMA_TO_DEVICE);
2044
2045                         /* set the TxBD length and buffer pointer */
2046                         txbdp->bufPtr = bufaddr;
2047                         txbdp->lstatus = lstatus;
2048                 }
2049
2050                 lstatus = txbdp_start->lstatus;
2051         }
2052
2053         /* Set up checksumming */
2054         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2055                 fcb = gfar_add_fcb(skb);
2056                 lstatus |= BD_LFLAG(TXBD_TOE);
2057                 gfar_tx_checksum(skb, fcb);
2058         }
2059
2060         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
2061                 if (unlikely(NULL == fcb)) {
2062                         fcb = gfar_add_fcb(skb);
2063                         lstatus |= BD_LFLAG(TXBD_TOE);
2064                 }
2065
2066                 gfar_tx_vlan(skb, fcb);
2067         }
2068
2069         /* setup the TxBD length and buffer pointer for the first BD */
2070         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2071                         skb_headlen(skb), DMA_TO_DEVICE);
2072
2073         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2074
2075         /*
2076          * We can work in parallel with gfar_clean_tx_ring(), except
2077          * when modifying num_txbdfree. Note that we didn't grab the lock
2078          * when we were reading the num_txbdfree and checking for available
2079          * space, that's because outside of this function it can only grow,
2080          * and once we've got needed space, it cannot suddenly disappear.
2081          *
2082          * The lock also protects us from gfar_error(), which can modify
2083          * regs->tstat and thus retrigger the transfers, which is why we
2084          * also must grab the lock before setting ready bit for the first
2085          * to be transmitted BD.
2086          */
2087         spin_lock_irqsave(&tx_queue->txlock, flags);
2088
2089         /*
2090          * The powerpc-specific eieio() is used, as wmb() has too strong
2091          * semantics (it requires synchronization between cacheable and
2092          * uncacheable mappings, which eieio doesn't provide and which we
2093          * don't need), thus requiring a more expensive sync instruction.  At
2094          * some point, the set of architecture-independent barrier functions
2095          * should be expanded to include weaker barriers.
2096          */
2097         eieio();
2098
2099         txbdp_start->lstatus = lstatus;
2100
2101         eieio(); /* force lstatus write before tx_skbuff */
2102
2103         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2104
2105         /* Update the current skb pointer to the next entry we will use
2106          * (wrapping if necessary) */
2107         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2108                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2109
2110         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2111
2112         /* reduce TxBD free count */
2113         tx_queue->num_txbdfree -= (nr_frags + 1);
2114
2115         dev->trans_start = jiffies;
2116
2117         /* If the next BD still needs to be cleaned up, then the bds
2118            are full.  We need to tell the kernel to stop sending us stuff. */
2119         if (!tx_queue->num_txbdfree) {
2120                 netif_tx_stop_queue(txq);
2121
2122                 dev->stats.tx_fifo_errors++;
2123         }
2124
2125         /* Tell the DMA to go go go */
2126         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2127
2128         /* Unlock priv */
2129         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2130
2131         return NETDEV_TX_OK;
2132 }
2133
2134 /* Stops the kernel queue, and halts the controller */
2135 static int gfar_close(struct net_device *dev)
2136 {
2137         struct gfar_private *priv = netdev_priv(dev);
2138
2139         disable_napi(priv);
2140
2141         skb_queue_purge(&priv->rx_recycle);
2142         cancel_work_sync(&priv->reset_task);
2143         stop_gfar(dev);
2144
2145         /* Disconnect from the PHY */
2146         phy_disconnect(priv->phydev);
2147         priv->phydev = NULL;
2148
2149         netif_tx_stop_all_queues(dev);
2150
2151         return 0;
2152 }
2153
2154 /* Changes the mac address if the controller is not running. */
2155 static int gfar_set_mac_address(struct net_device *dev)
2156 {
2157         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2158
2159         return 0;
2160 }
2161
2162
2163 /* Enables and disables VLAN insertion/extraction */
2164 static void gfar_vlan_rx_register(struct net_device *dev,
2165                 struct vlan_group *grp)
2166 {
2167         struct gfar_private *priv = netdev_priv(dev);
2168         struct gfar __iomem *regs = NULL;
2169         unsigned long flags;
2170         u32 tempval;
2171
2172         regs = priv->gfargrp[0].regs;
2173         local_irq_save(flags);
2174         lock_rx_qs(priv);
2175
2176         priv->vlgrp = grp;
2177
2178         if (grp) {
2179                 /* Enable VLAN tag insertion */
2180                 tempval = gfar_read(&regs->tctrl);
2181                 tempval |= TCTRL_VLINS;
2182
2183                 gfar_write(&regs->tctrl, tempval);
2184
2185                 /* Enable VLAN tag extraction */
2186                 tempval = gfar_read(&regs->rctrl);
2187                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2188                 gfar_write(&regs->rctrl, tempval);
2189         } else {
2190                 /* Disable VLAN tag insertion */
2191                 tempval = gfar_read(&regs->tctrl);
2192                 tempval &= ~TCTRL_VLINS;
2193                 gfar_write(&regs->tctrl, tempval);
2194
2195                 /* Disable VLAN tag extraction */
2196                 tempval = gfar_read(&regs->rctrl);
2197                 tempval &= ~RCTRL_VLEX;
2198                 /* If parse is no longer required, then disable parser */
2199                 if (tempval & RCTRL_REQ_PARSER)
2200                         tempval |= RCTRL_PRSDEP_INIT;
2201                 else
2202                         tempval &= ~RCTRL_PRSDEP_INIT;
2203                 gfar_write(&regs->rctrl, tempval);
2204         }
2205
2206         gfar_change_mtu(dev, dev->mtu);
2207
2208         unlock_rx_qs(priv);
2209         local_irq_restore(flags);
2210 }
2211
2212 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2213 {
2214         int tempsize, tempval;
2215         struct gfar_private *priv = netdev_priv(dev);
2216         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2217         int oldsize = priv->rx_buffer_size;
2218         int frame_size = new_mtu + ETH_HLEN;
2219
2220         if (priv->vlgrp)
2221                 frame_size += VLAN_HLEN;
2222
2223         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2224                 if (netif_msg_drv(priv))
2225                         printk(KERN_ERR "%s: Invalid MTU setting\n",
2226                                         dev->name);
2227                 return -EINVAL;
2228         }
2229
2230         if (gfar_uses_fcb(priv))
2231                 frame_size += GMAC_FCB_LEN;
2232
2233         frame_size += priv->padding;
2234
2235         tempsize =
2236             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2237             INCREMENTAL_BUFFER_SIZE;
2238
2239         /* Only stop and start the controller if it isn't already
2240          * stopped, and we changed something */
2241         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2242                 stop_gfar(dev);
2243
2244         priv->rx_buffer_size = tempsize;
2245
2246         dev->mtu = new_mtu;
2247
2248         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2249         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2250
2251         /* If the mtu is larger than the max size for standard
2252          * ethernet frames (ie, a jumbo frame), then set maccfg2
2253          * to allow huge frames, and to check the length */
2254         tempval = gfar_read(&regs->maccfg2);
2255
2256         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2257                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2258         else
2259                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2260
2261         gfar_write(&regs->maccfg2, tempval);
2262
2263         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2264                 startup_gfar(dev);
2265
2266         return 0;
2267 }
2268
2269 /* gfar_reset_task gets scheduled when a packet has not been
2270  * transmitted after a set amount of time.
2271  * For now, assume that clearing out all the structures, and
2272  * starting over will fix the problem.
2273  */
2274 static void gfar_reset_task(struct work_struct *work)
2275 {
2276         struct gfar_private *priv = container_of(work, struct gfar_private,
2277                         reset_task);
2278         struct net_device *dev = priv->ndev;
2279
2280         if (dev->flags & IFF_UP) {
2281                 netif_tx_stop_all_queues(dev);
2282                 stop_gfar(dev);
2283                 startup_gfar(dev);
2284                 netif_tx_start_all_queues(dev);
2285         }
2286
2287         netif_tx_schedule_all(dev);
2288 }
2289
2290 static void gfar_timeout(struct net_device *dev)
2291 {
2292         struct gfar_private *priv = netdev_priv(dev);
2293
2294         dev->stats.tx_errors++;
2295         schedule_work(&priv->reset_task);
2296 }
2297
2298 /* Interrupt Handler for Transmit complete */
2299 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2300 {
2301         struct net_device *dev = tx_queue->dev;
2302         struct gfar_private *priv = netdev_priv(dev);
2303         struct gfar_priv_rx_q *rx_queue = NULL;
2304         struct txbd8 *bdp;
2305         struct txbd8 *lbdp = NULL;
2306         struct txbd8 *base = tx_queue->tx_bd_base;
2307         struct sk_buff *skb;
2308         int skb_dirtytx;
2309         int tx_ring_size = tx_queue->tx_ring_size;
2310         int frags = 0;
2311         int i;
2312         int howmany = 0;
2313         u32 lstatus;
2314
2315         rx_queue = priv->rx_queue[tx_queue->qindex];
2316         bdp = tx_queue->dirty_tx;
2317         skb_dirtytx = tx_queue->skb_dirtytx;
2318
2319         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2320                 unsigned long flags;
2321
2322                 frags = skb_shinfo(skb)->nr_frags;
2323                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
2324
2325                 lstatus = lbdp->lstatus;
2326
2327                 /* Only clean completed frames */
2328                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2329                                 (lstatus & BD_LENGTH_MASK))
2330                         break;
2331
2332                 dma_unmap_single(&priv->ofdev->dev,
2333                                 bdp->bufPtr,
2334                                 bdp->length,
2335                                 DMA_TO_DEVICE);
2336
2337                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2338                 bdp = next_txbd(bdp, base, tx_ring_size);
2339
2340                 for (i = 0; i < frags; i++) {
2341                         dma_unmap_page(&priv->ofdev->dev,
2342                                         bdp->bufPtr,
2343                                         bdp->length,
2344                                         DMA_TO_DEVICE);
2345                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2346                         bdp = next_txbd(bdp, base, tx_ring_size);
2347                 }
2348
2349                 /*
2350                  * If there's room in the queue (limit it to rx_buffer_size)
2351                  * we add this skb back into the pool, if it's the right size
2352                  */
2353                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2354                                 skb_recycle_check(skb, priv->rx_buffer_size +
2355                                         RXBUF_ALIGNMENT))
2356                         __skb_queue_head(&priv->rx_recycle, skb);
2357                 else
2358                         dev_kfree_skb_any(skb);
2359
2360                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2361
2362                 skb_dirtytx = (skb_dirtytx + 1) &
2363                         TX_RING_MOD_MASK(tx_ring_size);
2364
2365                 howmany++;
2366                 spin_lock_irqsave(&tx_queue->txlock, flags);
2367                 tx_queue->num_txbdfree += frags + 1;
2368                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2369         }
2370
2371         /* If we freed a buffer, we can restart transmission, if necessary */
2372         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2373                 netif_wake_subqueue(dev, tx_queue->qindex);
2374
2375         /* Update dirty indicators */
2376         tx_queue->skb_dirtytx = skb_dirtytx;
2377         tx_queue->dirty_tx = bdp;
2378
2379         return howmany;
2380 }
2381
2382 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2383 {
2384         unsigned long flags;
2385
2386         spin_lock_irqsave(&gfargrp->grplock, flags);
2387         if (napi_schedule_prep(&gfargrp->napi)) {
2388                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2389                 __napi_schedule(&gfargrp->napi);
2390         } else {
2391                 /*
2392                  * Clear IEVENT, so interrupts aren't called again
2393                  * because of the packets that have already arrived.
2394                  */
2395                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2396         }
2397         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2398
2399 }
2400
2401 /* Interrupt Handler for Transmit complete */
2402 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2403 {
2404         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2405         return IRQ_HANDLED;
2406 }
2407
2408 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2409                 struct sk_buff *skb)
2410 {
2411         struct net_device *dev = rx_queue->dev;
2412         struct gfar_private *priv = netdev_priv(dev);
2413         dma_addr_t buf;
2414
2415         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2416                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2417         gfar_init_rxbdp(rx_queue, bdp, buf);
2418 }
2419
2420
2421 struct sk_buff * gfar_new_skb(struct net_device *dev)
2422 {
2423         unsigned int alignamount;
2424         struct gfar_private *priv = netdev_priv(dev);
2425         struct sk_buff *skb = NULL;
2426
2427         skb = __skb_dequeue(&priv->rx_recycle);
2428         if (!skb)
2429                 skb = netdev_alloc_skb(dev,
2430                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
2431
2432         if (!skb)
2433                 return NULL;
2434
2435         alignamount = RXBUF_ALIGNMENT -
2436                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
2437
2438         /* We need the data buffer to be aligned properly.  We will reserve
2439          * as many bytes as needed to align the data properly
2440          */
2441         skb_reserve(skb, alignamount);
2442         GFAR_CB(skb)->alignamount = alignamount;
2443
2444         return skb;
2445 }
2446
2447 static inline void count_errors(unsigned short status, struct net_device *dev)
2448 {
2449         struct gfar_private *priv = netdev_priv(dev);
2450         struct net_device_stats *stats = &dev->stats;
2451         struct gfar_extra_stats *estats = &priv->extra_stats;
2452
2453         /* If the packet was truncated, none of the other errors
2454          * matter */
2455         if (status & RXBD_TRUNCATED) {
2456                 stats->rx_length_errors++;
2457
2458                 estats->rx_trunc++;
2459
2460                 return;
2461         }
2462         /* Count the errors, if there were any */
2463         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2464                 stats->rx_length_errors++;
2465
2466                 if (status & RXBD_LARGE)
2467                         estats->rx_large++;
2468                 else
2469                         estats->rx_short++;
2470         }
2471         if (status & RXBD_NONOCTET) {
2472                 stats->rx_frame_errors++;
2473                 estats->rx_nonoctet++;
2474         }
2475         if (status & RXBD_CRCERR) {
2476                 estats->rx_crcerr++;
2477                 stats->rx_crc_errors++;
2478         }
2479         if (status & RXBD_OVERRUN) {
2480                 estats->rx_overrun++;
2481                 stats->rx_crc_errors++;
2482         }
2483 }
2484
2485 irqreturn_t gfar_receive(int irq, void *grp_id)
2486 {
2487         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2488         return IRQ_HANDLED;
2489 }
2490
2491 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2492 {
2493         /* If valid headers were found, and valid sums
2494          * were verified, then we tell the kernel that no
2495          * checksumming is necessary.  Otherwise, it is */
2496         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2497                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2498         else
2499                 skb->ip_summed = CHECKSUM_NONE;
2500 }
2501
2502
2503 /* gfar_process_frame() -- handle one incoming packet if skb
2504  * isn't NULL.  */
2505 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2506                               int amount_pull)
2507 {
2508         struct gfar_private *priv = netdev_priv(dev);
2509         struct rxfcb *fcb = NULL;
2510
2511         int ret;
2512
2513         /* fcb is at the beginning if exists */
2514         fcb = (struct rxfcb *)skb->data;
2515
2516         /* Remove the FCB from the skb */
2517         /* Remove the padded bytes, if there are any */
2518         if (amount_pull) {
2519                 skb_record_rx_queue(skb, fcb->rq);
2520                 skb_pull(skb, amount_pull);
2521         }
2522
2523         /* Get receive timestamp from the skb */
2524         if (priv->hwts_rx_en) {
2525                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2526                 u64 *ns = (u64 *) skb->data;
2527                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2528                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2529         }
2530
2531         if (priv->padding)
2532                 skb_pull(skb, priv->padding);
2533
2534         if (priv->rx_csum_enable)
2535                 gfar_rx_checksum(skb, fcb);
2536
2537         /* Tell the skb what kind of packet this is */
2538         skb->protocol = eth_type_trans(skb, dev);
2539
2540         /* Send the packet up the stack */
2541         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2542                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2543         else
2544                 ret = netif_receive_skb(skb);
2545
2546         if (NET_RX_DROP == ret)
2547                 priv->extra_stats.kernel_dropped++;
2548
2549         return 0;
2550 }
2551
2552 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2553  *   until the budget/quota has been reached. Returns the number
2554  *   of frames handled
2555  */
2556 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2557 {
2558         struct net_device *dev = rx_queue->dev;
2559         struct rxbd8 *bdp, *base;
2560         struct sk_buff *skb;
2561         int pkt_len;
2562         int amount_pull;
2563         int howmany = 0;
2564         struct gfar_private *priv = netdev_priv(dev);
2565
2566         /* Get the first full descriptor */
2567         bdp = rx_queue->cur_rx;
2568         base = rx_queue->rx_bd_base;
2569
2570         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2571
2572         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2573                 struct sk_buff *newskb;
2574                 rmb();
2575
2576                 /* Add another skb for the future */
2577                 newskb = gfar_new_skb(dev);
2578
2579                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2580
2581                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2582                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2583
2584                 /* We drop the frame if we failed to allocate a new buffer */
2585                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2586                                  bdp->status & RXBD_ERR)) {
2587                         count_errors(bdp->status, dev);
2588
2589                         if (unlikely(!newskb))
2590                                 newskb = skb;
2591                         else if (skb) {
2592                                 /*
2593                                  * We need to un-reserve() the skb to what it
2594                                  * was before gfar_new_skb() re-aligned
2595                                  * it to an RXBUF_ALIGNMENT boundary
2596                                  * before we put the skb back on the
2597                                  * recycle list.
2598                                  */
2599                                 skb_reserve(skb, -GFAR_CB(skb)->alignamount);
2600                                 __skb_queue_head(&priv->rx_recycle, skb);
2601                         }
2602                 } else {
2603                         /* Increment the number of packets */
2604                         rx_queue->stats.rx_packets++;
2605                         howmany++;
2606
2607                         if (likely(skb)) {
2608                                 pkt_len = bdp->length - ETH_FCS_LEN;
2609                                 /* Remove the FCS from the packet length */
2610                                 skb_put(skb, pkt_len);
2611                                 rx_queue->stats.rx_bytes += pkt_len;
2612                                 skb_record_rx_queue(skb, rx_queue->qindex);
2613                                 gfar_process_frame(dev, skb, amount_pull);
2614
2615                         } else {
2616                                 if (netif_msg_rx_err(priv))
2617                                         printk(KERN_WARNING
2618                                                "%s: Missing skb!\n", dev->name);
2619                                 rx_queue->stats.rx_dropped++;
2620                                 priv->extra_stats.rx_skbmissing++;
2621                         }
2622
2623                 }
2624
2625                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2626
2627                 /* Setup the new bdp */
2628                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2629
2630                 /* Update to the next pointer */
2631                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2632
2633                 /* update to point at the next skb */
2634                 rx_queue->skb_currx =
2635                     (rx_queue->skb_currx + 1) &
2636                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2637         }
2638
2639         /* Update the current rxbd pointer to be the next one */
2640         rx_queue->cur_rx = bdp;
2641
2642         return howmany;
2643 }
2644
2645 static int gfar_poll(struct napi_struct *napi, int budget)
2646 {
2647         struct gfar_priv_grp *gfargrp = container_of(napi,
2648                         struct gfar_priv_grp, napi);
2649         struct gfar_private *priv = gfargrp->priv;
2650         struct gfar __iomem *regs = gfargrp->regs;
2651         struct gfar_priv_tx_q *tx_queue = NULL;
2652         struct gfar_priv_rx_q *rx_queue = NULL;
2653         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2654         int tx_cleaned = 0, i, left_over_budget = budget;
2655         unsigned long serviced_queues = 0;
2656         int num_queues = 0;
2657
2658         num_queues = gfargrp->num_rx_queues;
2659         budget_per_queue = budget/num_queues;
2660
2661         /* Clear IEVENT, so interrupts aren't called again
2662          * because of the packets that have already arrived */
2663         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2664
2665         while (num_queues && left_over_budget) {
2666
2667                 budget_per_queue = left_over_budget/num_queues;
2668                 left_over_budget = 0;
2669
2670                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2671                         if (test_bit(i, &serviced_queues))
2672                                 continue;
2673                         rx_queue = priv->rx_queue[i];
2674                         tx_queue = priv->tx_queue[rx_queue->qindex];
2675
2676                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2677                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2678                                                         budget_per_queue);
2679                         rx_cleaned += rx_cleaned_per_queue;
2680                         if(rx_cleaned_per_queue < budget_per_queue) {
2681                                 left_over_budget = left_over_budget +
2682                                         (budget_per_queue - rx_cleaned_per_queue);
2683                                 set_bit(i, &serviced_queues);
2684                                 num_queues--;
2685                         }
2686                 }
2687         }
2688
2689         if (tx_cleaned)
2690                 return budget;
2691
2692         if (rx_cleaned < budget) {
2693                 napi_complete(napi);
2694
2695                 /* Clear the halt bit in RSTAT */
2696                 gfar_write(&regs->rstat, gfargrp->rstat);
2697
2698                 gfar_write(&regs->imask, IMASK_DEFAULT);
2699
2700                 /* If we are coalescing interrupts, update the timer */
2701                 /* Otherwise, clear it */
2702                 gfar_configure_coalescing(priv,
2703                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2704         }
2705
2706         return rx_cleaned;
2707 }
2708
2709 #ifdef CONFIG_NET_POLL_CONTROLLER
2710 /*
2711  * Polling 'interrupt' - used by things like netconsole to send skbs
2712  * without having to re-enable interrupts. It's not called while
2713  * the interrupt routine is executing.
2714  */
2715 static void gfar_netpoll(struct net_device *dev)
2716 {
2717         struct gfar_private *priv = netdev_priv(dev);
2718         int i = 0;
2719
2720         /* If the device has multiple interrupts, run tx/rx */
2721         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2722                 for (i = 0; i < priv->num_grps; i++) {
2723                         disable_irq(priv->gfargrp[i].interruptTransmit);
2724                         disable_irq(priv->gfargrp[i].interruptReceive);
2725                         disable_irq(priv->gfargrp[i].interruptError);
2726                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2727                                                 &priv->gfargrp[i]);
2728                         enable_irq(priv->gfargrp[i].interruptError);
2729                         enable_irq(priv->gfargrp[i].interruptReceive);
2730                         enable_irq(priv->gfargrp[i].interruptTransmit);
2731                 }
2732         } else {
2733                 for (i = 0; i < priv->num_grps; i++) {
2734                         disable_irq(priv->gfargrp[i].interruptTransmit);
2735                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2736                                                 &priv->gfargrp[i]);
2737                         enable_irq(priv->gfargrp[i].interruptTransmit);
2738                 }
2739         }
2740 }
2741 #endif
2742
2743 /* The interrupt handler for devices with one interrupt */
2744 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2745 {
2746         struct gfar_priv_grp *gfargrp = grp_id;
2747
2748         /* Save ievent for future reference */
2749         u32 events = gfar_read(&gfargrp->regs->ievent);
2750
2751         /* Check for reception */
2752         if (events & IEVENT_RX_MASK)
2753                 gfar_receive(irq, grp_id);
2754
2755         /* Check for transmit completion */
2756         if (events & IEVENT_TX_MASK)
2757                 gfar_transmit(irq, grp_id);
2758
2759         /* Check for errors */
2760         if (events & IEVENT_ERR_MASK)
2761                 gfar_error(irq, grp_id);
2762
2763         return IRQ_HANDLED;
2764 }
2765
2766 /* Called every time the controller might need to be made
2767  * aware of new link state.  The PHY code conveys this
2768  * information through variables in the phydev structure, and this
2769  * function converts those variables into the appropriate
2770  * register values, and can bring down the device if needed.
2771  */
2772 static void adjust_link(struct net_device *dev)
2773 {
2774         struct gfar_private *priv = netdev_priv(dev);
2775         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2776         unsigned long flags;
2777         struct phy_device *phydev = priv->phydev;
2778         int new_state = 0;
2779
2780         local_irq_save(flags);
2781         lock_tx_qs(priv);
2782
2783         if (phydev->link) {
2784                 u32 tempval = gfar_read(&regs->maccfg2);
2785                 u32 ecntrl = gfar_read(&regs->ecntrl);
2786
2787                 /* Now we make sure that we can be in full duplex mode.
2788                  * If not, we operate in half-duplex mode. */
2789                 if (phydev->duplex != priv->oldduplex) {
2790                         new_state = 1;
2791                         if (!(phydev->duplex))
2792                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2793                         else
2794                                 tempval |= MACCFG2_FULL_DUPLEX;
2795
2796                         priv->oldduplex = phydev->duplex;
2797                 }
2798
2799                 if (phydev->speed != priv->oldspeed) {
2800                         new_state = 1;
2801                         switch (phydev->speed) {
2802                         case 1000:
2803                                 tempval =
2804                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2805
2806                                 ecntrl &= ~(ECNTRL_R100);
2807                                 break;
2808                         case 100:
2809                         case 10:
2810                                 tempval =
2811                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2812
2813                                 /* Reduced mode distinguishes
2814                                  * between 10 and 100 */
2815                                 if (phydev->speed == SPEED_100)
2816                                         ecntrl |= ECNTRL_R100;
2817                                 else
2818                                         ecntrl &= ~(ECNTRL_R100);
2819                                 break;
2820                         default:
2821                                 if (netif_msg_link(priv))
2822                                         printk(KERN_WARNING
2823                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2824                                                 dev->name, phydev->speed);
2825                                 break;
2826                         }
2827
2828                         priv->oldspeed = phydev->speed;
2829                 }
2830
2831                 gfar_write(&regs->maccfg2, tempval);
2832                 gfar_write(&regs->ecntrl, ecntrl);
2833
2834                 if (!priv->oldlink) {
2835                         new_state = 1;
2836                         priv->oldlink = 1;
2837                 }
2838         } else if (priv->oldlink) {
2839                 new_state = 1;
2840                 priv->oldlink = 0;
2841                 priv->oldspeed = 0;
2842                 priv->oldduplex = -1;
2843         }
2844
2845         if (new_state && netif_msg_link(priv))
2846                 phy_print_status(phydev);
2847         unlock_tx_qs(priv);
2848         local_irq_restore(flags);
2849 }
2850
2851 /* Update the hash table based on the current list of multicast
2852  * addresses we subscribe to.  Also, change the promiscuity of
2853  * the device based on the flags (this function is called
2854  * whenever dev->flags is changed */
2855 static void gfar_set_multi(struct net_device *dev)
2856 {
2857         struct netdev_hw_addr *ha;
2858         struct gfar_private *priv = netdev_priv(dev);
2859         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2860         u32 tempval;
2861
2862         if (dev->flags & IFF_PROMISC) {
2863                 /* Set RCTRL to PROM */
2864                 tempval = gfar_read(&regs->rctrl);
2865                 tempval |= RCTRL_PROM;
2866                 gfar_write(&regs->rctrl, tempval);
2867         } else {
2868                 /* Set RCTRL to not PROM */
2869                 tempval = gfar_read(&regs->rctrl);
2870                 tempval &= ~(RCTRL_PROM);
2871                 gfar_write(&regs->rctrl, tempval);
2872         }
2873
2874         if (dev->flags & IFF_ALLMULTI) {
2875                 /* Set the hash to rx all multicast frames */
2876                 gfar_write(&regs->igaddr0, 0xffffffff);
2877                 gfar_write(&regs->igaddr1, 0xffffffff);
2878                 gfar_write(&regs->igaddr2, 0xffffffff);
2879                 gfar_write(&regs->igaddr3, 0xffffffff);
2880                 gfar_write(&regs->igaddr4, 0xffffffff);
2881                 gfar_write(&regs->igaddr5, 0xffffffff);
2882                 gfar_write(&regs->igaddr6, 0xffffffff);
2883                 gfar_write(&regs->igaddr7, 0xffffffff);
2884                 gfar_write(&regs->gaddr0, 0xffffffff);
2885                 gfar_write(&regs->gaddr1, 0xffffffff);
2886                 gfar_write(&regs->gaddr2, 0xffffffff);
2887                 gfar_write(&regs->gaddr3, 0xffffffff);
2888                 gfar_write(&regs->gaddr4, 0xffffffff);
2889                 gfar_write(&regs->gaddr5, 0xffffffff);
2890                 gfar_write(&regs->gaddr6, 0xffffffff);
2891                 gfar_write(&regs->gaddr7, 0xffffffff);
2892         } else {
2893                 int em_num;
2894                 int idx;
2895
2896                 /* zero out the hash */
2897                 gfar_write(&regs->igaddr0, 0x0);
2898                 gfar_write(&regs->igaddr1, 0x0);
2899                 gfar_write(&regs->igaddr2, 0x0);
2900                 gfar_write(&regs->igaddr3, 0x0);
2901                 gfar_write(&regs->igaddr4, 0x0);
2902                 gfar_write(&regs->igaddr5, 0x0);
2903                 gfar_write(&regs->igaddr6, 0x0);
2904                 gfar_write(&regs->igaddr7, 0x0);
2905                 gfar_write(&regs->gaddr0, 0x0);
2906                 gfar_write(&regs->gaddr1, 0x0);
2907                 gfar_write(&regs->gaddr2, 0x0);
2908                 gfar_write(&regs->gaddr3, 0x0);
2909                 gfar_write(&regs->gaddr4, 0x0);
2910                 gfar_write(&regs->gaddr5, 0x0);
2911                 gfar_write(&regs->gaddr6, 0x0);
2912                 gfar_write(&regs->gaddr7, 0x0);
2913
2914                 /* If we have extended hash tables, we need to
2915                  * clear the exact match registers to prepare for
2916                  * setting them */
2917                 if (priv->extended_hash) {
2918                         em_num = GFAR_EM_NUM + 1;
2919                         gfar_clear_exact_match(dev);
2920                         idx = 1;
2921                 } else {
2922                         idx = 0;
2923                         em_num = 0;
2924                 }
2925
2926                 if (netdev_mc_empty(dev))
2927                         return;
2928
2929                 /* Parse the list, and set the appropriate bits */
2930                 netdev_for_each_mc_addr(ha, dev) {
2931                         if (idx < em_num) {
2932                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
2933                                 idx++;
2934                         } else
2935                                 gfar_set_hash_for_addr(dev, ha->addr);
2936                 }
2937         }
2938
2939         return;
2940 }
2941
2942
2943 /* Clears each of the exact match registers to zero, so they
2944  * don't interfere with normal reception */
2945 static void gfar_clear_exact_match(struct net_device *dev)
2946 {
2947         int idx;
2948         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2949
2950         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2951                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2952 }
2953
2954 /* Set the appropriate hash bit for the given addr */
2955 /* The algorithm works like so:
2956  * 1) Take the Destination Address (ie the multicast address), and
2957  * do a CRC on it (little endian), and reverse the bits of the
2958  * result.
2959  * 2) Use the 8 most significant bits as a hash into a 256-entry
2960  * table.  The table is controlled through 8 32-bit registers:
2961  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2962  * gaddr7.  This means that the 3 most significant bits in the
2963  * hash index which gaddr register to use, and the 5 other bits
2964  * indicate which bit (assuming an IBM numbering scheme, which
2965  * for PowerPC (tm) is usually the case) in the register holds
2966  * the entry. */
2967 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2968 {
2969         u32 tempval;
2970         struct gfar_private *priv = netdev_priv(dev);
2971         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2972         int width = priv->hash_width;
2973         u8 whichbit = (result >> (32 - width)) & 0x1f;
2974         u8 whichreg = result >> (32 - width + 5);
2975         u32 value = (1 << (31-whichbit));
2976
2977         tempval = gfar_read(priv->hash_regs[whichreg]);
2978         tempval |= value;
2979         gfar_write(priv->hash_regs[whichreg], tempval);
2980
2981         return;
2982 }
2983
2984
2985 /* There are multiple MAC Address register pairs on some controllers
2986  * This function sets the numth pair to a given address
2987  */
2988 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2989 {
2990         struct gfar_private *priv = netdev_priv(dev);
2991         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2992         int idx;
2993         char tmpbuf[MAC_ADDR_LEN];
2994         u32 tempval;
2995         u32 __iomem *macptr = &regs->macstnaddr1;
2996
2997         macptr += num*2;
2998
2999         /* Now copy it into the mac registers backwards, cuz */
3000         /* little endian is silly */
3001         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3002                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3003
3004         gfar_write(macptr, *((u32 *) (tmpbuf)));
3005
3006         tempval = *((u32 *) (tmpbuf + 4));
3007
3008         gfar_write(macptr+1, tempval);
3009 }
3010
3011 /* GFAR error interrupt handler */
3012 static irqreturn_t gfar_error(int irq, void *grp_id)
3013 {
3014         struct gfar_priv_grp *gfargrp = grp_id;
3015         struct gfar __iomem *regs = gfargrp->regs;
3016         struct gfar_private *priv= gfargrp->priv;
3017         struct net_device *dev = priv->ndev;
3018
3019         /* Save ievent for future reference */
3020         u32 events = gfar_read(&regs->ievent);
3021
3022         /* Clear IEVENT */
3023         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3024
3025         /* Magic Packet is not an error. */
3026         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3027             (events & IEVENT_MAG))
3028                 events &= ~IEVENT_MAG;
3029
3030         /* Hmm... */
3031         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3032                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3033                        dev->name, events, gfar_read(&regs->imask));
3034
3035         /* Update the error counters */
3036         if (events & IEVENT_TXE) {
3037                 dev->stats.tx_errors++;
3038
3039                 if (events & IEVENT_LC)
3040                         dev->stats.tx_window_errors++;
3041                 if (events & IEVENT_CRL)
3042                         dev->stats.tx_aborted_errors++;
3043                 if (events & IEVENT_XFUN) {
3044                         unsigned long flags;
3045
3046                         if (netif_msg_tx_err(priv))
3047                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3048                                        "packet dropped.\n", dev->name);
3049                         dev->stats.tx_dropped++;
3050                         priv->extra_stats.tx_underrun++;
3051
3052                         local_irq_save(flags);
3053                         lock_tx_qs(priv);
3054
3055                         /* Reactivate the Tx Queues */
3056                         gfar_write(&regs->tstat, gfargrp->tstat);
3057
3058                         unlock_tx_qs(priv);
3059                         local_irq_restore(flags);
3060                 }
3061                 if (netif_msg_tx_err(priv))
3062                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
3063         }
3064         if (events & IEVENT_BSY) {
3065                 dev->stats.rx_errors++;
3066                 priv->extra_stats.rx_bsy++;
3067
3068                 gfar_receive(irq, grp_id);
3069
3070                 if (netif_msg_rx_err(priv))
3071                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
3072                                dev->name, gfar_read(&regs->rstat));
3073         }
3074         if (events & IEVENT_BABR) {
3075                 dev->stats.rx_errors++;
3076                 priv->extra_stats.rx_babr++;
3077
3078                 if (netif_msg_rx_err(priv))
3079                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
3080         }
3081         if (events & IEVENT_EBERR) {
3082                 priv->extra_stats.eberr++;
3083                 if (netif_msg_rx_err(priv))
3084                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
3085         }
3086         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
3087                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
3088
3089         if (events & IEVENT_BABT) {
3090                 priv->extra_stats.tx_babt++;
3091                 if (netif_msg_tx_err(priv))
3092                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
3093         }
3094         return IRQ_HANDLED;
3095 }
3096
3097 static struct of_device_id gfar_match[] =
3098 {
3099         {
3100                 .type = "network",
3101                 .compatible = "gianfar",
3102         },
3103         {
3104                 .compatible = "fsl,etsec2",
3105         },
3106         {},
3107 };
3108 MODULE_DEVICE_TABLE(of, gfar_match);
3109
3110 /* Structure for a device driver */
3111 static struct of_platform_driver gfar_driver = {
3112         .name = "fsl-gianfar",
3113         .match_table = gfar_match,
3114
3115         .probe = gfar_probe,
3116         .remove = gfar_remove,
3117         .suspend = gfar_legacy_suspend,
3118         .resume = gfar_legacy_resume,
3119         .driver.pm = GFAR_PM_OPS,
3120 };
3121
3122 static int __init gfar_init(void)
3123 {
3124         return of_register_platform_driver(&gfar_driver);
3125 }
3126
3127 static void __exit gfar_exit(void)
3128 {
3129         of_unregister_platform_driver(&gfar_driver);
3130 }
3131
3132 module_init(gfar_init);
3133 module_exit(gfar_exit);
3134