drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *
  94  * Known bugs:
  95  * We suspect that on some hardware no TX done interrupts are generated.
  96  * This means recovery from netif_stop_queue only happens if the hw timer
  97  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  98  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  99  * If your hardware reliably generates tx done interrupts, then you can remove
 100  * DEV_NEED_TIMERIRQ from the driver_data flags.
 101  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 102  * superfluous timer interrupts from the nic.
 103  */
 104 #define FORCEDETH_VERSION               "0.39"
 105 #define DRV_NAME                        "forcedeth"
 106
 107 #include <linux/module.h>
 108 #include <linux/types.h>
 109 #include <linux/pci.h>
 110 #include <linux/interrupt.h>
 111 #include <linux/netdevice.h>
 112 #include <linux/etherdevice.h>
 113 #include <linux/delay.h>
 114 #include <linux/spinlock.h>
 115 #include <linux/ethtool.h>
 116 #include <linux/timer.h>
 117 #include <linux/skbuff.h>
 118 #include <linux/mii.h>
 119 #include <linux/random.h>
 120 #include <linux/init.h>
 121 #include <linux/if_vlan.h>
 122
 123 #include <asm/irq.h>
 124 #include <asm/io.h>
 125 #include <asm/uaccess.h>
 126 #include <asm/system.h>
 127
 128 #if 0
 129 #define dprintk                 printk
 130 #else
 131 #define dprintk(x...)           do { } while (0)
 132 #endif
 133
 134
 135 /*
 136  * Hardware access:
 137  */
 138
 139 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 140 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 141 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 142 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 143
 144 enum {
 145         NvRegIrqStatus = 0x000,
 146 #define NVREG_IRQSTAT_MIIEVENT  0x040
 147 #define NVREG_IRQSTAT_MASK              0x1ff
 148         NvRegIrqMask = 0x004,
 149 #define NVREG_IRQ_RX_ERROR              0x0001
 150 #define NVREG_IRQ_RX                    0x0002
 151 #define NVREG_IRQ_RX_NOBUF              0x0004
 152 #define NVREG_IRQ_TX_ERR                0x0008
 153 #define NVREG_IRQ_TX_OK                 0x0010
 154 #define NVREG_IRQ_TIMER                 0x0020
 155 #define NVREG_IRQ_LINK                  0x0040
 156 #define NVREG_IRQ_TX_ERROR              0x0080
 157 #define NVREG_IRQ_TX1                   0x0100
 158 #define NVREG_IRQMASK_WANTED            0x00df
 159
 160 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 161                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
 162                                         NVREG_IRQ_TX1))
 163
 164         NvRegUnknownSetupReg6 = 0x008,
 165 #define NVREG_UNKSETUP6_VAL             3
 166
 167 /*
 168  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 169  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 170  */
 171         NvRegPollingInterval = 0x00c,
 172 #define NVREG_POLL_DEFAULT      970
 173         NvRegMisc1 = 0x080,
 174 #define NVREG_MISC1_HD          0x02
 175 #define NVREG_MISC1_FORCE       0x3b0f3c
 176
 177         NvRegTransmitterControl = 0x084,
 178 #define NVREG_XMITCTL_START     0x01
 179         NvRegTransmitterStatus = 0x088,
 180 #define NVREG_XMITSTAT_BUSY     0x01
 181
 182         NvRegPacketFilterFlags = 0x8c,
 183 #define NVREG_PFF_ALWAYS        0x7F0008
 184 #define NVREG_PFF_PROMISC       0x80
 185 #define NVREG_PFF_MYADDR        0x20
 186
 187         NvRegOffloadConfig = 0x90,
 188 #define NVREG_OFFLOAD_HOMEPHY   0x601
 189 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 190         NvRegReceiverControl = 0x094,
 191 #define NVREG_RCVCTL_START      0x01
 192         NvRegReceiverStatus = 0x98,
 193 #define NVREG_RCVSTAT_BUSY      0x01
 194
 195         NvRegRandomSeed = 0x9c,
 196 #define NVREG_RNDSEED_MASK      0x00ff
 197 #define NVREG_RNDSEED_FORCE     0x7f00
 198 #define NVREG_RNDSEED_FORCE2    0x2d00
 199 #define NVREG_RNDSEED_FORCE3    0x7400
 200
 201         NvRegUnknownSetupReg1 = 0xA0,
 202 #define NVREG_UNKSETUP1_VAL     0x16070f
 203         NvRegUnknownSetupReg2 = 0xA4,
 204 #define NVREG_UNKSETUP2_VAL     0x16
 205         NvRegMacAddrA = 0xA8,
 206         NvRegMacAddrB = 0xAC,
 207         NvRegMulticastAddrA = 0xB0,
 208 #define NVREG_MCASTADDRA_FORCE  0x01
 209         NvRegMulticastAddrB = 0xB4,
 210         NvRegMulticastMaskA = 0xB8,
 211         NvRegMulticastMaskB = 0xBC,
 212
 213         NvRegPhyInterface = 0xC0,
 214 #define PHY_RGMII               0x10000000
 215
 216         NvRegTxRingPhysAddr = 0x100,
 217         NvRegRxRingPhysAddr = 0x104,
 218         NvRegRingSizes = 0x108,
 219 #define NVREG_RINGSZ_TXSHIFT 0
 220 #define NVREG_RINGSZ_RXSHIFT 16
 221         NvRegUnknownTransmitterReg = 0x10c,
 222         NvRegLinkSpeed = 0x110,
 223 #define NVREG_LINKSPEED_FORCE 0x10000
 224 #define NVREG_LINKSPEED_10      1000
 225 #define NVREG_LINKSPEED_100     100
 226 #define NVREG_LINKSPEED_1000    50
 227 #define NVREG_LINKSPEED_MASK    (0xFFF)
 228         NvRegUnknownSetupReg5 = 0x130,
 229 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 230         NvRegUnknownSetupReg3 = 0x13c,
 231 #define NVREG_UNKSETUP3_VAL1    0x200010
 232         NvRegTxRxControl = 0x144,
 233 #define NVREG_TXRXCTL_KICK      0x0001
 234 #define NVREG_TXRXCTL_BIT1      0x0002
 235 #define NVREG_TXRXCTL_BIT2      0x0004
 236 #define NVREG_TXRXCTL_IDLE      0x0008
 237 #define NVREG_TXRXCTL_RESET     0x0010
 238 #define NVREG_TXRXCTL_RXCHECK   0x0400
 239         NvRegMIIStatus = 0x180,
 240 #define NVREG_MIISTAT_ERROR             0x0001
 241 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 242 #define NVREG_MIISTAT_MASK              0x000f
 243 #define NVREG_MIISTAT_MASK2             0x000f
 244         NvRegUnknownSetupReg4 = 0x184,
 245 #define NVREG_UNKSETUP4_VAL     8
 246
 247         NvRegAdapterControl = 0x188,
 248 #define NVREG_ADAPTCTL_START    0x02
 249 #define NVREG_ADAPTCTL_LINKUP   0x04
 250 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 251 #define NVREG_ADAPTCTL_RUNNING  0x100000
 252 #define NVREG_ADAPTCTL_PHYSHIFT 24
 253         NvRegMIISpeed = 0x18c,
 254 #define NVREG_MIISPEED_BIT8     (1<<8)
 255 #define NVREG_MIIDELAY  5
 256         NvRegMIIControl = 0x190,
 257 #define NVREG_MIICTL_INUSE      0x08000
 258 #define NVREG_MIICTL_WRITE      0x00400
 259 #define NVREG_MIICTL_ADDRSHIFT  5
 260         NvRegMIIData = 0x194,
 261         NvRegWakeUpFlags = 0x200,
 262 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 263 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 264 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 265 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 266 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 267 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 268 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 269 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 270 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 271 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 272 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 273
 274         NvRegPatternCRC = 0x204,
 275         NvRegPatternMask = 0x208,
 276         NvRegPowerCap = 0x268,
 277 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 278 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 279 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 280         NvRegPowerState = 0x26c,
 281 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 282 #define NVREG_POWERSTATE_VALID          0x0100
 283 #define NVREG_POWERSTATE_MASK           0x0003
 284 #define NVREG_POWERSTATE_D0             0x0000
 285 #define NVREG_POWERSTATE_D1             0x0001
 286 #define NVREG_POWERSTATE_D2             0x0002
 287 #define NVREG_POWERSTATE_D3             0x0003
 288 };
 289
 290 /* Big endian: should work, but is untested */
 291 struct ring_desc {
 292         u32 PacketBuffer;
 293         u32 FlagLen;
 294 };
 295
 296 struct ring_desc_ex {
 297         u32 PacketBufferHigh;
 298         u32 PacketBufferLow;
 299         u32 Reserved;
 300         u32 FlagLen;
 301 };
 302
 303 typedef union _ring_type {
 304         struct ring_desc* orig;
 305         struct ring_desc_ex* ex;
 306 } ring_type;
 307
 308 #define FLAG_MASK_V1 0xffff0000
 309 #define FLAG_MASK_V2 0xffffc000
 310 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 311 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 312
 313 #define NV_TX_LASTPACKET        (1<<16)
 314 #define NV_TX_RETRYERROR        (1<<19)
 315 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 316 #define NV_TX_DEFERRED          (1<<26)
 317 #define NV_TX_CARRIERLOST       (1<<27)
 318 #define NV_TX_LATECOLLISION     (1<<28)
 319 #define NV_TX_UNDERFLOW         (1<<29)
 320 #define NV_TX_ERROR             (1<<30)
 321 #define NV_TX_VALID             (1<<31)
 322
 323 #define NV_TX2_LASTPACKET       (1<<29)
 324 #define NV_TX2_RETRYERROR       (1<<18)
 325 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 326 #define NV_TX2_DEFERRED         (1<<25)
 327 #define NV_TX2_CARRIERLOST      (1<<26)
 328 #define NV_TX2_LATECOLLISION    (1<<27)
 329 #define NV_TX2_UNDERFLOW        (1<<28)
 330 /* error and valid are the same for both */
 331 #define NV_TX2_ERROR            (1<<30)
 332 #define NV_TX2_VALID            (1<<31)
 333
 334 #define NV_RX_DESCRIPTORVALID   (1<<16)
 335 #define NV_RX_MISSEDFRAME       (1<<17)
 336 #define NV_RX_SUBSTRACT1        (1<<18)
 337 #define NV_RX_ERROR1            (1<<23)
 338 #define NV_RX_ERROR2            (1<<24)
 339 #define NV_RX_ERROR3            (1<<25)
 340 #define NV_RX_ERROR4            (1<<26)
 341 #define NV_RX_CRCERR            (1<<27)
 342 #define NV_RX_OVERFLOW          (1<<28)
 343 #define NV_RX_FRAMINGERR        (1<<29)
 344 #define NV_RX_ERROR             (1<<30)
 345 #define NV_RX_AVAIL             (1<<31)
 346
 347 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 348 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 349 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 350 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 351 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 352 #define NV_RX2_SUBSTRACT1       (1<<25)
 353 #define NV_RX2_ERROR1           (1<<18)
 354 #define NV_RX2_ERROR2           (1<<19)
 355 #define NV_RX2_ERROR3           (1<<20)
 356 #define NV_RX2_ERROR4           (1<<21)
 357 #define NV_RX2_CRCERR           (1<<22)
 358 #define NV_RX2_OVERFLOW         (1<<23)
 359 #define NV_RX2_FRAMINGERR       (1<<24)
 360 /* error and avail are the same for both */
 361 #define NV_RX2_ERROR            (1<<30)
 362 #define NV_RX2_AVAIL            (1<<31)
 363
 364 /* Miscelaneous hardware related defines: */
 365 #define NV_PCI_REGSZ            0x270
 366
 367 /* various timeout delays: all in usec */
 368 #define NV_TXRX_RESET_DELAY     4
 369 #define NV_TXSTOP_DELAY1        10
 370 #define NV_TXSTOP_DELAY1MAX     500000
 371 #define NV_TXSTOP_DELAY2        100
 372 #define NV_RXSTOP_DELAY1        10
 373 #define NV_RXSTOP_DELAY1MAX     500000
 374 #define NV_RXSTOP_DELAY2        100
 375 #define NV_SETUP5_DELAY         5
 376 #define NV_SETUP5_DELAYMAX      50000
 377 #define NV_POWERUP_DELAY        5
 378 #define NV_POWERUP_DELAYMAX     5000
 379 #define NV_MIIBUSY_DELAY        50
 380 #define NV_MIIPHY_DELAY 10
 381 #define NV_MIIPHY_DELAYMAX      10000
 382
 383 #define NV_WAKEUPPATTERNS       5
 384 #define NV_WAKEUPMASKENTRIES    4
 385
 386 /* General driver defaults */
 387 #define NV_WATCHDOG_TIMEO       (5*HZ)
 388
 389 #define RX_RING         128
 390 #define TX_RING         64
 391 /*
 392  * If your nic mysteriously hangs then try to reduce the limits
 393  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 394  * last valid ring entry. But this would be impossible to
 395  * implement - probably a disassembly error.
 396  */
 397 #define TX_LIMIT_STOP   63
 398 #define TX_LIMIT_START  62
 399
 400 /* rx/tx mac addr + type + vlan + align + slack*/
 401 #define NV_RX_HEADERS           (64)
 402 /* even more slack. */
 403 #define NV_RX_ALLOC_PAD         (64)
 404
 405 /* maximum mtu size */
 406 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 407 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 408
 409 #define OOM_REFILL      (1+HZ/20)
 410 #define POLL_WAIT       (1+HZ/100)
 411 #define LINK_TIMEOUT    (3*HZ)
 412
 413 /*
 414  * desc_ver values:
 415  * This field has two purposes:
 416  * - Newer nics uses a different ring layout. The layout is selected by
 417  *   comparing np->desc_ver with DESC_VER_xy.
 418  * - It contains bits that are forced on when writing to NvRegTxRxControl.
 419  */
 420 #define DESC_VER_1      0x0
 421 #define DESC_VER_2      (0x02100|NVREG_TXRXCTL_RXCHECK)
 422 #define DESC_VER_3      (0x02200|NVREG_TXRXCTL_RXCHECK)
 423
 424 /* PHY defines */
 425 #define PHY_OUI_MARVELL 0x5043
 426 #define PHY_OUI_CICADA  0x03f1
 427 #define PHYID1_OUI_MASK 0x03ff
 428 #define PHYID1_OUI_SHFT 6
 429 #define PHYID2_OUI_MASK 0xfc00
 430 #define PHYID2_OUI_SHFT 10
 431 #define PHY_INIT1       0x0f000
 432 #define PHY_INIT2       0x0e00
 433 #define PHY_INIT3       0x01000
 434 #define PHY_INIT4       0x0200
 435 #define PHY_INIT5       0x0004
 436 #define PHY_INIT6       0x02000
 437 #define PHY_GIGABIT     0x0100
 438
 439 #define PHY_TIMEOUT     0x1
 440 #define PHY_ERROR       0x2
 441
 442 #define PHY_100 0x1
 443 #define PHY_1000        0x2
 444 #define PHY_HALF        0x100
 445
 446 /* FIXME: MII defines that should be added to <linux/mii.h> */
 447 #define MII_1000BT_CR   0x09
 448 #define MII_1000BT_SR   0x0a
 449 #define ADVERTISE_1000FULL      0x0200
 450 #define ADVERTISE_1000HALF      0x0100
 451 #define LPA_1000FULL    0x0800
 452 #define LPA_1000HALF    0x0400
 453
 454
 455 /*
 456  * SMP locking:
 457  * All hardware access under dev->priv->lock, except the performance
 458  * critical parts:
 459  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 460  *      by the arch code for interrupts.
 461  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 462  *      needs dev->priv->lock :-(
 463  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 464  */
 465
 466 /* in dev: base, irq */
 467 struct fe_priv {
 468         spinlock_t lock;
 469
 470         /* General data:
 471          * Locking: spin_lock(&np->lock); */
 472         struct net_device_stats stats;
 473         int in_shutdown;
 474         u32 linkspeed;
 475         int duplex;
 476         int autoneg;
 477         int fixed_mode;
 478         int phyaddr;
 479         int wolenabled;
 480         unsigned int phy_oui;
 481         u16 gigabit;
 482
 483         /* General data: RO fields */
 484         dma_addr_t ring_addr;
 485         struct pci_dev *pci_dev;
 486         u32 orig_mac[2];
 487         u32 irqmask;
 488         u32 desc_ver;
 489
 490         void __iomem *base;
 491
 492         /* rx specific fields.
 493          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 494          */
 495         ring_type rx_ring;
 496         unsigned int cur_rx, refill_rx;
 497         struct sk_buff *rx_skbuff[RX_RING];
 498         dma_addr_t rx_dma[RX_RING];
 499         unsigned int rx_buf_sz;
 500         unsigned int pkt_limit;
 501         struct timer_list oom_kick;
 502         struct timer_list nic_poll;
 503
 504         /* media detection workaround.
 505          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 506          */
 507         int need_linktimer;
 508         unsigned long link_timeout;
 509         /*
 510          * tx specific fields.
 511          */
 512         ring_type tx_ring;
 513         unsigned int next_tx, nic_tx;
 514         struct sk_buff *tx_skbuff[TX_RING];
 515         dma_addr_t tx_dma[TX_RING];
 516         u32 tx_flags;
 517 };
 518
 519 /*
 520  * Maximum number of loops until we assume that a bit in the irq mask
 521  * is stuck. Overridable with module param.
 522  */
 523 static int max_interrupt_work = 5;
 524
 525 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 526 {
 527         return netdev_priv(dev);
 528 }
 529
 530 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 531 {
 532         return get_nvpriv(dev)->base;
 533 }
 534
 535 static inline void pci_push(u8 __iomem *base)
 536 {
 537         /* force out pending posted writes */
 538         readl(base);
 539 }
 540
 541 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 542 {
 543         return le32_to_cpu(prd->FlagLen)
 544                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 545 }
 546
 547 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 548 {
 549         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 550 }
 551
 552 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 553                                 int delay, int delaymax, const char *msg)
 554 {
 555         u8 __iomem *base = get_hwbase(dev);
 556
 557         pci_push(base);
 558         do {
 559                 udelay(delay);
 560                 delaymax -= delay;
 561                 if (delaymax < 0) {
 562                         if (msg)
 563                                 printk(msg);
 564                         return 1;
 565                 }
 566         } while ((readl(base + offset) & mask) != target);
 567         return 0;
 568 }
 569
 570 #define MII_READ        (-1)
 571 /* mii_rw: read/write a register on the PHY.
 572  *
 573  * Caller must guarantee serialization
 574  */
 575 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 576 {
 577         u8 __iomem *base = get_hwbase(dev);
 578         u32 reg;
 579         int retval;
 580
 581         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 582
 583         reg = readl(base + NvRegMIIControl);
 584         if (reg & NVREG_MIICTL_INUSE) {
 585                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 586                 udelay(NV_MIIBUSY_DELAY);
 587         }
 588
 589         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 590         if (value != MII_READ) {
 591                 writel(value, base + NvRegMIIData);
 592                 reg |= NVREG_MIICTL_WRITE;
 593         }
 594         writel(reg, base + NvRegMIIControl);
 595
 596         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 597                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 598                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 599                                 dev->name, miireg, addr);
 600                 retval = -1;
 601         } else if (value != MII_READ) {
 602                 /* it was a write operation - fewer failures are detectable */
 603                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
 604                                 dev->name, value, miireg, addr);
 605                 retval = 0;
 606         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 607                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
 608                                 dev->name, miireg, addr);
 609                 retval = -1;
 610         } else {
 611                 retval = readl(base + NvRegMIIData);
 612                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
 613                                 dev->name, miireg, addr, retval);
 614         }
 615
 616         return retval;
 617 }
 618
 619 static int phy_reset(struct net_device *dev)
 620 {
 621         struct fe_priv *np = get_nvpriv(dev);
 622         u32 miicontrol;
 623         unsigned int tries = 0;
 624
 625         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 626         miicontrol |= BMCR_RESET;
 627         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
 628                 return -1;
 629         }
 630
 631         /* wait for 500ms */
 632         msleep(500);
 633
 634         /* must wait till reset is deasserted */
 635         while (miicontrol & BMCR_RESET) {
 636                 msleep(10);
 637                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 638                 /* FIXME: 100 tries seem excessive */
 639                 if (tries++ > 100)
 640                         return -1;
 641         }
 642         return 0;
 643 }
 644
 645 static int phy_init(struct net_device *dev)
 646 {
 647         struct fe_priv *np = get_nvpriv(dev);
 648         u8 __iomem *base = get_hwbase(dev);
 649         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
 650
 651         /* set advertise register */
 652         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
 653         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
 654         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
 655                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
 656                 return PHY_ERROR;
 657         }
 658
 659         /* get phy interface type */
 660         phyinterface = readl(base + NvRegPhyInterface);
 661
 662         /* see if gigabit phy */
 663         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
 664         if (mii_status & PHY_GIGABIT) {
 665                 np->gigabit = PHY_GIGABIT;
 666                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
 667                 mii_control_1000 &= ~ADVERTISE_1000HALF;
 668                 if (phyinterface & PHY_RGMII)
 669                         mii_control_1000 |= ADVERTISE_1000FULL;
 670                 else
 671                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 672
 673                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
 674                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 675                         return PHY_ERROR;
 676                 }
 677         }
 678         else
 679                 np->gigabit = 0;
 680
 681         /* reset the phy */
 682         if (phy_reset(dev)) {
 683                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
 684                 return PHY_ERROR;
 685         }
 686
 687         /* phy vendor specific configuration */
 688         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
 689                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
 690                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
 691                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
 692                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
 693                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 694                         return PHY_ERROR;
 695                 }
 696                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
 697                 phy_reserved |= PHY_INIT5;
 698                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
 699                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 700                         return PHY_ERROR;
 701                 }
 702         }
 703         if (np->phy_oui == PHY_OUI_CICADA) {
 704                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
 705                 phy_reserved |= PHY_INIT6;
 706                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
 707                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 708                         return PHY_ERROR;
 709                 }
 710         }
 711
 712         /* restart auto negotiation */
 713         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 714         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
 715         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
 716                 return PHY_ERROR;
 717         }
 718
 719         return 0;
 720 }
 721
 722 static void nv_start_rx(struct net_device *dev)
 723 {
 724         struct fe_priv *np = get_nvpriv(dev);
 725         u8 __iomem *base = get_hwbase(dev);
 726
 727         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
 728         /* Already running? Stop it. */
 729         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
 730                 writel(0, base + NvRegReceiverControl);
 731                 pci_push(base);
 732         }
 733         writel(np->linkspeed, base + NvRegLinkSpeed);
 734         pci_push(base);
 735         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
 736         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
 737                                 dev->name, np->duplex, np->linkspeed);
 738         pci_push(base);
 739 }
 740
 741 static void nv_stop_rx(struct net_device *dev)
 742 {
 743         u8 __iomem *base = get_hwbase(dev);
 744
 745         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
 746         writel(0, base + NvRegReceiverControl);
 747         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
 748                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
 749                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
 750
 751         udelay(NV_RXSTOP_DELAY2);
 752         writel(0, base + NvRegLinkSpeed);
 753 }
 754
 755 static void nv_start_tx(struct net_device *dev)
 756 {
 757         u8 __iomem *base = get_hwbase(dev);
 758
 759         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
 760         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
 761         pci_push(base);
 762 }
 763
 764 static void nv_stop_tx(struct net_device *dev)
 765 {
 766         u8 __iomem *base = get_hwbase(dev);
 767
 768         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
 769         writel(0, base + NvRegTransmitterControl);
 770         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
 771                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
 772                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
 773
 774         udelay(NV_TXSTOP_DELAY2);
 775         writel(0, base + NvRegUnknownTransmitterReg);
 776 }
 777
 778 static void nv_txrx_reset(struct net_device *dev)
 779 {
 780         struct fe_priv *np = get_nvpriv(dev);
 781         u8 __iomem *base = get_hwbase(dev);
 782
 783         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
 784         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
 785         pci_push(base);
 786         udelay(NV_TXRX_RESET_DELAY);
 787         writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
 788         pci_push(base);
 789 }
 790
 791 /*
 792  * nv_get_stats: dev->get_stats function
 793  * Get latest stats value from the nic.
 794  * Called with read_lock(&dev_base_lock) held for read -
 795  * only synchronized against unregister_netdevice.
 796  */
 797 static struct net_device_stats *nv_get_stats(struct net_device *dev)
 798 {
 799         struct fe_priv *np = get_nvpriv(dev);
 800
 801         /* It seems that the nic always generates interrupts and doesn't
 802          * accumulate errors internally. Thus the current values in np->stats
 803          * are already up to date.
 804          */
 805         return &np->stats;
 806 }
 807
 808 /*
 809  * nv_alloc_rx: fill rx ring entries.
 810  * Return 1 if the allocations for the skbs failed and the
 811  * rx engine is without Available descriptors
 812  */
 813 static int nv_alloc_rx(struct net_device *dev)
 814 {
 815         struct fe_priv *np = get_nvpriv(dev);
 816         unsigned int refill_rx = np->refill_rx;
 817         int nr;
 818
 819         while (np->cur_rx != refill_rx) {
 820                 struct sk_buff *skb;
 821
 822                 nr = refill_rx % RX_RING;
 823                 if (np->rx_skbuff[nr] == NULL) {
 824
 825                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
 826                         if (!skb)
 827                                 break;
 828
 829                         skb->dev = dev;
 830                         np->rx_skbuff[nr] = skb;
 831                 } else {
 832                         skb = np->rx_skbuff[nr];
 833                 }
 834                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
 835                                                 PCI_DMA_FROMDEVICE);
 836                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 837                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
 838                         wmb();
 839                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
 840                 } else {
 841                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
 842                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
 843                         wmb();
 844                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
 845                 }
 846                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
 847                                         dev->name, refill_rx);
 848                 refill_rx++;
 849         }
 850         np->refill_rx = refill_rx;
 851         if (np->cur_rx - refill_rx == RX_RING)
 852                 return 1;
 853         return 0;
 854 }
 855
 856 static void nv_do_rx_refill(unsigned long data)
 857 {
 858         struct net_device *dev = (struct net_device *) data;
 859         struct fe_priv *np = get_nvpriv(dev);
 860
 861         disable_irq(dev->irq);
 862         if (nv_alloc_rx(dev)) {
 863                 spin_lock(&np->lock);
 864                 if (!np->in_shutdown)
 865                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
 866                 spin_unlock(&np->lock);
 867         }
 868         enable_irq(dev->irq);
 869 }
 870
 871 static void nv_init_rx(struct net_device *dev)
 872 {
 873         struct fe_priv *np = get_nvpriv(dev);
 874         int i;
 875
 876         np->cur_rx = RX_RING;
 877         np->refill_rx = 0;
 878         for (i = 0; i < RX_RING; i++)
 879                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 880                         np->rx_ring.orig[i].FlagLen = 0;
 881                 else
 882                         np->rx_ring.ex[i].FlagLen = 0;
 883 }
 884
 885 static void nv_init_tx(struct net_device *dev)
 886 {
 887         struct fe_priv *np = get_nvpriv(dev);
 888         int i;
 889
 890         np->next_tx = np->nic_tx = 0;
 891         for (i = 0; i < TX_RING; i++)
 892                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 893                         np->tx_ring.orig[i].FlagLen = 0;
 894                 else
 895                         np->tx_ring.ex[i].FlagLen = 0;
 896 }
 897
 898 static int nv_init_ring(struct net_device *dev)
 899 {
 900         nv_init_tx(dev);
 901         nv_init_rx(dev);
 902         return nv_alloc_rx(dev);
 903 }
 904
 905 static void nv_drain_tx(struct net_device *dev)
 906 {
 907         struct fe_priv *np = get_nvpriv(dev);
 908         int i;
 909         for (i = 0; i < TX_RING; i++) {
 910                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 911                         np->tx_ring.orig[i].FlagLen = 0;
 912                 else
 913                         np->tx_ring.ex[i].FlagLen = 0;
 914                 if (np->tx_skbuff[i]) {
 915                         pci_unmap_single(np->pci_dev, np->tx_dma[i],
 916                                                 np->tx_skbuff[i]->len,
 917                                                 PCI_DMA_TODEVICE);
 918                         dev_kfree_skb(np->tx_skbuff[i]);
 919                         np->tx_skbuff[i] = NULL;
 920                         np->stats.tx_dropped++;
 921                 }
 922         }
 923 }
 924
 925 static void nv_drain_rx(struct net_device *dev)
 926 {
 927         struct fe_priv *np = get_nvpriv(dev);
 928         int i;
 929         for (i = 0; i < RX_RING; i++) {
 930                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 931                         np->rx_ring.orig[i].FlagLen = 0;
 932                 else
 933                         np->rx_ring.ex[i].FlagLen = 0;
 934                 wmb();
 935                 if (np->rx_skbuff[i]) {
 936                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
 937                                                 np->rx_skbuff[i]->len,
 938                                                 PCI_DMA_FROMDEVICE);
 939                         dev_kfree_skb(np->rx_skbuff[i]);
 940                         np->rx_skbuff[i] = NULL;
 941                 }
 942         }
 943 }
 944
 945 static void drain_ring(struct net_device *dev)
 946 {
 947         nv_drain_tx(dev);
 948         nv_drain_rx(dev);
 949 }
 950
 951 /*
 952  * nv_start_xmit: dev->hard_start_xmit function
 953  * Called with dev->xmit_lock held.
 954  */
 955 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
 956 {
 957         struct fe_priv *np = get_nvpriv(dev);
 958         int nr = np->next_tx % TX_RING;
 959
 960         np->tx_skbuff[nr] = skb;
 961         np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
 962                                         PCI_DMA_TODEVICE);
 963
 964         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 965                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
 966         else {
 967                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
 968                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
 969         }
 970
 971         spin_lock_irq(&np->lock);
 972         wmb();
 973         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 974                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
 975         else
 976                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
 977         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
 978                                 dev->name, np->next_tx);
 979         {
 980                 int j;
 981                 for (j=0; j<64; j++) {
 982                         if ((j%16) == 0)
 983                                 dprintk("\n%03x:", j);
 984                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
 985                 }
 986                 dprintk("\n");
 987         }
 988
 989         np->next_tx++;
 990
 991         dev->trans_start = jiffies;
 992         if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
 993                 netif_stop_queue(dev);
 994         spin_unlock_irq(&np->lock);
 995         writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
 996         pci_push(get_hwbase(dev));
 997         return 0;
 998 }
 999
1000 /*
1001  * nv_tx_done: check for completed packets, release the skbs.
1002  *
1003  * Caller must own np->lock.
1004  */
1005 static void nv_tx_done(struct net_device *dev)
1006 {
1007         struct fe_priv *np = get_nvpriv(dev);
1008         u32 Flags;
1009         int i;
1010
1011         while (np->nic_tx != np->next_tx) {
1012                 i = np->nic_tx % TX_RING;
1013
1014                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1015                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1016                 else
1017                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1018
1019                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1020                                         dev->name, np->nic_tx, Flags);
1021                 if (Flags & NV_TX_VALID)
1022                         break;
1023                 if (np->desc_ver == DESC_VER_1) {
1024                         if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1025                                                         NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1026                                 if (Flags & NV_TX_UNDERFLOW)
1027                                         np->stats.tx_fifo_errors++;
1028                                 if (Flags & NV_TX_CARRIERLOST)
1029                                         np->stats.tx_carrier_errors++;
1030                                 np->stats.tx_errors++;
1031                         } else {
1032                                 np->stats.tx_packets++;
1033                                 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1034                         }
1035                 } else {
1036                         if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1037                                                         NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1038                                 if (Flags & NV_TX2_UNDERFLOW)
1039                                         np->stats.tx_fifo_errors++;
1040                                 if (Flags & NV_TX2_CARRIERLOST)
1041                                         np->stats.tx_carrier_errors++;
1042                                 np->stats.tx_errors++;
1043                         } else {
1044                                 np->stats.tx_packets++;
1045                                 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1046                         }
1047                 }
1048                 pci_unmap_single(np->pci_dev, np->tx_dma[i],
1049                                         np->tx_skbuff[i]->len,
1050                                         PCI_DMA_TODEVICE);
1051                 dev_kfree_skb_irq(np->tx_skbuff[i]);
1052                 np->tx_skbuff[i] = NULL;
1053                 np->nic_tx++;
1054         }
1055         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1056                 netif_wake_queue(dev);
1057 }
1058
1059 /*
1060  * nv_tx_timeout: dev->tx_timeout function
1061  * Called with dev->xmit_lock held.
1062  */
1063 static void nv_tx_timeout(struct net_device *dev)
1064 {
1065         struct fe_priv *np = get_nvpriv(dev);
1066         u8 __iomem *base = get_hwbase(dev);
1067
1068         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1069                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1070
1071         {
1072                 int i;
1073
1074                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1075                                 dev->name, (unsigned long)np->ring_addr,
1076                                 np->next_tx, np->nic_tx);
1077                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1078                 for (i=0;i<0x400;i+= 32) {
1079                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1080                                         i,
1081                                         readl(base + i + 0), readl(base + i + 4),
1082                                         readl(base + i + 8), readl(base + i + 12),
1083                                         readl(base + i + 16), readl(base + i + 20),
1084                                         readl(base + i + 24), readl(base + i + 28));
1085                 }
1086                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1087                 for (i=0;i<TX_RING;i+= 4) {
1088                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1089                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1090                                        i,
1091                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1092                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1093                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1094                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1095                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1096                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1097                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1098                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1099                         } else {
1100                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1101                                        i,
1102                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1103                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1104                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1105                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1106                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1107                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1108                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1109                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1110                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1111                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1112                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1113                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1114                         }
1115                 }
1116         }
1117
1118         spin_lock_irq(&np->lock);
1119
1120         /* 1) stop tx engine */
1121         nv_stop_tx(dev);
1122
1123         /* 2) check that the packets were not sent already: */
1124         nv_tx_done(dev);
1125
1126         /* 3) if there are dead entries: clear everything */
1127         if (np->next_tx != np->nic_tx) {
1128                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1129                 nv_drain_tx(dev);
1130                 np->next_tx = np->nic_tx = 0;
1131                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1132                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1133                 else
1134                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1135                 netif_wake_queue(dev);
1136         }
1137
1138         /* 4) restart tx engine */
1139         nv_start_tx(dev);
1140         spin_unlock_irq(&np->lock);
1141 }
1142
1143 /*
1144  * Called when the nic notices a mismatch between the actual data len on the
1145  * wire and the len indicated in the 802 header
1146  */
1147 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1148 {
1149         int hdrlen;     /* length of the 802 header */
1150         int protolen;   /* length as stored in the proto field */
1151
1152         /* 1) calculate len according to header */
1153         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1154                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1155                 hdrlen = VLAN_HLEN;
1156         } else {
1157                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1158                 hdrlen = ETH_HLEN;
1159         }
1160         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1161                                 dev->name, datalen, protolen, hdrlen);
1162         if (protolen > ETH_DATA_LEN)
1163                 return datalen; /* Value in proto field not a len, no checks possible */
1164
1165         protolen += hdrlen;
1166         /* consistency checks: */
1167         if (datalen > ETH_ZLEN) {
1168                 if (datalen >= protolen) {
1169                         /* more data on wire than in 802 header, trim of
1170                          * additional data.
1171                          */
1172                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1173                                         dev->name, protolen);
1174                         return protolen;
1175                 } else {
1176                         /* less data on wire than mentioned in header.
1177                          * Discard the packet.
1178                          */
1179                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1180                                         dev->name);
1181                         return -1;
1182                 }
1183         } else {
1184                 /* short packet. Accept only if 802 values are also short */
1185                 if (protolen > ETH_ZLEN) {
1186                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1187                                         dev->name);
1188                         return -1;
1189                 }
1190                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1191                                 dev->name, datalen);
1192                 return datalen;
1193         }
1194 }
1195
1196 static void nv_rx_process(struct net_device *dev)
1197 {
1198         struct fe_priv *np = get_nvpriv(dev);
1199         u32 Flags;
1200
1201         for (;;) {
1202                 struct sk_buff *skb;
1203                 int len;
1204                 int i;
1205                 if (np->cur_rx - np->refill_rx >= RX_RING)
1206                         break;  /* we scanned the whole ring - do not continue */
1207
1208                 i = np->cur_rx % RX_RING;
1209                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1210                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1211                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1212                 } else {
1213                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1214                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1215                 }
1216
1217                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1218                                         dev->name, np->cur_rx, Flags);
1219
1220                 if (Flags & NV_RX_AVAIL)
1221                         break;  /* still owned by hardware, */
1222
1223                 /*
1224                  * the packet is for us - immediately tear down the pci mapping.
1225                  * TODO: check if a prefetch of the first cacheline improves
1226                  * the performance.
1227                  */
1228                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1229                                 np->rx_skbuff[i]->len,
1230                                 PCI_DMA_FROMDEVICE);
1231
1232                 {
1233                         int j;
1234                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1235                         for (j=0; j<64; j++) {
1236                                 if ((j%16) == 0)
1237                                         dprintk("\n%03x:", j);
1238                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1239                         }
1240                         dprintk("\n");
1241                 }
1242                 /* look at what we actually got: */
1243                 if (np->desc_ver == DESC_VER_1) {
1244                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1245                                 goto next_pkt;
1246
1247                         if (Flags & NV_RX_MISSEDFRAME) {
1248                                 np->stats.rx_missed_errors++;
1249                                 np->stats.rx_errors++;
1250                                 goto next_pkt;
1251                         }
1252                         if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1253                                 np->stats.rx_errors++;
1254                                 goto next_pkt;
1255                         }
1256                         if (Flags & NV_RX_CRCERR) {
1257                                 np->stats.rx_crc_errors++;
1258                                 np->stats.rx_errors++;
1259                                 goto next_pkt;
1260                         }
1261                         if (Flags & NV_RX_OVERFLOW) {
1262                                 np->stats.rx_over_errors++;
1263                                 np->stats.rx_errors++;
1264                                 goto next_pkt;
1265                         }
1266                         if (Flags & NV_RX_ERROR4) {
1267                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1268                                 if (len < 0) {
1269                                         np->stats.rx_errors++;
1270                                         goto next_pkt;
1271                                 }
1272                         }
1273                         /* framing errors are soft errors. */
1274                         if (Flags & NV_RX_FRAMINGERR) {
1275                                 if (Flags & NV_RX_SUBSTRACT1) {
1276                                         len--;
1277                                 }
1278                         }
1279                 } else {
1280                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1281                                 goto next_pkt;
1282
1283                         if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1284                                 np->stats.rx_errors++;
1285                                 goto next_pkt;
1286                         }
1287                         if (Flags & NV_RX2_CRCERR) {
1288                                 np->stats.rx_crc_errors++;
1289                                 np->stats.rx_errors++;
1290                                 goto next_pkt;
1291                         }
1292                         if (Flags & NV_RX2_OVERFLOW) {
1293                                 np->stats.rx_over_errors++;
1294                                 np->stats.rx_errors++;
1295                                 goto next_pkt;
1296                         }
1297                         if (Flags & NV_RX2_ERROR4) {
1298                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1299                                 if (len < 0) {
1300                                         np->stats.rx_errors++;
1301                                         goto next_pkt;
1302                                 }
1303                         }
1304                         /* framing errors are soft errors */
1305                         if (Flags & NV_RX2_FRAMINGERR) {
1306                                 if (Flags & NV_RX2_SUBSTRACT1) {
1307                                         len--;
1308                                 }
1309                         }
1310                         Flags &= NV_RX2_CHECKSUMMASK;
1311                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1312                                         Flags == NV_RX2_CHECKSUMOK2 ||
1313                                         Flags == NV_RX2_CHECKSUMOK3) {
1314                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1315                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1316                         } else {
1317                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1318                         }
1319                 }
1320                 /* got a valid packet - forward it to the network core */
1321                 skb = np->rx_skbuff[i];
1322                 np->rx_skbuff[i] = NULL;
1323
1324                 skb_put(skb, len);
1325                 skb->protocol = eth_type_trans(skb, dev);
1326                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1327                                         dev->name, np->cur_rx, len, skb->protocol);
1328                 netif_rx(skb);
1329                 dev->last_rx = jiffies;
1330                 np->stats.rx_packets++;
1331                 np->stats.rx_bytes += len;
1332 next_pkt:
1333                 np->cur_rx++;
1334         }
1335 }
1336
1337 static void set_bufsize(struct net_device *dev)
1338 {
1339         struct fe_priv *np = netdev_priv(dev);
1340
1341         if (dev->mtu <= ETH_DATA_LEN)
1342                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1343         else
1344                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1345 }
1346
1347 /*
1348  * nv_change_mtu: dev->change_mtu function
1349  * Called with dev_base_lock held for read.
1350  */
1351 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1352 {
1353         struct fe_priv *np = get_nvpriv(dev);
1354         int old_mtu;
1355
1356         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1357                 return -EINVAL;
1358
1359         old_mtu = dev->mtu;
1360         dev->mtu = new_mtu;
1361
1362         /* return early if the buffer sizes will not change */
1363         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1364                 return 0;
1365         if (old_mtu == new_mtu)
1366                 return 0;
1367
1368         /* synchronized against open : rtnl_lock() held by caller */
1369         if (netif_running(dev)) {
1370                 u8 *base = get_hwbase(dev);
1371                 /*
1372                  * It seems that the nic preloads valid ring entries into an
1373                  * internal buffer. The procedure for flushing everything is
1374                  * guessed, there is probably a simpler approach.
1375                  * Changing the MTU is a rare event, it shouldn't matter.
1376                  */
1377                 disable_irq(dev->irq);
1378                 spin_lock_bh(&dev->xmit_lock);
1379                 spin_lock(&np->lock);
1380                 /* stop engines */
1381                 nv_stop_rx(dev);
1382                 nv_stop_tx(dev);
1383                 nv_txrx_reset(dev);
1384                 /* drain rx queue */
1385                 nv_drain_rx(dev);
1386                 nv_drain_tx(dev);
1387                 /* reinit driver view of the rx queue */
1388                 nv_init_rx(dev);
1389                 nv_init_tx(dev);
1390                 /* alloc new rx buffers */
1391                 set_bufsize(dev);
1392                 if (nv_alloc_rx(dev)) {
1393                         if (!np->in_shutdown)
1394                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1395                 }
1396                 /* reinit nic view of the rx queue */
1397                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1398                 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1399                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1400                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1401                 else
1402                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1403                 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1404                         base + NvRegRingSizes);
1405                 pci_push(base);
1406                 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
1407                 pci_push(base);
1408
1409                 /* restart rx engine */
1410                 nv_start_rx(dev);
1411                 nv_start_tx(dev);
1412                 spin_unlock(&np->lock);
1413                 spin_unlock_bh(&dev->xmit_lock);
1414                 enable_irq(dev->irq);
1415         }
1416         return 0;
1417 }
1418
1419 /*
1420  * nv_set_multicast: dev->set_multicast function
1421  * Called with dev->xmit_lock held.
1422  */
1423 static void nv_set_multicast(struct net_device *dev)
1424 {
1425         struct fe_priv *np = get_nvpriv(dev);
1426         u8 __iomem *base = get_hwbase(dev);
1427         u32 addr[2];
1428         u32 mask[2];
1429         u32 pff;
1430
1431         memset(addr, 0, sizeof(addr));
1432         memset(mask, 0, sizeof(mask));
1433
1434         if (dev->flags & IFF_PROMISC) {
1435                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1436                 pff = NVREG_PFF_PROMISC;
1437         } else {
1438                 pff = NVREG_PFF_MYADDR;
1439
1440                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1441                         u32 alwaysOff[2];
1442                         u32 alwaysOn[2];
1443
1444                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1445                         if (dev->flags & IFF_ALLMULTI) {
1446                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1447                         } else {
1448                                 struct dev_mc_list *walk;
1449
1450                                 walk = dev->mc_list;
1451                                 while (walk != NULL) {
1452                                         u32 a, b;
1453                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1454                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1455                                         alwaysOn[0] &= a;
1456                                         alwaysOff[0] &= ~a;
1457                                         alwaysOn[1] &= b;
1458                                         alwaysOff[1] &= ~b;
1459                                         walk = walk->next;
1460                                 }
1461                         }
1462                         addr[0] = alwaysOn[0];
1463                         addr[1] = alwaysOn[1];
1464                         mask[0] = alwaysOn[0] | alwaysOff[0];
1465                         mask[1] = alwaysOn[1] | alwaysOff[1];
1466                 }
1467         }
1468         addr[0] |= NVREG_MCASTADDRA_FORCE;
1469         pff |= NVREG_PFF_ALWAYS;
1470         spin_lock_irq(&np->lock);
1471         nv_stop_rx(dev);
1472         writel(addr[0], base + NvRegMulticastAddrA);
1473         writel(addr[1], base + NvRegMulticastAddrB);
1474         writel(mask[0], base + NvRegMulticastMaskA);
1475         writel(mask[1], base + NvRegMulticastMaskB);
1476         writel(pff, base + NvRegPacketFilterFlags);
1477         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1478                 dev->name);
1479         nv_start_rx(dev);
1480         spin_unlock_irq(&np->lock);
1481 }
1482
1483 static int nv_update_linkspeed(struct net_device *dev)
1484 {
1485         struct fe_priv *np = get_nvpriv(dev);
1486         u8 __iomem *base = get_hwbase(dev);
1487         int adv, lpa;
1488         int newls = np->linkspeed;
1489         int newdup = np->duplex;
1490         int mii_status;
1491         int retval = 0;
1492         u32 control_1000, status_1000, phyreg;
1493
1494         /* BMSR_LSTATUS is latched, read it twice:
1495          * we want the current value.
1496          */
1497         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1498         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1499
1500         if (!(mii_status & BMSR_LSTATUS)) {
1501                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1502                                 dev->name);
1503                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1504                 newdup = 0;
1505                 retval = 0;
1506                 goto set_speed;
1507         }
1508
1509         if (np->autoneg == 0) {
1510                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1511                                 dev->name, np->fixed_mode);
1512                 if (np->fixed_mode & LPA_100FULL) {
1513                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1514                         newdup = 1;
1515                 } else if (np->fixed_mode & LPA_100HALF) {
1516                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1517                         newdup = 0;
1518                 } else if (np->fixed_mode & LPA_10FULL) {
1519                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1520                         newdup = 1;
1521                 } else {
1522                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1523                         newdup = 0;
1524                 }
1525                 retval = 1;
1526                 goto set_speed;
1527         }
1528         /* check auto negotiation is complete */
1529         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1530                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1531                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1532                 newdup = 0;
1533                 retval = 0;
1534                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1535                 goto set_speed;
1536         }
1537
1538         retval = 1;
1539         if (np->gigabit == PHY_GIGABIT) {
1540                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1541                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1542
1543                 if ((control_1000 & ADVERTISE_1000FULL) &&
1544                         (status_1000 & LPA_1000FULL)) {
1545                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1546                                 dev->name);
1547                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1548                         newdup = 1;
1549                         goto set_speed;
1550                 }
1551         }
1552
1553         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1554         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1555         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1556                                 dev->name, adv, lpa);
1557
1558         /* FIXME: handle parallel detection properly */
1559         lpa = lpa & adv;
1560         if (lpa & LPA_100FULL) {
1561                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1562                 newdup = 1;
1563         } else if (lpa & LPA_100HALF) {
1564                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1565                 newdup = 0;
1566         } else if (lpa & LPA_10FULL) {
1567                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1568                 newdup = 1;
1569         } else if (lpa & LPA_10HALF) {
1570                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1571                 newdup = 0;
1572         } else {
1573                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1574                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1575                 newdup = 0;
1576         }
1577
1578 set_speed:
1579         if (np->duplex == newdup && np->linkspeed == newls)
1580                 return retval;
1581
1582         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1583                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1584
1585         np->duplex = newdup;
1586         np->linkspeed = newls;
1587
1588         if (np->gigabit == PHY_GIGABIT) {
1589                 phyreg = readl(base + NvRegRandomSeed);
1590                 phyreg &= ~(0x3FF00);
1591                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1592                         phyreg |= NVREG_RNDSEED_FORCE3;
1593                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1594                         phyreg |= NVREG_RNDSEED_FORCE2;
1595                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1596                         phyreg |= NVREG_RNDSEED_FORCE;
1597                 writel(phyreg, base + NvRegRandomSeed);
1598         }
1599
1600         phyreg = readl(base + NvRegPhyInterface);
1601         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1602         if (np->duplex == 0)
1603                 phyreg |= PHY_HALF;
1604         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1605                 phyreg |= PHY_100;
1606         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1607                 phyreg |= PHY_1000;
1608         writel(phyreg, base + NvRegPhyInterface);
1609
1610         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1611                 base + NvRegMisc1);
1612         pci_push(base);
1613         writel(np->linkspeed, base + NvRegLinkSpeed);
1614         pci_push(base);
1615
1616         return retval;
1617 }
1618
1619 static void nv_linkchange(struct net_device *dev)
1620 {
1621         if (nv_update_linkspeed(dev)) {
1622                 if (netif_carrier_ok(dev)) {
1623                         nv_stop_rx(dev);
1624                 } else {
1625                         netif_carrier_on(dev);
1626                         printk(KERN_INFO "%s: link up.\n", dev->name);
1627                 }
1628                 nv_start_rx(dev);
1629         } else {
1630                 if (netif_carrier_ok(dev)) {
1631                         netif_carrier_off(dev);
1632                         printk(KERN_INFO "%s: link down.\n", dev->name);
1633                         nv_stop_rx(dev);
1634                 }
1635         }
1636 }
1637
1638 static void nv_link_irq(struct net_device *dev)
1639 {
1640         u8 __iomem *base = get_hwbase(dev);
1641         u32 miistat;
1642
1643         miistat = readl(base + NvRegMIIStatus);
1644         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1645         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1646
1647         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1648                 nv_linkchange(dev);
1649         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1650 }
1651
1652 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1653 {
1654         struct net_device *dev = (struct net_device *) data;
1655         struct fe_priv *np = get_nvpriv(dev);
1656         u8 __iomem *base = get_hwbase(dev);
1657         u32 events;
1658         int i;
1659
1660         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1661
1662         for (i=0; ; i++) {
1663                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1664                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1665                 pci_push(base);
1666                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1667                 if (!(events & np->irqmask))
1668                         break;
1669
1670                 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
1671                         spin_lock(&np->lock);
1672                         nv_tx_done(dev);
1673                         spin_unlock(&np->lock);
1674                 }
1675
1676                 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1677                         nv_rx_process(dev);
1678                         if (nv_alloc_rx(dev)) {
1679                                 spin_lock(&np->lock);
1680                                 if (!np->in_shutdown)
1681                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1682                                 spin_unlock(&np->lock);
1683                         }
1684                 }
1685
1686                 if (events & NVREG_IRQ_LINK) {
1687                         spin_lock(&np->lock);
1688                         nv_link_irq(dev);
1689                         spin_unlock(&np->lock);
1690                 }
1691                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1692                         spin_lock(&np->lock);
1693                         nv_linkchange(dev);
1694                         spin_unlock(&np->lock);
1695                         np->link_timeout = jiffies + LINK_TIMEOUT;
1696                 }
1697                 if (events & (NVREG_IRQ_TX_ERR)) {
1698                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1699                                                 dev->name, events);
1700                 }
1701                 if (events & (NVREG_IRQ_UNKNOWN)) {
1702                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1703                                                 dev->name, events);
1704                 }
1705                 if (i > max_interrupt_work) {
1706                         spin_lock(&np->lock);
1707                         /* disable interrupts on the nic */
1708                         writel(0, base + NvRegIrqMask);
1709                         pci_push(base);
1710
1711                         if (!np->in_shutdown)
1712                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1713                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1714                         spin_unlock(&np->lock);
1715                         break;
1716                 }
1717
1718         }
1719         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1720
1721         return IRQ_RETVAL(i);
1722 }
1723
1724 static void nv_do_nic_poll(unsigned long data)
1725 {
1726         struct net_device *dev = (struct net_device *) data;
1727         struct fe_priv *np = get_nvpriv(dev);
1728         u8 __iomem *base = get_hwbase(dev);
1729
1730         disable_irq(dev->irq);
1731         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1732         /*
1733          * reenable interrupts on the nic, we have to do this before calling
1734          * nv_nic_irq because that may decide to do otherwise
1735          */
1736         writel(np->irqmask, base + NvRegIrqMask);
1737         pci_push(base);
1738         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1739         enable_irq(dev->irq);
1740 }
1741
1742 #ifdef CONFIG_NET_POLL_CONTROLLER
1743 static void nv_poll_controller(struct net_device *dev)
1744 {
1745         nv_do_nic_poll((unsigned long) dev);
1746 }
1747 #endif
1748
1749 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1750 {
1751         struct fe_priv *np = get_nvpriv(dev);
1752         strcpy(info->driver, "forcedeth");
1753         strcpy(info->version, FORCEDETH_VERSION);
1754         strcpy(info->bus_info, pci_name(np->pci_dev));
1755 }
1756
1757 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1758 {
1759         struct fe_priv *np = get_nvpriv(dev);
1760         wolinfo->supported = WAKE_MAGIC;
1761
1762         spin_lock_irq(&np->lock);
1763         if (np->wolenabled)
1764                 wolinfo->wolopts = WAKE_MAGIC;
1765         spin_unlock_irq(&np->lock);
1766 }
1767
1768 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1769 {
1770         struct fe_priv *np = get_nvpriv(dev);
1771         u8 __iomem *base = get_hwbase(dev);
1772
1773         spin_lock_irq(&np->lock);
1774         if (wolinfo->wolopts == 0) {
1775                 writel(0, base + NvRegWakeUpFlags);
1776                 np->wolenabled = 0;
1777         }
1778         if (wolinfo->wolopts & WAKE_MAGIC) {
1779                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1780                 np->wolenabled = 1;
1781         }
1782         spin_unlock_irq(&np->lock);
1783         return 0;
1784 }
1785
1786 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1787 {
1788         struct fe_priv *np = netdev_priv(dev);
1789         int adv;
1790
1791         spin_lock_irq(&np->lock);
1792         ecmd->port = PORT_MII;
1793         if (!netif_running(dev)) {
1794                 /* We do not track link speed / duplex setting if the
1795                  * interface is disabled. Force a link check */
1796                 nv_update_linkspeed(dev);
1797         }
1798         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1799                 case NVREG_LINKSPEED_10:
1800                         ecmd->speed = SPEED_10;
1801                         break;
1802                 case NVREG_LINKSPEED_100:
1803                         ecmd->speed = SPEED_100;
1804                         break;
1805                 case NVREG_LINKSPEED_1000:
1806                         ecmd->speed = SPEED_1000;
1807                         break;
1808         }
1809         ecmd->duplex = DUPLEX_HALF;
1810         if (np->duplex)
1811                 ecmd->duplex = DUPLEX_FULL;
1812
1813         ecmd->autoneg = np->autoneg;
1814
1815         ecmd->advertising = ADVERTISED_MII;
1816         if (np->autoneg) {
1817                 ecmd->advertising |= ADVERTISED_Autoneg;
1818                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1819         } else {
1820                 adv = np->fixed_mode;
1821         }
1822         if (adv & ADVERTISE_10HALF)
1823                 ecmd->advertising |= ADVERTISED_10baseT_Half;
1824         if (adv & ADVERTISE_10FULL)
1825                 ecmd->advertising |= ADVERTISED_10baseT_Full;
1826         if (adv & ADVERTISE_100HALF)
1827                 ecmd->advertising |= ADVERTISED_100baseT_Half;
1828         if (adv & ADVERTISE_100FULL)
1829                 ecmd->advertising |= ADVERTISED_100baseT_Full;
1830         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1831                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1832                 if (adv & ADVERTISE_1000FULL)
1833                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
1834         }
1835
1836         ecmd->supported = (SUPPORTED_Autoneg |
1837                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1838                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1839                 SUPPORTED_MII);
1840         if (np->gigabit == PHY_GIGABIT)
1841                 ecmd->supported |= SUPPORTED_1000baseT_Full;
1842
1843         ecmd->phy_address = np->phyaddr;
1844         ecmd->transceiver = XCVR_EXTERNAL;
1845
1846         /* ignore maxtxpkt, maxrxpkt for now */
1847         spin_unlock_irq(&np->lock);
1848         return 0;
1849 }
1850
1851 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1852 {
1853         struct fe_priv *np = netdev_priv(dev);
1854
1855         if (ecmd->port != PORT_MII)
1856                 return -EINVAL;
1857         if (ecmd->transceiver != XCVR_EXTERNAL)
1858                 return -EINVAL;
1859         if (ecmd->phy_address != np->phyaddr) {
1860                 /* TODO: support switching between multiple phys. Should be
1861                  * trivial, but not enabled due to lack of test hardware. */
1862                 return -EINVAL;
1863         }
1864         if (ecmd->autoneg == AUTONEG_ENABLE) {
1865                 u32 mask;
1866
1867                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1868                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
1869                 if (np->gigabit == PHY_GIGABIT)
1870                         mask |= ADVERTISED_1000baseT_Full;
1871
1872                 if ((ecmd->advertising & mask) == 0)
1873                         return -EINVAL;
1874
1875         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
1876                 /* Note: autonegotiation disable, speed 1000 intentionally
1877                  * forbidden - noone should need that. */
1878
1879                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1880                         return -EINVAL;
1881                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1882                         return -EINVAL;
1883         } else {
1884                 return -EINVAL;
1885         }
1886
1887         spin_lock_irq(&np->lock);
1888         if (ecmd->autoneg == AUTONEG_ENABLE) {
1889                 int adv, bmcr;
1890
1891                 np->autoneg = 1;
1892
1893                 /* advertise only what has been requested */
1894                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1895                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1896                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
1897                         adv |= ADVERTISE_10HALF;
1898                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
1899                         adv |= ADVERTISE_10FULL;
1900                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
1901                         adv |= ADVERTISE_100HALF;
1902                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
1903                         adv |= ADVERTISE_100FULL;
1904                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1905
1906                 if (np->gigabit == PHY_GIGABIT) {
1907                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1908                         adv &= ~ADVERTISE_1000FULL;
1909                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
1910                                 adv |= ADVERTISE_1000FULL;
1911                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1912                 }
1913
1914                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1915                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1916                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1917
1918         } else {
1919                 int adv, bmcr;
1920
1921                 np->autoneg = 0;
1922
1923                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1924                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1925                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
1926                         adv |= ADVERTISE_10HALF;
1927                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
1928                         adv |= ADVERTISE_10FULL;
1929                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
1930                         adv |= ADVERTISE_100HALF;
1931                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
1932                         adv |= ADVERTISE_100FULL;
1933                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1934                 np->fixed_mode = adv;
1935
1936                 if (np->gigabit == PHY_GIGABIT) {
1937                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1938                         adv &= ~ADVERTISE_1000FULL;
1939                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1940                 }
1941
1942                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1943                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
1944                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
1945                         bmcr |= BMCR_FULLDPLX;
1946                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
1947                         bmcr |= BMCR_SPEED100;
1948                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1949
1950                 if (netif_running(dev)) {
1951                         /* Wait a bit and then reconfigure the nic. */
1952                         udelay(10);
1953                         nv_linkchange(dev);
1954                 }
1955         }
1956         spin_unlock_irq(&np->lock);
1957
1958         return 0;
1959 }
1960
1961 #define FORCEDETH_REGS_VER      1
1962 #define FORCEDETH_REGS_SIZE     0x400 /* 256 32-bit registers */
1963
1964 static int nv_get_regs_len(struct net_device *dev)
1965 {
1966         return FORCEDETH_REGS_SIZE;
1967 }
1968
1969 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1970 {
1971         struct fe_priv *np = get_nvpriv(dev);
1972         u8 __iomem *base = get_hwbase(dev);
1973         u32 *rbuf = buf;
1974         int i;
1975
1976         regs->version = FORCEDETH_REGS_VER;
1977         spin_lock_irq(&np->lock);
1978         for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
1979                 rbuf[i] = readl(base + i*sizeof(u32));
1980         spin_unlock_irq(&np->lock);
1981 }
1982
1983 static int nv_nway_reset(struct net_device *dev)
1984 {
1985         struct fe_priv *np = get_nvpriv(dev);
1986         int ret;
1987
1988         spin_lock_irq(&np->lock);
1989         if (np->autoneg) {
1990                 int bmcr;
1991
1992                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1993                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1994                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1995
1996                 ret = 0;
1997         } else {
1998                 ret = -EINVAL;
1999         }
2000         spin_unlock_irq(&np->lock);
2001
2002         return ret;
2003 }
2004
2005 static struct ethtool_ops ops = {
2006         .get_drvinfo = nv_get_drvinfo,
2007         .get_link = ethtool_op_get_link,
2008         .get_wol = nv_get_wol,
2009         .set_wol = nv_set_wol,
2010         .get_settings = nv_get_settings,
2011         .set_settings = nv_set_settings,
2012         .get_regs_len = nv_get_regs_len,
2013         .get_regs = nv_get_regs,
2014         .nway_reset = nv_nway_reset,
2015 };
2016
2017 static int nv_open(struct net_device *dev)
2018 {
2019         struct fe_priv *np = get_nvpriv(dev);
2020         u8 __iomem *base = get_hwbase(dev);
2021         int ret, oom, i;
2022
2023         dprintk(KERN_DEBUG "nv_open: begin\n");
2024
2025         /* 1) erase previous misconfiguration */
2026         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2027         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2028         writel(0, base + NvRegMulticastAddrB);
2029         writel(0, base + NvRegMulticastMaskA);
2030         writel(0, base + NvRegMulticastMaskB);
2031         writel(0, base + NvRegPacketFilterFlags);
2032
2033         writel(0, base + NvRegTransmitterControl);
2034         writel(0, base + NvRegReceiverControl);
2035
2036         writel(0, base + NvRegAdapterControl);
2037
2038         /* 2) initialize descriptor rings */
2039         set_bufsize(dev);
2040         oom = nv_init_ring(dev);
2041
2042         writel(0, base + NvRegLinkSpeed);
2043         writel(0, base + NvRegUnknownTransmitterReg);
2044         nv_txrx_reset(dev);
2045         writel(0, base + NvRegUnknownSetupReg6);
2046
2047         np->in_shutdown = 0;
2048
2049         /* 3) set mac address */
2050         {
2051                 u32 mac[2];
2052
2053                 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2054                                 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2055                 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2056
2057                 writel(mac[0], base + NvRegMacAddrA);
2058                 writel(mac[1], base + NvRegMacAddrB);
2059         }
2060
2061         /* 4) give hw rings */
2062         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2063         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2064                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2065         else
2066                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2067         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2068                 base + NvRegRingSizes);
2069
2070         /* 5) continue setup */
2071         writel(np->linkspeed, base + NvRegLinkSpeed);
2072         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2073         writel(np->desc_ver, base + NvRegTxRxControl);
2074         pci_push(base);
2075         writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
2076         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2077                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2078                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2079
2080         writel(0, base + NvRegUnknownSetupReg4);
2081         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2082         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2083
2084         /* 6) continue setup */
2085         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2086         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2087         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2088         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2089
2090         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2091         get_random_bytes(&i, sizeof(i));
2092         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2093         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2094         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2095         writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
2096         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2097         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2098                         base + NvRegAdapterControl);
2099         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2100         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2101         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2102
2103         i = readl(base + NvRegPowerState);
2104         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2105                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2106
2107         pci_push(base);
2108         udelay(10);
2109         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2110
2111         writel(0, base + NvRegIrqMask);
2112         pci_push(base);
2113         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2114         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2115         pci_push(base);
2116
2117         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2118         if (ret)
2119                 goto out_drain;
2120
2121         /* ask for interrupts */
2122         writel(np->irqmask, base + NvRegIrqMask);
2123
2124         spin_lock_irq(&np->lock);
2125         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2126         writel(0, base + NvRegMulticastAddrB);
2127         writel(0, base + NvRegMulticastMaskA);
2128         writel(0, base + NvRegMulticastMaskB);
2129         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2130         /* One manual link speed update: Interrupts are enabled, future link
2131          * speed changes cause interrupts and are handled by nv_link_irq().
2132          */
2133         {
2134                 u32 miistat;
2135                 miistat = readl(base + NvRegMIIStatus);
2136                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2137                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2138         }
2139         ret = nv_update_linkspeed(dev);
2140         nv_start_rx(dev);
2141         nv_start_tx(dev);
2142         netif_start_queue(dev);
2143         if (ret) {
2144                 netif_carrier_on(dev);
2145         } else {
2146                 printk("%s: no link during initialization.\n", dev->name);
2147                 netif_carrier_off(dev);
2148         }
2149         if (oom)
2150                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2151         spin_unlock_irq(&np->lock);
2152
2153         return 0;
2154 out_drain:
2155         drain_ring(dev);
2156         return ret;
2157 }
2158
2159 static int nv_close(struct net_device *dev)
2160 {
2161         struct fe_priv *np = get_nvpriv(dev);
2162         u8 __iomem *base;
2163
2164         spin_lock_irq(&np->lock);
2165         np->in_shutdown = 1;
2166         spin_unlock_irq(&np->lock);
2167         synchronize_irq(dev->irq);
2168
2169         del_timer_sync(&np->oom_kick);
2170         del_timer_sync(&np->nic_poll);
2171
2172         netif_stop_queue(dev);
2173         spin_lock_irq(&np->lock);
2174         nv_stop_tx(dev);
2175         nv_stop_rx(dev);
2176         nv_txrx_reset(dev);
2177
2178         /* disable interrupts on the nic or we will lock up */
2179         base = get_hwbase(dev);
2180         writel(0, base + NvRegIrqMask);
2181         pci_push(base);
2182         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2183
2184         spin_unlock_irq(&np->lock);
2185
2186         free_irq(dev->irq, dev);
2187
2188         drain_ring(dev);
2189
2190         if (np->wolenabled)
2191                 nv_start_rx(dev);
2192
2193         /* FIXME: power down nic */
2194
2195         return 0;
2196 }
2197
2198 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2199 {
2200         struct net_device *dev;
2201         struct fe_priv *np;
2202         unsigned long addr;
2203         u8 __iomem *base;
2204         int err, i;
2205
2206         dev = alloc_etherdev(sizeof(struct fe_priv));
2207         err = -ENOMEM;
2208         if (!dev)
2209                 goto out;
2210
2211         np = get_nvpriv(dev);
2212         np->pci_dev = pci_dev;
2213         spin_lock_init(&np->lock);
2214         SET_MODULE_OWNER(dev);
2215         SET_NETDEV_DEV(dev, &pci_dev->dev);
2216
2217         init_timer(&np->oom_kick);
2218         np->oom_kick.data = (unsigned long) dev;
2219         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
2220         init_timer(&np->nic_poll);
2221         np->nic_poll.data = (unsigned long) dev;
2222         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
2223
2224         err = pci_enable_device(pci_dev);
2225         if (err) {
2226                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2227                                 err, pci_name(pci_dev));
2228                 goto out_free;
2229         }
2230
2231         pci_set_master(pci_dev);
2232
2233         err = pci_request_regions(pci_dev, DRV_NAME);
2234         if (err < 0)
2235                 goto out_disable;
2236
2237         err = -EINVAL;
2238         addr = 0;
2239         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2240                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2241                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2242                                 pci_resource_len(pci_dev, i),
2243                                 pci_resource_flags(pci_dev, i));
2244                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2245                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2246                         addr = pci_resource_start(pci_dev, i);
2247                         break;
2248                 }
2249         }
2250         if (i == DEVICE_COUNT_RESOURCE) {
2251                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2252                                         pci_name(pci_dev));
2253                 goto out_relreg;
2254         }
2255
2256         /* handle different descriptor versions */
2257         if (id->driver_data & DEV_HAS_HIGH_DMA) {
2258                 /* packet format 3: supports 40-bit addressing */
2259                 np->desc_ver = DESC_VER_3;
2260                 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2261                         printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2262                                         pci_name(pci_dev));
2263                 }
2264         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2265                 /* packet format 2: supports jumbo frames */
2266                 np->desc_ver = DESC_VER_2;
2267         } else {
2268                 /* original packet format */
2269                 np->desc_ver = DESC_VER_1;
2270         }
2271
2272         np->pkt_limit = NV_PKTLIMIT_1;
2273         if (id->driver_data & DEV_HAS_LARGEDESC)
2274                 np->pkt_limit = NV_PKTLIMIT_2;
2275
2276         err = -ENOMEM;
2277         np->base = ioremap(addr, NV_PCI_REGSZ);
2278         if (!np->base)
2279                 goto out_relreg;
2280         dev->base_addr = (unsigned long)np->base;
2281
2282         dev->irq = pci_dev->irq;
2283
2284         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2285                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2286                                         sizeof(struct ring_desc) * (RX_RING + TX_RING),
2287                                         &np->ring_addr);
2288                 if (!np->rx_ring.orig)
2289                         goto out_unmap;
2290                 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2291         } else {
2292                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2293                                         sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2294                                         &np->ring_addr);
2295                 if (!np->rx_ring.ex)
2296                         goto out_unmap;
2297                 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2298         }
2299
2300         dev->open = nv_open;
2301         dev->stop = nv_close;
2302         dev->hard_start_xmit = nv_start_xmit;
2303         dev->get_stats = nv_get_stats;
2304         dev->change_mtu = nv_change_mtu;
2305         dev->set_multicast_list = nv_set_multicast;
2306 #ifdef CONFIG_NET_POLL_CONTROLLER
2307         dev->poll_controller = nv_poll_controller;
2308 #endif
2309         SET_ETHTOOL_OPS(dev, &ops);
2310         dev->tx_timeout = nv_tx_timeout;
2311         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2312
2313         pci_set_drvdata(pci_dev, dev);
2314
2315         /* read the mac address */
2316         base = get_hwbase(dev);
2317         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2318         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2319
2320         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2321         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2322         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2323         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2324         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2325         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2326
2327         if (!is_valid_ether_addr(dev->dev_addr)) {
2328                 /*
2329                  * Bad mac address. At least one bios sets the mac address
2330                  * to 01:23:45:67:89:ab
2331                  */
2332                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2333                         pci_name(pci_dev),
2334                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2335                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2336                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2337                 dev->dev_addr[0] = 0x00;
2338                 dev->dev_addr[1] = 0x00;
2339                 dev->dev_addr[2] = 0x6c;
2340                 get_random_bytes(&dev->dev_addr[3], 3);
2341         }
2342
2343         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2344                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2345                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2346
2347         /* disable WOL */
2348         writel(0, base + NvRegWakeUpFlags);
2349         np->wolenabled = 0;
2350
2351         if (np->desc_ver == DESC_VER_1) {
2352                 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
2353         } else {
2354                 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
2355         }
2356         np->irqmask = NVREG_IRQMASK_WANTED;
2357         if (id->driver_data & DEV_NEED_TIMERIRQ)
2358                 np->irqmask |= NVREG_IRQ_TIMER;
2359         if (id->driver_data & DEV_NEED_LINKTIMER) {
2360                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2361                 np->need_linktimer = 1;
2362                 np->link_timeout = jiffies + LINK_TIMEOUT;
2363         } else {
2364                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2365                 np->need_linktimer = 0;
2366         }
2367
2368         /* find a suitable phy */
2369         for (i = 1; i < 32; i++) {
2370                 int id1, id2;
2371
2372                 spin_lock_irq(&np->lock);
2373                 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2374                 spin_unlock_irq(&np->lock);
2375                 if (id1 < 0 || id1 == 0xffff)
2376                         continue;
2377                 spin_lock_irq(&np->lock);
2378                 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2379                 spin_unlock_irq(&np->lock);
2380                 if (id2 < 0 || id2 == 0xffff)
2381                         continue;
2382
2383                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2384                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2385                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2386                                 pci_name(pci_dev), id1, id2, i);
2387                 np->phyaddr = i;
2388                 np->phy_oui = id1 | id2;
2389                 break;
2390         }
2391         if (i == 32) {
2392                 /* PHY in isolate mode? No phy attached and user wants to
2393                  * test loopback? Very odd, but can be correct.
2394                  */
2395                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2396                                 pci_name(pci_dev));
2397         }
2398
2399         if (i != 32) {
2400                 /* reset it */
2401                 phy_init(dev);
2402         }
2403
2404         /* set default link speed settings */
2405         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2406         np->duplex = 0;
2407         np->autoneg = 1;
2408
2409         err = register_netdev(dev);
2410         if (err) {
2411                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2412                 goto out_freering;
2413         }
2414         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2415                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2416                         pci_name(pci_dev));
2417
2418         return 0;
2419
2420 out_freering:
2421         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2422                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2423                                     np->rx_ring.orig, np->ring_addr);
2424         else
2425                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2426                                     np->rx_ring.ex, np->ring_addr);
2427         pci_set_drvdata(pci_dev, NULL);
2428 out_unmap:
2429         iounmap(get_hwbase(dev));
2430 out_relreg:
2431         pci_release_regions(pci_dev);
2432 out_disable:
2433         pci_disable_device(pci_dev);
2434 out_free:
2435         free_netdev(dev);
2436 out:
2437         return err;
2438 }
2439
2440 static void __devexit nv_remove(struct pci_dev *pci_dev)
2441 {
2442         struct net_device *dev = pci_get_drvdata(pci_dev);
2443         struct fe_priv *np = get_nvpriv(dev);
2444         u8 __iomem *base = get_hwbase(dev);
2445
2446         unregister_netdev(dev);
2447
2448         /* special op: write back the misordered MAC address - otherwise
2449          * the next nv_probe would see a wrong address.
2450          */
2451         writel(np->orig_mac[0], base + NvRegMacAddrA);
2452         writel(np->orig_mac[1], base + NvRegMacAddrB);
2453
2454         /* free all structures */
2455         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2456                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2457         else
2458                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2459         iounmap(get_hwbase(dev));
2460         pci_release_regions(pci_dev);
2461         pci_disable_device(pci_dev);
2462         free_netdev(dev);
2463         pci_set_drvdata(pci_dev, NULL);
2464 }
2465
2466 static struct pci_device_id pci_tbl[] = {
2467         {       /* nForce Ethernet Controller */
2468                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2469                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2470         },
2471         {       /* nForce2 Ethernet Controller */
2472                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2473                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2474         },
2475         {       /* nForce3 Ethernet Controller */
2476                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2477                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2478         },
2479         {       /* nForce3 Ethernet Controller */
2480                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2481                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2482         },
2483         {       /* nForce3 Ethernet Controller */
2484                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2485                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2486         },
2487         {       /* nForce3 Ethernet Controller */
2488                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2489                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2490         },
2491         {       /* nForce3 Ethernet Controller */
2492                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2493                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2494         },
2495         {       /* CK804 Ethernet Controller */
2496                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2497                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2498         },
2499         {       /* CK804 Ethernet Controller */
2500                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2501                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2502         },
2503         {       /* MCP04 Ethernet Controller */
2504                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2505                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2506         },
2507         {       /* MCP04 Ethernet Controller */
2508                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2509                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2510         },
2511         {       /* MCP51 Ethernet Controller */
2512                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2513                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2514         },
2515         {       /* MCP51 Ethernet Controller */
2516                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2517                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2518         },
2519         {       /* MCP55 Ethernet Controller */
2520                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2521                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2522         },
2523         {       /* MCP55 Ethernet Controller */
2524                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2525                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2526         },
2527         {0,},
2528 };
2529
2530 static struct pci_driver driver = {
2531         .name = "forcedeth",
2532         .id_table = pci_tbl,
2533         .probe = nv_probe,
2534         .remove = __devexit_p(nv_remove),
2535 };
2536
2537
2538 static int __init init_nic(void)
2539 {
2540         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2541         return pci_module_init(&driver);
2542 }
2543
2544 static void __exit exit_nic(void)
2545 {
2546         pci_unregister_driver(&driver);
2547 }
2548
2549 module_param(max_interrupt_work, int, 0);
2550 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2551
2552 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2553 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2554 MODULE_LICENSE("GPL");
2555
2556 MODULE_DEVICE_TABLE(pci, pci_tbl);
2557
2558 module_init(init_nic);
2559 module_exit(exit_nic);