drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.64"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/sched.h>
  53 #include <linux/spinlock.h>
  54 #include <linux/ethtool.h>
  55 #include <linux/timer.h>
  56 #include <linux/skbuff.h>
  57 #include <linux/mii.h>
  58 #include <linux/random.h>
  59 #include <linux/init.h>
  60 #include <linux/if_vlan.h>
  61 #include <linux/dma-mapping.h>
  62 #include <linux/slab.h>
  63
  64 #include <asm/irq.h>
  65 #include <asm/io.h>
  66 #include <asm/uaccess.h>
  67 #include <asm/system.h>
  68
  69 #if 0
  70 #define dprintk                 printk
  71 #else
  72 #define dprintk(x...)           do { } while (0)
  73 #endif
  74
  75 #define TX_WORK_PER_LOOP  64
  76 #define RX_WORK_PER_LOOP  64
  77
  78 /*
  79  * Hardware access:
  80  */
  81
  82 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  83 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  84 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  85 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  86 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  87 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  88 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  89 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  90 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  91 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  92 #define DEV_HAS_STATISTICS_V2      0x0000600  /* device supports hw statistics version 2 */
  93 #define DEV_HAS_STATISTICS_V3      0x0000e00  /* device supports hw statistics version 3 */
  94 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  95 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  96 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  97 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  98 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  99 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
 100 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 101 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 102 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 103 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 104 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 105 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 106 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 107
 108 enum {
 109         NvRegIrqStatus = 0x000,
 110 #define NVREG_IRQSTAT_MIIEVENT  0x040
 111 #define NVREG_IRQSTAT_MASK              0x83ff
 112         NvRegIrqMask = 0x004,
 113 #define NVREG_IRQ_RX_ERROR              0x0001
 114 #define NVREG_IRQ_RX                    0x0002
 115 #define NVREG_IRQ_RX_NOBUF              0x0004
 116 #define NVREG_IRQ_TX_ERR                0x0008
 117 #define NVREG_IRQ_TX_OK                 0x0010
 118 #define NVREG_IRQ_TIMER                 0x0020
 119 #define NVREG_IRQ_LINK                  0x0040
 120 #define NVREG_IRQ_RX_FORCED             0x0080
 121 #define NVREG_IRQ_TX_FORCED             0x0100
 122 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 123 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 124 #define NVREG_IRQMASK_CPU               0x0060
 125 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 126 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 127 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 128
 129         NvRegUnknownSetupReg6 = 0x008,
 130 #define NVREG_UNKSETUP6_VAL             3
 131
 132 /*
 133  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 134  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 135  */
 136         NvRegPollingInterval = 0x00c,
 137 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 138 #define NVREG_POLL_DEFAULT_CPU  13
 139         NvRegMSIMap0 = 0x020,
 140         NvRegMSIMap1 = 0x024,
 141         NvRegMSIIrqMask = 0x030,
 142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 143         NvRegMisc1 = 0x080,
 144 #define NVREG_MISC1_PAUSE_TX    0x01
 145 #define NVREG_MISC1_HD          0x02
 146 #define NVREG_MISC1_FORCE       0x3b0f3c
 147
 148         NvRegMacReset = 0x34,
 149 #define NVREG_MAC_RESET_ASSERT  0x0F3
 150         NvRegTransmitterControl = 0x084,
 151 #define NVREG_XMITCTL_START     0x01
 152 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 153 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 154 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 155 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 156 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 157 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 158 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 159 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 160 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 161 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 162 #define NVREG_XMITCTL_DATA_START        0x00100000
 163 #define NVREG_XMITCTL_DATA_READY        0x00010000
 164 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 165         NvRegTransmitterStatus = 0x088,
 166 #define NVREG_XMITSTAT_BUSY     0x01
 167
 168         NvRegPacketFilterFlags = 0x8c,
 169 #define NVREG_PFF_PAUSE_RX      0x08
 170 #define NVREG_PFF_ALWAYS        0x7F0000
 171 #define NVREG_PFF_PROMISC       0x80
 172 #define NVREG_PFF_MYADDR        0x20
 173 #define NVREG_PFF_LOOPBACK      0x10
 174
 175         NvRegOffloadConfig = 0x90,
 176 #define NVREG_OFFLOAD_HOMEPHY   0x601
 177 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 178         NvRegReceiverControl = 0x094,
 179 #define NVREG_RCVCTL_START      0x01
 180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 181         NvRegReceiverStatus = 0x98,
 182 #define NVREG_RCVSTAT_BUSY      0x01
 183
 184         NvRegSlotTime = 0x9c,
 185 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 186 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 187 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 188 #define NVREG_SLOTTIME_HALF             0x0000ff00
 189 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 190 #define NVREG_SLOTTIME_MASK             0x000000ff
 191
 192         NvRegTxDeferral = 0xA0,
 193 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 194 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 195 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 198 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 199         NvRegRxDeferral = 0xA4,
 200 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 201         NvRegMacAddrA = 0xA8,
 202         NvRegMacAddrB = 0xAC,
 203         NvRegMulticastAddrA = 0xB0,
 204 #define NVREG_MCASTADDRA_FORCE  0x01
 205         NvRegMulticastAddrB = 0xB4,
 206         NvRegMulticastMaskA = 0xB8,
 207 #define NVREG_MCASTMASKA_NONE           0xffffffff
 208         NvRegMulticastMaskB = 0xBC,
 209 #define NVREG_MCASTMASKB_NONE           0xffff
 210
 211         NvRegPhyInterface = 0xC0,
 212 #define PHY_RGMII               0x10000000
 213         NvRegBackOffControl = 0xC4,
 214 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 215 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 216 #define NVREG_BKOFFCTRL_SELECT                  24
 217 #define NVREG_BKOFFCTRL_GEAR                    12
 218
 219         NvRegTxRingPhysAddr = 0x100,
 220         NvRegRxRingPhysAddr = 0x104,
 221         NvRegRingSizes = 0x108,
 222 #define NVREG_RINGSZ_TXSHIFT 0
 223 #define NVREG_RINGSZ_RXSHIFT 16
 224         NvRegTransmitPoll = 0x10c,
 225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 226         NvRegLinkSpeed = 0x110,
 227 #define NVREG_LINKSPEED_FORCE 0x10000
 228 #define NVREG_LINKSPEED_10      1000
 229 #define NVREG_LINKSPEED_100     100
 230 #define NVREG_LINKSPEED_1000    50
 231 #define NVREG_LINKSPEED_MASK    (0xFFF)
 232         NvRegUnknownSetupReg5 = 0x130,
 233 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 234         NvRegTxWatermark = 0x13c,
 235 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 236 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 237 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 238         NvRegTxRxControl = 0x144,
 239 #define NVREG_TXRXCTL_KICK      0x0001
 240 #define NVREG_TXRXCTL_BIT1      0x0002
 241 #define NVREG_TXRXCTL_BIT2      0x0004
 242 #define NVREG_TXRXCTL_IDLE      0x0008
 243 #define NVREG_TXRXCTL_RESET     0x0010
 244 #define NVREG_TXRXCTL_RXCHECK   0x0400
 245 #define NVREG_TXRXCTL_DESC_1    0
 246 #define NVREG_TXRXCTL_DESC_2    0x002100
 247 #define NVREG_TXRXCTL_DESC_3    0xc02200
 248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 249 #define NVREG_TXRXCTL_VLANINS   0x00080
 250         NvRegTxRingPhysAddrHigh = 0x148,
 251         NvRegRxRingPhysAddrHigh = 0x14C,
 252         NvRegTxPauseFrame = 0x170,
 253 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 257         NvRegTxPauseFrameLimit = 0x174,
 258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 259         NvRegMIIStatus = 0x180,
 260 #define NVREG_MIISTAT_ERROR             0x0001
 261 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 262 #define NVREG_MIISTAT_MASK_RW           0x0007
 263 #define NVREG_MIISTAT_MASK_ALL          0x000f
 264         NvRegMIIMask = 0x184,
 265 #define NVREG_MII_LINKCHANGE            0x0008
 266
 267         NvRegAdapterControl = 0x188,
 268 #define NVREG_ADAPTCTL_START    0x02
 269 #define NVREG_ADAPTCTL_LINKUP   0x04
 270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 271 #define NVREG_ADAPTCTL_RUNNING  0x100000
 272 #define NVREG_ADAPTCTL_PHYSHIFT 24
 273         NvRegMIISpeed = 0x18c,
 274 #define NVREG_MIISPEED_BIT8     (1<<8)
 275 #define NVREG_MIIDELAY  5
 276         NvRegMIIControl = 0x190,
 277 #define NVREG_MIICTL_INUSE      0x08000
 278 #define NVREG_MIICTL_WRITE      0x00400
 279 #define NVREG_MIICTL_ADDRSHIFT  5
 280         NvRegMIIData = 0x194,
 281         NvRegTxUnicast = 0x1a0,
 282         NvRegTxMulticast = 0x1a4,
 283         NvRegTxBroadcast = 0x1a8,
 284         NvRegWakeUpFlags = 0x200,
 285 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 288 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 289 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 290 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 291 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 295 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 296
 297         NvRegMgmtUnitGetVersion = 0x204,
 298 #define NVREG_MGMTUNITGETVERSION        0x01
 299         NvRegMgmtUnitVersion = 0x208,
 300 #define NVREG_MGMTUNITVERSION           0x08
 301         NvRegPowerCap = 0x268,
 302 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 303 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 304 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 305         NvRegPowerState = 0x26c,
 306 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 307 #define NVREG_POWERSTATE_VALID          0x0100
 308 #define NVREG_POWERSTATE_MASK           0x0003
 309 #define NVREG_POWERSTATE_D0             0x0000
 310 #define NVREG_POWERSTATE_D1             0x0001
 311 #define NVREG_POWERSTATE_D2             0x0002
 312 #define NVREG_POWERSTATE_D3             0x0003
 313         NvRegMgmtUnitControl = 0x278,
 314 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 315         NvRegTxCnt = 0x280,
 316         NvRegTxZeroReXmt = 0x284,
 317         NvRegTxOneReXmt = 0x288,
 318         NvRegTxManyReXmt = 0x28c,
 319         NvRegTxLateCol = 0x290,
 320         NvRegTxUnderflow = 0x294,
 321         NvRegTxLossCarrier = 0x298,
 322         NvRegTxExcessDef = 0x29c,
 323         NvRegTxRetryErr = 0x2a0,
 324         NvRegRxFrameErr = 0x2a4,
 325         NvRegRxExtraByte = 0x2a8,
 326         NvRegRxLateCol = 0x2ac,
 327         NvRegRxRunt = 0x2b0,
 328         NvRegRxFrameTooLong = 0x2b4,
 329         NvRegRxOverflow = 0x2b8,
 330         NvRegRxFCSErr = 0x2bc,
 331         NvRegRxFrameAlignErr = 0x2c0,
 332         NvRegRxLenErr = 0x2c4,
 333         NvRegRxUnicast = 0x2c8,
 334         NvRegRxMulticast = 0x2cc,
 335         NvRegRxBroadcast = 0x2d0,
 336         NvRegTxDef = 0x2d4,
 337         NvRegTxFrame = 0x2d8,
 338         NvRegRxCnt = 0x2dc,
 339         NvRegTxPause = 0x2e0,
 340         NvRegRxPause = 0x2e4,
 341         NvRegRxDropFrame = 0x2e8,
 342         NvRegVlanControl = 0x300,
 343 #define NVREG_VLANCONTROL_ENABLE        0x2000
 344         NvRegMSIXMap0 = 0x3e0,
 345         NvRegMSIXMap1 = 0x3e4,
 346         NvRegMSIXIrqStatus = 0x3f0,
 347
 348         NvRegPowerState2 = 0x600,
 349 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 350 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 351 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 352 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 353 };
 354
 355 /* Big endian: should work, but is untested */
 356 struct ring_desc {
 357         __le32 buf;
 358         __le32 flaglen;
 359 };
 360
 361 struct ring_desc_ex {
 362         __le32 bufhigh;
 363         __le32 buflow;
 364         __le32 txvlan;
 365         __le32 flaglen;
 366 };
 367
 368 union ring_type {
 369         struct ring_desc* orig;
 370         struct ring_desc_ex* ex;
 371 };
 372
 373 #define FLAG_MASK_V1 0xffff0000
 374 #define FLAG_MASK_V2 0xffffc000
 375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 377
 378 #define NV_TX_LASTPACKET        (1<<16)
 379 #define NV_TX_RETRYERROR        (1<<19)
 380 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 381 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 382 #define NV_TX_DEFERRED          (1<<26)
 383 #define NV_TX_CARRIERLOST       (1<<27)
 384 #define NV_TX_LATECOLLISION     (1<<28)
 385 #define NV_TX_UNDERFLOW         (1<<29)
 386 #define NV_TX_ERROR             (1<<30)
 387 #define NV_TX_VALID             (1<<31)
 388
 389 #define NV_TX2_LASTPACKET       (1<<29)
 390 #define NV_TX2_RETRYERROR       (1<<18)
 391 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 393 #define NV_TX2_DEFERRED         (1<<25)
 394 #define NV_TX2_CARRIERLOST      (1<<26)
 395 #define NV_TX2_LATECOLLISION    (1<<27)
 396 #define NV_TX2_UNDERFLOW        (1<<28)
 397 /* error and valid are the same for both */
 398 #define NV_TX2_ERROR            (1<<30)
 399 #define NV_TX2_VALID            (1<<31)
 400 #define NV_TX2_TSO              (1<<28)
 401 #define NV_TX2_TSO_SHIFT        14
 402 #define NV_TX2_TSO_MAX_SHIFT    14
 403 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 404 #define NV_TX2_CHECKSUM_L3      (1<<27)
 405 #define NV_TX2_CHECKSUM_L4      (1<<26)
 406
 407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 408
 409 #define NV_RX_DESCRIPTORVALID   (1<<16)
 410 #define NV_RX_MISSEDFRAME       (1<<17)
 411 #define NV_RX_SUBSTRACT1        (1<<18)
 412 #define NV_RX_ERROR1            (1<<23)
 413 #define NV_RX_ERROR2            (1<<24)
 414 #define NV_RX_ERROR3            (1<<25)
 415 #define NV_RX_ERROR4            (1<<26)
 416 #define NV_RX_CRCERR            (1<<27)
 417 #define NV_RX_OVERFLOW          (1<<28)
 418 #define NV_RX_FRAMINGERR        (1<<29)
 419 #define NV_RX_ERROR             (1<<30)
 420 #define NV_RX_AVAIL             (1<<31)
 421 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 422
 423 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 424 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 425 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 426 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 427 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 428 #define NV_RX2_SUBSTRACT1       (1<<25)
 429 #define NV_RX2_ERROR1           (1<<18)
 430 #define NV_RX2_ERROR2           (1<<19)
 431 #define NV_RX2_ERROR3           (1<<20)
 432 #define NV_RX2_ERROR4           (1<<21)
 433 #define NV_RX2_CRCERR           (1<<22)
 434 #define NV_RX2_OVERFLOW         (1<<23)
 435 #define NV_RX2_FRAMINGERR       (1<<24)
 436 /* error and avail are the same for both */
 437 #define NV_RX2_ERROR            (1<<30)
 438 #define NV_RX2_AVAIL            (1<<31)
 439 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 440
 441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 442 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 443
 444 /* Miscelaneous hardware related defines: */
 445 #define NV_PCI_REGSZ_VER1       0x270
 446 #define NV_PCI_REGSZ_VER2       0x2d4
 447 #define NV_PCI_REGSZ_VER3       0x604
 448 #define NV_PCI_REGSZ_MAX        0x604
 449
 450 /* various timeout delays: all in usec */
 451 #define NV_TXRX_RESET_DELAY     4
 452 #define NV_TXSTOP_DELAY1        10
 453 #define NV_TXSTOP_DELAY1MAX     500000
 454 #define NV_TXSTOP_DELAY2        100
 455 #define NV_RXSTOP_DELAY1        10
 456 #define NV_RXSTOP_DELAY1MAX     500000
 457 #define NV_RXSTOP_DELAY2        100
 458 #define NV_SETUP5_DELAY         5
 459 #define NV_SETUP5_DELAYMAX      50000
 460 #define NV_POWERUP_DELAY        5
 461 #define NV_POWERUP_DELAYMAX     5000
 462 #define NV_MIIBUSY_DELAY        50
 463 #define NV_MIIPHY_DELAY 10
 464 #define NV_MIIPHY_DELAYMAX      10000
 465 #define NV_MAC_RESET_DELAY      64
 466
 467 #define NV_WAKEUPPATTERNS       5
 468 #define NV_WAKEUPMASKENTRIES    4
 469
 470 /* General driver defaults */
 471 #define NV_WATCHDOG_TIMEO       (5*HZ)
 472
 473 #define RX_RING_DEFAULT         512
 474 #define TX_RING_DEFAULT         256
 475 #define RX_RING_MIN             128
 476 #define TX_RING_MIN             64
 477 #define RING_MAX_DESC_VER_1     1024
 478 #define RING_MAX_DESC_VER_2_3   16384
 479
 480 /* rx/tx mac addr + type + vlan + align + slack*/
 481 #define NV_RX_HEADERS           (64)
 482 /* even more slack. */
 483 #define NV_RX_ALLOC_PAD         (64)
 484
 485 /* maximum mtu size */
 486 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 487 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 488
 489 #define OOM_REFILL      (1+HZ/20)
 490 #define POLL_WAIT       (1+HZ/100)
 491 #define LINK_TIMEOUT    (3*HZ)
 492 #define STATS_INTERVAL  (10*HZ)
 493
 494 /*
 495  * desc_ver values:
 496  * The nic supports three different descriptor types:
 497  * - DESC_VER_1: Original
 498  * - DESC_VER_2: support for jumbo frames.
 499  * - DESC_VER_3: 64-bit format.
 500  */
 501 #define DESC_VER_1      1
 502 #define DESC_VER_2      2
 503 #define DESC_VER_3      3
 504
 505 /* PHY defines */
 506 #define PHY_OUI_MARVELL         0x5043
 507 #define PHY_OUI_CICADA          0x03f1
 508 #define PHY_OUI_VITESSE         0x01c1
 509 #define PHY_OUI_REALTEK         0x0732
 510 #define PHY_OUI_REALTEK2        0x0020
 511 #define PHYID1_OUI_MASK 0x03ff
 512 #define PHYID1_OUI_SHFT 6
 513 #define PHYID2_OUI_MASK 0xfc00
 514 #define PHYID2_OUI_SHFT 10
 515 #define PHYID2_MODEL_MASK               0x03f0
 516 #define PHY_MODEL_REALTEK_8211          0x0110
 517 #define PHY_REV_MASK                    0x0001
 518 #define PHY_REV_REALTEK_8211B           0x0000
 519 #define PHY_REV_REALTEK_8211C           0x0001
 520 #define PHY_MODEL_REALTEK_8201          0x0200
 521 #define PHY_MODEL_MARVELL_E3016         0x0220
 522 #define PHY_MARVELL_E3016_INITMASK      0x0300
 523 #define PHY_CICADA_INIT1        0x0f000
 524 #define PHY_CICADA_INIT2        0x0e00
 525 #define PHY_CICADA_INIT3        0x01000
 526 #define PHY_CICADA_INIT4        0x0200
 527 #define PHY_CICADA_INIT5        0x0004
 528 #define PHY_CICADA_INIT6        0x02000
 529 #define PHY_VITESSE_INIT_REG1   0x1f
 530 #define PHY_VITESSE_INIT_REG2   0x10
 531 #define PHY_VITESSE_INIT_REG3   0x11
 532 #define PHY_VITESSE_INIT_REG4   0x12
 533 #define PHY_VITESSE_INIT_MSK1   0xc
 534 #define PHY_VITESSE_INIT_MSK2   0x0180
 535 #define PHY_VITESSE_INIT1       0x52b5
 536 #define PHY_VITESSE_INIT2       0xaf8a
 537 #define PHY_VITESSE_INIT3       0x8
 538 #define PHY_VITESSE_INIT4       0x8f8a
 539 #define PHY_VITESSE_INIT5       0xaf86
 540 #define PHY_VITESSE_INIT6       0x8f86
 541 #define PHY_VITESSE_INIT7       0xaf82
 542 #define PHY_VITESSE_INIT8       0x0100
 543 #define PHY_VITESSE_INIT9       0x8f82
 544 #define PHY_VITESSE_INIT10      0x0
 545 #define PHY_REALTEK_INIT_REG1   0x1f
 546 #define PHY_REALTEK_INIT_REG2   0x19
 547 #define PHY_REALTEK_INIT_REG3   0x13
 548 #define PHY_REALTEK_INIT_REG4   0x14
 549 #define PHY_REALTEK_INIT_REG5   0x18
 550 #define PHY_REALTEK_INIT_REG6   0x11
 551 #define PHY_REALTEK_INIT_REG7   0x01
 552 #define PHY_REALTEK_INIT1       0x0000
 553 #define PHY_REALTEK_INIT2       0x8e00
 554 #define PHY_REALTEK_INIT3       0x0001
 555 #define PHY_REALTEK_INIT4       0xad17
 556 #define PHY_REALTEK_INIT5       0xfb54
 557 #define PHY_REALTEK_INIT6       0xf5c7
 558 #define PHY_REALTEK_INIT7       0x1000
 559 #define PHY_REALTEK_INIT8       0x0003
 560 #define PHY_REALTEK_INIT9       0x0008
 561 #define PHY_REALTEK_INIT10      0x0005
 562 #define PHY_REALTEK_INIT11      0x0200
 563 #define PHY_REALTEK_INIT_MSK1   0x0003
 564
 565 #define PHY_GIGABIT     0x0100
 566
 567 #define PHY_TIMEOUT     0x1
 568 #define PHY_ERROR       0x2
 569
 570 #define PHY_100 0x1
 571 #define PHY_1000        0x2
 572 #define PHY_HALF        0x100
 573
 574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 576 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 577 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 578 #define NV_PAUSEFRAME_RX_REQ     0x0010
 579 #define NV_PAUSEFRAME_TX_REQ     0x0020
 580 #define NV_PAUSEFRAME_AUTONEG    0x0040
 581
 582 /* MSI/MSI-X defines */
 583 #define NV_MSI_X_MAX_VECTORS  8
 584 #define NV_MSI_X_VECTORS_MASK 0x000f
 585 #define NV_MSI_CAPABLE        0x0010
 586 #define NV_MSI_X_CAPABLE      0x0020
 587 #define NV_MSI_ENABLED        0x0040
 588 #define NV_MSI_X_ENABLED      0x0080
 589
 590 #define NV_MSI_X_VECTOR_ALL   0x0
 591 #define NV_MSI_X_VECTOR_RX    0x0
 592 #define NV_MSI_X_VECTOR_TX    0x1
 593 #define NV_MSI_X_VECTOR_OTHER 0x2
 594
 595 #define NV_MSI_PRIV_OFFSET 0x68
 596 #define NV_MSI_PRIV_VALUE  0xffffffff
 597
 598 #define NV_RESTART_TX         0x1
 599 #define NV_RESTART_RX         0x2
 600
 601 #define NV_TX_LIMIT_COUNT     16
 602
 603 #define NV_DYNAMIC_THRESHOLD        4
 604 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 605
 606 /* statistics */
 607 struct nv_ethtool_str {
 608         char name[ETH_GSTRING_LEN];
 609 };
 610
 611 static const struct nv_ethtool_str nv_estats_str[] = {
 612         { "tx_bytes" },
 613         { "tx_zero_rexmt" },
 614         { "tx_one_rexmt" },
 615         { "tx_many_rexmt" },
 616         { "tx_late_collision" },
 617         { "tx_fifo_errors" },
 618         { "tx_carrier_errors" },
 619         { "tx_excess_deferral" },
 620         { "tx_retry_error" },
 621         { "rx_frame_error" },
 622         { "rx_extra_byte" },
 623         { "rx_late_collision" },
 624         { "rx_runt" },
 625         { "rx_frame_too_long" },
 626         { "rx_over_errors" },
 627         { "rx_crc_errors" },
 628         { "rx_frame_align_error" },
 629         { "rx_length_error" },
 630         { "rx_unicast" },
 631         { "rx_multicast" },
 632         { "rx_broadcast" },
 633         { "rx_packets" },
 634         { "rx_errors_total" },
 635         { "tx_errors_total" },
 636
 637         /* version 2 stats */
 638         { "tx_deferral" },
 639         { "tx_packets" },
 640         { "rx_bytes" },
 641         { "tx_pause" },
 642         { "rx_pause" },
 643         { "rx_drop_frame" },
 644
 645         /* version 3 stats */
 646         { "tx_unicast" },
 647         { "tx_multicast" },
 648         { "tx_broadcast" }
 649 };
 650
 651 struct nv_ethtool_stats {
 652         u64 tx_bytes;
 653         u64 tx_zero_rexmt;
 654         u64 tx_one_rexmt;
 655         u64 tx_many_rexmt;
 656         u64 tx_late_collision;
 657         u64 tx_fifo_errors;
 658         u64 tx_carrier_errors;
 659         u64 tx_excess_deferral;
 660         u64 tx_retry_error;
 661         u64 rx_frame_error;
 662         u64 rx_extra_byte;
 663         u64 rx_late_collision;
 664         u64 rx_runt;
 665         u64 rx_frame_too_long;
 666         u64 rx_over_errors;
 667         u64 rx_crc_errors;
 668         u64 rx_frame_align_error;
 669         u64 rx_length_error;
 670         u64 rx_unicast;
 671         u64 rx_multicast;
 672         u64 rx_broadcast;
 673         u64 rx_packets;
 674         u64 rx_errors_total;
 675         u64 tx_errors_total;
 676
 677         /* version 2 stats */
 678         u64 tx_deferral;
 679         u64 tx_packets;
 680         u64 rx_bytes;
 681         u64 tx_pause;
 682         u64 rx_pause;
 683         u64 rx_drop_frame;
 684
 685         /* version 3 stats */
 686         u64 tx_unicast;
 687         u64 tx_multicast;
 688         u64 tx_broadcast;
 689 };
 690
 691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 694
 695 /* diagnostics */
 696 #define NV_TEST_COUNT_BASE 3
 697 #define NV_TEST_COUNT_EXTENDED 4
 698
 699 static const struct nv_ethtool_str nv_etests_str[] = {
 700         { "link      (online/offline)" },
 701         { "register  (offline)       " },
 702         { "interrupt (offline)       " },
 703         { "loopback  (offline)       " }
 704 };
 705
 706 struct register_test {
 707         __u32 reg;
 708         __u32 mask;
 709 };
 710
 711 static const struct register_test nv_registers_test[] = {
 712         { NvRegUnknownSetupReg6, 0x01 },
 713         { NvRegMisc1, 0x03c },
 714         { NvRegOffloadConfig, 0x03ff },
 715         { NvRegMulticastAddrA, 0xffffffff },
 716         { NvRegTxWatermark, 0x0ff },
 717         { NvRegWakeUpFlags, 0x07777 },
 718         { 0,0 }
 719 };
 720
 721 struct nv_skb_map {
 722         struct sk_buff *skb;
 723         dma_addr_t dma;
 724         unsigned int dma_len:31;
 725         unsigned int dma_single:1;
 726         struct ring_desc_ex *first_tx_desc;
 727         struct nv_skb_map *next_tx_ctx;
 728 };
 729
 730 /*
 731  * SMP locking:
 732  * All hardware access under netdev_priv(dev)->lock, except the performance
 733  * critical parts:
 734  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 735  *      by the arch code for interrupts.
 736  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 737  *      needs netdev_priv(dev)->lock :-(
 738  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 739  */
 740
 741 /* in dev: base, irq */
 742 struct fe_priv {
 743         spinlock_t lock;
 744
 745         struct net_device *dev;
 746         struct napi_struct napi;
 747
 748         /* General data:
 749          * Locking: spin_lock(&np->lock); */
 750         struct nv_ethtool_stats estats;
 751         int in_shutdown;
 752         u32 linkspeed;
 753         int duplex;
 754         int autoneg;
 755         int fixed_mode;
 756         int phyaddr;
 757         int wolenabled;
 758         unsigned int phy_oui;
 759         unsigned int phy_model;
 760         unsigned int phy_rev;
 761         u16 gigabit;
 762         int intr_test;
 763         int recover_error;
 764         int quiet_count;
 765
 766         /* General data: RO fields */
 767         dma_addr_t ring_addr;
 768         struct pci_dev *pci_dev;
 769         u32 orig_mac[2];
 770         u32 events;
 771         u32 irqmask;
 772         u32 desc_ver;
 773         u32 txrxctl_bits;
 774         u32 vlanctl_bits;
 775         u32 driver_data;
 776         u32 device_id;
 777         u32 register_size;
 778         int rx_csum;
 779         u32 mac_in_use;
 780         int mgmt_version;
 781         int mgmt_sema;
 782
 783         void __iomem *base;
 784
 785         /* rx specific fields.
 786          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 787          */
 788         union ring_type get_rx, put_rx, first_rx, last_rx;
 789         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 790         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 791         struct nv_skb_map *rx_skb;
 792
 793         union ring_type rx_ring;
 794         unsigned int rx_buf_sz;
 795         unsigned int pkt_limit;
 796         struct timer_list oom_kick;
 797         struct timer_list nic_poll;
 798         struct timer_list stats_poll;
 799         u32 nic_poll_irq;
 800         int rx_ring_size;
 801
 802         /* media detection workaround.
 803          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 804          */
 805         int need_linktimer;
 806         unsigned long link_timeout;
 807         /*
 808          * tx specific fields.
 809          */
 810         union ring_type get_tx, put_tx, first_tx, last_tx;
 811         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 812         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 813         struct nv_skb_map *tx_skb;
 814
 815         union ring_type tx_ring;
 816         u32 tx_flags;
 817         int tx_ring_size;
 818         int tx_limit;
 819         u32 tx_pkts_in_progress;
 820         struct nv_skb_map *tx_change_owner;
 821         struct nv_skb_map *tx_end_flip;
 822         int tx_stop;
 823
 824         /* vlan fields */
 825         struct vlan_group *vlangrp;
 826
 827         /* msi/msi-x fields */
 828         u32 msi_flags;
 829         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 830
 831         /* flow control */
 832         u32 pause_flags;
 833
 834         /* power saved state */
 835         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 836
 837         /* for different msi-x irq type */
 838         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 839         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 840         char name_other[IFNAMSIZ + 6];    /* -other */
 841 };
 842
 843 /*
 844  * Maximum number of loops until we assume that a bit in the irq mask
 845  * is stuck. Overridable with module param.
 846  */
 847 static int max_interrupt_work = 4;
 848
 849 /*
 850  * Optimization can be either throuput mode or cpu mode
 851  *
 852  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 853  * CPU Mode: Interrupts are controlled by a timer.
 854  */
 855 enum {
 856         NV_OPTIMIZATION_MODE_THROUGHPUT,
 857         NV_OPTIMIZATION_MODE_CPU,
 858         NV_OPTIMIZATION_MODE_DYNAMIC
 859 };
 860 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 861
 862 /*
 863  * Poll interval for timer irq
 864  *
 865  * This interval determines how frequent an interrupt is generated.
 866  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 867  * Min = 0, and Max = 65535
 868  */
 869 static int poll_interval = -1;
 870
 871 /*
 872  * MSI interrupts
 873  */
 874 enum {
 875         NV_MSI_INT_DISABLED,
 876         NV_MSI_INT_ENABLED
 877 };
 878 static int msi = NV_MSI_INT_ENABLED;
 879
 880 /*
 881  * MSIX interrupts
 882  */
 883 enum {
 884         NV_MSIX_INT_DISABLED,
 885         NV_MSIX_INT_ENABLED
 886 };
 887 static int msix = NV_MSIX_INT_ENABLED;
 888
 889 /*
 890  * DMA 64bit
 891  */
 892 enum {
 893         NV_DMA_64BIT_DISABLED,
 894         NV_DMA_64BIT_ENABLED
 895 };
 896 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 897
 898 /*
 899  * Crossover Detection
 900  * Realtek 8201 phy + some OEM boards do not work properly.
 901  */
 902 enum {
 903         NV_CROSSOVER_DETECTION_DISABLED,
 904         NV_CROSSOVER_DETECTION_ENABLED
 905 };
 906 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 907
 908 /*
 909  * Power down phy when interface is down (persists through reboot;
 910  * older Linux and other OSes may not power it up again)
 911  */
 912 static int phy_power_down = 0;
 913
 914 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 915 {
 916         return netdev_priv(dev);
 917 }
 918
 919 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 920 {
 921         return ((struct fe_priv *)netdev_priv(dev))->base;
 922 }
 923
 924 static inline void pci_push(u8 __iomem *base)
 925 {
 926         /* force out pending posted writes */
 927         readl(base);
 928 }
 929
 930 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 931 {
 932         return le32_to_cpu(prd->flaglen)
 933                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 934 }
 935
 936 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 937 {
 938         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 939 }
 940
 941 static bool nv_optimized(struct fe_priv *np)
 942 {
 943         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 944                 return false;
 945         return true;
 946 }
 947
 948 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 949                                 int delay, int delaymax, const char *msg)
 950 {
 951         u8 __iomem *base = get_hwbase(dev);
 952
 953         pci_push(base);
 954         do {
 955                 udelay(delay);
 956                 delaymax -= delay;
 957                 if (delaymax < 0) {
 958                         if (msg)
 959                                 printk("%s", msg);
 960                         return 1;
 961                 }
 962         } while ((readl(base + offset) & mask) != target);
 963         return 0;
 964 }
 965
 966 #define NV_SETUP_RX_RING 0x01
 967 #define NV_SETUP_TX_RING 0x02
 968
 969 static inline u32 dma_low(dma_addr_t addr)
 970 {
 971         return addr;
 972 }
 973
 974 static inline u32 dma_high(dma_addr_t addr)
 975 {
 976         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 977 }
 978
 979 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 980 {
 981         struct fe_priv *np = get_nvpriv(dev);
 982         u8 __iomem *base = get_hwbase(dev);
 983
 984         if (!nv_optimized(np)) {
 985                 if (rxtx_flags & NV_SETUP_RX_RING) {
 986                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 987                 }
 988                 if (rxtx_flags & NV_SETUP_TX_RING) {
 989                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 990                 }
 991         } else {
 992                 if (rxtx_flags & NV_SETUP_RX_RING) {
 993                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 994                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 995                 }
 996                 if (rxtx_flags & NV_SETUP_TX_RING) {
 997                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 998                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 999                 }
1000         }
1001 }
1002
1003 static void free_rings(struct net_device *dev)
1004 {
1005         struct fe_priv *np = get_nvpriv(dev);
1006
1007         if (!nv_optimized(np)) {
1008                 if (np->rx_ring.orig)
1009                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1010                                             np->rx_ring.orig, np->ring_addr);
1011         } else {
1012                 if (np->rx_ring.ex)
1013                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1014                                             np->rx_ring.ex, np->ring_addr);
1015         }
1016         if (np->rx_skb)
1017                 kfree(np->rx_skb);
1018         if (np->tx_skb)
1019                 kfree(np->tx_skb);
1020 }
1021
1022 static int using_multi_irqs(struct net_device *dev)
1023 {
1024         struct fe_priv *np = get_nvpriv(dev);
1025
1026         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1027             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1028              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1029                 return 0;
1030         else
1031                 return 1;
1032 }
1033
1034 static void nv_txrx_gate(struct net_device *dev, bool gate)
1035 {
1036         struct fe_priv *np = get_nvpriv(dev);
1037         u8 __iomem *base = get_hwbase(dev);
1038         u32 powerstate;
1039
1040         if (!np->mac_in_use &&
1041             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1042                 powerstate = readl(base + NvRegPowerState2);
1043                 if (gate)
1044                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1045                 else
1046                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1047                 writel(powerstate, base + NvRegPowerState2);
1048         }
1049 }
1050
1051 static void nv_enable_irq(struct net_device *dev)
1052 {
1053         struct fe_priv *np = get_nvpriv(dev);
1054
1055         if (!using_multi_irqs(dev)) {
1056                 if (np->msi_flags & NV_MSI_X_ENABLED)
1057                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1058                 else
1059                         enable_irq(np->pci_dev->irq);
1060         } else {
1061                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1062                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1063                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1064         }
1065 }
1066
1067 static void nv_disable_irq(struct net_device *dev)
1068 {
1069         struct fe_priv *np = get_nvpriv(dev);
1070
1071         if (!using_multi_irqs(dev)) {
1072                 if (np->msi_flags & NV_MSI_X_ENABLED)
1073                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1074                 else
1075                         disable_irq(np->pci_dev->irq);
1076         } else {
1077                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1078                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1079                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1080         }
1081 }
1082
1083 /* In MSIX mode, a write to irqmask behaves as XOR */
1084 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1085 {
1086         u8 __iomem *base = get_hwbase(dev);
1087
1088         writel(mask, base + NvRegIrqMask);
1089 }
1090
1091 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1092 {
1093         struct fe_priv *np = get_nvpriv(dev);
1094         u8 __iomem *base = get_hwbase(dev);
1095
1096         if (np->msi_flags & NV_MSI_X_ENABLED) {
1097                 writel(mask, base + NvRegIrqMask);
1098         } else {
1099                 if (np->msi_flags & NV_MSI_ENABLED)
1100                         writel(0, base + NvRegMSIIrqMask);
1101                 writel(0, base + NvRegIrqMask);
1102         }
1103 }
1104
1105 static void nv_napi_enable(struct net_device *dev)
1106 {
1107 #ifdef CONFIG_FORCEDETH_NAPI
1108         struct fe_priv *np = get_nvpriv(dev);
1109
1110         napi_enable(&np->napi);
1111 #endif
1112 }
1113
1114 static void nv_napi_disable(struct net_device *dev)
1115 {
1116 #ifdef CONFIG_FORCEDETH_NAPI
1117         struct fe_priv *np = get_nvpriv(dev);
1118
1119         napi_disable(&np->napi);
1120 #endif
1121 }
1122
1123 #define MII_READ        (-1)
1124 /* mii_rw: read/write a register on the PHY.
1125  *
1126  * Caller must guarantee serialization
1127  */
1128 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1129 {
1130         u8 __iomem *base = get_hwbase(dev);
1131         u32 reg;
1132         int retval;
1133
1134         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1135
1136         reg = readl(base + NvRegMIIControl);
1137         if (reg & NVREG_MIICTL_INUSE) {
1138                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1139                 udelay(NV_MIIBUSY_DELAY);
1140         }
1141
1142         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1143         if (value != MII_READ) {
1144                 writel(value, base + NvRegMIIData);
1145                 reg |= NVREG_MIICTL_WRITE;
1146         }
1147         writel(reg, base + NvRegMIIControl);
1148
1149         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1150                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1151                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1152                                 dev->name, miireg, addr);
1153                 retval = -1;
1154         } else if (value != MII_READ) {
1155                 /* it was a write operation - fewer failures are detectable */
1156                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1157                                 dev->name, value, miireg, addr);
1158                 retval = 0;
1159         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1160                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1161                                 dev->name, miireg, addr);
1162                 retval = -1;
1163         } else {
1164                 retval = readl(base + NvRegMIIData);
1165                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1166                                 dev->name, miireg, addr, retval);
1167         }
1168
1169         return retval;
1170 }
1171
1172 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1173 {
1174         struct fe_priv *np = netdev_priv(dev);
1175         u32 miicontrol;
1176         unsigned int tries = 0;
1177
1178         miicontrol = BMCR_RESET | bmcr_setup;
1179         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1180                 return -1;
1181         }
1182
1183         /* wait for 500ms */
1184         msleep(500);
1185
1186         /* must wait till reset is deasserted */
1187         while (miicontrol & BMCR_RESET) {
1188                 msleep(10);
1189                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1190                 /* FIXME: 100 tries seem excessive */
1191                 if (tries++ > 100)
1192                         return -1;
1193         }
1194         return 0;
1195 }
1196
1197 static int phy_init(struct net_device *dev)
1198 {
1199         struct fe_priv *np = get_nvpriv(dev);
1200         u8 __iomem *base = get_hwbase(dev);
1201         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1202
1203         /* phy errata for E3016 phy */
1204         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1205                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1206                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1207                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1208                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1209                         return PHY_ERROR;
1210                 }
1211         }
1212         if (np->phy_oui == PHY_OUI_REALTEK) {
1213                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1214                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1215                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1216                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1217                                 return PHY_ERROR;
1218                         }
1219                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1220                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1221                                 return PHY_ERROR;
1222                         }
1223                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1224                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225                                 return PHY_ERROR;
1226                         }
1227                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1228                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1229                                 return PHY_ERROR;
1230                         }
1231                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1232                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233                                 return PHY_ERROR;
1234                         }
1235                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1236                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1237                                 return PHY_ERROR;
1238                         }
1239                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1240                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1241                                 return PHY_ERROR;
1242                         }
1243                 }
1244                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1245                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1246                         u32 powerstate = readl(base + NvRegPowerState2);
1247
1248                         /* need to perform hw phy reset */
1249                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1250                         writel(powerstate, base + NvRegPowerState2);
1251                         msleep(25);
1252
1253                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1254                         writel(powerstate, base + NvRegPowerState2);
1255                         msleep(25);
1256
1257                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1258                         reg |= PHY_REALTEK_INIT9;
1259                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1260                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1261                                 return PHY_ERROR;
1262                         }
1263                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1264                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1265                                 return PHY_ERROR;
1266                         }
1267                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1268                         if (!(reg & PHY_REALTEK_INIT11)) {
1269                                 reg |= PHY_REALTEK_INIT11;
1270                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1271                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1272                                         return PHY_ERROR;
1273                                 }
1274                         }
1275                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1276                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1277                                 return PHY_ERROR;
1278                         }
1279                 }
1280                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1281                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1282                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1283                                 phy_reserved |= PHY_REALTEK_INIT7;
1284                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1285                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1286                                         return PHY_ERROR;
1287                                 }
1288                         }
1289                 }
1290         }
1291
1292         /* set advertise register */
1293         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1294         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1295         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1296                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1297                 return PHY_ERROR;
1298         }
1299
1300         /* get phy interface type */
1301         phyinterface = readl(base + NvRegPhyInterface);
1302
1303         /* see if gigabit phy */
1304         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1305         if (mii_status & PHY_GIGABIT) {
1306                 np->gigabit = PHY_GIGABIT;
1307                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1308                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1309                 if (phyinterface & PHY_RGMII)
1310                         mii_control_1000 |= ADVERTISE_1000FULL;
1311                 else
1312                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1313
1314                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1315                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1316                         return PHY_ERROR;
1317                 }
1318         }
1319         else
1320                 np->gigabit = 0;
1321
1322         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1323         mii_control |= BMCR_ANENABLE;
1324
1325         if (np->phy_oui == PHY_OUI_REALTEK &&
1326             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1327             np->phy_rev == PHY_REV_REALTEK_8211C) {
1328                 /* start autoneg since we already performed hw reset above */
1329                 mii_control |= BMCR_ANRESTART;
1330                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1331                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1332                         return PHY_ERROR;
1333                 }
1334         } else {
1335                 /* reset the phy
1336                  * (certain phys need bmcr to be setup with reset)
1337                  */
1338                 if (phy_reset(dev, mii_control)) {
1339                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1340                         return PHY_ERROR;
1341                 }
1342         }
1343
1344         /* phy vendor specific configuration */
1345         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1346                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1347                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1348                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1349                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1350                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1351                         return PHY_ERROR;
1352                 }
1353                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1354                 phy_reserved |= PHY_CICADA_INIT5;
1355                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1356                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1357                         return PHY_ERROR;
1358                 }
1359         }
1360         if (np->phy_oui == PHY_OUI_CICADA) {
1361                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1362                 phy_reserved |= PHY_CICADA_INIT6;
1363                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1364                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365                         return PHY_ERROR;
1366                 }
1367         }
1368         if (np->phy_oui == PHY_OUI_VITESSE) {
1369                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1370                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1371                         return PHY_ERROR;
1372                 }
1373                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1374                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1375                         return PHY_ERROR;
1376                 }
1377                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1378                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1379                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1380                         return PHY_ERROR;
1381                 }
1382                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1383                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1384                 phy_reserved |= PHY_VITESSE_INIT3;
1385                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1386                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1387                         return PHY_ERROR;
1388                 }
1389                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1390                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1391                         return PHY_ERROR;
1392                 }
1393                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1394                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1395                         return PHY_ERROR;
1396                 }
1397                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1398                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1399                 phy_reserved |= PHY_VITESSE_INIT3;
1400                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1401                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1402                         return PHY_ERROR;
1403                 }
1404                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1405                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1406                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1407                         return PHY_ERROR;
1408                 }
1409                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1410                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1411                         return PHY_ERROR;
1412                 }
1413                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1414                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1415                         return PHY_ERROR;
1416                 }
1417                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1418                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1419                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1420                         return PHY_ERROR;
1421                 }
1422                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1423                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1424                 phy_reserved |= PHY_VITESSE_INIT8;
1425                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1426                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1427                         return PHY_ERROR;
1428                 }
1429                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1430                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1431                         return PHY_ERROR;
1432                 }
1433                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1434                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1435                         return PHY_ERROR;
1436                 }
1437         }
1438         if (np->phy_oui == PHY_OUI_REALTEK) {
1439                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1440                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1441                         /* reset could have cleared these out, set them back */
1442                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1443                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1444                                 return PHY_ERROR;
1445                         }
1446                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1447                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1448                                 return PHY_ERROR;
1449                         }
1450                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1451                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1452                                 return PHY_ERROR;
1453                         }
1454                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1455                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1456                                 return PHY_ERROR;
1457                         }
1458                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1459                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1460                                 return PHY_ERROR;
1461                         }
1462                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1463                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1464                                 return PHY_ERROR;
1465                         }
1466                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1467                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1468                                 return PHY_ERROR;
1469                         }
1470                 }
1471                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1472                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1473                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1474                                 phy_reserved |= PHY_REALTEK_INIT7;
1475                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1476                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1477                                         return PHY_ERROR;
1478                                 }
1479                         }
1480                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1481                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1482                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1483                                         return PHY_ERROR;
1484                                 }
1485                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1486                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1487                                 phy_reserved |= PHY_REALTEK_INIT3;
1488                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1489                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1490                                         return PHY_ERROR;
1491                                 }
1492                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1493                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1494                                         return PHY_ERROR;
1495                                 }
1496                         }
1497                 }
1498         }
1499
1500         /* some phys clear out pause advertisment on reset, set it back */
1501         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1502
1503         /* restart auto negotiation, power down phy */
1504         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1505         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1506         if (phy_power_down) {
1507                 mii_control |= BMCR_PDOWN;
1508         }
1509         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1510                 return PHY_ERROR;
1511         }
1512
1513         return 0;
1514 }
1515
1516 static void nv_start_rx(struct net_device *dev)
1517 {
1518         struct fe_priv *np = netdev_priv(dev);
1519         u8 __iomem *base = get_hwbase(dev);
1520         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1521
1522         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1523         /* Already running? Stop it. */
1524         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1525                 rx_ctrl &= ~NVREG_RCVCTL_START;
1526                 writel(rx_ctrl, base + NvRegReceiverControl);
1527                 pci_push(base);
1528         }
1529         writel(np->linkspeed, base + NvRegLinkSpeed);
1530         pci_push(base);
1531         rx_ctrl |= NVREG_RCVCTL_START;
1532         if (np->mac_in_use)
1533                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1534         writel(rx_ctrl, base + NvRegReceiverControl);
1535         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1536                                 dev->name, np->duplex, np->linkspeed);
1537         pci_push(base);
1538 }
1539
1540 static void nv_stop_rx(struct net_device *dev)
1541 {
1542         struct fe_priv *np = netdev_priv(dev);
1543         u8 __iomem *base = get_hwbase(dev);
1544         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1545
1546         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1547         if (!np->mac_in_use)
1548                 rx_ctrl &= ~NVREG_RCVCTL_START;
1549         else
1550                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1551         writel(rx_ctrl, base + NvRegReceiverControl);
1552         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1553                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1554                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1555
1556         udelay(NV_RXSTOP_DELAY2);
1557         if (!np->mac_in_use)
1558                 writel(0, base + NvRegLinkSpeed);
1559 }
1560
1561 static void nv_start_tx(struct net_device *dev)
1562 {
1563         struct fe_priv *np = netdev_priv(dev);
1564         u8 __iomem *base = get_hwbase(dev);
1565         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1566
1567         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1568         tx_ctrl |= NVREG_XMITCTL_START;
1569         if (np->mac_in_use)
1570                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1571         writel(tx_ctrl, base + NvRegTransmitterControl);
1572         pci_push(base);
1573 }
1574
1575 static void nv_stop_tx(struct net_device *dev)
1576 {
1577         struct fe_priv *np = netdev_priv(dev);
1578         u8 __iomem *base = get_hwbase(dev);
1579         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1580
1581         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1582         if (!np->mac_in_use)
1583                 tx_ctrl &= ~NVREG_XMITCTL_START;
1584         else
1585                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1586         writel(tx_ctrl, base + NvRegTransmitterControl);
1587         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1588                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1589                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1590
1591         udelay(NV_TXSTOP_DELAY2);
1592         if (!np->mac_in_use)
1593                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1594                        base + NvRegTransmitPoll);
1595 }
1596
1597 static void nv_start_rxtx(struct net_device *dev)
1598 {
1599         nv_start_rx(dev);
1600         nv_start_tx(dev);
1601 }
1602
1603 static void nv_stop_rxtx(struct net_device *dev)
1604 {
1605         nv_stop_rx(dev);
1606         nv_stop_tx(dev);
1607 }
1608
1609 static void nv_txrx_reset(struct net_device *dev)
1610 {
1611         struct fe_priv *np = netdev_priv(dev);
1612         u8 __iomem *base = get_hwbase(dev);
1613
1614         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1615         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1616         pci_push(base);
1617         udelay(NV_TXRX_RESET_DELAY);
1618         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1619         pci_push(base);
1620 }
1621
1622 static void nv_mac_reset(struct net_device *dev)
1623 {
1624         struct fe_priv *np = netdev_priv(dev);
1625         u8 __iomem *base = get_hwbase(dev);
1626         u32 temp1, temp2, temp3;
1627
1628         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1629
1630         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1631         pci_push(base);
1632
1633         /* save registers since they will be cleared on reset */
1634         temp1 = readl(base + NvRegMacAddrA);
1635         temp2 = readl(base + NvRegMacAddrB);
1636         temp3 = readl(base + NvRegTransmitPoll);
1637
1638         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1639         pci_push(base);
1640         udelay(NV_MAC_RESET_DELAY);
1641         writel(0, base + NvRegMacReset);
1642         pci_push(base);
1643         udelay(NV_MAC_RESET_DELAY);
1644
1645         /* restore saved registers */
1646         writel(temp1, base + NvRegMacAddrA);
1647         writel(temp2, base + NvRegMacAddrB);
1648         writel(temp3, base + NvRegTransmitPoll);
1649
1650         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1651         pci_push(base);
1652 }
1653
1654 static void nv_get_hw_stats(struct net_device *dev)
1655 {
1656         struct fe_priv *np = netdev_priv(dev);
1657         u8 __iomem *base = get_hwbase(dev);
1658
1659         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1660         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1661         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1662         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1663         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1664         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1665         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1666         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1667         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1668         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1669         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1670         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1671         np->estats.rx_runt += readl(base + NvRegRxRunt);
1672         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1673         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1674         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1675         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1676         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1677         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1678         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1679         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1680         np->estats.rx_packets =
1681                 np->estats.rx_unicast +
1682                 np->estats.rx_multicast +
1683                 np->estats.rx_broadcast;
1684         np->estats.rx_errors_total =
1685                 np->estats.rx_crc_errors +
1686                 np->estats.rx_over_errors +
1687                 np->estats.rx_frame_error +
1688                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1689                 np->estats.rx_late_collision +
1690                 np->estats.rx_runt +
1691                 np->estats.rx_frame_too_long;
1692         np->estats.tx_errors_total =
1693                 np->estats.tx_late_collision +
1694                 np->estats.tx_fifo_errors +
1695                 np->estats.tx_carrier_errors +
1696                 np->estats.tx_excess_deferral +
1697                 np->estats.tx_retry_error;
1698
1699         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1700                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1701                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1702                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1703                 np->estats.tx_pause += readl(base + NvRegTxPause);
1704                 np->estats.rx_pause += readl(base + NvRegRxPause);
1705                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1706         }
1707
1708         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1709                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1710                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1711                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1712         }
1713 }
1714
1715 /*
1716  * nv_get_stats: dev->get_stats function
1717  * Get latest stats value from the nic.
1718  * Called with read_lock(&dev_base_lock) held for read -
1719  * only synchronized against unregister_netdevice.
1720  */
1721 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1722 {
1723         struct fe_priv *np = netdev_priv(dev);
1724
1725         /* If the nic supports hw counters then retrieve latest values */
1726         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1727                 nv_get_hw_stats(dev);
1728
1729                 /* copy to net_device stats */
1730                 dev->stats.tx_bytes = np->estats.tx_bytes;
1731                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1732                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1733                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1734                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1735                 dev->stats.rx_errors = np->estats.rx_errors_total;
1736                 dev->stats.tx_errors = np->estats.tx_errors_total;
1737         }
1738
1739         return &dev->stats;
1740 }
1741
1742 /*
1743  * nv_alloc_rx: fill rx ring entries.
1744  * Return 1 if the allocations for the skbs failed and the
1745  * rx engine is without Available descriptors
1746  */
1747 static int nv_alloc_rx(struct net_device *dev)
1748 {
1749         struct fe_priv *np = netdev_priv(dev);
1750         struct ring_desc* less_rx;
1751
1752         less_rx = np->get_rx.orig;
1753         if (less_rx-- == np->first_rx.orig)
1754                 less_rx = np->last_rx.orig;
1755
1756         while (np->put_rx.orig != less_rx) {
1757                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1758                 if (skb) {
1759                         np->put_rx_ctx->skb = skb;
1760                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1761                                                              skb->data,
1762                                                              skb_tailroom(skb),
1763                                                              PCI_DMA_FROMDEVICE);
1764                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1765                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1766                         wmb();
1767                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1768                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1769                                 np->put_rx.orig = np->first_rx.orig;
1770                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1771                                 np->put_rx_ctx = np->first_rx_ctx;
1772                 } else {
1773                         return 1;
1774                 }
1775         }
1776         return 0;
1777 }
1778
1779 static int nv_alloc_rx_optimized(struct net_device *dev)
1780 {
1781         struct fe_priv *np = netdev_priv(dev);
1782         struct ring_desc_ex* less_rx;
1783
1784         less_rx = np->get_rx.ex;
1785         if (less_rx-- == np->first_rx.ex)
1786                 less_rx = np->last_rx.ex;
1787
1788         while (np->put_rx.ex != less_rx) {
1789                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1790                 if (skb) {
1791                         np->put_rx_ctx->skb = skb;
1792                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1793                                                              skb->data,
1794                                                              skb_tailroom(skb),
1795                                                              PCI_DMA_FROMDEVICE);
1796                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1797                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1798                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1799                         wmb();
1800                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1801                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1802                                 np->put_rx.ex = np->first_rx.ex;
1803                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1804                                 np->put_rx_ctx = np->first_rx_ctx;
1805                 } else {
1806                         return 1;
1807                 }
1808         }
1809         return 0;
1810 }
1811
1812 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1813 #ifdef CONFIG_FORCEDETH_NAPI
1814 static void nv_do_rx_refill(unsigned long data)
1815 {
1816         struct net_device *dev = (struct net_device *) data;
1817         struct fe_priv *np = netdev_priv(dev);
1818
1819         /* Just reschedule NAPI rx processing */
1820         napi_schedule(&np->napi);
1821 }
1822 #else
1823 static void nv_do_rx_refill(unsigned long data)
1824 {
1825         struct net_device *dev = (struct net_device *) data;
1826         struct fe_priv *np = netdev_priv(dev);
1827         int retcode;
1828
1829         if (!using_multi_irqs(dev)) {
1830                 if (np->msi_flags & NV_MSI_X_ENABLED)
1831                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1832                 else
1833                         disable_irq(np->pci_dev->irq);
1834         } else {
1835                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1836         }
1837         if (!nv_optimized(np))
1838                 retcode = nv_alloc_rx(dev);
1839         else
1840                 retcode = nv_alloc_rx_optimized(dev);
1841         if (retcode) {
1842                 spin_lock_irq(&np->lock);
1843                 if (!np->in_shutdown)
1844                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1845                 spin_unlock_irq(&np->lock);
1846         }
1847         if (!using_multi_irqs(dev)) {
1848                 if (np->msi_flags & NV_MSI_X_ENABLED)
1849                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1850                 else
1851                         enable_irq(np->pci_dev->irq);
1852         } else {
1853                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1854         }
1855 }
1856 #endif
1857
1858 static void nv_init_rx(struct net_device *dev)
1859 {
1860         struct fe_priv *np = netdev_priv(dev);
1861         int i;
1862
1863         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1864
1865         if (!nv_optimized(np))
1866                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1867         else
1868                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1869         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1870         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1871
1872         for (i = 0; i < np->rx_ring_size; i++) {
1873                 if (!nv_optimized(np)) {
1874                         np->rx_ring.orig[i].flaglen = 0;
1875                         np->rx_ring.orig[i].buf = 0;
1876                 } else {
1877                         np->rx_ring.ex[i].flaglen = 0;
1878                         np->rx_ring.ex[i].txvlan = 0;
1879                         np->rx_ring.ex[i].bufhigh = 0;
1880                         np->rx_ring.ex[i].buflow = 0;
1881                 }
1882                 np->rx_skb[i].skb = NULL;
1883                 np->rx_skb[i].dma = 0;
1884         }
1885 }
1886
1887 static void nv_init_tx(struct net_device *dev)
1888 {
1889         struct fe_priv *np = netdev_priv(dev);
1890         int i;
1891
1892         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1893
1894         if (!nv_optimized(np))
1895                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1896         else
1897                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1898         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1899         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1900         np->tx_pkts_in_progress = 0;
1901         np->tx_change_owner = NULL;
1902         np->tx_end_flip = NULL;
1903         np->tx_stop = 0;
1904
1905         for (i = 0; i < np->tx_ring_size; i++) {
1906                 if (!nv_optimized(np)) {
1907                         np->tx_ring.orig[i].flaglen = 0;
1908                         np->tx_ring.orig[i].buf = 0;
1909                 } else {
1910                         np->tx_ring.ex[i].flaglen = 0;
1911                         np->tx_ring.ex[i].txvlan = 0;
1912                         np->tx_ring.ex[i].bufhigh = 0;
1913                         np->tx_ring.ex[i].buflow = 0;
1914                 }
1915                 np->tx_skb[i].skb = NULL;
1916                 np->tx_skb[i].dma = 0;
1917                 np->tx_skb[i].dma_len = 0;
1918                 np->tx_skb[i].dma_single = 0;
1919                 np->tx_skb[i].first_tx_desc = NULL;
1920                 np->tx_skb[i].next_tx_ctx = NULL;
1921         }
1922 }
1923
1924 static int nv_init_ring(struct net_device *dev)
1925 {
1926         struct fe_priv *np = netdev_priv(dev);
1927
1928         nv_init_tx(dev);
1929         nv_init_rx(dev);
1930
1931         if (!nv_optimized(np))
1932                 return nv_alloc_rx(dev);
1933         else
1934                 return nv_alloc_rx_optimized(dev);
1935 }
1936
1937 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1938 {
1939         if (tx_skb->dma) {
1940                 if (tx_skb->dma_single)
1941                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1942                                          tx_skb->dma_len,
1943                                          PCI_DMA_TODEVICE);
1944                 else
1945                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1946                                        tx_skb->dma_len,
1947                                        PCI_DMA_TODEVICE);
1948                 tx_skb->dma = 0;
1949         }
1950 }
1951
1952 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1953 {
1954         nv_unmap_txskb(np, tx_skb);
1955         if (tx_skb->skb) {
1956                 dev_kfree_skb_any(tx_skb->skb);
1957                 tx_skb->skb = NULL;
1958                 return 1;
1959         }
1960         return 0;
1961 }
1962
1963 static void nv_drain_tx(struct net_device *dev)
1964 {
1965         struct fe_priv *np = netdev_priv(dev);
1966         unsigned int i;
1967
1968         for (i = 0; i < np->tx_ring_size; i++) {
1969                 if (!nv_optimized(np)) {
1970                         np->tx_ring.orig[i].flaglen = 0;
1971                         np->tx_ring.orig[i].buf = 0;
1972                 } else {
1973                         np->tx_ring.ex[i].flaglen = 0;
1974                         np->tx_ring.ex[i].txvlan = 0;
1975                         np->tx_ring.ex[i].bufhigh = 0;
1976                         np->tx_ring.ex[i].buflow = 0;
1977                 }
1978                 if (nv_release_txskb(np, &np->tx_skb[i]))
1979                         dev->stats.tx_dropped++;
1980                 np->tx_skb[i].dma = 0;
1981                 np->tx_skb[i].dma_len = 0;
1982                 np->tx_skb[i].dma_single = 0;
1983                 np->tx_skb[i].first_tx_desc = NULL;
1984                 np->tx_skb[i].next_tx_ctx = NULL;
1985         }
1986         np->tx_pkts_in_progress = 0;
1987         np->tx_change_owner = NULL;
1988         np->tx_end_flip = NULL;
1989 }
1990
1991 static void nv_drain_rx(struct net_device *dev)
1992 {
1993         struct fe_priv *np = netdev_priv(dev);
1994         int i;
1995
1996         for (i = 0; i < np->rx_ring_size; i++) {
1997                 if (!nv_optimized(np)) {
1998                         np->rx_ring.orig[i].flaglen = 0;
1999                         np->rx_ring.orig[i].buf = 0;
2000                 } else {
2001                         np->rx_ring.ex[i].flaglen = 0;
2002                         np->rx_ring.ex[i].txvlan = 0;
2003                         np->rx_ring.ex[i].bufhigh = 0;
2004                         np->rx_ring.ex[i].buflow = 0;
2005                 }
2006                 wmb();
2007                 if (np->rx_skb[i].skb) {
2008                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2009                                          (skb_end_pointer(np->rx_skb[i].skb) -
2010                                           np->rx_skb[i].skb->data),
2011                                          PCI_DMA_FROMDEVICE);
2012                         dev_kfree_skb(np->rx_skb[i].skb);
2013                         np->rx_skb[i].skb = NULL;
2014                 }
2015         }
2016 }
2017
2018 static void nv_drain_rxtx(struct net_device *dev)
2019 {
2020         nv_drain_tx(dev);
2021         nv_drain_rx(dev);
2022 }
2023
2024 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2025 {
2026         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2027 }
2028
2029 static void nv_legacybackoff_reseed(struct net_device *dev)
2030 {
2031         u8 __iomem *base = get_hwbase(dev);
2032         u32 reg;
2033         u32 low;
2034         int tx_status = 0;
2035
2036         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2037         get_random_bytes(&low, sizeof(low));
2038         reg |= low & NVREG_SLOTTIME_MASK;
2039
2040         /* Need to stop tx before change takes effect.
2041          * Caller has already gained np->lock.
2042          */
2043         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2044         if (tx_status)
2045                 nv_stop_tx(dev);
2046         nv_stop_rx(dev);
2047         writel(reg, base + NvRegSlotTime);
2048         if (tx_status)
2049                 nv_start_tx(dev);
2050         nv_start_rx(dev);
2051 }
2052
2053 /* Gear Backoff Seeds */
2054 #define BACKOFF_SEEDSET_ROWS    8
2055 #define BACKOFF_SEEDSET_LFSRS   15
2056
2057 /* Known Good seed sets */
2058 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2059     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2060     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2061     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2062     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2063     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2064     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2065     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2066     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2067
2068 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2069     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2070     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2071     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2072     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2073     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2074     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2075     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2076     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2077
2078 static void nv_gear_backoff_reseed(struct net_device *dev)
2079 {
2080         u8 __iomem *base = get_hwbase(dev);
2081         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2082         u32 temp, seedset, combinedSeed;
2083         int i;
2084
2085         /* Setup seed for free running LFSR */
2086         /* We are going to read the time stamp counter 3 times
2087            and swizzle bits around to increase randomness */
2088         get_random_bytes(&miniseed1, sizeof(miniseed1));
2089         miniseed1 &= 0x0fff;
2090         if (miniseed1 == 0)
2091                 miniseed1 = 0xabc;
2092
2093         get_random_bytes(&miniseed2, sizeof(miniseed2));
2094         miniseed2 &= 0x0fff;
2095         if (miniseed2 == 0)
2096                 miniseed2 = 0xabc;
2097         miniseed2_reversed =
2098                 ((miniseed2 & 0xF00) >> 8) |
2099                  (miniseed2 & 0x0F0) |
2100                  ((miniseed2 & 0x00F) << 8);
2101
2102         get_random_bytes(&miniseed3, sizeof(miniseed3));
2103         miniseed3 &= 0x0fff;
2104         if (miniseed3 == 0)
2105                 miniseed3 = 0xabc;
2106         miniseed3_reversed =
2107                 ((miniseed3 & 0xF00) >> 8) |
2108                  (miniseed3 & 0x0F0) |
2109                  ((miniseed3 & 0x00F) << 8);
2110
2111         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2112                        (miniseed2 ^ miniseed3_reversed);
2113
2114         /* Seeds can not be zero */
2115         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2116                 combinedSeed |= 0x08;
2117         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2118                 combinedSeed |= 0x8000;
2119
2120         /* No need to disable tx here */
2121         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2122         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2123         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2124         writel(temp,base + NvRegBackOffControl);
2125
2126         /* Setup seeds for all gear LFSRs. */
2127         get_random_bytes(&seedset, sizeof(seedset));
2128         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2129         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2130         {
2131                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2132                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2133                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2134                 writel(temp, base + NvRegBackOffControl);
2135         }
2136 }
2137
2138 /*
2139  * nv_start_xmit: dev->hard_start_xmit function
2140  * Called with netif_tx_lock held.
2141  */
2142 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2143 {
2144         struct fe_priv *np = netdev_priv(dev);
2145         u32 tx_flags = 0;
2146         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2147         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2148         unsigned int i;
2149         u32 offset = 0;
2150         u32 bcnt;
2151         u32 size = skb->len-skb->data_len;
2152         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2153         u32 empty_slots;
2154         struct ring_desc* put_tx;
2155         struct ring_desc* start_tx;
2156         struct ring_desc* prev_tx;
2157         struct nv_skb_map* prev_tx_ctx;
2158         unsigned long flags;
2159
2160         /* add fragments to entries count */
2161         for (i = 0; i < fragments; i++) {
2162                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2163                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2164         }
2165
2166         spin_lock_irqsave(&np->lock, flags);
2167         empty_slots = nv_get_empty_tx_slots(np);
2168         if (unlikely(empty_slots <= entries)) {
2169                 netif_stop_queue(dev);
2170                 np->tx_stop = 1;
2171                 spin_unlock_irqrestore(&np->lock, flags);
2172                 return NETDEV_TX_BUSY;
2173         }
2174         spin_unlock_irqrestore(&np->lock, flags);
2175
2176         start_tx = put_tx = np->put_tx.orig;
2177
2178         /* setup the header buffer */
2179         do {
2180                 prev_tx = put_tx;
2181                 prev_tx_ctx = np->put_tx_ctx;
2182                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2183                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2184                                                 PCI_DMA_TODEVICE);
2185                 np->put_tx_ctx->dma_len = bcnt;
2186                 np->put_tx_ctx->dma_single = 1;
2187                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2188                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2189
2190                 tx_flags = np->tx_flags;
2191                 offset += bcnt;
2192                 size -= bcnt;
2193                 if (unlikely(put_tx++ == np->last_tx.orig))
2194                         put_tx = np->first_tx.orig;
2195                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2196                         np->put_tx_ctx = np->first_tx_ctx;
2197         } while (size);
2198
2199         /* setup the fragments */
2200         for (i = 0; i < fragments; i++) {
2201                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2202                 u32 size = frag->size;
2203                 offset = 0;
2204
2205                 do {
2206                         prev_tx = put_tx;
2207                         prev_tx_ctx = np->put_tx_ctx;
2208                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2209                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2210                                                            PCI_DMA_TODEVICE);
2211                         np->put_tx_ctx->dma_len = bcnt;
2212                         np->put_tx_ctx->dma_single = 0;
2213                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2214                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2215
2216                         offset += bcnt;
2217                         size -= bcnt;
2218                         if (unlikely(put_tx++ == np->last_tx.orig))
2219                                 put_tx = np->first_tx.orig;
2220                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2221                                 np->put_tx_ctx = np->first_tx_ctx;
2222                 } while (size);
2223         }
2224
2225         /* set last fragment flag  */
2226         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2227
2228         /* save skb in this slot's context area */
2229         prev_tx_ctx->skb = skb;
2230
2231         if (skb_is_gso(skb))
2232                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2233         else
2234                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2235                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2236
2237         spin_lock_irqsave(&np->lock, flags);
2238
2239         /* set tx flags */
2240         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2241         np->put_tx.orig = put_tx;
2242
2243         spin_unlock_irqrestore(&np->lock, flags);
2244
2245         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2246                 dev->name, entries, tx_flags_extra);
2247         {
2248                 int j;
2249                 for (j=0; j<64; j++) {
2250                         if ((j%16) == 0)
2251                                 dprintk("\n%03x:", j);
2252                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2253                 }
2254                 dprintk("\n");
2255         }
2256
2257         dev->trans_start = jiffies;
2258         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2259         return NETDEV_TX_OK;
2260 }
2261
2262 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2263                                            struct net_device *dev)
2264 {
2265         struct fe_priv *np = netdev_priv(dev);
2266         u32 tx_flags = 0;
2267         u32 tx_flags_extra;
2268         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2269         unsigned int i;
2270         u32 offset = 0;
2271         u32 bcnt;
2272         u32 size = skb->len-skb->data_len;
2273         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2274         u32 empty_slots;
2275         struct ring_desc_ex* put_tx;
2276         struct ring_desc_ex* start_tx;
2277         struct ring_desc_ex* prev_tx;
2278         struct nv_skb_map* prev_tx_ctx;
2279         struct nv_skb_map* start_tx_ctx;
2280         unsigned long flags;
2281
2282         /* add fragments to entries count */
2283         for (i = 0; i < fragments; i++) {
2284                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2285                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2286         }
2287
2288         spin_lock_irqsave(&np->lock, flags);
2289         empty_slots = nv_get_empty_tx_slots(np);
2290         if (unlikely(empty_slots <= entries)) {
2291                 netif_stop_queue(dev);
2292                 np->tx_stop = 1;
2293                 spin_unlock_irqrestore(&np->lock, flags);
2294                 return NETDEV_TX_BUSY;
2295         }
2296         spin_unlock_irqrestore(&np->lock, flags);
2297
2298         start_tx = put_tx = np->put_tx.ex;
2299         start_tx_ctx = np->put_tx_ctx;
2300
2301         /* setup the header buffer */
2302         do {
2303                 prev_tx = put_tx;
2304                 prev_tx_ctx = np->put_tx_ctx;
2305                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2306                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2307                                                 PCI_DMA_TODEVICE);
2308                 np->put_tx_ctx->dma_len = bcnt;
2309                 np->put_tx_ctx->dma_single = 1;
2310                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2311                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2312                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2313
2314                 tx_flags = NV_TX2_VALID;
2315                 offset += bcnt;
2316                 size -= bcnt;
2317                 if (unlikely(put_tx++ == np->last_tx.ex))
2318                         put_tx = np->first_tx.ex;
2319                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2320                         np->put_tx_ctx = np->first_tx_ctx;
2321         } while (size);
2322
2323         /* setup the fragments */
2324         for (i = 0; i < fragments; i++) {
2325                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2326                 u32 size = frag->size;
2327                 offset = 0;
2328
2329                 do {
2330                         prev_tx = put_tx;
2331                         prev_tx_ctx = np->put_tx_ctx;
2332                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2333                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2334                                                            PCI_DMA_TODEVICE);
2335                         np->put_tx_ctx->dma_len = bcnt;
2336                         np->put_tx_ctx->dma_single = 0;
2337                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2338                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2339                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2340
2341                         offset += bcnt;
2342                         size -= bcnt;
2343                         if (unlikely(put_tx++ == np->last_tx.ex))
2344                                 put_tx = np->first_tx.ex;
2345                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2346                                 np->put_tx_ctx = np->first_tx_ctx;
2347                 } while (size);
2348         }
2349
2350         /* set last fragment flag  */
2351         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2352
2353         /* save skb in this slot's context area */
2354         prev_tx_ctx->skb = skb;
2355
2356         if (skb_is_gso(skb))
2357                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2358         else
2359                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2360                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2361
2362         /* vlan tag */
2363         if (likely(!np->vlangrp)) {
2364                 start_tx->txvlan = 0;
2365         } else {
2366                 if (vlan_tx_tag_present(skb))
2367                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2368                 else
2369                         start_tx->txvlan = 0;
2370         }
2371
2372         spin_lock_irqsave(&np->lock, flags);
2373
2374         if (np->tx_limit) {
2375                 /* Limit the number of outstanding tx. Setup all fragments, but
2376                  * do not set the VALID bit on the first descriptor. Save a pointer
2377                  * to that descriptor and also for next skb_map element.
2378                  */
2379
2380                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2381                         if (!np->tx_change_owner)
2382                                 np->tx_change_owner = start_tx_ctx;
2383
2384                         /* remove VALID bit */
2385                         tx_flags &= ~NV_TX2_VALID;
2386                         start_tx_ctx->first_tx_desc = start_tx;
2387                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2388                         np->tx_end_flip = np->put_tx_ctx;
2389                 } else {
2390                         np->tx_pkts_in_progress++;
2391                 }
2392         }
2393
2394         /* set tx flags */
2395         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2396         np->put_tx.ex = put_tx;
2397
2398         spin_unlock_irqrestore(&np->lock, flags);
2399
2400         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2401                 dev->name, entries, tx_flags_extra);
2402         {
2403                 int j;
2404                 for (j=0; j<64; j++) {
2405                         if ((j%16) == 0)
2406                                 dprintk("\n%03x:", j);
2407                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2408                 }
2409                 dprintk("\n");
2410         }
2411
2412         dev->trans_start = jiffies;
2413         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2414         return NETDEV_TX_OK;
2415 }
2416
2417 static inline void nv_tx_flip_ownership(struct net_device *dev)
2418 {
2419         struct fe_priv *np = netdev_priv(dev);
2420
2421         np->tx_pkts_in_progress--;
2422         if (np->tx_change_owner) {
2423                 np->tx_change_owner->first_tx_desc->flaglen |=
2424                         cpu_to_le32(NV_TX2_VALID);
2425                 np->tx_pkts_in_progress++;
2426
2427                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2428                 if (np->tx_change_owner == np->tx_end_flip)
2429                         np->tx_change_owner = NULL;
2430
2431                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2432         }
2433 }
2434
2435 /*
2436  * nv_tx_done: check for completed packets, release the skbs.
2437  *
2438  * Caller must own np->lock.
2439  */
2440 static int nv_tx_done(struct net_device *dev, int limit)
2441 {
2442         struct fe_priv *np = netdev_priv(dev);
2443         u32 flags;
2444         int tx_work = 0;
2445         struct ring_desc* orig_get_tx = np->get_tx.orig;
2446
2447         while ((np->get_tx.orig != np->put_tx.orig) &&
2448                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2449                (tx_work < limit)) {
2450
2451                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2452                                         dev->name, flags);
2453
2454                 nv_unmap_txskb(np, np->get_tx_ctx);
2455
2456                 if (np->desc_ver == DESC_VER_1) {
2457                         if (flags & NV_TX_LASTPACKET) {
2458                                 if (flags & NV_TX_ERROR) {
2459                                         if (flags & NV_TX_UNDERFLOW)
2460                                                 dev->stats.tx_fifo_errors++;
2461                                         if (flags & NV_TX_CARRIERLOST)
2462                                                 dev->stats.tx_carrier_errors++;
2463                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2464                                                 nv_legacybackoff_reseed(dev);
2465                                         dev->stats.tx_errors++;
2466                                 } else {
2467                                         dev->stats.tx_packets++;
2468                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2469                                 }
2470                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2471                                 np->get_tx_ctx->skb = NULL;
2472                                 tx_work++;
2473                         }
2474                 } else {
2475                         if (flags & NV_TX2_LASTPACKET) {
2476                                 if (flags & NV_TX2_ERROR) {
2477                                         if (flags & NV_TX2_UNDERFLOW)
2478                                                 dev->stats.tx_fifo_errors++;
2479                                         if (flags & NV_TX2_CARRIERLOST)
2480                                                 dev->stats.tx_carrier_errors++;
2481                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2482                                                 nv_legacybackoff_reseed(dev);
2483                                         dev->stats.tx_errors++;
2484                                 } else {
2485                                         dev->stats.tx_packets++;
2486                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2487                                 }
2488                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2489                                 np->get_tx_ctx->skb = NULL;
2490                                 tx_work++;
2491                         }
2492                 }
2493                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2494                         np->get_tx.orig = np->first_tx.orig;
2495                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2496                         np->get_tx_ctx = np->first_tx_ctx;
2497         }
2498         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2499                 np->tx_stop = 0;
2500                 netif_wake_queue(dev);
2501         }
2502         return tx_work;
2503 }
2504
2505 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2506 {
2507         struct fe_priv *np = netdev_priv(dev);
2508         u32 flags;
2509         int tx_work = 0;
2510         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2511
2512         while ((np->get_tx.ex != np->put_tx.ex) &&
2513                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2514                (tx_work < limit)) {
2515
2516                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2517                                         dev->name, flags);
2518
2519                 nv_unmap_txskb(np, np->get_tx_ctx);
2520
2521                 if (flags & NV_TX2_LASTPACKET) {
2522                         if (!(flags & NV_TX2_ERROR))
2523                                 dev->stats.tx_packets++;
2524                         else {
2525                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2526                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2527                                                 nv_gear_backoff_reseed(dev);
2528                                         else
2529                                                 nv_legacybackoff_reseed(dev);
2530                                 }
2531                         }
2532
2533                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2534                         np->get_tx_ctx->skb = NULL;
2535                         tx_work++;
2536
2537                         if (np->tx_limit) {
2538                                 nv_tx_flip_ownership(dev);
2539                         }
2540                 }
2541                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2542                         np->get_tx.ex = np->first_tx.ex;
2543                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2544                         np->get_tx_ctx = np->first_tx_ctx;
2545         }
2546         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2547                 np->tx_stop = 0;
2548                 netif_wake_queue(dev);
2549         }
2550         return tx_work;
2551 }
2552
2553 /*
2554  * nv_tx_timeout: dev->tx_timeout function
2555  * Called with netif_tx_lock held.
2556  */
2557 static void nv_tx_timeout(struct net_device *dev)
2558 {
2559         struct fe_priv *np = netdev_priv(dev);
2560         u8 __iomem *base = get_hwbase(dev);
2561         u32 status;
2562         union ring_type put_tx;
2563         int saved_tx_limit;
2564
2565         if (np->msi_flags & NV_MSI_X_ENABLED)
2566                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2567         else
2568                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2569
2570         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2571
2572         {
2573                 int i;
2574
2575                 printk(KERN_INFO "%s: Ring at %lx\n",
2576                        dev->name, (unsigned long)np->ring_addr);
2577                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2578                 for (i=0;i<=np->register_size;i+= 32) {
2579                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2580                                         i,
2581                                         readl(base + i + 0), readl(base + i + 4),
2582                                         readl(base + i + 8), readl(base + i + 12),
2583                                         readl(base + i + 16), readl(base + i + 20),
2584                                         readl(base + i + 24), readl(base + i + 28));
2585                 }
2586                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2587                 for (i=0;i<np->tx_ring_size;i+= 4) {
2588                         if (!nv_optimized(np)) {
2589                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2590                                        i,
2591                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2592                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2593                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2594                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2595                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2596                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2597                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2598                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2599                         } else {
2600                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2601                                        i,
2602                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2603                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2604                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2605                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2606                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2607                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2608                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2609                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2610                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2611                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2612                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2613                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2614                         }
2615                 }
2616         }
2617
2618         spin_lock_irq(&np->lock);
2619
2620         /* 1) stop tx engine */
2621         nv_stop_tx(dev);
2622
2623         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2624         saved_tx_limit = np->tx_limit;
2625         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2626         np->tx_stop = 0;  /* prevent waking tx queue */
2627         if (!nv_optimized(np))
2628                 nv_tx_done(dev, np->tx_ring_size);
2629         else
2630                 nv_tx_done_optimized(dev, np->tx_ring_size);
2631
2632         /* save current HW postion */
2633         if (np->tx_change_owner)
2634                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2635         else
2636                 put_tx = np->put_tx;
2637
2638         /* 3) clear all tx state */
2639         nv_drain_tx(dev);
2640         nv_init_tx(dev);
2641
2642         /* 4) restore state to current HW position */
2643         np->get_tx = np->put_tx = put_tx;
2644         np->tx_limit = saved_tx_limit;
2645
2646         /* 5) restart tx engine */
2647         nv_start_tx(dev);
2648         netif_wake_queue(dev);
2649         spin_unlock_irq(&np->lock);
2650 }
2651
2652 /*
2653  * Called when the nic notices a mismatch between the actual data len on the
2654  * wire and the len indicated in the 802 header
2655  */
2656 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2657 {
2658         int hdrlen;     /* length of the 802 header */
2659         int protolen;   /* length as stored in the proto field */
2660
2661         /* 1) calculate len according to header */
2662         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2663                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2664                 hdrlen = VLAN_HLEN;
2665         } else {
2666                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2667                 hdrlen = ETH_HLEN;
2668         }
2669         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2670                                 dev->name, datalen, protolen, hdrlen);
2671         if (protolen > ETH_DATA_LEN)
2672                 return datalen; /* Value in proto field not a len, no checks possible */
2673
2674         protolen += hdrlen;
2675         /* consistency checks: */
2676         if (datalen > ETH_ZLEN) {
2677                 if (datalen >= protolen) {
2678                         /* more data on wire than in 802 header, trim of
2679                          * additional data.
2680                          */
2681                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2682                                         dev->name, protolen);
2683                         return protolen;
2684                 } else {
2685                         /* less data on wire than mentioned in header.
2686                          * Discard the packet.
2687                          */
2688                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2689                                         dev->name);
2690                         return -1;
2691                 }
2692         } else {
2693                 /* short packet. Accept only if 802 values are also short */
2694                 if (protolen > ETH_ZLEN) {
2695                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2696                                         dev->name);
2697                         return -1;
2698                 }
2699                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2700                                 dev->name, datalen);
2701                 return datalen;
2702         }
2703 }
2704
2705 static int nv_rx_process(struct net_device *dev, int limit)
2706 {
2707         struct fe_priv *np = netdev_priv(dev);
2708         u32 flags;
2709         int rx_work = 0;
2710         struct sk_buff *skb;
2711         int len;
2712
2713         while((np->get_rx.orig != np->put_rx.orig) &&
2714               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2715                 (rx_work < limit)) {
2716
2717                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2718                                         dev->name, flags);
2719
2720                 /*
2721                  * the packet is for us - immediately tear down the pci mapping.
2722                  * TODO: check if a prefetch of the first cacheline improves
2723                  * the performance.
2724                  */
2725                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2726                                 np->get_rx_ctx->dma_len,
2727                                 PCI_DMA_FROMDEVICE);
2728                 skb = np->get_rx_ctx->skb;
2729                 np->get_rx_ctx->skb = NULL;
2730
2731                 {
2732                         int j;
2733                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2734                         for (j=0; j<64; j++) {
2735                                 if ((j%16) == 0)
2736                                         dprintk("\n%03x:", j);
2737                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2738                         }
2739                         dprintk("\n");
2740                 }
2741                 /* look at what we actually got: */
2742                 if (np->desc_ver == DESC_VER_1) {
2743                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2744                                 len = flags & LEN_MASK_V1;
2745                                 if (unlikely(flags & NV_RX_ERROR)) {
2746                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2747                                                 len = nv_getlen(dev, skb->data, len);
2748                                                 if (len < 0) {
2749                                                         dev->stats.rx_errors++;
2750                                                         dev_kfree_skb(skb);
2751                                                         goto next_pkt;
2752                                                 }
2753                                         }
2754                                         /* framing errors are soft errors */
2755                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2756                                                 if (flags & NV_RX_SUBSTRACT1) {
2757                                                         len--;
2758                                                 }
2759                                         }
2760                                         /* the rest are hard errors */
2761                                         else {
2762                                                 if (flags & NV_RX_MISSEDFRAME)
2763                                                         dev->stats.rx_missed_errors++;
2764                                                 if (flags & NV_RX_CRCERR)
2765                                                         dev->stats.rx_crc_errors++;
2766                                                 if (flags & NV_RX_OVERFLOW)
2767                                                         dev->stats.rx_over_errors++;
2768                                                 dev->stats.rx_errors++;
2769                                                 dev_kfree_skb(skb);
2770                                                 goto next_pkt;
2771                                         }
2772                                 }
2773                         } else {
2774                                 dev_kfree_skb(skb);
2775                                 goto next_pkt;
2776                         }
2777                 } else {
2778                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2779                                 len = flags & LEN_MASK_V2;
2780                                 if (unlikely(flags & NV_RX2_ERROR)) {
2781                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2782                                                 len = nv_getlen(dev, skb->data, len);
2783                                                 if (len < 0) {
2784                                                         dev->stats.rx_errors++;
2785                                                         dev_kfree_skb(skb);
2786                                                         goto next_pkt;
2787                                                 }
2788                                         }
2789                                         /* framing errors are soft errors */
2790                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2791                                                 if (flags & NV_RX2_SUBSTRACT1) {
2792                                                         len--;
2793                                                 }
2794                                         }
2795                                         /* the rest are hard errors */
2796                                         else {
2797                                                 if (flags & NV_RX2_CRCERR)
2798                                                         dev->stats.rx_crc_errors++;
2799                                                 if (flags & NV_RX2_OVERFLOW)
2800                                                         dev->stats.rx_over_errors++;
2801                                                 dev->stats.rx_errors++;
2802                                                 dev_kfree_skb(skb);
2803                                                 goto next_pkt;
2804                                         }
2805                                 }
2806                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2807                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2808                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2809                         } else {
2810                                 dev_kfree_skb(skb);
2811                                 goto next_pkt;
2812                         }
2813                 }
2814                 /* got a valid packet - forward it to the network core */
2815                 skb_put(skb, len);
2816                 skb->protocol = eth_type_trans(skb, dev);
2817                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2818                                         dev->name, len, skb->protocol);
2819 #ifdef CONFIG_FORCEDETH_NAPI
2820                 netif_receive_skb(skb);
2821 #else
2822                 netif_rx(skb);
2823 #endif
2824                 dev->stats.rx_packets++;
2825                 dev->stats.rx_bytes += len;
2826 next_pkt:
2827                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2828                         np->get_rx.orig = np->first_rx.orig;
2829                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2830                         np->get_rx_ctx = np->first_rx_ctx;
2831
2832                 rx_work++;
2833         }
2834
2835         return rx_work;
2836 }
2837
2838 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2839 {
2840         struct fe_priv *np = netdev_priv(dev);
2841         u32 flags;
2842         u32 vlanflags = 0;
2843         int rx_work = 0;
2844         struct sk_buff *skb;
2845         int len;
2846
2847         while((np->get_rx.ex != np->put_rx.ex) &&
2848               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2849               (rx_work < limit)) {
2850
2851                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2852                                         dev->name, flags);
2853
2854                 /*
2855                  * the packet is for us - immediately tear down the pci mapping.
2856                  * TODO: check if a prefetch of the first cacheline improves
2857                  * the performance.
2858                  */
2859                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2860                                 np->get_rx_ctx->dma_len,
2861                                 PCI_DMA_FROMDEVICE);
2862                 skb = np->get_rx_ctx->skb;
2863                 np->get_rx_ctx->skb = NULL;
2864
2865                 {
2866                         int j;
2867                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2868                         for (j=0; j<64; j++) {
2869                                 if ((j%16) == 0)
2870                                         dprintk("\n%03x:", j);
2871                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2872                         }
2873                         dprintk("\n");
2874                 }
2875                 /* look at what we actually got: */
2876                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2877                         len = flags & LEN_MASK_V2;
2878                         if (unlikely(flags & NV_RX2_ERROR)) {
2879                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2880                                         len = nv_getlen(dev, skb->data, len);
2881                                         if (len < 0) {
2882                                                 dev_kfree_skb(skb);
2883                                                 goto next_pkt;
2884                                         }
2885                                 }
2886                                 /* framing errors are soft errors */
2887                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2888                                         if (flags & NV_RX2_SUBSTRACT1) {
2889                                                 len--;
2890                                         }
2891                                 }
2892                                 /* the rest are hard errors */
2893                                 else {
2894                                         dev_kfree_skb(skb);
2895                                         goto next_pkt;
2896                                 }
2897                         }
2898
2899                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2900                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2901                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2902
2903                         /* got a valid packet - forward it to the network core */
2904                         skb_put(skb, len);
2905                         skb->protocol = eth_type_trans(skb, dev);
2906                         prefetch(skb->data);
2907
2908                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2909                                 dev->name, len, skb->protocol);
2910
2911                         if (likely(!np->vlangrp)) {
2912 #ifdef CONFIG_FORCEDETH_NAPI
2913                                 netif_receive_skb(skb);
2914 #else
2915                                 netif_rx(skb);
2916 #endif
2917                         } else {
2918                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2919                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2920 #ifdef CONFIG_FORCEDETH_NAPI
2921                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2922                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2923 #else
2924                                         vlan_hwaccel_rx(skb, np->vlangrp,
2925                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2926 #endif
2927                                 } else {
2928 #ifdef CONFIG_FORCEDETH_NAPI
2929                                         netif_receive_skb(skb);
2930 #else
2931                                         netif_rx(skb);
2932 #endif
2933                                 }
2934                         }
2935
2936                         dev->stats.rx_packets++;
2937                         dev->stats.rx_bytes += len;
2938                 } else {
2939                         dev_kfree_skb(skb);
2940                 }
2941 next_pkt:
2942                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2943                         np->get_rx.ex = np->first_rx.ex;
2944                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2945                         np->get_rx_ctx = np->first_rx_ctx;
2946
2947                 rx_work++;
2948         }
2949
2950         return rx_work;
2951 }
2952
2953 static void set_bufsize(struct net_device *dev)
2954 {
2955         struct fe_priv *np = netdev_priv(dev);
2956
2957         if (dev->mtu <= ETH_DATA_LEN)
2958                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2959         else
2960                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2961 }
2962
2963 /*
2964  * nv_change_mtu: dev->change_mtu function
2965  * Called with dev_base_lock held for read.
2966  */
2967 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2968 {
2969         struct fe_priv *np = netdev_priv(dev);
2970         int old_mtu;
2971
2972         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2973                 return -EINVAL;
2974
2975         old_mtu = dev->mtu;
2976         dev->mtu = new_mtu;
2977
2978         /* return early if the buffer sizes will not change */
2979         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2980                 return 0;
2981         if (old_mtu == new_mtu)
2982                 return 0;
2983
2984         /* synchronized against open : rtnl_lock() held by caller */
2985         if (netif_running(dev)) {
2986                 u8 __iomem *base = get_hwbase(dev);
2987                 /*
2988                  * It seems that the nic preloads valid ring entries into an
2989                  * internal buffer. The procedure for flushing everything is
2990                  * guessed, there is probably a simpler approach.
2991                  * Changing the MTU is a rare event, it shouldn't matter.
2992                  */
2993                 nv_disable_irq(dev);
2994                 nv_napi_disable(dev);
2995                 netif_tx_lock_bh(dev);
2996                 netif_addr_lock(dev);
2997                 spin_lock(&np->lock);
2998                 /* stop engines */
2999                 nv_stop_rxtx(dev);
3000                 nv_txrx_reset(dev);
3001                 /* drain rx queue */
3002                 nv_drain_rxtx(dev);
3003                 /* reinit driver view of the rx queue */
3004                 set_bufsize(dev);
3005                 if (nv_init_ring(dev)) {
3006                         if (!np->in_shutdown)
3007                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3008                 }
3009                 /* reinit nic view of the rx queue */
3010                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3011                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3012                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3013                         base + NvRegRingSizes);
3014                 pci_push(base);
3015                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3016                 pci_push(base);
3017
3018                 /* restart rx engine */
3019                 nv_start_rxtx(dev);
3020                 spin_unlock(&np->lock);
3021                 netif_addr_unlock(dev);
3022                 netif_tx_unlock_bh(dev);
3023                 nv_napi_enable(dev);
3024                 nv_enable_irq(dev);
3025         }
3026         return 0;
3027 }
3028
3029 static void nv_copy_mac_to_hw(struct net_device *dev)
3030 {
3031         u8 __iomem *base = get_hwbase(dev);
3032         u32 mac[2];
3033
3034         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3035                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3036         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3037
3038         writel(mac[0], base + NvRegMacAddrA);
3039         writel(mac[1], base + NvRegMacAddrB);
3040 }
3041
3042 /*
3043  * nv_set_mac_address: dev->set_mac_address function
3044  * Called with rtnl_lock() held.
3045  */
3046 static int nv_set_mac_address(struct net_device *dev, void *addr)
3047 {
3048         struct fe_priv *np = netdev_priv(dev);
3049         struct sockaddr *macaddr = (struct sockaddr*)addr;
3050
3051         if (!is_valid_ether_addr(macaddr->sa_data))
3052                 return -EADDRNOTAVAIL;
3053
3054         /* synchronized against open : rtnl_lock() held by caller */
3055         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3056
3057         if (netif_running(dev)) {
3058                 netif_tx_lock_bh(dev);
3059                 netif_addr_lock(dev);
3060                 spin_lock_irq(&np->lock);
3061
3062                 /* stop rx engine */
3063                 nv_stop_rx(dev);
3064
3065                 /* set mac address */
3066                 nv_copy_mac_to_hw(dev);
3067
3068                 /* restart rx engine */
3069                 nv_start_rx(dev);
3070                 spin_unlock_irq(&np->lock);
3071                 netif_addr_unlock(dev);
3072                 netif_tx_unlock_bh(dev);
3073         } else {
3074                 nv_copy_mac_to_hw(dev);
3075         }
3076         return 0;
3077 }
3078
3079 /*
3080  * nv_set_multicast: dev->set_multicast function
3081  * Called with netif_tx_lock held.
3082  */
3083 static void nv_set_multicast(struct net_device *dev)
3084 {
3085         struct fe_priv *np = netdev_priv(dev);
3086         u8 __iomem *base = get_hwbase(dev);
3087         u32 addr[2];
3088         u32 mask[2];
3089         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3090
3091         memset(addr, 0, sizeof(addr));
3092         memset(mask, 0, sizeof(mask));
3093
3094         if (dev->flags & IFF_PROMISC) {
3095                 pff |= NVREG_PFF_PROMISC;
3096         } else {
3097                 pff |= NVREG_PFF_MYADDR;
3098
3099                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3100                         u32 alwaysOff[2];
3101                         u32 alwaysOn[2];
3102
3103                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3104                         if (dev->flags & IFF_ALLMULTI) {
3105                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3106                         } else {
3107                                 struct netdev_hw_addr *ha;
3108
3109                                 netdev_for_each_mc_addr(ha, dev) {
3110                                         unsigned char *addr = ha->addr;
3111                                         u32 a, b;
3112
3113                                         a = le32_to_cpu(*(__le32 *) addr);
3114                                         b = le16_to_cpu(*(__le16 *) (&addr[4]));
3115                                         alwaysOn[0] &= a;
3116                                         alwaysOff[0] &= ~a;
3117                                         alwaysOn[1] &= b;
3118                                         alwaysOff[1] &= ~b;
3119                                 }
3120                         }
3121                         addr[0] = alwaysOn[0];
3122                         addr[1] = alwaysOn[1];
3123                         mask[0] = alwaysOn[0] | alwaysOff[0];
3124                         mask[1] = alwaysOn[1] | alwaysOff[1];
3125                 } else {
3126                         mask[0] = NVREG_MCASTMASKA_NONE;
3127                         mask[1] = NVREG_MCASTMASKB_NONE;
3128                 }
3129         }
3130         addr[0] |= NVREG_MCASTADDRA_FORCE;
3131         pff |= NVREG_PFF_ALWAYS;
3132         spin_lock_irq(&np->lock);
3133         nv_stop_rx(dev);
3134         writel(addr[0], base + NvRegMulticastAddrA);
3135         writel(addr[1], base + NvRegMulticastAddrB);
3136         writel(mask[0], base + NvRegMulticastMaskA);
3137         writel(mask[1], base + NvRegMulticastMaskB);
3138         writel(pff, base + NvRegPacketFilterFlags);
3139         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3140                 dev->name);
3141         nv_start_rx(dev);
3142         spin_unlock_irq(&np->lock);
3143 }
3144
3145 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3146 {
3147         struct fe_priv *np = netdev_priv(dev);
3148         u8 __iomem *base = get_hwbase(dev);
3149
3150         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3151
3152         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3153                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3154                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3155                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3156                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3157                 } else {
3158                         writel(pff, base + NvRegPacketFilterFlags);
3159                 }
3160         }
3161         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3162                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3163                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3164                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3165                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3166                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3167                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3168                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3169                                 /* limit the number of tx pause frames to a default of 8 */
3170                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3171                         }
3172                         writel(pause_enable,  base + NvRegTxPauseFrame);
3173                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3174                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3175                 } else {
3176                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3177                         writel(regmisc, base + NvRegMisc1);
3178                 }
3179         }
3180 }
3181
3182 /**
3183  * nv_update_linkspeed: Setup the MAC according to the link partner
3184  * @dev: Network device to be configured
3185  *
3186  * The function queries the PHY and checks if there is a link partner.
3187  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3188  * set to 10 MBit HD.
3189  *
3190  * The function returns 0 if there is no link partner and 1 if there is
3191  * a good link partner.
3192  */
3193 static int nv_update_linkspeed(struct net_device *dev)
3194 {
3195         struct fe_priv *np = netdev_priv(dev);
3196         u8 __iomem *base = get_hwbase(dev);
3197         int adv = 0;
3198         int lpa = 0;
3199         int adv_lpa, adv_pause, lpa_pause;
3200         int newls = np->linkspeed;
3201         int newdup = np->duplex;
3202         int mii_status;
3203         int retval = 0;
3204         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3205         u32 txrxFlags = 0;
3206         u32 phy_exp;
3207
3208         /* BMSR_LSTATUS is latched, read it twice:
3209          * we want the current value.
3210          */
3211         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3212         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3213
3214         if (!(mii_status & BMSR_LSTATUS)) {
3215                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3216                                 dev->name);
3217                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3218                 newdup = 0;
3219                 retval = 0;
3220                 goto set_speed;
3221         }
3222
3223         if (np->autoneg == 0) {
3224                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3225                                 dev->name, np->fixed_mode);
3226                 if (np->fixed_mode & LPA_100FULL) {
3227                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3228                         newdup = 1;
3229                 } else if (np->fixed_mode & LPA_100HALF) {
3230                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3231                         newdup = 0;
3232                 } else if (np->fixed_mode & LPA_10FULL) {
3233                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3234                         newdup = 1;
3235                 } else {
3236                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3237                         newdup = 0;
3238                 }
3239                 retval = 1;
3240                 goto set_speed;
3241         }
3242         /* check auto negotiation is complete */
3243         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3244                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3245                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3246                 newdup = 0;
3247                 retval = 0;
3248                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3249                 goto set_speed;
3250         }
3251
3252         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3253         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3254         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3255                                 dev->name, adv, lpa);
3256
3257         retval = 1;
3258         if (np->gigabit == PHY_GIGABIT) {
3259                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3260                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3261
3262                 if ((control_1000 & ADVERTISE_1000FULL) &&
3263                         (status_1000 & LPA_1000FULL)) {
3264                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3265                                 dev->name);
3266                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3267                         newdup = 1;
3268                         goto set_speed;
3269                 }
3270         }
3271
3272         /* FIXME: handle parallel detection properly */
3273         adv_lpa = lpa & adv;
3274         if (adv_lpa & LPA_100FULL) {
3275                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3276                 newdup = 1;
3277         } else if (adv_lpa & LPA_100HALF) {
3278                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3279                 newdup = 0;
3280         } else if (adv_lpa & LPA_10FULL) {
3281                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3282                 newdup = 1;
3283         } else if (adv_lpa & LPA_10HALF) {
3284                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3285                 newdup = 0;
3286         } else {
3287                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3288                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3289                 newdup = 0;
3290         }
3291
3292 set_speed:
3293         if (np->duplex == newdup && np->linkspeed == newls)
3294                 return retval;
3295
3296         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3297                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3298
3299         np->duplex = newdup;
3300         np->linkspeed = newls;
3301
3302         /* The transmitter and receiver must be restarted for safe update */
3303         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3304                 txrxFlags |= NV_RESTART_TX;
3305                 nv_stop_tx(dev);
3306         }
3307         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3308                 txrxFlags |= NV_RESTART_RX;
3309                 nv_stop_rx(dev);
3310         }
3311
3312         if (np->gigabit == PHY_GIGABIT) {
3313                 phyreg = readl(base + NvRegSlotTime);
3314                 phyreg &= ~(0x3FF00);
3315                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3316                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3317                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3318                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3319                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3320                 writel(phyreg, base + NvRegSlotTime);
3321         }
3322
3323         phyreg = readl(base + NvRegPhyInterface);
3324         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3325         if (np->duplex == 0)
3326                 phyreg |= PHY_HALF;
3327         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3328                 phyreg |= PHY_100;
3329         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3330                 phyreg |= PHY_1000;
3331         writel(phyreg, base + NvRegPhyInterface);
3332
3333         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3334         if (phyreg & PHY_RGMII) {
3335                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3336                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3337                 } else {
3338                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3339                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3340                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3341                                 else
3342                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3343                         } else {
3344                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3345                         }
3346                 }
3347         } else {
3348                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3349                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3350                 else
3351                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3352         }
3353         writel(txreg, base + NvRegTxDeferral);
3354
3355         if (np->desc_ver == DESC_VER_1) {
3356                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3357         } else {
3358                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3359                         txreg = NVREG_TX_WM_DESC2_3_1000;
3360                 else
3361                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3362         }
3363         writel(txreg, base + NvRegTxWatermark);
3364
3365         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3366                 base + NvRegMisc1);
3367         pci_push(base);
3368         writel(np->linkspeed, base + NvRegLinkSpeed);
3369         pci_push(base);
3370
3371         pause_flags = 0;
3372         /* setup pause frame */
3373         if (np->duplex != 0) {
3374                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3375                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3376                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3377
3378                         switch (adv_pause) {
3379                         case ADVERTISE_PAUSE_CAP:
3380                                 if (lpa_pause & LPA_PAUSE_CAP) {
3381                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3382                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3383                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3384                                 }
3385                                 break;
3386                         case ADVERTISE_PAUSE_ASYM:
3387                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3388                                 {
3389                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3390                                 }
3391                                 break;
3392                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3393                                 if (lpa_pause & LPA_PAUSE_CAP)
3394                                 {
3395                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3396                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3397                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3398                                 }
3399                                 if (lpa_pause == LPA_PAUSE_ASYM)
3400                                 {
3401                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3402                                 }
3403                                 break;
3404                         }
3405                 } else {
3406                         pause_flags = np->pause_flags;
3407                 }
3408         }
3409         nv_update_pause(dev, pause_flags);
3410
3411         if (txrxFlags & NV_RESTART_TX)
3412                 nv_start_tx(dev);
3413         if (txrxFlags & NV_RESTART_RX)
3414                 nv_start_rx(dev);
3415
3416         return retval;
3417 }
3418
3419 static void nv_linkchange(struct net_device *dev)
3420 {
3421         if (nv_update_linkspeed(dev)) {
3422                 if (!netif_carrier_ok(dev)) {
3423                         netif_carrier_on(dev);
3424                         printk(KERN_INFO "%s: link up.\n", dev->name);
3425                         nv_txrx_gate(dev, false);
3426                         nv_start_rx(dev);
3427                 }
3428         } else {
3429                 if (netif_carrier_ok(dev)) {
3430                         netif_carrier_off(dev);
3431                         printk(KERN_INFO "%s: link down.\n", dev->name);
3432                         nv_txrx_gate(dev, true);
3433                         nv_stop_rx(dev);
3434                 }
3435         }
3436 }
3437
3438 static void nv_link_irq(struct net_device *dev)
3439 {
3440         u8 __iomem *base = get_hwbase(dev);
3441         u32 miistat;
3442
3443         miistat = readl(base + NvRegMIIStatus);
3444         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3445         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3446
3447         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3448                 nv_linkchange(dev);
3449         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3450 }
3451
3452 static void nv_msi_workaround(struct fe_priv *np)
3453 {
3454
3455         /* Need to toggle the msi irq mask within the ethernet device,
3456          * otherwise, future interrupts will not be detected.
3457          */
3458         if (np->msi_flags & NV_MSI_ENABLED) {
3459                 u8 __iomem *base = np->base;
3460
3461                 writel(0, base + NvRegMSIIrqMask);
3462                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3463         }
3464 }
3465
3466 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3467 {
3468         struct fe_priv *np = netdev_priv(dev);
3469
3470         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3471                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3472                         /* transition to poll based interrupts */
3473                         np->quiet_count = 0;
3474                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3475                                 np->irqmask = NVREG_IRQMASK_CPU;
3476                                 return 1;
3477                         }
3478                 } else {
3479                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3480                                 np->quiet_count++;
3481                         } else {
3482                                 /* reached a period of low activity, switch
3483                                    to per tx/rx packet interrupts */
3484                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3485                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3486                                         return 1;
3487                                 }
3488                         }
3489                 }
3490         }
3491         return 0;
3492 }
3493
3494 static irqreturn_t nv_nic_irq(int foo, void *data)
3495 {
3496         struct net_device *dev = (struct net_device *) data;
3497         struct fe_priv *np = netdev_priv(dev);
3498         u8 __iomem *base = get_hwbase(dev);
3499 #ifndef CONFIG_FORCEDETH_NAPI
3500         int total_work = 0;
3501         int loop_count = 0;
3502 #endif
3503
3504         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3505
3506         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3507                 np->events = readl(base + NvRegIrqStatus);
3508                 writel(np->events, base + NvRegIrqStatus);
3509         } else {
3510                 np->events = readl(base + NvRegMSIXIrqStatus);
3511                 writel(np->events, base + NvRegMSIXIrqStatus);
3512         }
3513         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3514         if (!(np->events & np->irqmask))
3515                 return IRQ_NONE;
3516
3517         nv_msi_workaround(np);
3518
3519 #ifdef CONFIG_FORCEDETH_NAPI
3520         if (napi_schedule_prep(&np->napi)) {
3521                 /*
3522                  * Disable further irq's (msix not enabled with napi)
3523                  */
3524                 writel(0, base + NvRegIrqMask);
3525                 __napi_schedule(&np->napi);
3526         }
3527
3528 #else
3529         do
3530         {
3531                 int work = 0;
3532                 if ((work = nv_rx_process(dev, RX_WORK_PER_LOOP))) {
3533                         if (unlikely(nv_alloc_rx(dev))) {
3534                                 spin_lock(&np->lock);
3535                                 if (!np->in_shutdown)
3536                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3537                                 spin_unlock(&np->lock);
3538                         }
3539                 }
3540
3541                 spin_lock(&np->lock);
3542                 work += nv_tx_done(dev, TX_WORK_PER_LOOP);
3543                 spin_unlock(&np->lock);
3544
3545                 if (!work)
3546                         break;
3547
3548                 total_work += work;
3549
3550                 loop_count++;
3551         }
3552         while (loop_count < max_interrupt_work);
3553
3554         if (nv_change_interrupt_mode(dev, total_work)) {
3555                 /* setup new irq mask */
3556                 writel(np->irqmask, base + NvRegIrqMask);
3557         }
3558
3559         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3560                 spin_lock(&np->lock);
3561                 nv_link_irq(dev);
3562                 spin_unlock(&np->lock);
3563         }
3564         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3565                 spin_lock(&np->lock);
3566                 nv_linkchange(dev);
3567                 spin_unlock(&np->lock);
3568                 np->link_timeout = jiffies + LINK_TIMEOUT;
3569         }
3570         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3571                 spin_lock(&np->lock);
3572                 /* disable interrupts on the nic */
3573                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3574                         writel(0, base + NvRegIrqMask);
3575                 else
3576                         writel(np->irqmask, base + NvRegIrqMask);
3577                 pci_push(base);
3578
3579                 if (!np->in_shutdown) {
3580                         np->nic_poll_irq = np->irqmask;
3581                         np->recover_error = 1;
3582                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3583                 }
3584                 spin_unlock(&np->lock);
3585         }
3586 #endif
3587         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3588
3589         return IRQ_HANDLED;
3590 }
3591
3592 /**
3593  * All _optimized functions are used to help increase performance
3594  * (reduce CPU and increase throughput). They use descripter version 3,
3595  * compiler directives, and reduce memory accesses.
3596  */
3597 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3598 {
3599         struct net_device *dev = (struct net_device *) data;
3600         struct fe_priv *np = netdev_priv(dev);
3601         u8 __iomem *base = get_hwbase(dev);
3602 #ifndef CONFIG_FORCEDETH_NAPI
3603         int total_work = 0;
3604         int loop_count = 0;
3605 #endif
3606
3607         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3608
3609         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3610                 np->events = readl(base + NvRegIrqStatus);
3611                 writel(np->events, base + NvRegIrqStatus);
3612         } else {
3613                 np->events = readl(base + NvRegMSIXIrqStatus);
3614                 writel(np->events, base + NvRegMSIXIrqStatus);
3615         }
3616         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3617         if (!(np->events & np->irqmask))
3618                 return IRQ_NONE;
3619
3620         nv_msi_workaround(np);
3621
3622 #ifdef CONFIG_FORCEDETH_NAPI
3623         if (napi_schedule_prep(&np->napi)) {
3624                 /*
3625                  * Disable further irq's (msix not enabled with napi)
3626                  */
3627                 writel(0, base + NvRegIrqMask);
3628                 __napi_schedule(&np->napi);
3629         }
3630 #else
3631         do
3632         {
3633                 int work = 0;
3634                 if ((work = nv_rx_process_optimized(dev, RX_WORK_PER_LOOP))) {
3635                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3636                                 spin_lock(&np->lock);
3637                                 if (!np->in_shutdown)
3638                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3639                                 spin_unlock(&np->lock);
3640                         }
3641                 }
3642
3643                 spin_lock(&np->lock);
3644                 work += nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3645                 spin_unlock(&np->lock);
3646
3647                 if (!work)
3648                         break;
3649
3650                 total_work += work;
3651
3652                 loop_count++;
3653         }
3654         while (loop_count < max_interrupt_work);
3655
3656         if (nv_change_interrupt_mode(dev, total_work)) {
3657                 /* setup new irq mask */
3658                 writel(np->irqmask, base + NvRegIrqMask);
3659         }
3660
3661         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3662                 spin_lock(&np->lock);
3663                 nv_link_irq(dev);
3664                 spin_unlock(&np->lock);
3665         }
3666         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3667                 spin_lock(&np->lock);
3668                 nv_linkchange(dev);
3669                 spin_unlock(&np->lock);
3670                 np->link_timeout = jiffies + LINK_TIMEOUT;
3671         }
3672         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3673                 spin_lock(&np->lock);
3674                 /* disable interrupts on the nic */
3675                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3676                         writel(0, base + NvRegIrqMask);
3677                 else
3678                         writel(np->irqmask, base + NvRegIrqMask);
3679                 pci_push(base);
3680
3681                 if (!np->in_shutdown) {
3682                         np->nic_poll_irq = np->irqmask;
3683                         np->recover_error = 1;
3684                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3685                 }
3686                 spin_unlock(&np->lock);
3687         }
3688
3689 #endif
3690         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3691
3692         return IRQ_HANDLED;
3693 }
3694
3695 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3696 {
3697         struct net_device *dev = (struct net_device *) data;
3698         struct fe_priv *np = netdev_priv(dev);
3699         u8 __iomem *base = get_hwbase(dev);
3700         u32 events;
3701         int i;
3702         unsigned long flags;
3703
3704         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3705
3706         for (i=0; ; i++) {
3707                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3708                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3709                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3710                 if (!(events & np->irqmask))
3711                         break;
3712
3713                 spin_lock_irqsave(&np->lock, flags);
3714                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3715                 spin_unlock_irqrestore(&np->lock, flags);
3716
3717                 if (unlikely(i > max_interrupt_work)) {
3718                         spin_lock_irqsave(&np->lock, flags);
3719                         /* disable interrupts on the nic */
3720                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3721                         pci_push(base);
3722
3723                         if (!np->in_shutdown) {
3724                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3725                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3726                         }
3727                         spin_unlock_irqrestore(&np->lock, flags);
3728                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3729                         break;
3730                 }
3731
3732         }
3733         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3734
3735         return IRQ_RETVAL(i);
3736 }
3737
3738 #ifdef CONFIG_FORCEDETH_NAPI
3739 static int nv_napi_poll(struct napi_struct *napi, int budget)
3740 {
3741         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3742         struct net_device *dev = np->dev;
3743         u8 __iomem *base = get_hwbase(dev);
3744         unsigned long flags;
3745         int retcode;
3746         int tx_work, rx_work;
3747
3748         if (!nv_optimized(np)) {
3749                 spin_lock_irqsave(&np->lock, flags);
3750                 tx_work = nv_tx_done(dev, np->tx_ring_size);
3751                 spin_unlock_irqrestore(&np->lock, flags);
3752
3753                 rx_work = nv_rx_process(dev, budget);
3754                 retcode = nv_alloc_rx(dev);
3755         } else {
3756                 spin_lock_irqsave(&np->lock, flags);
3757                 tx_work = nv_tx_done_optimized(dev, np->tx_ring_size);
3758                 spin_unlock_irqrestore(&np->lock, flags);
3759
3760                 rx_work = nv_rx_process_optimized(dev, budget);
3761                 retcode = nv_alloc_rx_optimized(dev);
3762         }
3763
3764         if (retcode) {
3765                 spin_lock_irqsave(&np->lock, flags);
3766                 if (!np->in_shutdown)
3767                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3768                 spin_unlock_irqrestore(&np->lock, flags);
3769         }
3770
3771         nv_change_interrupt_mode(dev, tx_work + rx_work);
3772
3773         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3774                 spin_lock_irqsave(&np->lock, flags);
3775                 nv_link_irq(dev);
3776                 spin_unlock_irqrestore(&np->lock, flags);
3777         }
3778         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3779                 spin_lock_irqsave(&np->lock, flags);
3780                 nv_linkchange(dev);
3781                 spin_unlock_irqrestore(&np->lock, flags);
3782                 np->link_timeout = jiffies + LINK_TIMEOUT;
3783         }
3784         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3785                 spin_lock_irqsave(&np->lock, flags);
3786                 if (!np->in_shutdown) {
3787                         np->nic_poll_irq = np->irqmask;
3788                         np->recover_error = 1;
3789                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3790                 }
3791                 spin_unlock_irqrestore(&np->lock, flags);
3792                 napi_complete(napi);
3793                 return rx_work;
3794         }
3795
3796         if (rx_work < budget) {
3797                 /* re-enable interrupts
3798                    (msix not enabled in napi) */
3799                 napi_complete(napi);
3800
3801                 writel(np->irqmask, base + NvRegIrqMask);
3802         }
3803         return rx_work;
3804 }
3805 #endif
3806
3807 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3808 {
3809         struct net_device *dev = (struct net_device *) data;
3810         struct fe_priv *np = netdev_priv(dev);
3811         u8 __iomem *base = get_hwbase(dev);
3812         u32 events;
3813         int i;
3814         unsigned long flags;
3815
3816         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3817
3818         for (i=0; ; i++) {
3819                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3820                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3821                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3822                 if (!(events & np->irqmask))
3823                         break;
3824
3825                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3826                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3827                                 spin_lock_irqsave(&np->lock, flags);
3828                                 if (!np->in_shutdown)
3829                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3830                                 spin_unlock_irqrestore(&np->lock, flags);
3831                         }
3832                 }
3833
3834                 if (unlikely(i > max_interrupt_work)) {
3835                         spin_lock_irqsave(&np->lock, flags);
3836                         /* disable interrupts on the nic */
3837                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3838                         pci_push(base);
3839
3840                         if (!np->in_shutdown) {
3841                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3842                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3843                         }
3844                         spin_unlock_irqrestore(&np->lock, flags);
3845                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3846                         break;
3847                 }
3848         }
3849         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3850
3851         return IRQ_RETVAL(i);
3852 }
3853
3854 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3855 {
3856         struct net_device *dev = (struct net_device *) data;
3857         struct fe_priv *np = netdev_priv(dev);
3858         u8 __iomem *base = get_hwbase(dev);
3859         u32 events;
3860         int i;
3861         unsigned long flags;
3862
3863         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3864
3865         for (i=0; ; i++) {
3866                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3867                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3868                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3869                 if (!(events & np->irqmask))
3870                         break;
3871
3872                 /* check tx in case we reached max loop limit in tx isr */
3873                 spin_lock_irqsave(&np->lock, flags);
3874                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3875                 spin_unlock_irqrestore(&np->lock, flags);
3876
3877                 if (events & NVREG_IRQ_LINK) {
3878                         spin_lock_irqsave(&np->lock, flags);
3879                         nv_link_irq(dev);
3880                         spin_unlock_irqrestore(&np->lock, flags);
3881                 }
3882                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3883                         spin_lock_irqsave(&np->lock, flags);
3884                         nv_linkchange(dev);
3885                         spin_unlock_irqrestore(&np->lock, flags);
3886                         np->link_timeout = jiffies + LINK_TIMEOUT;
3887                 }
3888                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3889                         spin_lock_irq(&np->lock);
3890                         /* disable interrupts on the nic */
3891                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3892                         pci_push(base);
3893
3894                         if (!np->in_shutdown) {
3895                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3896                                 np->recover_error = 1;
3897                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3898                         }
3899                         spin_unlock_irq(&np->lock);
3900                         break;
3901                 }
3902                 if (unlikely(i > max_interrupt_work)) {
3903                         spin_lock_irqsave(&np->lock, flags);
3904                         /* disable interrupts on the nic */
3905                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3906                         pci_push(base);
3907
3908                         if (!np->in_shutdown) {
3909                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3910                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3911                         }
3912                         spin_unlock_irqrestore(&np->lock, flags);
3913                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3914                         break;
3915                 }
3916
3917         }
3918         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3919
3920         return IRQ_RETVAL(i);
3921 }
3922
3923 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3924 {
3925         struct net_device *dev = (struct net_device *) data;
3926         struct fe_priv *np = netdev_priv(dev);
3927         u8 __iomem *base = get_hwbase(dev);
3928         u32 events;
3929
3930         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3931
3932         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3933                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3934                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3935         } else {
3936                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3937                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3938         }
3939         pci_push(base);
3940         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3941         if (!(events & NVREG_IRQ_TIMER))
3942                 return IRQ_RETVAL(0);
3943
3944         nv_msi_workaround(np);
3945
3946         spin_lock(&np->lock);
3947         np->intr_test = 1;
3948         spin_unlock(&np->lock);
3949
3950         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3951
3952         return IRQ_RETVAL(1);
3953 }
3954
3955 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3956 {
3957         u8 __iomem *base = get_hwbase(dev);
3958         int i;
3959         u32 msixmap = 0;
3960
3961         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3962          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3963          * the remaining 8 interrupts.
3964          */
3965         for (i = 0; i < 8; i++) {
3966                 if ((irqmask >> i) & 0x1) {
3967                         msixmap |= vector << (i << 2);
3968                 }
3969         }
3970         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3971
3972         msixmap = 0;
3973         for (i = 0; i < 8; i++) {
3974                 if ((irqmask >> (i + 8)) & 0x1) {
3975                         msixmap |= vector << (i << 2);
3976                 }
3977         }
3978         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3979 }
3980
3981 static int nv_request_irq(struct net_device *dev, int intr_test)
3982 {
3983         struct fe_priv *np = get_nvpriv(dev);
3984         u8 __iomem *base = get_hwbase(dev);
3985         int ret = 1;
3986         int i;
3987         irqreturn_t (*handler)(int foo, void *data);
3988
3989         if (intr_test) {
3990                 handler = nv_nic_irq_test;
3991         } else {
3992                 if (nv_optimized(np))
3993                         handler = nv_nic_irq_optimized;
3994                 else
3995                         handler = nv_nic_irq;
3996         }
3997
3998         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3999                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4000                         np->msi_x_entry[i].entry = i;
4001                 }
4002                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
4003                         np->msi_flags |= NV_MSI_X_ENABLED;
4004                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
4005                                 /* Request irq for rx handling */
4006                                 sprintf(np->name_rx, "%s-rx", dev->name);
4007                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
4008                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
4009                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
4010                                         pci_disable_msix(np->pci_dev);
4011                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4012                                         goto out_err;
4013                                 }
4014                                 /* Request irq for tx handling */
4015                                 sprintf(np->name_tx, "%s-tx", dev->name);
4016                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
4017                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
4018                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
4019                                         pci_disable_msix(np->pci_dev);
4020                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4021                                         goto out_free_rx;
4022                                 }
4023                                 /* Request irq for link and timer handling */
4024                                 sprintf(np->name_other, "%s-other", dev->name);
4025                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4026                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
4027                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
4028                                         pci_disable_msix(np->pci_dev);
4029                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4030                                         goto out_free_tx;
4031                                 }
4032                                 /* map interrupts to their respective vector */
4033                                 writel(0, base + NvRegMSIXMap0);
4034                                 writel(0, base + NvRegMSIXMap1);
4035                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4036                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4037                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4038                         } else {
4039                                 /* Request irq for all interrupts */
4040                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
4041                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4042                                         pci_disable_msix(np->pci_dev);
4043                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4044                                         goto out_err;
4045                                 }
4046
4047                                 /* map interrupts to vector 0 */
4048                                 writel(0, base + NvRegMSIXMap0);
4049                                 writel(0, base + NvRegMSIXMap1);
4050                         }
4051                 }
4052         }
4053         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4054                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
4055                         np->msi_flags |= NV_MSI_ENABLED;
4056                         dev->irq = np->pci_dev->irq;
4057                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4058                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4059                                 pci_disable_msi(np->pci_dev);
4060                                 np->msi_flags &= ~NV_MSI_ENABLED;
4061                                 dev->irq = np->pci_dev->irq;
4062                                 goto out_err;
4063                         }
4064
4065                         /* map interrupts to vector 0 */
4066                         writel(0, base + NvRegMSIMap0);
4067                         writel(0, base + NvRegMSIMap1);
4068                         /* enable msi vector 0 */
4069                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4070                 }
4071         }
4072         if (ret != 0) {
4073                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4074                         goto out_err;
4075
4076         }
4077
4078         return 0;
4079 out_free_tx:
4080         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4081 out_free_rx:
4082         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4083 out_err:
4084         return 1;
4085 }
4086
4087 static void nv_free_irq(struct net_device *dev)
4088 {
4089         struct fe_priv *np = get_nvpriv(dev);
4090         int i;
4091
4092         if (np->msi_flags & NV_MSI_X_ENABLED) {
4093                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4094                         free_irq(np->msi_x_entry[i].vector, dev);
4095                 }
4096                 pci_disable_msix(np->pci_dev);
4097                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4098         } else {
4099                 free_irq(np->pci_dev->irq, dev);
4100                 if (np->msi_flags & NV_MSI_ENABLED) {
4101                         pci_disable_msi(np->pci_dev);
4102                         np->msi_flags &= ~NV_MSI_ENABLED;
4103                 }
4104         }
4105 }
4106
4107 static void nv_do_nic_poll(unsigned long data)
4108 {
4109         struct net_device *dev = (struct net_device *) data;
4110         struct fe_priv *np = netdev_priv(dev);
4111         u8 __iomem *base = get_hwbase(dev);
4112         u32 mask = 0;
4113
4114         /*
4115          * First disable irq(s) and then
4116          * reenable interrupts on the nic, we have to do this before calling
4117          * nv_nic_irq because that may decide to do otherwise
4118          */
4119
4120         if (!using_multi_irqs(dev)) {
4121                 if (np->msi_flags & NV_MSI_X_ENABLED)
4122                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4123                 else
4124                         disable_irq_lockdep(np->pci_dev->irq);
4125                 mask = np->irqmask;
4126         } else {
4127                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4128                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4129                         mask |= NVREG_IRQ_RX_ALL;
4130                 }
4131                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4132                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4133                         mask |= NVREG_IRQ_TX_ALL;
4134                 }
4135                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4136                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4137                         mask |= NVREG_IRQ_OTHER;
4138                 }
4139         }
4140         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4141
4142         if (np->recover_error) {
4143                 np->recover_error = 0;
4144                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4145                 if (netif_running(dev)) {
4146                         netif_tx_lock_bh(dev);
4147                         netif_addr_lock(dev);
4148                         spin_lock(&np->lock);
4149                         /* stop engines */
4150                         nv_stop_rxtx(dev);
4151                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4152                                 nv_mac_reset(dev);
4153                         nv_txrx_reset(dev);
4154                         /* drain rx queue */
4155                         nv_drain_rxtx(dev);
4156                         /* reinit driver view of the rx queue */
4157                         set_bufsize(dev);
4158                         if (nv_init_ring(dev)) {
4159                                 if (!np->in_shutdown)
4160                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4161                         }
4162                         /* reinit nic view of the rx queue */
4163                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4164                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4165                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4166                                 base + NvRegRingSizes);
4167                         pci_push(base);
4168                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4169                         pci_push(base);
4170                         /* clear interrupts */
4171                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4172                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4173                         else
4174                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4175
4176                         /* restart rx engine */
4177                         nv_start_rxtx(dev);
4178                         spin_unlock(&np->lock);
4179                         netif_addr_unlock(dev);
4180                         netif_tx_unlock_bh(dev);
4181                 }
4182         }
4183
4184         writel(mask, base + NvRegIrqMask);
4185         pci_push(base);
4186
4187         if (!using_multi_irqs(dev)) {
4188                 np->nic_poll_irq = 0;
4189                 if (nv_optimized(np))
4190                         nv_nic_irq_optimized(0, dev);
4191                 else
4192                         nv_nic_irq(0, dev);
4193                 if (np->msi_flags & NV_MSI_X_ENABLED)
4194                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4195                 else
4196                         enable_irq_lockdep(np->pci_dev->irq);
4197         } else {
4198                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4199                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4200                         nv_nic_irq_rx(0, dev);
4201                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4202                 }
4203                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4204                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4205                         nv_nic_irq_tx(0, dev);
4206                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4207                 }
4208                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4209                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4210                         nv_nic_irq_other(0, dev);
4211                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4212                 }
4213         }
4214
4215 }
4216
4217 #ifdef CONFIG_NET_POLL_CONTROLLER
4218 static void nv_poll_controller(struct net_device *dev)
4219 {
4220         nv_do_nic_poll((unsigned long) dev);
4221 }
4222 #endif
4223
4224 static void nv_do_stats_poll(unsigned long data)
4225 {
4226         struct net_device *dev = (struct net_device *) data;
4227         struct fe_priv *np = netdev_priv(dev);
4228
4229         nv_get_hw_stats(dev);
4230
4231         if (!np->in_shutdown)
4232                 mod_timer(&np->stats_poll,
4233                         round_jiffies(jiffies + STATS_INTERVAL));
4234 }
4235
4236 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4237 {
4238         struct fe_priv *np = netdev_priv(dev);
4239         strcpy(info->driver, DRV_NAME);
4240         strcpy(info->version, FORCEDETH_VERSION);
4241         strcpy(info->bus_info, pci_name(np->pci_dev));
4242 }
4243
4244 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4245 {
4246         struct fe_priv *np = netdev_priv(dev);
4247         wolinfo->supported = WAKE_MAGIC;
4248
4249         spin_lock_irq(&np->lock);
4250         if (np->wolenabled)
4251                 wolinfo->wolopts = WAKE_MAGIC;
4252         spin_unlock_irq(&np->lock);
4253 }
4254
4255 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4256 {
4257         struct fe_priv *np = netdev_priv(dev);
4258         u8 __iomem *base = get_hwbase(dev);
4259         u32 flags = 0;
4260
4261         if (wolinfo->wolopts == 0) {
4262                 np->wolenabled = 0;
4263         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4264                 np->wolenabled = 1;
4265                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4266         }
4267         if (netif_running(dev)) {
4268                 spin_lock_irq(&np->lock);
4269                 writel(flags, base + NvRegWakeUpFlags);
4270                 spin_unlock_irq(&np->lock);
4271         }
4272         return 0;
4273 }
4274
4275 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4276 {
4277         struct fe_priv *np = netdev_priv(dev);
4278         int adv;
4279
4280         spin_lock_irq(&np->lock);
4281         ecmd->port = PORT_MII;
4282         if (!netif_running(dev)) {
4283                 /* We do not track link speed / duplex setting if the
4284                  * interface is disabled. Force a link check */
4285                 if (nv_update_linkspeed(dev)) {
4286                         if (!netif_carrier_ok(dev))
4287                                 netif_carrier_on(dev);
4288                 } else {
4289                         if (netif_carrier_ok(dev))
4290                                 netif_carrier_off(dev);
4291                 }
4292         }
4293
4294         if (netif_carrier_ok(dev)) {
4295                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4296                 case NVREG_LINKSPEED_10:
4297                         ecmd->speed = SPEED_10;
4298                         break;
4299                 case NVREG_LINKSPEED_100:
4300                         ecmd->speed = SPEED_100;
4301                         break;
4302                 case NVREG_LINKSPEED_1000:
4303                         ecmd->speed = SPEED_1000;
4304                         break;
4305                 }
4306                 ecmd->duplex = DUPLEX_HALF;
4307                 if (np->duplex)
4308                         ecmd->duplex = DUPLEX_FULL;
4309         } else {
4310                 ecmd->speed = -1;
4311                 ecmd->duplex = -1;
4312         }
4313
4314         ecmd->autoneg = np->autoneg;
4315
4316         ecmd->advertising = ADVERTISED_MII;
4317         if (np->autoneg) {
4318                 ecmd->advertising |= ADVERTISED_Autoneg;
4319                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4320                 if (adv & ADVERTISE_10HALF)
4321                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4322                 if (adv & ADVERTISE_10FULL)
4323                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4324                 if (adv & ADVERTISE_100HALF)
4325                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4326                 if (adv & ADVERTISE_100FULL)
4327                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4328                 if (np->gigabit == PHY_GIGABIT) {
4329                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4330                         if (adv & ADVERTISE_1000FULL)
4331                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4332                 }
4333         }
4334         ecmd->supported = (SUPPORTED_Autoneg |
4335                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4336                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4337                 SUPPORTED_MII);
4338         if (np->gigabit == PHY_GIGABIT)
4339                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4340
4341         ecmd->phy_address = np->phyaddr;
4342         ecmd->transceiver = XCVR_EXTERNAL;
4343
4344         /* ignore maxtxpkt, maxrxpkt for now */
4345         spin_unlock_irq(&np->lock);
4346         return 0;
4347 }
4348
4349 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4350 {
4351         struct fe_priv *np = netdev_priv(dev);
4352
4353         if (ecmd->port != PORT_MII)
4354                 return -EINVAL;
4355         if (ecmd->transceiver != XCVR_EXTERNAL)
4356                 return -EINVAL;
4357         if (ecmd->phy_address != np->phyaddr) {
4358                 /* TODO: support switching between multiple phys. Should be
4359                  * trivial, but not enabled due to lack of test hardware. */
4360                 return -EINVAL;
4361         }
4362         if (ecmd->autoneg == AUTONEG_ENABLE) {
4363                 u32 mask;
4364
4365                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4366                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4367                 if (np->gigabit == PHY_GIGABIT)
4368                         mask |= ADVERTISED_1000baseT_Full;
4369
4370                 if ((ecmd->advertising & mask) == 0)
4371                         return -EINVAL;
4372
4373         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4374                 /* Note: autonegotiation disable, speed 1000 intentionally
4375                  * forbidden - noone should need that. */
4376
4377                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4378                         return -EINVAL;
4379                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4380                         return -EINVAL;
4381         } else {
4382                 return -EINVAL;
4383         }
4384
4385         netif_carrier_off(dev);
4386         if (netif_running(dev)) {
4387                 unsigned long flags;
4388
4389                 nv_disable_irq(dev);
4390                 netif_tx_lock_bh(dev);
4391                 netif_addr_lock(dev);
4392                 /* with plain spinlock lockdep complains */
4393                 spin_lock_irqsave(&np->lock, flags);
4394                 /* stop engines */
4395                 /* FIXME:
4396                  * this can take some time, and interrupts are disabled
4397                  * due to spin_lock_irqsave, but let's hope no daemon
4398                  * is going to change the settings very often...
4399                  * Worst case:
4400                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4401                  * + some minor delays, which is up to a second approximately
4402                  */
4403                 nv_stop_rxtx(dev);
4404                 spin_unlock_irqrestore(&np->lock, flags);
4405                 netif_addr_unlock(dev);
4406                 netif_tx_unlock_bh(dev);
4407         }
4408
4409         if (ecmd->autoneg == AUTONEG_ENABLE) {
4410                 int adv, bmcr;
4411
4412                 np->autoneg = 1;
4413
4414                 /* advertise only what has been requested */
4415                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4416                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4417                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4418                         adv |= ADVERTISE_10HALF;
4419                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4420                         adv |= ADVERTISE_10FULL;
4421                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4422                         adv |= ADVERTISE_100HALF;
4423                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4424                         adv |= ADVERTISE_100FULL;
4425                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4426                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4427                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4428                         adv |=  ADVERTISE_PAUSE_ASYM;
4429                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4430
4431                 if (np->gigabit == PHY_GIGABIT) {
4432                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4433                         adv &= ~ADVERTISE_1000FULL;
4434                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4435                                 adv |= ADVERTISE_1000FULL;
4436                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4437                 }
4438
4439                 if (netif_running(dev))
4440                         printk(KERN_INFO "%s: link down.\n", dev->name);
4441                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4442                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4443                         bmcr |= BMCR_ANENABLE;
4444                         /* reset the phy in order for settings to stick,
4445                          * and cause autoneg to start */
4446                         if (phy_reset(dev, bmcr)) {
4447                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4448                                 return -EINVAL;
4449                         }
4450                 } else {
4451                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4452                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4453                 }
4454         } else {
4455                 int adv, bmcr;
4456
4457                 np->autoneg = 0;
4458
4459                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4460                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4461                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4462                         adv |= ADVERTISE_10HALF;
4463                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4464                         adv |= ADVERTISE_10FULL;
4465                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4466                         adv |= ADVERTISE_100HALF;
4467                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4468                         adv |= ADVERTISE_100FULL;
4469                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4470                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4471                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4472                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4473                 }
4474                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4475                         adv |=  ADVERTISE_PAUSE_ASYM;
4476                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4477                 }
4478                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4479                 np->fixed_mode = adv;
4480
4481                 if (np->gigabit == PHY_GIGABIT) {
4482                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4483                         adv &= ~ADVERTISE_1000FULL;
4484                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4485                 }
4486
4487                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4488                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4489                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4490                         bmcr |= BMCR_FULLDPLX;
4491                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4492                         bmcr |= BMCR_SPEED100;
4493                 if (np->phy_oui == PHY_OUI_MARVELL) {
4494                         /* reset the phy in order for forced mode settings to stick */
4495                         if (phy_reset(dev, bmcr)) {
4496                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4497                                 return -EINVAL;
4498                         }
4499                 } else {
4500                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4501                         if (netif_running(dev)) {
4502                                 /* Wait a bit and then reconfigure the nic. */
4503                                 udelay(10);
4504                                 nv_linkchange(dev);
4505                         }
4506                 }
4507         }
4508
4509         if (netif_running(dev)) {
4510                 nv_start_rxtx(dev);
4511                 nv_enable_irq(dev);
4512         }
4513
4514         return 0;
4515 }
4516
4517 #define FORCEDETH_REGS_VER      1
4518
4519 static int nv_get_regs_len(struct net_device *dev)
4520 {
4521         struct fe_priv *np = netdev_priv(dev);
4522         return np->register_size;
4523 }
4524
4525 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4526 {
4527         struct fe_priv *np = netdev_priv(dev);
4528         u8 __iomem *base = get_hwbase(dev);
4529         u32 *rbuf = buf;
4530         int i;
4531
4532         regs->version = FORCEDETH_REGS_VER;
4533         spin_lock_irq(&np->lock);
4534         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4535                 rbuf[i] = readl(base + i*sizeof(u32));
4536         spin_unlock_irq(&np->lock);
4537 }
4538
4539 static int nv_nway_reset(struct net_device *dev)
4540 {
4541         struct fe_priv *np = netdev_priv(dev);
4542         int ret;
4543
4544         if (np->autoneg) {
4545                 int bmcr;
4546
4547                 netif_carrier_off(dev);
4548                 if (netif_running(dev)) {
4549                         nv_disable_irq(dev);
4550                         netif_tx_lock_bh(dev);
4551                         netif_addr_lock(dev);
4552                         spin_lock(&np->lock);
4553                         /* stop engines */
4554                         nv_stop_rxtx(dev);
4555                         spin_unlock(&np->lock);
4556                         netif_addr_unlock(dev);
4557                         netif_tx_unlock_bh(dev);
4558                         printk(KERN_INFO "%s: link down.\n", dev->name);
4559                 }
4560
4561                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4562                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4563                         bmcr |= BMCR_ANENABLE;
4564                         /* reset the phy in order for settings to stick*/
4565                         if (phy_reset(dev, bmcr)) {
4566                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4567                                 return -EINVAL;
4568                         }
4569                 } else {
4570                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4571                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4572                 }
4573
4574                 if (netif_running(dev)) {
4575                         nv_start_rxtx(dev);
4576                         nv_enable_irq(dev);
4577                 }
4578                 ret = 0;
4579         } else {
4580                 ret = -EINVAL;
4581         }
4582
4583         return ret;
4584 }
4585
4586 static int nv_set_tso(struct net_device *dev, u32 value)
4587 {
4588         struct fe_priv *np = netdev_priv(dev);
4589
4590         if ((np->driver_data & DEV_HAS_CHECKSUM))
4591                 return ethtool_op_set_tso(dev, value);
4592         else
4593                 return -EOPNOTSUPP;
4594 }
4595
4596 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4597 {
4598         struct fe_priv *np = netdev_priv(dev);
4599
4600         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4601         ring->rx_mini_max_pending = 0;
4602         ring->rx_jumbo_max_pending = 0;
4603         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4604
4605         ring->rx_pending = np->rx_ring_size;
4606         ring->rx_mini_pending = 0;
4607         ring->rx_jumbo_pending = 0;
4608         ring->tx_pending = np->tx_ring_size;
4609 }
4610
4611 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4612 {
4613         struct fe_priv *np = netdev_priv(dev);
4614         u8 __iomem *base = get_hwbase(dev);
4615         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4616         dma_addr_t ring_addr;
4617
4618         if (ring->rx_pending < RX_RING_MIN ||
4619             ring->tx_pending < TX_RING_MIN ||
4620             ring->rx_mini_pending != 0 ||
4621             ring->rx_jumbo_pending != 0 ||
4622             (np->desc_ver == DESC_VER_1 &&
4623              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4624               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4625             (np->desc_ver != DESC_VER_1 &&
4626              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4627               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4628                 return -EINVAL;
4629         }
4630
4631         /* allocate new rings */
4632         if (!nv_optimized(np)) {
4633                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4634                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4635                                             &ring_addr);
4636         } else {
4637                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4638                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4639                                             &ring_addr);
4640         }
4641         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4642         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4643         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4644                 /* fall back to old rings */
4645                 if (!nv_optimized(np)) {
4646                         if (rxtx_ring)
4647                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4648                                                     rxtx_ring, ring_addr);
4649                 } else {
4650                         if (rxtx_ring)
4651                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4652                                                     rxtx_ring, ring_addr);
4653                 }
4654                 if (rx_skbuff)
4655                         kfree(rx_skbuff);
4656                 if (tx_skbuff)
4657                         kfree(tx_skbuff);
4658                 goto exit;
4659         }
4660
4661         if (netif_running(dev)) {
4662                 nv_disable_irq(dev);
4663                 nv_napi_disable(dev);
4664                 netif_tx_lock_bh(dev);
4665                 netif_addr_lock(dev);
4666                 spin_lock(&np->lock);
4667                 /* stop engines */
4668                 nv_stop_rxtx(dev);
4669                 nv_txrx_reset(dev);
4670                 /* drain queues */
4671                 nv_drain_rxtx(dev);
4672                 /* delete queues */
4673                 free_rings(dev);
4674         }
4675
4676         /* set new values */
4677         np->rx_ring_size = ring->rx_pending;
4678         np->tx_ring_size = ring->tx_pending;
4679
4680         if (!nv_optimized(np)) {
4681                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4682                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4683         } else {
4684                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4685                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4686         }
4687         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4688         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4689         np->ring_addr = ring_addr;
4690
4691         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4692         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4693
4694         if (netif_running(dev)) {
4695                 /* reinit driver view of the queues */
4696                 set_bufsize(dev);
4697                 if (nv_init_ring(dev)) {
4698                         if (!np->in_shutdown)
4699                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4700                 }
4701
4702                 /* reinit nic view of the queues */
4703                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4704                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4705                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4706                         base + NvRegRingSizes);
4707                 pci_push(base);
4708                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4709                 pci_push(base);
4710
4711                 /* restart engines */
4712                 nv_start_rxtx(dev);
4713                 spin_unlock(&np->lock);
4714                 netif_addr_unlock(dev);
4715                 netif_tx_unlock_bh(dev);
4716                 nv_napi_enable(dev);
4717                 nv_enable_irq(dev);
4718         }
4719         return 0;
4720 exit:
4721         return -ENOMEM;
4722 }
4723
4724 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4725 {
4726         struct fe_priv *np = netdev_priv(dev);
4727
4728         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4729         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4730         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4731 }
4732
4733 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4734 {
4735         struct fe_priv *np = netdev_priv(dev);
4736         int adv, bmcr;
4737
4738         if ((!np->autoneg && np->duplex == 0) ||
4739             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4740                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4741                        dev->name);
4742                 return -EINVAL;
4743         }
4744         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4745                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4746                 return -EINVAL;
4747         }
4748
4749         netif_carrier_off(dev);
4750         if (netif_running(dev)) {
4751                 nv_disable_irq(dev);
4752                 netif_tx_lock_bh(dev);
4753                 netif_addr_lock(dev);
4754                 spin_lock(&np->lock);
4755                 /* stop engines */
4756                 nv_stop_rxtx(dev);
4757                 spin_unlock(&np->lock);
4758                 netif_addr_unlock(dev);
4759                 netif_tx_unlock_bh(dev);
4760         }
4761
4762         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4763         if (pause->rx_pause)
4764                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4765         if (pause->tx_pause)
4766                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4767
4768         if (np->autoneg && pause->autoneg) {
4769                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4770
4771                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4772                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4773                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4774                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4775                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4776                         adv |=  ADVERTISE_PAUSE_ASYM;
4777                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4778
4779                 if (netif_running(dev))
4780                         printk(KERN_INFO "%s: link down.\n", dev->name);
4781                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4782                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4783                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4784         } else {
4785                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4786                 if (pause->rx_pause)
4787                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4788                 if (pause->tx_pause)
4789                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4790
4791                 if (!netif_running(dev))
4792                         nv_update_linkspeed(dev);
4793                 else
4794                         nv_update_pause(dev, np->pause_flags);
4795         }
4796
4797         if (netif_running(dev)) {
4798                 nv_start_rxtx(dev);
4799                 nv_enable_irq(dev);
4800         }
4801         return 0;
4802 }
4803
4804 static u32 nv_get_rx_csum(struct net_device *dev)
4805 {
4806         struct fe_priv *np = netdev_priv(dev);
4807         return (np->rx_csum) != 0;
4808 }
4809
4810 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4811 {
4812         struct fe_priv *np = netdev_priv(dev);
4813         u8 __iomem *base = get_hwbase(dev);
4814         int retcode = 0;
4815
4816         if (np->driver_data & DEV_HAS_CHECKSUM) {
4817                 if (data) {
4818                         np->rx_csum = 1;
4819                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4820                 } else {
4821                         np->rx_csum = 0;
4822                         /* vlan is dependent on rx checksum offload */
4823                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4824                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4825                 }
4826                 if (netif_running(dev)) {
4827                         spin_lock_irq(&np->lock);
4828                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4829                         spin_unlock_irq(&np->lock);
4830                 }
4831         } else {
4832                 return -EINVAL;
4833         }
4834
4835         return retcode;
4836 }
4837
4838 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4839 {
4840         struct fe_priv *np = netdev_priv(dev);
4841
4842         if (np->driver_data & DEV_HAS_CHECKSUM)
4843                 return ethtool_op_set_tx_csum(dev, data);
4844         else
4845                 return -EOPNOTSUPP;
4846 }
4847
4848 static int nv_set_sg(struct net_device *dev, u32 data)
4849 {
4850         struct fe_priv *np = netdev_priv(dev);
4851
4852         if (np->driver_data & DEV_HAS_CHECKSUM)
4853                 return ethtool_op_set_sg(dev, data);
4854         else
4855                 return -EOPNOTSUPP;
4856 }
4857
4858 static int nv_get_sset_count(struct net_device *dev, int sset)
4859 {
4860         struct fe_priv *np = netdev_priv(dev);
4861
4862         switch (sset) {
4863         case ETH_SS_TEST:
4864                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4865                         return NV_TEST_COUNT_EXTENDED;
4866                 else
4867                         return NV_TEST_COUNT_BASE;
4868         case ETH_SS_STATS:
4869                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4870                         return NV_DEV_STATISTICS_V3_COUNT;
4871                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4872                         return NV_DEV_STATISTICS_V2_COUNT;
4873                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4874                         return NV_DEV_STATISTICS_V1_COUNT;
4875                 else
4876                         return 0;
4877         default:
4878                 return -EOPNOTSUPP;
4879         }
4880 }
4881
4882 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4883 {
4884         struct fe_priv *np = netdev_priv(dev);
4885
4886         /* update stats */
4887         nv_do_stats_poll((unsigned long)dev);
4888
4889         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4890 }
4891
4892 static int nv_link_test(struct net_device *dev)
4893 {
4894         struct fe_priv *np = netdev_priv(dev);
4895         int mii_status;
4896
4897         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4898         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4899
4900         /* check phy link status */
4901         if (!(mii_status & BMSR_LSTATUS))
4902                 return 0;
4903         else
4904                 return 1;
4905 }
4906
4907 static int nv_register_test(struct net_device *dev)
4908 {
4909         u8 __iomem *base = get_hwbase(dev);
4910         int i = 0;
4911         u32 orig_read, new_read;
4912
4913         do {
4914                 orig_read = readl(base + nv_registers_test[i].reg);
4915
4916                 /* xor with mask to toggle bits */
4917                 orig_read ^= nv_registers_test[i].mask;
4918
4919                 writel(orig_read, base + nv_registers_test[i].reg);
4920
4921                 new_read = readl(base + nv_registers_test[i].reg);
4922
4923                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4924                         return 0;
4925
4926                 /* restore original value */
4927                 orig_read ^= nv_registers_test[i].mask;
4928                 writel(orig_read, base + nv_registers_test[i].reg);
4929
4930         } while (nv_registers_test[++i].reg != 0);
4931
4932         return 1;
4933 }
4934
4935 static int nv_interrupt_test(struct net_device *dev)
4936 {
4937         struct fe_priv *np = netdev_priv(dev);
4938         u8 __iomem *base = get_hwbase(dev);
4939         int ret = 1;
4940         int testcnt;
4941         u32 save_msi_flags, save_poll_interval = 0;
4942
4943         if (netif_running(dev)) {
4944                 /* free current irq */
4945                 nv_free_irq(dev);
4946                 save_poll_interval = readl(base+NvRegPollingInterval);
4947         }
4948
4949         /* flag to test interrupt handler */
4950         np->intr_test = 0;
4951
4952         /* setup test irq */
4953         save_msi_flags = np->msi_flags;
4954         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4955         np->msi_flags |= 0x001; /* setup 1 vector */
4956         if (nv_request_irq(dev, 1))
4957                 return 0;
4958
4959         /* setup timer interrupt */
4960         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4961         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4962
4963         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4964
4965         /* wait for at least one interrupt */
4966         msleep(100);
4967
4968         spin_lock_irq(&np->lock);
4969
4970         /* flag should be set within ISR */
4971         testcnt = np->intr_test;
4972         if (!testcnt)
4973                 ret = 2;
4974
4975         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4976         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4977                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4978         else
4979                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4980
4981         spin_unlock_irq(&np->lock);
4982
4983         nv_free_irq(dev);
4984
4985         np->msi_flags = save_msi_flags;
4986
4987         if (netif_running(dev)) {
4988                 writel(save_poll_interval, base + NvRegPollingInterval);
4989                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4990                 /* restore original irq */
4991                 if (nv_request_irq(dev, 0))
4992                         return 0;
4993         }
4994
4995         return ret;
4996 }
4997
4998 static int nv_loopback_test(struct net_device *dev)
4999 {
5000         struct fe_priv *np = netdev_priv(dev);
5001         u8 __iomem *base = get_hwbase(dev);
5002         struct sk_buff *tx_skb, *rx_skb;
5003         dma_addr_t test_dma_addr;
5004         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
5005         u32 flags;
5006         int len, i, pkt_len;
5007         u8 *pkt_data;
5008         u32 filter_flags = 0;
5009         u32 misc1_flags = 0;
5010         int ret = 1;
5011
5012         if (netif_running(dev)) {
5013                 nv_disable_irq(dev);
5014                 filter_flags = readl(base + NvRegPacketFilterFlags);
5015                 misc1_flags = readl(base + NvRegMisc1);
5016         } else {
5017                 nv_txrx_reset(dev);
5018         }
5019
5020         /* reinit driver view of the rx queue */
5021         set_bufsize(dev);
5022         nv_init_ring(dev);
5023
5024         /* setup hardware for loopback */
5025         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5026         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5027
5028         /* reinit nic view of the rx queue */
5029         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5030         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5031         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5032                 base + NvRegRingSizes);
5033         pci_push(base);
5034
5035         /* restart rx engine */
5036         nv_start_rxtx(dev);
5037
5038         /* setup packet for tx */
5039         pkt_len = ETH_DATA_LEN;
5040         tx_skb = dev_alloc_skb(pkt_len);
5041         if (!tx_skb) {
5042                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
5043                          " of %s\n", dev->name);
5044                 ret = 0;
5045                 goto out;
5046         }
5047         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5048                                        skb_tailroom(tx_skb),
5049                                        PCI_DMA_FROMDEVICE);
5050         pkt_data = skb_put(tx_skb, pkt_len);
5051         for (i = 0; i < pkt_len; i++)
5052                 pkt_data[i] = (u8)(i & 0xff);
5053
5054         if (!nv_optimized(np)) {
5055                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5056                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5057         } else {
5058                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5059                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5060                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5061         }
5062         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5063         pci_push(get_hwbase(dev));
5064
5065         msleep(500);
5066
5067         /* check for rx of the packet */
5068         if (!nv_optimized(np)) {
5069                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5070                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5071
5072         } else {
5073                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5074                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5075         }
5076
5077         if (flags & NV_RX_AVAIL) {
5078                 ret = 0;
5079         } else if (np->desc_ver == DESC_VER_1) {
5080                 if (flags & NV_RX_ERROR)
5081                         ret = 0;
5082         } else {
5083                 if (flags & NV_RX2_ERROR) {
5084                         ret = 0;
5085                 }
5086         }
5087
5088         if (ret) {
5089                 if (len != pkt_len) {
5090                         ret = 0;
5091                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5092                                 dev->name, len, pkt_len);
5093                 } else {
5094                         rx_skb = np->rx_skb[0].skb;
5095                         for (i = 0; i < pkt_len; i++) {
5096                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5097                                         ret = 0;
5098                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5099                                                 dev->name, i);
5100                                         break;
5101                                 }
5102                         }
5103                 }
5104         } else {
5105                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5106         }
5107
5108         pci_unmap_single(np->pci_dev, test_dma_addr,
5109                        (skb_end_pointer(tx_skb) - tx_skb->data),
5110                        PCI_DMA_TODEVICE);
5111         dev_kfree_skb_any(tx_skb);
5112  out:
5113         /* stop engines */
5114         nv_stop_rxtx(dev);
5115         nv_txrx_reset(dev);
5116         /* drain rx queue */
5117         nv_drain_rxtx(dev);
5118
5119         if (netif_running(dev)) {
5120                 writel(misc1_flags, base + NvRegMisc1);
5121                 writel(filter_flags, base + NvRegPacketFilterFlags);
5122                 nv_enable_irq(dev);
5123         }
5124
5125         return ret;
5126 }
5127
5128 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5129 {
5130         struct fe_priv *np = netdev_priv(dev);
5131         u8 __iomem *base = get_hwbase(dev);
5132         int result;
5133         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5134
5135         if (!nv_link_test(dev)) {
5136                 test->flags |= ETH_TEST_FL_FAILED;
5137                 buffer[0] = 1;
5138         }
5139
5140         if (test->flags & ETH_TEST_FL_OFFLINE) {
5141                 if (netif_running(dev)) {
5142                         netif_stop_queue(dev);
5143                         nv_napi_disable(dev);
5144                         netif_tx_lock_bh(dev);
5145                         netif_addr_lock(dev);
5146                         spin_lock_irq(&np->lock);
5147                         nv_disable_hw_interrupts(dev, np->irqmask);
5148                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5149                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5150                         } else {
5151                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5152                         }
5153                         /* stop engines */
5154                         nv_stop_rxtx(dev);
5155                         nv_txrx_reset(dev);
5156                         /* drain rx queue */
5157                         nv_drain_rxtx(dev);
5158                         spin_unlock_irq(&np->lock);
5159                         netif_addr_unlock(dev);
5160                         netif_tx_unlock_bh(dev);
5161                 }
5162
5163                 if (!nv_register_test(dev)) {
5164                         test->flags |= ETH_TEST_FL_FAILED;
5165                         buffer[1] = 1;
5166                 }
5167
5168                 result = nv_interrupt_test(dev);
5169                 if (result != 1) {
5170                         test->flags |= ETH_TEST_FL_FAILED;
5171                         buffer[2] = 1;
5172                 }
5173                 if (result == 0) {
5174                         /* bail out */
5175                         return;
5176                 }
5177
5178                 if (!nv_loopback_test(dev)) {
5179                         test->flags |= ETH_TEST_FL_FAILED;
5180                         buffer[3] = 1;
5181                 }
5182
5183                 if (netif_running(dev)) {
5184                         /* reinit driver view of the rx queue */
5185                         set_bufsize(dev);
5186                         if (nv_init_ring(dev)) {
5187                                 if (!np->in_shutdown)
5188                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5189                         }
5190                         /* reinit nic view of the rx queue */
5191                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5192                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5193                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5194                                 base + NvRegRingSizes);
5195                         pci_push(base);
5196                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5197                         pci_push(base);
5198                         /* restart rx engine */
5199                         nv_start_rxtx(dev);
5200                         netif_start_queue(dev);
5201                         nv_napi_enable(dev);
5202                         nv_enable_hw_interrupts(dev, np->irqmask);
5203                 }
5204         }
5205 }
5206
5207 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5208 {
5209         switch (stringset) {
5210         case ETH_SS_STATS:
5211                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5212                 break;
5213         case ETH_SS_TEST:
5214                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5215                 break;
5216         }
5217 }
5218
5219 static const struct ethtool_ops ops = {
5220         .get_drvinfo = nv_get_drvinfo,
5221         .get_link = ethtool_op_get_link,
5222         .get_wol = nv_get_wol,
5223         .set_wol = nv_set_wol,
5224         .get_settings = nv_get_settings,
5225         .set_settings = nv_set_settings,
5226         .get_regs_len = nv_get_regs_len,
5227         .get_regs = nv_get_regs,
5228         .nway_reset = nv_nway_reset,
5229         .set_tso = nv_set_tso,
5230         .get_ringparam = nv_get_ringparam,
5231         .set_ringparam = nv_set_ringparam,
5232         .get_pauseparam = nv_get_pauseparam,
5233         .set_pauseparam = nv_set_pauseparam,
5234         .get_rx_csum = nv_get_rx_csum,
5235         .set_rx_csum = nv_set_rx_csum,
5236         .set_tx_csum = nv_set_tx_csum,
5237         .set_sg = nv_set_sg,
5238         .get_strings = nv_get_strings,
5239         .get_ethtool_stats = nv_get_ethtool_stats,
5240         .get_sset_count = nv_get_sset_count,
5241         .self_test = nv_self_test,
5242 };
5243
5244 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5245 {
5246         struct fe_priv *np = get_nvpriv(dev);
5247
5248         spin_lock_irq(&np->lock);
5249
5250         /* save vlan group */
5251         np->vlangrp = grp;
5252
5253         if (grp) {
5254                 /* enable vlan on MAC */
5255                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5256         } else {
5257                 /* disable vlan on MAC */
5258                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5259                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5260         }
5261
5262         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5263
5264         spin_unlock_irq(&np->lock);
5265 }
5266
5267 /* The mgmt unit and driver use a semaphore to access the phy during init */
5268 static int nv_mgmt_acquire_sema(struct net_device *dev)
5269 {
5270         struct fe_priv *np = netdev_priv(dev);
5271         u8 __iomem *base = get_hwbase(dev);
5272         int i;
5273         u32 tx_ctrl, mgmt_sema;
5274
5275         for (i = 0; i < 10; i++) {
5276                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5277                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5278                         break;
5279                 msleep(500);
5280         }
5281
5282         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5283                 return 0;
5284
5285         for (i = 0; i < 2; i++) {
5286                 tx_ctrl = readl(base + NvRegTransmitterControl);
5287                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5288                 writel(tx_ctrl, base + NvRegTransmitterControl);
5289
5290                 /* verify that semaphore was acquired */
5291                 tx_ctrl = readl(base + NvRegTransmitterControl);
5292                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5293                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5294                         np->mgmt_sema = 1;
5295                         return 1;
5296                 }
5297                 else
5298                         udelay(50);
5299         }
5300
5301         return 0;
5302 }
5303
5304 static void nv_mgmt_release_sema(struct net_device *dev)
5305 {
5306         struct fe_priv *np = netdev_priv(dev);
5307         u8 __iomem *base = get_hwbase(dev);
5308         u32 tx_ctrl;
5309
5310         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5311                 if (np->mgmt_sema) {
5312                         tx_ctrl = readl(base + NvRegTransmitterControl);
5313                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5314                         writel(tx_ctrl, base + NvRegTransmitterControl);
5315                 }
5316         }
5317 }
5318
5319
5320 static int nv_mgmt_get_version(struct net_device *dev)
5321 {
5322         struct fe_priv *np = netdev_priv(dev);
5323         u8 __iomem *base = get_hwbase(dev);
5324         u32 data_ready = readl(base + NvRegTransmitterControl);
5325         u32 data_ready2 = 0;
5326         unsigned long start;
5327         int ready = 0;
5328
5329         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5330         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5331         start = jiffies;
5332         while (time_before(jiffies, start + 5*HZ)) {
5333                 data_ready2 = readl(base + NvRegTransmitterControl);
5334                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5335                         ready = 1;
5336                         break;
5337                 }
5338                 schedule_timeout_uninterruptible(1);
5339         }
5340
5341         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5342                 return 0;
5343
5344         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5345
5346         return 1;
5347 }
5348
5349 static int nv_open(struct net_device *dev)
5350 {
5351         struct fe_priv *np = netdev_priv(dev);
5352         u8 __iomem *base = get_hwbase(dev);
5353         int ret = 1;
5354         int oom, i;
5355         u32 low;
5356
5357         dprintk(KERN_DEBUG "nv_open: begin\n");
5358
5359         /* power up phy */
5360         mii_rw(dev, np->phyaddr, MII_BMCR,
5361                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5362
5363         nv_txrx_gate(dev, false);
5364         /* erase previous misconfiguration */
5365         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5366                 nv_mac_reset(dev);
5367         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5368         writel(0, base + NvRegMulticastAddrB);
5369         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5370         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5371         writel(0, base + NvRegPacketFilterFlags);
5372
5373         writel(0, base + NvRegTransmitterControl);
5374         writel(0, base + NvRegReceiverControl);
5375
5376         writel(0, base + NvRegAdapterControl);
5377
5378         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5379                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5380
5381         /* initialize descriptor rings */
5382         set_bufsize(dev);
5383         oom = nv_init_ring(dev);
5384
5385         writel(0, base + NvRegLinkSpeed);
5386         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5387         nv_txrx_reset(dev);
5388         writel(0, base + NvRegUnknownSetupReg6);
5389
5390         np->in_shutdown = 0;
5391
5392         /* give hw rings */
5393         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5394         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5395                 base + NvRegRingSizes);
5396
5397         writel(np->linkspeed, base + NvRegLinkSpeed);
5398         if (np->desc_ver == DESC_VER_1)
5399                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5400         else
5401                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5402         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5403         writel(np->vlanctl_bits, base + NvRegVlanControl);
5404         pci_push(base);
5405         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5406         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5407                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5408                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5409
5410         writel(0, base + NvRegMIIMask);
5411         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5412         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5413
5414         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5415         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5416         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5417         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5418
5419         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5420
5421         get_random_bytes(&low, sizeof(low));
5422         low &= NVREG_SLOTTIME_MASK;
5423         if (np->desc_ver == DESC_VER_1) {
5424                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5425         } else {
5426                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5427                         /* setup legacy backoff */
5428                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5429                 } else {
5430                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5431                         nv_gear_backoff_reseed(dev);
5432                 }
5433         }
5434         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5435         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5436         if (poll_interval == -1) {
5437                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5438                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5439                 else
5440                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5441         }
5442         else
5443                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5444         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5445         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5446                         base + NvRegAdapterControl);
5447         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5448         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5449         if (np->wolenabled)
5450                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5451
5452         i = readl(base + NvRegPowerState);
5453         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5454                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5455
5456         pci_push(base);
5457         udelay(10);
5458         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5459
5460         nv_disable_hw_interrupts(dev, np->irqmask);
5461         pci_push(base);
5462         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5463         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5464         pci_push(base);
5465
5466         if (nv_request_irq(dev, 0)) {
5467                 goto out_drain;
5468         }
5469
5470         /* ask for interrupts */
5471         nv_enable_hw_interrupts(dev, np->irqmask);
5472
5473         spin_lock_irq(&np->lock);
5474         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5475         writel(0, base + NvRegMulticastAddrB);
5476         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5477         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5478         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5479         /* One manual link speed update: Interrupts are enabled, future link
5480          * speed changes cause interrupts and are handled by nv_link_irq().
5481          */
5482         {
5483                 u32 miistat;
5484                 miistat = readl(base + NvRegMIIStatus);
5485                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5486                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5487         }
5488         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5489          * to init hw */
5490         np->linkspeed = 0;
5491         ret = nv_update_linkspeed(dev);
5492         nv_start_rxtx(dev);
5493         netif_start_queue(dev);
5494         nv_napi_enable(dev);
5495
5496         if (ret) {
5497                 netif_carrier_on(dev);
5498         } else {
5499                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5500                 netif_carrier_off(dev);
5501         }
5502         if (oom)
5503                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5504
5505         /* start statistics timer */
5506         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5507                 mod_timer(&np->stats_poll,
5508                         round_jiffies(jiffies + STATS_INTERVAL));
5509
5510         spin_unlock_irq(&np->lock);
5511
5512         return 0;
5513 out_drain:
5514         nv_drain_rxtx(dev);
5515         return ret;
5516 }
5517
5518 static int nv_close(struct net_device *dev)
5519 {
5520         struct fe_priv *np = netdev_priv(dev);
5521         u8 __iomem *base;
5522
5523         spin_lock_irq(&np->lock);
5524         np->in_shutdown = 1;
5525         spin_unlock_irq(&np->lock);
5526         nv_napi_disable(dev);
5527         synchronize_irq(np->pci_dev->irq);
5528
5529         del_timer_sync(&np->oom_kick);
5530         del_timer_sync(&np->nic_poll);
5531         del_timer_sync(&np->stats_poll);
5532
5533         netif_stop_queue(dev);
5534         spin_lock_irq(&np->lock);
5535         nv_stop_rxtx(dev);
5536         nv_txrx_reset(dev);
5537
5538         /* disable interrupts on the nic or we will lock up */
5539         base = get_hwbase(dev);
5540         nv_disable_hw_interrupts(dev, np->irqmask);
5541         pci_push(base);
5542         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5543
5544         spin_unlock_irq(&np->lock);
5545
5546         nv_free_irq(dev);
5547
5548         nv_drain_rxtx(dev);
5549
5550         if (np->wolenabled || !phy_power_down) {
5551                 nv_txrx_gate(dev, false);
5552                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5553                 nv_start_rx(dev);
5554         } else {
5555                 /* power down phy */
5556                 mii_rw(dev, np->phyaddr, MII_BMCR,
5557                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5558                 nv_txrx_gate(dev, true);
5559         }
5560
5561         /* FIXME: power down nic */
5562
5563         return 0;
5564 }
5565
5566 static const struct net_device_ops nv_netdev_ops = {
5567         .ndo_open               = nv_open,
5568         .ndo_stop               = nv_close,
5569         .ndo_get_stats          = nv_get_stats,
5570         .ndo_start_xmit         = nv_start_xmit,
5571         .ndo_tx_timeout         = nv_tx_timeout,
5572         .ndo_change_mtu         = nv_change_mtu,
5573         .ndo_validate_addr      = eth_validate_addr,
5574         .ndo_set_mac_address    = nv_set_mac_address,
5575         .ndo_set_multicast_list = nv_set_multicast,
5576         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5577 #ifdef CONFIG_NET_POLL_CONTROLLER
5578         .ndo_poll_controller    = nv_poll_controller,
5579 #endif
5580 };
5581
5582 static const struct net_device_ops nv_netdev_ops_optimized = {
5583         .ndo_open               = nv_open,
5584         .ndo_stop               = nv_close,
5585         .ndo_get_stats          = nv_get_stats,
5586         .ndo_start_xmit         = nv_start_xmit_optimized,
5587         .ndo_tx_timeout         = nv_tx_timeout,
5588         .ndo_change_mtu         = nv_change_mtu,
5589         .ndo_validate_addr      = eth_validate_addr,
5590         .ndo_set_mac_address    = nv_set_mac_address,
5591         .ndo_set_multicast_list = nv_set_multicast,
5592         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5593 #ifdef CONFIG_NET_POLL_CONTROLLER
5594         .ndo_poll_controller    = nv_poll_controller,
5595 #endif
5596 };
5597
5598 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5599 {
5600         struct net_device *dev;
5601         struct fe_priv *np;
5602         unsigned long addr;
5603         u8 __iomem *base;
5604         int err, i;
5605         u32 powerstate, txreg;
5606         u32 phystate_orig = 0, phystate;
5607         int phyinitialized = 0;
5608         static int printed_version;
5609
5610         if (!printed_version++)
5611                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5612                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5613
5614         dev = alloc_etherdev(sizeof(struct fe_priv));
5615         err = -ENOMEM;
5616         if (!dev)
5617                 goto out;
5618
5619         np = netdev_priv(dev);
5620         np->dev = dev;
5621         np->pci_dev = pci_dev;
5622         spin_lock_init(&np->lock);
5623         SET_NETDEV_DEV(dev, &pci_dev->dev);
5624
5625         init_timer(&np->oom_kick);
5626         np->oom_kick.data = (unsigned long) dev;
5627         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5628         init_timer(&np->nic_poll);
5629         np->nic_poll.data = (unsigned long) dev;
5630         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5631         init_timer(&np->stats_poll);
5632         np->stats_poll.data = (unsigned long) dev;
5633         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5634
5635         err = pci_enable_device(pci_dev);
5636         if (err)
5637                 goto out_free;
5638
5639         pci_set_master(pci_dev);
5640
5641         err = pci_request_regions(pci_dev, DRV_NAME);
5642         if (err < 0)
5643                 goto out_disable;
5644
5645         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5646                 np->register_size = NV_PCI_REGSZ_VER3;
5647         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5648                 np->register_size = NV_PCI_REGSZ_VER2;
5649         else
5650                 np->register_size = NV_PCI_REGSZ_VER1;
5651
5652         err = -EINVAL;
5653         addr = 0;
5654         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5655                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5656                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5657                                 pci_resource_len(pci_dev, i),
5658                                 pci_resource_flags(pci_dev, i));
5659                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5660                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5661                         addr = pci_resource_start(pci_dev, i);
5662                         break;
5663                 }
5664         }
5665         if (i == DEVICE_COUNT_RESOURCE) {
5666                 dev_printk(KERN_INFO, &pci_dev->dev,
5667                            "Couldn't find register window\n");
5668                 goto out_relreg;
5669         }
5670
5671         /* copy of driver data */
5672         np->driver_data = id->driver_data;
5673         /* copy of device id */
5674         np->device_id = id->device;
5675
5676         /* handle different descriptor versions */
5677         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5678                 /* packet format 3: supports 40-bit addressing */
5679                 np->desc_ver = DESC_VER_3;
5680                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5681                 if (dma_64bit) {
5682                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5683                                 dev_printk(KERN_INFO, &pci_dev->dev,
5684                                         "64-bit DMA failed, using 32-bit addressing\n");
5685                         else
5686                                 dev->features |= NETIF_F_HIGHDMA;
5687                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5688                                 dev_printk(KERN_INFO, &pci_dev->dev,
5689                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5690                         }
5691                 }
5692         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5693                 /* packet format 2: supports jumbo frames */
5694                 np->desc_ver = DESC_VER_2;
5695                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5696         } else {
5697                 /* original packet format */
5698                 np->desc_ver = DESC_VER_1;
5699                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5700         }
5701
5702         np->pkt_limit = NV_PKTLIMIT_1;
5703         if (id->driver_data & DEV_HAS_LARGEDESC)
5704                 np->pkt_limit = NV_PKTLIMIT_2;
5705
5706         if (id->driver_data & DEV_HAS_CHECKSUM) {
5707                 np->rx_csum = 1;
5708                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5709                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5710                 dev->features |= NETIF_F_TSO;
5711         }
5712
5713         np->vlanctl_bits = 0;
5714         if (id->driver_data & DEV_HAS_VLAN) {
5715                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5716                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5717         }
5718
5719         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5720         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5721             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5722             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5723                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5724         }
5725
5726
5727         err = -ENOMEM;
5728         np->base = ioremap(addr, np->register_size);
5729         if (!np->base)
5730                 goto out_relreg;
5731         dev->base_addr = (unsigned long)np->base;
5732
5733         dev->irq = pci_dev->irq;
5734
5735         np->rx_ring_size = RX_RING_DEFAULT;
5736         np->tx_ring_size = TX_RING_DEFAULT;
5737
5738         if (!nv_optimized(np)) {
5739                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5740                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5741                                         &np->ring_addr);
5742                 if (!np->rx_ring.orig)
5743                         goto out_unmap;
5744                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5745         } else {
5746                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5747                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5748                                         &np->ring_addr);
5749                 if (!np->rx_ring.ex)
5750                         goto out_unmap;
5751                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5752         }
5753         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5754         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5755         if (!np->rx_skb || !np->tx_skb)
5756                 goto out_freering;
5757
5758         if (!nv_optimized(np))
5759                 dev->netdev_ops = &nv_netdev_ops;
5760         else
5761                 dev->netdev_ops = &nv_netdev_ops_optimized;
5762
5763 #ifdef CONFIG_FORCEDETH_NAPI
5764         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5765 #endif
5766         SET_ETHTOOL_OPS(dev, &ops);
5767         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5768
5769         pci_set_drvdata(pci_dev, dev);
5770
5771         /* read the mac address */
5772         base = get_hwbase(dev);
5773         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5774         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5775
5776         /* check the workaround bit for correct mac address order */
5777         txreg = readl(base + NvRegTransmitPoll);
5778         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5779                 /* mac address is already in correct order */
5780                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5781                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5782                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5783                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5784                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5785                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5786         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5787                 /* mac address is already in correct order */
5788                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5789                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5790                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5791                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5792                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5793                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5794                 /*
5795                  * Set orig mac address back to the reversed version.
5796                  * This flag will be cleared during low power transition.
5797                  * Therefore, we should always put back the reversed address.
5798                  */
5799                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5800                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5801                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5802         } else {
5803                 /* need to reverse mac address to correct order */
5804                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5805                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5806                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5807                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5808                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5809                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5810                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5811                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5812         }
5813         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5814
5815         if (!is_valid_ether_addr(dev->perm_addr)) {
5816                 /*
5817                  * Bad mac address. At least one bios sets the mac address
5818                  * to 01:23:45:67:89:ab
5819                  */
5820                 dev_printk(KERN_ERR, &pci_dev->dev,
5821                         "Invalid Mac address detected: %pM\n",
5822                         dev->dev_addr);
5823                 dev_printk(KERN_ERR, &pci_dev->dev,
5824                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5825                 random_ether_addr(dev->dev_addr);
5826         }
5827
5828         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5829                 pci_name(pci_dev), dev->dev_addr);
5830
5831         /* set mac address */
5832         nv_copy_mac_to_hw(dev);
5833
5834         /* Workaround current PCI init glitch:  wakeup bits aren't
5835          * being set from PCI PM capability.
5836          */
5837         device_init_wakeup(&pci_dev->dev, 1);
5838
5839         /* disable WOL */
5840         writel(0, base + NvRegWakeUpFlags);
5841         np->wolenabled = 0;
5842
5843         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5844
5845                 /* take phy and nic out of low power mode */
5846                 powerstate = readl(base + NvRegPowerState2);
5847                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5848                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5849                     pci_dev->revision >= 0xA3)
5850                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5851                 writel(powerstate, base + NvRegPowerState2);
5852         }
5853
5854         if (np->desc_ver == DESC_VER_1) {
5855                 np->tx_flags = NV_TX_VALID;
5856         } else {
5857                 np->tx_flags = NV_TX2_VALID;
5858         }
5859
5860         np->msi_flags = 0;
5861         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5862                 np->msi_flags |= NV_MSI_CAPABLE;
5863         }
5864         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5865                 /* msix has had reported issues when modifying irqmask
5866                    as in the case of napi, therefore, disable for now
5867                 */
5868 #ifndef CONFIG_FORCEDETH_NAPI
5869                 np->msi_flags |= NV_MSI_X_CAPABLE;
5870 #endif
5871         }
5872
5873         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5874                 np->irqmask = NVREG_IRQMASK_CPU;
5875                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5876                         np->msi_flags |= 0x0001;
5877         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5878                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5879                 /* start off in throughput mode */
5880                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5881                 /* remove support for msix mode */
5882                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5883         } else {
5884                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5885                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5886                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5887                         np->msi_flags |= 0x0003;
5888         }
5889
5890         if (id->driver_data & DEV_NEED_TIMERIRQ)
5891                 np->irqmask |= NVREG_IRQ_TIMER;
5892         if (id->driver_data & DEV_NEED_LINKTIMER) {
5893                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5894                 np->need_linktimer = 1;
5895                 np->link_timeout = jiffies + LINK_TIMEOUT;
5896         } else {
5897                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5898                 np->need_linktimer = 0;
5899         }
5900
5901         /* Limit the number of tx's outstanding for hw bug */
5902         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5903                 np->tx_limit = 1;
5904                 if ((id->driver_data & DEV_NEED_TX_LIMIT2) &&
5905                     pci_dev->revision >= 0xA2)
5906                         np->tx_limit = 0;
5907         }
5908
5909         /* clear phy state and temporarily halt phy interrupts */
5910         writel(0, base + NvRegMIIMask);
5911         phystate = readl(base + NvRegAdapterControl);
5912         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5913                 phystate_orig = 1;
5914                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5915                 writel(phystate, base + NvRegAdapterControl);
5916         }
5917         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5918
5919         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5920                 /* management unit running on the mac? */
5921                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5922                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5923                     nv_mgmt_acquire_sema(dev) &&
5924                     nv_mgmt_get_version(dev)) {
5925                         np->mac_in_use = 1;
5926                         if (np->mgmt_version > 0) {
5927                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5928                         }
5929                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5930                                 pci_name(pci_dev), np->mac_in_use);
5931                         /* management unit setup the phy already? */
5932                         if (np->mac_in_use &&
5933                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5934                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5935                                 /* phy is inited by mgmt unit */
5936                                 phyinitialized = 1;
5937                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5938                                         pci_name(pci_dev));
5939                         } else {
5940                                 /* we need to init the phy */
5941                         }
5942                 }
5943         }
5944
5945         /* find a suitable phy */
5946         for (i = 1; i <= 32; i++) {
5947                 int id1, id2;
5948                 int phyaddr = i & 0x1F;
5949
5950                 spin_lock_irq(&np->lock);
5951                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5952                 spin_unlock_irq(&np->lock);
5953                 if (id1 < 0 || id1 == 0xffff)
5954                         continue;
5955                 spin_lock_irq(&np->lock);
5956                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5957                 spin_unlock_irq(&np->lock);
5958                 if (id2 < 0 || id2 == 0xffff)
5959                         continue;
5960
5961                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5962                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5963                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5964                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5965                         pci_name(pci_dev), id1, id2, phyaddr);
5966                 np->phyaddr = phyaddr;
5967                 np->phy_oui = id1 | id2;
5968
5969                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5970                 if (np->phy_oui == PHY_OUI_REALTEK2)
5971                         np->phy_oui = PHY_OUI_REALTEK;
5972                 /* Setup phy revision for Realtek */
5973                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5974                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5975
5976                 break;
5977         }
5978         if (i == 33) {
5979                 dev_printk(KERN_INFO, &pci_dev->dev,
5980                         "open: Could not find a valid PHY.\n");
5981                 goto out_error;
5982         }
5983
5984         if (!phyinitialized) {
5985                 /* reset it */
5986                 phy_init(dev);
5987         } else {
5988                 /* see if it is a gigabit phy */
5989                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5990                 if (mii_status & PHY_GIGABIT) {
5991                         np->gigabit = PHY_GIGABIT;
5992                 }
5993         }
5994
5995         /* set default link speed settings */
5996         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5997         np->duplex = 0;
5998         np->autoneg = 1;
5999
6000         err = register_netdev(dev);
6001         if (err) {
6002                 dev_printk(KERN_INFO, &pci_dev->dev,
6003                            "unable to register netdev: %d\n", err);
6004                 goto out_error;
6005         }
6006
6007         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
6008                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
6009                    dev->name,
6010                    np->phy_oui,
6011                    np->phyaddr,
6012                    dev->dev_addr[0],
6013                    dev->dev_addr[1],
6014                    dev->dev_addr[2],
6015                    dev->dev_addr[3],
6016                    dev->dev_addr[4],
6017                    dev->dev_addr[5]);
6018
6019         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6020                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6021                    dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6022                         "csum " : "",
6023                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
6024                         "vlan " : "",
6025                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6026                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6027                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6028                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
6029                    np->need_linktimer ? "lnktim " : "",
6030                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6031                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6032                    np->desc_ver);
6033
6034         return 0;
6035
6036 out_error:
6037         if (phystate_orig)
6038                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6039         pci_set_drvdata(pci_dev, NULL);
6040 out_freering:
6041         free_rings(dev);
6042 out_unmap:
6043         iounmap(get_hwbase(dev));
6044 out_relreg:
6045         pci_release_regions(pci_dev);
6046 out_disable:
6047         pci_disable_device(pci_dev);
6048 out_free:
6049         free_netdev(dev);
6050 out:
6051         return err;
6052 }
6053
6054 static void nv_restore_phy(struct net_device *dev)
6055 {
6056         struct fe_priv *np = netdev_priv(dev);
6057         u16 phy_reserved, mii_control;
6058
6059         if (np->phy_oui == PHY_OUI_REALTEK &&
6060             np->phy_model == PHY_MODEL_REALTEK_8201 &&
6061             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6062                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6063                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6064                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6065                 phy_reserved |= PHY_REALTEK_INIT8;
6066                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6067                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6068
6069                 /* restart auto negotiation */
6070                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6071                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6072                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6073         }
6074 }
6075
6076 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6077 {
6078         struct net_device *dev = pci_get_drvdata(pci_dev);
6079         struct fe_priv *np = netdev_priv(dev);
6080         u8 __iomem *base = get_hwbase(dev);
6081
6082         /* special op: write back the misordered MAC address - otherwise
6083          * the next nv_probe would see a wrong address.
6084          */
6085         writel(np->orig_mac[0], base + NvRegMacAddrA);
6086         writel(np->orig_mac[1], base + NvRegMacAddrB);
6087         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6088                base + NvRegTransmitPoll);
6089 }
6090
6091 static void __devexit nv_remove(struct pci_dev *pci_dev)
6092 {
6093         struct net_device *dev = pci_get_drvdata(pci_dev);
6094
6095         unregister_netdev(dev);
6096
6097         nv_restore_mac_addr(pci_dev);
6098
6099         /* restore any phy related changes */
6100         nv_restore_phy(dev);
6101
6102         nv_mgmt_release_sema(dev);
6103
6104         /* free all structures */
6105         free_rings(dev);
6106         iounmap(get_hwbase(dev));
6107         pci_release_regions(pci_dev);
6108         pci_disable_device(pci_dev);
6109         free_netdev(dev);
6110         pci_set_drvdata(pci_dev, NULL);
6111 }
6112
6113 #ifdef CONFIG_PM
6114 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6115 {
6116         struct net_device *dev = pci_get_drvdata(pdev);
6117         struct fe_priv *np = netdev_priv(dev);
6118         u8 __iomem *base = get_hwbase(dev);
6119         int i;
6120
6121         if (netif_running(dev)) {
6122                 // Gross.
6123                 nv_close(dev);
6124         }
6125         netif_device_detach(dev);
6126
6127         /* save non-pci configuration space */
6128         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6129                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6130
6131         pci_save_state(pdev);
6132         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
6133         pci_disable_device(pdev);
6134         pci_set_power_state(pdev, pci_choose_state(pdev, state));
6135         return 0;
6136 }
6137
6138 static int nv_resume(struct pci_dev *pdev)
6139 {
6140         struct net_device *dev = pci_get_drvdata(pdev);
6141         struct fe_priv *np = netdev_priv(dev);
6142         u8 __iomem *base = get_hwbase(dev);
6143         int i, rc = 0;
6144
6145         pci_set_power_state(pdev, PCI_D0);
6146         pci_restore_state(pdev);
6147         /* ack any pending wake events, disable PME */
6148         pci_enable_wake(pdev, PCI_D0, 0);
6149
6150         /* restore non-pci configuration space */
6151         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6152                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6153
6154         if (np->driver_data & DEV_NEED_MSI_FIX)
6155                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6156
6157         /* restore phy state, including autoneg */
6158         phy_init(dev);
6159
6160         netif_device_attach(dev);
6161         if (netif_running(dev)) {
6162                 rc = nv_open(dev);
6163                 nv_set_multicast(dev);
6164         }
6165         return rc;
6166 }
6167
6168 static void nv_shutdown(struct pci_dev *pdev)
6169 {
6170         struct net_device *dev = pci_get_drvdata(pdev);
6171         struct fe_priv *np = netdev_priv(dev);
6172
6173         if (netif_running(dev))
6174                 nv_close(dev);
6175
6176         /*
6177          * Restore the MAC so a kernel started by kexec won't get confused.
6178          * If we really go for poweroff, we must not restore the MAC,
6179          * otherwise the MAC for WOL will be reversed at least on some boards.
6180          */
6181         if (system_state != SYSTEM_POWER_OFF) {
6182                 nv_restore_mac_addr(pdev);
6183         }
6184
6185         pci_disable_device(pdev);
6186         /*
6187          * Apparently it is not possible to reinitialise from D3 hot,
6188          * only put the device into D3 if we really go for poweroff.
6189          */
6190         if (system_state == SYSTEM_POWER_OFF) {
6191                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6192                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6193                 pci_set_power_state(pdev, PCI_D3hot);
6194         }
6195 }
6196 #else
6197 #define nv_suspend NULL
6198 #define nv_shutdown NULL
6199 #define nv_resume NULL
6200 #endif /* CONFIG_PM */
6201
6202 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6203         {       /* nForce Ethernet Controller */
6204                 PCI_DEVICE(0x10DE, 0x01C3),
6205                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6206         },
6207         {       /* nForce2 Ethernet Controller */
6208                 PCI_DEVICE(0x10DE, 0x0066),
6209                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6210         },
6211         {       /* nForce3 Ethernet Controller */
6212                 PCI_DEVICE(0x10DE, 0x00D6),
6213                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6214         },
6215         {       /* nForce3 Ethernet Controller */
6216                 PCI_DEVICE(0x10DE, 0x0086),
6217                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6218         },
6219         {       /* nForce3 Ethernet Controller */
6220                 PCI_DEVICE(0x10DE, 0x008C),
6221                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6222         },
6223         {       /* nForce3 Ethernet Controller */
6224                 PCI_DEVICE(0x10DE, 0x00E6),
6225                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6226         },
6227         {       /* nForce3 Ethernet Controller */
6228                 PCI_DEVICE(0x10DE, 0x00DF),
6229                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6230         },
6231         {       /* CK804 Ethernet Controller */
6232                 PCI_DEVICE(0x10DE, 0x0056),
6233                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6234         },
6235         {       /* CK804 Ethernet Controller */
6236                 PCI_DEVICE(0x10DE, 0x0057),
6237                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6238         },
6239         {       /* MCP04 Ethernet Controller */
6240                 PCI_DEVICE(0x10DE, 0x0037),
6241                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6242         },
6243         {       /* MCP04 Ethernet Controller */
6244                 PCI_DEVICE(0x10DE, 0x0038),
6245                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6246         },
6247         {       /* MCP51 Ethernet Controller */
6248                 PCI_DEVICE(0x10DE, 0x0268),
6249                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6250         },
6251         {       /* MCP51 Ethernet Controller */
6252                 PCI_DEVICE(0x10DE, 0x0269),
6253                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6254         },
6255         {       /* MCP55 Ethernet Controller */
6256                 PCI_DEVICE(0x10DE, 0x0372),
6257                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6258         },
6259         {       /* MCP55 Ethernet Controller */
6260                 PCI_DEVICE(0x10DE, 0x0373),
6261                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6262         },
6263         {       /* MCP61 Ethernet Controller */
6264                 PCI_DEVICE(0x10DE, 0x03E5),
6265                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6266         },
6267         {       /* MCP61 Ethernet Controller */
6268                 PCI_DEVICE(0x10DE, 0x03E6),
6269                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6270         },
6271         {       /* MCP61 Ethernet Controller */
6272                 PCI_DEVICE(0x10DE, 0x03EE),
6273                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6274         },
6275         {       /* MCP61 Ethernet Controller */
6276                 PCI_DEVICE(0x10DE, 0x03EF),
6277                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6278         },
6279         {       /* MCP65 Ethernet Controller */
6280                 PCI_DEVICE(0x10DE, 0x0450),
6281                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6282         },
6283         {       /* MCP65 Ethernet Controller */
6284                 PCI_DEVICE(0x10DE, 0x0451),
6285                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6286         },
6287         {       /* MCP65 Ethernet Controller */
6288                 PCI_DEVICE(0x10DE, 0x0452),
6289                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6290         },
6291         {       /* MCP65 Ethernet Controller */
6292                 PCI_DEVICE(0x10DE, 0x0453),
6293                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6294         },
6295         {       /* MCP67 Ethernet Controller */
6296                 PCI_DEVICE(0x10DE, 0x054C),
6297                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6298         },
6299         {       /* MCP67 Ethernet Controller */
6300                 PCI_DEVICE(0x10DE, 0x054D),
6301                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6302         },
6303         {       /* MCP67 Ethernet Controller */
6304                 PCI_DEVICE(0x10DE, 0x054E),
6305                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6306         },
6307         {       /* MCP67 Ethernet Controller */
6308                 PCI_DEVICE(0x10DE, 0x054F),
6309                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6310         },
6311         {       /* MCP73 Ethernet Controller */
6312                 PCI_DEVICE(0x10DE, 0x07DC),
6313                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6314         },
6315         {       /* MCP73 Ethernet Controller */
6316                 PCI_DEVICE(0x10DE, 0x07DD),
6317                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6318         },
6319         {       /* MCP73 Ethernet Controller */
6320                 PCI_DEVICE(0x10DE, 0x07DE),
6321                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6322         },
6323         {       /* MCP73 Ethernet Controller */
6324                 PCI_DEVICE(0x10DE, 0x07DF),
6325                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6326         },
6327         {       /* MCP77 Ethernet Controller */
6328                 PCI_DEVICE(0x10DE, 0x0760),
6329                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6330         },
6331         {       /* MCP77 Ethernet Controller */
6332                 PCI_DEVICE(0x10DE, 0x0761),
6333                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6334         },
6335         {       /* MCP77 Ethernet Controller */
6336                 PCI_DEVICE(0x10DE, 0x0762),
6337                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6338         },
6339         {       /* MCP77 Ethernet Controller */
6340                 PCI_DEVICE(0x10DE, 0x0763),
6341                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6342         },
6343         {       /* MCP79 Ethernet Controller */
6344                 PCI_DEVICE(0x10DE, 0x0AB0),
6345                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6346         },
6347         {       /* MCP79 Ethernet Controller */
6348                 PCI_DEVICE(0x10DE, 0x0AB1),
6349                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6350         },
6351         {       /* MCP79 Ethernet Controller */
6352                 PCI_DEVICE(0x10DE, 0x0AB2),
6353                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6354         },
6355         {       /* MCP79 Ethernet Controller */
6356                 PCI_DEVICE(0x10DE, 0x0AB3),
6357                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6358         },
6359         {       /* MCP89 Ethernet Controller */
6360                 PCI_DEVICE(0x10DE, 0x0D7D),
6361                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6362         },
6363         {0,},
6364 };
6365
6366 static struct pci_driver driver = {
6367         .name           = DRV_NAME,
6368         .id_table       = pci_tbl,
6369         .probe          = nv_probe,
6370         .remove         = __devexit_p(nv_remove),
6371         .suspend        = nv_suspend,
6372         .resume         = nv_resume,
6373         .shutdown       = nv_shutdown,
6374 };
6375
6376 static int __init init_nic(void)
6377 {
6378         return pci_register_driver(&driver);
6379 }
6380
6381 static void __exit exit_nic(void)
6382 {
6383         pci_unregister_driver(&driver);
6384 }
6385
6386 module_param(max_interrupt_work, int, 0);
6387 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6388 module_param(optimization_mode, int, 0);
6389 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6390 module_param(poll_interval, int, 0);
6391 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6392 module_param(msi, int, 0);
6393 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6394 module_param(msix, int, 0);
6395 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6396 module_param(dma_64bit, int, 0);
6397 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6398 module_param(phy_cross, int, 0);
6399 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6400 module_param(phy_power_down, int, 0);
6401 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6402
6403 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6404 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6405 MODULE_LICENSE("GPL");
6406
6407 MODULE_DEVICE_TABLE(pci, pci_tbl);
6408
6409 module_init(init_nic);
6410 module_exit(exit_nic);