drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 142
 143 /* Strapping Option Register - RO */
 144 #define E1000_STRAP                     0x0000C
 145 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 146 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 147
 148 /* OEM Bits Phy Register */
 149 #define HV_OEM_BITS            PHY_REG(768, 25)
 150 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 151 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 152 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 153
 154 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 155 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 156
 157 /* KMRN Mode Control */
 158 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 159 #define HV_KMRN_MDIO_SLOW      0x0400
 160
 161 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 162 /* Offset 04h HSFSTS */
 163 union ich8_hws_flash_status {
 164         struct ich8_hsfsts {
 165                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 166                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 167                 u16 dael       :1; /* bit 2 Direct Access error Log */
 168                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 169                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 170                 u16 reserved1  :2; /* bit 13:6 Reserved */
 171                 u16 reserved2  :6; /* bit 13:6 Reserved */
 172                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 173                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 174         } hsf_status;
 175         u16 regval;
 176 };
 177
 178 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 179 /* Offset 06h FLCTL */
 180 union ich8_hws_flash_ctrl {
 181         struct ich8_hsflctl {
 182                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 183                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 184                 u16 reserved   :5;   /* 7:3 Reserved  */
 185                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 186                 u16 flockdn    :6;   /* 15:10 Reserved */
 187         } hsf_ctrl;
 188         u16 regval;
 189 };
 190
 191 /* ICH Flash Region Access Permissions */
 192 union ich8_hws_flash_regacc {
 193         struct ich8_flracc {
 194                 u32 grra      :8; /* 0:7 GbE region Read Access */
 195                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 196                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 197                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 198         } hsf_flregacc;
 199         u16 regval;
 200 };
 201
 202 /* ICH Flash Protected Region */
 203 union ich8_flash_protected_range {
 204         struct ich8_pr {
 205                 u32 base:13;     /* 0:12 Protected Range Base */
 206                 u32 reserved1:2; /* 13:14 Reserved */
 207                 u32 rpe:1;       /* 15 Read Protection Enable */
 208                 u32 limit:13;    /* 16:28 Protected Range Limit */
 209                 u32 reserved2:2; /* 29:30 Reserved */
 210                 u32 wpe:1;       /* 31 Write Protection Enable */
 211         } range;
 212         u32 regval;
 213 };
 214
 215 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 216 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 217 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 218 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 219 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 220                                                 u32 offset, u8 byte);
 221 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 222                                          u8 *data);
 223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 224                                          u16 *data);
 225 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 226                                          u8 size, u16 *data);
 227 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 228 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 229 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 230 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 231 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 232 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 233 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 234 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 235 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 236 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 237 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 238 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 239 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 240 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 241 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 242 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 243 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 244 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 245 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 246
 247 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 248 {
 249         return readw(hw->flash_address + reg);
 250 }
 251
 252 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 253 {
 254         return readl(hw->flash_address + reg);
 255 }
 256
 257 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 258 {
 259         writew(val, hw->flash_address + reg);
 260 }
 261
 262 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 263 {
 264         writel(val, hw->flash_address + reg);
 265 }
 266
 267 #define er16flash(reg)          __er16flash(hw, (reg))
 268 #define er32flash(reg)          __er32flash(hw, (reg))
 269 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 270 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 271
 272 /**
 273  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 274  *  @hw: pointer to the HW structure
 275  *
 276  *  Initialize family-specific PHY parameters and function pointers.
 277  **/
 278 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 279 {
 280         struct e1000_phy_info *phy = &hw->phy;
 281         u32 ctrl;
 282         s32 ret_val = 0;
 283
 284         phy->addr                     = 1;
 285         phy->reset_delay_us           = 100;
 286
 287         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 288         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 289         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 290         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 291         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 292         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 293         phy->ops.power_up             = e1000_power_up_phy_copper;
 294         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 295         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 296
 297         /*
 298          * The MAC-PHY interconnect may still be in SMBus mode
 299          * after Sx->S0.  If the manageability engine (ME) is
 300          * disabled, then toggle the LANPHYPC Value bit to force
 301          * the interconnect to PCIe mode.
 302          */
 303         if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 304                 ctrl = er32(CTRL);
 305                 ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
 306                 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 307                 ew32(CTRL, ctrl);
 308                 udelay(10);
 309                 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 310                 ew32(CTRL, ctrl);
 311                 msleep(50);
 312         }
 313
 314         /*
 315          * Reset the PHY before any acccess to it.  Doing so, ensures that
 316          * the PHY is in a known good state before we read/write PHY registers.
 317          * The generic reset is sufficient here, because we haven't determined
 318          * the PHY type yet.
 319          */
 320         ret_val = e1000e_phy_hw_reset_generic(hw);
 321         if (ret_val)
 322                 goto out;
 323
 324         phy->id = e1000_phy_unknown;
 325         ret_val = e1000e_get_phy_id(hw);
 326         if (ret_val)
 327                 goto out;
 328         if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
 329                 /*
 330                  * In case the PHY needs to be in mdio slow mode (eg. 82577),
 331                  * set slow mode and try to get the PHY id again.
 332                  */
 333                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 334                 if (ret_val)
 335                         goto out;
 336                 ret_val = e1000e_get_phy_id(hw);
 337                 if (ret_val)
 338                         goto out;
 339         }
 340         phy->type = e1000e_get_phy_type_from_id(phy->id);
 341
 342         switch (phy->type) {
 343         case e1000_phy_82577:
 344         case e1000_phy_82579:
 345                 phy->ops.check_polarity = e1000_check_polarity_82577;
 346                 phy->ops.force_speed_duplex =
 347                         e1000_phy_force_speed_duplex_82577;
 348                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 349                 phy->ops.get_info = e1000_get_phy_info_82577;
 350                 phy->ops.commit = e1000e_phy_sw_reset;
 351                 break;
 352         case e1000_phy_82578:
 353                 phy->ops.check_polarity = e1000_check_polarity_m88;
 354                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 355                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 356                 phy->ops.get_info = e1000e_get_phy_info_m88;
 357                 break;
 358         default:
 359                 ret_val = -E1000_ERR_PHY;
 360                 break;
 361         }
 362
 363 out:
 364         return ret_val;
 365 }
 366
 367 /**
 368  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 369  *  @hw: pointer to the HW structure
 370  *
 371  *  Initialize family-specific PHY parameters and function pointers.
 372  **/
 373 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 374 {
 375         struct e1000_phy_info *phy = &hw->phy;
 376         s32 ret_val;
 377         u16 i = 0;
 378
 379         phy->addr                       = 1;
 380         phy->reset_delay_us             = 100;
 381
 382         phy->ops.power_up               = e1000_power_up_phy_copper;
 383         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 384
 385         /*
 386          * We may need to do this twice - once for IGP and if that fails,
 387          * we'll set BM func pointers and try again
 388          */
 389         ret_val = e1000e_determine_phy_address(hw);
 390         if (ret_val) {
 391                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 392                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 393                 ret_val = e1000e_determine_phy_address(hw);
 394                 if (ret_val) {
 395                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 396                         return ret_val;
 397                 }
 398         }
 399
 400         phy->id = 0;
 401         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 402                (i++ < 100)) {
 403                 msleep(1);
 404                 ret_val = e1000e_get_phy_id(hw);
 405                 if (ret_val)
 406                         return ret_val;
 407         }
 408
 409         /* Verify phy id */
 410         switch (phy->id) {
 411         case IGP03E1000_E_PHY_ID:
 412                 phy->type = e1000_phy_igp_3;
 413                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 414                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 415                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 416                 phy->ops.get_info = e1000e_get_phy_info_igp;
 417                 phy->ops.check_polarity = e1000_check_polarity_igp;
 418                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 419                 break;
 420         case IFE_E_PHY_ID:
 421         case IFE_PLUS_E_PHY_ID:
 422         case IFE_C_E_PHY_ID:
 423                 phy->type = e1000_phy_ife;
 424                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 425                 phy->ops.get_info = e1000_get_phy_info_ife;
 426                 phy->ops.check_polarity = e1000_check_polarity_ife;
 427                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 428                 break;
 429         case BME1000_E_PHY_ID:
 430                 phy->type = e1000_phy_bm;
 431                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 432                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 433                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 434                 phy->ops.commit = e1000e_phy_sw_reset;
 435                 phy->ops.get_info = e1000e_get_phy_info_m88;
 436                 phy->ops.check_polarity = e1000_check_polarity_m88;
 437                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 438                 break;
 439         default:
 440                 return -E1000_ERR_PHY;
 441                 break;
 442         }
 443
 444         return 0;
 445 }
 446
 447 /**
 448  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 449  *  @hw: pointer to the HW structure
 450  *
 451  *  Initialize family-specific NVM parameters and function
 452  *  pointers.
 453  **/
 454 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 455 {
 456         struct e1000_nvm_info *nvm = &hw->nvm;
 457         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 458         u32 gfpreg, sector_base_addr, sector_end_addr;
 459         u16 i;
 460
 461         /* Can't read flash registers if the register set isn't mapped. */
 462         if (!hw->flash_address) {
 463                 e_dbg("ERROR: Flash registers not mapped\n");
 464                 return -E1000_ERR_CONFIG;
 465         }
 466
 467         nvm->type = e1000_nvm_flash_sw;
 468
 469         gfpreg = er32flash(ICH_FLASH_GFPREG);
 470
 471         /*
 472          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 473          * Add 1 to sector_end_addr since this sector is included in
 474          * the overall size.
 475          */
 476         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 477         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 478
 479         /* flash_base_addr is byte-aligned */
 480         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 481
 482         /*
 483          * find total size of the NVM, then cut in half since the total
 484          * size represents two separate NVM banks.
 485          */
 486         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 487                                 << FLASH_SECTOR_ADDR_SHIFT;
 488         nvm->flash_bank_size /= 2;
 489         /* Adjust to word count */
 490         nvm->flash_bank_size /= sizeof(u16);
 491
 492         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 493
 494         /* Clear shadow ram */
 495         for (i = 0; i < nvm->word_size; i++) {
 496                 dev_spec->shadow_ram[i].modified = false;
 497                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 498         }
 499
 500         return 0;
 501 }
 502
 503 /**
 504  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 505  *  @hw: pointer to the HW structure
 506  *
 507  *  Initialize family-specific MAC parameters and function
 508  *  pointers.
 509  **/
 510 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 511 {
 512         struct e1000_hw *hw = &adapter->hw;
 513         struct e1000_mac_info *mac = &hw->mac;
 514
 515         /* Set media type function pointer */
 516         hw->phy.media_type = e1000_media_type_copper;
 517
 518         /* Set mta register count */
 519         mac->mta_reg_count = 32;
 520         /* Set rar entry count */
 521         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 522         if (mac->type == e1000_ich8lan)
 523                 mac->rar_entry_count--;
 524         /* FWSM register */
 525         mac->has_fwsm = true;
 526         /* ARC subsystem not supported */
 527         mac->arc_subsystem_valid = false;
 528         /* Adaptive IFS supported */
 529         mac->adaptive_ifs = true;
 530
 531         /* LED operations */
 532         switch (mac->type) {
 533         case e1000_ich8lan:
 534         case e1000_ich9lan:
 535         case e1000_ich10lan:
 536                 /* check management mode */
 537                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 538                 /* ID LED init */
 539                 mac->ops.id_led_init = e1000e_id_led_init;
 540                 /* setup LED */
 541                 mac->ops.setup_led = e1000e_setup_led_generic;
 542                 /* cleanup LED */
 543                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 544                 /* turn on/off LED */
 545                 mac->ops.led_on = e1000_led_on_ich8lan;
 546                 mac->ops.led_off = e1000_led_off_ich8lan;
 547                 break;
 548         case e1000_pchlan:
 549         case e1000_pch2lan:
 550                 /* check management mode */
 551                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 552                 /* ID LED init */
 553                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 554                 /* setup LED */
 555                 mac->ops.setup_led = e1000_setup_led_pchlan;
 556                 /* cleanup LED */
 557                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 558                 /* turn on/off LED */
 559                 mac->ops.led_on = e1000_led_on_pchlan;
 560                 mac->ops.led_off = e1000_led_off_pchlan;
 561                 break;
 562         default:
 563                 break;
 564         }
 565
 566         /* Enable PCS Lock-loss workaround for ICH8 */
 567         if (mac->type == e1000_ich8lan)
 568                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 569
 570         /* Disable PHY configuration by hardware, config by software */
 571         if (mac->type == e1000_pch2lan) {
 572                 u32 extcnf_ctrl = er32(EXTCNF_CTRL);
 573
 574                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
 575                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 576         }
 577
 578         return 0;
 579 }
 580
 581 /**
 582  *  e1000_set_eee_pchlan - Enable/disable EEE support
 583  *  @hw: pointer to the HW structure
 584  *
 585  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 586  *  the LPI Control register will remain set only if/when link is up.
 587  **/
 588 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 589 {
 590         s32 ret_val = 0;
 591         u16 phy_reg;
 592
 593         if (hw->phy.type != e1000_phy_82579)
 594                 goto out;
 595
 596         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 597         if (ret_val)
 598                 goto out;
 599
 600         if (hw->dev_spec.ich8lan.eee_disable)
 601                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 602         else
 603                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 604
 605         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 606 out:
 607         return ret_val;
 608 }
 609
 610 /**
 611  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 612  *  @hw: pointer to the HW structure
 613  *
 614  *  Checks to see of the link status of the hardware has changed.  If a
 615  *  change in link status has been detected, then we read the PHY registers
 616  *  to get the current speed/duplex if link exists.
 617  **/
 618 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 619 {
 620         struct e1000_mac_info *mac = &hw->mac;
 621         s32 ret_val;
 622         bool link;
 623
 624         /*
 625          * We only want to go out to the PHY registers to see if Auto-Neg
 626          * has completed and/or if our link status has changed.  The
 627          * get_link_status flag is set upon receiving a Link Status
 628          * Change or Rx Sequence Error interrupt.
 629          */
 630         if (!mac->get_link_status) {
 631                 ret_val = 0;
 632                 goto out;
 633         }
 634
 635         /*
 636          * First we want to see if the MII Status Register reports
 637          * link.  If so, then we want to get the current speed/duplex
 638          * of the PHY.
 639          */
 640         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 641         if (ret_val)
 642                 goto out;
 643
 644         if (hw->mac.type == e1000_pchlan) {
 645                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 646                 if (ret_val)
 647                         goto out;
 648         }
 649
 650         if (!link)
 651                 goto out; /* No link detected */
 652
 653         mac->get_link_status = false;
 654
 655         if (hw->phy.type == e1000_phy_82578) {
 656                 ret_val = e1000_link_stall_workaround_hv(hw);
 657                 if (ret_val)
 658                         goto out;
 659         }
 660
 661         if (hw->mac.type == e1000_pch2lan) {
 662                 ret_val = e1000_k1_workaround_lv(hw);
 663                 if (ret_val)
 664                         goto out;
 665         }
 666
 667         /*
 668          * Check if there was DownShift, must be checked
 669          * immediately after link-up
 670          */
 671         e1000e_check_downshift(hw);
 672
 673         /* Enable/Disable EEE after link up */
 674         ret_val = e1000_set_eee_pchlan(hw);
 675         if (ret_val)
 676                 goto out;
 677
 678         /*
 679          * If we are forcing speed/duplex, then we simply return since
 680          * we have already determined whether we have link or not.
 681          */
 682         if (!mac->autoneg) {
 683                 ret_val = -E1000_ERR_CONFIG;
 684                 goto out;
 685         }
 686
 687         /*
 688          * Auto-Neg is enabled.  Auto Speed Detection takes care
 689          * of MAC speed/duplex configuration.  So we only need to
 690          * configure Collision Distance in the MAC.
 691          */
 692         e1000e_config_collision_dist(hw);
 693
 694         /*
 695          * Configure Flow Control now that Auto-Neg has completed.
 696          * First, we need to restore the desired flow control
 697          * settings because we may have had to re-autoneg with a
 698          * different link partner.
 699          */
 700         ret_val = e1000e_config_fc_after_link_up(hw);
 701         if (ret_val)
 702                 e_dbg("Error configuring flow control\n");
 703
 704 out:
 705         return ret_val;
 706 }
 707
 708 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 709 {
 710         struct e1000_hw *hw = &adapter->hw;
 711         s32 rc;
 712
 713         rc = e1000_init_mac_params_ich8lan(adapter);
 714         if (rc)
 715                 return rc;
 716
 717         rc = e1000_init_nvm_params_ich8lan(hw);
 718         if (rc)
 719                 return rc;
 720
 721         switch (hw->mac.type) {
 722         case e1000_ich8lan:
 723         case e1000_ich9lan:
 724         case e1000_ich10lan:
 725                 rc = e1000_init_phy_params_ich8lan(hw);
 726                 break;
 727         case e1000_pchlan:
 728         case e1000_pch2lan:
 729                 rc = e1000_init_phy_params_pchlan(hw);
 730                 break;
 731         default:
 732                 break;
 733         }
 734         if (rc)
 735                 return rc;
 736
 737         if (adapter->hw.phy.type == e1000_phy_ife) {
 738                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 739                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 740         }
 741
 742         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 743             (adapter->hw.phy.type == e1000_phy_igp_3))
 744                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 745
 746         /* Disable EEE by default until IEEE802.3az spec is finalized */
 747         if (adapter->flags2 & FLAG2_HAS_EEE)
 748                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 749
 750         return 0;
 751 }
 752
 753 static DEFINE_MUTEX(nvm_mutex);
 754
 755 /**
 756  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 757  *  @hw: pointer to the HW structure
 758  *
 759  *  Acquires the mutex for performing NVM operations.
 760  **/
 761 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 762 {
 763         mutex_lock(&nvm_mutex);
 764
 765         return 0;
 766 }
 767
 768 /**
 769  *  e1000_release_nvm_ich8lan - Release NVM mutex
 770  *  @hw: pointer to the HW structure
 771  *
 772  *  Releases the mutex used while performing NVM operations.
 773  **/
 774 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 775 {
 776         mutex_unlock(&nvm_mutex);
 777 }
 778
 779 static DEFINE_MUTEX(swflag_mutex);
 780
 781 /**
 782  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 783  *  @hw: pointer to the HW structure
 784  *
 785  *  Acquires the software control flag for performing PHY and select
 786  *  MAC CSR accesses.
 787  **/
 788 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 789 {
 790         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 791         s32 ret_val = 0;
 792
 793         mutex_lock(&swflag_mutex);
 794
 795         while (timeout) {
 796                 extcnf_ctrl = er32(EXTCNF_CTRL);
 797                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 798                         break;
 799
 800                 mdelay(1);
 801                 timeout--;
 802         }
 803
 804         if (!timeout) {
 805                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 806                 ret_val = -E1000_ERR_CONFIG;
 807                 goto out;
 808         }
 809
 810         timeout = SW_FLAG_TIMEOUT;
 811
 812         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 813         ew32(EXTCNF_CTRL, extcnf_ctrl);
 814
 815         while (timeout) {
 816                 extcnf_ctrl = er32(EXTCNF_CTRL);
 817                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 818                         break;
 819
 820                 mdelay(1);
 821                 timeout--;
 822         }
 823
 824         if (!timeout) {
 825                 e_dbg("Failed to acquire the semaphore.\n");
 826                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 827                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 828                 ret_val = -E1000_ERR_CONFIG;
 829                 goto out;
 830         }
 831
 832 out:
 833         if (ret_val)
 834                 mutex_unlock(&swflag_mutex);
 835
 836         return ret_val;
 837 }
 838
 839 /**
 840  *  e1000_release_swflag_ich8lan - Release software control flag
 841  *  @hw: pointer to the HW structure
 842  *
 843  *  Releases the software control flag for performing PHY and select
 844  *  MAC CSR accesses.
 845  **/
 846 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 847 {
 848         u32 extcnf_ctrl;
 849
 850         extcnf_ctrl = er32(EXTCNF_CTRL);
 851         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 852         ew32(EXTCNF_CTRL, extcnf_ctrl);
 853
 854         mutex_unlock(&swflag_mutex);
 855 }
 856
 857 /**
 858  *  e1000_check_mng_mode_ich8lan - Checks management mode
 859  *  @hw: pointer to the HW structure
 860  *
 861  *  This checks if the adapter has any manageability enabled.
 862  *  This is a function pointer entry point only called by read/write
 863  *  routines for the PHY and NVM parts.
 864  **/
 865 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 866 {
 867         u32 fwsm;
 868
 869         fwsm = er32(FWSM);
 870         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 871                ((fwsm & E1000_FWSM_MODE_MASK) ==
 872                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 873 }
 874
 875 /**
 876  *  e1000_check_mng_mode_pchlan - Checks management mode
 877  *  @hw: pointer to the HW structure
 878  *
 879  *  This checks if the adapter has iAMT enabled.
 880  *  This is a function pointer entry point only called by read/write
 881  *  routines for the PHY and NVM parts.
 882  **/
 883 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 884 {
 885         u32 fwsm;
 886
 887         fwsm = er32(FWSM);
 888         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 889                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 890 }
 891
 892 /**
 893  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 894  *  @hw: pointer to the HW structure
 895  *
 896  *  Checks if firmware is blocking the reset of the PHY.
 897  *  This is a function pointer entry point only called by
 898  *  reset routines.
 899  **/
 900 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 901 {
 902         u32 fwsm;
 903
 904         fwsm = er32(FWSM);
 905
 906         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 907 }
 908
 909 /**
 910  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 911  *  @hw: pointer to the HW structure
 912  *
 913  *  Assumes semaphore already acquired.
 914  *
 915  **/
 916 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 917 {
 918         u16 phy_data;
 919         u32 strap = er32(STRAP);
 920         s32 ret_val = 0;
 921
 922         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 923
 924         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
 925         if (ret_val)
 926                 goto out;
 927
 928         phy_data &= ~HV_SMB_ADDR_MASK;
 929         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
 930         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 931         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
 932
 933 out:
 934         return ret_val;
 935 }
 936
 937 /**
 938  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 939  *  @hw:   pointer to the HW structure
 940  *
 941  *  SW should configure the LCD from the NVM extended configuration region
 942  *  as a workaround for certain parts.
 943  **/
 944 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 945 {
 946         struct e1000_phy_info *phy = &hw->phy;
 947         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 948         s32 ret_val = 0;
 949         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 950
 951         /*
 952          * Initialize the PHY from the NVM on ICH platforms.  This
 953          * is needed due to an issue where the NVM configuration is
 954          * not properly autoloaded after power transitions.
 955          * Therefore, after each PHY reset, we will load the
 956          * configuration data out of the NVM manually.
 957          */
 958         switch (hw->mac.type) {
 959         case e1000_ich8lan:
 960                 if (phy->type != e1000_phy_igp_3)
 961                         return ret_val;
 962
 963                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
 964                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
 965                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 966                         break;
 967                 }
 968                 /* Fall-thru */
 969         case e1000_pchlan:
 970         case e1000_pch2lan:
 971                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 972                 break;
 973         default:
 974                 return ret_val;
 975         }
 976
 977         ret_val = hw->phy.ops.acquire(hw);
 978         if (ret_val)
 979                 return ret_val;
 980
 981         data = er32(FEXTNVM);
 982         if (!(data & sw_cfg_mask))
 983                 goto out;
 984
 985         /*
 986          * Make sure HW does not configure LCD from PHY
 987          * extended configuration before SW configuration
 988          */
 989         data = er32(EXTCNF_CTRL);
 990         if (!(hw->mac.type == e1000_pch2lan)) {
 991                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 992                         goto out;
 993         }
 994
 995         cnf_size = er32(EXTCNF_SIZE);
 996         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 997         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 998         if (!cnf_size)
 999                 goto out;
1000
1001         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1002         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1003
1004         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1005             (hw->mac.type == e1000_pchlan)) ||
1006              (hw->mac.type == e1000_pch2lan)) {
1007                 /*
1008                  * HW configures the SMBus address and LEDs when the
1009                  * OEM and LCD Write Enable bits are set in the NVM.
1010                  * When both NVM bits are cleared, SW will configure
1011                  * them instead.
1012                  */
1013                 ret_val = e1000_write_smbus_addr(hw);
1014                 if (ret_val)
1015                         goto out;
1016
1017                 data = er32(LEDCTL);
1018                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1019                                                         (u16)data);
1020                 if (ret_val)
1021                         goto out;
1022         }
1023
1024         /* Configure LCD from extended configuration region. */
1025
1026         /* cnf_base_addr is in DWORD */
1027         word_addr = (u16)(cnf_base_addr << 1);
1028
1029         for (i = 0; i < cnf_size; i++) {
1030                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1031                                          &reg_data);
1032                 if (ret_val)
1033                         goto out;
1034
1035                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1036                                          1, &reg_addr);
1037                 if (ret_val)
1038                         goto out;
1039
1040                 /* Save off the PHY page for future writes. */
1041                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1042                         phy_page = reg_data;
1043                         continue;
1044                 }
1045
1046                 reg_addr &= PHY_REG_MASK;
1047                 reg_addr |= phy_page;
1048
1049                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1050                                                     reg_data);
1051                 if (ret_val)
1052                         goto out;
1053         }
1054
1055 out:
1056         hw->phy.ops.release(hw);
1057         return ret_val;
1058 }
1059
1060 /**
1061  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1062  *  @hw:   pointer to the HW structure
1063  *  @link: link up bool flag
1064  *
1065  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1066  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1067  *  If link is down, the function will restore the default K1 setting located
1068  *  in the NVM.
1069  **/
1070 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1071 {
1072         s32 ret_val = 0;
1073         u16 status_reg = 0;
1074         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1075
1076         if (hw->mac.type != e1000_pchlan)
1077                 goto out;
1078
1079         /* Wrap the whole flow with the sw flag */
1080         ret_val = hw->phy.ops.acquire(hw);
1081         if (ret_val)
1082                 goto out;
1083
1084         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1085         if (link) {
1086                 if (hw->phy.type == e1000_phy_82578) {
1087                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1088                                                                   &status_reg);
1089                         if (ret_val)
1090                                 goto release;
1091
1092                         status_reg &= BM_CS_STATUS_LINK_UP |
1093                                       BM_CS_STATUS_RESOLVED |
1094                                       BM_CS_STATUS_SPEED_MASK;
1095
1096                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1097                                            BM_CS_STATUS_RESOLVED |
1098                                            BM_CS_STATUS_SPEED_1000))
1099                                 k1_enable = false;
1100                 }
1101
1102                 if (hw->phy.type == e1000_phy_82577) {
1103                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1104                                                                   &status_reg);
1105                         if (ret_val)
1106                                 goto release;
1107
1108                         status_reg &= HV_M_STATUS_LINK_UP |
1109                                       HV_M_STATUS_AUTONEG_COMPLETE |
1110                                       HV_M_STATUS_SPEED_MASK;
1111
1112                         if (status_reg == (HV_M_STATUS_LINK_UP |
1113                                            HV_M_STATUS_AUTONEG_COMPLETE |
1114                                            HV_M_STATUS_SPEED_1000))
1115                                 k1_enable = false;
1116                 }
1117
1118                 /* Link stall fix for link up */
1119                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1120                                                            0x0100);
1121                 if (ret_val)
1122                         goto release;
1123
1124         } else {
1125                 /* Link stall fix for link down */
1126                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1127                                                            0x4100);
1128                 if (ret_val)
1129                         goto release;
1130         }
1131
1132         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1133
1134 release:
1135         hw->phy.ops.release(hw);
1136 out:
1137         return ret_val;
1138 }
1139
1140 /**
1141  *  e1000_configure_k1_ich8lan - Configure K1 power state
1142  *  @hw: pointer to the HW structure
1143  *  @enable: K1 state to configure
1144  *
1145  *  Configure the K1 power state based on the provided parameter.
1146  *  Assumes semaphore already acquired.
1147  *
1148  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1149  **/
1150 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1151 {
1152         s32 ret_val = 0;
1153         u32 ctrl_reg = 0;
1154         u32 ctrl_ext = 0;
1155         u32 reg = 0;
1156         u16 kmrn_reg = 0;
1157
1158         ret_val = e1000e_read_kmrn_reg_locked(hw,
1159                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1160                                              &kmrn_reg);
1161         if (ret_val)
1162                 goto out;
1163
1164         if (k1_enable)
1165                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1166         else
1167                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1168
1169         ret_val = e1000e_write_kmrn_reg_locked(hw,
1170                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1171                                               kmrn_reg);
1172         if (ret_val)
1173                 goto out;
1174
1175         udelay(20);
1176         ctrl_ext = er32(CTRL_EXT);
1177         ctrl_reg = er32(CTRL);
1178
1179         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1180         reg |= E1000_CTRL_FRCSPD;
1181         ew32(CTRL, reg);
1182
1183         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1184         udelay(20);
1185         ew32(CTRL, ctrl_reg);
1186         ew32(CTRL_EXT, ctrl_ext);
1187         udelay(20);
1188
1189 out:
1190         return ret_val;
1191 }
1192
1193 /**
1194  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1195  *  @hw:       pointer to the HW structure
1196  *  @d0_state: boolean if entering d0 or d3 device state
1197  *
1198  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1199  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1200  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1201  **/
1202 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1203 {
1204         s32 ret_val = 0;
1205         u32 mac_reg;
1206         u16 oem_reg;
1207
1208         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1209                 return ret_val;
1210
1211         ret_val = hw->phy.ops.acquire(hw);
1212         if (ret_val)
1213                 return ret_val;
1214
1215         if (!(hw->mac.type == e1000_pch2lan)) {
1216                 mac_reg = er32(EXTCNF_CTRL);
1217                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1218                         goto out;
1219         }
1220
1221         mac_reg = er32(FEXTNVM);
1222         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1223                 goto out;
1224
1225         mac_reg = er32(PHY_CTRL);
1226
1227         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1228         if (ret_val)
1229                 goto out;
1230
1231         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1232
1233         if (d0_state) {
1234                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1235                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1236
1237                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1238                         oem_reg |= HV_OEM_BITS_LPLU;
1239         } else {
1240                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1241                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1242
1243                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1244                         oem_reg |= HV_OEM_BITS_LPLU;
1245         }
1246         /* Restart auto-neg to activate the bits */
1247         if (!e1000_check_reset_block(hw))
1248                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1249         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1250
1251 out:
1252         hw->phy.ops.release(hw);
1253
1254         return ret_val;
1255 }
1256
1257
1258 /**
1259  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1260  *  @hw:   pointer to the HW structure
1261  **/
1262 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1263 {
1264         s32 ret_val;
1265         u16 data;
1266
1267         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1268         if (ret_val)
1269                 return ret_val;
1270
1271         data |= HV_KMRN_MDIO_SLOW;
1272
1273         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1274
1275         return ret_val;
1276 }
1277
1278 /**
1279  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1280  *  done after every PHY reset.
1281  **/
1282 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1283 {
1284         s32 ret_val = 0;
1285         u16 phy_data;
1286
1287         if (hw->mac.type != e1000_pchlan)
1288                 return ret_val;
1289
1290         /* Set MDIO slow mode before any other MDIO access */
1291         if (hw->phy.type == e1000_phy_82577) {
1292                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1293                 if (ret_val)
1294                         goto out;
1295         }
1296
1297         if (((hw->phy.type == e1000_phy_82577) &&
1298              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1299             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1300                 /* Disable generation of early preamble */
1301                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1302                 if (ret_val)
1303                         return ret_val;
1304
1305                 /* Preamble tuning for SSC */
1306                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1307                 if (ret_val)
1308                         return ret_val;
1309         }
1310
1311         if (hw->phy.type == e1000_phy_82578) {
1312                 /*
1313                  * Return registers to default by doing a soft reset then
1314                  * writing 0x3140 to the control register.
1315                  */
1316                 if (hw->phy.revision < 2) {
1317                         e1000e_phy_sw_reset(hw);
1318                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1319                 }
1320         }
1321
1322         /* Select page 0 */
1323         ret_val = hw->phy.ops.acquire(hw);
1324         if (ret_val)
1325                 return ret_val;
1326
1327         hw->phy.addr = 1;
1328         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1329         hw->phy.ops.release(hw);
1330         if (ret_val)
1331                 goto out;
1332
1333         /*
1334          * Configure the K1 Si workaround during phy reset assuming there is
1335          * link so that it disables K1 if link is in 1Gbps.
1336          */
1337         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1338         if (ret_val)
1339                 goto out;
1340
1341         /* Workaround for link disconnects on a busy hub in half duplex */
1342         ret_val = hw->phy.ops.acquire(hw);
1343         if (ret_val)
1344                 goto out;
1345         ret_val = hw->phy.ops.read_reg_locked(hw,
1346                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1347                                               &phy_data);
1348         if (ret_val)
1349                 goto release;
1350         ret_val = hw->phy.ops.write_reg_locked(hw,
1351                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1352                                                phy_data & 0x00FF);
1353 release:
1354         hw->phy.ops.release(hw);
1355 out:
1356         return ret_val;
1357 }
1358
1359 /**
1360  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1361  *  @hw:   pointer to the HW structure
1362  **/
1363 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1364 {
1365         u32 mac_reg;
1366         u16 i;
1367
1368         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1369         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1370                 mac_reg = er32(RAL(i));
1371                 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1372                 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1373                 mac_reg = er32(RAH(i));
1374                 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1375                 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1376         }
1377 }
1378
1379 static u32 e1000_calc_rx_da_crc(u8 mac[])
1380 {
1381         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
1382         u32 i, j, mask, crc;
1383
1384         crc = 0xffffffff;
1385         for (i = 0; i < 6; i++) {
1386                 crc = crc ^ mac[i];
1387                 for (j = 8; j > 0; j--) {
1388                         mask = (crc & 1) * (-1);
1389                         crc = (crc >> 1) ^ (poly & mask);
1390                 }
1391         }
1392         return ~crc;
1393 }
1394
1395 /**
1396  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1397  *  with 82579 PHY
1398  *  @hw: pointer to the HW structure
1399  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1400  **/
1401 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1402 {
1403         s32 ret_val = 0;
1404         u16 phy_reg, data;
1405         u32 mac_reg;
1406         u16 i;
1407
1408         if (hw->mac.type != e1000_pch2lan)
1409                 goto out;
1410
1411         /* disable Rx path while enabling/disabling workaround */
1412         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1413         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1414         if (ret_val)
1415                 goto out;
1416
1417         if (enable) {
1418                 /*
1419                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1420                  * SHRAL/H) and initial CRC values to the MAC
1421                  */
1422                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1423                         u8 mac_addr[ETH_ALEN] = {0};
1424                         u32 addr_high, addr_low;
1425
1426                         addr_high = er32(RAH(i));
1427                         if (!(addr_high & E1000_RAH_AV))
1428                                 continue;
1429                         addr_low = er32(RAL(i));
1430                         mac_addr[0] = (addr_low & 0xFF);
1431                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1432                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1433                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1434                         mac_addr[4] = (addr_high & 0xFF);
1435                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1436
1437                         ew32(PCH_RAICC(i),
1438                                         e1000_calc_rx_da_crc(mac_addr));
1439                 }
1440
1441                 /* Write Rx addresses to the PHY */
1442                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1443
1444                 /* Enable jumbo frame workaround in the MAC */
1445                 mac_reg = er32(FFLT_DBG);
1446                 mac_reg &= ~(1 << 14);
1447                 mac_reg |= (7 << 15);
1448                 ew32(FFLT_DBG, mac_reg);
1449
1450                 mac_reg = er32(RCTL);
1451                 mac_reg |= E1000_RCTL_SECRC;
1452                 ew32(RCTL, mac_reg);
1453
1454                 ret_val = e1000e_read_kmrn_reg(hw,
1455                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1456                                                 &data);
1457                 if (ret_val)
1458                         goto out;
1459                 ret_val = e1000e_write_kmrn_reg(hw,
1460                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1461                                                 data | (1 << 0));
1462                 if (ret_val)
1463                         goto out;
1464                 ret_val = e1000e_read_kmrn_reg(hw,
1465                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1466                                                 &data);
1467                 if (ret_val)
1468                         goto out;
1469                 data &= ~(0xF << 8);
1470                 data |= (0xB << 8);
1471                 ret_val = e1000e_write_kmrn_reg(hw,
1472                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1473                                                 data);
1474                 if (ret_val)
1475                         goto out;
1476
1477                 /* Enable jumbo frame workaround in the PHY */
1478                 e1e_rphy(hw, PHY_REG(769, 20), &data);
1479                 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1480                 if (ret_val)
1481                         goto out;
1482                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1483                 data &= ~(0x7F << 5);
1484                 data |= (0x37 << 5);
1485                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1486                 if (ret_val)
1487                         goto out;
1488                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1489                 data &= ~(1 << 13);
1490                 data |= (1 << 12);
1491                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1492                 if (ret_val)
1493                         goto out;
1494                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1495                 data &= ~(0x3FF << 2);
1496                 data |= (0x1A << 2);
1497                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1498                 if (ret_val)
1499                         goto out;
1500                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1501                 if (ret_val)
1502                         goto out;
1503                 e1e_rphy(hw, HV_PM_CTRL, &data);
1504                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1505                 if (ret_val)
1506                         goto out;
1507         } else {
1508                 /* Write MAC register values back to h/w defaults */
1509                 mac_reg = er32(FFLT_DBG);
1510                 mac_reg &= ~(0xF << 14);
1511                 ew32(FFLT_DBG, mac_reg);
1512
1513                 mac_reg = er32(RCTL);
1514                 mac_reg &= ~E1000_RCTL_SECRC;
1515                 ew32(FFLT_DBG, mac_reg);
1516
1517                 ret_val = e1000e_read_kmrn_reg(hw,
1518                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1519                                                 &data);
1520                 if (ret_val)
1521                         goto out;
1522                 ret_val = e1000e_write_kmrn_reg(hw,
1523                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1524                                                 data & ~(1 << 0));
1525                 if (ret_val)
1526                         goto out;
1527                 ret_val = e1000e_read_kmrn_reg(hw,
1528                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1529                                                 &data);
1530                 if (ret_val)
1531                         goto out;
1532                 data &= ~(0xF << 8);
1533                 data |= (0xB << 8);
1534                 ret_val = e1000e_write_kmrn_reg(hw,
1535                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1536                                                 data);
1537                 if (ret_val)
1538                         goto out;
1539
1540                 /* Write PHY register values back to h/w defaults */
1541                 e1e_rphy(hw, PHY_REG(769, 20), &data);
1542                 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1543                 if (ret_val)
1544                         goto out;
1545                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1546                 data &= ~(0x7F << 5);
1547                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1548                 if (ret_val)
1549                         goto out;
1550                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1551                 data &= ~(1 << 12);
1552                 data |= (1 << 13);
1553                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1554                 if (ret_val)
1555                         goto out;
1556                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1557                 data &= ~(0x3FF << 2);
1558                 data |= (0x8 << 2);
1559                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1560                 if (ret_val)
1561                         goto out;
1562                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1563                 if (ret_val)
1564                         goto out;
1565                 e1e_rphy(hw, HV_PM_CTRL, &data);
1566                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1567                 if (ret_val)
1568                         goto out;
1569         }
1570
1571         /* re-enable Rx path after enabling/disabling workaround */
1572         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1573
1574 out:
1575         return ret_val;
1576 }
1577
1578 /**
1579  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1580  *  done after every PHY reset.
1581  **/
1582 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1583 {
1584         s32 ret_val = 0;
1585
1586         if (hw->mac.type != e1000_pch2lan)
1587                 goto out;
1588
1589         /* Set MDIO slow mode before any other MDIO access */
1590         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1591
1592 out:
1593         return ret_val;
1594 }
1595
1596 /**
1597  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1598  *  @hw:   pointer to the HW structure
1599  *
1600  *  Workaround to set the K1 beacon duration for 82579 parts
1601  **/
1602 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1603 {
1604         s32 ret_val = 0;
1605         u16 status_reg = 0;
1606         u32 mac_reg;
1607
1608         if (hw->mac.type != e1000_pch2lan)
1609                 goto out;
1610
1611         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1612         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1613         if (ret_val)
1614                 goto out;
1615
1616         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1617             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1618                 mac_reg = er32(FEXTNVM4);
1619                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1620
1621                 if (status_reg & HV_M_STATUS_SPEED_1000)
1622                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1623                 else
1624                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1625
1626                 ew32(FEXTNVM4, mac_reg);
1627         }
1628
1629 out:
1630         return ret_val;
1631 }
1632
1633 /**
1634  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1635  *  @hw: pointer to the HW structure
1636  *
1637  *  Check the appropriate indication the MAC has finished configuring the
1638  *  PHY after a software reset.
1639  **/
1640 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1641 {
1642         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1643
1644         /* Wait for basic configuration completes before proceeding */
1645         do {
1646                 data = er32(STATUS);
1647                 data &= E1000_STATUS_LAN_INIT_DONE;
1648                 udelay(100);
1649         } while ((!data) && --loop);
1650
1651         /*
1652          * If basic configuration is incomplete before the above loop
1653          * count reaches 0, loading the configuration from NVM will
1654          * leave the PHY in a bad state possibly resulting in no link.
1655          */
1656         if (loop == 0)
1657                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1658
1659         /* Clear the Init Done bit for the next init event */
1660         data = er32(STATUS);
1661         data &= ~E1000_STATUS_LAN_INIT_DONE;
1662         ew32(STATUS, data);
1663 }
1664
1665 /**
1666  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1667  *  @hw: pointer to the HW structure
1668  **/
1669 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1670 {
1671         s32 ret_val = 0;
1672         u16 reg;
1673
1674         if (e1000_check_reset_block(hw))
1675                 goto out;
1676
1677         /* Allow time for h/w to get to quiescent state after reset */
1678         msleep(10);
1679
1680         /* Perform any necessary post-reset workarounds */
1681         switch (hw->mac.type) {
1682         case e1000_pchlan:
1683                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1684                 if (ret_val)
1685                         goto out;
1686                 break;
1687         case e1000_pch2lan:
1688                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1689                 if (ret_val)
1690                         goto out;
1691                 break;
1692         default:
1693                 break;
1694         }
1695
1696         /* Dummy read to clear the phy wakeup bit after lcd reset */
1697         if (hw->mac.type >= e1000_pchlan)
1698                 e1e_rphy(hw, BM_WUC, &reg);
1699
1700         /* Configure the LCD with the extended configuration region in NVM */
1701         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1702         if (ret_val)
1703                 goto out;
1704
1705         /* Configure the LCD with the OEM bits in NVM */
1706         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1707
1708 out:
1709         return ret_val;
1710 }
1711
1712 /**
1713  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1714  *  @hw: pointer to the HW structure
1715  *
1716  *  Resets the PHY
1717  *  This is a function pointer entry point called by drivers
1718  *  or other shared routines.
1719  **/
1720 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1721 {
1722         s32 ret_val = 0;
1723
1724         ret_val = e1000e_phy_hw_reset_generic(hw);
1725         if (ret_val)
1726                 goto out;
1727
1728         ret_val = e1000_post_phy_reset_ich8lan(hw);
1729
1730 out:
1731         return ret_val;
1732 }
1733
1734 /**
1735  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1736  *  @hw: pointer to the HW structure
1737  *  @active: true to enable LPLU, false to disable
1738  *
1739  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1740  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1741  *  the phy speed. This function will manually set the LPLU bit and restart
1742  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1743  *  since it configures the same bit.
1744  **/
1745 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1746 {
1747         s32 ret_val = 0;
1748         u16 oem_reg;
1749
1750         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1751         if (ret_val)
1752                 goto out;
1753
1754         if (active)
1755                 oem_reg |= HV_OEM_BITS_LPLU;
1756         else
1757                 oem_reg &= ~HV_OEM_BITS_LPLU;
1758
1759         oem_reg |= HV_OEM_BITS_RESTART_AN;
1760         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1761
1762 out:
1763         return ret_val;
1764 }
1765
1766 /**
1767  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1768  *  @hw: pointer to the HW structure
1769  *  @active: true to enable LPLU, false to disable
1770  *
1771  *  Sets the LPLU D0 state according to the active flag.  When
1772  *  activating LPLU this function also disables smart speed
1773  *  and vice versa.  LPLU will not be activated unless the
1774  *  device autonegotiation advertisement meets standards of
1775  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1776  *  This is a function pointer entry point only called by
1777  *  PHY setup routines.
1778  **/
1779 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1780 {
1781         struct e1000_phy_info *phy = &hw->phy;
1782         u32 phy_ctrl;
1783         s32 ret_val = 0;
1784         u16 data;
1785
1786         if (phy->type == e1000_phy_ife)
1787                 return ret_val;
1788
1789         phy_ctrl = er32(PHY_CTRL);
1790
1791         if (active) {
1792                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1793                 ew32(PHY_CTRL, phy_ctrl);
1794
1795                 if (phy->type != e1000_phy_igp_3)
1796                         return 0;
1797
1798                 /*
1799                  * Call gig speed drop workaround on LPLU before accessing
1800                  * any PHY registers
1801                  */
1802                 if (hw->mac.type == e1000_ich8lan)
1803                         e1000e_gig_downshift_workaround_ich8lan(hw);
1804
1805                 /* When LPLU is enabled, we should disable SmartSpeed */
1806                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1807                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1808                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1809                 if (ret_val)
1810                         return ret_val;
1811         } else {
1812                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1813                 ew32(PHY_CTRL, phy_ctrl);
1814
1815                 if (phy->type != e1000_phy_igp_3)
1816                         return 0;
1817
1818                 /*
1819                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1820                  * during Dx states where the power conservation is most
1821                  * important.  During driver activity we should enable
1822                  * SmartSpeed, so performance is maintained.
1823                  */
1824                 if (phy->smart_speed == e1000_smart_speed_on) {
1825                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1826                                            &data);
1827                         if (ret_val)
1828                                 return ret_val;
1829
1830                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1831                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1832                                            data);
1833                         if (ret_val)
1834                                 return ret_val;
1835                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1836                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1837                                            &data);
1838                         if (ret_val)
1839                                 return ret_val;
1840
1841                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1842                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1843                                            data);
1844                         if (ret_val)
1845                                 return ret_val;
1846                 }
1847         }
1848
1849         return 0;
1850 }
1851
1852 /**
1853  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1854  *  @hw: pointer to the HW structure
1855  *  @active: true to enable LPLU, false to disable
1856  *
1857  *  Sets the LPLU D3 state according to the active flag.  When
1858  *  activating LPLU this function also disables smart speed
1859  *  and vice versa.  LPLU will not be activated unless the
1860  *  device autonegotiation advertisement meets standards of
1861  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1862  *  This is a function pointer entry point only called by
1863  *  PHY setup routines.
1864  **/
1865 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1866 {
1867         struct e1000_phy_info *phy = &hw->phy;
1868         u32 phy_ctrl;
1869         s32 ret_val;
1870         u16 data;
1871
1872         phy_ctrl = er32(PHY_CTRL);
1873
1874         if (!active) {
1875                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1876                 ew32(PHY_CTRL, phy_ctrl);
1877
1878                 if (phy->type != e1000_phy_igp_3)
1879                         return 0;
1880
1881                 /*
1882                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1883                  * during Dx states where the power conservation is most
1884                  * important.  During driver activity we should enable
1885                  * SmartSpeed, so performance is maintained.
1886                  */
1887                 if (phy->smart_speed == e1000_smart_speed_on) {
1888                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1889                                            &data);
1890                         if (ret_val)
1891                                 return ret_val;
1892
1893                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1894                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1895                                            data);
1896                         if (ret_val)
1897                                 return ret_val;
1898                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1899                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1900                                            &data);
1901                         if (ret_val)
1902                                 return ret_val;
1903
1904                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1905                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1906                                            data);
1907                         if (ret_val)
1908                                 return ret_val;
1909                 }
1910         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1911                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1912                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1913                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1914                 ew32(PHY_CTRL, phy_ctrl);
1915
1916                 if (phy->type != e1000_phy_igp_3)
1917                         return 0;
1918
1919                 /*
1920                  * Call gig speed drop workaround on LPLU before accessing
1921                  * any PHY registers
1922                  */
1923                 if (hw->mac.type == e1000_ich8lan)
1924                         e1000e_gig_downshift_workaround_ich8lan(hw);
1925
1926                 /* When LPLU is enabled, we should disable SmartSpeed */
1927                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1928                 if (ret_val)
1929                         return ret_val;
1930
1931                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1932                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1933         }
1934
1935         return 0;
1936 }
1937
1938 /**
1939  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1940  *  @hw: pointer to the HW structure
1941  *  @bank:  pointer to the variable that returns the active bank
1942  *
1943  *  Reads signature byte from the NVM using the flash access registers.
1944  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1945  **/
1946 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1947 {
1948         u32 eecd;
1949         struct e1000_nvm_info *nvm = &hw->nvm;
1950         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1951         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1952         u8 sig_byte = 0;
1953         s32 ret_val = 0;
1954
1955         switch (hw->mac.type) {
1956         case e1000_ich8lan:
1957         case e1000_ich9lan:
1958                 eecd = er32(EECD);
1959                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1960                     E1000_EECD_SEC1VAL_VALID_MASK) {
1961                         if (eecd & E1000_EECD_SEC1VAL)
1962                                 *bank = 1;
1963                         else
1964                                 *bank = 0;
1965
1966                         return 0;
1967                 }
1968                 e_dbg("Unable to determine valid NVM bank via EEC - "
1969                        "reading flash signature\n");
1970                 /* fall-thru */
1971         default:
1972                 /* set bank to 0 in case flash read fails */
1973                 *bank = 0;
1974
1975                 /* Check bank 0 */
1976                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1977                                                         &sig_byte);
1978                 if (ret_val)
1979                         return ret_val;
1980                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1981                     E1000_ICH_NVM_SIG_VALUE) {
1982                         *bank = 0;
1983                         return 0;
1984                 }
1985
1986                 /* Check bank 1 */
1987                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1988                                                         bank1_offset,
1989                                                         &sig_byte);
1990                 if (ret_val)
1991                         return ret_val;
1992                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1993                     E1000_ICH_NVM_SIG_VALUE) {
1994                         *bank = 1;
1995                         return 0;
1996                 }
1997
1998                 e_dbg("ERROR: No valid NVM bank present\n");
1999                 return -E1000_ERR_NVM;
2000         }
2001
2002         return 0;
2003 }
2004
2005 /**
2006  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2007  *  @hw: pointer to the HW structure
2008  *  @offset: The offset (in bytes) of the word(s) to read.
2009  *  @words: Size of data to read in words
2010  *  @data: Pointer to the word(s) to read at offset.
2011  *
2012  *  Reads a word(s) from the NVM using the flash access registers.
2013  **/
2014 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2015                                   u16 *data)
2016 {
2017         struct e1000_nvm_info *nvm = &hw->nvm;
2018         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2019         u32 act_offset;
2020         s32 ret_val = 0;
2021         u32 bank = 0;
2022         u16 i, word;
2023
2024         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2025             (words == 0)) {
2026                 e_dbg("nvm parameter(s) out of bounds\n");
2027                 ret_val = -E1000_ERR_NVM;
2028                 goto out;
2029         }
2030
2031         nvm->ops.acquire(hw);
2032
2033         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2034         if (ret_val) {
2035                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2036                 bank = 0;
2037         }
2038
2039         act_offset = (bank) ? nvm->flash_bank_size : 0;
2040         act_offset += offset;
2041
2042         ret_val = 0;
2043         for (i = 0; i < words; i++) {
2044                 if ((dev_spec->shadow_ram) &&
2045                     (dev_spec->shadow_ram[offset+i].modified)) {
2046                         data[i] = dev_spec->shadow_ram[offset+i].value;
2047                 } else {
2048                         ret_val = e1000_read_flash_word_ich8lan(hw,
2049                                                                 act_offset + i,
2050                                                                 &word);
2051                         if (ret_val)
2052                                 break;
2053                         data[i] = word;
2054                 }
2055         }
2056
2057         nvm->ops.release(hw);
2058
2059 out:
2060         if (ret_val)
2061                 e_dbg("NVM read error: %d\n", ret_val);
2062
2063         return ret_val;
2064 }
2065
2066 /**
2067  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2068  *  @hw: pointer to the HW structure
2069  *
2070  *  This function does initial flash setup so that a new read/write/erase cycle
2071  *  can be started.
2072  **/
2073 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2074 {
2075         union ich8_hws_flash_status hsfsts;
2076         s32 ret_val = -E1000_ERR_NVM;
2077         s32 i = 0;
2078
2079         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2080
2081         /* Check if the flash descriptor is valid */
2082         if (hsfsts.hsf_status.fldesvalid == 0) {
2083                 e_dbg("Flash descriptor invalid.  "
2084                          "SW Sequencing must be used.\n");
2085                 return -E1000_ERR_NVM;
2086         }
2087
2088         /* Clear FCERR and DAEL in hw status by writing 1 */
2089         hsfsts.hsf_status.flcerr = 1;
2090         hsfsts.hsf_status.dael = 1;
2091
2092         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2093
2094         /*
2095          * Either we should have a hardware SPI cycle in progress
2096          * bit to check against, in order to start a new cycle or
2097          * FDONE bit should be changed in the hardware so that it
2098          * is 1 after hardware reset, which can then be used as an
2099          * indication whether a cycle is in progress or has been
2100          * completed.
2101          */
2102
2103         if (hsfsts.hsf_status.flcinprog == 0) {
2104                 /*
2105                  * There is no cycle running at present,
2106                  * so we can start a cycle.
2107                  * Begin by setting Flash Cycle Done.
2108                  */
2109                 hsfsts.hsf_status.flcdone = 1;
2110                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2111                 ret_val = 0;
2112         } else {
2113                 /*
2114                  * Otherwise poll for sometime so the current
2115                  * cycle has a chance to end before giving up.
2116                  */
2117                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2118                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2119                         if (hsfsts.hsf_status.flcinprog == 0) {
2120                                 ret_val = 0;
2121                                 break;
2122                         }
2123                         udelay(1);
2124                 }
2125                 if (ret_val == 0) {
2126                         /*
2127                          * Successful in waiting for previous cycle to timeout,
2128                          * now set the Flash Cycle Done.
2129                          */
2130                         hsfsts.hsf_status.flcdone = 1;
2131                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2132                 } else {
2133                         e_dbg("Flash controller busy, cannot get access\n");
2134                 }
2135         }
2136
2137         return ret_val;
2138 }
2139
2140 /**
2141  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2142  *  @hw: pointer to the HW structure
2143  *  @timeout: maximum time to wait for completion
2144  *
2145  *  This function starts a flash cycle and waits for its completion.
2146  **/
2147 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2148 {
2149         union ich8_hws_flash_ctrl hsflctl;
2150         union ich8_hws_flash_status hsfsts;
2151         s32 ret_val = -E1000_ERR_NVM;
2152         u32 i = 0;
2153
2154         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2155         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2156         hsflctl.hsf_ctrl.flcgo = 1;
2157         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2158
2159         /* wait till FDONE bit is set to 1 */
2160         do {
2161                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2162                 if (hsfsts.hsf_status.flcdone == 1)
2163                         break;
2164                 udelay(1);
2165         } while (i++ < timeout);
2166
2167         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2168                 return 0;
2169
2170         return ret_val;
2171 }
2172
2173 /**
2174  *  e1000_read_flash_word_ich8lan - Read word from flash
2175  *  @hw: pointer to the HW structure
2176  *  @offset: offset to data location
2177  *  @data: pointer to the location for storing the data
2178  *
2179  *  Reads the flash word at offset into data.  Offset is converted
2180  *  to bytes before read.
2181  **/
2182 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2183                                          u16 *data)
2184 {
2185         /* Must convert offset into bytes. */
2186         offset <<= 1;
2187
2188         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2189 }
2190
2191 /**
2192  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2193  *  @hw: pointer to the HW structure
2194  *  @offset: The offset of the byte to read.
2195  *  @data: Pointer to a byte to store the value read.
2196  *
2197  *  Reads a single byte from the NVM using the flash access registers.
2198  **/
2199 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2200                                          u8 *data)
2201 {
2202         s32 ret_val;
2203         u16 word = 0;
2204
2205         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2206         if (ret_val)
2207                 return ret_val;
2208
2209         *data = (u8)word;
2210
2211         return 0;
2212 }
2213
2214 /**
2215  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2216  *  @hw: pointer to the HW structure
2217  *  @offset: The offset (in bytes) of the byte or word to read.
2218  *  @size: Size of data to read, 1=byte 2=word
2219  *  @data: Pointer to the word to store the value read.
2220  *
2221  *  Reads a byte or word from the NVM using the flash access registers.
2222  **/
2223 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2224                                          u8 size, u16 *data)
2225 {
2226         union ich8_hws_flash_status hsfsts;
2227         union ich8_hws_flash_ctrl hsflctl;
2228         u32 flash_linear_addr;
2229         u32 flash_data = 0;
2230         s32 ret_val = -E1000_ERR_NVM;
2231         u8 count = 0;
2232
2233         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2234                 return -E1000_ERR_NVM;
2235
2236         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2237                             hw->nvm.flash_base_addr;
2238
2239         do {
2240                 udelay(1);
2241                 /* Steps */
2242                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2243                 if (ret_val != 0)
2244                         break;
2245
2246                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2247                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2248                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2249                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2250                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2251
2252                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2253
2254                 ret_val = e1000_flash_cycle_ich8lan(hw,
2255                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2256
2257                 /*
2258                  * Check if FCERR is set to 1, if set to 1, clear it
2259                  * and try the whole sequence a few more times, else
2260                  * read in (shift in) the Flash Data0, the order is
2261                  * least significant byte first msb to lsb
2262                  */
2263                 if (ret_val == 0) {
2264                         flash_data = er32flash(ICH_FLASH_FDATA0);
2265                         if (size == 1) {
2266                                 *data = (u8)(flash_data & 0x000000FF);
2267                         } else if (size == 2) {
2268                                 *data = (u16)(flash_data & 0x0000FFFF);
2269                         }
2270                         break;
2271                 } else {
2272                         /*
2273                          * If we've gotten here, then things are probably
2274                          * completely hosed, but if the error condition is
2275                          * detected, it won't hurt to give it another try...
2276                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2277                          */
2278                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2279                         if (hsfsts.hsf_status.flcerr == 1) {
2280                                 /* Repeat for some time before giving up. */
2281                                 continue;
2282                         } else if (hsfsts.hsf_status.flcdone == 0) {
2283                                 e_dbg("Timeout error - flash cycle "
2284                                          "did not complete.\n");
2285                                 break;
2286                         }
2287                 }
2288         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2289
2290         return ret_val;
2291 }
2292
2293 /**
2294  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2295  *  @hw: pointer to the HW structure
2296  *  @offset: The offset (in bytes) of the word(s) to write.
2297  *  @words: Size of data to write in words
2298  *  @data: Pointer to the word(s) to write at offset.
2299  *
2300  *  Writes a byte or word to the NVM using the flash access registers.
2301  **/
2302 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2303                                    u16 *data)
2304 {
2305         struct e1000_nvm_info *nvm = &hw->nvm;
2306         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2307         u16 i;
2308
2309         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2310             (words == 0)) {
2311                 e_dbg("nvm parameter(s) out of bounds\n");
2312                 return -E1000_ERR_NVM;
2313         }
2314
2315         nvm->ops.acquire(hw);
2316
2317         for (i = 0; i < words; i++) {
2318                 dev_spec->shadow_ram[offset+i].modified = true;
2319                 dev_spec->shadow_ram[offset+i].value = data[i];
2320         }
2321
2322         nvm->ops.release(hw);
2323
2324         return 0;
2325 }
2326
2327 /**
2328  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2329  *  @hw: pointer to the HW structure
2330  *
2331  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2332  *  which writes the checksum to the shadow ram.  The changes in the shadow
2333  *  ram are then committed to the EEPROM by processing each bank at a time
2334  *  checking for the modified bit and writing only the pending changes.
2335  *  After a successful commit, the shadow ram is cleared and is ready for
2336  *  future writes.
2337  **/
2338 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2339 {
2340         struct e1000_nvm_info *nvm = &hw->nvm;
2341         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2342         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2343         s32 ret_val;
2344         u16 data;
2345
2346         ret_val = e1000e_update_nvm_checksum_generic(hw);
2347         if (ret_val)
2348                 goto out;
2349
2350         if (nvm->type != e1000_nvm_flash_sw)
2351                 goto out;
2352
2353         nvm->ops.acquire(hw);
2354
2355         /*
2356          * We're writing to the opposite bank so if we're on bank 1,
2357          * write to bank 0 etc.  We also need to erase the segment that
2358          * is going to be written
2359          */
2360         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2361         if (ret_val) {
2362                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2363                 bank = 0;
2364         }
2365
2366         if (bank == 0) {
2367                 new_bank_offset = nvm->flash_bank_size;
2368                 old_bank_offset = 0;
2369                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2370                 if (ret_val)
2371                         goto release;
2372         } else {
2373                 old_bank_offset = nvm->flash_bank_size;
2374                 new_bank_offset = 0;
2375                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2376                 if (ret_val)
2377                         goto release;
2378         }
2379
2380         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2381                 /*
2382                  * Determine whether to write the value stored
2383                  * in the other NVM bank or a modified value stored
2384                  * in the shadow RAM
2385                  */
2386                 if (dev_spec->shadow_ram[i].modified) {
2387                         data = dev_spec->shadow_ram[i].value;
2388                 } else {
2389                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2390                                                                 old_bank_offset,
2391                                                                 &data);
2392                         if (ret_val)
2393                                 break;
2394                 }
2395
2396                 /*
2397                  * If the word is 0x13, then make sure the signature bits
2398                  * (15:14) are 11b until the commit has completed.
2399                  * This will allow us to write 10b which indicates the
2400                  * signature is valid.  We want to do this after the write
2401                  * has completed so that we don't mark the segment valid
2402                  * while the write is still in progress
2403                  */
2404                 if (i == E1000_ICH_NVM_SIG_WORD)
2405                         data |= E1000_ICH_NVM_SIG_MASK;
2406
2407                 /* Convert offset to bytes. */
2408                 act_offset = (i + new_bank_offset) << 1;
2409
2410                 udelay(100);
2411                 /* Write the bytes to the new bank. */
2412                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2413                                                                act_offset,
2414                                                                (u8)data);
2415                 if (ret_val)
2416                         break;
2417
2418                 udelay(100);
2419                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2420                                                           act_offset + 1,
2421                                                           (u8)(data >> 8));
2422                 if (ret_val)
2423                         break;
2424         }
2425
2426         /*
2427          * Don't bother writing the segment valid bits if sector
2428          * programming failed.
2429          */
2430         if (ret_val) {
2431                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2432                 e_dbg("Flash commit failed.\n");
2433                 goto release;
2434         }
2435
2436         /*
2437          * Finally validate the new segment by setting bit 15:14
2438          * to 10b in word 0x13 , this can be done without an
2439          * erase as well since these bits are 11 to start with
2440          * and we need to change bit 14 to 0b
2441          */
2442         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2443         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2444         if (ret_val)
2445                 goto release;
2446
2447         data &= 0xBFFF;
2448         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2449                                                        act_offset * 2 + 1,
2450                                                        (u8)(data >> 8));
2451         if (ret_val)
2452                 goto release;
2453
2454         /*
2455          * And invalidate the previously valid segment by setting
2456          * its signature word (0x13) high_byte to 0b. This can be
2457          * done without an erase because flash erase sets all bits
2458          * to 1's. We can write 1's to 0's without an erase
2459          */
2460         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2461         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2462         if (ret_val)
2463                 goto release;
2464
2465         /* Great!  Everything worked, we can now clear the cached entries. */
2466         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2467                 dev_spec->shadow_ram[i].modified = false;
2468                 dev_spec->shadow_ram[i].value = 0xFFFF;
2469         }
2470
2471 release:
2472         nvm->ops.release(hw);
2473
2474         /*
2475          * Reload the EEPROM, or else modifications will not appear
2476          * until after the next adapter reset.
2477          */
2478         if (!ret_val) {
2479                 e1000e_reload_nvm(hw);
2480                 msleep(10);
2481         }
2482
2483 out:
2484         if (ret_val)
2485                 e_dbg("NVM update error: %d\n", ret_val);
2486
2487         return ret_val;
2488 }
2489
2490 /**
2491  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2492  *  @hw: pointer to the HW structure
2493  *
2494  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2495  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2496  *  calculated, in which case we need to calculate the checksum and set bit 6.
2497  **/
2498 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2499 {
2500         s32 ret_val;
2501         u16 data;
2502
2503         /*
2504          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2505          * needs to be fixed.  This bit is an indication that the NVM
2506          * was prepared by OEM software and did not calculate the
2507          * checksum...a likely scenario.
2508          */
2509         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2510         if (ret_val)
2511                 return ret_val;
2512
2513         if ((data & 0x40) == 0) {
2514                 data |= 0x40;
2515                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2516                 if (ret_val)
2517                         return ret_val;
2518                 ret_val = e1000e_update_nvm_checksum(hw);
2519                 if (ret_val)
2520                         return ret_val;
2521         }
2522
2523         return e1000e_validate_nvm_checksum_generic(hw);
2524 }
2525
2526 /**
2527  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2528  *  @hw: pointer to the HW structure
2529  *
2530  *  To prevent malicious write/erase of the NVM, set it to be read-only
2531  *  so that the hardware ignores all write/erase cycles of the NVM via
2532  *  the flash control registers.  The shadow-ram copy of the NVM will
2533  *  still be updated, however any updates to this copy will not stick
2534  *  across driver reloads.
2535  **/
2536 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2537 {
2538         struct e1000_nvm_info *nvm = &hw->nvm;
2539         union ich8_flash_protected_range pr0;
2540         union ich8_hws_flash_status hsfsts;
2541         u32 gfpreg;
2542
2543         nvm->ops.acquire(hw);
2544
2545         gfpreg = er32flash(ICH_FLASH_GFPREG);
2546
2547         /* Write-protect GbE Sector of NVM */
2548         pr0.regval = er32flash(ICH_FLASH_PR0);
2549         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2550         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2551         pr0.range.wpe = true;
2552         ew32flash(ICH_FLASH_PR0, pr0.regval);
2553
2554         /*
2555          * Lock down a subset of GbE Flash Control Registers, e.g.
2556          * PR0 to prevent the write-protection from being lifted.
2557          * Once FLOCKDN is set, the registers protected by it cannot
2558          * be written until FLOCKDN is cleared by a hardware reset.
2559          */
2560         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2561         hsfsts.hsf_status.flockdn = true;
2562         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2563
2564         nvm->ops.release(hw);
2565 }
2566
2567 /**
2568  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2569  *  @hw: pointer to the HW structure
2570  *  @offset: The offset (in bytes) of the byte/word to read.
2571  *  @size: Size of data to read, 1=byte 2=word
2572  *  @data: The byte(s) to write to the NVM.
2573  *
2574  *  Writes one/two bytes to the NVM using the flash access registers.
2575  **/
2576 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2577                                           u8 size, u16 data)
2578 {
2579         union ich8_hws_flash_status hsfsts;
2580         union ich8_hws_flash_ctrl hsflctl;
2581         u32 flash_linear_addr;
2582         u32 flash_data = 0;
2583         s32 ret_val;
2584         u8 count = 0;
2585
2586         if (size < 1 || size > 2 || data > size * 0xff ||
2587             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2588                 return -E1000_ERR_NVM;
2589
2590         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2591                             hw->nvm.flash_base_addr;
2592
2593         do {
2594                 udelay(1);
2595                 /* Steps */
2596                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2597                 if (ret_val)
2598                         break;
2599
2600                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2601                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2602                 hsflctl.hsf_ctrl.fldbcount = size -1;
2603                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2604                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2605
2606                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2607
2608                 if (size == 1)
2609                         flash_data = (u32)data & 0x00FF;
2610                 else
2611                         flash_data = (u32)data;
2612
2613                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2614
2615                 /*
2616                  * check if FCERR is set to 1 , if set to 1, clear it
2617                  * and try the whole sequence a few more times else done
2618                  */
2619                 ret_val = e1000_flash_cycle_ich8lan(hw,
2620                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2621                 if (!ret_val)
2622                         break;
2623
2624                 /*
2625                  * If we're here, then things are most likely
2626                  * completely hosed, but if the error condition
2627                  * is detected, it won't hurt to give it another
2628                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2629                  */
2630                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2631                 if (hsfsts.hsf_status.flcerr == 1)
2632                         /* Repeat for some time before giving up. */
2633                         continue;
2634                 if (hsfsts.hsf_status.flcdone == 0) {
2635                         e_dbg("Timeout error - flash cycle "
2636                                  "did not complete.");
2637                         break;
2638                 }
2639         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2640
2641         return ret_val;
2642 }
2643
2644 /**
2645  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2646  *  @hw: pointer to the HW structure
2647  *  @offset: The index of the byte to read.
2648  *  @data: The byte to write to the NVM.
2649  *
2650  *  Writes a single byte to the NVM using the flash access registers.
2651  **/
2652 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2653                                           u8 data)
2654 {
2655         u16 word = (u16)data;
2656
2657         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2658 }
2659
2660 /**
2661  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2662  *  @hw: pointer to the HW structure
2663  *  @offset: The offset of the byte to write.
2664  *  @byte: The byte to write to the NVM.
2665  *
2666  *  Writes a single byte to the NVM using the flash access registers.
2667  *  Goes through a retry algorithm before giving up.
2668  **/
2669 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2670                                                 u32 offset, u8 byte)
2671 {
2672         s32 ret_val;
2673         u16 program_retries;
2674
2675         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2676         if (!ret_val)
2677                 return ret_val;
2678
2679         for (program_retries = 0; program_retries < 100; program_retries++) {
2680                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2681                 udelay(100);
2682                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2683                 if (!ret_val)
2684                         break;
2685         }
2686         if (program_retries == 100)
2687                 return -E1000_ERR_NVM;
2688
2689         return 0;
2690 }
2691
2692 /**
2693  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2694  *  @hw: pointer to the HW structure
2695  *  @bank: 0 for first bank, 1 for second bank, etc.
2696  *
2697  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2698  *  bank N is 4096 * N + flash_reg_addr.
2699  **/
2700 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2701 {
2702         struct e1000_nvm_info *nvm = &hw->nvm;
2703         union ich8_hws_flash_status hsfsts;
2704         union ich8_hws_flash_ctrl hsflctl;
2705         u32 flash_linear_addr;
2706         /* bank size is in 16bit words - adjust to bytes */
2707         u32 flash_bank_size = nvm->flash_bank_size * 2;
2708         s32 ret_val;
2709         s32 count = 0;
2710         s32 j, iteration, sector_size;
2711
2712         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2713
2714         /*
2715          * Determine HW Sector size: Read BERASE bits of hw flash status
2716          * register
2717          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2718          *     consecutive sectors.  The start index for the nth Hw sector
2719          *     can be calculated as = bank * 4096 + n * 256
2720          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2721          *     The start index for the nth Hw sector can be calculated
2722          *     as = bank * 4096
2723          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2724          *     (ich9 only, otherwise error condition)
2725          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2726          */
2727         switch (hsfsts.hsf_status.berasesz) {
2728         case 0:
2729                 /* Hw sector size 256 */
2730                 sector_size = ICH_FLASH_SEG_SIZE_256;
2731                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2732                 break;
2733         case 1:
2734                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2735                 iteration = 1;
2736                 break;
2737         case 2:
2738                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2739                 iteration = 1;
2740                 break;
2741         case 3:
2742                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2743                 iteration = 1;
2744                 break;
2745         default:
2746                 return -E1000_ERR_NVM;
2747         }
2748
2749         /* Start with the base address, then add the sector offset. */
2750         flash_linear_addr = hw->nvm.flash_base_addr;
2751         flash_linear_addr += (bank) ? flash_bank_size : 0;
2752
2753         for (j = 0; j < iteration ; j++) {
2754                 do {
2755                         /* Steps */
2756                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2757                         if (ret_val)
2758                                 return ret_val;
2759
2760                         /*
2761                          * Write a value 11 (block Erase) in Flash
2762                          * Cycle field in hw flash control
2763                          */
2764                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2765                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2766                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2767
2768                         /*
2769                          * Write the last 24 bits of an index within the
2770                          * block into Flash Linear address field in Flash
2771                          * Address.
2772                          */
2773                         flash_linear_addr += (j * sector_size);
2774                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2775
2776                         ret_val = e1000_flash_cycle_ich8lan(hw,
2777                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2778                         if (ret_val == 0)
2779                                 break;
2780
2781                         /*
2782                          * Check if FCERR is set to 1.  If 1,
2783                          * clear it and try the whole sequence
2784                          * a few more times else Done
2785                          */
2786                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2787                         if (hsfsts.hsf_status.flcerr == 1)
2788                                 /* repeat for some time before giving up */
2789                                 continue;
2790                         else if (hsfsts.hsf_status.flcdone == 0)
2791                                 return ret_val;
2792                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2793         }
2794
2795         return 0;
2796 }
2797
2798 /**
2799  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2800  *  @hw: pointer to the HW structure
2801  *  @data: Pointer to the LED settings
2802  *
2803  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2804  *  settings is all 0's or F's, set the LED default to a valid LED default
2805  *  setting.
2806  **/
2807 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2808 {
2809         s32 ret_val;
2810
2811         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2812         if (ret_val) {
2813                 e_dbg("NVM Read Error\n");
2814                 return ret_val;
2815         }
2816
2817         if (*data == ID_LED_RESERVED_0000 ||
2818             *data == ID_LED_RESERVED_FFFF)
2819                 *data = ID_LED_DEFAULT_ICH8LAN;
2820
2821         return 0;
2822 }
2823
2824 /**
2825  *  e1000_id_led_init_pchlan - store LED configurations
2826  *  @hw: pointer to the HW structure
2827  *
2828  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2829  *  the PHY LED configuration register.
2830  *
2831  *  PCH also does not have an "always on" or "always off" mode which
2832  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2833  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2834  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2835  *  link based on logic in e1000_led_[on|off]_pchlan().
2836  **/
2837 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2838 {
2839         struct e1000_mac_info *mac = &hw->mac;
2840         s32 ret_val;
2841         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2842         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2843         u16 data, i, temp, shift;
2844
2845         /* Get default ID LED modes */
2846         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2847         if (ret_val)
2848                 goto out;
2849
2850         mac->ledctl_default = er32(LEDCTL);
2851         mac->ledctl_mode1 = mac->ledctl_default;
2852         mac->ledctl_mode2 = mac->ledctl_default;
2853
2854         for (i = 0; i < 4; i++) {
2855                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2856                 shift = (i * 5);
2857                 switch (temp) {
2858                 case ID_LED_ON1_DEF2:
2859                 case ID_LED_ON1_ON2:
2860                 case ID_LED_ON1_OFF2:
2861                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2862                         mac->ledctl_mode1 |= (ledctl_on << shift);
2863                         break;
2864                 case ID_LED_OFF1_DEF2:
2865                 case ID_LED_OFF1_ON2:
2866                 case ID_LED_OFF1_OFF2:
2867                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2868                         mac->ledctl_mode1 |= (ledctl_off << shift);
2869                         break;
2870                 default:
2871                         /* Do nothing */
2872                         break;
2873                 }
2874                 switch (temp) {
2875                 case ID_LED_DEF1_ON2:
2876                 case ID_LED_ON1_ON2:
2877                 case ID_LED_OFF1_ON2:
2878                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2879                         mac->ledctl_mode2 |= (ledctl_on << shift);
2880                         break;
2881                 case ID_LED_DEF1_OFF2:
2882                 case ID_LED_ON1_OFF2:
2883                 case ID_LED_OFF1_OFF2:
2884                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2885                         mac->ledctl_mode2 |= (ledctl_off << shift);
2886                         break;
2887                 default:
2888                         /* Do nothing */
2889                         break;
2890                 }
2891         }
2892
2893 out:
2894         return ret_val;
2895 }
2896
2897 /**
2898  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2899  *  @hw: pointer to the HW structure
2900  *
2901  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2902  *  register, so the the bus width is hard coded.
2903  **/
2904 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2905 {
2906         struct e1000_bus_info *bus = &hw->bus;
2907         s32 ret_val;
2908
2909         ret_val = e1000e_get_bus_info_pcie(hw);
2910
2911         /*
2912          * ICH devices are "PCI Express"-ish.  They have
2913          * a configuration space, but do not contain
2914          * PCI Express Capability registers, so bus width
2915          * must be hardcoded.
2916          */
2917         if (bus->width == e1000_bus_width_unknown)
2918                 bus->width = e1000_bus_width_pcie_x1;
2919
2920         return ret_val;
2921 }
2922
2923 /**
2924  *  e1000_reset_hw_ich8lan - Reset the hardware
2925  *  @hw: pointer to the HW structure
2926  *
2927  *  Does a full reset of the hardware which includes a reset of the PHY and
2928  *  MAC.
2929  **/
2930 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2931 {
2932         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2933         u16 reg;
2934         u32 ctrl, icr, kab;
2935         s32 ret_val;
2936
2937         /*
2938          * Prevent the PCI-E bus from sticking if there is no TLP connection
2939          * on the last TLP read/write transaction when MAC is reset.
2940          */
2941         ret_val = e1000e_disable_pcie_master(hw);
2942         if (ret_val)
2943                 e_dbg("PCI-E Master disable polling has failed.\n");
2944
2945         e_dbg("Masking off all interrupts\n");
2946         ew32(IMC, 0xffffffff);
2947
2948         /*
2949          * Disable the Transmit and Receive units.  Then delay to allow
2950          * any pending transactions to complete before we hit the MAC
2951          * with the global reset.
2952          */
2953         ew32(RCTL, 0);
2954         ew32(TCTL, E1000_TCTL_PSP);
2955         e1e_flush();
2956
2957         msleep(10);
2958
2959         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2960         if (hw->mac.type == e1000_ich8lan) {
2961                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2962                 ew32(PBA, E1000_PBA_8K);
2963                 /* Set Packet Buffer Size to 16k. */
2964                 ew32(PBS, E1000_PBS_16K);
2965         }
2966
2967         if (hw->mac.type == e1000_pchlan) {
2968                 /* Save the NVM K1 bit setting*/
2969                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2970                 if (ret_val)
2971                         return ret_val;
2972
2973                 if (reg & E1000_NVM_K1_ENABLE)
2974                         dev_spec->nvm_k1_enabled = true;
2975                 else
2976                         dev_spec->nvm_k1_enabled = false;
2977         }
2978
2979         ctrl = er32(CTRL);
2980
2981         if (!e1000_check_reset_block(hw)) {
2982                 /*
2983                  * Full-chip reset requires MAC and PHY reset at the same
2984                  * time to make sure the interface between MAC and the
2985                  * external PHY is reset.
2986                  */
2987                 ctrl |= E1000_CTRL_PHY_RST;
2988         }
2989         ret_val = e1000_acquire_swflag_ich8lan(hw);
2990         e_dbg("Issuing a global reset to ich8lan\n");
2991         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2992         msleep(20);
2993
2994         if (!ret_val)
2995                 e1000_release_swflag_ich8lan(hw);
2996
2997         if (ctrl & E1000_CTRL_PHY_RST) {
2998                 ret_val = hw->phy.ops.get_cfg_done(hw);
2999                 if (ret_val)
3000                         goto out;
3001
3002                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3003                 if (ret_val)
3004                         goto out;
3005         }
3006
3007         /*
3008          * For PCH, this write will make sure that any noise
3009          * will be detected as a CRC error and be dropped rather than show up
3010          * as a bad packet to the DMA engine.
3011          */
3012         if (hw->mac.type == e1000_pchlan)
3013                 ew32(CRC_OFFSET, 0x65656565);
3014
3015         ew32(IMC, 0xffffffff);
3016         icr = er32(ICR);
3017
3018         kab = er32(KABGTXD);
3019         kab |= E1000_KABGTXD_BGSQLBIAS;
3020         ew32(KABGTXD, kab);
3021
3022 out:
3023         return ret_val;
3024 }
3025
3026 /**
3027  *  e1000_init_hw_ich8lan - Initialize the hardware
3028  *  @hw: pointer to the HW structure
3029  *
3030  *  Prepares the hardware for transmit and receive by doing the following:
3031  *   - initialize hardware bits
3032  *   - initialize LED identification
3033  *   - setup receive address registers
3034  *   - setup flow control
3035  *   - setup transmit descriptors
3036  *   - clear statistics
3037  **/
3038 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3039 {
3040         struct e1000_mac_info *mac = &hw->mac;
3041         u32 ctrl_ext, txdctl, snoop;
3042         s32 ret_val;
3043         u16 i;
3044
3045         e1000_initialize_hw_bits_ich8lan(hw);
3046
3047         /* Initialize identification LED */
3048         ret_val = mac->ops.id_led_init(hw);
3049         if (ret_val)
3050                 e_dbg("Error initializing identification LED\n");
3051                 /* This is not fatal and we should not stop init due to this */
3052
3053         /* Setup the receive address. */
3054         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3055
3056         /* Zero out the Multicast HASH table */
3057         e_dbg("Zeroing the MTA\n");
3058         for (i = 0; i < mac->mta_reg_count; i++)
3059                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3060
3061         /*
3062          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3063          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
3064          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3065          */
3066         if (hw->phy.type == e1000_phy_82578) {
3067                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
3068                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3069                 if (ret_val)
3070                         return ret_val;
3071         }
3072
3073         /* Setup link and flow control */
3074         ret_val = e1000_setup_link_ich8lan(hw);
3075
3076         /* Set the transmit descriptor write-back policy for both queues */
3077         txdctl = er32(TXDCTL(0));
3078         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3079                  E1000_TXDCTL_FULL_TX_DESC_WB;
3080         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3081                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3082         ew32(TXDCTL(0), txdctl);
3083         txdctl = er32(TXDCTL(1));
3084         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3085                  E1000_TXDCTL_FULL_TX_DESC_WB;
3086         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3087                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3088         ew32(TXDCTL(1), txdctl);
3089
3090         /*
3091          * ICH8 has opposite polarity of no_snoop bits.
3092          * By default, we should use snoop behavior.
3093          */
3094         if (mac->type == e1000_ich8lan)
3095                 snoop = PCIE_ICH8_SNOOP_ALL;
3096         else
3097                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3098         e1000e_set_pcie_no_snoop(hw, snoop);
3099
3100         ctrl_ext = er32(CTRL_EXT);
3101         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3102         ew32(CTRL_EXT, ctrl_ext);
3103
3104         /*
3105          * Clear all of the statistics registers (clear on read).  It is
3106          * important that we do this after we have tried to establish link
3107          * because the symbol error count will increment wildly if there
3108          * is no link.
3109          */
3110         e1000_clear_hw_cntrs_ich8lan(hw);
3111
3112         return 0;
3113 }
3114 /**
3115  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3116  *  @hw: pointer to the HW structure
3117  *
3118  *  Sets/Clears required hardware bits necessary for correctly setting up the
3119  *  hardware for transmit and receive.
3120  **/
3121 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3122 {
3123         u32 reg;
3124
3125         /* Extended Device Control */
3126         reg = er32(CTRL_EXT);
3127         reg |= (1 << 22);
3128         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3129         if (hw->mac.type >= e1000_pchlan)
3130                 reg |= E1000_CTRL_EXT_PHYPDEN;
3131         ew32(CTRL_EXT, reg);
3132
3133         /* Transmit Descriptor Control 0 */
3134         reg = er32(TXDCTL(0));
3135         reg |= (1 << 22);
3136         ew32(TXDCTL(0), reg);
3137
3138         /* Transmit Descriptor Control 1 */
3139         reg = er32(TXDCTL(1));
3140         reg |= (1 << 22);
3141         ew32(TXDCTL(1), reg);
3142
3143         /* Transmit Arbitration Control 0 */
3144         reg = er32(TARC(0));
3145         if (hw->mac.type == e1000_ich8lan)
3146                 reg |= (1 << 28) | (1 << 29);
3147         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3148         ew32(TARC(0), reg);
3149
3150         /* Transmit Arbitration Control 1 */
3151         reg = er32(TARC(1));
3152         if (er32(TCTL) & E1000_TCTL_MULR)
3153                 reg &= ~(1 << 28);
3154         else
3155                 reg |= (1 << 28);
3156         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3157         ew32(TARC(1), reg);
3158
3159         /* Device Status */
3160         if (hw->mac.type == e1000_ich8lan) {
3161                 reg = er32(STATUS);
3162                 reg &= ~(1 << 31);
3163                 ew32(STATUS, reg);
3164         }
3165
3166         /*
3167          * work-around descriptor data corruption issue during nfs v2 udp
3168          * traffic, just disable the nfs filtering capability
3169          */
3170         reg = er32(RFCTL);
3171         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3172         ew32(RFCTL, reg);
3173 }
3174
3175 /**
3176  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3177  *  @hw: pointer to the HW structure
3178  *
3179  *  Determines which flow control settings to use, then configures flow
3180  *  control.  Calls the appropriate media-specific link configuration
3181  *  function.  Assuming the adapter has a valid link partner, a valid link
3182  *  should be established.  Assumes the hardware has previously been reset
3183  *  and the transmitter and receiver are not enabled.
3184  **/
3185 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3186 {
3187         s32 ret_val;
3188
3189         if (e1000_check_reset_block(hw))
3190                 return 0;
3191
3192         /*
3193          * ICH parts do not have a word in the NVM to determine
3194          * the default flow control setting, so we explicitly
3195          * set it to full.
3196          */
3197         if (hw->fc.requested_mode == e1000_fc_default) {
3198                 /* Workaround h/w hang when Tx flow control enabled */
3199                 if (hw->mac.type == e1000_pchlan)
3200                         hw->fc.requested_mode = e1000_fc_rx_pause;
3201                 else
3202                         hw->fc.requested_mode = e1000_fc_full;
3203         }
3204
3205         /*
3206          * Save off the requested flow control mode for use later.  Depending
3207          * on the link partner's capabilities, we may or may not use this mode.
3208          */
3209         hw->fc.current_mode = hw->fc.requested_mode;
3210
3211         e_dbg("After fix-ups FlowControl is now = %x\n",
3212                 hw->fc.current_mode);
3213
3214         /* Continue to configure the copper link. */
3215         ret_val = e1000_setup_copper_link_ich8lan(hw);
3216         if (ret_val)
3217                 return ret_val;
3218
3219         ew32(FCTTV, hw->fc.pause_time);
3220         if ((hw->phy.type == e1000_phy_82578) ||
3221             (hw->phy.type == e1000_phy_82579) ||
3222             (hw->phy.type == e1000_phy_82577)) {
3223                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3224
3225                 ret_val = hw->phy.ops.write_reg(hw,
3226                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
3227                                              hw->fc.pause_time);
3228                 if (ret_val)
3229                         return ret_val;
3230         }
3231
3232         return e1000e_set_fc_watermarks(hw);
3233 }
3234
3235 /**
3236  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3237  *  @hw: pointer to the HW structure
3238  *
3239  *  Configures the kumeran interface to the PHY to wait the appropriate time
3240  *  when polling the PHY, then call the generic setup_copper_link to finish
3241  *  configuring the copper link.
3242  **/
3243 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3244 {
3245         u32 ctrl;
3246         s32 ret_val;
3247         u16 reg_data;
3248
3249         ctrl = er32(CTRL);
3250         ctrl |= E1000_CTRL_SLU;
3251         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3252         ew32(CTRL, ctrl);
3253
3254         /*
3255          * Set the mac to wait the maximum time between each iteration
3256          * and increase the max iterations when polling the phy;
3257          * this fixes erroneous timeouts at 10Mbps.
3258          */
3259         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3260         if (ret_val)
3261                 return ret_val;
3262         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3263                                        &reg_data);
3264         if (ret_val)
3265                 return ret_val;
3266         reg_data |= 0x3F;
3267         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3268                                         reg_data);
3269         if (ret_val)
3270                 return ret_val;
3271
3272         switch (hw->phy.type) {
3273         case e1000_phy_igp_3:
3274                 ret_val = e1000e_copper_link_setup_igp(hw);
3275                 if (ret_val)
3276                         return ret_val;
3277                 break;
3278         case e1000_phy_bm:
3279         case e1000_phy_82578:
3280                 ret_val = e1000e_copper_link_setup_m88(hw);
3281                 if (ret_val)
3282                         return ret_val;
3283                 break;
3284         case e1000_phy_82577:
3285         case e1000_phy_82579:
3286                 ret_val = e1000_copper_link_setup_82577(hw);
3287                 if (ret_val)
3288                         return ret_val;
3289                 break;
3290         case e1000_phy_ife:
3291                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3292                                                &reg_data);
3293                 if (ret_val)
3294                         return ret_val;
3295
3296                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3297
3298                 switch (hw->phy.mdix) {
3299                 case 1:
3300                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3301                         break;
3302                 case 2:
3303                         reg_data |= IFE_PMC_FORCE_MDIX;
3304                         break;
3305                 case 0:
3306                 default:
3307                         reg_data |= IFE_PMC_AUTO_MDIX;
3308                         break;
3309                 }
3310                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3311                                                 reg_data);
3312                 if (ret_val)
3313                         return ret_val;
3314                 break;
3315         default:
3316                 break;
3317         }
3318         return e1000e_setup_copper_link(hw);
3319 }
3320
3321 /**
3322  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3323  *  @hw: pointer to the HW structure
3324  *  @speed: pointer to store current link speed
3325  *  @duplex: pointer to store the current link duplex
3326  *
3327  *  Calls the generic get_speed_and_duplex to retrieve the current link
3328  *  information and then calls the Kumeran lock loss workaround for links at
3329  *  gigabit speeds.
3330  **/
3331 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3332                                           u16 *duplex)
3333 {
3334         s32 ret_val;
3335
3336         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3337         if (ret_val)
3338                 return ret_val;
3339
3340         if ((hw->mac.type == e1000_ich8lan) &&
3341             (hw->phy.type == e1000_phy_igp_3) &&
3342             (*speed == SPEED_1000)) {
3343                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3344         }
3345
3346         return ret_val;
3347 }
3348
3349 /**
3350  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3351  *  @hw: pointer to the HW structure
3352  *
3353  *  Work-around for 82566 Kumeran PCS lock loss:
3354  *  On link status change (i.e. PCI reset, speed change) and link is up and
3355  *  speed is gigabit-
3356  *    0) if workaround is optionally disabled do nothing
3357  *    1) wait 1ms for Kumeran link to come up
3358  *    2) check Kumeran Diagnostic register PCS lock loss bit
3359  *    3) if not set the link is locked (all is good), otherwise...
3360  *    4) reset the PHY
3361  *    5) repeat up to 10 times
3362  *  Note: this is only called for IGP3 copper when speed is 1gb.
3363  **/
3364 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3365 {
3366         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3367         u32 phy_ctrl;
3368         s32 ret_val;
3369         u16 i, data;
3370         bool link;
3371
3372         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3373                 return 0;
3374
3375         /*
3376          * Make sure link is up before proceeding.  If not just return.
3377          * Attempting this while link is negotiating fouled up link
3378          * stability
3379          */
3380         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3381         if (!link)
3382                 return 0;
3383
3384         for (i = 0; i < 10; i++) {
3385                 /* read once to clear */
3386                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3387                 if (ret_val)
3388                         return ret_val;
3389                 /* and again to get new status */
3390                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3391                 if (ret_val)
3392                         return ret_val;
3393
3394                 /* check for PCS lock */
3395                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3396                         return 0;
3397
3398                 /* Issue PHY reset */
3399                 e1000_phy_hw_reset(hw);
3400                 mdelay(5);
3401         }
3402         /* Disable GigE link negotiation */
3403         phy_ctrl = er32(PHY_CTRL);
3404         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3405                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3406         ew32(PHY_CTRL, phy_ctrl);
3407
3408         /*
3409          * Call gig speed drop workaround on Gig disable before accessing
3410          * any PHY registers
3411          */
3412         e1000e_gig_downshift_workaround_ich8lan(hw);
3413
3414         /* unable to acquire PCS lock */
3415         return -E1000_ERR_PHY;
3416 }
3417
3418 /**
3419  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3420  *  @hw: pointer to the HW structure
3421  *  @state: boolean value used to set the current Kumeran workaround state
3422  *
3423  *  If ICH8, set the current Kumeran workaround state (enabled - true
3424  *  /disabled - false).
3425  **/
3426 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3427                                                  bool state)
3428 {
3429         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3430
3431         if (hw->mac.type != e1000_ich8lan) {
3432                 e_dbg("Workaround applies to ICH8 only.\n");
3433                 return;
3434         }
3435
3436         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3437 }
3438
3439 /**
3440  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3441  *  @hw: pointer to the HW structure
3442  *
3443  *  Workaround for 82566 power-down on D3 entry:
3444  *    1) disable gigabit link
3445  *    2) write VR power-down enable
3446  *    3) read it back
3447  *  Continue if successful, else issue LCD reset and repeat
3448  **/
3449 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3450 {
3451         u32 reg;
3452         u16 data;
3453         u8  retry = 0;
3454
3455         if (hw->phy.type != e1000_phy_igp_3)
3456                 return;
3457
3458         /* Try the workaround twice (if needed) */
3459         do {
3460                 /* Disable link */
3461                 reg = er32(PHY_CTRL);
3462                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3463                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3464                 ew32(PHY_CTRL, reg);
3465
3466                 /*
3467                  * Call gig speed drop workaround on Gig disable before
3468                  * accessing any PHY registers
3469                  */
3470                 if (hw->mac.type == e1000_ich8lan)
3471                         e1000e_gig_downshift_workaround_ich8lan(hw);
3472
3473                 /* Write VR power-down enable */
3474                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3475                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3476                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3477
3478                 /* Read it back and test */
3479                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3480                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3481                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3482                         break;
3483
3484                 /* Issue PHY reset and repeat at most one more time */
3485                 reg = er32(CTRL);
3486                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3487                 retry++;
3488         } while (retry);
3489 }
3490
3491 /**
3492  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3493  *  @hw: pointer to the HW structure
3494  *
3495  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3496  *  LPLU, Gig disable, MDIC PHY reset):
3497  *    1) Set Kumeran Near-end loopback
3498  *    2) Clear Kumeran Near-end loopback
3499  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3500  **/
3501 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3502 {
3503         s32 ret_val;
3504         u16 reg_data;
3505
3506         if ((hw->mac.type != e1000_ich8lan) ||
3507             (hw->phy.type != e1000_phy_igp_3))
3508                 return;
3509
3510         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3511                                       &reg_data);
3512         if (ret_val)
3513                 return;
3514         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3515         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3516                                        reg_data);
3517         if (ret_val)
3518                 return;
3519         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3520         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3521                                        reg_data);
3522 }
3523
3524 /**
3525  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3526  *  @hw: pointer to the HW structure
3527  *
3528  *  During S0 to Sx transition, it is possible the link remains at gig
3529  *  instead of negotiating to a lower speed.  Before going to Sx, set
3530  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3531  *  to a lower speed.
3532  *
3533  *  Should only be called for applicable parts.
3534  **/
3535 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3536 {
3537         u32 phy_ctrl;
3538         s32 ret_val;
3539
3540         phy_ctrl = er32(PHY_CTRL);
3541         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3542         ew32(PHY_CTRL, phy_ctrl);
3543
3544         if (hw->mac.type >= e1000_pchlan) {
3545                 e1000_oem_bits_config_ich8lan(hw, true);
3546                 ret_val = hw->phy.ops.acquire(hw);
3547                 if (ret_val)
3548                         return;
3549                 e1000_write_smbus_addr(hw);
3550                 hw->phy.ops.release(hw);
3551         }
3552 }
3553
3554 /**
3555  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3556  *  @hw: pointer to the HW structure
3557  *
3558  *  Return the LED back to the default configuration.
3559  **/
3560 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3561 {
3562         if (hw->phy.type == e1000_phy_ife)
3563                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3564
3565         ew32(LEDCTL, hw->mac.ledctl_default);
3566         return 0;
3567 }
3568
3569 /**
3570  *  e1000_led_on_ich8lan - Turn LEDs on
3571  *  @hw: pointer to the HW structure
3572  *
3573  *  Turn on the LEDs.
3574  **/
3575 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3576 {
3577         if (hw->phy.type == e1000_phy_ife)
3578                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3579                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3580
3581         ew32(LEDCTL, hw->mac.ledctl_mode2);
3582         return 0;
3583 }
3584
3585 /**
3586  *  e1000_led_off_ich8lan - Turn LEDs off
3587  *  @hw: pointer to the HW structure
3588  *
3589  *  Turn off the LEDs.
3590  **/
3591 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3592 {
3593         if (hw->phy.type == e1000_phy_ife)
3594                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3595                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3596
3597         ew32(LEDCTL, hw->mac.ledctl_mode1);
3598         return 0;
3599 }
3600
3601 /**
3602  *  e1000_setup_led_pchlan - Configures SW controllable LED
3603  *  @hw: pointer to the HW structure
3604  *
3605  *  This prepares the SW controllable LED for use.
3606  **/
3607 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3608 {
3609         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3610                                         (u16)hw->mac.ledctl_mode1);
3611 }
3612
3613 /**
3614  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3615  *  @hw: pointer to the HW structure
3616  *
3617  *  Return the LED back to the default configuration.
3618  **/
3619 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3620 {
3621         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3622                                         (u16)hw->mac.ledctl_default);
3623 }
3624
3625 /**
3626  *  e1000_led_on_pchlan - Turn LEDs on
3627  *  @hw: pointer to the HW structure
3628  *
3629  *  Turn on the LEDs.
3630  **/
3631 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3632 {
3633         u16 data = (u16)hw->mac.ledctl_mode2;
3634         u32 i, led;
3635
3636         /*
3637          * If no link, then turn LED on by setting the invert bit
3638          * for each LED that's mode is "link_up" in ledctl_mode2.
3639          */
3640         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3641                 for (i = 0; i < 3; i++) {
3642                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3643                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3644                             E1000_LEDCTL_MODE_LINK_UP)
3645                                 continue;
3646                         if (led & E1000_PHY_LED0_IVRT)
3647                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3648                         else
3649                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3650                 }
3651         }
3652
3653         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3654 }
3655
3656 /**
3657  *  e1000_led_off_pchlan - Turn LEDs off
3658  *  @hw: pointer to the HW structure
3659  *
3660  *  Turn off the LEDs.
3661  **/
3662 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3663 {
3664         u16 data = (u16)hw->mac.ledctl_mode1;
3665         u32 i, led;
3666
3667         /*
3668          * If no link, then turn LED off by clearing the invert bit
3669          * for each LED that's mode is "link_up" in ledctl_mode1.
3670          */
3671         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3672                 for (i = 0; i < 3; i++) {
3673                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3674                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3675                             E1000_LEDCTL_MODE_LINK_UP)
3676                                 continue;
3677                         if (led & E1000_PHY_LED0_IVRT)
3678                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3679                         else
3680                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3681                 }
3682         }
3683
3684         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3685 }
3686
3687 /**
3688  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3689  *  @hw: pointer to the HW structure
3690  *
3691  *  Read appropriate register for the config done bit for completion status
3692  *  and configure the PHY through s/w for EEPROM-less parts.
3693  *
3694  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3695  *  config done bit, so only an error is logged and continues.  If we were
3696  *  to return with error, EEPROM-less silicon would not be able to be reset
3697  *  or change link.
3698  **/
3699 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3700 {
3701         s32 ret_val = 0;
3702         u32 bank = 0;
3703         u32 status;
3704
3705         e1000e_get_cfg_done(hw);
3706
3707         /* Wait for indication from h/w that it has completed basic config */
3708         if (hw->mac.type >= e1000_ich10lan) {
3709                 e1000_lan_init_done_ich8lan(hw);
3710         } else {
3711                 ret_val = e1000e_get_auto_rd_done(hw);
3712                 if (ret_val) {
3713                         /*
3714                          * When auto config read does not complete, do not
3715                          * return with an error. This can happen in situations
3716                          * where there is no eeprom and prevents getting link.
3717                          */
3718                         e_dbg("Auto Read Done did not complete\n");
3719                         ret_val = 0;
3720                 }
3721         }
3722
3723         /* Clear PHY Reset Asserted bit */
3724         status = er32(STATUS);
3725         if (status & E1000_STATUS_PHYRA)
3726                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3727         else
3728                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3729
3730         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3731         if (hw->mac.type <= e1000_ich9lan) {
3732                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3733                     (hw->phy.type == e1000_phy_igp_3)) {
3734                         e1000e_phy_init_script_igp3(hw);
3735                 }
3736         } else {
3737                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3738                         /* Maybe we should do a basic PHY config */
3739                         e_dbg("EEPROM not present\n");
3740                         ret_val = -E1000_ERR_CONFIG;
3741                 }
3742         }
3743
3744         return ret_val;
3745 }
3746
3747 /**
3748  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3749  * @hw: pointer to the HW structure
3750  *
3751  * In the case of a PHY power down to save power, or to turn off link during a
3752  * driver unload, or wake on lan is not enabled, remove the link.
3753  **/
3754 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3755 {
3756         /* If the management interface is not enabled, then power down */
3757         if (!(hw->mac.ops.check_mng_mode(hw) ||
3758               hw->phy.ops.check_reset_block(hw)))
3759                 e1000_power_down_phy_copper(hw);
3760 }
3761
3762 /**
3763  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3764  *  @hw: pointer to the HW structure
3765  *
3766  *  Clears hardware counters specific to the silicon family and calls
3767  *  clear_hw_cntrs_generic to clear all general purpose counters.
3768  **/
3769 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3770 {
3771         u16 phy_data;
3772
3773         e1000e_clear_hw_cntrs_base(hw);
3774
3775         er32(ALGNERRC);
3776         er32(RXERRC);
3777         er32(TNCRS);
3778         er32(CEXTERR);
3779         er32(TSCTC);
3780         er32(TSCTFC);
3781
3782         er32(MGTPRC);
3783         er32(MGTPDC);
3784         er32(MGTPTC);
3785
3786         er32(IAC);
3787         er32(ICRXOC);
3788
3789         /* Clear PHY statistics registers */
3790         if ((hw->phy.type == e1000_phy_82578) ||
3791             (hw->phy.type == e1000_phy_82579) ||
3792             (hw->phy.type == e1000_phy_82577)) {
3793                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3794                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3795                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3796                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3797                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3798                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3799                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3800                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3801                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3802                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3803                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3804                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3805                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3806                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3807         }
3808 }
3809
3810 static struct e1000_mac_operations ich8_mac_ops = {
3811         .id_led_init            = e1000e_id_led_init,
3812         /* check_mng_mode dependent on mac type */
3813         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3814         /* cleanup_led dependent on mac type */
3815         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3816         .get_bus_info           = e1000_get_bus_info_ich8lan,
3817         .set_lan_id             = e1000_set_lan_id_single_port,
3818         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3819         /* led_on dependent on mac type */
3820         /* led_off dependent on mac type */
3821         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3822         .reset_hw               = e1000_reset_hw_ich8lan,
3823         .init_hw                = e1000_init_hw_ich8lan,
3824         .setup_link             = e1000_setup_link_ich8lan,
3825         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3826         /* id_led_init dependent on mac type */
3827 };
3828
3829 static struct e1000_phy_operations ich8_phy_ops = {
3830         .acquire                = e1000_acquire_swflag_ich8lan,
3831         .check_reset_block      = e1000_check_reset_block_ich8lan,
3832         .commit                 = NULL,
3833         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3834         .get_cable_length       = e1000e_get_cable_length_igp_2,
3835         .read_reg               = e1000e_read_phy_reg_igp,
3836         .release                = e1000_release_swflag_ich8lan,
3837         .reset                  = e1000_phy_hw_reset_ich8lan,
3838         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3839         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3840         .write_reg              = e1000e_write_phy_reg_igp,
3841 };
3842
3843 static struct e1000_nvm_operations ich8_nvm_ops = {
3844         .acquire                = e1000_acquire_nvm_ich8lan,
3845         .read                   = e1000_read_nvm_ich8lan,
3846         .release                = e1000_release_nvm_ich8lan,
3847         .update                 = e1000_update_nvm_checksum_ich8lan,
3848         .valid_led_default      = e1000_valid_led_default_ich8lan,
3849         .validate               = e1000_validate_nvm_checksum_ich8lan,
3850         .write                  = e1000_write_nvm_ich8lan,
3851 };
3852
3853 struct e1000_info e1000_ich8_info = {
3854         .mac                    = e1000_ich8lan,
3855         .flags                  = FLAG_HAS_WOL
3856                                   | FLAG_IS_ICH
3857                                   | FLAG_RX_CSUM_ENABLED
3858                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3859                                   | FLAG_HAS_AMT
3860                                   | FLAG_HAS_FLASH
3861                                   | FLAG_APME_IN_WUC,
3862         .pba                    = 8,
3863         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3864         .get_variants           = e1000_get_variants_ich8lan,
3865         .mac_ops                = &ich8_mac_ops,
3866         .phy_ops                = &ich8_phy_ops,
3867         .nvm_ops                = &ich8_nvm_ops,
3868 };
3869
3870 struct e1000_info e1000_ich9_info = {
3871         .mac                    = e1000_ich9lan,
3872         .flags                  = FLAG_HAS_JUMBO_FRAMES
3873                                   | FLAG_IS_ICH
3874                                   | FLAG_HAS_WOL
3875                                   | FLAG_RX_CSUM_ENABLED
3876                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3877                                   | FLAG_HAS_AMT
3878                                   | FLAG_HAS_ERT
3879                                   | FLAG_HAS_FLASH
3880                                   | FLAG_APME_IN_WUC,
3881         .pba                    = 10,
3882         .max_hw_frame_size      = DEFAULT_JUMBO,
3883         .get_variants           = e1000_get_variants_ich8lan,
3884         .mac_ops                = &ich8_mac_ops,
3885         .phy_ops                = &ich8_phy_ops,
3886         .nvm_ops                = &ich8_nvm_ops,
3887 };
3888
3889 struct e1000_info e1000_ich10_info = {
3890         .mac                    = e1000_ich10lan,
3891         .flags                  = FLAG_HAS_JUMBO_FRAMES
3892                                   | FLAG_IS_ICH
3893                                   | FLAG_HAS_WOL
3894                                   | FLAG_RX_CSUM_ENABLED
3895                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3896                                   | FLAG_HAS_AMT
3897                                   | FLAG_HAS_ERT
3898                                   | FLAG_HAS_FLASH
3899                                   | FLAG_APME_IN_WUC,
3900         .pba                    = 10,
3901         .max_hw_frame_size      = DEFAULT_JUMBO,
3902         .get_variants           = e1000_get_variants_ich8lan,
3903         .mac_ops                = &ich8_mac_ops,
3904         .phy_ops                = &ich8_phy_ops,
3905         .nvm_ops                = &ich8_nvm_ops,
3906 };
3907
3908 struct e1000_info e1000_pch_info = {
3909         .mac                    = e1000_pchlan,
3910         .flags                  = FLAG_IS_ICH
3911                                   | FLAG_HAS_WOL
3912                                   | FLAG_RX_CSUM_ENABLED
3913                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3914                                   | FLAG_HAS_AMT
3915                                   | FLAG_HAS_FLASH
3916                                   | FLAG_HAS_JUMBO_FRAMES
3917                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3918                                   | FLAG_APME_IN_WUC,
3919         .flags2                 = FLAG2_HAS_PHY_STATS,
3920         .pba                    = 26,
3921         .max_hw_frame_size      = 4096,
3922         .get_variants           = e1000_get_variants_ich8lan,
3923         .mac_ops                = &ich8_mac_ops,
3924         .phy_ops                = &ich8_phy_ops,
3925         .nvm_ops                = &ich8_nvm_ops,
3926 };
3927
3928 struct e1000_info e1000_pch2_info = {
3929         .mac                    = e1000_pch2lan,
3930         .flags                  = FLAG_IS_ICH
3931                                   | FLAG_HAS_WOL
3932                                   | FLAG_RX_CSUM_ENABLED
3933                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3934                                   | FLAG_HAS_AMT
3935                                   | FLAG_HAS_FLASH
3936                                   | FLAG_HAS_JUMBO_FRAMES
3937                                   | FLAG_APME_IN_WUC,
3938         .flags2                 = FLAG2_HAS_PHY_STATS
3939                                   | FLAG2_HAS_EEE,
3940         .pba                    = 18,
3941         .max_hw_frame_size      = DEFAULT_JUMBO,
3942         .get_variants           = e1000_get_variants_ich8lan,
3943         .mac_ops                = &ich8_mac_ops,
3944         .phy_ops                = &ich8_phy_ops,
3945         .nvm_ops                = &ich8_nvm_ops,
3946 };