drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 142
 143 /* Strapping Option Register - RO */
 144 #define E1000_STRAP                     0x0000C
 145 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 146 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 147
 148 /* OEM Bits Phy Register */
 149 #define HV_OEM_BITS            PHY_REG(768, 25)
 150 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 151 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 152 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 153
 154 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 155 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 156
 157 /* KMRN Mode Control */
 158 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 159 #define HV_KMRN_MDIO_SLOW      0x0400
 160
 161 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 162 /* Offset 04h HSFSTS */
 163 union ich8_hws_flash_status {
 164         struct ich8_hsfsts {
 165                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 166                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 167                 u16 dael       :1; /* bit 2 Direct Access error Log */
 168                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 169                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 170                 u16 reserved1  :2; /* bit 13:6 Reserved */
 171                 u16 reserved2  :6; /* bit 13:6 Reserved */
 172                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 173                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 174         } hsf_status;
 175         u16 regval;
 176 };
 177
 178 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 179 /* Offset 06h FLCTL */
 180 union ich8_hws_flash_ctrl {
 181         struct ich8_hsflctl {
 182                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 183                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 184                 u16 reserved   :5;   /* 7:3 Reserved  */
 185                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 186                 u16 flockdn    :6;   /* 15:10 Reserved */
 187         } hsf_ctrl;
 188         u16 regval;
 189 };
 190
 191 /* ICH Flash Region Access Permissions */
 192 union ich8_hws_flash_regacc {
 193         struct ich8_flracc {
 194                 u32 grra      :8; /* 0:7 GbE region Read Access */
 195                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 196                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 197                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 198         } hsf_flregacc;
 199         u16 regval;
 200 };
 201
 202 /* ICH Flash Protected Region */
 203 union ich8_flash_protected_range {
 204         struct ich8_pr {
 205                 u32 base:13;     /* 0:12 Protected Range Base */
 206                 u32 reserved1:2; /* 13:14 Reserved */
 207                 u32 rpe:1;       /* 15 Read Protection Enable */
 208                 u32 limit:13;    /* 16:28 Protected Range Limit */
 209                 u32 reserved2:2; /* 29:30 Reserved */
 210                 u32 wpe:1;       /* 31 Write Protection Enable */
 211         } range;
 212         u32 regval;
 213 };
 214
 215 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 216 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 217 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 218 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 219 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 220                                                 u32 offset, u8 byte);
 221 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 222                                          u8 *data);
 223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 224                                          u16 *data);
 225 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 226                                          u8 size, u16 *data);
 227 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 228 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 229 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 230 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 231 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 232 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 233 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 234 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 235 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 236 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 237 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 238 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 239 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 240 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 241 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 242 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 243 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 244 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 245 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 246
 247 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 248 {
 249         return readw(hw->flash_address + reg);
 250 }
 251
 252 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 253 {
 254         return readl(hw->flash_address + reg);
 255 }
 256
 257 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 258 {
 259         writew(val, hw->flash_address + reg);
 260 }
 261
 262 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 263 {
 264         writel(val, hw->flash_address + reg);
 265 }
 266
 267 #define er16flash(reg)          __er16flash(hw, (reg))
 268 #define er32flash(reg)          __er32flash(hw, (reg))
 269 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 270 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 271
 272 /**
 273  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 274  *  @hw: pointer to the HW structure
 275  *
 276  *  Initialize family-specific PHY parameters and function pointers.
 277  **/
 278 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 279 {
 280         struct e1000_phy_info *phy = &hw->phy;
 281         u32 ctrl;
 282         s32 ret_val = 0;
 283
 284         phy->addr                     = 1;
 285         phy->reset_delay_us           = 100;
 286
 287         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 288         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 289         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 290         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 291         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 292         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 293         phy->ops.power_up             = e1000_power_up_phy_copper;
 294         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 295         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 296
 297         /*
 298          * The MAC-PHY interconnect may still be in SMBus mode
 299          * after Sx->S0.  If the manageability engine (ME) is
 300          * disabled, then toggle the LANPHYPC Value bit to force
 301          * the interconnect to PCIe mode.
 302          */
 303         if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 304                 ctrl = er32(CTRL);
 305                 ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
 306                 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 307                 ew32(CTRL, ctrl);
 308                 udelay(10);
 309                 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 310                 ew32(CTRL, ctrl);
 311                 msleep(50);
 312         }
 313
 314         /*
 315          * Reset the PHY before any acccess to it.  Doing so, ensures that
 316          * the PHY is in a known good state before we read/write PHY registers.
 317          * The generic reset is sufficient here, because we haven't determined
 318          * the PHY type yet.
 319          */
 320         ret_val = e1000e_phy_hw_reset_generic(hw);
 321         if (ret_val)
 322                 goto out;
 323
 324         phy->id = e1000_phy_unknown;
 325         ret_val = e1000e_get_phy_id(hw);
 326         if (ret_val)
 327                 goto out;
 328         if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
 329                 /*
 330                  * In case the PHY needs to be in mdio slow mode (eg. 82577),
 331                  * set slow mode and try to get the PHY id again.
 332                  */
 333                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 334                 if (ret_val)
 335                         goto out;
 336                 ret_val = e1000e_get_phy_id(hw);
 337                 if (ret_val)
 338                         goto out;
 339         }
 340         phy->type = e1000e_get_phy_type_from_id(phy->id);
 341
 342         switch (phy->type) {
 343         case e1000_phy_82577:
 344         case e1000_phy_82579:
 345                 phy->ops.check_polarity = e1000_check_polarity_82577;
 346                 phy->ops.force_speed_duplex =
 347                         e1000_phy_force_speed_duplex_82577;
 348                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 349                 phy->ops.get_info = e1000_get_phy_info_82577;
 350                 phy->ops.commit = e1000e_phy_sw_reset;
 351                 break;
 352         case e1000_phy_82578:
 353                 phy->ops.check_polarity = e1000_check_polarity_m88;
 354                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 355                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 356                 phy->ops.get_info = e1000e_get_phy_info_m88;
 357                 break;
 358         default:
 359                 ret_val = -E1000_ERR_PHY;
 360                 break;
 361         }
 362
 363 out:
 364         return ret_val;
 365 }
 366
 367 /**
 368  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 369  *  @hw: pointer to the HW structure
 370  *
 371  *  Initialize family-specific PHY parameters and function pointers.
 372  **/
 373 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 374 {
 375         struct e1000_phy_info *phy = &hw->phy;
 376         s32 ret_val;
 377         u16 i = 0;
 378
 379         phy->addr                       = 1;
 380         phy->reset_delay_us             = 100;
 381
 382         phy->ops.power_up               = e1000_power_up_phy_copper;
 383         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 384
 385         /*
 386          * We may need to do this twice - once for IGP and if that fails,
 387          * we'll set BM func pointers and try again
 388          */
 389         ret_val = e1000e_determine_phy_address(hw);
 390         if (ret_val) {
 391                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 392                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 393                 ret_val = e1000e_determine_phy_address(hw);
 394                 if (ret_val) {
 395                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 396                         return ret_val;
 397                 }
 398         }
 399
 400         phy->id = 0;
 401         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 402                (i++ < 100)) {
 403                 msleep(1);
 404                 ret_val = e1000e_get_phy_id(hw);
 405                 if (ret_val)
 406                         return ret_val;
 407         }
 408
 409         /* Verify phy id */
 410         switch (phy->id) {
 411         case IGP03E1000_E_PHY_ID:
 412                 phy->type = e1000_phy_igp_3;
 413                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 414                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 415                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 416                 phy->ops.get_info = e1000e_get_phy_info_igp;
 417                 phy->ops.check_polarity = e1000_check_polarity_igp;
 418                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 419                 break;
 420         case IFE_E_PHY_ID:
 421         case IFE_PLUS_E_PHY_ID:
 422         case IFE_C_E_PHY_ID:
 423                 phy->type = e1000_phy_ife;
 424                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 425                 phy->ops.get_info = e1000_get_phy_info_ife;
 426                 phy->ops.check_polarity = e1000_check_polarity_ife;
 427                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 428                 break;
 429         case BME1000_E_PHY_ID:
 430                 phy->type = e1000_phy_bm;
 431                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 432                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 433                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 434                 phy->ops.commit = e1000e_phy_sw_reset;
 435                 phy->ops.get_info = e1000e_get_phy_info_m88;
 436                 phy->ops.check_polarity = e1000_check_polarity_m88;
 437                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 438                 break;
 439         default:
 440                 return -E1000_ERR_PHY;
 441                 break;
 442         }
 443
 444         return 0;
 445 }
 446
 447 /**
 448  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 449  *  @hw: pointer to the HW structure
 450  *
 451  *  Initialize family-specific NVM parameters and function
 452  *  pointers.
 453  **/
 454 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 455 {
 456         struct e1000_nvm_info *nvm = &hw->nvm;
 457         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 458         u32 gfpreg, sector_base_addr, sector_end_addr;
 459         u16 i;
 460
 461         /* Can't read flash registers if the register set isn't mapped. */
 462         if (!hw->flash_address) {
 463                 e_dbg("ERROR: Flash registers not mapped\n");
 464                 return -E1000_ERR_CONFIG;
 465         }
 466
 467         nvm->type = e1000_nvm_flash_sw;
 468
 469         gfpreg = er32flash(ICH_FLASH_GFPREG);
 470
 471         /*
 472          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 473          * Add 1 to sector_end_addr since this sector is included in
 474          * the overall size.
 475          */
 476         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 477         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 478
 479         /* flash_base_addr is byte-aligned */
 480         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 481
 482         /*
 483          * find total size of the NVM, then cut in half since the total
 484          * size represents two separate NVM banks.
 485          */
 486         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 487                                 << FLASH_SECTOR_ADDR_SHIFT;
 488         nvm->flash_bank_size /= 2;
 489         /* Adjust to word count */
 490         nvm->flash_bank_size /= sizeof(u16);
 491
 492         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 493
 494         /* Clear shadow ram */
 495         for (i = 0; i < nvm->word_size; i++) {
 496                 dev_spec->shadow_ram[i].modified = false;
 497                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 498         }
 499
 500         return 0;
 501 }
 502
 503 /**
 504  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 505  *  @hw: pointer to the HW structure
 506  *
 507  *  Initialize family-specific MAC parameters and function
 508  *  pointers.
 509  **/
 510 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 511 {
 512         struct e1000_hw *hw = &adapter->hw;
 513         struct e1000_mac_info *mac = &hw->mac;
 514
 515         /* Set media type function pointer */
 516         hw->phy.media_type = e1000_media_type_copper;
 517
 518         /* Set mta register count */
 519         mac->mta_reg_count = 32;
 520         /* Set rar entry count */
 521         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 522         if (mac->type == e1000_ich8lan)
 523                 mac->rar_entry_count--;
 524         /* FWSM register */
 525         mac->has_fwsm = true;
 526         /* ARC subsystem not supported */
 527         mac->arc_subsystem_valid = false;
 528         /* Adaptive IFS supported */
 529         mac->adaptive_ifs = true;
 530
 531         /* LED operations */
 532         switch (mac->type) {
 533         case e1000_ich8lan:
 534         case e1000_ich9lan:
 535         case e1000_ich10lan:
 536                 /* check management mode */
 537                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 538                 /* ID LED init */
 539                 mac->ops.id_led_init = e1000e_id_led_init;
 540                 /* setup LED */
 541                 mac->ops.setup_led = e1000e_setup_led_generic;
 542                 /* cleanup LED */
 543                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 544                 /* turn on/off LED */
 545                 mac->ops.led_on = e1000_led_on_ich8lan;
 546                 mac->ops.led_off = e1000_led_off_ich8lan;
 547                 break;
 548         case e1000_pchlan:
 549         case e1000_pch2lan:
 550                 /* check management mode */
 551                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 552                 /* ID LED init */
 553                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 554                 /* setup LED */
 555                 mac->ops.setup_led = e1000_setup_led_pchlan;
 556                 /* cleanup LED */
 557                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 558                 /* turn on/off LED */
 559                 mac->ops.led_on = e1000_led_on_pchlan;
 560                 mac->ops.led_off = e1000_led_off_pchlan;
 561                 break;
 562         default:
 563                 break;
 564         }
 565
 566         /* Enable PCS Lock-loss workaround for ICH8 */
 567         if (mac->type == e1000_ich8lan)
 568                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 569
 570         /* Disable PHY configuration by hardware, config by software */
 571         if (mac->type == e1000_pch2lan) {
 572                 u32 extcnf_ctrl = er32(EXTCNF_CTRL);
 573
 574                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
 575                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 576         }
 577
 578         return 0;
 579 }
 580
 581 /**
 582  *  e1000_set_eee_pchlan - Enable/disable EEE support
 583  *  @hw: pointer to the HW structure
 584  *
 585  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 586  *  the LPI Control register will remain set only if/when link is up.
 587  **/
 588 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 589 {
 590         s32 ret_val = 0;
 591         u16 phy_reg;
 592
 593         if (hw->phy.type != e1000_phy_82579)
 594                 goto out;
 595
 596         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 597         if (ret_val)
 598                 goto out;
 599
 600         if (hw->dev_spec.ich8lan.eee_disable)
 601                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 602         else
 603                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 604
 605         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 606 out:
 607         return ret_val;
 608 }
 609
 610 /**
 611  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 612  *  @hw: pointer to the HW structure
 613  *
 614  *  Checks to see of the link status of the hardware has changed.  If a
 615  *  change in link status has been detected, then we read the PHY registers
 616  *  to get the current speed/duplex if link exists.
 617  **/
 618 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 619 {
 620         struct e1000_mac_info *mac = &hw->mac;
 621         s32 ret_val;
 622         bool link;
 623
 624         /*
 625          * We only want to go out to the PHY registers to see if Auto-Neg
 626          * has completed and/or if our link status has changed.  The
 627          * get_link_status flag is set upon receiving a Link Status
 628          * Change or Rx Sequence Error interrupt.
 629          */
 630         if (!mac->get_link_status) {
 631                 ret_val = 0;
 632                 goto out;
 633         }
 634
 635         /*
 636          * First we want to see if the MII Status Register reports
 637          * link.  If so, then we want to get the current speed/duplex
 638          * of the PHY.
 639          */
 640         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 641         if (ret_val)
 642                 goto out;
 643
 644         if (hw->mac.type == e1000_pchlan) {
 645                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 646                 if (ret_val)
 647                         goto out;
 648         }
 649
 650         if (!link)
 651                 goto out; /* No link detected */
 652
 653         mac->get_link_status = false;
 654
 655         if (hw->phy.type == e1000_phy_82578) {
 656                 ret_val = e1000_link_stall_workaround_hv(hw);
 657                 if (ret_val)
 658                         goto out;
 659         }
 660
 661         if (hw->mac.type == e1000_pch2lan) {
 662                 ret_val = e1000_k1_workaround_lv(hw);
 663                 if (ret_val)
 664                         goto out;
 665         }
 666
 667         /*
 668          * Check if there was DownShift, must be checked
 669          * immediately after link-up
 670          */
 671         e1000e_check_downshift(hw);
 672
 673         /* Enable/Disable EEE after link up */
 674         ret_val = e1000_set_eee_pchlan(hw);
 675         if (ret_val)
 676                 goto out;
 677
 678         /*
 679          * If we are forcing speed/duplex, then we simply return since
 680          * we have already determined whether we have link or not.
 681          */
 682         if (!mac->autoneg) {
 683                 ret_val = -E1000_ERR_CONFIG;
 684                 goto out;
 685         }
 686
 687         /*
 688          * Auto-Neg is enabled.  Auto Speed Detection takes care
 689          * of MAC speed/duplex configuration.  So we only need to
 690          * configure Collision Distance in the MAC.
 691          */
 692         e1000e_config_collision_dist(hw);
 693
 694         /*
 695          * Configure Flow Control now that Auto-Neg has completed.
 696          * First, we need to restore the desired flow control
 697          * settings because we may have had to re-autoneg with a
 698          * different link partner.
 699          */
 700         ret_val = e1000e_config_fc_after_link_up(hw);
 701         if (ret_val)
 702                 e_dbg("Error configuring flow control\n");
 703
 704 out:
 705         return ret_val;
 706 }
 707
 708 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 709 {
 710         struct e1000_hw *hw = &adapter->hw;
 711         s32 rc;
 712
 713         rc = e1000_init_mac_params_ich8lan(adapter);
 714         if (rc)
 715                 return rc;
 716
 717         rc = e1000_init_nvm_params_ich8lan(hw);
 718         if (rc)
 719                 return rc;
 720
 721         switch (hw->mac.type) {
 722         case e1000_ich8lan:
 723         case e1000_ich9lan:
 724         case e1000_ich10lan:
 725                 rc = e1000_init_phy_params_ich8lan(hw);
 726                 break;
 727         case e1000_pchlan:
 728         case e1000_pch2lan:
 729                 rc = e1000_init_phy_params_pchlan(hw);
 730                 break;
 731         default:
 732                 break;
 733         }
 734         if (rc)
 735                 return rc;
 736
 737         if (adapter->hw.phy.type == e1000_phy_ife) {
 738                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 739                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 740         }
 741
 742         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 743             (adapter->hw.phy.type == e1000_phy_igp_3))
 744                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 745
 746         /* Disable EEE by default until IEEE802.3az spec is finalized */
 747         if (adapter->flags2 & FLAG2_HAS_EEE)
 748                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 749
 750         return 0;
 751 }
 752
 753 static DEFINE_MUTEX(nvm_mutex);
 754
 755 /**
 756  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 757  *  @hw: pointer to the HW structure
 758  *
 759  *  Acquires the mutex for performing NVM operations.
 760  **/
 761 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 762 {
 763         mutex_lock(&nvm_mutex);
 764
 765         return 0;
 766 }
 767
 768 /**
 769  *  e1000_release_nvm_ich8lan - Release NVM mutex
 770  *  @hw: pointer to the HW structure
 771  *
 772  *  Releases the mutex used while performing NVM operations.
 773  **/
 774 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 775 {
 776         mutex_unlock(&nvm_mutex);
 777 }
 778
 779 static DEFINE_MUTEX(swflag_mutex);
 780
 781 /**
 782  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 783  *  @hw: pointer to the HW structure
 784  *
 785  *  Acquires the software control flag for performing PHY and select
 786  *  MAC CSR accesses.
 787  **/
 788 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 789 {
 790         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 791         s32 ret_val = 0;
 792
 793         mutex_lock(&swflag_mutex);
 794
 795         while (timeout) {
 796                 extcnf_ctrl = er32(EXTCNF_CTRL);
 797                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 798                         break;
 799
 800                 mdelay(1);
 801                 timeout--;
 802         }
 803
 804         if (!timeout) {
 805                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 806                 ret_val = -E1000_ERR_CONFIG;
 807                 goto out;
 808         }
 809
 810         timeout = SW_FLAG_TIMEOUT;
 811
 812         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 813         ew32(EXTCNF_CTRL, extcnf_ctrl);
 814
 815         while (timeout) {
 816                 extcnf_ctrl = er32(EXTCNF_CTRL);
 817                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 818                         break;
 819
 820                 mdelay(1);
 821                 timeout--;
 822         }
 823
 824         if (!timeout) {
 825                 e_dbg("Failed to acquire the semaphore.\n");
 826                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 827                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 828                 ret_val = -E1000_ERR_CONFIG;
 829                 goto out;
 830         }
 831
 832 out:
 833         if (ret_val)
 834                 mutex_unlock(&swflag_mutex);
 835
 836         return ret_val;
 837 }
 838
 839 /**
 840  *  e1000_release_swflag_ich8lan - Release software control flag
 841  *  @hw: pointer to the HW structure
 842  *
 843  *  Releases the software control flag for performing PHY and select
 844  *  MAC CSR accesses.
 845  **/
 846 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 847 {
 848         u32 extcnf_ctrl;
 849
 850         extcnf_ctrl = er32(EXTCNF_CTRL);
 851         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 852         ew32(EXTCNF_CTRL, extcnf_ctrl);
 853
 854         mutex_unlock(&swflag_mutex);
 855 }
 856
 857 /**
 858  *  e1000_check_mng_mode_ich8lan - Checks management mode
 859  *  @hw: pointer to the HW structure
 860  *
 861  *  This checks if the adapter has any manageability enabled.
 862  *  This is a function pointer entry point only called by read/write
 863  *  routines for the PHY and NVM parts.
 864  **/
 865 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 866 {
 867         u32 fwsm;
 868
 869         fwsm = er32(FWSM);
 870         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 871                ((fwsm & E1000_FWSM_MODE_MASK) ==
 872                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 873 }
 874
 875 /**
 876  *  e1000_check_mng_mode_pchlan - Checks management mode
 877  *  @hw: pointer to the HW structure
 878  *
 879  *  This checks if the adapter has iAMT enabled.
 880  *  This is a function pointer entry point only called by read/write
 881  *  routines for the PHY and NVM parts.
 882  **/
 883 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 884 {
 885         u32 fwsm;
 886
 887         fwsm = er32(FWSM);
 888         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 889                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 890 }
 891
 892 /**
 893  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 894  *  @hw: pointer to the HW structure
 895  *
 896  *  Checks if firmware is blocking the reset of the PHY.
 897  *  This is a function pointer entry point only called by
 898  *  reset routines.
 899  **/
 900 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 901 {
 902         u32 fwsm;
 903
 904         fwsm = er32(FWSM);
 905
 906         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 907 }
 908
 909 /**
 910  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 911  *  @hw: pointer to the HW structure
 912  *
 913  *  Assumes semaphore already acquired.
 914  *
 915  **/
 916 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 917 {
 918         u16 phy_data;
 919         u32 strap = er32(STRAP);
 920         s32 ret_val = 0;
 921
 922         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 923
 924         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
 925         if (ret_val)
 926                 goto out;
 927
 928         phy_data &= ~HV_SMB_ADDR_MASK;
 929         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
 930         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 931         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
 932
 933 out:
 934         return ret_val;
 935 }
 936
 937 /**
 938  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 939  *  @hw:   pointer to the HW structure
 940  *
 941  *  SW should configure the LCD from the NVM extended configuration region
 942  *  as a workaround for certain parts.
 943  **/
 944 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 945 {
 946         struct e1000_phy_info *phy = &hw->phy;
 947         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 948         s32 ret_val = 0;
 949         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 950
 951         /*
 952          * Initialize the PHY from the NVM on ICH platforms.  This
 953          * is needed due to an issue where the NVM configuration is
 954          * not properly autoloaded after power transitions.
 955          * Therefore, after each PHY reset, we will load the
 956          * configuration data out of the NVM manually.
 957          */
 958         switch (hw->mac.type) {
 959         case e1000_ich8lan:
 960                 if (phy->type != e1000_phy_igp_3)
 961                         return ret_val;
 962
 963                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
 964                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
 965                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 966                         break;
 967                 }
 968                 /* Fall-thru */
 969         case e1000_pchlan:
 970         case e1000_pch2lan:
 971                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 972                 break;
 973         default:
 974                 return ret_val;
 975         }
 976
 977         ret_val = hw->phy.ops.acquire(hw);
 978         if (ret_val)
 979                 return ret_val;
 980
 981         data = er32(FEXTNVM);
 982         if (!(data & sw_cfg_mask))
 983                 goto out;
 984
 985         /*
 986          * Make sure HW does not configure LCD from PHY
 987          * extended configuration before SW configuration
 988          */
 989         data = er32(EXTCNF_CTRL);
 990         if (!(hw->mac.type == e1000_pch2lan)) {
 991                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 992                         goto out;
 993         }
 994
 995         cnf_size = er32(EXTCNF_SIZE);
 996         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 997         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 998         if (!cnf_size)
 999                 goto out;
1000
1001         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1002         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1003
1004         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1005             (hw->mac.type == e1000_pchlan)) ||
1006              (hw->mac.type == e1000_pch2lan)) {
1007                 /*
1008                  * HW configures the SMBus address and LEDs when the
1009                  * OEM and LCD Write Enable bits are set in the NVM.
1010                  * When both NVM bits are cleared, SW will configure
1011                  * them instead.
1012                  */
1013                 ret_val = e1000_write_smbus_addr(hw);
1014                 if (ret_val)
1015                         goto out;
1016
1017                 data = er32(LEDCTL);
1018                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1019                                                         (u16)data);
1020                 if (ret_val)
1021                         goto out;
1022         }
1023
1024         /* Configure LCD from extended configuration region. */
1025
1026         /* cnf_base_addr is in DWORD */
1027         word_addr = (u16)(cnf_base_addr << 1);
1028
1029         for (i = 0; i < cnf_size; i++) {
1030                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1031                                          &reg_data);
1032                 if (ret_val)
1033                         goto out;
1034
1035                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1036                                          1, &reg_addr);
1037                 if (ret_val)
1038                         goto out;
1039
1040                 /* Save off the PHY page for future writes. */
1041                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1042                         phy_page = reg_data;
1043                         continue;
1044                 }
1045
1046                 reg_addr &= PHY_REG_MASK;
1047                 reg_addr |= phy_page;
1048
1049                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1050                                                     reg_data);
1051                 if (ret_val)
1052                         goto out;
1053         }
1054
1055 out:
1056         hw->phy.ops.release(hw);
1057         return ret_val;
1058 }
1059
1060 /**
1061  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1062  *  @hw:   pointer to the HW structure
1063  *  @link: link up bool flag
1064  *
1065  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1066  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1067  *  If link is down, the function will restore the default K1 setting located
1068  *  in the NVM.
1069  **/
1070 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1071 {
1072         s32 ret_val = 0;
1073         u16 status_reg = 0;
1074         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1075
1076         if (hw->mac.type != e1000_pchlan)
1077                 goto out;
1078
1079         /* Wrap the whole flow with the sw flag */
1080         ret_val = hw->phy.ops.acquire(hw);
1081         if (ret_val)
1082                 goto out;
1083
1084         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1085         if (link) {
1086                 if (hw->phy.type == e1000_phy_82578) {
1087                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1088                                                                   &status_reg);
1089                         if (ret_val)
1090                                 goto release;
1091
1092                         status_reg &= BM_CS_STATUS_LINK_UP |
1093                                       BM_CS_STATUS_RESOLVED |
1094                                       BM_CS_STATUS_SPEED_MASK;
1095
1096                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1097                                            BM_CS_STATUS_RESOLVED |
1098                                            BM_CS_STATUS_SPEED_1000))
1099                                 k1_enable = false;
1100                 }
1101
1102                 if (hw->phy.type == e1000_phy_82577) {
1103                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1104                                                                   &status_reg);
1105                         if (ret_val)
1106                                 goto release;
1107
1108                         status_reg &= HV_M_STATUS_LINK_UP |
1109                                       HV_M_STATUS_AUTONEG_COMPLETE |
1110                                       HV_M_STATUS_SPEED_MASK;
1111
1112                         if (status_reg == (HV_M_STATUS_LINK_UP |
1113                                            HV_M_STATUS_AUTONEG_COMPLETE |
1114                                            HV_M_STATUS_SPEED_1000))
1115                                 k1_enable = false;
1116                 }
1117
1118                 /* Link stall fix for link up */
1119                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1120                                                            0x0100);
1121                 if (ret_val)
1122                         goto release;
1123
1124         } else {
1125                 /* Link stall fix for link down */
1126                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1127                                                            0x4100);
1128                 if (ret_val)
1129                         goto release;
1130         }
1131
1132         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1133
1134 release:
1135         hw->phy.ops.release(hw);
1136 out:
1137         return ret_val;
1138 }
1139
1140 /**
1141  *  e1000_configure_k1_ich8lan - Configure K1 power state
1142  *  @hw: pointer to the HW structure
1143  *  @enable: K1 state to configure
1144  *
1145  *  Configure the K1 power state based on the provided parameter.
1146  *  Assumes semaphore already acquired.
1147  *
1148  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1149  **/
1150 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1151 {
1152         s32 ret_val = 0;
1153         u32 ctrl_reg = 0;
1154         u32 ctrl_ext = 0;
1155         u32 reg = 0;
1156         u16 kmrn_reg = 0;
1157
1158         ret_val = e1000e_read_kmrn_reg_locked(hw,
1159                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1160                                              &kmrn_reg);
1161         if (ret_val)
1162                 goto out;
1163
1164         if (k1_enable)
1165                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1166         else
1167                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1168
1169         ret_val = e1000e_write_kmrn_reg_locked(hw,
1170                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1171                                               kmrn_reg);
1172         if (ret_val)
1173                 goto out;
1174
1175         udelay(20);
1176         ctrl_ext = er32(CTRL_EXT);
1177         ctrl_reg = er32(CTRL);
1178
1179         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1180         reg |= E1000_CTRL_FRCSPD;
1181         ew32(CTRL, reg);
1182
1183         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1184         udelay(20);
1185         ew32(CTRL, ctrl_reg);
1186         ew32(CTRL_EXT, ctrl_ext);
1187         udelay(20);
1188
1189 out:
1190         return ret_val;
1191 }
1192
1193 /**
1194  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1195  *  @hw:       pointer to the HW structure
1196  *  @d0_state: boolean if entering d0 or d3 device state
1197  *
1198  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1199  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1200  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1201  **/
1202 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1203 {
1204         s32 ret_val = 0;
1205         u32 mac_reg;
1206         u16 oem_reg;
1207
1208         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1209                 return ret_val;
1210
1211         ret_val = hw->phy.ops.acquire(hw);
1212         if (ret_val)
1213                 return ret_val;
1214
1215         if (!(hw->mac.type == e1000_pch2lan)) {
1216                 mac_reg = er32(EXTCNF_CTRL);
1217                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1218                         goto out;
1219         }
1220
1221         mac_reg = er32(FEXTNVM);
1222         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1223                 goto out;
1224
1225         mac_reg = er32(PHY_CTRL);
1226
1227         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1228         if (ret_val)
1229                 goto out;
1230
1231         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1232
1233         if (d0_state) {
1234                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1235                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1236
1237                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1238                         oem_reg |= HV_OEM_BITS_LPLU;
1239         } else {
1240                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1241                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1242
1243                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1244                         oem_reg |= HV_OEM_BITS_LPLU;
1245         }
1246         /* Restart auto-neg to activate the bits */
1247         if (!e1000_check_reset_block(hw))
1248                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1249         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1250
1251 out:
1252         hw->phy.ops.release(hw);
1253
1254         return ret_val;
1255 }
1256
1257
1258 /**
1259  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1260  *  @hw:   pointer to the HW structure
1261  **/
1262 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1263 {
1264         s32 ret_val;
1265         u16 data;
1266
1267         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1268         if (ret_val)
1269                 return ret_val;
1270
1271         data |= HV_KMRN_MDIO_SLOW;
1272
1273         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1274
1275         return ret_val;
1276 }
1277
1278 /**
1279  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1280  *  done after every PHY reset.
1281  **/
1282 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1283 {
1284         s32 ret_val = 0;
1285         u16 phy_data;
1286
1287         if (hw->mac.type != e1000_pchlan)
1288                 return ret_val;
1289
1290         /* Set MDIO slow mode before any other MDIO access */
1291         if (hw->phy.type == e1000_phy_82577) {
1292                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1293                 if (ret_val)
1294                         goto out;
1295         }
1296
1297         if (((hw->phy.type == e1000_phy_82577) &&
1298              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1299             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1300                 /* Disable generation of early preamble */
1301                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1302                 if (ret_val)
1303                         return ret_val;
1304
1305                 /* Preamble tuning for SSC */
1306                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1307                 if (ret_val)
1308                         return ret_val;
1309         }
1310
1311         if (hw->phy.type == e1000_phy_82578) {
1312                 /*
1313                  * Return registers to default by doing a soft reset then
1314                  * writing 0x3140 to the control register.
1315                  */
1316                 if (hw->phy.revision < 2) {
1317                         e1000e_phy_sw_reset(hw);
1318                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1319                 }
1320         }
1321
1322         /* Select page 0 */
1323         ret_val = hw->phy.ops.acquire(hw);
1324         if (ret_val)
1325                 return ret_val;
1326
1327         hw->phy.addr = 1;
1328         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1329         hw->phy.ops.release(hw);
1330         if (ret_val)
1331                 goto out;
1332
1333         /*
1334          * Configure the K1 Si workaround during phy reset assuming there is
1335          * link so that it disables K1 if link is in 1Gbps.
1336          */
1337         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1338         if (ret_val)
1339                 goto out;
1340
1341         /* Workaround for link disconnects on a busy hub in half duplex */
1342         ret_val = hw->phy.ops.acquire(hw);
1343         if (ret_val)
1344                 goto out;
1345         ret_val = hw->phy.ops.read_reg_locked(hw,
1346                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1347                                               &phy_data);
1348         if (ret_val)
1349                 goto release;
1350         ret_val = hw->phy.ops.write_reg_locked(hw,
1351                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1352                                                phy_data & 0x00FF);
1353 release:
1354         hw->phy.ops.release(hw);
1355 out:
1356         return ret_val;
1357 }
1358
1359 /**
1360  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1361  *  @hw:   pointer to the HW structure
1362  **/
1363 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1364 {
1365         u32 mac_reg;
1366         u16 i;
1367
1368         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1369         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1370                 mac_reg = er32(RAL(i));
1371                 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1372                 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1373                 mac_reg = er32(RAH(i));
1374                 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1375                 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1376         }
1377 }
1378
1379 static u32 e1000_calc_rx_da_crc(u8 mac[])
1380 {
1381         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
1382         u32 i, j, mask, crc;
1383
1384         crc = 0xffffffff;
1385         for (i = 0; i < 6; i++) {
1386                 crc = crc ^ mac[i];
1387                 for (j = 8; j > 0; j--) {
1388                         mask = (crc & 1) * (-1);
1389                         crc = (crc >> 1) ^ (poly & mask);
1390                 }
1391         }
1392         return ~crc;
1393 }
1394
1395 /**
1396  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1397  *  with 82579 PHY
1398  *  @hw: pointer to the HW structure
1399  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1400  **/
1401 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1402 {
1403         s32 ret_val = 0;
1404         u16 phy_reg, data;
1405         u32 mac_reg;
1406         u16 i;
1407
1408         if (hw->mac.type != e1000_pch2lan)
1409                 goto out;
1410
1411         /* disable Rx path while enabling/disabling workaround */
1412         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1413         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1414         if (ret_val)
1415                 goto out;
1416
1417         if (enable) {
1418                 /*
1419                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1420                  * SHRAL/H) and initial CRC values to the MAC
1421                  */
1422                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1423                         u8 mac_addr[ETH_ALEN] = {0};
1424                         u32 addr_high, addr_low;
1425
1426                         addr_high = er32(RAH(i));
1427                         if (!(addr_high & E1000_RAH_AV))
1428                                 continue;
1429                         addr_low = er32(RAL(i));
1430                         mac_addr[0] = (addr_low & 0xFF);
1431                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1432                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1433                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1434                         mac_addr[4] = (addr_high & 0xFF);
1435                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1436
1437                         ew32(PCH_RAICC(i),
1438                                         e1000_calc_rx_da_crc(mac_addr));
1439                 }
1440
1441                 /* Write Rx addresses to the PHY */
1442                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1443
1444                 /* Enable jumbo frame workaround in the MAC */
1445                 mac_reg = er32(FFLT_DBG);
1446                 mac_reg &= ~(1 << 14);
1447                 mac_reg |= (7 << 15);
1448                 ew32(FFLT_DBG, mac_reg);
1449
1450                 mac_reg = er32(RCTL);
1451                 mac_reg |= E1000_RCTL_SECRC;
1452                 ew32(RCTL, mac_reg);
1453
1454                 ret_val = e1000e_read_kmrn_reg(hw,
1455                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1456                                                 &data);
1457                 if (ret_val)
1458                         goto out;
1459                 ret_val = e1000e_write_kmrn_reg(hw,
1460                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1461                                                 data | (1 << 0));
1462                 if (ret_val)
1463                         goto out;
1464                 ret_val = e1000e_read_kmrn_reg(hw,
1465                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1466                                                 &data);
1467                 if (ret_val)
1468                         goto out;
1469                 data &= ~(0xF << 8);
1470                 data |= (0xB << 8);
1471                 ret_val = e1000e_write_kmrn_reg(hw,
1472                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1473                                                 data);
1474                 if (ret_val)
1475                         goto out;
1476
1477                 /* Enable jumbo frame workaround in the PHY */
1478                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1479                 data &= ~(0x7F << 5);
1480                 data |= (0x37 << 5);
1481                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1482                 if (ret_val)
1483                         goto out;
1484                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1485                 data &= ~(1 << 13);
1486                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1487                 if (ret_val)
1488                         goto out;
1489                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1490                 data &= ~(0x3FF << 2);
1491                 data |= (0x1A << 2);
1492                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1493                 if (ret_val)
1494                         goto out;
1495                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1496                 if (ret_val)
1497                         goto out;
1498                 e1e_rphy(hw, HV_PM_CTRL, &data);
1499                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1500                 if (ret_val)
1501                         goto out;
1502         } else {
1503                 /* Write MAC register values back to h/w defaults */
1504                 mac_reg = er32(FFLT_DBG);
1505                 mac_reg &= ~(0xF << 14);
1506                 ew32(FFLT_DBG, mac_reg);
1507
1508                 mac_reg = er32(RCTL);
1509                 mac_reg &= ~E1000_RCTL_SECRC;
1510                 ew32(RCTL, mac_reg);
1511
1512                 ret_val = e1000e_read_kmrn_reg(hw,
1513                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1514                                                 &data);
1515                 if (ret_val)
1516                         goto out;
1517                 ret_val = e1000e_write_kmrn_reg(hw,
1518                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1519                                                 data & ~(1 << 0));
1520                 if (ret_val)
1521                         goto out;
1522                 ret_val = e1000e_read_kmrn_reg(hw,
1523                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1524                                                 &data);
1525                 if (ret_val)
1526                         goto out;
1527                 data &= ~(0xF << 8);
1528                 data |= (0xB << 8);
1529                 ret_val = e1000e_write_kmrn_reg(hw,
1530                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1531                                                 data);
1532                 if (ret_val)
1533                         goto out;
1534
1535                 /* Write PHY register values back to h/w defaults */
1536                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1537                 data &= ~(0x7F << 5);
1538                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1539                 if (ret_val)
1540                         goto out;
1541                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1542                 data |= (1 << 13);
1543                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1544                 if (ret_val)
1545                         goto out;
1546                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1547                 data &= ~(0x3FF << 2);
1548                 data |= (0x8 << 2);
1549                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1550                 if (ret_val)
1551                         goto out;
1552                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1553                 if (ret_val)
1554                         goto out;
1555                 e1e_rphy(hw, HV_PM_CTRL, &data);
1556                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1557                 if (ret_val)
1558                         goto out;
1559         }
1560
1561         /* re-enable Rx path after enabling/disabling workaround */
1562         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1563
1564 out:
1565         return ret_val;
1566 }
1567
1568 /**
1569  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1570  *  done after every PHY reset.
1571  **/
1572 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1573 {
1574         s32 ret_val = 0;
1575
1576         if (hw->mac.type != e1000_pch2lan)
1577                 goto out;
1578
1579         /* Set MDIO slow mode before any other MDIO access */
1580         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1581
1582 out:
1583         return ret_val;
1584 }
1585
1586 /**
1587  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1588  *  @hw:   pointer to the HW structure
1589  *
1590  *  Workaround to set the K1 beacon duration for 82579 parts
1591  **/
1592 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1593 {
1594         s32 ret_val = 0;
1595         u16 status_reg = 0;
1596         u32 mac_reg;
1597
1598         if (hw->mac.type != e1000_pch2lan)
1599                 goto out;
1600
1601         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1602         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1603         if (ret_val)
1604                 goto out;
1605
1606         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1607             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1608                 mac_reg = er32(FEXTNVM4);
1609                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1610
1611                 if (status_reg & HV_M_STATUS_SPEED_1000)
1612                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1613                 else
1614                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1615
1616                 ew32(FEXTNVM4, mac_reg);
1617         }
1618
1619 out:
1620         return ret_val;
1621 }
1622
1623 /**
1624  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1625  *  @hw: pointer to the HW structure
1626  *
1627  *  Check the appropriate indication the MAC has finished configuring the
1628  *  PHY after a software reset.
1629  **/
1630 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1631 {
1632         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1633
1634         /* Wait for basic configuration completes before proceeding */
1635         do {
1636                 data = er32(STATUS);
1637                 data &= E1000_STATUS_LAN_INIT_DONE;
1638                 udelay(100);
1639         } while ((!data) && --loop);
1640
1641         /*
1642          * If basic configuration is incomplete before the above loop
1643          * count reaches 0, loading the configuration from NVM will
1644          * leave the PHY in a bad state possibly resulting in no link.
1645          */
1646         if (loop == 0)
1647                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1648
1649         /* Clear the Init Done bit for the next init event */
1650         data = er32(STATUS);
1651         data &= ~E1000_STATUS_LAN_INIT_DONE;
1652         ew32(STATUS, data);
1653 }
1654
1655 /**
1656  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1657  *  @hw: pointer to the HW structure
1658  **/
1659 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1660 {
1661         s32 ret_val = 0;
1662         u16 reg;
1663
1664         if (e1000_check_reset_block(hw))
1665                 goto out;
1666
1667         /* Allow time for h/w to get to quiescent state after reset */
1668         msleep(10);
1669
1670         /* Perform any necessary post-reset workarounds */
1671         switch (hw->mac.type) {
1672         case e1000_pchlan:
1673                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1674                 if (ret_val)
1675                         goto out;
1676                 break;
1677         case e1000_pch2lan:
1678                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1679                 if (ret_val)
1680                         goto out;
1681                 break;
1682         default:
1683                 break;
1684         }
1685
1686         /* Dummy read to clear the phy wakeup bit after lcd reset */
1687         if (hw->mac.type >= e1000_pchlan)
1688                 e1e_rphy(hw, BM_WUC, &reg);
1689
1690         /* Configure the LCD with the extended configuration region in NVM */
1691         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1692         if (ret_val)
1693                 goto out;
1694
1695         /* Configure the LCD with the OEM bits in NVM */
1696         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1697
1698 out:
1699         return ret_val;
1700 }
1701
1702 /**
1703  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1704  *  @hw: pointer to the HW structure
1705  *
1706  *  Resets the PHY
1707  *  This is a function pointer entry point called by drivers
1708  *  or other shared routines.
1709  **/
1710 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1711 {
1712         s32 ret_val = 0;
1713
1714         ret_val = e1000e_phy_hw_reset_generic(hw);
1715         if (ret_val)
1716                 goto out;
1717
1718         ret_val = e1000_post_phy_reset_ich8lan(hw);
1719
1720 out:
1721         return ret_val;
1722 }
1723
1724 /**
1725  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1726  *  @hw: pointer to the HW structure
1727  *  @active: true to enable LPLU, false to disable
1728  *
1729  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1730  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1731  *  the phy speed. This function will manually set the LPLU bit and restart
1732  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1733  *  since it configures the same bit.
1734  **/
1735 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1736 {
1737         s32 ret_val = 0;
1738         u16 oem_reg;
1739
1740         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1741         if (ret_val)
1742                 goto out;
1743
1744         if (active)
1745                 oem_reg |= HV_OEM_BITS_LPLU;
1746         else
1747                 oem_reg &= ~HV_OEM_BITS_LPLU;
1748
1749         oem_reg |= HV_OEM_BITS_RESTART_AN;
1750         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1751
1752 out:
1753         return ret_val;
1754 }
1755
1756 /**
1757  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1758  *  @hw: pointer to the HW structure
1759  *  @active: true to enable LPLU, false to disable
1760  *
1761  *  Sets the LPLU D0 state according to the active flag.  When
1762  *  activating LPLU this function also disables smart speed
1763  *  and vice versa.  LPLU will not be activated unless the
1764  *  device autonegotiation advertisement meets standards of
1765  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1766  *  This is a function pointer entry point only called by
1767  *  PHY setup routines.
1768  **/
1769 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1770 {
1771         struct e1000_phy_info *phy = &hw->phy;
1772         u32 phy_ctrl;
1773         s32 ret_val = 0;
1774         u16 data;
1775
1776         if (phy->type == e1000_phy_ife)
1777                 return ret_val;
1778
1779         phy_ctrl = er32(PHY_CTRL);
1780
1781         if (active) {
1782                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1783                 ew32(PHY_CTRL, phy_ctrl);
1784
1785                 if (phy->type != e1000_phy_igp_3)
1786                         return 0;
1787
1788                 /*
1789                  * Call gig speed drop workaround on LPLU before accessing
1790                  * any PHY registers
1791                  */
1792                 if (hw->mac.type == e1000_ich8lan)
1793                         e1000e_gig_downshift_workaround_ich8lan(hw);
1794
1795                 /* When LPLU is enabled, we should disable SmartSpeed */
1796                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1797                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1798                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1799                 if (ret_val)
1800                         return ret_val;
1801         } else {
1802                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1803                 ew32(PHY_CTRL, phy_ctrl);
1804
1805                 if (phy->type != e1000_phy_igp_3)
1806                         return 0;
1807
1808                 /*
1809                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1810                  * during Dx states where the power conservation is most
1811                  * important.  During driver activity we should enable
1812                  * SmartSpeed, so performance is maintained.
1813                  */
1814                 if (phy->smart_speed == e1000_smart_speed_on) {
1815                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1816                                            &data);
1817                         if (ret_val)
1818                                 return ret_val;
1819
1820                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1821                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1822                                            data);
1823                         if (ret_val)
1824                                 return ret_val;
1825                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1826                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1827                                            &data);
1828                         if (ret_val)
1829                                 return ret_val;
1830
1831                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1832                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1833                                            data);
1834                         if (ret_val)
1835                                 return ret_val;
1836                 }
1837         }
1838
1839         return 0;
1840 }
1841
1842 /**
1843  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1844  *  @hw: pointer to the HW structure
1845  *  @active: true to enable LPLU, false to disable
1846  *
1847  *  Sets the LPLU D3 state according to the active flag.  When
1848  *  activating LPLU this function also disables smart speed
1849  *  and vice versa.  LPLU will not be activated unless the
1850  *  device autonegotiation advertisement meets standards of
1851  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1852  *  This is a function pointer entry point only called by
1853  *  PHY setup routines.
1854  **/
1855 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1856 {
1857         struct e1000_phy_info *phy = &hw->phy;
1858         u32 phy_ctrl;
1859         s32 ret_val;
1860         u16 data;
1861
1862         phy_ctrl = er32(PHY_CTRL);
1863
1864         if (!active) {
1865                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1866                 ew32(PHY_CTRL, phy_ctrl);
1867
1868                 if (phy->type != e1000_phy_igp_3)
1869                         return 0;
1870
1871                 /*
1872                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1873                  * during Dx states where the power conservation is most
1874                  * important.  During driver activity we should enable
1875                  * SmartSpeed, so performance is maintained.
1876                  */
1877                 if (phy->smart_speed == e1000_smart_speed_on) {
1878                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1879                                            &data);
1880                         if (ret_val)
1881                                 return ret_val;
1882
1883                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1884                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1885                                            data);
1886                         if (ret_val)
1887                                 return ret_val;
1888                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1889                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1890                                            &data);
1891                         if (ret_val)
1892                                 return ret_val;
1893
1894                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1895                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1896                                            data);
1897                         if (ret_val)
1898                                 return ret_val;
1899                 }
1900         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1901                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1902                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1903                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1904                 ew32(PHY_CTRL, phy_ctrl);
1905
1906                 if (phy->type != e1000_phy_igp_3)
1907                         return 0;
1908
1909                 /*
1910                  * Call gig speed drop workaround on LPLU before accessing
1911                  * any PHY registers
1912                  */
1913                 if (hw->mac.type == e1000_ich8lan)
1914                         e1000e_gig_downshift_workaround_ich8lan(hw);
1915
1916                 /* When LPLU is enabled, we should disable SmartSpeed */
1917                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1918                 if (ret_val)
1919                         return ret_val;
1920
1921                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1922                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1923         }
1924
1925         return 0;
1926 }
1927
1928 /**
1929  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1930  *  @hw: pointer to the HW structure
1931  *  @bank:  pointer to the variable that returns the active bank
1932  *
1933  *  Reads signature byte from the NVM using the flash access registers.
1934  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1935  **/
1936 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1937 {
1938         u32 eecd;
1939         struct e1000_nvm_info *nvm = &hw->nvm;
1940         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1941         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1942         u8 sig_byte = 0;
1943         s32 ret_val = 0;
1944
1945         switch (hw->mac.type) {
1946         case e1000_ich8lan:
1947         case e1000_ich9lan:
1948                 eecd = er32(EECD);
1949                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1950                     E1000_EECD_SEC1VAL_VALID_MASK) {
1951                         if (eecd & E1000_EECD_SEC1VAL)
1952                                 *bank = 1;
1953                         else
1954                                 *bank = 0;
1955
1956                         return 0;
1957                 }
1958                 e_dbg("Unable to determine valid NVM bank via EEC - "
1959                        "reading flash signature\n");
1960                 /* fall-thru */
1961         default:
1962                 /* set bank to 0 in case flash read fails */
1963                 *bank = 0;
1964
1965                 /* Check bank 0 */
1966                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1967                                                         &sig_byte);
1968                 if (ret_val)
1969                         return ret_val;
1970                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1971                     E1000_ICH_NVM_SIG_VALUE) {
1972                         *bank = 0;
1973                         return 0;
1974                 }
1975
1976                 /* Check bank 1 */
1977                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1978                                                         bank1_offset,
1979                                                         &sig_byte);
1980                 if (ret_val)
1981                         return ret_val;
1982                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1983                     E1000_ICH_NVM_SIG_VALUE) {
1984                         *bank = 1;
1985                         return 0;
1986                 }
1987
1988                 e_dbg("ERROR: No valid NVM bank present\n");
1989                 return -E1000_ERR_NVM;
1990         }
1991
1992         return 0;
1993 }
1994
1995 /**
1996  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1997  *  @hw: pointer to the HW structure
1998  *  @offset: The offset (in bytes) of the word(s) to read.
1999  *  @words: Size of data to read in words
2000  *  @data: Pointer to the word(s) to read at offset.
2001  *
2002  *  Reads a word(s) from the NVM using the flash access registers.
2003  **/
2004 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2005                                   u16 *data)
2006 {
2007         struct e1000_nvm_info *nvm = &hw->nvm;
2008         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2009         u32 act_offset;
2010         s32 ret_val = 0;
2011         u32 bank = 0;
2012         u16 i, word;
2013
2014         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2015             (words == 0)) {
2016                 e_dbg("nvm parameter(s) out of bounds\n");
2017                 ret_val = -E1000_ERR_NVM;
2018                 goto out;
2019         }
2020
2021         nvm->ops.acquire(hw);
2022
2023         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2024         if (ret_val) {
2025                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2026                 bank = 0;
2027         }
2028
2029         act_offset = (bank) ? nvm->flash_bank_size : 0;
2030         act_offset += offset;
2031
2032         ret_val = 0;
2033         for (i = 0; i < words; i++) {
2034                 if ((dev_spec->shadow_ram) &&
2035                     (dev_spec->shadow_ram[offset+i].modified)) {
2036                         data[i] = dev_spec->shadow_ram[offset+i].value;
2037                 } else {
2038                         ret_val = e1000_read_flash_word_ich8lan(hw,
2039                                                                 act_offset + i,
2040                                                                 &word);
2041                         if (ret_val)
2042                                 break;
2043                         data[i] = word;
2044                 }
2045         }
2046
2047         nvm->ops.release(hw);
2048
2049 out:
2050         if (ret_val)
2051                 e_dbg("NVM read error: %d\n", ret_val);
2052
2053         return ret_val;
2054 }
2055
2056 /**
2057  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2058  *  @hw: pointer to the HW structure
2059  *
2060  *  This function does initial flash setup so that a new read/write/erase cycle
2061  *  can be started.
2062  **/
2063 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2064 {
2065         union ich8_hws_flash_status hsfsts;
2066         s32 ret_val = -E1000_ERR_NVM;
2067         s32 i = 0;
2068
2069         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2070
2071         /* Check if the flash descriptor is valid */
2072         if (hsfsts.hsf_status.fldesvalid == 0) {
2073                 e_dbg("Flash descriptor invalid.  "
2074                          "SW Sequencing must be used.\n");
2075                 return -E1000_ERR_NVM;
2076         }
2077
2078         /* Clear FCERR and DAEL in hw status by writing 1 */
2079         hsfsts.hsf_status.flcerr = 1;
2080         hsfsts.hsf_status.dael = 1;
2081
2082         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2083
2084         /*
2085          * Either we should have a hardware SPI cycle in progress
2086          * bit to check against, in order to start a new cycle or
2087          * FDONE bit should be changed in the hardware so that it
2088          * is 1 after hardware reset, which can then be used as an
2089          * indication whether a cycle is in progress or has been
2090          * completed.
2091          */
2092
2093         if (hsfsts.hsf_status.flcinprog == 0) {
2094                 /*
2095                  * There is no cycle running at present,
2096                  * so we can start a cycle.
2097                  * Begin by setting Flash Cycle Done.
2098                  */
2099                 hsfsts.hsf_status.flcdone = 1;
2100                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2101                 ret_val = 0;
2102         } else {
2103                 /*
2104                  * Otherwise poll for sometime so the current
2105                  * cycle has a chance to end before giving up.
2106                  */
2107                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2108                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2109                         if (hsfsts.hsf_status.flcinprog == 0) {
2110                                 ret_val = 0;
2111                                 break;
2112                         }
2113                         udelay(1);
2114                 }
2115                 if (ret_val == 0) {
2116                         /*
2117                          * Successful in waiting for previous cycle to timeout,
2118                          * now set the Flash Cycle Done.
2119                          */
2120                         hsfsts.hsf_status.flcdone = 1;
2121                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2122                 } else {
2123                         e_dbg("Flash controller busy, cannot get access\n");
2124                 }
2125         }
2126
2127         return ret_val;
2128 }
2129
2130 /**
2131  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2132  *  @hw: pointer to the HW structure
2133  *  @timeout: maximum time to wait for completion
2134  *
2135  *  This function starts a flash cycle and waits for its completion.
2136  **/
2137 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2138 {
2139         union ich8_hws_flash_ctrl hsflctl;
2140         union ich8_hws_flash_status hsfsts;
2141         s32 ret_val = -E1000_ERR_NVM;
2142         u32 i = 0;
2143
2144         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2145         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2146         hsflctl.hsf_ctrl.flcgo = 1;
2147         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2148
2149         /* wait till FDONE bit is set to 1 */
2150         do {
2151                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2152                 if (hsfsts.hsf_status.flcdone == 1)
2153                         break;
2154                 udelay(1);
2155         } while (i++ < timeout);
2156
2157         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2158                 return 0;
2159
2160         return ret_val;
2161 }
2162
2163 /**
2164  *  e1000_read_flash_word_ich8lan - Read word from flash
2165  *  @hw: pointer to the HW structure
2166  *  @offset: offset to data location
2167  *  @data: pointer to the location for storing the data
2168  *
2169  *  Reads the flash word at offset into data.  Offset is converted
2170  *  to bytes before read.
2171  **/
2172 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2173                                          u16 *data)
2174 {
2175         /* Must convert offset into bytes. */
2176         offset <<= 1;
2177
2178         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2179 }
2180
2181 /**
2182  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2183  *  @hw: pointer to the HW structure
2184  *  @offset: The offset of the byte to read.
2185  *  @data: Pointer to a byte to store the value read.
2186  *
2187  *  Reads a single byte from the NVM using the flash access registers.
2188  **/
2189 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2190                                          u8 *data)
2191 {
2192         s32 ret_val;
2193         u16 word = 0;
2194
2195         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2196         if (ret_val)
2197                 return ret_val;
2198
2199         *data = (u8)word;
2200
2201         return 0;
2202 }
2203
2204 /**
2205  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2206  *  @hw: pointer to the HW structure
2207  *  @offset: The offset (in bytes) of the byte or word to read.
2208  *  @size: Size of data to read, 1=byte 2=word
2209  *  @data: Pointer to the word to store the value read.
2210  *
2211  *  Reads a byte or word from the NVM using the flash access registers.
2212  **/
2213 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2214                                          u8 size, u16 *data)
2215 {
2216         union ich8_hws_flash_status hsfsts;
2217         union ich8_hws_flash_ctrl hsflctl;
2218         u32 flash_linear_addr;
2219         u32 flash_data = 0;
2220         s32 ret_val = -E1000_ERR_NVM;
2221         u8 count = 0;
2222
2223         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2224                 return -E1000_ERR_NVM;
2225
2226         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2227                             hw->nvm.flash_base_addr;
2228
2229         do {
2230                 udelay(1);
2231                 /* Steps */
2232                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2233                 if (ret_val != 0)
2234                         break;
2235
2236                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2237                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2238                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2239                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2240                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2241
2242                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2243
2244                 ret_val = e1000_flash_cycle_ich8lan(hw,
2245                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2246
2247                 /*
2248                  * Check if FCERR is set to 1, if set to 1, clear it
2249                  * and try the whole sequence a few more times, else
2250                  * read in (shift in) the Flash Data0, the order is
2251                  * least significant byte first msb to lsb
2252                  */
2253                 if (ret_val == 0) {
2254                         flash_data = er32flash(ICH_FLASH_FDATA0);
2255                         if (size == 1) {
2256                                 *data = (u8)(flash_data & 0x000000FF);
2257                         } else if (size == 2) {
2258                                 *data = (u16)(flash_data & 0x0000FFFF);
2259                         }
2260                         break;
2261                 } else {
2262                         /*
2263                          * If we've gotten here, then things are probably
2264                          * completely hosed, but if the error condition is
2265                          * detected, it won't hurt to give it another try...
2266                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2267                          */
2268                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2269                         if (hsfsts.hsf_status.flcerr == 1) {
2270                                 /* Repeat for some time before giving up. */
2271                                 continue;
2272                         } else if (hsfsts.hsf_status.flcdone == 0) {
2273                                 e_dbg("Timeout error - flash cycle "
2274                                          "did not complete.\n");
2275                                 break;
2276                         }
2277                 }
2278         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2279
2280         return ret_val;
2281 }
2282
2283 /**
2284  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2285  *  @hw: pointer to the HW structure
2286  *  @offset: The offset (in bytes) of the word(s) to write.
2287  *  @words: Size of data to write in words
2288  *  @data: Pointer to the word(s) to write at offset.
2289  *
2290  *  Writes a byte or word to the NVM using the flash access registers.
2291  **/
2292 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2293                                    u16 *data)
2294 {
2295         struct e1000_nvm_info *nvm = &hw->nvm;
2296         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2297         u16 i;
2298
2299         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2300             (words == 0)) {
2301                 e_dbg("nvm parameter(s) out of bounds\n");
2302                 return -E1000_ERR_NVM;
2303         }
2304
2305         nvm->ops.acquire(hw);
2306
2307         for (i = 0; i < words; i++) {
2308                 dev_spec->shadow_ram[offset+i].modified = true;
2309                 dev_spec->shadow_ram[offset+i].value = data[i];
2310         }
2311
2312         nvm->ops.release(hw);
2313
2314         return 0;
2315 }
2316
2317 /**
2318  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2319  *  @hw: pointer to the HW structure
2320  *
2321  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2322  *  which writes the checksum to the shadow ram.  The changes in the shadow
2323  *  ram are then committed to the EEPROM by processing each bank at a time
2324  *  checking for the modified bit and writing only the pending changes.
2325  *  After a successful commit, the shadow ram is cleared and is ready for
2326  *  future writes.
2327  **/
2328 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2329 {
2330         struct e1000_nvm_info *nvm = &hw->nvm;
2331         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2332         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2333         s32 ret_val;
2334         u16 data;
2335
2336         ret_val = e1000e_update_nvm_checksum_generic(hw);
2337         if (ret_val)
2338                 goto out;
2339
2340         if (nvm->type != e1000_nvm_flash_sw)
2341                 goto out;
2342
2343         nvm->ops.acquire(hw);
2344
2345         /*
2346          * We're writing to the opposite bank so if we're on bank 1,
2347          * write to bank 0 etc.  We also need to erase the segment that
2348          * is going to be written
2349          */
2350         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2351         if (ret_val) {
2352                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2353                 bank = 0;
2354         }
2355
2356         if (bank == 0) {
2357                 new_bank_offset = nvm->flash_bank_size;
2358                 old_bank_offset = 0;
2359                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2360                 if (ret_val)
2361                         goto release;
2362         } else {
2363                 old_bank_offset = nvm->flash_bank_size;
2364                 new_bank_offset = 0;
2365                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2366                 if (ret_val)
2367                         goto release;
2368         }
2369
2370         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2371                 /*
2372                  * Determine whether to write the value stored
2373                  * in the other NVM bank or a modified value stored
2374                  * in the shadow RAM
2375                  */
2376                 if (dev_spec->shadow_ram[i].modified) {
2377                         data = dev_spec->shadow_ram[i].value;
2378                 } else {
2379                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2380                                                                 old_bank_offset,
2381                                                                 &data);
2382                         if (ret_val)
2383                                 break;
2384                 }
2385
2386                 /*
2387                  * If the word is 0x13, then make sure the signature bits
2388                  * (15:14) are 11b until the commit has completed.
2389                  * This will allow us to write 10b which indicates the
2390                  * signature is valid.  We want to do this after the write
2391                  * has completed so that we don't mark the segment valid
2392                  * while the write is still in progress
2393                  */
2394                 if (i == E1000_ICH_NVM_SIG_WORD)
2395                         data |= E1000_ICH_NVM_SIG_MASK;
2396
2397                 /* Convert offset to bytes. */
2398                 act_offset = (i + new_bank_offset) << 1;
2399
2400                 udelay(100);
2401                 /* Write the bytes to the new bank. */
2402                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2403                                                                act_offset,
2404                                                                (u8)data);
2405                 if (ret_val)
2406                         break;
2407
2408                 udelay(100);
2409                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2410                                                           act_offset + 1,
2411                                                           (u8)(data >> 8));
2412                 if (ret_val)
2413                         break;
2414         }
2415
2416         /*
2417          * Don't bother writing the segment valid bits if sector
2418          * programming failed.
2419          */
2420         if (ret_val) {
2421                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2422                 e_dbg("Flash commit failed.\n");
2423                 goto release;
2424         }
2425
2426         /*
2427          * Finally validate the new segment by setting bit 15:14
2428          * to 10b in word 0x13 , this can be done without an
2429          * erase as well since these bits are 11 to start with
2430          * and we need to change bit 14 to 0b
2431          */
2432         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2433         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2434         if (ret_val)
2435                 goto release;
2436
2437         data &= 0xBFFF;
2438         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2439                                                        act_offset * 2 + 1,
2440                                                        (u8)(data >> 8));
2441         if (ret_val)
2442                 goto release;
2443
2444         /*
2445          * And invalidate the previously valid segment by setting
2446          * its signature word (0x13) high_byte to 0b. This can be
2447          * done without an erase because flash erase sets all bits
2448          * to 1's. We can write 1's to 0's without an erase
2449          */
2450         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2451         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2452         if (ret_val)
2453                 goto release;
2454
2455         /* Great!  Everything worked, we can now clear the cached entries. */
2456         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2457                 dev_spec->shadow_ram[i].modified = false;
2458                 dev_spec->shadow_ram[i].value = 0xFFFF;
2459         }
2460
2461 release:
2462         nvm->ops.release(hw);
2463
2464         /*
2465          * Reload the EEPROM, or else modifications will not appear
2466          * until after the next adapter reset.
2467          */
2468         if (!ret_val) {
2469                 e1000e_reload_nvm(hw);
2470                 msleep(10);
2471         }
2472
2473 out:
2474         if (ret_val)
2475                 e_dbg("NVM update error: %d\n", ret_val);
2476
2477         return ret_val;
2478 }
2479
2480 /**
2481  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2482  *  @hw: pointer to the HW structure
2483  *
2484  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2485  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2486  *  calculated, in which case we need to calculate the checksum and set bit 6.
2487  **/
2488 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2489 {
2490         s32 ret_val;
2491         u16 data;
2492
2493         /*
2494          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2495          * needs to be fixed.  This bit is an indication that the NVM
2496          * was prepared by OEM software and did not calculate the
2497          * checksum...a likely scenario.
2498          */
2499         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2500         if (ret_val)
2501                 return ret_val;
2502
2503         if ((data & 0x40) == 0) {
2504                 data |= 0x40;
2505                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2506                 if (ret_val)
2507                         return ret_val;
2508                 ret_val = e1000e_update_nvm_checksum(hw);
2509                 if (ret_val)
2510                         return ret_val;
2511         }
2512
2513         return e1000e_validate_nvm_checksum_generic(hw);
2514 }
2515
2516 /**
2517  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2518  *  @hw: pointer to the HW structure
2519  *
2520  *  To prevent malicious write/erase of the NVM, set it to be read-only
2521  *  so that the hardware ignores all write/erase cycles of the NVM via
2522  *  the flash control registers.  The shadow-ram copy of the NVM will
2523  *  still be updated, however any updates to this copy will not stick
2524  *  across driver reloads.
2525  **/
2526 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2527 {
2528         struct e1000_nvm_info *nvm = &hw->nvm;
2529         union ich8_flash_protected_range pr0;
2530         union ich8_hws_flash_status hsfsts;
2531         u32 gfpreg;
2532
2533         nvm->ops.acquire(hw);
2534
2535         gfpreg = er32flash(ICH_FLASH_GFPREG);
2536
2537         /* Write-protect GbE Sector of NVM */
2538         pr0.regval = er32flash(ICH_FLASH_PR0);
2539         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2540         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2541         pr0.range.wpe = true;
2542         ew32flash(ICH_FLASH_PR0, pr0.regval);
2543
2544         /*
2545          * Lock down a subset of GbE Flash Control Registers, e.g.
2546          * PR0 to prevent the write-protection from being lifted.
2547          * Once FLOCKDN is set, the registers protected by it cannot
2548          * be written until FLOCKDN is cleared by a hardware reset.
2549          */
2550         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2551         hsfsts.hsf_status.flockdn = true;
2552         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2553
2554         nvm->ops.release(hw);
2555 }
2556
2557 /**
2558  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2559  *  @hw: pointer to the HW structure
2560  *  @offset: The offset (in bytes) of the byte/word to read.
2561  *  @size: Size of data to read, 1=byte 2=word
2562  *  @data: The byte(s) to write to the NVM.
2563  *
2564  *  Writes one/two bytes to the NVM using the flash access registers.
2565  **/
2566 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2567                                           u8 size, u16 data)
2568 {
2569         union ich8_hws_flash_status hsfsts;
2570         union ich8_hws_flash_ctrl hsflctl;
2571         u32 flash_linear_addr;
2572         u32 flash_data = 0;
2573         s32 ret_val;
2574         u8 count = 0;
2575
2576         if (size < 1 || size > 2 || data > size * 0xff ||
2577             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2578                 return -E1000_ERR_NVM;
2579
2580         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2581                             hw->nvm.flash_base_addr;
2582
2583         do {
2584                 udelay(1);
2585                 /* Steps */
2586                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2587                 if (ret_val)
2588                         break;
2589
2590                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2591                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2592                 hsflctl.hsf_ctrl.fldbcount = size -1;
2593                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2594                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2595
2596                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2597
2598                 if (size == 1)
2599                         flash_data = (u32)data & 0x00FF;
2600                 else
2601                         flash_data = (u32)data;
2602
2603                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2604
2605                 /*
2606                  * check if FCERR is set to 1 , if set to 1, clear it
2607                  * and try the whole sequence a few more times else done
2608                  */
2609                 ret_val = e1000_flash_cycle_ich8lan(hw,
2610                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2611                 if (!ret_val)
2612                         break;
2613
2614                 /*
2615                  * If we're here, then things are most likely
2616                  * completely hosed, but if the error condition
2617                  * is detected, it won't hurt to give it another
2618                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2619                  */
2620                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2621                 if (hsfsts.hsf_status.flcerr == 1)
2622                         /* Repeat for some time before giving up. */
2623                         continue;
2624                 if (hsfsts.hsf_status.flcdone == 0) {
2625                         e_dbg("Timeout error - flash cycle "
2626                                  "did not complete.");
2627                         break;
2628                 }
2629         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2630
2631         return ret_val;
2632 }
2633
2634 /**
2635  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2636  *  @hw: pointer to the HW structure
2637  *  @offset: The index of the byte to read.
2638  *  @data: The byte to write to the NVM.
2639  *
2640  *  Writes a single byte to the NVM using the flash access registers.
2641  **/
2642 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2643                                           u8 data)
2644 {
2645         u16 word = (u16)data;
2646
2647         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2648 }
2649
2650 /**
2651  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2652  *  @hw: pointer to the HW structure
2653  *  @offset: The offset of the byte to write.
2654  *  @byte: The byte to write to the NVM.
2655  *
2656  *  Writes a single byte to the NVM using the flash access registers.
2657  *  Goes through a retry algorithm before giving up.
2658  **/
2659 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2660                                                 u32 offset, u8 byte)
2661 {
2662         s32 ret_val;
2663         u16 program_retries;
2664
2665         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2666         if (!ret_val)
2667                 return ret_val;
2668
2669         for (program_retries = 0; program_retries < 100; program_retries++) {
2670                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2671                 udelay(100);
2672                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2673                 if (!ret_val)
2674                         break;
2675         }
2676         if (program_retries == 100)
2677                 return -E1000_ERR_NVM;
2678
2679         return 0;
2680 }
2681
2682 /**
2683  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2684  *  @hw: pointer to the HW structure
2685  *  @bank: 0 for first bank, 1 for second bank, etc.
2686  *
2687  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2688  *  bank N is 4096 * N + flash_reg_addr.
2689  **/
2690 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2691 {
2692         struct e1000_nvm_info *nvm = &hw->nvm;
2693         union ich8_hws_flash_status hsfsts;
2694         union ich8_hws_flash_ctrl hsflctl;
2695         u32 flash_linear_addr;
2696         /* bank size is in 16bit words - adjust to bytes */
2697         u32 flash_bank_size = nvm->flash_bank_size * 2;
2698         s32 ret_val;
2699         s32 count = 0;
2700         s32 j, iteration, sector_size;
2701
2702         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2703
2704         /*
2705          * Determine HW Sector size: Read BERASE bits of hw flash status
2706          * register
2707          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2708          *     consecutive sectors.  The start index for the nth Hw sector
2709          *     can be calculated as = bank * 4096 + n * 256
2710          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2711          *     The start index for the nth Hw sector can be calculated
2712          *     as = bank * 4096
2713          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2714          *     (ich9 only, otherwise error condition)
2715          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2716          */
2717         switch (hsfsts.hsf_status.berasesz) {
2718         case 0:
2719                 /* Hw sector size 256 */
2720                 sector_size = ICH_FLASH_SEG_SIZE_256;
2721                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2722                 break;
2723         case 1:
2724                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2725                 iteration = 1;
2726                 break;
2727         case 2:
2728                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2729                 iteration = 1;
2730                 break;
2731         case 3:
2732                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2733                 iteration = 1;
2734                 break;
2735         default:
2736                 return -E1000_ERR_NVM;
2737         }
2738
2739         /* Start with the base address, then add the sector offset. */
2740         flash_linear_addr = hw->nvm.flash_base_addr;
2741         flash_linear_addr += (bank) ? flash_bank_size : 0;
2742
2743         for (j = 0; j < iteration ; j++) {
2744                 do {
2745                         /* Steps */
2746                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2747                         if (ret_val)
2748                                 return ret_val;
2749
2750                         /*
2751                          * Write a value 11 (block Erase) in Flash
2752                          * Cycle field in hw flash control
2753                          */
2754                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2755                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2756                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2757
2758                         /*
2759                          * Write the last 24 bits of an index within the
2760                          * block into Flash Linear address field in Flash
2761                          * Address.
2762                          */
2763                         flash_linear_addr += (j * sector_size);
2764                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2765
2766                         ret_val = e1000_flash_cycle_ich8lan(hw,
2767                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2768                         if (ret_val == 0)
2769                                 break;
2770
2771                         /*
2772                          * Check if FCERR is set to 1.  If 1,
2773                          * clear it and try the whole sequence
2774                          * a few more times else Done
2775                          */
2776                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2777                         if (hsfsts.hsf_status.flcerr == 1)
2778                                 /* repeat for some time before giving up */
2779                                 continue;
2780                         else if (hsfsts.hsf_status.flcdone == 0)
2781                                 return ret_val;
2782                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2783         }
2784
2785         return 0;
2786 }
2787
2788 /**
2789  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2790  *  @hw: pointer to the HW structure
2791  *  @data: Pointer to the LED settings
2792  *
2793  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2794  *  settings is all 0's or F's, set the LED default to a valid LED default
2795  *  setting.
2796  **/
2797 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2798 {
2799         s32 ret_val;
2800
2801         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2802         if (ret_val) {
2803                 e_dbg("NVM Read Error\n");
2804                 return ret_val;
2805         }
2806
2807         if (*data == ID_LED_RESERVED_0000 ||
2808             *data == ID_LED_RESERVED_FFFF)
2809                 *data = ID_LED_DEFAULT_ICH8LAN;
2810
2811         return 0;
2812 }
2813
2814 /**
2815  *  e1000_id_led_init_pchlan - store LED configurations
2816  *  @hw: pointer to the HW structure
2817  *
2818  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2819  *  the PHY LED configuration register.
2820  *
2821  *  PCH also does not have an "always on" or "always off" mode which
2822  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2823  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2824  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2825  *  link based on logic in e1000_led_[on|off]_pchlan().
2826  **/
2827 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2828 {
2829         struct e1000_mac_info *mac = &hw->mac;
2830         s32 ret_val;
2831         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2832         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2833         u16 data, i, temp, shift;
2834
2835         /* Get default ID LED modes */
2836         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2837         if (ret_val)
2838                 goto out;
2839
2840         mac->ledctl_default = er32(LEDCTL);
2841         mac->ledctl_mode1 = mac->ledctl_default;
2842         mac->ledctl_mode2 = mac->ledctl_default;
2843
2844         for (i = 0; i < 4; i++) {
2845                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2846                 shift = (i * 5);
2847                 switch (temp) {
2848                 case ID_LED_ON1_DEF2:
2849                 case ID_LED_ON1_ON2:
2850                 case ID_LED_ON1_OFF2:
2851                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2852                         mac->ledctl_mode1 |= (ledctl_on << shift);
2853                         break;
2854                 case ID_LED_OFF1_DEF2:
2855                 case ID_LED_OFF1_ON2:
2856                 case ID_LED_OFF1_OFF2:
2857                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2858                         mac->ledctl_mode1 |= (ledctl_off << shift);
2859                         break;
2860                 default:
2861                         /* Do nothing */
2862                         break;
2863                 }
2864                 switch (temp) {
2865                 case ID_LED_DEF1_ON2:
2866                 case ID_LED_ON1_ON2:
2867                 case ID_LED_OFF1_ON2:
2868                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2869                         mac->ledctl_mode2 |= (ledctl_on << shift);
2870                         break;
2871                 case ID_LED_DEF1_OFF2:
2872                 case ID_LED_ON1_OFF2:
2873                 case ID_LED_OFF1_OFF2:
2874                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2875                         mac->ledctl_mode2 |= (ledctl_off << shift);
2876                         break;
2877                 default:
2878                         /* Do nothing */
2879                         break;
2880                 }
2881         }
2882
2883 out:
2884         return ret_val;
2885 }
2886
2887 /**
2888  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2889  *  @hw: pointer to the HW structure
2890  *
2891  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2892  *  register, so the the bus width is hard coded.
2893  **/
2894 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2895 {
2896         struct e1000_bus_info *bus = &hw->bus;
2897         s32 ret_val;
2898
2899         ret_val = e1000e_get_bus_info_pcie(hw);
2900
2901         /*
2902          * ICH devices are "PCI Express"-ish.  They have
2903          * a configuration space, but do not contain
2904          * PCI Express Capability registers, so bus width
2905          * must be hardcoded.
2906          */
2907         if (bus->width == e1000_bus_width_unknown)
2908                 bus->width = e1000_bus_width_pcie_x1;
2909
2910         return ret_val;
2911 }
2912
2913 /**
2914  *  e1000_reset_hw_ich8lan - Reset the hardware
2915  *  @hw: pointer to the HW structure
2916  *
2917  *  Does a full reset of the hardware which includes a reset of the PHY and
2918  *  MAC.
2919  **/
2920 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2921 {
2922         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2923         u16 reg;
2924         u32 ctrl, icr, kab;
2925         s32 ret_val;
2926
2927         /*
2928          * Prevent the PCI-E bus from sticking if there is no TLP connection
2929          * on the last TLP read/write transaction when MAC is reset.
2930          */
2931         ret_val = e1000e_disable_pcie_master(hw);
2932         if (ret_val)
2933                 e_dbg("PCI-E Master disable polling has failed.\n");
2934
2935         e_dbg("Masking off all interrupts\n");
2936         ew32(IMC, 0xffffffff);
2937
2938         /*
2939          * Disable the Transmit and Receive units.  Then delay to allow
2940          * any pending transactions to complete before we hit the MAC
2941          * with the global reset.
2942          */
2943         ew32(RCTL, 0);
2944         ew32(TCTL, E1000_TCTL_PSP);
2945         e1e_flush();
2946
2947         msleep(10);
2948
2949         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2950         if (hw->mac.type == e1000_ich8lan) {
2951                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2952                 ew32(PBA, E1000_PBA_8K);
2953                 /* Set Packet Buffer Size to 16k. */
2954                 ew32(PBS, E1000_PBS_16K);
2955         }
2956
2957         if (hw->mac.type == e1000_pchlan) {
2958                 /* Save the NVM K1 bit setting*/
2959                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2960                 if (ret_val)
2961                         return ret_val;
2962
2963                 if (reg & E1000_NVM_K1_ENABLE)
2964                         dev_spec->nvm_k1_enabled = true;
2965                 else
2966                         dev_spec->nvm_k1_enabled = false;
2967         }
2968
2969         ctrl = er32(CTRL);
2970
2971         if (!e1000_check_reset_block(hw)) {
2972                 /*
2973                  * Full-chip reset requires MAC and PHY reset at the same
2974                  * time to make sure the interface between MAC and the
2975                  * external PHY is reset.
2976                  */
2977                 ctrl |= E1000_CTRL_PHY_RST;
2978         }
2979         ret_val = e1000_acquire_swflag_ich8lan(hw);
2980         e_dbg("Issuing a global reset to ich8lan\n");
2981         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2982         msleep(20);
2983
2984         if (!ret_val)
2985                 e1000_release_swflag_ich8lan(hw);
2986
2987         if (ctrl & E1000_CTRL_PHY_RST) {
2988                 ret_val = hw->phy.ops.get_cfg_done(hw);
2989                 if (ret_val)
2990                         goto out;
2991
2992                 ret_val = e1000_post_phy_reset_ich8lan(hw);
2993                 if (ret_val)
2994                         goto out;
2995         }
2996
2997         /*
2998          * For PCH, this write will make sure that any noise
2999          * will be detected as a CRC error and be dropped rather than show up
3000          * as a bad packet to the DMA engine.
3001          */
3002         if (hw->mac.type == e1000_pchlan)
3003                 ew32(CRC_OFFSET, 0x65656565);
3004
3005         ew32(IMC, 0xffffffff);
3006         icr = er32(ICR);
3007
3008         kab = er32(KABGTXD);
3009         kab |= E1000_KABGTXD_BGSQLBIAS;
3010         ew32(KABGTXD, kab);
3011
3012 out:
3013         return ret_val;
3014 }
3015
3016 /**
3017  *  e1000_init_hw_ich8lan - Initialize the hardware
3018  *  @hw: pointer to the HW structure
3019  *
3020  *  Prepares the hardware for transmit and receive by doing the following:
3021  *   - initialize hardware bits
3022  *   - initialize LED identification
3023  *   - setup receive address registers
3024  *   - setup flow control
3025  *   - setup transmit descriptors
3026  *   - clear statistics
3027  **/
3028 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3029 {
3030         struct e1000_mac_info *mac = &hw->mac;
3031         u32 ctrl_ext, txdctl, snoop;
3032         s32 ret_val;
3033         u16 i;
3034
3035         e1000_initialize_hw_bits_ich8lan(hw);
3036
3037         /* Initialize identification LED */
3038         ret_val = mac->ops.id_led_init(hw);
3039         if (ret_val)
3040                 e_dbg("Error initializing identification LED\n");
3041                 /* This is not fatal and we should not stop init due to this */
3042
3043         /* Setup the receive address. */
3044         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3045
3046         /* Zero out the Multicast HASH table */
3047         e_dbg("Zeroing the MTA\n");
3048         for (i = 0; i < mac->mta_reg_count; i++)
3049                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3050
3051         /*
3052          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3053          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
3054          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3055          */
3056         if (hw->phy.type == e1000_phy_82578) {
3057                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
3058                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3059                 if (ret_val)
3060                         return ret_val;
3061         }
3062
3063         /* Setup link and flow control */
3064         ret_val = e1000_setup_link_ich8lan(hw);
3065
3066         /* Set the transmit descriptor write-back policy for both queues */
3067         txdctl = er32(TXDCTL(0));
3068         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3069                  E1000_TXDCTL_FULL_TX_DESC_WB;
3070         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3071                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3072         ew32(TXDCTL(0), txdctl);
3073         txdctl = er32(TXDCTL(1));
3074         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3075                  E1000_TXDCTL_FULL_TX_DESC_WB;
3076         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3077                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3078         ew32(TXDCTL(1), txdctl);
3079
3080         /*
3081          * ICH8 has opposite polarity of no_snoop bits.
3082          * By default, we should use snoop behavior.
3083          */
3084         if (mac->type == e1000_ich8lan)
3085                 snoop = PCIE_ICH8_SNOOP_ALL;
3086         else
3087                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3088         e1000e_set_pcie_no_snoop(hw, snoop);
3089
3090         ctrl_ext = er32(CTRL_EXT);
3091         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3092         ew32(CTRL_EXT, ctrl_ext);
3093
3094         /*
3095          * Clear all of the statistics registers (clear on read).  It is
3096          * important that we do this after we have tried to establish link
3097          * because the symbol error count will increment wildly if there
3098          * is no link.
3099          */
3100         e1000_clear_hw_cntrs_ich8lan(hw);
3101
3102         return 0;
3103 }
3104 /**
3105  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3106  *  @hw: pointer to the HW structure
3107  *
3108  *  Sets/Clears required hardware bits necessary for correctly setting up the
3109  *  hardware for transmit and receive.
3110  **/
3111 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3112 {
3113         u32 reg;
3114
3115         /* Extended Device Control */
3116         reg = er32(CTRL_EXT);
3117         reg |= (1 << 22);
3118         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3119         if (hw->mac.type >= e1000_pchlan)
3120                 reg |= E1000_CTRL_EXT_PHYPDEN;
3121         ew32(CTRL_EXT, reg);
3122
3123         /* Transmit Descriptor Control 0 */
3124         reg = er32(TXDCTL(0));
3125         reg |= (1 << 22);
3126         ew32(TXDCTL(0), reg);
3127
3128         /* Transmit Descriptor Control 1 */
3129         reg = er32(TXDCTL(1));
3130         reg |= (1 << 22);
3131         ew32(TXDCTL(1), reg);
3132
3133         /* Transmit Arbitration Control 0 */
3134         reg = er32(TARC(0));
3135         if (hw->mac.type == e1000_ich8lan)
3136                 reg |= (1 << 28) | (1 << 29);
3137         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3138         ew32(TARC(0), reg);
3139
3140         /* Transmit Arbitration Control 1 */
3141         reg = er32(TARC(1));
3142         if (er32(TCTL) & E1000_TCTL_MULR)
3143                 reg &= ~(1 << 28);
3144         else
3145                 reg |= (1 << 28);
3146         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3147         ew32(TARC(1), reg);
3148
3149         /* Device Status */
3150         if (hw->mac.type == e1000_ich8lan) {
3151                 reg = er32(STATUS);
3152                 reg &= ~(1 << 31);
3153                 ew32(STATUS, reg);
3154         }
3155
3156         /*
3157          * work-around descriptor data corruption issue during nfs v2 udp
3158          * traffic, just disable the nfs filtering capability
3159          */
3160         reg = er32(RFCTL);
3161         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3162         ew32(RFCTL, reg);
3163 }
3164
3165 /**
3166  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3167  *  @hw: pointer to the HW structure
3168  *
3169  *  Determines which flow control settings to use, then configures flow
3170  *  control.  Calls the appropriate media-specific link configuration
3171  *  function.  Assuming the adapter has a valid link partner, a valid link
3172  *  should be established.  Assumes the hardware has previously been reset
3173  *  and the transmitter and receiver are not enabled.
3174  **/
3175 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3176 {
3177         s32 ret_val;
3178
3179         if (e1000_check_reset_block(hw))
3180                 return 0;
3181
3182         /*
3183          * ICH parts do not have a word in the NVM to determine
3184          * the default flow control setting, so we explicitly
3185          * set it to full.
3186          */
3187         if (hw->fc.requested_mode == e1000_fc_default) {
3188                 /* Workaround h/w hang when Tx flow control enabled */
3189                 if (hw->mac.type == e1000_pchlan)
3190                         hw->fc.requested_mode = e1000_fc_rx_pause;
3191                 else
3192                         hw->fc.requested_mode = e1000_fc_full;
3193         }
3194
3195         /*
3196          * Save off the requested flow control mode for use later.  Depending
3197          * on the link partner's capabilities, we may or may not use this mode.
3198          */
3199         hw->fc.current_mode = hw->fc.requested_mode;
3200
3201         e_dbg("After fix-ups FlowControl is now = %x\n",
3202                 hw->fc.current_mode);
3203
3204         /* Continue to configure the copper link. */
3205         ret_val = e1000_setup_copper_link_ich8lan(hw);
3206         if (ret_val)
3207                 return ret_val;
3208
3209         ew32(FCTTV, hw->fc.pause_time);
3210         if ((hw->phy.type == e1000_phy_82578) ||
3211             (hw->phy.type == e1000_phy_82579) ||
3212             (hw->phy.type == e1000_phy_82577)) {
3213                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3214
3215                 ret_val = hw->phy.ops.write_reg(hw,
3216                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
3217                                              hw->fc.pause_time);
3218                 if (ret_val)
3219                         return ret_val;
3220         }
3221
3222         return e1000e_set_fc_watermarks(hw);
3223 }
3224
3225 /**
3226  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3227  *  @hw: pointer to the HW structure
3228  *
3229  *  Configures the kumeran interface to the PHY to wait the appropriate time
3230  *  when polling the PHY, then call the generic setup_copper_link to finish
3231  *  configuring the copper link.
3232  **/
3233 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3234 {
3235         u32 ctrl;
3236         s32 ret_val;
3237         u16 reg_data;
3238
3239         ctrl = er32(CTRL);
3240         ctrl |= E1000_CTRL_SLU;
3241         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3242         ew32(CTRL, ctrl);
3243
3244         /*
3245          * Set the mac to wait the maximum time between each iteration
3246          * and increase the max iterations when polling the phy;
3247          * this fixes erroneous timeouts at 10Mbps.
3248          */
3249         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3250         if (ret_val)
3251                 return ret_val;
3252         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3253                                        &reg_data);
3254         if (ret_val)
3255                 return ret_val;
3256         reg_data |= 0x3F;
3257         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3258                                         reg_data);
3259         if (ret_val)
3260                 return ret_val;
3261
3262         switch (hw->phy.type) {
3263         case e1000_phy_igp_3:
3264                 ret_val = e1000e_copper_link_setup_igp(hw);
3265                 if (ret_val)
3266                         return ret_val;
3267                 break;
3268         case e1000_phy_bm:
3269         case e1000_phy_82578:
3270                 ret_val = e1000e_copper_link_setup_m88(hw);
3271                 if (ret_val)
3272                         return ret_val;
3273                 break;
3274         case e1000_phy_82577:
3275         case e1000_phy_82579:
3276                 ret_val = e1000_copper_link_setup_82577(hw);
3277                 if (ret_val)
3278                         return ret_val;
3279                 break;
3280         case e1000_phy_ife:
3281                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3282                                                &reg_data);
3283                 if (ret_val)
3284                         return ret_val;
3285
3286                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3287
3288                 switch (hw->phy.mdix) {
3289                 case 1:
3290                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3291                         break;
3292                 case 2:
3293                         reg_data |= IFE_PMC_FORCE_MDIX;
3294                         break;
3295                 case 0:
3296                 default:
3297                         reg_data |= IFE_PMC_AUTO_MDIX;
3298                         break;
3299                 }
3300                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3301                                                 reg_data);
3302                 if (ret_val)
3303                         return ret_val;
3304                 break;
3305         default:
3306                 break;
3307         }
3308         return e1000e_setup_copper_link(hw);
3309 }
3310
3311 /**
3312  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3313  *  @hw: pointer to the HW structure
3314  *  @speed: pointer to store current link speed
3315  *  @duplex: pointer to store the current link duplex
3316  *
3317  *  Calls the generic get_speed_and_duplex to retrieve the current link
3318  *  information and then calls the Kumeran lock loss workaround for links at
3319  *  gigabit speeds.
3320  **/
3321 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3322                                           u16 *duplex)
3323 {
3324         s32 ret_val;
3325
3326         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3327         if (ret_val)
3328                 return ret_val;
3329
3330         if ((hw->mac.type == e1000_ich8lan) &&
3331             (hw->phy.type == e1000_phy_igp_3) &&
3332             (*speed == SPEED_1000)) {
3333                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3334         }
3335
3336         return ret_val;
3337 }
3338
3339 /**
3340  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3341  *  @hw: pointer to the HW structure
3342  *
3343  *  Work-around for 82566 Kumeran PCS lock loss:
3344  *  On link status change (i.e. PCI reset, speed change) and link is up and
3345  *  speed is gigabit-
3346  *    0) if workaround is optionally disabled do nothing
3347  *    1) wait 1ms for Kumeran link to come up
3348  *    2) check Kumeran Diagnostic register PCS lock loss bit
3349  *    3) if not set the link is locked (all is good), otherwise...
3350  *    4) reset the PHY
3351  *    5) repeat up to 10 times
3352  *  Note: this is only called for IGP3 copper when speed is 1gb.
3353  **/
3354 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3355 {
3356         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3357         u32 phy_ctrl;
3358         s32 ret_val;
3359         u16 i, data;
3360         bool link;
3361
3362         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3363                 return 0;
3364
3365         /*
3366          * Make sure link is up before proceeding.  If not just return.
3367          * Attempting this while link is negotiating fouled up link
3368          * stability
3369          */
3370         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3371         if (!link)
3372                 return 0;
3373
3374         for (i = 0; i < 10; i++) {
3375                 /* read once to clear */
3376                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3377                 if (ret_val)
3378                         return ret_val;
3379                 /* and again to get new status */
3380                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3381                 if (ret_val)
3382                         return ret_val;
3383
3384                 /* check for PCS lock */
3385                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3386                         return 0;
3387
3388                 /* Issue PHY reset */
3389                 e1000_phy_hw_reset(hw);
3390                 mdelay(5);
3391         }
3392         /* Disable GigE link negotiation */
3393         phy_ctrl = er32(PHY_CTRL);
3394         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3395                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3396         ew32(PHY_CTRL, phy_ctrl);
3397
3398         /*
3399          * Call gig speed drop workaround on Gig disable before accessing
3400          * any PHY registers
3401          */
3402         e1000e_gig_downshift_workaround_ich8lan(hw);
3403
3404         /* unable to acquire PCS lock */
3405         return -E1000_ERR_PHY;
3406 }
3407
3408 /**
3409  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3410  *  @hw: pointer to the HW structure
3411  *  @state: boolean value used to set the current Kumeran workaround state
3412  *
3413  *  If ICH8, set the current Kumeran workaround state (enabled - true
3414  *  /disabled - false).
3415  **/
3416 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3417                                                  bool state)
3418 {
3419         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3420
3421         if (hw->mac.type != e1000_ich8lan) {
3422                 e_dbg("Workaround applies to ICH8 only.\n");
3423                 return;
3424         }
3425
3426         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3427 }
3428
3429 /**
3430  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3431  *  @hw: pointer to the HW structure
3432  *
3433  *  Workaround for 82566 power-down on D3 entry:
3434  *    1) disable gigabit link
3435  *    2) write VR power-down enable
3436  *    3) read it back
3437  *  Continue if successful, else issue LCD reset and repeat
3438  **/
3439 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3440 {
3441         u32 reg;
3442         u16 data;
3443         u8  retry = 0;
3444
3445         if (hw->phy.type != e1000_phy_igp_3)
3446                 return;
3447
3448         /* Try the workaround twice (if needed) */
3449         do {
3450                 /* Disable link */
3451                 reg = er32(PHY_CTRL);
3452                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3453                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3454                 ew32(PHY_CTRL, reg);
3455
3456                 /*
3457                  * Call gig speed drop workaround on Gig disable before
3458                  * accessing any PHY registers
3459                  */
3460                 if (hw->mac.type == e1000_ich8lan)
3461                         e1000e_gig_downshift_workaround_ich8lan(hw);
3462
3463                 /* Write VR power-down enable */
3464                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3465                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3466                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3467
3468                 /* Read it back and test */
3469                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3470                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3471                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3472                         break;
3473
3474                 /* Issue PHY reset and repeat at most one more time */
3475                 reg = er32(CTRL);
3476                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3477                 retry++;
3478         } while (retry);
3479 }
3480
3481 /**
3482  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3483  *  @hw: pointer to the HW structure
3484  *
3485  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3486  *  LPLU, Gig disable, MDIC PHY reset):
3487  *    1) Set Kumeran Near-end loopback
3488  *    2) Clear Kumeran Near-end loopback
3489  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3490  **/
3491 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3492 {
3493         s32 ret_val;
3494         u16 reg_data;
3495
3496         if ((hw->mac.type != e1000_ich8lan) ||
3497             (hw->phy.type != e1000_phy_igp_3))
3498                 return;
3499
3500         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3501                                       &reg_data);
3502         if (ret_val)
3503                 return;
3504         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3505         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3506                                        reg_data);
3507         if (ret_val)
3508                 return;
3509         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3510         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3511                                        reg_data);
3512 }
3513
3514 /**
3515  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3516  *  @hw: pointer to the HW structure
3517  *
3518  *  During S0 to Sx transition, it is possible the link remains at gig
3519  *  instead of negotiating to a lower speed.  Before going to Sx, set
3520  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3521  *  to a lower speed.
3522  *
3523  *  Should only be called for applicable parts.
3524  **/
3525 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3526 {
3527         u32 phy_ctrl;
3528         s32 ret_val;
3529
3530         phy_ctrl = er32(PHY_CTRL);
3531         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3532         ew32(PHY_CTRL, phy_ctrl);
3533
3534         if (hw->mac.type >= e1000_pchlan) {
3535                 e1000_oem_bits_config_ich8lan(hw, true);
3536                 ret_val = hw->phy.ops.acquire(hw);
3537                 if (ret_val)
3538                         return;
3539                 e1000_write_smbus_addr(hw);
3540                 hw->phy.ops.release(hw);
3541         }
3542 }
3543
3544 /**
3545  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3546  *  @hw: pointer to the HW structure
3547  *
3548  *  Return the LED back to the default configuration.
3549  **/
3550 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3551 {
3552         if (hw->phy.type == e1000_phy_ife)
3553                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3554
3555         ew32(LEDCTL, hw->mac.ledctl_default);
3556         return 0;
3557 }
3558
3559 /**
3560  *  e1000_led_on_ich8lan - Turn LEDs on
3561  *  @hw: pointer to the HW structure
3562  *
3563  *  Turn on the LEDs.
3564  **/
3565 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3566 {
3567         if (hw->phy.type == e1000_phy_ife)
3568                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3569                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3570
3571         ew32(LEDCTL, hw->mac.ledctl_mode2);
3572         return 0;
3573 }
3574
3575 /**
3576  *  e1000_led_off_ich8lan - Turn LEDs off
3577  *  @hw: pointer to the HW structure
3578  *
3579  *  Turn off the LEDs.
3580  **/
3581 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3582 {
3583         if (hw->phy.type == e1000_phy_ife)
3584                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3585                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3586
3587         ew32(LEDCTL, hw->mac.ledctl_mode1);
3588         return 0;
3589 }
3590
3591 /**
3592  *  e1000_setup_led_pchlan - Configures SW controllable LED
3593  *  @hw: pointer to the HW structure
3594  *
3595  *  This prepares the SW controllable LED for use.
3596  **/
3597 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3598 {
3599         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3600                                         (u16)hw->mac.ledctl_mode1);
3601 }
3602
3603 /**
3604  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3605  *  @hw: pointer to the HW structure
3606  *
3607  *  Return the LED back to the default configuration.
3608  **/
3609 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3610 {
3611         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3612                                         (u16)hw->mac.ledctl_default);
3613 }
3614
3615 /**
3616  *  e1000_led_on_pchlan - Turn LEDs on
3617  *  @hw: pointer to the HW structure
3618  *
3619  *  Turn on the LEDs.
3620  **/
3621 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3622 {
3623         u16 data = (u16)hw->mac.ledctl_mode2;
3624         u32 i, led;
3625
3626         /*
3627          * If no link, then turn LED on by setting the invert bit
3628          * for each LED that's mode is "link_up" in ledctl_mode2.
3629          */
3630         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3631                 for (i = 0; i < 3; i++) {
3632                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3633                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3634                             E1000_LEDCTL_MODE_LINK_UP)
3635                                 continue;
3636                         if (led & E1000_PHY_LED0_IVRT)
3637                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3638                         else
3639                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3640                 }
3641         }
3642
3643         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3644 }
3645
3646 /**
3647  *  e1000_led_off_pchlan - Turn LEDs off
3648  *  @hw: pointer to the HW structure
3649  *
3650  *  Turn off the LEDs.
3651  **/
3652 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3653 {
3654         u16 data = (u16)hw->mac.ledctl_mode1;
3655         u32 i, led;
3656
3657         /*
3658          * If no link, then turn LED off by clearing the invert bit
3659          * for each LED that's mode is "link_up" in ledctl_mode1.
3660          */
3661         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3662                 for (i = 0; i < 3; i++) {
3663                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3664                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3665                             E1000_LEDCTL_MODE_LINK_UP)
3666                                 continue;
3667                         if (led & E1000_PHY_LED0_IVRT)
3668                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3669                         else
3670                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3671                 }
3672         }
3673
3674         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3675 }
3676
3677 /**
3678  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3679  *  @hw: pointer to the HW structure
3680  *
3681  *  Read appropriate register for the config done bit for completion status
3682  *  and configure the PHY through s/w for EEPROM-less parts.
3683  *
3684  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3685  *  config done bit, so only an error is logged and continues.  If we were
3686  *  to return with error, EEPROM-less silicon would not be able to be reset
3687  *  or change link.
3688  **/
3689 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3690 {
3691         s32 ret_val = 0;
3692         u32 bank = 0;
3693         u32 status;
3694
3695         e1000e_get_cfg_done(hw);
3696
3697         /* Wait for indication from h/w that it has completed basic config */
3698         if (hw->mac.type >= e1000_ich10lan) {
3699                 e1000_lan_init_done_ich8lan(hw);
3700         } else {
3701                 ret_val = e1000e_get_auto_rd_done(hw);
3702                 if (ret_val) {
3703                         /*
3704                          * When auto config read does not complete, do not
3705                          * return with an error. This can happen in situations
3706                          * where there is no eeprom and prevents getting link.
3707                          */
3708                         e_dbg("Auto Read Done did not complete\n");
3709                         ret_val = 0;
3710                 }
3711         }
3712
3713         /* Clear PHY Reset Asserted bit */
3714         status = er32(STATUS);
3715         if (status & E1000_STATUS_PHYRA)
3716                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3717         else
3718                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3719
3720         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3721         if (hw->mac.type <= e1000_ich9lan) {
3722                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3723                     (hw->phy.type == e1000_phy_igp_3)) {
3724                         e1000e_phy_init_script_igp3(hw);
3725                 }
3726         } else {
3727                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3728                         /* Maybe we should do a basic PHY config */
3729                         e_dbg("EEPROM not present\n");
3730                         ret_val = -E1000_ERR_CONFIG;
3731                 }
3732         }
3733
3734         return ret_val;
3735 }
3736
3737 /**
3738  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3739  * @hw: pointer to the HW structure
3740  *
3741  * In the case of a PHY power down to save power, or to turn off link during a
3742  * driver unload, or wake on lan is not enabled, remove the link.
3743  **/
3744 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3745 {
3746         /* If the management interface is not enabled, then power down */
3747         if (!(hw->mac.ops.check_mng_mode(hw) ||
3748               hw->phy.ops.check_reset_block(hw)))
3749                 e1000_power_down_phy_copper(hw);
3750 }
3751
3752 /**
3753  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3754  *  @hw: pointer to the HW structure
3755  *
3756  *  Clears hardware counters specific to the silicon family and calls
3757  *  clear_hw_cntrs_generic to clear all general purpose counters.
3758  **/
3759 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3760 {
3761         u16 phy_data;
3762
3763         e1000e_clear_hw_cntrs_base(hw);
3764
3765         er32(ALGNERRC);
3766         er32(RXERRC);
3767         er32(TNCRS);
3768         er32(CEXTERR);
3769         er32(TSCTC);
3770         er32(TSCTFC);
3771
3772         er32(MGTPRC);
3773         er32(MGTPDC);
3774         er32(MGTPTC);
3775
3776         er32(IAC);
3777         er32(ICRXOC);
3778
3779         /* Clear PHY statistics registers */
3780         if ((hw->phy.type == e1000_phy_82578) ||
3781             (hw->phy.type == e1000_phy_82579) ||
3782             (hw->phy.type == e1000_phy_82577)) {
3783                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3784                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3785                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3786                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3787                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3788                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3789                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3790                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3791                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3792                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3793                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3794                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3795                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3796                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3797         }
3798 }
3799
3800 static struct e1000_mac_operations ich8_mac_ops = {
3801         .id_led_init            = e1000e_id_led_init,
3802         /* check_mng_mode dependent on mac type */
3803         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3804         /* cleanup_led dependent on mac type */
3805         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3806         .get_bus_info           = e1000_get_bus_info_ich8lan,
3807         .set_lan_id             = e1000_set_lan_id_single_port,
3808         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3809         /* led_on dependent on mac type */
3810         /* led_off dependent on mac type */
3811         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3812         .reset_hw               = e1000_reset_hw_ich8lan,
3813         .init_hw                = e1000_init_hw_ich8lan,
3814         .setup_link             = e1000_setup_link_ich8lan,
3815         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3816         /* id_led_init dependent on mac type */
3817 };
3818
3819 static struct e1000_phy_operations ich8_phy_ops = {
3820         .acquire                = e1000_acquire_swflag_ich8lan,
3821         .check_reset_block      = e1000_check_reset_block_ich8lan,
3822         .commit                 = NULL,
3823         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3824         .get_cable_length       = e1000e_get_cable_length_igp_2,
3825         .read_reg               = e1000e_read_phy_reg_igp,
3826         .release                = e1000_release_swflag_ich8lan,
3827         .reset                  = e1000_phy_hw_reset_ich8lan,
3828         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3829         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3830         .write_reg              = e1000e_write_phy_reg_igp,
3831 };
3832
3833 static struct e1000_nvm_operations ich8_nvm_ops = {
3834         .acquire                = e1000_acquire_nvm_ich8lan,
3835         .read                   = e1000_read_nvm_ich8lan,
3836         .release                = e1000_release_nvm_ich8lan,
3837         .update                 = e1000_update_nvm_checksum_ich8lan,
3838         .valid_led_default      = e1000_valid_led_default_ich8lan,
3839         .validate               = e1000_validate_nvm_checksum_ich8lan,
3840         .write                  = e1000_write_nvm_ich8lan,
3841 };
3842
3843 struct e1000_info e1000_ich8_info = {
3844         .mac                    = e1000_ich8lan,
3845         .flags                  = FLAG_HAS_WOL
3846                                   | FLAG_IS_ICH
3847                                   | FLAG_RX_CSUM_ENABLED
3848                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3849                                   | FLAG_HAS_AMT
3850                                   | FLAG_HAS_FLASH
3851                                   | FLAG_APME_IN_WUC,
3852         .pba                    = 8,
3853         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3854         .get_variants           = e1000_get_variants_ich8lan,
3855         .mac_ops                = &ich8_mac_ops,
3856         .phy_ops                = &ich8_phy_ops,
3857         .nvm_ops                = &ich8_nvm_ops,
3858 };
3859
3860 struct e1000_info e1000_ich9_info = {
3861         .mac                    = e1000_ich9lan,
3862         .flags                  = FLAG_HAS_JUMBO_FRAMES
3863                                   | FLAG_IS_ICH
3864                                   | FLAG_HAS_WOL
3865                                   | FLAG_RX_CSUM_ENABLED
3866                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3867                                   | FLAG_HAS_AMT
3868                                   | FLAG_HAS_ERT
3869                                   | FLAG_HAS_FLASH
3870                                   | FLAG_APME_IN_WUC,
3871         .pba                    = 10,
3872         .max_hw_frame_size      = DEFAULT_JUMBO,
3873         .get_variants           = e1000_get_variants_ich8lan,
3874         .mac_ops                = &ich8_mac_ops,
3875         .phy_ops                = &ich8_phy_ops,
3876         .nvm_ops                = &ich8_nvm_ops,
3877 };
3878
3879 struct e1000_info e1000_ich10_info = {
3880         .mac                    = e1000_ich10lan,
3881         .flags                  = FLAG_HAS_JUMBO_FRAMES
3882                                   | FLAG_IS_ICH
3883                                   | FLAG_HAS_WOL
3884                                   | FLAG_RX_CSUM_ENABLED
3885                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3886                                   | FLAG_HAS_AMT
3887                                   | FLAG_HAS_ERT
3888                                   | FLAG_HAS_FLASH
3889                                   | FLAG_APME_IN_WUC,
3890         .pba                    = 10,
3891         .max_hw_frame_size      = DEFAULT_JUMBO,
3892         .get_variants           = e1000_get_variants_ich8lan,
3893         .mac_ops                = &ich8_mac_ops,
3894         .phy_ops                = &ich8_phy_ops,
3895         .nvm_ops                = &ich8_nvm_ops,
3896 };
3897
3898 struct e1000_info e1000_pch_info = {
3899         .mac                    = e1000_pchlan,
3900         .flags                  = FLAG_IS_ICH
3901                                   | FLAG_HAS_WOL
3902                                   | FLAG_RX_CSUM_ENABLED
3903                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3904                                   | FLAG_HAS_AMT
3905                                   | FLAG_HAS_FLASH
3906                                   | FLAG_HAS_JUMBO_FRAMES
3907                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3908                                   | FLAG_APME_IN_WUC,
3909         .flags2                 = FLAG2_HAS_PHY_STATS,
3910         .pba                    = 26,
3911         .max_hw_frame_size      = 4096,
3912         .get_variants           = e1000_get_variants_ich8lan,
3913         .mac_ops                = &ich8_mac_ops,
3914         .phy_ops                = &ich8_phy_ops,
3915         .nvm_ops                = &ich8_nvm_ops,
3916 };
3917
3918 struct e1000_info e1000_pch2_info = {
3919         .mac                    = e1000_pch2lan,
3920         .flags                  = FLAG_IS_ICH
3921                                   | FLAG_HAS_WOL
3922                                   | FLAG_RX_CSUM_ENABLED
3923                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3924                                   | FLAG_HAS_AMT
3925                                   | FLAG_HAS_FLASH
3926                                   | FLAG_HAS_JUMBO_FRAMES
3927                                   | FLAG_APME_IN_WUC,
3928         .flags2                 = FLAG2_HAS_PHY_STATS
3929                                   | FLAG2_HAS_EEE,
3930         .pba                    = 18,
3931         .max_hw_frame_size      = DEFAULT_JUMBO,
3932         .get_variants           = e1000_get_variants_ich8lan,
3933         .mac_ops                = &ich8_mac_ops,
3934         .phy_ops                = &ich8_phy_ops,
3935         .nvm_ops                = &ich8_nvm_ops,
3936 };