drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 static void be_mcc_notify(struct be_adapter *adapter)
  22 {
  23         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  24         u32 val = 0;
  25
  26         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  27         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  28
  29         wmb();
  30         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  31 }
  32
  33 /* To check if valid bit is set, check the entire word as we don't know
  34  * the endianness of the data (old entry is host endian while a new entry is
  35  * little endian) */
  36 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  37 {
  38         if (compl->flags != 0) {
  39                 compl->flags = le32_to_cpu(compl->flags);
  40                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  41                 return true;
  42         } else {
  43                 return false;
  44         }
  45 }
  46
  47 /* Need to reset the entire word that houses the valid bit */
  48 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  49 {
  50         compl->flags = 0;
  51 }
  52
  53 static int be_mcc_compl_process(struct be_adapter *adapter,
  54         struct be_mcc_compl *compl)
  55 {
  56         u16 compl_status, extd_status;
  57
  58         /* Just swap the status to host endian; mcc tag is opaquely copied
  59          * from mcc_wrb */
  60         be_dws_le_to_cpu(compl, 4);
  61
  62         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  63                                 CQE_STATUS_COMPL_MASK;
  64
  65         if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
  66                 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  67                 adapter->flash_status = compl_status;
  68                 complete(&adapter->flash_compl);
  69         }
  70
  71         if (compl_status == MCC_STATUS_SUCCESS) {
  72                 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
  73                         struct be_cmd_resp_get_stats *resp =
  74                                                 adapter->stats.cmd.va;
  75                         be_dws_le_to_cpu(&resp->hw_stats,
  76                                                 sizeof(resp->hw_stats));
  77                         netdev_stats_update(adapter);
  78                         adapter->stats_ioctl_sent = false;
  79                 }
  80         } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
  81                    (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
  82                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
  83                                 CQE_STATUS_EXTD_MASK;
  84                 dev_warn(&adapter->pdev->dev,
  85                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
  86                         compl->tag0, compl_status, extd_status);
  87         }
  88         return compl_status;
  89 }
  90
  91 /* Link state evt is a string of bytes; no need for endian swapping */
  92 static void be_async_link_state_process(struct be_adapter *adapter,
  93                 struct be_async_event_link_state *evt)
  94 {
  95         be_link_status_update(adapter,
  96                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
  97 }
  98
  99 static inline bool is_link_state_evt(u32 trailer)
 100 {
 101         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 102                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 103                                 ASYNC_EVENT_CODE_LINK_STATE);
 104 }
 105
 106 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 107 {
 108         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 109         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 110
 111         if (be_mcc_compl_is_new(compl)) {
 112                 queue_tail_inc(mcc_cq);
 113                 return compl;
 114         }
 115         return NULL;
 116 }
 117
 118 void be_async_mcc_enable(struct be_adapter *adapter)
 119 {
 120         spin_lock_bh(&adapter->mcc_cq_lock);
 121
 122         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 123         adapter->mcc_obj.rearm_cq = true;
 124
 125         spin_unlock_bh(&adapter->mcc_cq_lock);
 126 }
 127
 128 void be_async_mcc_disable(struct be_adapter *adapter)
 129 {
 130         adapter->mcc_obj.rearm_cq = false;
 131 }
 132
 133 int be_process_mcc(struct be_adapter *adapter, int *status)
 134 {
 135         struct be_mcc_compl *compl;
 136         int num = 0;
 137         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 138
 139         spin_lock_bh(&adapter->mcc_cq_lock);
 140         while ((compl = be_mcc_compl_get(adapter))) {
 141                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 142                         /* Interpret flags as an async trailer */
 143                         BUG_ON(!is_link_state_evt(compl->flags));
 144
 145                         /* Interpret compl as a async link evt */
 146                         be_async_link_state_process(adapter,
 147                                 (struct be_async_event_link_state *) compl);
 148                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 149                                 *status = be_mcc_compl_process(adapter, compl);
 150                                 atomic_dec(&mcc_obj->q.used);
 151                 }
 152                 be_mcc_compl_use(compl);
 153                 num++;
 154         }
 155
 156         spin_unlock_bh(&adapter->mcc_cq_lock);
 157         return num;
 158 }
 159
 160 /* Wait till no more pending mcc requests are present */
 161 static int be_mcc_wait_compl(struct be_adapter *adapter)
 162 {
 163 #define mcc_timeout             120000 /* 12s timeout */
 164         int i, num, status = 0;
 165         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 166
 167         for (i = 0; i < mcc_timeout; i++) {
 168                 num = be_process_mcc(adapter, &status);
 169                 if (num)
 170                         be_cq_notify(adapter, mcc_obj->cq.id,
 171                                 mcc_obj->rearm_cq, num);
 172
 173                 if (atomic_read(&mcc_obj->q.used) == 0)
 174                         break;
 175                 udelay(100);
 176         }
 177         if (i == mcc_timeout) {
 178                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 179                 return -1;
 180         }
 181         return status;
 182 }
 183
 184 /* Notify MCC requests and wait for completion */
 185 static int be_mcc_notify_wait(struct be_adapter *adapter)
 186 {
 187         be_mcc_notify(adapter);
 188         return be_mcc_wait_compl(adapter);
 189 }
 190
 191 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 192 {
 193         int msecs = 0;
 194         u32 ready;
 195
 196         do {
 197                 ready = ioread32(db);
 198                 if (ready == 0xffffffff) {
 199                         dev_err(&adapter->pdev->dev,
 200                                 "pci slot disconnected\n");
 201                         return -1;
 202                 }
 203
 204                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 205                 if (ready)
 206                         break;
 207
 208                 if (msecs > 4000) {
 209                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 210                         be_dump_ue(adapter);
 211                         return -1;
 212                 }
 213
 214                 set_current_state(TASK_INTERRUPTIBLE);
 215                 schedule_timeout(msecs_to_jiffies(1));
 216                 msecs++;
 217         } while (true);
 218
 219         return 0;
 220 }
 221
 222 /*
 223  * Insert the mailbox address into the doorbell in two steps
 224  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 225  */
 226 static int be_mbox_notify_wait(struct be_adapter *adapter)
 227 {
 228         int status;
 229         u32 val = 0;
 230         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 231         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 232         struct be_mcc_mailbox *mbox = mbox_mem->va;
 233         struct be_mcc_compl *compl = &mbox->compl;
 234
 235         /* wait for ready to be set */
 236         status = be_mbox_db_ready_wait(adapter, db);
 237         if (status != 0)
 238                 return status;
 239
 240         val |= MPU_MAILBOX_DB_HI_MASK;
 241         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 242         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 243         iowrite32(val, db);
 244
 245         /* wait for ready to be set */
 246         status = be_mbox_db_ready_wait(adapter, db);
 247         if (status != 0)
 248                 return status;
 249
 250         val = 0;
 251         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 252         val |= (u32)(mbox_mem->dma >> 4) << 2;
 253         iowrite32(val, db);
 254
 255         status = be_mbox_db_ready_wait(adapter, db);
 256         if (status != 0)
 257                 return status;
 258
 259         /* A cq entry has been made now */
 260         if (be_mcc_compl_is_new(compl)) {
 261                 status = be_mcc_compl_process(adapter, &mbox->compl);
 262                 be_mcc_compl_use(compl);
 263                 if (status)
 264                         return status;
 265         } else {
 266                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 267                 return -1;
 268         }
 269         return 0;
 270 }
 271
 272 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 273 {
 274         u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 275
 276         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 277         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 278                 return -1;
 279         else
 280                 return 0;
 281 }
 282
 283 int be_cmd_POST(struct be_adapter *adapter)
 284 {
 285         u16 stage;
 286         int status, timeout = 0;
 287
 288         do {
 289                 status = be_POST_stage_get(adapter, &stage);
 290                 if (status) {
 291                         dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
 292                                 stage);
 293                         return -1;
 294                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 295                         set_current_state(TASK_INTERRUPTIBLE);
 296                         schedule_timeout(2 * HZ);
 297                         timeout += 2;
 298                 } else {
 299                         return 0;
 300                 }
 301         } while (timeout < 40);
 302
 303         dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
 304         return -1;
 305 }
 306
 307 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 308 {
 309         return wrb->payload.embedded_payload;
 310 }
 311
 312 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 313 {
 314         return &wrb->payload.sgl[0];
 315 }
 316
 317 /* Don't touch the hdr after it's prepared */
 318 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 319                                 bool embedded, u8 sge_cnt, u32 opcode)
 320 {
 321         if (embedded)
 322                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 323         else
 324                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 325                                 MCC_WRB_SGE_CNT_SHIFT;
 326         wrb->payload_length = payload_len;
 327         wrb->tag0 = opcode;
 328         be_dws_cpu_to_le(wrb, 8);
 329 }
 330
 331 /* Don't touch the hdr after it's prepared */
 332 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 333                                 u8 subsystem, u8 opcode, int cmd_len)
 334 {
 335         req_hdr->opcode = opcode;
 336         req_hdr->subsystem = subsystem;
 337         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 338         req_hdr->version = 0;
 339 }
 340
 341 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 342                         struct be_dma_mem *mem)
 343 {
 344         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 345         u64 dma = (u64)mem->dma;
 346
 347         for (i = 0; i < buf_pages; i++) {
 348                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 349                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 350                 dma += PAGE_SIZE_4K;
 351         }
 352 }
 353
 354 /* Converts interrupt delay in microseconds to multiplier value */
 355 static u32 eq_delay_to_mult(u32 usec_delay)
 356 {
 357 #define MAX_INTR_RATE                   651042
 358         const u32 round = 10;
 359         u32 multiplier;
 360
 361         if (usec_delay == 0)
 362                 multiplier = 0;
 363         else {
 364                 u32 interrupt_rate = 1000000 / usec_delay;
 365                 /* Max delay, corresponding to the lowest interrupt rate */
 366                 if (interrupt_rate == 0)
 367                         multiplier = 1023;
 368                 else {
 369                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 370                         multiplier /= interrupt_rate;
 371                         /* Round the multiplier to the closest value.*/
 372                         multiplier = (multiplier + round/2) / round;
 373                         multiplier = min(multiplier, (u32)1023);
 374                 }
 375         }
 376         return multiplier;
 377 }
 378
 379 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 380 {
 381         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 382         struct be_mcc_wrb *wrb
 383                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 384         memset(wrb, 0, sizeof(*wrb));
 385         return wrb;
 386 }
 387
 388 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 389 {
 390         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 391         struct be_mcc_wrb *wrb;
 392
 393         if (atomic_read(&mccq->used) >= mccq->len) {
 394                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 395                 return NULL;
 396         }
 397
 398         wrb = queue_head_node(mccq);
 399         queue_head_inc(mccq);
 400         atomic_inc(&mccq->used);
 401         memset(wrb, 0, sizeof(*wrb));
 402         return wrb;
 403 }
 404
 405 /* Tell fw we're about to start firing cmds by writing a
 406  * special pattern across the wrb hdr; uses mbox
 407  */
 408 int be_cmd_fw_init(struct be_adapter *adapter)
 409 {
 410         u8 *wrb;
 411         int status;
 412
 413         spin_lock(&adapter->mbox_lock);
 414
 415         wrb = (u8 *)wrb_from_mbox(adapter);
 416         *wrb++ = 0xFF;
 417         *wrb++ = 0x12;
 418         *wrb++ = 0x34;
 419         *wrb++ = 0xFF;
 420         *wrb++ = 0xFF;
 421         *wrb++ = 0x56;
 422         *wrb++ = 0x78;
 423         *wrb = 0xFF;
 424
 425         status = be_mbox_notify_wait(adapter);
 426
 427         spin_unlock(&adapter->mbox_lock);
 428         return status;
 429 }
 430
 431 /* Tell fw we're done with firing cmds by writing a
 432  * special pattern across the wrb hdr; uses mbox
 433  */
 434 int be_cmd_fw_clean(struct be_adapter *adapter)
 435 {
 436         u8 *wrb;
 437         int status;
 438
 439         if (adapter->eeh_err)
 440                 return -EIO;
 441
 442         spin_lock(&adapter->mbox_lock);
 443
 444         wrb = (u8 *)wrb_from_mbox(adapter);
 445         *wrb++ = 0xFF;
 446         *wrb++ = 0xAA;
 447         *wrb++ = 0xBB;
 448         *wrb++ = 0xFF;
 449         *wrb++ = 0xFF;
 450         *wrb++ = 0xCC;
 451         *wrb++ = 0xDD;
 452         *wrb = 0xFF;
 453
 454         status = be_mbox_notify_wait(adapter);
 455
 456         spin_unlock(&adapter->mbox_lock);
 457         return status;
 458 }
 459 int be_cmd_eq_create(struct be_adapter *adapter,
 460                 struct be_queue_info *eq, int eq_delay)
 461 {
 462         struct be_mcc_wrb *wrb;
 463         struct be_cmd_req_eq_create *req;
 464         struct be_dma_mem *q_mem = &eq->dma_mem;
 465         int status;
 466
 467         spin_lock(&adapter->mbox_lock);
 468
 469         wrb = wrb_from_mbox(adapter);
 470         req = embedded_payload(wrb);
 471
 472         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
 473
 474         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 475                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 476
 477         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 478
 479         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 480         /* 4byte eqe*/
 481         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 482         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 483                         __ilog2_u32(eq->len/256));
 484         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 485                         eq_delay_to_mult(eq_delay));
 486         be_dws_cpu_to_le(req->context, sizeof(req->context));
 487
 488         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 489
 490         status = be_mbox_notify_wait(adapter);
 491         if (!status) {
 492                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 493                 eq->id = le16_to_cpu(resp->eq_id);
 494                 eq->created = true;
 495         }
 496
 497         spin_unlock(&adapter->mbox_lock);
 498         return status;
 499 }
 500
 501 /* Uses mbox */
 502 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 503                         u8 type, bool permanent, u32 if_handle)
 504 {
 505         struct be_mcc_wrb *wrb;
 506         struct be_cmd_req_mac_query *req;
 507         int status;
 508
 509         spin_lock(&adapter->mbox_lock);
 510
 511         wrb = wrb_from_mbox(adapter);
 512         req = embedded_payload(wrb);
 513
 514         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 515                         OPCODE_COMMON_NTWK_MAC_QUERY);
 516
 517         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 518                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 519
 520         req->type = type;
 521         if (permanent) {
 522                 req->permanent = 1;
 523         } else {
 524                 req->if_id = cpu_to_le16((u16) if_handle);
 525                 req->permanent = 0;
 526         }
 527
 528         status = be_mbox_notify_wait(adapter);
 529         if (!status) {
 530                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 531                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 532         }
 533
 534         spin_unlock(&adapter->mbox_lock);
 535         return status;
 536 }
 537
 538 /* Uses synchronous MCCQ */
 539 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 540                 u32 if_id, u32 *pmac_id)
 541 {
 542         struct be_mcc_wrb *wrb;
 543         struct be_cmd_req_pmac_add *req;
 544         int status;
 545
 546         spin_lock_bh(&adapter->mcc_lock);
 547
 548         wrb = wrb_from_mccq(adapter);
 549         if (!wrb) {
 550                 status = -EBUSY;
 551                 goto err;
 552         }
 553         req = embedded_payload(wrb);
 554
 555         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 556                         OPCODE_COMMON_NTWK_PMAC_ADD);
 557
 558         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 559                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 560
 561         req->if_id = cpu_to_le32(if_id);
 562         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 563
 564         status = be_mcc_notify_wait(adapter);
 565         if (!status) {
 566                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 567                 *pmac_id = le32_to_cpu(resp->pmac_id);
 568         }
 569
 570 err:
 571         spin_unlock_bh(&adapter->mcc_lock);
 572         return status;
 573 }
 574
 575 /* Uses synchronous MCCQ */
 576 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
 577 {
 578         struct be_mcc_wrb *wrb;
 579         struct be_cmd_req_pmac_del *req;
 580         int status;
 581
 582         spin_lock_bh(&adapter->mcc_lock);
 583
 584         wrb = wrb_from_mccq(adapter);
 585         if (!wrb) {
 586                 status = -EBUSY;
 587                 goto err;
 588         }
 589         req = embedded_payload(wrb);
 590
 591         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 592                         OPCODE_COMMON_NTWK_PMAC_DEL);
 593
 594         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 595                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 596
 597         req->if_id = cpu_to_le32(if_id);
 598         req->pmac_id = cpu_to_le32(pmac_id);
 599
 600         status = be_mcc_notify_wait(adapter);
 601
 602 err:
 603         spin_unlock_bh(&adapter->mcc_lock);
 604         return status;
 605 }
 606
 607 /* Uses Mbox */
 608 int be_cmd_cq_create(struct be_adapter *adapter,
 609                 struct be_queue_info *cq, struct be_queue_info *eq,
 610                 bool sol_evts, bool no_delay, int coalesce_wm)
 611 {
 612         struct be_mcc_wrb *wrb;
 613         struct be_cmd_req_cq_create *req;
 614         struct be_dma_mem *q_mem = &cq->dma_mem;
 615         void *ctxt;
 616         int status;
 617
 618         spin_lock(&adapter->mbox_lock);
 619
 620         wrb = wrb_from_mbox(adapter);
 621         req = embedded_payload(wrb);
 622         ctxt = &req->context;
 623
 624         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 625                         OPCODE_COMMON_CQ_CREATE);
 626
 627         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 628                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 629
 630         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 631
 632         AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
 633         AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
 634         AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
 635                         __ilog2_u32(cq->len/256));
 636         AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
 637         AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
 638         AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
 639         AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
 640         AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
 641         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 642
 643         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 644
 645         status = be_mbox_notify_wait(adapter);
 646         if (!status) {
 647                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 648                 cq->id = le16_to_cpu(resp->cq_id);
 649                 cq->created = true;
 650         }
 651
 652         spin_unlock(&adapter->mbox_lock);
 653
 654         return status;
 655 }
 656
 657 static u32 be_encoded_q_len(int q_len)
 658 {
 659         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 660         if (len_encoded == 16)
 661                 len_encoded = 0;
 662         return len_encoded;
 663 }
 664
 665 int be_cmd_mccq_create(struct be_adapter *adapter,
 666                         struct be_queue_info *mccq,
 667                         struct be_queue_info *cq)
 668 {
 669         struct be_mcc_wrb *wrb;
 670         struct be_cmd_req_mcc_create *req;
 671         struct be_dma_mem *q_mem = &mccq->dma_mem;
 672         void *ctxt;
 673         int status;
 674
 675         spin_lock(&adapter->mbox_lock);
 676
 677         wrb = wrb_from_mbox(adapter);
 678         req = embedded_payload(wrb);
 679         ctxt = &req->context;
 680
 681         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 682                         OPCODE_COMMON_MCC_CREATE);
 683
 684         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 685                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
 686
 687         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 688
 689         AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
 690         AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
 691                 be_encoded_q_len(mccq->len));
 692         AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
 693
 694         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 695
 696         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 697
 698         status = be_mbox_notify_wait(adapter);
 699         if (!status) {
 700                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 701                 mccq->id = le16_to_cpu(resp->id);
 702                 mccq->created = true;
 703         }
 704         spin_unlock(&adapter->mbox_lock);
 705
 706         return status;
 707 }
 708
 709 int be_cmd_txq_create(struct be_adapter *adapter,
 710                         struct be_queue_info *txq,
 711                         struct be_queue_info *cq)
 712 {
 713         struct be_mcc_wrb *wrb;
 714         struct be_cmd_req_eth_tx_create *req;
 715         struct be_dma_mem *q_mem = &txq->dma_mem;
 716         void *ctxt;
 717         int status;
 718
 719         spin_lock(&adapter->mbox_lock);
 720
 721         wrb = wrb_from_mbox(adapter);
 722         req = embedded_payload(wrb);
 723         ctxt = &req->context;
 724
 725         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 726                         OPCODE_ETH_TX_CREATE);
 727
 728         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 729                 sizeof(*req));
 730
 731         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 732         req->ulp_num = BE_ULP1_NUM;
 733         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 734
 735         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 736                 be_encoded_q_len(txq->len));
 737         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 738         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 739
 740         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 741
 742         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 743
 744         status = be_mbox_notify_wait(adapter);
 745         if (!status) {
 746                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 747                 txq->id = le16_to_cpu(resp->cid);
 748                 txq->created = true;
 749         }
 750
 751         spin_unlock(&adapter->mbox_lock);
 752
 753         return status;
 754 }
 755
 756 /* Uses mbox */
 757 int be_cmd_rxq_create(struct be_adapter *adapter,
 758                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 759                 u16 max_frame_size, u32 if_id, u32 rss)
 760 {
 761         struct be_mcc_wrb *wrb;
 762         struct be_cmd_req_eth_rx_create *req;
 763         struct be_dma_mem *q_mem = &rxq->dma_mem;
 764         int status;
 765
 766         spin_lock(&adapter->mbox_lock);
 767
 768         wrb = wrb_from_mbox(adapter);
 769         req = embedded_payload(wrb);
 770
 771         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 772                         OPCODE_ETH_RX_CREATE);
 773
 774         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
 775                 sizeof(*req));
 776
 777         req->cq_id = cpu_to_le16(cq_id);
 778         req->frag_size = fls(frag_size) - 1;
 779         req->num_pages = 2;
 780         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 781         req->interface_id = cpu_to_le32(if_id);
 782         req->max_frame_size = cpu_to_le16(max_frame_size);
 783         req->rss_queue = cpu_to_le32(rss);
 784
 785         status = be_mbox_notify_wait(adapter);
 786         if (!status) {
 787                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
 788                 rxq->id = le16_to_cpu(resp->id);
 789                 rxq->created = true;
 790         }
 791
 792         spin_unlock(&adapter->mbox_lock);
 793
 794         return status;
 795 }
 796
 797 /* Generic destroyer function for all types of queues
 798  * Uses Mbox
 799  */
 800 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 801                 int queue_type)
 802 {
 803         struct be_mcc_wrb *wrb;
 804         struct be_cmd_req_q_destroy *req;
 805         u8 subsys = 0, opcode = 0;
 806         int status;
 807
 808         if (adapter->eeh_err)
 809                 return -EIO;
 810
 811         spin_lock(&adapter->mbox_lock);
 812
 813         wrb = wrb_from_mbox(adapter);
 814         req = embedded_payload(wrb);
 815
 816         switch (queue_type) {
 817         case QTYPE_EQ:
 818                 subsys = CMD_SUBSYSTEM_COMMON;
 819                 opcode = OPCODE_COMMON_EQ_DESTROY;
 820                 break;
 821         case QTYPE_CQ:
 822                 subsys = CMD_SUBSYSTEM_COMMON;
 823                 opcode = OPCODE_COMMON_CQ_DESTROY;
 824                 break;
 825         case QTYPE_TXQ:
 826                 subsys = CMD_SUBSYSTEM_ETH;
 827                 opcode = OPCODE_ETH_TX_DESTROY;
 828                 break;
 829         case QTYPE_RXQ:
 830                 subsys = CMD_SUBSYSTEM_ETH;
 831                 opcode = OPCODE_ETH_RX_DESTROY;
 832                 break;
 833         case QTYPE_MCCQ:
 834                 subsys = CMD_SUBSYSTEM_COMMON;
 835                 opcode = OPCODE_COMMON_MCC_DESTROY;
 836                 break;
 837         default:
 838                 BUG();
 839         }
 840
 841         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
 842
 843         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
 844         req->id = cpu_to_le16(q->id);
 845
 846         status = be_mbox_notify_wait(adapter);
 847
 848         spin_unlock(&adapter->mbox_lock);
 849
 850         return status;
 851 }
 852
 853 /* Create an rx filtering policy configuration on an i/f
 854  * Uses mbox
 855  */
 856 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
 857                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
 858                 u32 domain)
 859 {
 860         struct be_mcc_wrb *wrb;
 861         struct be_cmd_req_if_create *req;
 862         int status;
 863
 864         spin_lock(&adapter->mbox_lock);
 865
 866         wrb = wrb_from_mbox(adapter);
 867         req = embedded_payload(wrb);
 868
 869         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 870                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
 871
 872         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 873                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
 874
 875         req->hdr.domain = domain;
 876         req->capability_flags = cpu_to_le32(cap_flags);
 877         req->enable_flags = cpu_to_le32(en_flags);
 878         req->pmac_invalid = pmac_invalid;
 879         if (!pmac_invalid)
 880                 memcpy(req->mac_addr, mac, ETH_ALEN);
 881
 882         status = be_mbox_notify_wait(adapter);
 883         if (!status) {
 884                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
 885                 *if_handle = le32_to_cpu(resp->interface_id);
 886                 if (!pmac_invalid)
 887                         *pmac_id = le32_to_cpu(resp->pmac_id);
 888         }
 889
 890         spin_unlock(&adapter->mbox_lock);
 891         return status;
 892 }
 893
 894 /* Uses mbox */
 895 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
 896 {
 897         struct be_mcc_wrb *wrb;
 898         struct be_cmd_req_if_destroy *req;
 899         int status;
 900
 901         if (adapter->eeh_err)
 902                 return -EIO;
 903
 904         spin_lock(&adapter->mbox_lock);
 905
 906         wrb = wrb_from_mbox(adapter);
 907         req = embedded_payload(wrb);
 908
 909         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 910                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
 911
 912         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 913                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
 914
 915         req->interface_id = cpu_to_le32(interface_id);
 916
 917         status = be_mbox_notify_wait(adapter);
 918
 919         spin_unlock(&adapter->mbox_lock);
 920
 921         return status;
 922 }
 923
 924 /* Get stats is a non embedded command: the request is not embedded inside
 925  * WRB but is a separate dma memory block
 926  * Uses asynchronous MCC
 927  */
 928 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
 929 {
 930         struct be_mcc_wrb *wrb;
 931         struct be_cmd_req_get_stats *req;
 932         struct be_sge *sge;
 933         int status = 0;
 934
 935         spin_lock_bh(&adapter->mcc_lock);
 936
 937         wrb = wrb_from_mccq(adapter);
 938         if (!wrb) {
 939                 status = -EBUSY;
 940                 goto err;
 941         }
 942         req = nonemb_cmd->va;
 943         sge = nonembedded_sgl(wrb);
 944
 945         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
 946                         OPCODE_ETH_GET_STATISTICS);
 947
 948         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 949                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
 950         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
 951         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
 952         sge->len = cpu_to_le32(nonemb_cmd->size);
 953
 954         be_mcc_notify(adapter);
 955         adapter->stats_ioctl_sent = true;
 956
 957 err:
 958         spin_unlock_bh(&adapter->mcc_lock);
 959         return status;
 960 }
 961
 962 /* Uses synchronous mcc */
 963 int be_cmd_link_status_query(struct be_adapter *adapter,
 964                         bool *link_up, u8 *mac_speed, u16 *link_speed)
 965 {
 966         struct be_mcc_wrb *wrb;
 967         struct be_cmd_req_link_status *req;
 968         int status;
 969
 970         spin_lock_bh(&adapter->mcc_lock);
 971
 972         wrb = wrb_from_mccq(adapter);
 973         if (!wrb) {
 974                 status = -EBUSY;
 975                 goto err;
 976         }
 977         req = embedded_payload(wrb);
 978
 979         *link_up = false;
 980
 981         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 982                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
 983
 984         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 985                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
 986
 987         status = be_mcc_notify_wait(adapter);
 988         if (!status) {
 989                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
 990                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
 991                         *link_up = true;
 992                         *link_speed = le16_to_cpu(resp->link_speed);
 993                         *mac_speed = resp->mac_speed;
 994                 }
 995         }
 996
 997 err:
 998         spin_unlock_bh(&adapter->mcc_lock);
 999         return status;
1000 }
1001
1002 /* Uses Mbox */
1003 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1004 {
1005         struct be_mcc_wrb *wrb;
1006         struct be_cmd_req_get_fw_version *req;
1007         int status;
1008
1009         spin_lock(&adapter->mbox_lock);
1010
1011         wrb = wrb_from_mbox(adapter);
1012         req = embedded_payload(wrb);
1013
1014         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1015                         OPCODE_COMMON_GET_FW_VERSION);
1016
1017         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1018                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1019
1020         status = be_mbox_notify_wait(adapter);
1021         if (!status) {
1022                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1023                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1024         }
1025
1026         spin_unlock(&adapter->mbox_lock);
1027         return status;
1028 }
1029
1030 /* set the EQ delay interval of an EQ to specified value
1031  * Uses async mcc
1032  */
1033 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1034 {
1035         struct be_mcc_wrb *wrb;
1036         struct be_cmd_req_modify_eq_delay *req;
1037         int status = 0;
1038
1039         spin_lock_bh(&adapter->mcc_lock);
1040
1041         wrb = wrb_from_mccq(adapter);
1042         if (!wrb) {
1043                 status = -EBUSY;
1044                 goto err;
1045         }
1046         req = embedded_payload(wrb);
1047
1048         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1049                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1050
1051         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1052                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1053
1054         req->num_eq = cpu_to_le32(1);
1055         req->delay[0].eq_id = cpu_to_le32(eq_id);
1056         req->delay[0].phase = 0;
1057         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1058
1059         be_mcc_notify(adapter);
1060
1061 err:
1062         spin_unlock_bh(&adapter->mcc_lock);
1063         return status;
1064 }
1065
1066 /* Uses sycnhronous mcc */
1067 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1068                         u32 num, bool untagged, bool promiscuous)
1069 {
1070         struct be_mcc_wrb *wrb;
1071         struct be_cmd_req_vlan_config *req;
1072         int status;
1073
1074         spin_lock_bh(&adapter->mcc_lock);
1075
1076         wrb = wrb_from_mccq(adapter);
1077         if (!wrb) {
1078                 status = -EBUSY;
1079                 goto err;
1080         }
1081         req = embedded_payload(wrb);
1082
1083         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1084                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1085
1086         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1087                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1088
1089         req->interface_id = if_id;
1090         req->promiscuous = promiscuous;
1091         req->untagged = untagged;
1092         req->num_vlan = num;
1093         if (!promiscuous) {
1094                 memcpy(req->normal_vlan, vtag_array,
1095                         req->num_vlan * sizeof(vtag_array[0]));
1096         }
1097
1098         status = be_mcc_notify_wait(adapter);
1099
1100 err:
1101         spin_unlock_bh(&adapter->mcc_lock);
1102         return status;
1103 }
1104
1105 /* Uses MCC for this command as it may be called in BH context
1106  * Uses synchronous mcc
1107  */
1108 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1109 {
1110         struct be_mcc_wrb *wrb;
1111         struct be_cmd_req_promiscuous_config *req;
1112         int status;
1113
1114         spin_lock_bh(&adapter->mcc_lock);
1115
1116         wrb = wrb_from_mccq(adapter);
1117         if (!wrb) {
1118                 status = -EBUSY;
1119                 goto err;
1120         }
1121         req = embedded_payload(wrb);
1122
1123         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1124
1125         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1126                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1127
1128         /* In FW versions X.102.149/X.101.487 and later,
1129          * the port setting associated only with the
1130          * issuing pci function will take effect
1131          */
1132         if (port_num)
1133                 req->port1_promiscuous = en;
1134         else
1135                 req->port0_promiscuous = en;
1136
1137         status = be_mcc_notify_wait(adapter);
1138
1139 err:
1140         spin_unlock_bh(&adapter->mcc_lock);
1141         return status;
1142 }
1143
1144 /*
1145  * Uses MCC for this command as it may be called in BH context
1146  * (mc == NULL) => multicast promiscous
1147  */
1148 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1149                 struct net_device *netdev, struct be_dma_mem *mem)
1150 {
1151         struct be_mcc_wrb *wrb;
1152         struct be_cmd_req_mcast_mac_config *req = mem->va;
1153         struct be_sge *sge;
1154         int status;
1155
1156         spin_lock_bh(&adapter->mcc_lock);
1157
1158         wrb = wrb_from_mccq(adapter);
1159         if (!wrb) {
1160                 status = -EBUSY;
1161                 goto err;
1162         }
1163         sge = nonembedded_sgl(wrb);
1164         memset(req, 0, sizeof(*req));
1165
1166         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1167                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1168         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1169         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1170         sge->len = cpu_to_le32(mem->size);
1171
1172         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1173                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1174
1175         req->interface_id = if_id;
1176         if (netdev) {
1177                 int i;
1178                 struct netdev_hw_addr *ha;
1179
1180                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1181
1182                 i = 0;
1183                 netdev_for_each_mc_addr(ha, netdev)
1184                         memcpy(req->mac[i].byte, ha->addr, ETH_ALEN);
1185         } else {
1186                 req->promiscuous = 1;
1187         }
1188
1189         status = be_mcc_notify_wait(adapter);
1190
1191 err:
1192         spin_unlock_bh(&adapter->mcc_lock);
1193         return status;
1194 }
1195
1196 /* Uses synchrounous mcc */
1197 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1198 {
1199         struct be_mcc_wrb *wrb;
1200         struct be_cmd_req_set_flow_control *req;
1201         int status;
1202
1203         spin_lock_bh(&adapter->mcc_lock);
1204
1205         wrb = wrb_from_mccq(adapter);
1206         if (!wrb) {
1207                 status = -EBUSY;
1208                 goto err;
1209         }
1210         req = embedded_payload(wrb);
1211
1212         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1213                         OPCODE_COMMON_SET_FLOW_CONTROL);
1214
1215         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1216                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1217
1218         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1219         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1220
1221         status = be_mcc_notify_wait(adapter);
1222
1223 err:
1224         spin_unlock_bh(&adapter->mcc_lock);
1225         return status;
1226 }
1227
1228 /* Uses sycn mcc */
1229 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1230 {
1231         struct be_mcc_wrb *wrb;
1232         struct be_cmd_req_get_flow_control *req;
1233         int status;
1234
1235         spin_lock_bh(&adapter->mcc_lock);
1236
1237         wrb = wrb_from_mccq(adapter);
1238         if (!wrb) {
1239                 status = -EBUSY;
1240                 goto err;
1241         }
1242         req = embedded_payload(wrb);
1243
1244         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1245                         OPCODE_COMMON_GET_FLOW_CONTROL);
1246
1247         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1248                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1249
1250         status = be_mcc_notify_wait(adapter);
1251         if (!status) {
1252                 struct be_cmd_resp_get_flow_control *resp =
1253                                                 embedded_payload(wrb);
1254                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1255                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1256         }
1257
1258 err:
1259         spin_unlock_bh(&adapter->mcc_lock);
1260         return status;
1261 }
1262
1263 /* Uses mbox */
1264 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *mode)
1265 {
1266         struct be_mcc_wrb *wrb;
1267         struct be_cmd_req_query_fw_cfg *req;
1268         int status;
1269
1270         spin_lock(&adapter->mbox_lock);
1271
1272         wrb = wrb_from_mbox(adapter);
1273         req = embedded_payload(wrb);
1274
1275         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1276                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1277
1278         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1279                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1280
1281         status = be_mbox_notify_wait(adapter);
1282         if (!status) {
1283                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1284                 *port_num = le32_to_cpu(resp->phys_port);
1285                 *mode = le32_to_cpu(resp->function_mode);
1286         }
1287
1288         spin_unlock(&adapter->mbox_lock);
1289         return status;
1290 }
1291
1292 /* Uses mbox */
1293 int be_cmd_reset_function(struct be_adapter *adapter)
1294 {
1295         struct be_mcc_wrb *wrb;
1296         struct be_cmd_req_hdr *req;
1297         int status;
1298
1299         spin_lock(&adapter->mbox_lock);
1300
1301         wrb = wrb_from_mbox(adapter);
1302         req = embedded_payload(wrb);
1303
1304         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1305                         OPCODE_COMMON_FUNCTION_RESET);
1306
1307         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1308                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1309
1310         status = be_mbox_notify_wait(adapter);
1311
1312         spin_unlock(&adapter->mbox_lock);
1313         return status;
1314 }
1315
1316 /* Uses sync mcc */
1317 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1318                         u8 bcn, u8 sts, u8 state)
1319 {
1320         struct be_mcc_wrb *wrb;
1321         struct be_cmd_req_enable_disable_beacon *req;
1322         int status;
1323
1324         spin_lock_bh(&adapter->mcc_lock);
1325
1326         wrb = wrb_from_mccq(adapter);
1327         if (!wrb) {
1328                 status = -EBUSY;
1329                 goto err;
1330         }
1331         req = embedded_payload(wrb);
1332
1333         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1334                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1335
1336         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1337                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1338
1339         req->port_num = port_num;
1340         req->beacon_state = state;
1341         req->beacon_duration = bcn;
1342         req->status_duration = sts;
1343
1344         status = be_mcc_notify_wait(adapter);
1345
1346 err:
1347         spin_unlock_bh(&adapter->mcc_lock);
1348         return status;
1349 }
1350
1351 /* Uses sync mcc */
1352 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1353 {
1354         struct be_mcc_wrb *wrb;
1355         struct be_cmd_req_get_beacon_state *req;
1356         int status;
1357
1358         spin_lock_bh(&adapter->mcc_lock);
1359
1360         wrb = wrb_from_mccq(adapter);
1361         if (!wrb) {
1362                 status = -EBUSY;
1363                 goto err;
1364         }
1365         req = embedded_payload(wrb);
1366
1367         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1368                         OPCODE_COMMON_GET_BEACON_STATE);
1369
1370         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1371                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1372
1373         req->port_num = port_num;
1374
1375         status = be_mcc_notify_wait(adapter);
1376         if (!status) {
1377                 struct be_cmd_resp_get_beacon_state *resp =
1378                                                 embedded_payload(wrb);
1379                 *state = resp->beacon_state;
1380         }
1381
1382 err:
1383         spin_unlock_bh(&adapter->mcc_lock);
1384         return status;
1385 }
1386
1387 /* Uses sync mcc */
1388 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1389                                 u8 *connector)
1390 {
1391         struct be_mcc_wrb *wrb;
1392         struct be_cmd_req_port_type *req;
1393         int status;
1394
1395         spin_lock_bh(&adapter->mcc_lock);
1396
1397         wrb = wrb_from_mccq(adapter);
1398         if (!wrb) {
1399                 status = -EBUSY;
1400                 goto err;
1401         }
1402         req = embedded_payload(wrb);
1403
1404         be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1405                         OPCODE_COMMON_READ_TRANSRECV_DATA);
1406
1407         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1408                 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1409
1410         req->port = cpu_to_le32(port);
1411         req->page_num = cpu_to_le32(TR_PAGE_A0);
1412         status = be_mcc_notify_wait(adapter);
1413         if (!status) {
1414                 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1415                         *connector = resp->data.connector;
1416         }
1417
1418 err:
1419         spin_unlock_bh(&adapter->mcc_lock);
1420         return status;
1421 }
1422
1423 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1424                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1425 {
1426         struct be_mcc_wrb *wrb;
1427         struct be_cmd_write_flashrom *req;
1428         struct be_sge *sge;
1429         int status;
1430
1431         spin_lock_bh(&adapter->mcc_lock);
1432         adapter->flash_status = 0;
1433
1434         wrb = wrb_from_mccq(adapter);
1435         if (!wrb) {
1436                 status = -EBUSY;
1437                 goto err_unlock;
1438         }
1439         req = cmd->va;
1440         sge = nonembedded_sgl(wrb);
1441
1442         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1443                         OPCODE_COMMON_WRITE_FLASHROM);
1444         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1445
1446         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1447                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1448         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1449         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1450         sge->len = cpu_to_le32(cmd->size);
1451
1452         req->params.op_type = cpu_to_le32(flash_type);
1453         req->params.op_code = cpu_to_le32(flash_opcode);
1454         req->params.data_buf_size = cpu_to_le32(buf_size);
1455
1456         be_mcc_notify(adapter);
1457         spin_unlock_bh(&adapter->mcc_lock);
1458
1459         if (!wait_for_completion_timeout(&adapter->flash_compl,
1460                         msecs_to_jiffies(12000)))
1461                 status = -1;
1462         else
1463                 status = adapter->flash_status;
1464
1465         return status;
1466
1467 err_unlock:
1468         spin_unlock_bh(&adapter->mcc_lock);
1469         return status;
1470 }
1471
1472 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1473                          int offset)
1474 {
1475         struct be_mcc_wrb *wrb;
1476         struct be_cmd_write_flashrom *req;
1477         int status;
1478
1479         spin_lock_bh(&adapter->mcc_lock);
1480
1481         wrb = wrb_from_mccq(adapter);
1482         if (!wrb) {
1483                 status = -EBUSY;
1484                 goto err;
1485         }
1486         req = embedded_payload(wrb);
1487
1488         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1489                         OPCODE_COMMON_READ_FLASHROM);
1490
1491         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1492                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1493
1494         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1495         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1496         req->params.offset = cpu_to_le32(offset);
1497         req->params.data_buf_size = cpu_to_le32(0x4);
1498
1499         status = be_mcc_notify_wait(adapter);
1500         if (!status)
1501                 memcpy(flashed_crc, req->params.data_buf, 4);
1502
1503 err:
1504         spin_unlock_bh(&adapter->mcc_lock);
1505         return status;
1506 }
1507
1508 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1509                                 struct be_dma_mem *nonemb_cmd)
1510 {
1511         struct be_mcc_wrb *wrb;
1512         struct be_cmd_req_acpi_wol_magic_config *req;
1513         struct be_sge *sge;
1514         int status;
1515
1516         spin_lock_bh(&adapter->mcc_lock);
1517
1518         wrb = wrb_from_mccq(adapter);
1519         if (!wrb) {
1520                 status = -EBUSY;
1521                 goto err;
1522         }
1523         req = nonemb_cmd->va;
1524         sge = nonembedded_sgl(wrb);
1525
1526         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1527                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1528
1529         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1530                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1531         memcpy(req->magic_mac, mac, ETH_ALEN);
1532
1533         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1534         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1535         sge->len = cpu_to_le32(nonemb_cmd->size);
1536
1537         status = be_mcc_notify_wait(adapter);
1538
1539 err:
1540         spin_unlock_bh(&adapter->mcc_lock);
1541         return status;
1542 }
1543
1544 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1545                         u8 loopback_type, u8 enable)
1546 {
1547         struct be_mcc_wrb *wrb;
1548         struct be_cmd_req_set_lmode *req;
1549         int status;
1550
1551         spin_lock_bh(&adapter->mcc_lock);
1552
1553         wrb = wrb_from_mccq(adapter);
1554         if (!wrb) {
1555                 status = -EBUSY;
1556                 goto err;
1557         }
1558
1559         req = embedded_payload(wrb);
1560
1561         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1562                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1563
1564         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1565                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1566                         sizeof(*req));
1567
1568         req->src_port = port_num;
1569         req->dest_port = port_num;
1570         req->loopback_type = loopback_type;
1571         req->loopback_state = enable;
1572
1573         status = be_mcc_notify_wait(adapter);
1574 err:
1575         spin_unlock_bh(&adapter->mcc_lock);
1576         return status;
1577 }
1578
1579 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1580                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1581 {
1582         struct be_mcc_wrb *wrb;
1583         struct be_cmd_req_loopback_test *req;
1584         int status;
1585
1586         spin_lock_bh(&adapter->mcc_lock);
1587
1588         wrb = wrb_from_mccq(adapter);
1589         if (!wrb) {
1590                 status = -EBUSY;
1591                 goto err;
1592         }
1593
1594         req = embedded_payload(wrb);
1595
1596         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1597                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1598
1599         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1600                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1601         req->hdr.timeout = cpu_to_le32(4);
1602
1603         req->pattern = cpu_to_le64(pattern);
1604         req->src_port = cpu_to_le32(port_num);
1605         req->dest_port = cpu_to_le32(port_num);
1606         req->pkt_size = cpu_to_le32(pkt_size);
1607         req->num_pkts = cpu_to_le32(num_pkts);
1608         req->loopback_type = cpu_to_le32(loopback_type);
1609
1610         status = be_mcc_notify_wait(adapter);
1611         if (!status) {
1612                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1613                 status = le32_to_cpu(resp->status);
1614         }
1615
1616 err:
1617         spin_unlock_bh(&adapter->mcc_lock);
1618         return status;
1619 }
1620
1621 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1622                                 u32 byte_cnt, struct be_dma_mem *cmd)
1623 {
1624         struct be_mcc_wrb *wrb;
1625         struct be_cmd_req_ddrdma_test *req;
1626         struct be_sge *sge;
1627         int status;
1628         int i, j = 0;
1629
1630         spin_lock_bh(&adapter->mcc_lock);
1631
1632         wrb = wrb_from_mccq(adapter);
1633         if (!wrb) {
1634                 status = -EBUSY;
1635                 goto err;
1636         }
1637         req = cmd->va;
1638         sge = nonembedded_sgl(wrb);
1639         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1640                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1641         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1642                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1643
1644         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1645         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1646         sge->len = cpu_to_le32(cmd->size);
1647
1648         req->pattern = cpu_to_le64(pattern);
1649         req->byte_count = cpu_to_le32(byte_cnt);
1650         for (i = 0; i < byte_cnt; i++) {
1651                 req->snd_buff[i] = (u8)(pattern >> (j*8));
1652                 j++;
1653                 if (j > 7)
1654                         j = 0;
1655         }
1656
1657         status = be_mcc_notify_wait(adapter);
1658
1659         if (!status) {
1660                 struct be_cmd_resp_ddrdma_test *resp;
1661                 resp = cmd->va;
1662                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1663                                 resp->snd_err) {
1664                         status = -1;
1665                 }
1666         }
1667
1668 err:
1669         spin_unlock_bh(&adapter->mcc_lock);
1670         return status;
1671 }
1672
1673 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1674                                 struct be_dma_mem *nonemb_cmd)
1675 {
1676         struct be_mcc_wrb *wrb;
1677         struct be_cmd_req_seeprom_read *req;
1678         struct be_sge *sge;
1679         int status;
1680
1681         spin_lock_bh(&adapter->mcc_lock);
1682
1683         wrb = wrb_from_mccq(adapter);
1684         req = nonemb_cmd->va;
1685         sge = nonembedded_sgl(wrb);
1686
1687         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1688                         OPCODE_COMMON_SEEPROM_READ);
1689
1690         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1691                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1692
1693         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1694         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1695         sge->len = cpu_to_le32(nonemb_cmd->size);
1696
1697         status = be_mcc_notify_wait(adapter);
1698
1699         spin_unlock_bh(&adapter->mcc_lock);
1700         return status;
1701 }
1702
1703 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
1704 {
1705         struct be_mcc_wrb *wrb;
1706         struct be_cmd_req_get_phy_info *req;
1707         struct be_sge *sge;
1708         int status;
1709
1710         spin_lock_bh(&adapter->mcc_lock);
1711
1712         wrb = wrb_from_mccq(adapter);
1713         if (!wrb) {
1714                 status = -EBUSY;
1715                 goto err;
1716         }
1717
1718         req = cmd->va;
1719         sge = nonembedded_sgl(wrb);
1720
1721         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1722                                 OPCODE_COMMON_GET_PHY_DETAILS);
1723
1724         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1725                         OPCODE_COMMON_GET_PHY_DETAILS,
1726                         sizeof(*req));
1727
1728         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1729         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1730         sge->len = cpu_to_le32(cmd->size);
1731
1732         status = be_mcc_notify_wait(adapter);
1733 err:
1734         spin_unlock_bh(&adapter->mcc_lock);
1735         return status;
1736 }
1737
1738 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
1739 {
1740         struct be_mcc_wrb *wrb;
1741         struct be_cmd_req_set_qos *req;
1742         int status;
1743
1744         spin_lock_bh(&adapter->mcc_lock);
1745
1746         wrb = wrb_from_mccq(adapter);
1747         if (!wrb) {
1748                 status = -EBUSY;
1749                 goto err;
1750         }
1751
1752         req = embedded_payload(wrb);
1753
1754         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1755                                 OPCODE_COMMON_SET_QOS);
1756
1757         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1758                         OPCODE_COMMON_SET_QOS, sizeof(*req));
1759
1760         req->hdr.domain = domain;
1761         req->valid_bits = BE_QOS_BITS_NIC;
1762         req->max_bps_nic = bps;
1763
1764         status = be_mcc_notify_wait(adapter);
1765
1766 err:
1767         spin_unlock_bh(&adapter->mcc_lock);
1768         return status;
1769 }