drivers/mtd/onenand/samsung.c

   1 /*
   2  * Samsung S3C64XX/S5PC1XX OneNAND driver
   3  *
   4  *  Copyright © 2008-2010 Samsung Electronics
   5  *  Kyungmin Park <kyungmin.park@samsung.com>
   6  *  Marek Szyprowski <m.szyprowski@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Implementation:
  13  *      S3C64XX and S5PC100: emulate the pseudo BufferRAM
  14  *      S5PC110: use DMA
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/onenand.h>
  23 #include <linux/mtd/partitions.h>
  24 #include <linux/dma-mapping.h>
  25
  26 #include <asm/mach/flash.h>
  27 #include <plat/regs-onenand.h>
  28
  29 #include <linux/io.h>
  30
  31 enum soc_type {
  32         TYPE_S3C6400,
  33         TYPE_S3C6410,
  34         TYPE_S5PC100,
  35         TYPE_S5PC110,
  36 };
  37
  38 #define ONENAND_ERASE_STATUS            0x00
  39 #define ONENAND_MULTI_ERASE_SET         0x01
  40 #define ONENAND_ERASE_START             0x03
  41 #define ONENAND_UNLOCK_START            0x08
  42 #define ONENAND_UNLOCK_END              0x09
  43 #define ONENAND_LOCK_START              0x0A
  44 #define ONENAND_LOCK_END                0x0B
  45 #define ONENAND_LOCK_TIGHT_START        0x0C
  46 #define ONENAND_LOCK_TIGHT_END          0x0D
  47 #define ONENAND_UNLOCK_ALL              0x0E
  48 #define ONENAND_OTP_ACCESS              0x12
  49 #define ONENAND_SPARE_ACCESS_ONLY       0x13
  50 #define ONENAND_MAIN_ACCESS_ONLY        0x14
  51 #define ONENAND_ERASE_VERIFY            0x15
  52 #define ONENAND_MAIN_SPARE_ACCESS       0x16
  53 #define ONENAND_PIPELINE_READ           0x4000
  54
  55 #define MAP_00                          (0x0)
  56 #define MAP_01                          (0x1)
  57 #define MAP_10                          (0x2)
  58 #define MAP_11                          (0x3)
  59
  60 #define S3C64XX_CMD_MAP_SHIFT           24
  61 #define S5PC1XX_CMD_MAP_SHIFT           26
  62
  63 #define S3C6400_FBA_SHIFT               10
  64 #define S3C6400_FPA_SHIFT               4
  65 #define S3C6400_FSA_SHIFT               2
  66
  67 #define S3C6410_FBA_SHIFT               12
  68 #define S3C6410_FPA_SHIFT               6
  69 #define S3C6410_FSA_SHIFT               4
  70
  71 #define S5PC100_FBA_SHIFT               13
  72 #define S5PC100_FPA_SHIFT               7
  73 #define S5PC100_FSA_SHIFT               5
  74
  75 /* S5PC110 specific definitions */
  76 #define S5PC110_DMA_SRC_ADDR            0x400
  77 #define S5PC110_DMA_SRC_CFG             0x404
  78 #define S5PC110_DMA_DST_ADDR            0x408
  79 #define S5PC110_DMA_DST_CFG             0x40C
  80 #define S5PC110_DMA_TRANS_SIZE          0x414
  81 #define S5PC110_DMA_TRANS_CMD           0x418
  82 #define S5PC110_DMA_TRANS_STATUS        0x41C
  83 #define S5PC110_DMA_TRANS_DIR           0x420
  84
  85 #define S5PC110_DMA_CFG_SINGLE          (0x0 << 16)
  86 #define S5PC110_DMA_CFG_4BURST          (0x2 << 16)
  87 #define S5PC110_DMA_CFG_8BURST          (0x3 << 16)
  88 #define S5PC110_DMA_CFG_16BURST         (0x4 << 16)
  89
  90 #define S5PC110_DMA_CFG_INC             (0x0 << 8)
  91 #define S5PC110_DMA_CFG_CNT             (0x1 << 8)
  92
  93 #define S5PC110_DMA_CFG_8BIT            (0x0 << 0)
  94 #define S5PC110_DMA_CFG_16BIT           (0x1 << 0)
  95 #define S5PC110_DMA_CFG_32BIT           (0x2 << 0)
  96
  97 #define S5PC110_DMA_SRC_CFG_READ        (S5PC110_DMA_CFG_16BURST | \
  98                                         S5PC110_DMA_CFG_INC | \
  99                                         S5PC110_DMA_CFG_16BIT)
 100 #define S5PC110_DMA_DST_CFG_READ        (S5PC110_DMA_CFG_16BURST | \
 101                                         S5PC110_DMA_CFG_INC | \
 102                                         S5PC110_DMA_CFG_32BIT)
 103 #define S5PC110_DMA_SRC_CFG_WRITE       (S5PC110_DMA_CFG_16BURST | \
 104                                         S5PC110_DMA_CFG_INC | \
 105                                         S5PC110_DMA_CFG_32BIT)
 106 #define S5PC110_DMA_DST_CFG_WRITE       (S5PC110_DMA_CFG_16BURST | \
 107                                         S5PC110_DMA_CFG_INC | \
 108                                         S5PC110_DMA_CFG_16BIT)
 109
 110 #define S5PC110_DMA_TRANS_CMD_TDC       (0x1 << 18)
 111 #define S5PC110_DMA_TRANS_CMD_TEC       (0x1 << 16)
 112 #define S5PC110_DMA_TRANS_CMD_TR        (0x1 << 0)
 113
 114 #define S5PC110_DMA_TRANS_STATUS_TD     (0x1 << 18)
 115 #define S5PC110_DMA_TRANS_STATUS_TB     (0x1 << 17)
 116 #define S5PC110_DMA_TRANS_STATUS_TE     (0x1 << 16)
 117
 118 #define S5PC110_DMA_DIR_READ            0x0
 119 #define S5PC110_DMA_DIR_WRITE           0x1
 120
 121 struct s3c_onenand {
 122         struct mtd_info *mtd;
 123         struct platform_device  *pdev;
 124         enum soc_type   type;
 125         void __iomem    *base;
 126         struct resource *base_res;
 127         void __iomem    *ahb_addr;
 128         struct resource *ahb_res;
 129         int             bootram_command;
 130         void __iomem    *page_buf;
 131         void __iomem    *oob_buf;
 132         unsigned int    (*mem_addr)(int fba, int fpa, int fsa);
 133         unsigned int    (*cmd_map)(unsigned int type, unsigned int val);
 134         void __iomem    *dma_addr;
 135         struct resource *dma_res;
 136         unsigned long   phys_base;
 137 #ifdef CONFIG_MTD_PARTITIONS
 138         struct mtd_partition *parts;
 139 #endif
 140 };
 141
 142 #define CMD_MAP_00(dev, addr)           (dev->cmd_map(MAP_00, ((addr) << 1)))
 143 #define CMD_MAP_01(dev, mem_addr)       (dev->cmd_map(MAP_01, (mem_addr)))
 144 #define CMD_MAP_10(dev, mem_addr)       (dev->cmd_map(MAP_10, (mem_addr)))
 145 #define CMD_MAP_11(dev, addr)           (dev->cmd_map(MAP_11, ((addr) << 2)))
 146
 147 static struct s3c_onenand *onenand;
 148
 149 #ifdef CONFIG_MTD_PARTITIONS
 150 static const char *part_probes[] = { "cmdlinepart", NULL, };
 151 #endif
 152
 153 static inline int s3c_read_reg(int offset)
 154 {
 155         return readl(onenand->base + offset);
 156 }
 157
 158 static inline void s3c_write_reg(int value, int offset)
 159 {
 160         writel(value, onenand->base + offset);
 161 }
 162
 163 static inline int s3c_read_cmd(unsigned int cmd)
 164 {
 165         return readl(onenand->ahb_addr + cmd);
 166 }
 167
 168 static inline void s3c_write_cmd(int value, unsigned int cmd)
 169 {
 170         writel(value, onenand->ahb_addr + cmd);
 171 }
 172
 173 #ifdef SAMSUNG_DEBUG
 174 static void s3c_dump_reg(void)
 175 {
 176         int i;
 177
 178         for (i = 0; i < 0x400; i += 0x40) {
 179                 printk(KERN_INFO "0x%08X: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 180                         (unsigned int) onenand->base + i,
 181                         s3c_read_reg(i), s3c_read_reg(i + 0x10),
 182                         s3c_read_reg(i + 0x20), s3c_read_reg(i + 0x30));
 183         }
 184 }
 185 #endif
 186
 187 static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val)
 188 {
 189         return (type << S3C64XX_CMD_MAP_SHIFT) | val;
 190 }
 191
 192 static unsigned int s5pc1xx_cmd_map(unsigned type, unsigned val)
 193 {
 194         return (type << S5PC1XX_CMD_MAP_SHIFT) | val;
 195 }
 196
 197 static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa)
 198 {
 199         return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) |
 200                 (fsa << S3C6400_FSA_SHIFT);
 201 }
 202
 203 static unsigned int s3c6410_mem_addr(int fba, int fpa, int fsa)
 204 {
 205         return (fba << S3C6410_FBA_SHIFT) | (fpa << S3C6410_FPA_SHIFT) |
 206                 (fsa << S3C6410_FSA_SHIFT);
 207 }
 208
 209 static unsigned int s5pc100_mem_addr(int fba, int fpa, int fsa)
 210 {
 211         return (fba << S5PC100_FBA_SHIFT) | (fpa << S5PC100_FPA_SHIFT) |
 212                 (fsa << S5PC100_FSA_SHIFT);
 213 }
 214
 215 static void s3c_onenand_reset(void)
 216 {
 217         unsigned long timeout = 0x10000;
 218         int stat;
 219
 220         s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
 221         while (1 && timeout--) {
 222                 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 223                 if (stat & RST_CMP)
 224                         break;
 225         }
 226         stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 227         s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
 228
 229         /* Clear interrupt */
 230         s3c_write_reg(0x0, INT_ERR_ACK_OFFSET);
 231         /* Clear the ECC status */
 232         s3c_write_reg(0x0, ECC_ERR_STAT_OFFSET);
 233 }
 234
 235 static unsigned short s3c_onenand_readw(void __iomem *addr)
 236 {
 237         struct onenand_chip *this = onenand->mtd->priv;
 238         struct device *dev = &onenand->pdev->dev;
 239         int reg = addr - this->base;
 240         int word_addr = reg >> 1;
 241         int value;
 242
 243         /* It's used for probing time */
 244         switch (reg) {
 245         case ONENAND_REG_MANUFACTURER_ID:
 246                 return s3c_read_reg(MANUFACT_ID_OFFSET);
 247         case ONENAND_REG_DEVICE_ID:
 248                 return s3c_read_reg(DEVICE_ID_OFFSET);
 249         case ONENAND_REG_VERSION_ID:
 250                 return s3c_read_reg(FLASH_VER_ID_OFFSET);
 251         case ONENAND_REG_DATA_BUFFER_SIZE:
 252                 return s3c_read_reg(DATA_BUF_SIZE_OFFSET);
 253         case ONENAND_REG_TECHNOLOGY:
 254                 return s3c_read_reg(TECH_OFFSET);
 255         case ONENAND_REG_SYS_CFG1:
 256                 return s3c_read_reg(MEM_CFG_OFFSET);
 257
 258         /* Used at unlock all status */
 259         case ONENAND_REG_CTRL_STATUS:
 260                 return 0;
 261
 262         case ONENAND_REG_WP_STATUS:
 263                 return ONENAND_WP_US;
 264
 265         default:
 266                 break;
 267         }
 268
 269         /* BootRAM access control */
 270         if ((unsigned int) addr < ONENAND_DATARAM && onenand->bootram_command) {
 271                 if (word_addr == 0)
 272                         return s3c_read_reg(MANUFACT_ID_OFFSET);
 273                 if (word_addr == 1)
 274                         return s3c_read_reg(DEVICE_ID_OFFSET);
 275                 if (word_addr == 2)
 276                         return s3c_read_reg(FLASH_VER_ID_OFFSET);
 277         }
 278
 279         value = s3c_read_cmd(CMD_MAP_11(onenand, word_addr)) & 0xffff;
 280         dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__,
 281                  word_addr, value);
 282         return value;
 283 }
 284
 285 static void s3c_onenand_writew(unsigned short value, void __iomem *addr)
 286 {
 287         struct onenand_chip *this = onenand->mtd->priv;
 288         struct device *dev = &onenand->pdev->dev;
 289         unsigned int reg = addr - this->base;
 290         unsigned int word_addr = reg >> 1;
 291
 292         /* It's used for probing time */
 293         switch (reg) {
 294         case ONENAND_REG_SYS_CFG1:
 295                 s3c_write_reg(value, MEM_CFG_OFFSET);
 296                 return;
 297
 298         case ONENAND_REG_START_ADDRESS1:
 299         case ONENAND_REG_START_ADDRESS2:
 300                 return;
 301
 302         /* Lock/lock-tight/unlock/unlock_all */
 303         case ONENAND_REG_START_BLOCK_ADDRESS:
 304                 return;
 305
 306         default:
 307                 break;
 308         }
 309
 310         /* BootRAM access control */
 311         if ((unsigned int)addr < ONENAND_DATARAM) {
 312                 if (value == ONENAND_CMD_READID) {
 313                         onenand->bootram_command = 1;
 314                         return;
 315                 }
 316                 if (value == ONENAND_CMD_RESET) {
 317                         s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
 318                         onenand->bootram_command = 0;
 319                         return;
 320                 }
 321         }
 322
 323         dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__,
 324                  word_addr, value);
 325
 326         s3c_write_cmd(value, CMD_MAP_11(onenand, word_addr));
 327 }
 328
 329 static int s3c_onenand_wait(struct mtd_info *mtd, int state)
 330 {
 331         struct device *dev = &onenand->pdev->dev;
 332         unsigned int flags = INT_ACT;
 333         unsigned int stat, ecc;
 334         unsigned long timeout;
 335
 336         switch (state) {
 337         case FL_READING:
 338                 flags |= BLK_RW_CMP | LOAD_CMP;
 339                 break;
 340         case FL_WRITING:
 341                 flags |= BLK_RW_CMP | PGM_CMP;
 342                 break;
 343         case FL_ERASING:
 344                 flags |= BLK_RW_CMP | ERS_CMP;
 345                 break;
 346         case FL_LOCKING:
 347                 flags |= BLK_RW_CMP;
 348                 break;
 349         default:
 350                 break;
 351         }
 352
 353         /* The 20 msec is enough */
 354         timeout = jiffies + msecs_to_jiffies(20);
 355         while (time_before(jiffies, timeout)) {
 356                 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 357                 if (stat & flags)
 358                         break;
 359
 360                 if (state != FL_READING)
 361                         cond_resched();
 362         }
 363         /* To get correct interrupt status in timeout case */
 364         stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 365         s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
 366
 367         /*
 368          * In the Spec. it checks the controller status first
 369          * However if you get the correct information in case of
 370          * power off recovery (POR) test, it should read ECC status first
 371          */
 372         if (stat & LOAD_CMP) {
 373                 ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET);
 374                 if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
 375                         dev_info(dev, "%s: ECC error = 0x%04x\n", __func__,
 376                                  ecc);
 377                         mtd->ecc_stats.failed++;
 378                         return -EBADMSG;
 379                 }
 380         }
 381
 382         if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) {
 383                 dev_info(dev, "%s: controller error = 0x%04x\n", __func__,
 384                          stat);
 385                 if (stat & LOCKED_BLK)
 386                         dev_info(dev, "%s: it's locked error = 0x%04x\n",
 387                                  __func__, stat);
 388
 389                 return -EIO;
 390         }
 391
 392         return 0;
 393 }
 394
 395 static int s3c_onenand_command(struct mtd_info *mtd, int cmd, loff_t addr,
 396                                size_t len)
 397 {
 398         struct onenand_chip *this = mtd->priv;
 399         unsigned int *m, *s;
 400         int fba, fpa, fsa = 0;
 401         unsigned int mem_addr, cmd_map_01, cmd_map_10;
 402         int i, mcount, scount;
 403         int index;
 404
 405         fba = (int) (addr >> this->erase_shift);
 406         fpa = (int) (addr >> this->page_shift);
 407         fpa &= this->page_mask;
 408
 409         mem_addr = onenand->mem_addr(fba, fpa, fsa);
 410         cmd_map_01 = CMD_MAP_01(onenand, mem_addr);
 411         cmd_map_10 = CMD_MAP_10(onenand, mem_addr);
 412
 413         switch (cmd) {
 414         case ONENAND_CMD_READ:
 415         case ONENAND_CMD_READOOB:
 416         case ONENAND_CMD_BUFFERRAM:
 417                 ONENAND_SET_NEXT_BUFFERRAM(this);
 418         default:
 419                 break;
 420         }
 421
 422         index = ONENAND_CURRENT_BUFFERRAM(this);
 423
 424         /*
 425          * Emulate Two BufferRAMs and access with 4 bytes pointer
 426          */
 427         m = (unsigned int *) onenand->page_buf;
 428         s = (unsigned int *) onenand->oob_buf;
 429
 430         if (index) {
 431                 m += (this->writesize >> 2);
 432                 s += (mtd->oobsize >> 2);
 433         }
 434
 435         mcount = mtd->writesize >> 2;
 436         scount = mtd->oobsize >> 2;
 437
 438         switch (cmd) {
 439         case ONENAND_CMD_READ:
 440                 /* Main */
 441                 for (i = 0; i < mcount; i++)
 442                         *m++ = s3c_read_cmd(cmd_map_01);
 443                 return 0;
 444
 445         case ONENAND_CMD_READOOB:
 446                 s3c_write_reg(TSRF, TRANS_SPARE_OFFSET);
 447                 /* Main */
 448                 for (i = 0; i < mcount; i++)
 449                         *m++ = s3c_read_cmd(cmd_map_01);
 450
 451                 /* Spare */
 452                 for (i = 0; i < scount; i++)
 453                         *s++ = s3c_read_cmd(cmd_map_01);
 454
 455                 s3c_write_reg(0, TRANS_SPARE_OFFSET);
 456                 return 0;
 457
 458         case ONENAND_CMD_PROG:
 459                 /* Main */
 460                 for (i = 0; i < mcount; i++)
 461                         s3c_write_cmd(*m++, cmd_map_01);
 462                 return 0;
 463
 464         case ONENAND_CMD_PROGOOB:
 465                 s3c_write_reg(TSRF, TRANS_SPARE_OFFSET);
 466
 467                 /* Main - dummy write */
 468                 for (i = 0; i < mcount; i++)
 469                         s3c_write_cmd(0xffffffff, cmd_map_01);
 470
 471                 /* Spare */
 472                 for (i = 0; i < scount; i++)
 473                         s3c_write_cmd(*s++, cmd_map_01);
 474
 475                 s3c_write_reg(0, TRANS_SPARE_OFFSET);
 476                 return 0;
 477
 478         case ONENAND_CMD_UNLOCK_ALL:
 479                 s3c_write_cmd(ONENAND_UNLOCK_ALL, cmd_map_10);
 480                 return 0;
 481
 482         case ONENAND_CMD_ERASE:
 483                 s3c_write_cmd(ONENAND_ERASE_START, cmd_map_10);
 484                 return 0;
 485
 486         default:
 487                 break;
 488         }
 489
 490         return 0;
 491 }
 492
 493 static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area)
 494 {
 495         struct onenand_chip *this = mtd->priv;
 496         int index = ONENAND_CURRENT_BUFFERRAM(this);
 497         unsigned char *p;
 498
 499         if (area == ONENAND_DATARAM) {
 500                 p = (unsigned char *) onenand->page_buf;
 501                 if (index == 1)
 502                         p += this->writesize;
 503         } else {
 504                 p = (unsigned char *) onenand->oob_buf;
 505                 if (index == 1)
 506                         p += mtd->oobsize;
 507         }
 508
 509         return p;
 510 }
 511
 512 static int onenand_read_bufferram(struct mtd_info *mtd, int area,
 513                                   unsigned char *buffer, int offset,
 514                                   size_t count)
 515 {
 516         unsigned char *p;
 517
 518         p = s3c_get_bufferram(mtd, area);
 519         memcpy(buffer, p + offset, count);
 520         return 0;
 521 }
 522
 523 static int onenand_write_bufferram(struct mtd_info *mtd, int area,
 524                                    const unsigned char *buffer, int offset,
 525                                    size_t count)
 526 {
 527         unsigned char *p;
 528
 529         p = s3c_get_bufferram(mtd, area);
 530         memcpy(p + offset, buffer, count);
 531         return 0;
 532 }
 533
 534 static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
 535 {
 536         void __iomem *base = onenand->dma_addr;
 537         int status;
 538
 539         writel(src, base + S5PC110_DMA_SRC_ADDR);
 540         writel(dst, base + S5PC110_DMA_DST_ADDR);
 541
 542         if (direction == S5PC110_DMA_DIR_READ) {
 543                 writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
 544                 writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
 545         } else {
 546                 writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
 547                 writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
 548         }
 549
 550         writel(count, base + S5PC110_DMA_TRANS_SIZE);
 551         writel(direction, base + S5PC110_DMA_TRANS_DIR);
 552
 553         writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
 554
 555         do {
 556                 status = readl(base + S5PC110_DMA_TRANS_STATUS);
 557         } while (!(status & S5PC110_DMA_TRANS_STATUS_TD));
 558
 559         if (status & S5PC110_DMA_TRANS_STATUS_TE) {
 560                 writel(S5PC110_DMA_TRANS_CMD_TEC, base + S5PC110_DMA_TRANS_CMD);
 561                 writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
 562                 return -EIO;
 563         }
 564
 565         writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
 566
 567         return 0;
 568 }
 569
 570 static int s5pc110_read_bufferram(struct mtd_info *mtd, int area,
 571                 unsigned char *buffer, int offset, size_t count)
 572 {
 573         struct onenand_chip *this = mtd->priv;
 574         void __iomem *bufferram;
 575         void __iomem *p;
 576         void *buf = (void *) buffer;
 577         dma_addr_t dma_src, dma_dst;
 578         int err;
 579
 580         p = bufferram = this->base + area;
 581         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 582                 if (area == ONENAND_DATARAM)
 583                         p += this->writesize;
 584                 else
 585                         p += mtd->oobsize;
 586         }
 587
 588         if (offset & 3 || (size_t) buf & 3 ||
 589                 !onenand->dma_addr || count != mtd->writesize)
 590                 goto normal;
 591
 592         /* Handle vmalloc address */
 593         if (buf >= high_memory) {
 594                 struct page *page;
 595
 596                 if (((size_t) buf & PAGE_MASK) !=
 597                     ((size_t) (buf + count - 1) & PAGE_MASK))
 598                         goto normal;
 599                 page = vmalloc_to_page(buf);
 600                 if (!page)
 601                         goto normal;
 602                 buf = page_address(page) + ((size_t) buf & ~PAGE_MASK);
 603         }
 604
 605         /* DMA routine */
 606         dma_src = onenand->phys_base + (p - this->base);
 607         dma_dst = dma_map_single(&onenand->pdev->dev,
 608                         buf, count, DMA_FROM_DEVICE);
 609         if (dma_mapping_error(&onenand->pdev->dev, dma_dst)) {
 610                 dev_err(&onenand->pdev->dev,
 611                         "Couldn't map a %d byte buffer for DMA\n", count);
 612                 goto normal;
 613         }
 614         err = s5pc110_dma_ops((void *) dma_dst, (void *) dma_src,
 615                         count, S5PC110_DMA_DIR_READ);
 616         dma_unmap_single(&onenand->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 617
 618         if (!err)
 619                 return 0;
 620
 621 normal:
 622         if (count != mtd->writesize) {
 623                 /* Copy the bufferram to memory to prevent unaligned access */
 624                 memcpy(this->page_buf, bufferram, mtd->writesize);
 625                 p = this->page_buf + offset;
 626         }
 627
 628         memcpy(buffer, p, count);
 629
 630         return 0;
 631 }
 632
 633 static int s5pc110_chip_probe(struct mtd_info *mtd)
 634 {
 635         /* Now just return 0 */
 636         return 0;
 637 }
 638
 639 static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state)
 640 {
 641         unsigned int flags = INT_ACT | LOAD_CMP;
 642         unsigned int stat;
 643         unsigned long timeout;
 644
 645         /* The 20 msec is enough */
 646         timeout = jiffies + msecs_to_jiffies(20);
 647         while (time_before(jiffies, timeout)) {
 648                 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 649                 if (stat & flags)
 650                         break;
 651         }
 652         /* To get correct interrupt status in timeout case */
 653         stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 654         s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
 655
 656         if (stat & LD_FAIL_ECC_ERR) {
 657                 s3c_onenand_reset();
 658                 return ONENAND_BBT_READ_ERROR;
 659         }
 660
 661         if (stat & LOAD_CMP) {
 662                 int ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET);
 663                 if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
 664                         s3c_onenand_reset();
 665                         return ONENAND_BBT_READ_ERROR;
 666                 }
 667         }
 668
 669         return 0;
 670 }
 671
 672 static void s3c_onenand_check_lock_status(struct mtd_info *mtd)
 673 {
 674         struct onenand_chip *this = mtd->priv;
 675         struct device *dev = &onenand->pdev->dev;
 676         unsigned int block, end;
 677         int tmp;
 678
 679         end = this->chipsize >> this->erase_shift;
 680
 681         for (block = 0; block < end; block++) {
 682                 unsigned int mem_addr = onenand->mem_addr(block, 0, 0);
 683                 tmp = s3c_read_cmd(CMD_MAP_01(onenand, mem_addr));
 684
 685                 if (s3c_read_reg(INT_ERR_STAT_OFFSET) & LOCKED_BLK) {
 686                         dev_err(dev, "block %d is write-protected!\n", block);
 687                         s3c_write_reg(LOCKED_BLK, INT_ERR_ACK_OFFSET);
 688                 }
 689         }
 690 }
 691
 692 static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs,
 693                                     size_t len, int cmd)
 694 {
 695         struct onenand_chip *this = mtd->priv;
 696         int start, end, start_mem_addr, end_mem_addr;
 697
 698         start = ofs >> this->erase_shift;
 699         start_mem_addr = onenand->mem_addr(start, 0, 0);
 700         end = start + (len >> this->erase_shift) - 1;
 701         end_mem_addr = onenand->mem_addr(end, 0, 0);
 702
 703         if (cmd == ONENAND_CMD_LOCK) {
 704                 s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(onenand,
 705                                                              start_mem_addr));
 706                 s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(onenand,
 707                                                            end_mem_addr));
 708         } else {
 709                 s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(onenand,
 710                                                                start_mem_addr));
 711                 s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(onenand,
 712                                                              end_mem_addr));
 713         }
 714
 715         this->wait(mtd, FL_LOCKING);
 716 }
 717
 718 static void s3c_unlock_all(struct mtd_info *mtd)
 719 {
 720         struct onenand_chip *this = mtd->priv;
 721         loff_t ofs = 0;
 722         size_t len = this->chipsize;
 723
 724         if (this->options & ONENAND_HAS_UNLOCK_ALL) {
 725                 /* Write unlock command */
 726                 this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
 727
 728                 /* No need to check return value */
 729                 this->wait(mtd, FL_LOCKING);
 730
 731                 /* Workaround for all block unlock in DDP */
 732                 if (!ONENAND_IS_DDP(this)) {
 733                         s3c_onenand_check_lock_status(mtd);
 734                         return;
 735                 }
 736
 737                 /* All blocks on another chip */
 738                 ofs = this->chipsize >> 1;
 739                 len = this->chipsize >> 1;
 740         }
 741
 742         s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
 743
 744         s3c_onenand_check_lock_status(mtd);
 745 }
 746
 747 static void s3c_onenand_setup(struct mtd_info *mtd)
 748 {
 749         struct onenand_chip *this = mtd->priv;
 750
 751         onenand->mtd = mtd;
 752
 753         if (onenand->type == TYPE_S3C6400) {
 754                 onenand->mem_addr = s3c6400_mem_addr;
 755                 onenand->cmd_map = s3c64xx_cmd_map;
 756         } else if (onenand->type == TYPE_S3C6410) {
 757                 onenand->mem_addr = s3c6410_mem_addr;
 758                 onenand->cmd_map = s3c64xx_cmd_map;
 759         } else if (onenand->type == TYPE_S5PC100) {
 760                 onenand->mem_addr = s5pc100_mem_addr;
 761                 onenand->cmd_map = s5pc1xx_cmd_map;
 762         } else if (onenand->type == TYPE_S5PC110) {
 763                 /* Use generic onenand functions */
 764                 onenand->cmd_map = s5pc1xx_cmd_map;
 765                 this->read_bufferram = s5pc110_read_bufferram;
 766                 this->chip_probe = s5pc110_chip_probe;
 767                 return;
 768         } else {
 769                 BUG();
 770         }
 771
 772         this->read_word = s3c_onenand_readw;
 773         this->write_word = s3c_onenand_writew;
 774
 775         this->wait = s3c_onenand_wait;
 776         this->bbt_wait = s3c_onenand_bbt_wait;
 777         this->unlock_all = s3c_unlock_all;
 778         this->command = s3c_onenand_command;
 779
 780         this->read_bufferram = onenand_read_bufferram;
 781         this->write_bufferram = onenand_write_bufferram;
 782 }
 783
 784 static int s3c_onenand_probe(struct platform_device *pdev)
 785 {
 786         struct onenand_platform_data *pdata;
 787         struct onenand_chip *this;
 788         struct mtd_info *mtd;
 789         struct resource *r;
 790         int size, err;
 791
 792         pdata = pdev->dev.platform_data;
 793         /* No need to check pdata. the platform data is optional */
 794
 795         size = sizeof(struct mtd_info) + sizeof(struct onenand_chip);
 796         mtd = kzalloc(size, GFP_KERNEL);
 797         if (!mtd) {
 798                 dev_err(&pdev->dev, "failed to allocate memory\n");
 799                 return -ENOMEM;
 800         }
 801
 802         onenand = kzalloc(sizeof(struct s3c_onenand), GFP_KERNEL);
 803         if (!onenand) {
 804                 err = -ENOMEM;
 805                 goto onenand_fail;
 806         }
 807
 808         this = (struct onenand_chip *) &mtd[1];
 809         mtd->priv = this;
 810         mtd->dev.parent = &pdev->dev;
 811         mtd->owner = THIS_MODULE;
 812         onenand->pdev = pdev;
 813         onenand->type = platform_get_device_id(pdev)->driver_data;
 814
 815         s3c_onenand_setup(mtd);
 816
 817         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 818         if (!r) {
 819                 dev_err(&pdev->dev, "no memory resource defined\n");
 820                 return -ENOENT;
 821                 goto ahb_resource_failed;
 822         }
 823
 824         onenand->base_res = request_mem_region(r->start, resource_size(r),
 825                                                pdev->name);
 826         if (!onenand->base_res) {
 827                 dev_err(&pdev->dev, "failed to request memory resource\n");
 828                 err = -EBUSY;
 829                 goto resource_failed;
 830         }
 831
 832         onenand->base = ioremap(r->start, resource_size(r));
 833         if (!onenand->base) {
 834                 dev_err(&pdev->dev, "failed to map memory resource\n");
 835                 err = -EFAULT;
 836                 goto ioremap_failed;
 837         }
 838         /* Set onenand_chip also */
 839         this->base = onenand->base;
 840
 841         /* Use runtime badblock check */
 842         this->options |= ONENAND_SKIP_UNLOCK_CHECK;
 843
 844         if (onenand->type != TYPE_S5PC110) {
 845                 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 846                 if (!r) {
 847                         dev_err(&pdev->dev, "no buffer memory resource defined\n");
 848                         return -ENOENT;
 849                         goto ahb_resource_failed;
 850                 }
 851
 852                 onenand->ahb_res = request_mem_region(r->start, resource_size(r),
 853                                                       pdev->name);
 854                 if (!onenand->ahb_res) {
 855                         dev_err(&pdev->dev, "failed to request buffer memory resource\n");
 856                         err = -EBUSY;
 857                         goto ahb_resource_failed;
 858                 }
 859
 860                 onenand->ahb_addr = ioremap(r->start, resource_size(r));
 861                 if (!onenand->ahb_addr) {
 862                         dev_err(&pdev->dev, "failed to map buffer memory resource\n");
 863                         err = -EINVAL;
 864                         goto ahb_ioremap_failed;
 865                 }
 866
 867                 /* Allocate 4KiB BufferRAM */
 868                 onenand->page_buf = kzalloc(SZ_4K, GFP_KERNEL);
 869                 if (!onenand->page_buf) {
 870                         err = -ENOMEM;
 871                         goto page_buf_fail;
 872                 }
 873
 874                 /* Allocate 128 SpareRAM */
 875                 onenand->oob_buf = kzalloc(128, GFP_KERNEL);
 876                 if (!onenand->oob_buf) {
 877                         err = -ENOMEM;
 878                         goto oob_buf_fail;
 879                 }
 880
 881                 /* S3C doesn't handle subpage write */
 882                 mtd->subpage_sft = 0;
 883                 this->subpagesize = mtd->writesize;
 884
 885         } else { /* S5PC110 */
 886                 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 887                 if (!r) {
 888                         dev_err(&pdev->dev, "no dma memory resource defined\n");
 889                         return -ENOENT;
 890                         goto dma_resource_failed;
 891                 }
 892
 893                 onenand->dma_res = request_mem_region(r->start, resource_size(r),
 894                                                       pdev->name);
 895                 if (!onenand->dma_res) {
 896                         dev_err(&pdev->dev, "failed to request dma memory resource\n");
 897                         err = -EBUSY;
 898                         goto dma_resource_failed;
 899                 }
 900
 901                 onenand->dma_addr = ioremap(r->start, resource_size(r));
 902                 if (!onenand->dma_addr) {
 903                         dev_err(&pdev->dev, "failed to map dma memory resource\n");
 904                         err = -EINVAL;
 905                         goto dma_ioremap_failed;
 906                 }
 907
 908                 onenand->phys_base = onenand->base_res->start;
 909         }
 910
 911         if (onenand_scan(mtd, 1)) {
 912                 err = -EFAULT;
 913                 goto scan_failed;
 914         }
 915
 916         if (onenand->type != TYPE_S5PC110) {
 917                 /* S3C doesn't handle subpage write */
 918                 mtd->subpage_sft = 0;
 919                 this->subpagesize = mtd->writesize;
 920         }
 921
 922         if (s3c_read_reg(MEM_CFG_OFFSET) & ONENAND_SYS_CFG1_SYNC_READ)
 923                 dev_info(&onenand->pdev->dev, "OneNAND Sync. Burst Read enabled\n");
 924
 925 #ifdef CONFIG_MTD_PARTITIONS
 926         err = parse_mtd_partitions(mtd, part_probes, &onenand->parts, 0);
 927         if (err > 0)
 928                 add_mtd_partitions(mtd, onenand->parts, err);
 929         else if (err <= 0 && pdata && pdata->parts)
 930                 add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
 931         else
 932 #endif
 933                 err = add_mtd_device(mtd);
 934
 935         platform_set_drvdata(pdev, mtd);
 936
 937         return 0;
 938
 939 scan_failed:
 940         if (onenand->dma_addr)
 941                 iounmap(onenand->dma_addr);
 942 dma_ioremap_failed:
 943         if (onenand->dma_res)
 944                 release_mem_region(onenand->dma_res->start,
 945                                    resource_size(onenand->dma_res));
 946         kfree(onenand->oob_buf);
 947 oob_buf_fail:
 948         kfree(onenand->page_buf);
 949 page_buf_fail:
 950         if (onenand->ahb_addr)
 951                 iounmap(onenand->ahb_addr);
 952 ahb_ioremap_failed:
 953         if (onenand->ahb_res)
 954                 release_mem_region(onenand->ahb_res->start,
 955                                    resource_size(onenand->ahb_res));
 956 dma_resource_failed:
 957 ahb_resource_failed:
 958         iounmap(onenand->base);
 959 ioremap_failed:
 960         if (onenand->base_res)
 961                 release_mem_region(onenand->base_res->start,
 962                                    resource_size(onenand->base_res));
 963 resource_failed:
 964         kfree(onenand);
 965 onenand_fail:
 966         kfree(mtd);
 967         return err;
 968 }
 969
 970 static int __devexit s3c_onenand_remove(struct platform_device *pdev)
 971 {
 972         struct mtd_info *mtd = platform_get_drvdata(pdev);
 973
 974         onenand_release(mtd);
 975         if (onenand->ahb_addr)
 976                 iounmap(onenand->ahb_addr);
 977         if (onenand->ahb_res)
 978                 release_mem_region(onenand->ahb_res->start,
 979                                    resource_size(onenand->ahb_res));
 980         if (onenand->dma_addr)
 981                 iounmap(onenand->dma_addr);
 982         if (onenand->dma_res)
 983                 release_mem_region(onenand->dma_res->start,
 984                                    resource_size(onenand->dma_res));
 985
 986         iounmap(onenand->base);
 987         release_mem_region(onenand->base_res->start,
 988                            resource_size(onenand->base_res));
 989
 990         platform_set_drvdata(pdev, NULL);
 991         kfree(onenand->oob_buf);
 992         kfree(onenand->page_buf);
 993         kfree(onenand);
 994         kfree(mtd);
 995         return 0;
 996 }
 997
 998 static int s3c_pm_ops_suspend(struct device *dev)
 999 {
1000         struct platform_device *pdev = to_platform_device(dev);
1001         struct mtd_info *mtd = platform_get_drvdata(pdev);
1002         struct onenand_chip *this = mtd->priv;
1003
1004         this->wait(mtd, FL_PM_SUSPENDED);
1005         return mtd->suspend(mtd);
1006 }
1007
1008 static  int s3c_pm_ops_resume(struct device *dev)
1009 {
1010         struct platform_device *pdev = to_platform_device(dev);
1011         struct mtd_info *mtd = platform_get_drvdata(pdev);
1012         struct onenand_chip *this = mtd->priv;
1013
1014         mtd->resume(mtd);
1015         this->unlock_all(mtd);
1016         return 0;
1017 }
1018
1019 static const struct dev_pm_ops s3c_pm_ops = {
1020         .suspend        = s3c_pm_ops_suspend,
1021         .resume         = s3c_pm_ops_resume,
1022 };
1023
1024 static struct platform_device_id s3c_onenand_driver_ids[] = {
1025         {
1026                 .name           = "s3c6400-onenand",
1027                 .driver_data    = TYPE_S3C6400,
1028         }, {
1029                 .name           = "s3c6410-onenand",
1030                 .driver_data    = TYPE_S3C6410,
1031         }, {
1032                 .name           = "s5pc100-onenand",
1033                 .driver_data    = TYPE_S5PC100,
1034         }, {
1035                 .name           = "s5pc110-onenand",
1036                 .driver_data    = TYPE_S5PC110,
1037         }, { },
1038 };
1039 MODULE_DEVICE_TABLE(platform, s3c_onenand_driver_ids);
1040
1041 static struct platform_driver s3c_onenand_driver = {
1042         .driver         = {
1043                 .name   = "samsung-onenand",
1044                 .pm     = &s3c_pm_ops,
1045         },
1046         .id_table       = s3c_onenand_driver_ids,
1047         .probe          = s3c_onenand_probe,
1048         .remove         = __devexit_p(s3c_onenand_remove),
1049 };
1050
1051 static int __init s3c_onenand_init(void)
1052 {
1053         return platform_driver_register(&s3c_onenand_driver);
1054 }
1055
1056 static void __exit s3c_onenand_exit(void)
1057 {
1058         platform_driver_unregister(&s3c_onenand_driver);
1059 }
1060
1061 module_init(s3c_onenand_init);
1062 module_exit(s3c_onenand_exit);
1063
1064 MODULE_LICENSE("GPL");
1065 MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
1066 MODULE_DESCRIPTION("Samsung OneNAND controller support");