drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/compatmac.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <asm/io.h>
  50
  51 #ifdef CONFIG_MTD_PARTITIONS
  52 #include <linux/mtd/partitions.h>
  53 #endif
  54
  55 /* Define default oob placement schemes for large and small page devices */
  56 static struct nand_ecclayout nand_oob_8 = {
  57         .eccbytes = 3,
  58         .eccpos = {0, 1, 2},
  59         .oobfree = {
  60                 {.offset = 3,
  61                  .length = 2},
  62                 {.offset = 6,
  63                  .length = 2}}
  64 };
  65
  66 static struct nand_ecclayout nand_oob_16 = {
  67         .eccbytes = 6,
  68         .eccpos = {0, 1, 2, 3, 6, 7},
  69         .oobfree = {
  70                 {.offset = 8,
  71                  . length = 8}}
  72 };
  73
  74 static struct nand_ecclayout nand_oob_64 = {
  75         .eccbytes = 24,
  76         .eccpos = {
  77                    40, 41, 42, 43, 44, 45, 46, 47,
  78                    48, 49, 50, 51, 52, 53, 54, 55,
  79                    56, 57, 58, 59, 60, 61, 62, 63},
  80         .oobfree = {
  81                 {.offset = 2,
  82                  .length = 38}}
  83 };
  84
  85 static struct nand_ecclayout nand_oob_128 = {
  86         .eccbytes = 48,
  87         .eccpos = {
  88                    80, 81, 82, 83, 84, 85, 86, 87,
  89                    88, 89, 90, 91, 92, 93, 94, 95,
  90                    96, 97, 98, 99, 100, 101, 102, 103,
  91                    104, 105, 106, 107, 108, 109, 110, 111,
  92                    112, 113, 114, 115, 116, 117, 118, 119,
  93                    120, 121, 122, 123, 124, 125, 126, 127},
  94         .oobfree = {
  95                 {.offset = 2,
  96                  .length = 78}}
  97 };
  98
  99 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 100                            int new_state);
 101
 102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 103                              struct mtd_oob_ops *ops);
 104
 105 /*
 106  * For devices which display every fart in the system on a separate LED. Is
 107  * compiled away when LED support is disabled.
 108  */
 109 DEFINE_LED_TRIGGER(nand_led_trigger);
 110
 111 static int check_offs_len(struct mtd_info *mtd,
 112                                         loff_t ofs, uint64_t len)
 113 {
 114         struct nand_chip *chip = mtd->priv;
 115         int ret = 0;
 116
 117         /* Start address must align on block boundary */
 118         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 119                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 120                 ret = -EINVAL;
 121         }
 122
 123         /* Length must align on block boundary */
 124         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 125                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 126                                         __func__);
 127                 ret = -EINVAL;
 128         }
 129
 130         /* Do not allow past end of device */
 131         if (ofs + len > mtd->size) {
 132                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
 133                                         __func__);
 134                 ret = -EINVAL;
 135         }
 136
 137         return ret;
 138 }
 139
 140 /**
 141  * nand_release_device - [GENERIC] release chip
 142  * @mtd:        MTD device structure
 143  *
 144  * Deselect, release chip lock and wake up anyone waiting on the device
 145  */
 146 static void nand_release_device(struct mtd_info *mtd)
 147 {
 148         struct nand_chip *chip = mtd->priv;
 149
 150         /* De-select the NAND device */
 151         chip->select_chip(mtd, -1);
 152
 153         /* Release the controller and the chip */
 154         spin_lock(&chip->controller->lock);
 155         chip->controller->active = NULL;
 156         chip->state = FL_READY;
 157         wake_up(&chip->controller->wq);
 158         spin_unlock(&chip->controller->lock);
 159 }
 160
 161 /**
 162  * nand_read_byte - [DEFAULT] read one byte from the chip
 163  * @mtd:        MTD device structure
 164  *
 165  * Default read function for 8bit buswith
 166  */
 167 static uint8_t nand_read_byte(struct mtd_info *mtd)
 168 {
 169         struct nand_chip *chip = mtd->priv;
 170         return readb(chip->IO_ADDR_R);
 171 }
 172
 173 /**
 174  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 175  * @mtd:        MTD device structure
 176  *
 177  * Default read function for 16bit buswith with
 178  * endianess conversion
 179  */
 180 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 181 {
 182         struct nand_chip *chip = mtd->priv;
 183         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 184 }
 185
 186 /**
 187  * nand_read_word - [DEFAULT] read one word from the chip
 188  * @mtd:        MTD device structure
 189  *
 190  * Default read function for 16bit buswith without
 191  * endianess conversion
 192  */
 193 static u16 nand_read_word(struct mtd_info *mtd)
 194 {
 195         struct nand_chip *chip = mtd->priv;
 196         return readw(chip->IO_ADDR_R);
 197 }
 198
 199 /**
 200  * nand_select_chip - [DEFAULT] control CE line
 201  * @mtd:        MTD device structure
 202  * @chipnr:     chipnumber to select, -1 for deselect
 203  *
 204  * Default select function for 1 chip devices.
 205  */
 206 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 207 {
 208         struct nand_chip *chip = mtd->priv;
 209
 210         switch (chipnr) {
 211         case -1:
 212                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 213                 break;
 214         case 0:
 215                 break;
 216
 217         default:
 218                 BUG();
 219         }
 220 }
 221
 222 /**
 223  * nand_write_buf - [DEFAULT] write buffer to chip
 224  * @mtd:        MTD device structure
 225  * @buf:        data buffer
 226  * @len:        number of bytes to write
 227  *
 228  * Default write function for 8bit buswith
 229  */
 230 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 231 {
 232         int i;
 233         struct nand_chip *chip = mtd->priv;
 234
 235         for (i = 0; i < len; i++)
 236                 writeb(buf[i], chip->IO_ADDR_W);
 237 }
 238
 239 /**
 240  * nand_read_buf - [DEFAULT] read chip data into buffer
 241  * @mtd:        MTD device structure
 242  * @buf:        buffer to store date
 243  * @len:        number of bytes to read
 244  *
 245  * Default read function for 8bit buswith
 246  */
 247 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 248 {
 249         int i;
 250         struct nand_chip *chip = mtd->priv;
 251
 252         for (i = 0; i < len; i++)
 253                 buf[i] = readb(chip->IO_ADDR_R);
 254 }
 255
 256 /**
 257  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 258  * @mtd:        MTD device structure
 259  * @buf:        buffer containing the data to compare
 260  * @len:        number of bytes to compare
 261  *
 262  * Default verify function for 8bit buswith
 263  */
 264 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 265 {
 266         int i;
 267         struct nand_chip *chip = mtd->priv;
 268
 269         for (i = 0; i < len; i++)
 270                 if (buf[i] != readb(chip->IO_ADDR_R))
 271                         return -EFAULT;
 272         return 0;
 273 }
 274
 275 /**
 276  * nand_write_buf16 - [DEFAULT] write buffer to chip
 277  * @mtd:        MTD device structure
 278  * @buf:        data buffer
 279  * @len:        number of bytes to write
 280  *
 281  * Default write function for 16bit buswith
 282  */
 283 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 284 {
 285         int i;
 286         struct nand_chip *chip = mtd->priv;
 287         u16 *p = (u16 *) buf;
 288         len >>= 1;
 289
 290         for (i = 0; i < len; i++)
 291                 writew(p[i], chip->IO_ADDR_W);
 292
 293 }
 294
 295 /**
 296  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 297  * @mtd:        MTD device structure
 298  * @buf:        buffer to store date
 299  * @len:        number of bytes to read
 300  *
 301  * Default read function for 16bit buswith
 302  */
 303 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 304 {
 305         int i;
 306         struct nand_chip *chip = mtd->priv;
 307         u16 *p = (u16 *) buf;
 308         len >>= 1;
 309
 310         for (i = 0; i < len; i++)
 311                 p[i] = readw(chip->IO_ADDR_R);
 312 }
 313
 314 /**
 315  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 316  * @mtd:        MTD device structure
 317  * @buf:        buffer containing the data to compare
 318  * @len:        number of bytes to compare
 319  *
 320  * Default verify function for 16bit buswith
 321  */
 322 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 323 {
 324         int i;
 325         struct nand_chip *chip = mtd->priv;
 326         u16 *p = (u16 *) buf;
 327         len >>= 1;
 328
 329         for (i = 0; i < len; i++)
 330                 if (p[i] != readw(chip->IO_ADDR_R))
 331                         return -EFAULT;
 332
 333         return 0;
 334 }
 335
 336 /**
 337  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 338  * @mtd:        MTD device structure
 339  * @ofs:        offset from device start
 340  * @getchip:    0, if the chip is already selected
 341  *
 342  * Check, if the block is bad.
 343  */
 344 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 345 {
 346         int page, chipnr, res = 0;
 347         struct nand_chip *chip = mtd->priv;
 348         u16 bad;
 349
 350         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 351
 352         if (getchip) {
 353                 chipnr = (int)(ofs >> chip->chip_shift);
 354
 355                 nand_get_device(chip, mtd, FL_READING);
 356
 357                 /* Select the NAND device */
 358                 chip->select_chip(mtd, chipnr);
 359         }
 360
 361         if (chip->options & NAND_BUSWIDTH_16) {
 362                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 363                               page);
 364                 bad = cpu_to_le16(chip->read_word(mtd));
 365                 if (chip->badblockpos & 0x1)
 366                         bad >>= 8;
 367                 if ((bad & 0xFF) != 0xff)
 368                         res = 1;
 369         } else {
 370                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 371                 if (chip->read_byte(mtd) != 0xff)
 372                         res = 1;
 373         }
 374
 375         if (getchip)
 376                 nand_release_device(mtd);
 377
 378         return res;
 379 }
 380
 381 /**
 382  * nand_default_block_markbad - [DEFAULT] mark a block bad
 383  * @mtd:        MTD device structure
 384  * @ofs:        offset from device start
 385  *
 386  * This is the default implementation, which can be overridden by
 387  * a hardware specific driver.
 388 */
 389 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 390 {
 391         struct nand_chip *chip = mtd->priv;
 392         uint8_t buf[2] = { 0, 0 };
 393         int block, ret;
 394
 395         /* Get block number */
 396         block = (int)(ofs >> chip->bbt_erase_shift);
 397         if (chip->bbt)
 398                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 399
 400         /* Do we have a flash based bad block table ? */
 401         if (chip->options & NAND_USE_FLASH_BBT)
 402                 ret = nand_update_bbt(mtd, ofs);
 403         else {
 404                 /* We write two bytes, so we dont have to mess with 16 bit
 405                  * access
 406                  */
 407                 nand_get_device(chip, mtd, FL_WRITING);
 408                 ofs += mtd->oobsize;
 409                 chip->ops.len = chip->ops.ooblen = 2;
 410                 chip->ops.datbuf = NULL;
 411                 chip->ops.oobbuf = buf;
 412                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 413
 414                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 415                 nand_release_device(mtd);
 416         }
 417         if (!ret)
 418                 mtd->ecc_stats.badblocks++;
 419
 420         return ret;
 421 }
 422
 423 /**
 424  * nand_check_wp - [GENERIC] check if the chip is write protected
 425  * @mtd:        MTD device structure
 426  * Check, if the device is write protected
 427  *
 428  * The function expects, that the device is already selected
 429  */
 430 static int nand_check_wp(struct mtd_info *mtd)
 431 {
 432         struct nand_chip *chip = mtd->priv;
 433         /* Check the WP bit */
 434         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 435         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 436 }
 437
 438 /**
 439  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 440  * @mtd:        MTD device structure
 441  * @ofs:        offset from device start
 442  * @getchip:    0, if the chip is already selected
 443  * @allowbbt:   1, if its allowed to access the bbt area
 444  *
 445  * Check, if the block is bad. Either by reading the bad block table or
 446  * calling of the scan function.
 447  */
 448 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 449                                int allowbbt)
 450 {
 451         struct nand_chip *chip = mtd->priv;
 452
 453         if (!chip->bbt)
 454                 return chip->block_bad(mtd, ofs, getchip);
 455
 456         /* Return info from the table */
 457         return nand_isbad_bbt(mtd, ofs, allowbbt);
 458 }
 459
 460 /**
 461  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 462  * @mtd:        MTD device structure
 463  * @timeo:      Timeout
 464  *
 465  * Helper function for nand_wait_ready used when needing to wait in interrupt
 466  * context.
 467  */
 468 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 469 {
 470         struct nand_chip *chip = mtd->priv;
 471         int i;
 472
 473         /* Wait for the device to get ready */
 474         for (i = 0; i < timeo; i++) {
 475                 if (chip->dev_ready(mtd))
 476                         break;
 477                 touch_softlockup_watchdog();
 478                 mdelay(1);
 479         }
 480 }
 481
 482 /*
 483  * Wait for the ready pin, after a command
 484  * The timeout is catched later.
 485  */
 486 void nand_wait_ready(struct mtd_info *mtd)
 487 {
 488         struct nand_chip *chip = mtd->priv;
 489         unsigned long timeo = jiffies + 2;
 490
 491         /* 400ms timeout */
 492         if (in_interrupt() || oops_in_progress)
 493                 return panic_nand_wait_ready(mtd, 400);
 494
 495         led_trigger_event(nand_led_trigger, LED_FULL);
 496         /* wait until command is processed or timeout occures */
 497         do {
 498                 if (chip->dev_ready(mtd))
 499                         break;
 500                 touch_softlockup_watchdog();
 501         } while (time_before(jiffies, timeo));
 502         led_trigger_event(nand_led_trigger, LED_OFF);
 503 }
 504 EXPORT_SYMBOL_GPL(nand_wait_ready);
 505
 506 /**
 507  * nand_command - [DEFAULT] Send command to NAND device
 508  * @mtd:        MTD device structure
 509  * @command:    the command to be sent
 510  * @column:     the column address for this command, -1 if none
 511  * @page_addr:  the page address for this command, -1 if none
 512  *
 513  * Send command to NAND device. This function is used for small page
 514  * devices (256/512 Bytes per page)
 515  */
 516 static void nand_command(struct mtd_info *mtd, unsigned int command,
 517                          int column, int page_addr)
 518 {
 519         register struct nand_chip *chip = mtd->priv;
 520         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 521
 522         /*
 523          * Write out the command to the device.
 524          */
 525         if (command == NAND_CMD_SEQIN) {
 526                 int readcmd;
 527
 528                 if (column >= mtd->writesize) {
 529                         /* OOB area */
 530                         column -= mtd->writesize;
 531                         readcmd = NAND_CMD_READOOB;
 532                 } else if (column < 256) {
 533                         /* First 256 bytes --> READ0 */
 534                         readcmd = NAND_CMD_READ0;
 535                 } else {
 536                         column -= 256;
 537                         readcmd = NAND_CMD_READ1;
 538                 }
 539                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 540                 ctrl &= ~NAND_CTRL_CHANGE;
 541         }
 542         chip->cmd_ctrl(mtd, command, ctrl);
 543
 544         /*
 545          * Address cycle, when necessary
 546          */
 547         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 548         /* Serially input address */
 549         if (column != -1) {
 550                 /* Adjust columns for 16 bit buswidth */
 551                 if (chip->options & NAND_BUSWIDTH_16)
 552                         column >>= 1;
 553                 chip->cmd_ctrl(mtd, column, ctrl);
 554                 ctrl &= ~NAND_CTRL_CHANGE;
 555         }
 556         if (page_addr != -1) {
 557                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 558                 ctrl &= ~NAND_CTRL_CHANGE;
 559                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 560                 /* One more address cycle for devices > 32MiB */
 561                 if (chip->chipsize > (32 << 20))
 562                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 563         }
 564         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 565
 566         /*
 567          * program and erase have their own busy handlers
 568          * status and sequential in needs no delay
 569          */
 570         switch (command) {
 571
 572         case NAND_CMD_PAGEPROG:
 573         case NAND_CMD_ERASE1:
 574         case NAND_CMD_ERASE2:
 575         case NAND_CMD_SEQIN:
 576         case NAND_CMD_STATUS:
 577                 return;
 578
 579         case NAND_CMD_RESET:
 580                 if (chip->dev_ready)
 581                         break;
 582                 udelay(chip->chip_delay);
 583                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 584                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 585                 chip->cmd_ctrl(mtd,
 586                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 587                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 588                 return;
 589
 590                 /* This applies to read commands */
 591         default:
 592                 /*
 593                  * If we don't have access to the busy pin, we apply the given
 594                  * command delay
 595                  */
 596                 if (!chip->dev_ready) {
 597                         udelay(chip->chip_delay);
 598                         return;
 599                 }
 600         }
 601         /* Apply this short delay always to ensure that we do wait tWB in
 602          * any case on any machine. */
 603         ndelay(100);
 604
 605         nand_wait_ready(mtd);
 606 }
 607
 608 /**
 609  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 610  * @mtd:        MTD device structure
 611  * @command:    the command to be sent
 612  * @column:     the column address for this command, -1 if none
 613  * @page_addr:  the page address for this command, -1 if none
 614  *
 615  * Send command to NAND device. This is the version for the new large page
 616  * devices We dont have the separate regions as we have in the small page
 617  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 618  */
 619 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 620                             int column, int page_addr)
 621 {
 622         register struct nand_chip *chip = mtd->priv;
 623
 624         /* Emulate NAND_CMD_READOOB */
 625         if (command == NAND_CMD_READOOB) {
 626                 column += mtd->writesize;
 627                 command = NAND_CMD_READ0;
 628         }
 629
 630         /* Command latch cycle */
 631         chip->cmd_ctrl(mtd, command & 0xff,
 632                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 633
 634         if (column != -1 || page_addr != -1) {
 635                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 636
 637                 /* Serially input address */
 638                 if (column != -1) {
 639                         /* Adjust columns for 16 bit buswidth */
 640                         if (chip->options & NAND_BUSWIDTH_16)
 641                                 column >>= 1;
 642                         chip->cmd_ctrl(mtd, column, ctrl);
 643                         ctrl &= ~NAND_CTRL_CHANGE;
 644                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 645                 }
 646                 if (page_addr != -1) {
 647                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 648                         chip->cmd_ctrl(mtd, page_addr >> 8,
 649                                        NAND_NCE | NAND_ALE);
 650                         /* One more address cycle for devices > 128MiB */
 651                         if (chip->chipsize > (128 << 20))
 652                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 653                                                NAND_NCE | NAND_ALE);
 654                 }
 655         }
 656         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 657
 658         /*
 659          * program and erase have their own busy handlers
 660          * status, sequential in, and deplete1 need no delay
 661          */
 662         switch (command) {
 663
 664         case NAND_CMD_CACHEDPROG:
 665         case NAND_CMD_PAGEPROG:
 666         case NAND_CMD_ERASE1:
 667         case NAND_CMD_ERASE2:
 668         case NAND_CMD_SEQIN:
 669         case NAND_CMD_RNDIN:
 670         case NAND_CMD_STATUS:
 671         case NAND_CMD_DEPLETE1:
 672                 return;
 673
 674                 /*
 675                  * read error status commands require only a short delay
 676                  */
 677         case NAND_CMD_STATUS_ERROR:
 678         case NAND_CMD_STATUS_ERROR0:
 679         case NAND_CMD_STATUS_ERROR1:
 680         case NAND_CMD_STATUS_ERROR2:
 681         case NAND_CMD_STATUS_ERROR3:
 682                 udelay(chip->chip_delay);
 683                 return;
 684
 685         case NAND_CMD_RESET:
 686                 if (chip->dev_ready)
 687                         break;
 688                 udelay(chip->chip_delay);
 689                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 690                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 691                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 692                                NAND_NCE | NAND_CTRL_CHANGE);
 693                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 694                 return;
 695
 696         case NAND_CMD_RNDOUT:
 697                 /* No ready / busy check necessary */
 698                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 699                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 700                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 701                                NAND_NCE | NAND_CTRL_CHANGE);
 702                 return;
 703
 704         case NAND_CMD_READ0:
 705                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 706                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 707                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 708                                NAND_NCE | NAND_CTRL_CHANGE);
 709
 710                 /* This applies to read commands */
 711         default:
 712                 /*
 713                  * If we don't have access to the busy pin, we apply the given
 714                  * command delay
 715                  */
 716                 if (!chip->dev_ready) {
 717                         udelay(chip->chip_delay);
 718                         return;
 719                 }
 720         }
 721
 722         /* Apply this short delay always to ensure that we do wait tWB in
 723          * any case on any machine. */
 724         ndelay(100);
 725
 726         nand_wait_ready(mtd);
 727 }
 728
 729 /**
 730  * panic_nand_get_device - [GENERIC] Get chip for selected access
 731  * @chip:       the nand chip descriptor
 732  * @mtd:        MTD device structure
 733  * @new_state:  the state which is requested
 734  *
 735  * Used when in panic, no locks are taken.
 736  */
 737 static void panic_nand_get_device(struct nand_chip *chip,
 738                       struct mtd_info *mtd, int new_state)
 739 {
 740         /* Hardware controller shared among independend devices */
 741         chip->controller->active = chip;
 742         chip->state = new_state;
 743 }
 744
 745 /**
 746  * nand_get_device - [GENERIC] Get chip for selected access
 747  * @chip:       the nand chip descriptor
 748  * @mtd:        MTD device structure
 749  * @new_state:  the state which is requested
 750  *
 751  * Get the device and lock it for exclusive access
 752  */
 753 static int
 754 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 755 {
 756         spinlock_t *lock = &chip->controller->lock;
 757         wait_queue_head_t *wq = &chip->controller->wq;
 758         DECLARE_WAITQUEUE(wait, current);
 759  retry:
 760         spin_lock(lock);
 761
 762         /* Hardware controller shared among independent devices */
 763         if (!chip->controller->active)
 764                 chip->controller->active = chip;
 765
 766         if (chip->controller->active == chip && chip->state == FL_READY) {
 767                 chip->state = new_state;
 768                 spin_unlock(lock);
 769                 return 0;
 770         }
 771         if (new_state == FL_PM_SUSPENDED) {
 772                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 773                         chip->state = FL_PM_SUSPENDED;
 774                         spin_unlock(lock);
 775                         return 0;
 776                 }
 777         }
 778         set_current_state(TASK_UNINTERRUPTIBLE);
 779         add_wait_queue(wq, &wait);
 780         spin_unlock(lock);
 781         schedule();
 782         remove_wait_queue(wq, &wait);
 783         goto retry;
 784 }
 785
 786 /**
 787  * panic_nand_wait - [GENERIC]  wait until the command is done
 788  * @mtd:        MTD device structure
 789  * @chip:       NAND chip structure
 790  * @timeo:      Timeout
 791  *
 792  * Wait for command done. This is a helper function for nand_wait used when
 793  * we are in interrupt context. May happen when in panic and trying to write
 794  * an oops trough mtdoops.
 795  */
 796 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 797                             unsigned long timeo)
 798 {
 799         int i;
 800         for (i = 0; i < timeo; i++) {
 801                 if (chip->dev_ready) {
 802                         if (chip->dev_ready(mtd))
 803                                 break;
 804                 } else {
 805                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 806                                 break;
 807                 }
 808                 mdelay(1);
 809         }
 810 }
 811
 812 /**
 813  * nand_wait - [DEFAULT]  wait until the command is done
 814  * @mtd:        MTD device structure
 815  * @chip:       NAND chip structure
 816  *
 817  * Wait for command done. This applies to erase and program only
 818  * Erase can take up to 400ms and program up to 20ms according to
 819  * general NAND and SmartMedia specs
 820  */
 821 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 822 {
 823
 824         unsigned long timeo = jiffies;
 825         int status, state = chip->state;
 826
 827         if (state == FL_ERASING)
 828                 timeo += (HZ * 400) / 1000;
 829         else
 830                 timeo += (HZ * 20) / 1000;
 831
 832         led_trigger_event(nand_led_trigger, LED_FULL);
 833
 834         /* Apply this short delay always to ensure that we do wait tWB in
 835          * any case on any machine. */
 836         ndelay(100);
 837
 838         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 839                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 840         else
 841                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 842
 843         if (in_interrupt() || oops_in_progress)
 844                 panic_nand_wait(mtd, chip, timeo);
 845         else {
 846                 while (time_before(jiffies, timeo)) {
 847                         if (chip->dev_ready) {
 848                                 if (chip->dev_ready(mtd))
 849                                         break;
 850                         } else {
 851                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 852                                         break;
 853                         }
 854                         cond_resched();
 855                 }
 856         }
 857         led_trigger_event(nand_led_trigger, LED_OFF);
 858
 859         status = (int)chip->read_byte(mtd);
 860         return status;
 861 }
 862
 863 /**
 864  * __nand_unlock - [REPLACABLE] unlocks specified locked blockes
 865  *
 866  * @param mtd - mtd info
 867  * @param ofs - offset to start unlock from
 868  * @param len - length to unlock
 869  * @invert -  when = 0, unlock the range of blocks within the lower and
 870  *                      upper boundary address
 871  *            whne = 1, unlock the range of blocks outside the boundaries
 872  *                      of the lower and upper boundary address
 873  *
 874  * @return - unlock status
 875  */
 876 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 877                                         uint64_t len, int invert)
 878 {
 879         int ret = 0;
 880         int status, page;
 881         struct nand_chip *chip = mtd->priv;
 882
 883         /* Submit address of first page to unlock */
 884         page = ofs >> chip->page_shift;
 885         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 886
 887         /* Submit address of last page to unlock */
 888         page = (ofs + len) >> chip->page_shift;
 889         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 890                                 (page | invert) & chip->pagemask);
 891
 892         /* Call wait ready function */
 893         status = chip->waitfunc(mtd, chip);
 894         udelay(1000);
 895         /* See if device thinks it succeeded */
 896         if (status & 0x01) {
 897                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
 898                                         __func__, status);
 899                 ret = -EIO;
 900         }
 901
 902         return ret;
 903 }
 904
 905 /**
 906  * nand_unlock - [REPLACABLE] unlocks specified locked blockes
 907  *
 908  * @param mtd - mtd info
 909  * @param ofs - offset to start unlock from
 910  * @param len - length to unlock
 911  *
 912  * @return - unlock status
 913  */
 914 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 915 {
 916         int ret = 0;
 917         int chipnr;
 918         struct nand_chip *chip = mtd->priv;
 919
 920         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 921                         __func__, (unsigned long long)ofs, len);
 922
 923         if (check_offs_len(mtd, ofs, len))
 924                 ret = -EINVAL;
 925
 926         /* Align to last block address if size addresses end of the device */
 927         if (ofs + len == mtd->size)
 928                 len -= mtd->erasesize;
 929
 930         nand_get_device(chip, mtd, FL_UNLOCKING);
 931
 932         /* Shift to get chip number */
 933         chipnr = ofs >> chip->chip_shift;
 934
 935         chip->select_chip(mtd, chipnr);
 936
 937         /* Check, if it is write protected */
 938         if (nand_check_wp(mtd)) {
 939                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 940                                         __func__);
 941                 ret = -EIO;
 942                 goto out;
 943         }
 944
 945         ret = __nand_unlock(mtd, ofs, len, 0);
 946
 947 out:
 948         /* de-select the NAND device */
 949         chip->select_chip(mtd, -1);
 950
 951         nand_release_device(mtd);
 952
 953         return ret;
 954 }
 955
 956 /**
 957  * nand_lock - [REPLACABLE] locks all blockes present in the device
 958  *
 959  * @param mtd - mtd info
 960  * @param ofs - offset to start unlock from
 961  * @param len - length to unlock
 962  *
 963  * @return - lock status
 964  *
 965  * This feature is not support in many NAND parts. 'Micron' NAND parts
 966  * do have this feature, but it allows only to lock all blocks not for
 967  * specified range for block.
 968  *
 969  * Implementing 'lock' feature by making use of 'unlock', for now.
 970  */
 971 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 972 {
 973         int ret = 0;
 974         int chipnr, status, page;
 975         struct nand_chip *chip = mtd->priv;
 976
 977         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 978                         __func__, (unsigned long long)ofs, len);
 979
 980         if (check_offs_len(mtd, ofs, len))
 981                 ret = -EINVAL;
 982
 983         nand_get_device(chip, mtd, FL_LOCKING);
 984
 985         /* Shift to get chip number */
 986         chipnr = ofs >> chip->chip_shift;
 987
 988         chip->select_chip(mtd, chipnr);
 989
 990         /* Check, if it is write protected */
 991         if (nand_check_wp(mtd)) {
 992                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 993                                         __func__);
 994                 status = MTD_ERASE_FAILED;
 995                 ret = -EIO;
 996                 goto out;
 997         }
 998
 999         /* Submit address of first page to lock */
1000         page = ofs >> chip->page_shift;
1001         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1002
1003         /* Call wait ready function */
1004         status = chip->waitfunc(mtd, chip);
1005         udelay(1000);
1006         /* See if device thinks it succeeded */
1007         if (status & 0x01) {
1008                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1009                                         __func__, status);
1010                 ret = -EIO;
1011                 goto out;
1012         }
1013
1014         ret = __nand_unlock(mtd, ofs, len, 0x1);
1015
1016 out:
1017         /* de-select the NAND device */
1018         chip->select_chip(mtd, -1);
1019
1020         nand_release_device(mtd);
1021
1022         return ret;
1023 }
1024
1025 /**
1026  * nand_read_page_raw - [Intern] read raw page data without ecc
1027  * @mtd:        mtd info structure
1028  * @chip:       nand chip info structure
1029  * @buf:        buffer to store read data
1030  * @page:       page number to read
1031  *
1032  * Not for syndrome calculating ecc controllers, which use a special oob layout
1033  */
1034 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1035                               uint8_t *buf, int page)
1036 {
1037         chip->read_buf(mtd, buf, mtd->writesize);
1038         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1039         return 0;
1040 }
1041
1042 /**
1043  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1044  * @mtd:        mtd info structure
1045  * @chip:       nand chip info structure
1046  * @buf:        buffer to store read data
1047  * @page:       page number to read
1048  *
1049  * We need a special oob layout and handling even when OOB isn't used.
1050  */
1051 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1052                               uint8_t *buf, int page)
1053 {
1054         int eccsize = chip->ecc.size;
1055         int eccbytes = chip->ecc.bytes;
1056         uint8_t *oob = chip->oob_poi;
1057         int steps, size;
1058
1059         for (steps = chip->ecc.steps; steps > 0; steps--) {
1060                 chip->read_buf(mtd, buf, eccsize);
1061                 buf += eccsize;
1062
1063                 if (chip->ecc.prepad) {
1064                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1065                         oob += chip->ecc.prepad;
1066                 }
1067
1068                 chip->read_buf(mtd, oob, eccbytes);
1069                 oob += eccbytes;
1070
1071                 if (chip->ecc.postpad) {
1072                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1073                         oob += chip->ecc.postpad;
1074                 }
1075         }
1076
1077         size = mtd->oobsize - (oob - chip->oob_poi);
1078         if (size)
1079                 chip->read_buf(mtd, oob, size);
1080
1081         return 0;
1082 }
1083
1084 /**
1085  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1086  * @mtd:        mtd info structure
1087  * @chip:       nand chip info structure
1088  * @buf:        buffer to store read data
1089  * @page:       page number to read
1090  */
1091 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1092                                 uint8_t *buf, int page)
1093 {
1094         int i, eccsize = chip->ecc.size;
1095         int eccbytes = chip->ecc.bytes;
1096         int eccsteps = chip->ecc.steps;
1097         uint8_t *p = buf;
1098         uint8_t *ecc_calc = chip->buffers->ecccalc;
1099         uint8_t *ecc_code = chip->buffers->ecccode;
1100         uint32_t *eccpos = chip->ecc.layout->eccpos;
1101
1102         chip->ecc.read_page_raw(mtd, chip, buf, page);
1103
1104         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1105                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1106
1107         for (i = 0; i < chip->ecc.total; i++)
1108                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1109
1110         eccsteps = chip->ecc.steps;
1111         p = buf;
1112
1113         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1114                 int stat;
1115
1116                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1117                 if (stat < 0)
1118                         mtd->ecc_stats.failed++;
1119                 else
1120                         mtd->ecc_stats.corrected += stat;
1121         }
1122         return 0;
1123 }
1124
1125 /**
1126  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1127  * @mtd:        mtd info structure
1128  * @chip:       nand chip info structure
1129  * @data_offs:  offset of requested data within the page
1130  * @readlen:    data length
1131  * @bufpoi:     buffer to store read data
1132  */
1133 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1134 {
1135         int start_step, end_step, num_steps;
1136         uint32_t *eccpos = chip->ecc.layout->eccpos;
1137         uint8_t *p;
1138         int data_col_addr, i, gaps = 0;
1139         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1140         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1141
1142         /* Column address wihin the page aligned to ECC size (256bytes). */
1143         start_step = data_offs / chip->ecc.size;
1144         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1145         num_steps = end_step - start_step + 1;
1146
1147         /* Data size aligned to ECC ecc.size*/
1148         datafrag_len = num_steps * chip->ecc.size;
1149         eccfrag_len = num_steps * chip->ecc.bytes;
1150
1151         data_col_addr = start_step * chip->ecc.size;
1152         /* If we read not a page aligned data */
1153         if (data_col_addr != 0)
1154                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1155
1156         p = bufpoi + data_col_addr;
1157         chip->read_buf(mtd, p, datafrag_len);
1158
1159         /* Calculate  ECC */
1160         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1161                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1162
1163         /* The performance is faster if to position offsets
1164            according to ecc.pos. Let make sure here that
1165            there are no gaps in ecc positions */
1166         for (i = 0; i < eccfrag_len - 1; i++) {
1167                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1168                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1169                         gaps = 1;
1170                         break;
1171                 }
1172         }
1173         if (gaps) {
1174                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1175                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1176         } else {
1177                 /* send the command to read the particular ecc bytes */
1178                 /* take care about buswidth alignment in read_buf */
1179                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1180                 aligned_len = eccfrag_len;
1181                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1182                         aligned_len++;
1183                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1184                         aligned_len++;
1185
1186                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1187                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1188         }
1189
1190         for (i = 0; i < eccfrag_len; i++)
1191                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1192
1193         p = bufpoi + data_col_addr;
1194         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1195                 int stat;
1196
1197                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1198                 if (stat == -1)
1199                         mtd->ecc_stats.failed++;
1200                 else
1201                         mtd->ecc_stats.corrected += stat;
1202         }
1203         return 0;
1204 }
1205
1206 /**
1207  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1208  * @mtd:        mtd info structure
1209  * @chip:       nand chip info structure
1210  * @buf:        buffer to store read data
1211  * @page:       page number to read
1212  *
1213  * Not for syndrome calculating ecc controllers which need a special oob layout
1214  */
1215 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1216                                 uint8_t *buf, int page)
1217 {
1218         int i, eccsize = chip->ecc.size;
1219         int eccbytes = chip->ecc.bytes;
1220         int eccsteps = chip->ecc.steps;
1221         uint8_t *p = buf;
1222         uint8_t *ecc_calc = chip->buffers->ecccalc;
1223         uint8_t *ecc_code = chip->buffers->ecccode;
1224         uint32_t *eccpos = chip->ecc.layout->eccpos;
1225
1226         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1227                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1228                 chip->read_buf(mtd, p, eccsize);
1229                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1230         }
1231         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1232
1233         for (i = 0; i < chip->ecc.total; i++)
1234                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1235
1236         eccsteps = chip->ecc.steps;
1237         p = buf;
1238
1239         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1240                 int stat;
1241
1242                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1243                 if (stat < 0)
1244                         mtd->ecc_stats.failed++;
1245                 else
1246                         mtd->ecc_stats.corrected += stat;
1247         }
1248         return 0;
1249 }
1250
1251 /**
1252  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1253  * @mtd:        mtd info structure
1254  * @chip:       nand chip info structure
1255  * @buf:        buffer to store read data
1256  * @page:       page number to read
1257  *
1258  * Hardware ECC for large page chips, require OOB to be read first.
1259  * For this ECC mode, the write_page method is re-used from ECC_HW.
1260  * These methods read/write ECC from the OOB area, unlike the
1261  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1262  * "infix ECC" scheme and reads/writes ECC from the data area, by
1263  * overwriting the NAND manufacturer bad block markings.
1264  */
1265 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1266         struct nand_chip *chip, uint8_t *buf, int page)
1267 {
1268         int i, eccsize = chip->ecc.size;
1269         int eccbytes = chip->ecc.bytes;
1270         int eccsteps = chip->ecc.steps;
1271         uint8_t *p = buf;
1272         uint8_t *ecc_code = chip->buffers->ecccode;
1273         uint32_t *eccpos = chip->ecc.layout->eccpos;
1274         uint8_t *ecc_calc = chip->buffers->ecccalc;
1275
1276         /* Read the OOB area first */
1277         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1278         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1279         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1280
1281         for (i = 0; i < chip->ecc.total; i++)
1282                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1283
1284         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1285                 int stat;
1286
1287                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1288                 chip->read_buf(mtd, p, eccsize);
1289                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1290
1291                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1292                 if (stat < 0)
1293                         mtd->ecc_stats.failed++;
1294                 else
1295                         mtd->ecc_stats.corrected += stat;
1296         }
1297         return 0;
1298 }
1299
1300 /**
1301  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1302  * @mtd:        mtd info structure
1303  * @chip:       nand chip info structure
1304  * @buf:        buffer to store read data
1305  * @page:       page number to read
1306  *
1307  * The hw generator calculates the error syndrome automatically. Therefor
1308  * we need a special oob layout and handling.
1309  */
1310 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1311                                    uint8_t *buf, int page)
1312 {
1313         int i, eccsize = chip->ecc.size;
1314         int eccbytes = chip->ecc.bytes;
1315         int eccsteps = chip->ecc.steps;
1316         uint8_t *p = buf;
1317         uint8_t *oob = chip->oob_poi;
1318
1319         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1320                 int stat;
1321
1322                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1323                 chip->read_buf(mtd, p, eccsize);
1324
1325                 if (chip->ecc.prepad) {
1326                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1327                         oob += chip->ecc.prepad;
1328                 }
1329
1330                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1331                 chip->read_buf(mtd, oob, eccbytes);
1332                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1333
1334                 if (stat < 0)
1335                         mtd->ecc_stats.failed++;
1336                 else
1337                         mtd->ecc_stats.corrected += stat;
1338
1339                 oob += eccbytes;
1340
1341                 if (chip->ecc.postpad) {
1342                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1343                         oob += chip->ecc.postpad;
1344                 }
1345         }
1346
1347         /* Calculate remaining oob bytes */
1348         i = mtd->oobsize - (oob - chip->oob_poi);
1349         if (i)
1350                 chip->read_buf(mtd, oob, i);
1351
1352         return 0;
1353 }
1354
1355 /**
1356  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1357  * @chip:       nand chip structure
1358  * @oob:        oob destination address
1359  * @ops:        oob ops structure
1360  * @len:        size of oob to transfer
1361  */
1362 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1363                                   struct mtd_oob_ops *ops, size_t len)
1364 {
1365         switch(ops->mode) {
1366
1367         case MTD_OOB_PLACE:
1368         case MTD_OOB_RAW:
1369                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1370                 return oob + len;
1371
1372         case MTD_OOB_AUTO: {
1373                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1374                 uint32_t boffs = 0, roffs = ops->ooboffs;
1375                 size_t bytes = 0;
1376
1377                 for(; free->length && len; free++, len -= bytes) {
1378                         /* Read request not from offset 0 ? */
1379                         if (unlikely(roffs)) {
1380                                 if (roffs >= free->length) {
1381                                         roffs -= free->length;
1382                                         continue;
1383                                 }
1384                                 boffs = free->offset + roffs;
1385                                 bytes = min_t(size_t, len,
1386                                               (free->length - roffs));
1387                                 roffs = 0;
1388                         } else {
1389                                 bytes = min_t(size_t, len, free->length);
1390                                 boffs = free->offset;
1391                         }
1392                         memcpy(oob, chip->oob_poi + boffs, bytes);
1393                         oob += bytes;
1394                 }
1395                 return oob;
1396         }
1397         default:
1398                 BUG();
1399         }
1400         return NULL;
1401 }
1402
1403 /**
1404  * nand_do_read_ops - [Internal] Read data with ECC
1405  *
1406  * @mtd:        MTD device structure
1407  * @from:       offset to read from
1408  * @ops:        oob ops structure
1409  *
1410  * Internal function. Called with chip held.
1411  */
1412 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1413                             struct mtd_oob_ops *ops)
1414 {
1415         int chipnr, page, realpage, col, bytes, aligned;
1416         struct nand_chip *chip = mtd->priv;
1417         struct mtd_ecc_stats stats;
1418         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1419         int sndcmd = 1;
1420         int ret = 0;
1421         uint32_t readlen = ops->len;
1422         uint32_t oobreadlen = ops->ooblen;
1423         uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1424                 mtd->oobavail : mtd->oobsize;
1425
1426         uint8_t *bufpoi, *oob, *buf;
1427
1428         stats = mtd->ecc_stats;
1429
1430         chipnr = (int)(from >> chip->chip_shift);
1431         chip->select_chip(mtd, chipnr);
1432
1433         realpage = (int)(from >> chip->page_shift);
1434         page = realpage & chip->pagemask;
1435
1436         col = (int)(from & (mtd->writesize - 1));
1437
1438         buf = ops->datbuf;
1439         oob = ops->oobbuf;
1440
1441         while(1) {
1442                 bytes = min(mtd->writesize - col, readlen);
1443                 aligned = (bytes == mtd->writesize);
1444
1445                 /* Is the current page in the buffer ? */
1446                 if (realpage != chip->pagebuf || oob) {
1447                         bufpoi = aligned ? buf : chip->buffers->databuf;
1448
1449                         if (likely(sndcmd)) {
1450                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1451                                 sndcmd = 0;
1452                         }
1453
1454                         /* Now read the page into the buffer */
1455                         if (unlikely(ops->mode == MTD_OOB_RAW))
1456                                 ret = chip->ecc.read_page_raw(mtd, chip,
1457                                                               bufpoi, page);
1458                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1459                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1460                         else
1461                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1462                                                           page);
1463                         if (ret < 0)
1464                                 break;
1465
1466                         /* Transfer not aligned data */
1467                         if (!aligned) {
1468                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1469                                         chip->pagebuf = realpage;
1470                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1471                         }
1472
1473                         buf += bytes;
1474
1475                         if (unlikely(oob)) {
1476
1477                                 /* Raw mode does data:oob:data:oob */
1478                                 if (ops->mode != MTD_OOB_RAW) {
1479                                         int toread = min(oobreadlen,
1480                                                                 max_oobsize);
1481                                         if (toread) {
1482                                                 oob = nand_transfer_oob(chip,
1483                                                         oob, ops, toread);
1484                                                 oobreadlen -= toread;
1485                                         }
1486                                 } else
1487                                         buf = nand_transfer_oob(chip,
1488                                                 buf, ops, mtd->oobsize);
1489                         }
1490
1491                         if (!(chip->options & NAND_NO_READRDY)) {
1492                                 /*
1493                                  * Apply delay or wait for ready/busy pin. Do
1494                                  * this before the AUTOINCR check, so no
1495                                  * problems arise if a chip which does auto
1496                                  * increment is marked as NOAUTOINCR by the
1497                                  * board driver.
1498                                  */
1499                                 if (!chip->dev_ready)
1500                                         udelay(chip->chip_delay);
1501                                 else
1502                                         nand_wait_ready(mtd);
1503                         }
1504                 } else {
1505                         memcpy(buf, chip->buffers->databuf + col, bytes);
1506                         buf += bytes;
1507                 }
1508
1509                 readlen -= bytes;
1510
1511                 if (!readlen)
1512                         break;
1513
1514                 /* For subsequent reads align to page boundary. */
1515                 col = 0;
1516                 /* Increment page address */
1517                 realpage++;
1518
1519                 page = realpage & chip->pagemask;
1520                 /* Check, if we cross a chip boundary */
1521                 if (!page) {
1522                         chipnr++;
1523                         chip->select_chip(mtd, -1);
1524                         chip->select_chip(mtd, chipnr);
1525                 }
1526
1527                 /* Check, if the chip supports auto page increment
1528                  * or if we have hit a block boundary.
1529                  */
1530                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1531                         sndcmd = 1;
1532         }
1533
1534         ops->retlen = ops->len - (size_t) readlen;
1535         if (oob)
1536                 ops->oobretlen = ops->ooblen - oobreadlen;
1537
1538         if (ret)
1539                 return ret;
1540
1541         if (mtd->ecc_stats.failed - stats.failed)
1542                 return -EBADMSG;
1543
1544         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1545 }
1546
1547 /**
1548  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1549  * @mtd:        MTD device structure
1550  * @from:       offset to read from
1551  * @len:        number of bytes to read
1552  * @retlen:     pointer to variable to store the number of read bytes
1553  * @buf:        the databuffer to put data
1554  *
1555  * Get hold of the chip and call nand_do_read
1556  */
1557 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1558                      size_t *retlen, uint8_t *buf)
1559 {
1560         struct nand_chip *chip = mtd->priv;
1561         int ret;
1562
1563         /* Do not allow reads past end of device */
1564         if ((from + len) > mtd->size)
1565                 return -EINVAL;
1566         if (!len)
1567                 return 0;
1568
1569         nand_get_device(chip, mtd, FL_READING);
1570
1571         chip->ops.len = len;
1572         chip->ops.datbuf = buf;
1573         chip->ops.oobbuf = NULL;
1574
1575         ret = nand_do_read_ops(mtd, from, &chip->ops);
1576
1577         *retlen = chip->ops.retlen;
1578
1579         nand_release_device(mtd);
1580
1581         return ret;
1582 }
1583
1584 /**
1585  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1586  * @mtd:        mtd info structure
1587  * @chip:       nand chip info structure
1588  * @page:       page number to read
1589  * @sndcmd:     flag whether to issue read command or not
1590  */
1591 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1592                              int page, int sndcmd)
1593 {
1594         if (sndcmd) {
1595                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1596                 sndcmd = 0;
1597         }
1598         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1599         return sndcmd;
1600 }
1601
1602 /**
1603  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1604  *                          with syndromes
1605  * @mtd:        mtd info structure
1606  * @chip:       nand chip info structure
1607  * @page:       page number to read
1608  * @sndcmd:     flag whether to issue read command or not
1609  */
1610 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1611                                   int page, int sndcmd)
1612 {
1613         uint8_t *buf = chip->oob_poi;
1614         int length = mtd->oobsize;
1615         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1616         int eccsize = chip->ecc.size;
1617         uint8_t *bufpoi = buf;
1618         int i, toread, sndrnd = 0, pos;
1619
1620         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1621         for (i = 0; i < chip->ecc.steps; i++) {
1622                 if (sndrnd) {
1623                         pos = eccsize + i * (eccsize + chunk);
1624                         if (mtd->writesize > 512)
1625                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1626                         else
1627                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1628                 } else
1629                         sndrnd = 1;
1630                 toread = min_t(int, length, chunk);
1631                 chip->read_buf(mtd, bufpoi, toread);
1632                 bufpoi += toread;
1633                 length -= toread;
1634         }
1635         if (length > 0)
1636                 chip->read_buf(mtd, bufpoi, length);
1637
1638         return 1;
1639 }
1640
1641 /**
1642  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1643  * @mtd:        mtd info structure
1644  * @chip:       nand chip info structure
1645  * @page:       page number to write
1646  */
1647 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1648                               int page)
1649 {
1650         int status = 0;
1651         const uint8_t *buf = chip->oob_poi;
1652         int length = mtd->oobsize;
1653
1654         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1655         chip->write_buf(mtd, buf, length);
1656         /* Send command to program the OOB data */
1657         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1658
1659         status = chip->waitfunc(mtd, chip);
1660
1661         return status & NAND_STATUS_FAIL ? -EIO : 0;
1662 }
1663
1664 /**
1665  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1666  *                           with syndrome - only for large page flash !
1667  * @mtd:        mtd info structure
1668  * @chip:       nand chip info structure
1669  * @page:       page number to write
1670  */
1671 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1672                                    struct nand_chip *chip, int page)
1673 {
1674         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1675         int eccsize = chip->ecc.size, length = mtd->oobsize;
1676         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1677         const uint8_t *bufpoi = chip->oob_poi;
1678
1679         /*
1680          * data-ecc-data-ecc ... ecc-oob
1681          * or
1682          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1683          */
1684         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1685                 pos = steps * (eccsize + chunk);
1686                 steps = 0;
1687         } else
1688                 pos = eccsize;
1689
1690         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1691         for (i = 0; i < steps; i++) {
1692                 if (sndcmd) {
1693                         if (mtd->writesize <= 512) {
1694                                 uint32_t fill = 0xFFFFFFFF;
1695
1696                                 len = eccsize;
1697                                 while (len > 0) {
1698                                         int num = min_t(int, len, 4);
1699                                         chip->write_buf(mtd, (uint8_t *)&fill,
1700                                                         num);
1701                                         len -= num;
1702                                 }
1703                         } else {
1704                                 pos = eccsize + i * (eccsize + chunk);
1705                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1706                         }
1707                 } else
1708                         sndcmd = 1;
1709                 len = min_t(int, length, chunk);
1710                 chip->write_buf(mtd, bufpoi, len);
1711                 bufpoi += len;
1712                 length -= len;
1713         }
1714         if (length > 0)
1715                 chip->write_buf(mtd, bufpoi, length);
1716
1717         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1718         status = chip->waitfunc(mtd, chip);
1719
1720         return status & NAND_STATUS_FAIL ? -EIO : 0;
1721 }
1722
1723 /**
1724  * nand_do_read_oob - [Intern] NAND read out-of-band
1725  * @mtd:        MTD device structure
1726  * @from:       offset to read from
1727  * @ops:        oob operations description structure
1728  *
1729  * NAND read out-of-band data from the spare area
1730  */
1731 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1732                             struct mtd_oob_ops *ops)
1733 {
1734         int page, realpage, chipnr, sndcmd = 1;
1735         struct nand_chip *chip = mtd->priv;
1736         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1737         int readlen = ops->ooblen;
1738         int len;
1739         uint8_t *buf = ops->oobbuf;
1740
1741         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1742                         __func__, (unsigned long long)from, readlen);
1743
1744         if (ops->mode == MTD_OOB_AUTO)
1745                 len = chip->ecc.layout->oobavail;
1746         else
1747                 len = mtd->oobsize;
1748
1749         if (unlikely(ops->ooboffs >= len)) {
1750                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1751                                         "outside oob\n", __func__);
1752                 return -EINVAL;
1753         }
1754
1755         /* Do not allow reads past end of device */
1756         if (unlikely(from >= mtd->size ||
1757                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1758                                         (from >> chip->page_shift)) * len)) {
1759                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1760                                         "of device\n", __func__);
1761                 return -EINVAL;
1762         }
1763
1764         chipnr = (int)(from >> chip->chip_shift);
1765         chip->select_chip(mtd, chipnr);
1766
1767         /* Shift to get page */
1768         realpage = (int)(from >> chip->page_shift);
1769         page = realpage & chip->pagemask;
1770
1771         while(1) {
1772                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1773
1774                 len = min(len, readlen);
1775                 buf = nand_transfer_oob(chip, buf, ops, len);
1776
1777                 if (!(chip->options & NAND_NO_READRDY)) {
1778                         /*
1779                          * Apply delay or wait for ready/busy pin. Do this
1780                          * before the AUTOINCR check, so no problems arise if a
1781                          * chip which does auto increment is marked as
1782                          * NOAUTOINCR by the board driver.
1783                          */
1784                         if (!chip->dev_ready)
1785                                 udelay(chip->chip_delay);
1786                         else
1787                                 nand_wait_ready(mtd);
1788                 }
1789
1790                 readlen -= len;
1791                 if (!readlen)
1792                         break;
1793
1794                 /* Increment page address */
1795                 realpage++;
1796
1797                 page = realpage & chip->pagemask;
1798                 /* Check, if we cross a chip boundary */
1799                 if (!page) {
1800                         chipnr++;
1801                         chip->select_chip(mtd, -1);
1802                         chip->select_chip(mtd, chipnr);
1803                 }
1804
1805                 /* Check, if the chip supports auto page increment
1806                  * or if we have hit a block boundary.
1807                  */
1808                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1809                         sndcmd = 1;
1810         }
1811
1812         ops->oobretlen = ops->ooblen;
1813         return 0;
1814 }
1815
1816 /**
1817  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1818  * @mtd:        MTD device structure
1819  * @from:       offset to read from
1820  * @ops:        oob operation description structure
1821  *
1822  * NAND read data and/or out-of-band data
1823  */
1824 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1825                          struct mtd_oob_ops *ops)
1826 {
1827         struct nand_chip *chip = mtd->priv;
1828         int ret = -ENOTSUPP;
1829
1830         ops->retlen = 0;
1831
1832         /* Do not allow reads past end of device */
1833         if (ops->datbuf && (from + ops->len) > mtd->size) {
1834                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1835                                 "beyond end of device\n", __func__);
1836                 return -EINVAL;
1837         }
1838
1839         nand_get_device(chip, mtd, FL_READING);
1840
1841         switch(ops->mode) {
1842         case MTD_OOB_PLACE:
1843         case MTD_OOB_AUTO:
1844         case MTD_OOB_RAW:
1845                 break;
1846
1847         default:
1848                 goto out;
1849         }
1850
1851         if (!ops->datbuf)
1852                 ret = nand_do_read_oob(mtd, from, ops);
1853         else
1854                 ret = nand_do_read_ops(mtd, from, ops);
1855
1856  out:
1857         nand_release_device(mtd);
1858         return ret;
1859 }
1860
1861
1862 /**
1863  * nand_write_page_raw - [Intern] raw page write function
1864  * @mtd:        mtd info structure
1865  * @chip:       nand chip info structure
1866  * @buf:        data buffer
1867  *
1868  * Not for syndrome calculating ecc controllers, which use a special oob layout
1869  */
1870 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1871                                 const uint8_t *buf)
1872 {
1873         chip->write_buf(mtd, buf, mtd->writesize);
1874         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1875 }
1876
1877 /**
1878  * nand_write_page_raw_syndrome - [Intern] raw page write function
1879  * @mtd:        mtd info structure
1880  * @chip:       nand chip info structure
1881  * @buf:        data buffer
1882  *
1883  * We need a special oob layout and handling even when ECC isn't checked.
1884  */
1885 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1886                                 const uint8_t *buf)
1887 {
1888         int eccsize = chip->ecc.size;
1889         int eccbytes = chip->ecc.bytes;
1890         uint8_t *oob = chip->oob_poi;
1891         int steps, size;
1892
1893         for (steps = chip->ecc.steps; steps > 0; steps--) {
1894                 chip->write_buf(mtd, buf, eccsize);
1895                 buf += eccsize;
1896
1897                 if (chip->ecc.prepad) {
1898                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1899                         oob += chip->ecc.prepad;
1900                 }
1901
1902                 chip->read_buf(mtd, oob, eccbytes);
1903                 oob += eccbytes;
1904
1905                 if (chip->ecc.postpad) {
1906                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1907                         oob += chip->ecc.postpad;
1908                 }
1909         }
1910
1911         size = mtd->oobsize - (oob - chip->oob_poi);
1912         if (size)
1913                 chip->write_buf(mtd, oob, size);
1914 }
1915 /**
1916  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1917  * @mtd:        mtd info structure
1918  * @chip:       nand chip info structure
1919  * @buf:        data buffer
1920  */
1921 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1922                                   const uint8_t *buf)
1923 {
1924         int i, eccsize = chip->ecc.size;
1925         int eccbytes = chip->ecc.bytes;
1926         int eccsteps = chip->ecc.steps;
1927         uint8_t *ecc_calc = chip->buffers->ecccalc;
1928         const uint8_t *p = buf;
1929         uint32_t *eccpos = chip->ecc.layout->eccpos;
1930
1931         /* Software ecc calculation */
1932         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1933                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1934
1935         for (i = 0; i < chip->ecc.total; i++)
1936                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1937
1938         chip->ecc.write_page_raw(mtd, chip, buf);
1939 }
1940
1941 /**
1942  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1943  * @mtd:        mtd info structure
1944  * @chip:       nand chip info structure
1945  * @buf:        data buffer
1946  */
1947 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1948                                   const uint8_t *buf)
1949 {
1950         int i, eccsize = chip->ecc.size;
1951         int eccbytes = chip->ecc.bytes;
1952         int eccsteps = chip->ecc.steps;
1953         uint8_t *ecc_calc = chip->buffers->ecccalc;
1954         const uint8_t *p = buf;
1955         uint32_t *eccpos = chip->ecc.layout->eccpos;
1956
1957         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1958                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1959                 chip->write_buf(mtd, p, eccsize);
1960                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1961         }
1962
1963         for (i = 0; i < chip->ecc.total; i++)
1964                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1965
1966         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1967 }
1968
1969 /**
1970  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1971  * @mtd:        mtd info structure
1972  * @chip:       nand chip info structure
1973  * @buf:        data buffer
1974  *
1975  * The hw generator calculates the error syndrome automatically. Therefor
1976  * we need a special oob layout and handling.
1977  */
1978 static void nand_write_page_syndrome(struct mtd_info *mtd,
1979                                     struct nand_chip *chip, const uint8_t *buf)
1980 {
1981         int i, eccsize = chip->ecc.size;
1982         int eccbytes = chip->ecc.bytes;
1983         int eccsteps = chip->ecc.steps;
1984         const uint8_t *p = buf;
1985         uint8_t *oob = chip->oob_poi;
1986
1987         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1988
1989                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1990                 chip->write_buf(mtd, p, eccsize);
1991
1992                 if (chip->ecc.prepad) {
1993                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1994                         oob += chip->ecc.prepad;
1995                 }
1996
1997                 chip->ecc.calculate(mtd, p, oob);
1998                 chip->write_buf(mtd, oob, eccbytes);
1999                 oob += eccbytes;
2000
2001                 if (chip->ecc.postpad) {
2002                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2003                         oob += chip->ecc.postpad;
2004                 }
2005         }
2006
2007         /* Calculate remaining oob bytes */
2008         i = mtd->oobsize - (oob - chip->oob_poi);
2009         if (i)
2010                 chip->write_buf(mtd, oob, i);
2011 }
2012
2013 /**
2014  * nand_write_page - [REPLACEABLE] write one page
2015  * @mtd:        MTD device structure
2016  * @chip:       NAND chip descriptor
2017  * @buf:        the data to write
2018  * @page:       page number to write
2019  * @cached:     cached programming
2020  * @raw:        use _raw version of write_page
2021  */
2022 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2023                            const uint8_t *buf, int page, int cached, int raw)
2024 {
2025         int status;
2026
2027         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2028
2029         if (unlikely(raw))
2030                 chip->ecc.write_page_raw(mtd, chip, buf);
2031         else
2032                 chip->ecc.write_page(mtd, chip, buf);
2033
2034         /*
2035          * Cached progamming disabled for now, Not sure if its worth the
2036          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2037          */
2038         cached = 0;
2039
2040         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2041
2042                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2043                 status = chip->waitfunc(mtd, chip);
2044                 /*
2045                  * See if operation failed and additional status checks are
2046                  * available
2047                  */
2048                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2049                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2050                                                page);
2051
2052                 if (status & NAND_STATUS_FAIL)
2053                         return -EIO;
2054         } else {
2055                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2056                 status = chip->waitfunc(mtd, chip);
2057         }
2058
2059 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2060         /* Send command to read back the data */
2061         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2062
2063         if (chip->verify_buf(mtd, buf, mtd->writesize))
2064                 return -EIO;
2065 #endif
2066         return 0;
2067 }
2068
2069 /**
2070  * nand_fill_oob - [Internal] Transfer client buffer to oob
2071  * @chip:       nand chip structure
2072  * @oob:        oob data buffer
2073  * @ops:        oob ops structure
2074  */
2075 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2076                                                 struct mtd_oob_ops *ops)
2077 {
2078         switch(ops->mode) {
2079
2080         case MTD_OOB_PLACE:
2081         case MTD_OOB_RAW:
2082                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2083                 return oob + len;
2084
2085         case MTD_OOB_AUTO: {
2086                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2087                 uint32_t boffs = 0, woffs = ops->ooboffs;
2088                 size_t bytes = 0;
2089
2090                 for(; free->length && len; free++, len -= bytes) {
2091                         /* Write request not from offset 0 ? */
2092                         if (unlikely(woffs)) {
2093                                 if (woffs >= free->length) {
2094                                         woffs -= free->length;
2095                                         continue;
2096                                 }
2097                                 boffs = free->offset + woffs;
2098                                 bytes = min_t(size_t, len,
2099                                               (free->length - woffs));
2100                                 woffs = 0;
2101                         } else {
2102                                 bytes = min_t(size_t, len, free->length);
2103                                 boffs = free->offset;
2104                         }
2105                         memcpy(chip->oob_poi + boffs, oob, bytes);
2106                         oob += bytes;
2107                 }
2108                 return oob;
2109         }
2110         default:
2111                 BUG();
2112         }
2113         return NULL;
2114 }
2115
2116 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
2117
2118 /**
2119  * nand_do_write_ops - [Internal] NAND write with ECC
2120  * @mtd:        MTD device structure
2121  * @to:         offset to write to
2122  * @ops:        oob operations description structure
2123  *
2124  * NAND write with ECC
2125  */
2126 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2127                              struct mtd_oob_ops *ops)
2128 {
2129         int chipnr, realpage, page, blockmask, column;
2130         struct nand_chip *chip = mtd->priv;
2131         uint32_t writelen = ops->len;
2132
2133         uint32_t oobwritelen = ops->ooblen;
2134         uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2135                                 mtd->oobavail : mtd->oobsize;
2136
2137         uint8_t *oob = ops->oobbuf;
2138         uint8_t *buf = ops->datbuf;
2139         int ret, subpage;
2140
2141         ops->retlen = 0;
2142         if (!writelen)
2143                 return 0;
2144
2145         /* reject writes, which are not page aligned */
2146         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2147                 printk(KERN_NOTICE "%s: Attempt to write not "
2148                                 "page aligned data\n", __func__);
2149                 return -EINVAL;
2150         }
2151
2152         column = to & (mtd->writesize - 1);
2153         subpage = column || (writelen & (mtd->writesize - 1));
2154
2155         if (subpage && oob)
2156                 return -EINVAL;
2157
2158         chipnr = (int)(to >> chip->chip_shift);
2159         chip->select_chip(mtd, chipnr);
2160
2161         /* Check, if it is write protected */
2162         if (nand_check_wp(mtd))
2163                 return -EIO;
2164
2165         realpage = (int)(to >> chip->page_shift);
2166         page = realpage & chip->pagemask;
2167         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2168
2169         /* Invalidate the page cache, when we write to the cached page */
2170         if (to <= (chip->pagebuf << chip->page_shift) &&
2171             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2172                 chip->pagebuf = -1;
2173
2174         /* If we're not given explicit OOB data, let it be 0xFF */
2175         if (likely(!oob))
2176                 memset(chip->oob_poi, 0xff, mtd->oobsize);
2177
2178         /* Don't allow multipage oob writes with offset */
2179         if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2180                 return -EINVAL;
2181
2182         while(1) {
2183                 int bytes = mtd->writesize;
2184                 int cached = writelen > bytes && page != blockmask;
2185                 uint8_t *wbuf = buf;
2186
2187                 /* Partial page write ? */
2188                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2189                         cached = 0;
2190                         bytes = min_t(int, bytes - column, (int) writelen);
2191                         chip->pagebuf = -1;
2192                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2193                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2194                         wbuf = chip->buffers->databuf;
2195                 }
2196
2197                 if (unlikely(oob)) {
2198                         size_t len = min(oobwritelen, oobmaxlen);
2199                         oob = nand_fill_oob(chip, oob, len, ops);
2200                         oobwritelen -= len;
2201                 }
2202
2203                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2204                                        (ops->mode == MTD_OOB_RAW));
2205                 if (ret)
2206                         break;
2207
2208                 writelen -= bytes;
2209                 if (!writelen)
2210                         break;
2211
2212                 column = 0;
2213                 buf += bytes;
2214                 realpage++;
2215
2216                 page = realpage & chip->pagemask;
2217                 /* Check, if we cross a chip boundary */
2218                 if (!page) {
2219                         chipnr++;
2220                         chip->select_chip(mtd, -1);
2221                         chip->select_chip(mtd, chipnr);
2222                 }
2223         }
2224
2225         ops->retlen = ops->len - writelen;
2226         if (unlikely(oob))
2227                 ops->oobretlen = ops->ooblen;
2228         return ret;
2229 }
2230
2231 /**
2232  * panic_nand_write - [MTD Interface] NAND write with ECC
2233  * @mtd:        MTD device structure
2234  * @to:         offset to write to
2235  * @len:        number of bytes to write
2236  * @retlen:     pointer to variable to store the number of written bytes
2237  * @buf:        the data to write
2238  *
2239  * NAND write with ECC. Used when performing writes in interrupt context, this
2240  * may for example be called by mtdoops when writing an oops while in panic.
2241  */
2242 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2243                             size_t *retlen, const uint8_t *buf)
2244 {
2245         struct nand_chip *chip = mtd->priv;
2246         int ret;
2247
2248         /* Do not allow reads past end of device */
2249         if ((to + len) > mtd->size)
2250                 return -EINVAL;
2251         if (!len)
2252                 return 0;
2253
2254         /* Wait for the device to get ready.  */
2255         panic_nand_wait(mtd, chip, 400);
2256
2257         /* Grab the device.  */
2258         panic_nand_get_device(chip, mtd, FL_WRITING);
2259
2260         chip->ops.len = len;
2261         chip->ops.datbuf = (uint8_t *)buf;
2262         chip->ops.oobbuf = NULL;
2263
2264         ret = nand_do_write_ops(mtd, to, &chip->ops);
2265
2266         *retlen = chip->ops.retlen;
2267         return ret;
2268 }
2269
2270 /**
2271  * nand_write - [MTD Interface] NAND write with ECC
2272  * @mtd:        MTD device structure
2273  * @to:         offset to write to
2274  * @len:        number of bytes to write
2275  * @retlen:     pointer to variable to store the number of written bytes
2276  * @buf:        the data to write
2277  *
2278  * NAND write with ECC
2279  */
2280 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2281                           size_t *retlen, const uint8_t *buf)
2282 {
2283         struct nand_chip *chip = mtd->priv;
2284         int ret;
2285
2286         /* Do not allow reads past end of device */
2287         if ((to + len) > mtd->size)
2288                 return -EINVAL;
2289         if (!len)
2290                 return 0;
2291
2292         nand_get_device(chip, mtd, FL_WRITING);
2293
2294         chip->ops.len = len;
2295         chip->ops.datbuf = (uint8_t *)buf;
2296         chip->ops.oobbuf = NULL;
2297
2298         ret = nand_do_write_ops(mtd, to, &chip->ops);
2299
2300         *retlen = chip->ops.retlen;
2301
2302         nand_release_device(mtd);
2303
2304         return ret;
2305 }
2306
2307 /**
2308  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2309  * @mtd:        MTD device structure
2310  * @to:         offset to write to
2311  * @ops:        oob operation description structure
2312  *
2313  * NAND write out-of-band
2314  */
2315 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2316                              struct mtd_oob_ops *ops)
2317 {
2318         int chipnr, page, status, len;
2319         struct nand_chip *chip = mtd->priv;
2320
2321         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2322                          __func__, (unsigned int)to, (int)ops->ooblen);
2323
2324         if (ops->mode == MTD_OOB_AUTO)
2325                 len = chip->ecc.layout->oobavail;
2326         else
2327                 len = mtd->oobsize;
2328
2329         /* Do not allow write past end of page */
2330         if ((ops->ooboffs + ops->ooblen) > len) {
2331                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2332                                 "past end of page\n", __func__);
2333                 return -EINVAL;
2334         }
2335
2336         if (unlikely(ops->ooboffs >= len)) {
2337                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2338                                 "write outside oob\n", __func__);
2339                 return -EINVAL;
2340         }
2341
2342         /* Do not allow reads past end of device */
2343         if (unlikely(to >= mtd->size ||
2344                      ops->ooboffs + ops->ooblen >
2345                         ((mtd->size >> chip->page_shift) -
2346                          (to >> chip->page_shift)) * len)) {
2347                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2348                                 "end of device\n", __func__);
2349                 return -EINVAL;
2350         }
2351
2352         chipnr = (int)(to >> chip->chip_shift);
2353         chip->select_chip(mtd, chipnr);
2354
2355         /* Shift to get page */
2356         page = (int)(to >> chip->page_shift);
2357
2358         /*
2359          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2360          * of my DiskOnChip 2000 test units) will clear the whole data page too
2361          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2362          * it in the doc2000 driver in August 1999.  dwmw2.
2363          */
2364         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2365
2366         /* Check, if it is write protected */
2367         if (nand_check_wp(mtd))
2368                 return -EROFS;
2369
2370         /* Invalidate the page cache, if we write to the cached page */
2371         if (page == chip->pagebuf)
2372                 chip->pagebuf = -1;
2373
2374         memset(chip->oob_poi, 0xff, mtd->oobsize);
2375         nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2376         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2377         memset(chip->oob_poi, 0xff, mtd->oobsize);
2378
2379         if (status)
2380                 return status;
2381
2382         ops->oobretlen = ops->ooblen;
2383
2384         return 0;
2385 }
2386
2387 /**
2388  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2389  * @mtd:        MTD device structure
2390  * @to:         offset to write to
2391  * @ops:        oob operation description structure
2392  */
2393 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2394                           struct mtd_oob_ops *ops)
2395 {
2396         struct nand_chip *chip = mtd->priv;
2397         int ret = -ENOTSUPP;
2398
2399         ops->retlen = 0;
2400
2401         /* Do not allow writes past end of device */
2402         if (ops->datbuf && (to + ops->len) > mtd->size) {
2403                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2404                                 "end of device\n", __func__);
2405                 return -EINVAL;
2406         }
2407
2408         nand_get_device(chip, mtd, FL_WRITING);
2409
2410         switch(ops->mode) {
2411         case MTD_OOB_PLACE:
2412         case MTD_OOB_AUTO:
2413         case MTD_OOB_RAW:
2414                 break;
2415
2416         default:
2417                 goto out;
2418         }
2419
2420         if (!ops->datbuf)
2421                 ret = nand_do_write_oob(mtd, to, ops);
2422         else
2423                 ret = nand_do_write_ops(mtd, to, ops);
2424
2425  out:
2426         nand_release_device(mtd);
2427         return ret;
2428 }
2429
2430 /**
2431  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2432  * @mtd:        MTD device structure
2433  * @page:       the page address of the block which will be erased
2434  *
2435  * Standard erase command for NAND chips
2436  */
2437 static void single_erase_cmd(struct mtd_info *mtd, int page)
2438 {
2439         struct nand_chip *chip = mtd->priv;
2440         /* Send commands to erase a block */
2441         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2442         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2443 }
2444
2445 /**
2446  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2447  * @mtd:        MTD device structure
2448  * @page:       the page address of the block which will be erased
2449  *
2450  * AND multi block erase command function
2451  * Erase 4 consecutive blocks
2452  */
2453 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2454 {
2455         struct nand_chip *chip = mtd->priv;
2456         /* Send commands to erase a block */
2457         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2458         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2459         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2460         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2461         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2462 }
2463
2464 /**
2465  * nand_erase - [MTD Interface] erase block(s)
2466  * @mtd:        MTD device structure
2467  * @instr:      erase instruction
2468  *
2469  * Erase one ore more blocks
2470  */
2471 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2472 {
2473         return nand_erase_nand(mtd, instr, 0);
2474 }
2475
2476 #define BBT_PAGE_MASK   0xffffff3f
2477 /**
2478  * nand_erase_nand - [Internal] erase block(s)
2479  * @mtd:        MTD device structure
2480  * @instr:      erase instruction
2481  * @allowbbt:   allow erasing the bbt area
2482  *
2483  * Erase one ore more blocks
2484  */
2485 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2486                     int allowbbt)
2487 {
2488         int page, status, pages_per_block, ret, chipnr;
2489         struct nand_chip *chip = mtd->priv;
2490         loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2491         unsigned int bbt_masked_page = 0xffffffff;
2492         loff_t len;
2493
2494         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2495                                 __func__, (unsigned long long)instr->addr,
2496                                 (unsigned long long)instr->len);
2497
2498         if (check_offs_len(mtd, instr->addr, instr->len))
2499                 return -EINVAL;
2500
2501         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2502
2503         /* Grab the lock and see if the device is available */
2504         nand_get_device(chip, mtd, FL_ERASING);
2505
2506         /* Shift to get first page */
2507         page = (int)(instr->addr >> chip->page_shift);
2508         chipnr = (int)(instr->addr >> chip->chip_shift);
2509
2510         /* Calculate pages in each block */
2511         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2512
2513         /* Select the NAND device */
2514         chip->select_chip(mtd, chipnr);
2515
2516         /* Check, if it is write protected */
2517         if (nand_check_wp(mtd)) {
2518                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2519                                         __func__);
2520                 instr->state = MTD_ERASE_FAILED;
2521                 goto erase_exit;
2522         }
2523
2524         /*
2525          * If BBT requires refresh, set the BBT page mask to see if the BBT
2526          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2527          * can not be matched. This is also done when the bbt is actually
2528          * erased to avoid recusrsive updates
2529          */
2530         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2531                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2532
2533         /* Loop through the pages */
2534         len = instr->len;
2535
2536         instr->state = MTD_ERASING;
2537
2538         while (len) {
2539                 /*
2540                  * heck if we have a bad block, we do not erase bad blocks !
2541                  */
2542                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2543                                         chip->page_shift, 0, allowbbt)) {
2544                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2545                                         "at page 0x%08x\n", __func__, page);
2546                         instr->state = MTD_ERASE_FAILED;
2547                         goto erase_exit;
2548                 }
2549
2550                 /*
2551                  * Invalidate the page cache, if we erase the block which
2552                  * contains the current cached page
2553                  */
2554                 if (page <= chip->pagebuf && chip->pagebuf <
2555                     (page + pages_per_block))
2556                         chip->pagebuf = -1;
2557
2558                 chip->erase_cmd(mtd, page & chip->pagemask);
2559
2560                 status = chip->waitfunc(mtd, chip);
2561
2562                 /*
2563                  * See if operation failed and additional status checks are
2564                  * available
2565                  */
2566                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2567                         status = chip->errstat(mtd, chip, FL_ERASING,
2568                                                status, page);
2569
2570                 /* See if block erase succeeded */
2571                 if (status & NAND_STATUS_FAIL) {
2572                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2573                                         "page 0x%08x\n", __func__, page);
2574                         instr->state = MTD_ERASE_FAILED;
2575                         instr->fail_addr =
2576                                 ((loff_t)page << chip->page_shift);
2577                         goto erase_exit;
2578                 }
2579
2580                 /*
2581                  * If BBT requires refresh, set the BBT rewrite flag to the
2582                  * page being erased
2583                  */
2584                 if (bbt_masked_page != 0xffffffff &&
2585                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2586                             rewrite_bbt[chipnr] =
2587                                         ((loff_t)page << chip->page_shift);
2588
2589                 /* Increment page address and decrement length */
2590                 len -= (1 << chip->phys_erase_shift);
2591                 page += pages_per_block;
2592
2593                 /* Check, if we cross a chip boundary */
2594                 if (len && !(page & chip->pagemask)) {
2595                         chipnr++;
2596                         chip->select_chip(mtd, -1);
2597                         chip->select_chip(mtd, chipnr);
2598
2599                         /*
2600                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2601                          * page mask to see if this BBT should be rewritten
2602                          */
2603                         if (bbt_masked_page != 0xffffffff &&
2604                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2605                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2606                                         BBT_PAGE_MASK;
2607                 }
2608         }
2609         instr->state = MTD_ERASE_DONE;
2610
2611  erase_exit:
2612
2613         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2614
2615         /* Deselect and wake up anyone waiting on the device */
2616         nand_release_device(mtd);
2617
2618         /* Do call back function */
2619         if (!ret)
2620                 mtd_erase_callback(instr);
2621
2622         /*
2623          * If BBT requires refresh and erase was successful, rewrite any
2624          * selected bad block tables
2625          */
2626         if (bbt_masked_page == 0xffffffff || ret)
2627                 return ret;
2628
2629         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2630                 if (!rewrite_bbt[chipnr])
2631                         continue;
2632                 /* update the BBT for chip */
2633                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2634                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2635                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2636                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2637         }
2638
2639         /* Return more or less happy */
2640         return ret;
2641 }
2642
2643 /**
2644  * nand_sync - [MTD Interface] sync
2645  * @mtd:        MTD device structure
2646  *
2647  * Sync is actually a wait for chip ready function
2648  */
2649 static void nand_sync(struct mtd_info *mtd)
2650 {
2651         struct nand_chip *chip = mtd->priv;
2652
2653         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2654
2655         /* Grab the lock and see if the device is available */
2656         nand_get_device(chip, mtd, FL_SYNCING);
2657         /* Release it and go back */
2658         nand_release_device(mtd);
2659 }
2660
2661 /**
2662  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2663  * @mtd:        MTD device structure
2664  * @offs:       offset relative to mtd start
2665  */
2666 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2667 {
2668         /* Check for invalid offset */
2669         if (offs > mtd->size)
2670                 return -EINVAL;
2671
2672         return nand_block_checkbad(mtd, offs, 1, 0);
2673 }
2674
2675 /**
2676  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2677  * @mtd:        MTD device structure
2678  * @ofs:        offset relative to mtd start
2679  */
2680 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2681 {
2682         struct nand_chip *chip = mtd->priv;
2683         int ret;
2684
2685         if ((ret = nand_block_isbad(mtd, ofs))) {
2686                 /* If it was bad already, return success and do nothing. */
2687                 if (ret > 0)
2688                         return 0;
2689                 return ret;
2690         }
2691
2692         return chip->block_markbad(mtd, ofs);
2693 }
2694
2695 /**
2696  * nand_suspend - [MTD Interface] Suspend the NAND flash
2697  * @mtd:        MTD device structure
2698  */
2699 static int nand_suspend(struct mtd_info *mtd)
2700 {
2701         struct nand_chip *chip = mtd->priv;
2702
2703         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2704 }
2705
2706 /**
2707  * nand_resume - [MTD Interface] Resume the NAND flash
2708  * @mtd:        MTD device structure
2709  */
2710 static void nand_resume(struct mtd_info *mtd)
2711 {
2712         struct nand_chip *chip = mtd->priv;
2713
2714         if (chip->state == FL_PM_SUSPENDED)
2715                 nand_release_device(mtd);
2716         else
2717                 printk(KERN_ERR "%s called for a chip which is not "
2718                        "in suspended state\n", __func__);
2719 }
2720
2721 /*
2722  * Set default functions
2723  */
2724 static void nand_set_defaults(struct nand_chip *chip, int busw)
2725 {
2726         /* check for proper chip_delay setup, set 20us if not */
2727         if (!chip->chip_delay)
2728                 chip->chip_delay = 20;
2729
2730         /* check, if a user supplied command function given */
2731         if (chip->cmdfunc == NULL)
2732                 chip->cmdfunc = nand_command;
2733
2734         /* check, if a user supplied wait function given */
2735         if (chip->waitfunc == NULL)
2736                 chip->waitfunc = nand_wait;
2737
2738         if (!chip->select_chip)
2739                 chip->select_chip = nand_select_chip;
2740         if (!chip->read_byte)
2741                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2742         if (!chip->read_word)
2743                 chip->read_word = nand_read_word;
2744         if (!chip->block_bad)
2745                 chip->block_bad = nand_block_bad;
2746         if (!chip->block_markbad)
2747                 chip->block_markbad = nand_default_block_markbad;
2748         if (!chip->write_buf)
2749                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2750         if (!chip->read_buf)
2751                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2752         if (!chip->verify_buf)
2753                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2754         if (!chip->scan_bbt)
2755                 chip->scan_bbt = nand_default_bbt;
2756
2757         if (!chip->controller) {
2758                 chip->controller = &chip->hwcontrol;
2759                 spin_lock_init(&chip->controller->lock);
2760                 init_waitqueue_head(&chip->controller->wq);
2761         }
2762
2763 }
2764
2765 /*
2766  * Get the flash and manufacturer id and lookup if the type is supported
2767  */
2768 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2769                                                   struct nand_chip *chip,
2770                                                   int busw, int *maf_id)
2771 {
2772         struct nand_flash_dev *type = NULL;
2773         int i, dev_id, maf_idx;
2774         int tmp_id, tmp_manf;
2775
2776         /* Select the device */
2777         chip->select_chip(mtd, 0);
2778
2779         /*
2780          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2781          * after power-up
2782          */
2783         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2784
2785         /* Send the command for reading device ID */
2786         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2787
2788         /* Read manufacturer and device IDs */
2789         *maf_id = chip->read_byte(mtd);
2790         dev_id = chip->read_byte(mtd);
2791
2792         /* Try again to make sure, as some systems the bus-hold or other
2793          * interface concerns can cause random data which looks like a
2794          * possibly credible NAND flash to appear. If the two results do
2795          * not match, ignore the device completely.
2796          */
2797
2798         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2799
2800         /* Read manufacturer and device IDs */
2801
2802         tmp_manf = chip->read_byte(mtd);
2803         tmp_id = chip->read_byte(mtd);
2804
2805         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2806                 printk(KERN_INFO "%s: second ID read did not match "
2807                        "%02x,%02x against %02x,%02x\n", __func__,
2808                        *maf_id, dev_id, tmp_manf, tmp_id);
2809                 return ERR_PTR(-ENODEV);
2810         }
2811
2812         /* Lookup the flash id */
2813         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2814                 if (dev_id == nand_flash_ids[i].id) {
2815                         type =  &nand_flash_ids[i];
2816                         break;
2817                 }
2818         }
2819
2820         if (!type)
2821                 return ERR_PTR(-ENODEV);
2822
2823         if (!mtd->name)
2824                 mtd->name = type->name;
2825
2826         chip->chipsize = (uint64_t)type->chipsize << 20;
2827
2828         /* Newer devices have all the information in additional id bytes */
2829         if (!type->pagesize) {
2830                 int extid;
2831                 /* The 3rd id byte holds MLC / multichip data */
2832                 chip->cellinfo = chip->read_byte(mtd);
2833                 /* The 4th id byte is the important one */
2834                 extid = chip->read_byte(mtd);
2835                 /* Calc pagesize */
2836                 mtd->writesize = 1024 << (extid & 0x3);
2837                 extid >>= 2;
2838                 /* Calc oobsize */
2839                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2840                 extid >>= 2;
2841                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2842                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2843                 extid >>= 2;
2844                 /* Get buswidth information */
2845                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2846
2847         } else {
2848                 /*
2849                  * Old devices have chip data hardcoded in the device id table
2850                  */
2851                 mtd->erasesize = type->erasesize;
2852                 mtd->writesize = type->pagesize;
2853                 mtd->oobsize = mtd->writesize / 32;
2854                 busw = type->options & NAND_BUSWIDTH_16;
2855         }
2856
2857         /* Try to identify manufacturer */
2858         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2859                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2860                         break;
2861         }
2862
2863         /*
2864          * Check, if buswidth is correct. Hardware drivers should set
2865          * chip correct !
2866          */
2867         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2868                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2869                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2870                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2871                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2872                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2873                        busw ? 16 : 8);
2874                 return ERR_PTR(-EINVAL);
2875         }
2876
2877         /* Calculate the address shift from the page size */
2878         chip->page_shift = ffs(mtd->writesize) - 1;
2879         /* Convert chipsize to number of pages per chip -1. */
2880         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2881
2882         chip->bbt_erase_shift = chip->phys_erase_shift =
2883                 ffs(mtd->erasesize) - 1;
2884         if (chip->chipsize & 0xffffffff)
2885                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2886         else
2887                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2888
2889         /* Set the bad block position */
2890         chip->badblockpos = mtd->writesize > 512 ?
2891                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2892
2893         /* Get chip options, preserve non chip based options */
2894         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2895         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2896
2897         /*
2898          * Set chip as a default. Board drivers can override it, if necessary
2899          */
2900         chip->options |= NAND_NO_AUTOINCR;
2901
2902         /* Check if chip is a not a samsung device. Do not clear the
2903          * options for chips which are not having an extended id.
2904          */
2905         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2906                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2907
2908         /* Check for AND chips with 4 page planes */
2909         if (chip->options & NAND_4PAGE_ARRAY)
2910                 chip->erase_cmd = multi_erase_cmd;
2911         else
2912                 chip->erase_cmd = single_erase_cmd;
2913
2914         /* Do not replace user supplied command function ! */
2915         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2916                 chip->cmdfunc = nand_command_lp;
2917
2918         printk(KERN_INFO "NAND device: Manufacturer ID:"
2919                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2920                nand_manuf_ids[maf_idx].name, type->name);
2921
2922         return type;
2923 }
2924
2925 /**
2926  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2927  * @mtd:             MTD device structure
2928  * @maxchips:        Number of chips to scan for
2929  *
2930  * This is the first phase of the normal nand_scan() function. It
2931  * reads the flash ID and sets up MTD fields accordingly.
2932  *
2933  * The mtd->owner field must be set to the module of the caller.
2934  */
2935 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2936 {
2937         int i, busw, nand_maf_id;
2938         struct nand_chip *chip = mtd->priv;
2939         struct nand_flash_dev *type;
2940
2941         /* Get buswidth to select the correct functions */
2942         busw = chip->options & NAND_BUSWIDTH_16;
2943         /* Set the default functions */
2944         nand_set_defaults(chip, busw);
2945
2946         /* Read the flash type */
2947         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2948
2949         if (IS_ERR(type)) {
2950                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
2951                         printk(KERN_WARNING "No NAND device found.\n");
2952                 chip->select_chip(mtd, -1);
2953                 return PTR_ERR(type);
2954         }
2955
2956         /* Check for a chip array */
2957         for (i = 1; i < maxchips; i++) {
2958                 chip->select_chip(mtd, i);
2959                 /* See comment in nand_get_flash_type for reset */
2960                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2961                 /* Send the command for reading device ID */
2962                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2963                 /* Read manufacturer and device IDs */
2964                 if (nand_maf_id != chip->read_byte(mtd) ||
2965                     type->id != chip->read_byte(mtd))
2966                         break;
2967         }
2968         if (i > 1)
2969                 printk(KERN_INFO "%d NAND chips detected\n", i);
2970
2971         /* Store the number of chips and calc total size for mtd */
2972         chip->numchips = i;
2973         mtd->size = i * chip->chipsize;
2974
2975         return 0;
2976 }
2977
2978
2979 /**
2980  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2981  * @mtd:            MTD device structure
2982  *
2983  * This is the second phase of the normal nand_scan() function. It
2984  * fills out all the uninitialized function pointers with the defaults
2985  * and scans for a bad block table if appropriate.
2986  */
2987 int nand_scan_tail(struct mtd_info *mtd)
2988 {
2989         int i;
2990         struct nand_chip *chip = mtd->priv;
2991
2992         if (!(chip->options & NAND_OWN_BUFFERS))
2993                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2994         if (!chip->buffers)
2995                 return -ENOMEM;
2996
2997         /* Set the internal oob buffer location, just after the page data */
2998         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2999
3000         /*
3001          * If no default placement scheme is given, select an appropriate one
3002          */
3003         if (!chip->ecc.layout) {
3004                 switch (mtd->oobsize) {
3005                 case 8:
3006                         chip->ecc.layout = &nand_oob_8;
3007                         break;
3008                 case 16:
3009                         chip->ecc.layout = &nand_oob_16;
3010                         break;
3011                 case 64:
3012                         chip->ecc.layout = &nand_oob_64;
3013                         break;
3014                 case 128:
3015                         chip->ecc.layout = &nand_oob_128;
3016                         break;
3017                 default:
3018                         printk(KERN_WARNING "No oob scheme defined for "
3019                                "oobsize %d\n", mtd->oobsize);
3020                         BUG();
3021                 }
3022         }
3023
3024         if (!chip->write_page)
3025                 chip->write_page = nand_write_page;
3026
3027         /*
3028          * check ECC mode, default to software if 3byte/512byte hardware ECC is
3029          * selected and we have 256 byte pagesize fallback to software ECC
3030          */
3031
3032         switch (chip->ecc.mode) {
3033         case NAND_ECC_HW_OOB_FIRST:
3034                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3035                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3036                      !chip->ecc.hwctl) {
3037                         printk(KERN_WARNING "No ECC functions supplied; "
3038                                "Hardware ECC not possible\n");
3039                         BUG();
3040                 }
3041                 if (!chip->ecc.read_page)
3042                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3043
3044         case NAND_ECC_HW:
3045                 /* Use standard hwecc read page function ? */
3046                 if (!chip->ecc.read_page)
3047                         chip->ecc.read_page = nand_read_page_hwecc;
3048                 if (!chip->ecc.write_page)
3049                         chip->ecc.write_page = nand_write_page_hwecc;
3050                 if (!chip->ecc.read_page_raw)
3051                         chip->ecc.read_page_raw = nand_read_page_raw;
3052                 if (!chip->ecc.write_page_raw)
3053                         chip->ecc.write_page_raw = nand_write_page_raw;
3054                 if (!chip->ecc.read_oob)
3055                         chip->ecc.read_oob = nand_read_oob_std;
3056                 if (!chip->ecc.write_oob)
3057                         chip->ecc.write_oob = nand_write_oob_std;
3058
3059         case NAND_ECC_HW_SYNDROME:
3060                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3061                      !chip->ecc.hwctl) &&
3062                     (!chip->ecc.read_page ||
3063                      chip->ecc.read_page == nand_read_page_hwecc ||
3064                      !chip->ecc.write_page ||
3065                      chip->ecc.write_page == nand_write_page_hwecc)) {
3066                         printk(KERN_WARNING "No ECC functions supplied; "
3067                                "Hardware ECC not possible\n");
3068                         BUG();
3069                 }
3070                 /* Use standard syndrome read/write page function ? */
3071                 if (!chip->ecc.read_page)
3072                         chip->ecc.read_page = nand_read_page_syndrome;
3073                 if (!chip->ecc.write_page)
3074                         chip->ecc.write_page = nand_write_page_syndrome;
3075                 if (!chip->ecc.read_page_raw)
3076                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3077                 if (!chip->ecc.write_page_raw)
3078                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3079                 if (!chip->ecc.read_oob)
3080                         chip->ecc.read_oob = nand_read_oob_syndrome;
3081                 if (!chip->ecc.write_oob)
3082                         chip->ecc.write_oob = nand_write_oob_syndrome;
3083
3084                 if (mtd->writesize >= chip->ecc.size)
3085                         break;
3086                 printk(KERN_WARNING "%d byte HW ECC not possible on "
3087                        "%d byte page size, fallback to SW ECC\n",
3088                        chip->ecc.size, mtd->writesize);
3089                 chip->ecc.mode = NAND_ECC_SOFT;
3090
3091         case NAND_ECC_SOFT:
3092                 chip->ecc.calculate = nand_calculate_ecc;
3093                 chip->ecc.correct = nand_correct_data;
3094                 chip->ecc.read_page = nand_read_page_swecc;
3095                 chip->ecc.read_subpage = nand_read_subpage;
3096                 chip->ecc.write_page = nand_write_page_swecc;
3097                 chip->ecc.read_page_raw = nand_read_page_raw;
3098                 chip->ecc.write_page_raw = nand_write_page_raw;
3099                 chip->ecc.read_oob = nand_read_oob_std;
3100                 chip->ecc.write_oob = nand_write_oob_std;
3101                 if (!chip->ecc.size)
3102                         chip->ecc.size = 256;
3103                 chip->ecc.bytes = 3;
3104                 break;
3105
3106         case NAND_ECC_NONE:
3107                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3108                        "This is not recommended !!\n");
3109                 chip->ecc.read_page = nand_read_page_raw;
3110                 chip->ecc.write_page = nand_write_page_raw;
3111                 chip->ecc.read_oob = nand_read_oob_std;
3112                 chip->ecc.read_page_raw = nand_read_page_raw;
3113                 chip->ecc.write_page_raw = nand_write_page_raw;
3114                 chip->ecc.write_oob = nand_write_oob_std;
3115                 chip->ecc.size = mtd->writesize;
3116                 chip->ecc.bytes = 0;
3117                 break;
3118
3119         default:
3120                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3121                        chip->ecc.mode);
3122                 BUG();
3123         }
3124
3125         /*
3126          * The number of bytes available for a client to place data into
3127          * the out of band area
3128          */
3129         chip->ecc.layout->oobavail = 0;
3130         for (i = 0; chip->ecc.layout->oobfree[i].length
3131                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3132                 chip->ecc.layout->oobavail +=
3133                         chip->ecc.layout->oobfree[i].length;
3134         mtd->oobavail = chip->ecc.layout->oobavail;
3135
3136         /*
3137          * Set the number of read / write steps for one page depending on ECC
3138          * mode
3139          */
3140         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3141         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3142                 printk(KERN_WARNING "Invalid ecc parameters\n");
3143                 BUG();
3144         }
3145         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3146
3147         /*
3148          * Allow subpage writes up to ecc.steps. Not possible for MLC
3149          * FLASH.
3150          */
3151         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3152             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3153                 switch(chip->ecc.steps) {
3154                 case 2:
3155                         mtd->subpage_sft = 1;
3156                         break;
3157                 case 4:
3158                 case 8:
3159                 case 16:
3160                         mtd->subpage_sft = 2;
3161                         break;
3162                 }
3163         }
3164         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3165
3166         /* Initialize state */
3167         chip->state = FL_READY;
3168
3169         /* De-select the device */
3170         chip->select_chip(mtd, -1);
3171
3172         /* Invalidate the pagebuffer reference */
3173         chip->pagebuf = -1;
3174
3175         /* Fill in remaining MTD driver data */
3176         mtd->type = MTD_NANDFLASH;
3177         mtd->flags = MTD_CAP_NANDFLASH;
3178         mtd->erase = nand_erase;
3179         mtd->point = NULL;
3180         mtd->unpoint = NULL;
3181         mtd->read = nand_read;
3182         mtd->write = nand_write;
3183         mtd->panic_write = panic_nand_write;
3184         mtd->read_oob = nand_read_oob;
3185         mtd->write_oob = nand_write_oob;
3186         mtd->sync = nand_sync;
3187         mtd->lock = NULL;
3188         mtd->unlock = NULL;
3189         mtd->suspend = nand_suspend;
3190         mtd->resume = nand_resume;
3191         mtd->block_isbad = nand_block_isbad;
3192         mtd->block_markbad = nand_block_markbad;
3193
3194         /* propagate ecc.layout to mtd_info */
3195         mtd->ecclayout = chip->ecc.layout;
3196
3197         /* Check, if we should skip the bad block table scan */
3198         if (chip->options & NAND_SKIP_BBTSCAN)
3199                 return 0;
3200
3201         /* Build bad block table */
3202         return chip->scan_bbt(mtd);
3203 }
3204
3205 /* is_module_text_address() isn't exported, and it's mostly a pointless
3206    test if this is a module _anyway_ -- they'd have to try _really_ hard
3207    to call us from in-kernel code if the core NAND support is modular. */
3208 #ifdef MODULE
3209 #define caller_is_module() (1)
3210 #else
3211 #define caller_is_module() \
3212         is_module_text_address((unsigned long)__builtin_return_address(0))
3213 #endif
3214
3215 /**
3216  * nand_scan - [NAND Interface] Scan for the NAND device
3217  * @mtd:        MTD device structure
3218  * @maxchips:   Number of chips to scan for
3219  *
3220  * This fills out all the uninitialized function pointers
3221  * with the defaults.
3222  * The flash ID is read and the mtd/chip structures are
3223  * filled with the appropriate values.
3224  * The mtd->owner field must be set to the module of the caller
3225  *
3226  */
3227 int nand_scan(struct mtd_info *mtd, int maxchips)
3228 {
3229         int ret;
3230
3231         /* Many callers got this wrong, so check for it for a while... */
3232         if (!mtd->owner && caller_is_module()) {
3233                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3234                                 __func__);
3235                 BUG();
3236         }
3237
3238         ret = nand_scan_ident(mtd, maxchips);
3239         if (!ret)
3240                 ret = nand_scan_tail(mtd);
3241         return ret;
3242 }
3243
3244 /**
3245  * nand_release - [NAND Interface] Free resources held by the NAND device
3246  * @mtd:        MTD device structure
3247 */
3248 void nand_release(struct mtd_info *mtd)
3249 {
3250         struct nand_chip *chip = mtd->priv;
3251
3252 #ifdef CONFIG_MTD_PARTITIONS
3253         /* Deregister partitions */
3254         del_mtd_partitions(mtd);
3255 #endif
3256         /* Deregister the device */
3257         del_mtd_device(mtd);
3258
3259         /* Free bad block table memory */
3260         kfree(chip->bbt);
3261         if (!(chip->options & NAND_OWN_BUFFERS))
3262                 kfree(chip->buffers);
3263 }
3264
3265 EXPORT_SYMBOL_GPL(nand_lock);
3266 EXPORT_SYMBOL_GPL(nand_unlock);
3267 EXPORT_SYMBOL_GPL(nand_scan);
3268 EXPORT_SYMBOL_GPL(nand_scan_ident);
3269 EXPORT_SYMBOL_GPL(nand_scan_tail);
3270 EXPORT_SYMBOL_GPL(nand_release);
3271
3272 static int __init nand_base_init(void)
3273 {
3274         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3275         return 0;
3276 }
3277
3278 static void __exit nand_base_exit(void)
3279 {
3280         led_trigger_unregister_simple(nand_led_trigger);
3281 }
3282
3283 module_init(nand_base_init);
3284 module_exit(nand_base_exit);
3285
3286 MODULE_LICENSE("GPL");
3287 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3288 MODULE_DESCRIPTION("Generic NAND flash driver code");