drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33
  34 #include <asm/mach/flash.h>
  35 #include <mach/mxc_nand.h>
  36
  37 #define DRIVER_NAME "mxc_nand"
  38
  39 /* Addresses for NFC registers */
  40 #define NFC_BUF_SIZE            0xE00
  41 #define NFC_BUF_ADDR            0xE04
  42 #define NFC_FLASH_ADDR          0xE06
  43 #define NFC_FLASH_CMD           0xE08
  44 #define NFC_CONFIG              0xE0A
  45 #define NFC_ECC_STATUS_RESULT   0xE0C
  46 #define NFC_RSLTMAIN_AREA       0xE0E
  47 #define NFC_RSLTSPARE_AREA      0xE10
  48 #define NFC_WRPROT              0xE12
  49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
  50 #define NFC_UNLOCKEND_BLKADDR   0xE16
  51 #define NFC_NF_WRPRST           0xE18
  52 #define NFC_CONFIG1             0xE1A
  53 #define NFC_CONFIG2             0xE1C
  54
  55 /* Addresses for NFC RAM BUFFER Main area 0 */
  56 #define MAIN_AREA0              0x000
  57 #define MAIN_AREA1              0x200
  58 #define MAIN_AREA2              0x400
  59 #define MAIN_AREA3              0x600
  60
  61 /* Addresses for NFC SPARE BUFFER Spare area 0 */
  62 #define SPARE_AREA0             0x800
  63 #define SPARE_AREA1             0x810
  64 #define SPARE_AREA2             0x820
  65 #define SPARE_AREA3             0x830
  66
  67 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
  68  * for Command operation */
  69 #define NFC_CMD            0x1
  70
  71 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
  72  * for Address operation */
  73 #define NFC_ADDR           0x2
  74
  75 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
  76  * for Input operation */
  77 #define NFC_INPUT          0x4
  78
  79 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
  80  * for Data Output operation */
  81 #define NFC_OUTPUT         0x8
  82
  83 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
  84  * for Read ID operation */
  85 #define NFC_ID             0x10
  86
  87 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
  88  * for Read Status operation */
  89 #define NFC_STATUS         0x20
  90
  91 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
  92  * Status operation */
  93 #define NFC_INT            0x8000
  94
  95 #define NFC_SP_EN           (1 << 2)
  96 #define NFC_ECC_EN          (1 << 3)
  97 #define NFC_INT_MSK         (1 << 4)
  98 #define NFC_BIG             (1 << 5)
  99 #define NFC_RST             (1 << 6)
 100 #define NFC_CE              (1 << 7)
 101 #define NFC_ONE_CYCLE       (1 << 8)
 102
 103 struct mxc_nand_host {
 104         struct mtd_info         mtd;
 105         struct nand_chip        nand;
 106         struct mtd_partition    *parts;
 107         struct device           *dev;
 108
 109         void __iomem            *regs;
 110         int                     spare_only;
 111         int                     status_request;
 112         int                     pagesize_2k;
 113         uint16_t                col_addr;
 114         struct clk              *clk;
 115         int                     clk_act;
 116         int                     irq;
 117
 118         wait_queue_head_t       irq_waitq;
 119 };
 120
 121 /* Define delays in microsec for NAND device operations */
 122 #define TROP_US_DELAY   2000
 123 /* Macros to get byte and bit positions of ECC */
 124 #define COLPOS(x)  ((x) >> 3)
 125 #define BITPOS(x) ((x) & 0xf)
 126
 127 /* Define single bit Error positions in Main & Spare area */
 128 #define MAIN_SINGLEBIT_ERROR 0x4
 129 #define SPARE_SINGLEBIT_ERROR 0x1
 130
 131 /* OOB placement block for use with hardware ecc generation */
 132 static struct nand_ecclayout nand_hw_eccoob_smallpage = {
 133         .eccbytes = 5,
 134         .eccpos = {6, 7, 8, 9, 10},
 135         .oobfree = {{0, 5}, {12, 4}, }
 136 };
 137
 138 static struct nand_ecclayout nand_hw_eccoob_largepage = {
 139         .eccbytes = 20,
 140         .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
 141                    38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
 142         .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
 143 };
 144
 145 #ifdef CONFIG_MTD_PARTITIONS
 146 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
 147 #endif
 148
 149 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 150 {
 151         struct mxc_nand_host *host = dev_id;
 152
 153         uint16_t tmp;
 154
 155         tmp = readw(host->regs + NFC_CONFIG1);
 156         tmp |= NFC_INT_MSK; /* Disable interrupt */
 157         writew(tmp, host->regs + NFC_CONFIG1);
 158
 159         wake_up(&host->irq_waitq);
 160
 161         return IRQ_HANDLED;
 162 }
 163
 164 /* This function polls the NANDFC to wait for the basic operation to
 165  * complete by checking the INT bit of config2 register.
 166  */
 167 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 168                                 uint16_t param, int useirq)
 169 {
 170         uint32_t tmp;
 171
 172         if (useirq) {
 173                 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
 174
 175                         tmp = readw(host->regs + NFC_CONFIG1);
 176                         tmp  &= ~NFC_INT_MSK;   /* Enable interrupt */
 177                         writew(tmp, host->regs + NFC_CONFIG1);
 178
 179                         wait_event(host->irq_waitq,
 180                                 readw(host->regs + NFC_CONFIG2) & NFC_INT);
 181
 182                         tmp = readw(host->regs + NFC_CONFIG2);
 183                         tmp  &= ~NFC_INT;
 184                         writew(tmp, host->regs + NFC_CONFIG2);
 185                 }
 186         } else {
 187                 while (max_retries-- > 0) {
 188                         if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
 189                                 tmp = readw(host->regs + NFC_CONFIG2);
 190                                 tmp  &= ~NFC_INT;
 191                                 writew(tmp, host->regs + NFC_CONFIG2);
 192                                 break;
 193                         }
 194                         udelay(1);
 195                 }
 196                 if (max_retries < 0)
 197                         DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
 198                               __func__, param);
 199         }
 200 }
 201
 202 /* This function issues the specified command to the NAND device and
 203  * waits for completion. */
 204 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 205 {
 206         DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 207
 208         writew(cmd, host->regs + NFC_FLASH_CMD);
 209         writew(NFC_CMD, host->regs + NFC_CONFIG2);
 210
 211         /* Wait for operation to complete */
 212         wait_op_done(host, TROP_US_DELAY, cmd, useirq);
 213 }
 214
 215 /* This function sends an address (or partial address) to the
 216  * NAND device. The address is used to select the source/destination for
 217  * a NAND command. */
 218 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
 219 {
 220         DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
 221
 222         writew(addr, host->regs + NFC_FLASH_ADDR);
 223         writew(NFC_ADDR, host->regs + NFC_CONFIG2);
 224
 225         /* Wait for operation to complete */
 226         wait_op_done(host, TROP_US_DELAY, addr, islast);
 227 }
 228
 229 /* This function requests the NANDFC to initate the transfer
 230  * of data currently in the NANDFC RAM buffer to the NAND device. */
 231 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 232                         int spare_only)
 233 {
 234         DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
 235
 236         /* NANDFC buffer 0 is used for page read/write */
 237         writew(buf_id, host->regs + NFC_BUF_ADDR);
 238
 239         /* Configure spare or page+spare access */
 240         if (!host->pagesize_2k) {
 241                 uint16_t config1 = readw(host->regs + NFC_CONFIG1);
 242                 if (spare_only)
 243                         config1 |= NFC_SP_EN;
 244                 else
 245                         config1 &= ~(NFC_SP_EN);
 246                 writew(config1, host->regs + NFC_CONFIG1);
 247         }
 248
 249         writew(NFC_INPUT, host->regs + NFC_CONFIG2);
 250
 251         /* Wait for operation to complete */
 252         wait_op_done(host, TROP_US_DELAY, spare_only, true);
 253 }
 254
 255 /* Requests NANDFC to initated the transfer of data from the
 256  * NAND device into in the NANDFC ram buffer. */
 257 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 258                 int spare_only)
 259 {
 260         DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
 261
 262         /* NANDFC buffer 0 is used for page read/write */
 263         writew(buf_id, host->regs + NFC_BUF_ADDR);
 264
 265         /* Configure spare or page+spare access */
 266         if (!host->pagesize_2k) {
 267                 uint32_t config1 = readw(host->regs + NFC_CONFIG1);
 268                 if (spare_only)
 269                         config1 |= NFC_SP_EN;
 270                 else
 271                         config1 &= ~NFC_SP_EN;
 272                 writew(config1, host->regs + NFC_CONFIG1);
 273         }
 274
 275         writew(NFC_OUTPUT, host->regs + NFC_CONFIG2);
 276
 277         /* Wait for operation to complete */
 278         wait_op_done(host, TROP_US_DELAY, spare_only, true);
 279 }
 280
 281 /* Request the NANDFC to perform a read of the NAND device ID. */
 282 static void send_read_id(struct mxc_nand_host *host)
 283 {
 284         struct nand_chip *this = &host->nand;
 285         uint16_t tmp;
 286
 287         /* NANDFC buffer 0 is used for device ID output */
 288         writew(0x0, host->regs + NFC_BUF_ADDR);
 289
 290         /* Read ID into main buffer */
 291         tmp = readw(host->regs + NFC_CONFIG1);
 292         tmp &= ~NFC_SP_EN;
 293         writew(tmp, host->regs + NFC_CONFIG1);
 294
 295         writew(NFC_ID, host->regs + NFC_CONFIG2);
 296
 297         /* Wait for operation to complete */
 298         wait_op_done(host, TROP_US_DELAY, 0, true);
 299
 300         if (this->options & NAND_BUSWIDTH_16) {
 301                 void __iomem *main_buf = host->regs + MAIN_AREA0;
 302                 /* compress the ID info */
 303                 writeb(readb(main_buf + 2), main_buf + 1);
 304                 writeb(readb(main_buf + 4), main_buf + 2);
 305                 writeb(readb(main_buf + 6), main_buf + 3);
 306                 writeb(readb(main_buf + 8), main_buf + 4);
 307                 writeb(readb(main_buf + 10), main_buf + 5);
 308         }
 309 }
 310
 311 /* This function requests the NANDFC to perform a read of the
 312  * NAND device status and returns the current status. */
 313 static uint16_t get_dev_status(struct mxc_nand_host *host)
 314 {
 315         void __iomem *main_buf = host->regs + MAIN_AREA1;
 316         uint32_t store;
 317         uint16_t ret, tmp;
 318         /* Issue status request to NAND device */
 319
 320         /* store the main area1 first word, later do recovery */
 321         store = readl(main_buf);
 322         /* NANDFC buffer 1 is used for device status to prevent
 323          * corruption of read/write buffer on status requests. */
 324         writew(1, host->regs + NFC_BUF_ADDR);
 325
 326         /* Read status into main buffer */
 327         tmp = readw(host->regs + NFC_CONFIG1);
 328         tmp &= ~NFC_SP_EN;
 329         writew(tmp, host->regs + NFC_CONFIG1);
 330
 331         writew(NFC_STATUS, host->regs + NFC_CONFIG2);
 332
 333         /* Wait for operation to complete */
 334         wait_op_done(host, TROP_US_DELAY, 0, true);
 335
 336         /* Status is placed in first word of main buffer */
 337         /* get status, then recovery area 1 data */
 338         ret = readw(main_buf);
 339         writel(store, main_buf);
 340
 341         return ret;
 342 }
 343
 344 /* This functions is used by upper layer to checks if device is ready */
 345 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 346 {
 347         /*
 348          * NFC handles R/B internally. Therefore, this function
 349          * always returns status as ready.
 350          */
 351         return 1;
 352 }
 353
 354 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 355 {
 356         /*
 357          * If HW ECC is enabled, we turn it on during init. There is
 358          * no need to enable again here.
 359          */
 360 }
 361
 362 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 363                                  u_char *read_ecc, u_char *calc_ecc)
 364 {
 365         struct nand_chip *nand_chip = mtd->priv;
 366         struct mxc_nand_host *host = nand_chip->priv;
 367
 368         /*
 369          * 1-Bit errors are automatically corrected in HW.  No need for
 370          * additional correction.  2-Bit errors cannot be corrected by
 371          * HW ECC, so we need to return failure
 372          */
 373         uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
 374
 375         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 376                 DEBUG(MTD_DEBUG_LEVEL0,
 377                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 378                 return -1;
 379         }
 380
 381         return 0;
 382 }
 383
 384 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 385                                   u_char *ecc_code)
 386 {
 387         return 0;
 388 }
 389
 390 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 391 {
 392         struct nand_chip *nand_chip = mtd->priv;
 393         struct mxc_nand_host *host = nand_chip->priv;
 394         uint8_t ret = 0;
 395         uint16_t col, rd_word;
 396         uint16_t __iomem *main_buf = host->regs + MAIN_AREA0;
 397         uint16_t __iomem *spare_buf = host->regs + SPARE_AREA0;
 398
 399         /* Check for status request */
 400         if (host->status_request)
 401                 return get_dev_status(host) & 0xFF;
 402
 403         /* Get column for 16-bit access */
 404         col = host->col_addr >> 1;
 405
 406         /* If we are accessing the spare region */
 407         if (host->spare_only)
 408                 rd_word = readw(&spare_buf[col]);
 409         else
 410                 rd_word = readw(&main_buf[col]);
 411
 412         /* Pick upper/lower byte of word from RAM buffer */
 413         if (host->col_addr & 0x1)
 414                 ret = (rd_word >> 8) & 0xFF;
 415         else
 416                 ret = rd_word & 0xFF;
 417
 418         /* Update saved column address */
 419         host->col_addr++;
 420
 421         return ret;
 422 }
 423
 424 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 425 {
 426         struct nand_chip *nand_chip = mtd->priv;
 427         struct mxc_nand_host *host = nand_chip->priv;
 428         uint16_t col, rd_word, ret;
 429         uint16_t __iomem *p;
 430
 431         DEBUG(MTD_DEBUG_LEVEL3,
 432               "mxc_nand_read_word(col = %d)\n", host->col_addr);
 433
 434         col = host->col_addr;
 435         /* Adjust saved column address */
 436         if (col < mtd->writesize && host->spare_only)
 437                 col += mtd->writesize;
 438
 439         if (col < mtd->writesize)
 440                 p = (host->regs + MAIN_AREA0) + (col >> 1);
 441         else
 442                 p = (host->regs + SPARE_AREA0) + ((col - mtd->writesize) >> 1);
 443
 444         if (col & 1) {
 445                 rd_word = readw(p);
 446                 ret = (rd_word >> 8) & 0xff;
 447                 rd_word = readw(&p[1]);
 448                 ret |= (rd_word << 8) & 0xff00;
 449
 450         } else
 451                 ret = readw(p);
 452
 453         /* Update saved column address */
 454         host->col_addr = col + 2;
 455
 456         return ret;
 457 }
 458
 459 /* Write data of length len to buffer buf. The data to be
 460  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 461  * Operation by the NFC, the data is written to NAND Flash */
 462 static void mxc_nand_write_buf(struct mtd_info *mtd,
 463                                 const u_char *buf, int len)
 464 {
 465         struct nand_chip *nand_chip = mtd->priv;
 466         struct mxc_nand_host *host = nand_chip->priv;
 467         int n, col, i = 0;
 468
 469         DEBUG(MTD_DEBUG_LEVEL3,
 470               "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 471               len);
 472
 473         col = host->col_addr;
 474
 475         /* Adjust saved column address */
 476         if (col < mtd->writesize && host->spare_only)
 477                 col += mtd->writesize;
 478
 479         n = mtd->writesize + mtd->oobsize - col;
 480         n = min(len, n);
 481
 482         DEBUG(MTD_DEBUG_LEVEL3,
 483               "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 484
 485         while (n) {
 486                 void __iomem *p;
 487
 488                 if (col < mtd->writesize)
 489                         p = host->regs + MAIN_AREA0 + (col & ~3);
 490                 else
 491                         p = host->regs + SPARE_AREA0 -
 492                                                 mtd->writesize + (col & ~3);
 493
 494                 DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
 495                       __LINE__, p);
 496
 497                 if (((col | (int)&buf[i]) & 3) || n < 16) {
 498                         uint32_t data = 0;
 499
 500                         if (col & 3 || n < 4)
 501                                 data = readl(p);
 502
 503                         switch (col & 3) {
 504                         case 0:
 505                                 if (n) {
 506                                         data = (data & 0xffffff00) |
 507                                             (buf[i++] << 0);
 508                                         n--;
 509                                         col++;
 510                                 }
 511                         case 1:
 512                                 if (n) {
 513                                         data = (data & 0xffff00ff) |
 514                                             (buf[i++] << 8);
 515                                         n--;
 516                                         col++;
 517                                 }
 518                         case 2:
 519                                 if (n) {
 520                                         data = (data & 0xff00ffff) |
 521                                             (buf[i++] << 16);
 522                                         n--;
 523                                         col++;
 524                                 }
 525                         case 3:
 526                                 if (n) {
 527                                         data = (data & 0x00ffffff) |
 528                                             (buf[i++] << 24);
 529                                         n--;
 530                                         col++;
 531                                 }
 532                         }
 533
 534                         writel(data, p);
 535                 } else {
 536                         int m = mtd->writesize - col;
 537
 538                         if (col >= mtd->writesize)
 539                                 m += mtd->oobsize;
 540
 541                         m = min(n, m) & ~3;
 542
 543                         DEBUG(MTD_DEBUG_LEVEL3,
 544                               "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 545                               __func__,  __LINE__, n, m, i, col);
 546
 547                         memcpy(p, &buf[i], m);
 548                         col += m;
 549                         i += m;
 550                         n -= m;
 551                 }
 552         }
 553         /* Update saved column address */
 554         host->col_addr = col;
 555 }
 556
 557 /* Read the data buffer from the NAND Flash. To read the data from NAND
 558  * Flash first the data output cycle is initiated by the NFC, which copies
 559  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 560  */
 561 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 562 {
 563         struct nand_chip *nand_chip = mtd->priv;
 564         struct mxc_nand_host *host = nand_chip->priv;
 565         int n, col, i = 0;
 566
 567         DEBUG(MTD_DEBUG_LEVEL3,
 568               "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
 569
 570         col = host->col_addr;
 571
 572         /* Adjust saved column address */
 573         if (col < mtd->writesize && host->spare_only)
 574                 col += mtd->writesize;
 575
 576         n = mtd->writesize + mtd->oobsize - col;
 577         n = min(len, n);
 578
 579         while (n) {
 580                 void __iomem *p;
 581
 582                 if (col < mtd->writesize)
 583                         p = host->regs + MAIN_AREA0 + (col & ~3);
 584                 else
 585                         p = host->regs + SPARE_AREA0 -
 586                                         mtd->writesize + (col & ~3);
 587
 588                 if (((col | (int)&buf[i]) & 3) || n < 16) {
 589                         uint32_t data;
 590
 591                         data = readl(p);
 592                         switch (col & 3) {
 593                         case 0:
 594                                 if (n) {
 595                                         buf[i++] = (uint8_t) (data);
 596                                         n--;
 597                                         col++;
 598                                 }
 599                         case 1:
 600                                 if (n) {
 601                                         buf[i++] = (uint8_t) (data >> 8);
 602                                         n--;
 603                                         col++;
 604                                 }
 605                         case 2:
 606                                 if (n) {
 607                                         buf[i++] = (uint8_t) (data >> 16);
 608                                         n--;
 609                                         col++;
 610                                 }
 611                         case 3:
 612                                 if (n) {
 613                                         buf[i++] = (uint8_t) (data >> 24);
 614                                         n--;
 615                                         col++;
 616                                 }
 617                         }
 618                 } else {
 619                         int m = mtd->writesize - col;
 620
 621                         if (col >= mtd->writesize)
 622                                 m += mtd->oobsize;
 623
 624                         m = min(n, m) & ~3;
 625                         memcpy(&buf[i], p, m);
 626                         col += m;
 627                         i += m;
 628                         n -= m;
 629                 }
 630         }
 631         /* Update saved column address */
 632         host->col_addr = col;
 633
 634 }
 635
 636 /* Used by the upper layer to verify the data in NAND Flash
 637  * with the data in the buf. */
 638 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 639                                 const u_char *buf, int len)
 640 {
 641         return -EFAULT;
 642 }
 643
 644 /* This function is used by upper layer for select and
 645  * deselect of the NAND chip */
 646 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 647 {
 648         struct nand_chip *nand_chip = mtd->priv;
 649         struct mxc_nand_host *host = nand_chip->priv;
 650
 651 #ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
 652         if (chip > 0) {
 653                 DEBUG(MTD_DEBUG_LEVEL0,
 654                       "ERROR:  Illegal chip select (chip = %d)\n", chip);
 655                 return;
 656         }
 657
 658         if (chip == -1) {
 659                 writew(readw(host->regs + NFC_CONFIG1) & ~NFC_CE,
 660                                 host->regs + NFC_CONFIG1);
 661                 return;
 662         }
 663
 664         writew(readw(host->regs + NFC_CONFIG1) | NFC_CE,
 665                         host->regs + NFC_CONFIG1);
 666 #endif
 667
 668         switch (chip) {
 669         case -1:
 670                 /* Disable the NFC clock */
 671                 if (host->clk_act) {
 672                         clk_disable(host->clk);
 673                         host->clk_act = 0;
 674                 }
 675                 break;
 676         case 0:
 677                 /* Enable the NFC clock */
 678                 if (!host->clk_act) {
 679                         clk_enable(host->clk);
 680                         host->clk_act = 1;
 681                 }
 682                 break;
 683
 684         default:
 685                 break;
 686         }
 687 }
 688
 689 /* Used by the upper layer to write command to NAND Flash for
 690  * different operations to be carried out on NAND Flash */
 691 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 692                                 int column, int page_addr)
 693 {
 694         struct nand_chip *nand_chip = mtd->priv;
 695         struct mxc_nand_host *host = nand_chip->priv;
 696         int useirq = true;
 697
 698         DEBUG(MTD_DEBUG_LEVEL3,
 699               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 700               command, column, page_addr);
 701
 702         /* Reset command state information */
 703         host->status_request = false;
 704
 705         /* Command pre-processing step */
 706         switch (command) {
 707
 708         case NAND_CMD_STATUS:
 709                 host->col_addr = 0;
 710                 host->status_request = true;
 711                 break;
 712
 713         case NAND_CMD_READ0:
 714                 host->col_addr = column;
 715                 host->spare_only = false;
 716                 useirq = false;
 717                 break;
 718
 719         case NAND_CMD_READOOB:
 720                 host->col_addr = column;
 721                 host->spare_only = true;
 722                 useirq = false;
 723                 if (host->pagesize_2k)
 724                         command = NAND_CMD_READ0; /* only READ0 is valid */
 725                 break;
 726
 727         case NAND_CMD_SEQIN:
 728                 if (column >= mtd->writesize) {
 729                         /*
 730                          * FIXME: before send SEQIN command for write OOB,
 731                          * We must read one page out.
 732                          * For K9F1GXX has no READ1 command to set current HW
 733                          * pointer to spare area, we must write the whole page
 734                          * including OOB together.
 735                          */
 736                         if (host->pagesize_2k)
 737                                 /* call ourself to read a page */
 738                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
 739                                                 page_addr);
 740
 741                         host->col_addr = column - mtd->writesize;
 742                         host->spare_only = true;
 743
 744                         /* Set program pointer to spare region */
 745                         if (!host->pagesize_2k)
 746                                 send_cmd(host, NAND_CMD_READOOB, false);
 747                 } else {
 748                         host->spare_only = false;
 749                         host->col_addr = column;
 750
 751                         /* Set program pointer to page start */
 752                         if (!host->pagesize_2k)
 753                                 send_cmd(host, NAND_CMD_READ0, false);
 754                 }
 755                 useirq = false;
 756                 break;
 757
 758         case NAND_CMD_PAGEPROG:
 759                 send_prog_page(host, 0, host->spare_only);
 760
 761                 if (host->pagesize_2k) {
 762                         /* data in 4 areas datas */
 763                         send_prog_page(host, 1, host->spare_only);
 764                         send_prog_page(host, 2, host->spare_only);
 765                         send_prog_page(host, 3, host->spare_only);
 766                 }
 767
 768                 break;
 769
 770         case NAND_CMD_ERASE1:
 771                 useirq = false;
 772                 break;
 773         }
 774
 775         /* Write out the command to the device. */
 776         send_cmd(host, command, useirq);
 777
 778         /* Write out column address, if necessary */
 779         if (column != -1) {
 780                 /*
 781                  * MXC NANDFC can only perform full page+spare or
 782                  * spare-only read/write.  When the upper layers
 783                  * layers perform a read/write buf operation,
 784                  * we will used the saved column adress to index into
 785                  * the full page.
 786                  */
 787                 send_addr(host, 0, page_addr == -1);
 788                 if (host->pagesize_2k)
 789                         /* another col addr cycle for 2k page */
 790                         send_addr(host, 0, false);
 791         }
 792
 793         /* Write out page address, if necessary */
 794         if (page_addr != -1) {
 795                 /* paddr_0 - p_addr_7 */
 796                 send_addr(host, (page_addr & 0xff), false);
 797
 798                 if (host->pagesize_2k) {
 799                         if (mtd->size >= 0x10000000) {
 800                                 /* paddr_8 - paddr_15 */
 801                                 send_addr(host, (page_addr >> 8) & 0xff, false);
 802                                 send_addr(host, (page_addr >> 16) & 0xff, true);
 803                         } else
 804                                 /* paddr_8 - paddr_15 */
 805                                 send_addr(host, (page_addr >> 8) & 0xff, true);
 806                 } else {
 807                         /* One more address cycle for higher density devices */
 808                         if (mtd->size >= 0x4000000) {
 809                                 /* paddr_8 - paddr_15 */
 810                                 send_addr(host, (page_addr >> 8) & 0xff, false);
 811                                 send_addr(host, (page_addr >> 16) & 0xff, true);
 812                         } else
 813                                 /* paddr_8 - paddr_15 */
 814                                 send_addr(host, (page_addr >> 8) & 0xff, true);
 815                 }
 816         }
 817
 818         /* Command post-processing step */
 819         switch (command) {
 820
 821         case NAND_CMD_RESET:
 822                 break;
 823
 824         case NAND_CMD_READOOB:
 825         case NAND_CMD_READ0:
 826                 if (host->pagesize_2k) {
 827                         /* send read confirm command */
 828                         send_cmd(host, NAND_CMD_READSTART, true);
 829                         /* read for each AREA */
 830                         send_read_page(host, 0, host->spare_only);
 831                         send_read_page(host, 1, host->spare_only);
 832                         send_read_page(host, 2, host->spare_only);
 833                         send_read_page(host, 3, host->spare_only);
 834                 } else
 835                         send_read_page(host, 0, host->spare_only);
 836                 break;
 837
 838         case NAND_CMD_READID:
 839                 host->col_addr = 0;
 840                 send_read_id(host);
 841                 break;
 842
 843         case NAND_CMD_PAGEPROG:
 844                 break;
 845
 846         case NAND_CMD_STATUS:
 847                 break;
 848
 849         case NAND_CMD_ERASE2:
 850                 break;
 851         }
 852 }
 853
 854 static int __init mxcnd_probe(struct platform_device *pdev)
 855 {
 856         struct nand_chip *this;
 857         struct mtd_info *mtd;
 858         struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
 859         struct mxc_nand_host *host;
 860         struct resource *res;
 861         uint16_t tmp;
 862         int err = 0, nr_parts = 0;
 863
 864         /* Allocate memory for MTD device structure and private data */
 865         host = kzalloc(sizeof(struct mxc_nand_host), GFP_KERNEL);
 866         if (!host)
 867                 return -ENOMEM;
 868
 869         host->dev = &pdev->dev;
 870         /* structures must be linked */
 871         this = &host->nand;
 872         mtd = &host->mtd;
 873         mtd->priv = this;
 874         mtd->owner = THIS_MODULE;
 875         mtd->dev.parent = &pdev->dev;
 876         mtd->name = "mxc_nand";
 877
 878         /* 50 us command delay time */
 879         this->chip_delay = 5;
 880
 881         this->priv = host;
 882         this->dev_ready = mxc_nand_dev_ready;
 883         this->cmdfunc = mxc_nand_command;
 884         this->select_chip = mxc_nand_select_chip;
 885         this->read_byte = mxc_nand_read_byte;
 886         this->read_word = mxc_nand_read_word;
 887         this->write_buf = mxc_nand_write_buf;
 888         this->read_buf = mxc_nand_read_buf;
 889         this->verify_buf = mxc_nand_verify_buf;
 890
 891         host->clk = clk_get(&pdev->dev, "nfc");
 892         if (IS_ERR(host->clk)) {
 893                 err = PTR_ERR(host->clk);
 894                 goto eclk;
 895         }
 896
 897         clk_enable(host->clk);
 898         host->clk_act = 1;
 899
 900         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 901         if (!res) {
 902                 err = -ENODEV;
 903                 goto eres;
 904         }
 905
 906         host->regs = ioremap(res->start, res->end - res->start + 1);
 907         if (!host->regs) {
 908                 err = -ENOMEM;
 909                 goto eres;
 910         }
 911
 912         tmp = readw(host->regs + NFC_CONFIG1);
 913         tmp |= NFC_INT_MSK;
 914         writew(tmp, host->regs + NFC_CONFIG1);
 915
 916         init_waitqueue_head(&host->irq_waitq);
 917
 918         host->irq = platform_get_irq(pdev, 0);
 919
 920         err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
 921         if (err)
 922                 goto eirq;
 923
 924         if (pdata->hw_ecc) {
 925                 this->ecc.calculate = mxc_nand_calculate_ecc;
 926                 this->ecc.hwctl = mxc_nand_enable_hwecc;
 927                 this->ecc.correct = mxc_nand_correct_data;
 928                 this->ecc.mode = NAND_ECC_HW;
 929                 this->ecc.size = 512;
 930                 this->ecc.bytes = 3;
 931                 tmp = readw(host->regs + NFC_CONFIG1);
 932                 tmp |= NFC_ECC_EN;
 933                 writew(tmp, host->regs + NFC_CONFIG1);
 934         } else {
 935                 this->ecc.size = 512;
 936                 this->ecc.bytes = 3;
 937                 this->ecc.layout = &nand_hw_eccoob_smallpage;
 938                 this->ecc.mode = NAND_ECC_SOFT;
 939                 tmp = readw(host->regs + NFC_CONFIG1);
 940                 tmp &= ~NFC_ECC_EN;
 941                 writew(tmp, host->regs + NFC_CONFIG1);
 942         }
 943
 944         /* Reset NAND */
 945         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 946
 947         /* preset operation */
 948         /* Unlock the internal RAM Buffer */
 949         writew(0x2, host->regs + NFC_CONFIG);
 950
 951         /* Blocks to be unlocked */
 952         writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
 953         writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
 954
 955         /* Unlock Block Command for given address range */
 956         writew(0x4, host->regs + NFC_WRPROT);
 957
 958         /* NAND bus width determines access funtions used by upper layer */
 959         if (pdata->width == 2) {
 960                 this->options |= NAND_BUSWIDTH_16;
 961                 this->ecc.layout = &nand_hw_eccoob_smallpage;
 962         }
 963
 964         /* first scan to find the device and get the page size */
 965         if (nand_scan_ident(mtd, 1)) {
 966                 err = -ENXIO;
 967                 goto escan;
 968         }
 969
 970         host->pagesize_2k = (mtd->writesize == 2048) ? 1 : 0;
 971
 972         if (this->ecc.mode == NAND_ECC_HW) {
 973                 switch (mtd->oobsize) {
 974                 case 8:
 975                         this->ecc.layout = &nand_hw_eccoob_smallpage;
 976                         break;
 977                 case 16:
 978                         this->ecc.layout = &nand_hw_eccoob_smallpage;
 979                         break;
 980                 case 64:
 981                         this->ecc.layout = &nand_hw_eccoob_largepage;
 982                         break;
 983                 default:
 984                         /* page size not handled by HW ECC */
 985                         /* switching back to soft ECC */
 986                         this->ecc.size = 512;
 987                         this->ecc.bytes = 3;
 988                         this->ecc.layout = &nand_hw_eccoob_smallpage;
 989                         this->ecc.mode = NAND_ECC_SOFT;
 990                         this->ecc.calculate = NULL;
 991                         this->ecc.correct = NULL;
 992                         this->ecc.hwctl = NULL;
 993                         tmp = readw(host->regs + NFC_CONFIG1);
 994                         tmp &= ~NFC_ECC_EN;
 995                         writew(tmp, host->regs + NFC_CONFIG1);
 996                         break;
 997                 }
 998         }
 999
1000         /* second phase scan */
1001         if (nand_scan_tail(mtd)) {
1002                 err = -ENXIO;
1003                 goto escan;
1004         }
1005
1006         /* Register the partitions */
1007 #ifdef CONFIG_MTD_PARTITIONS
1008         nr_parts =
1009             parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
1010         if (nr_parts > 0)
1011                 add_mtd_partitions(mtd, host->parts, nr_parts);
1012         else
1013 #endif
1014         {
1015                 pr_info("Registering %s as whole device\n", mtd->name);
1016                 add_mtd_device(mtd);
1017         }
1018
1019         platform_set_drvdata(pdev, host);
1020
1021         return 0;
1022
1023 escan:
1024         free_irq(host->irq, host);
1025 eirq:
1026         iounmap(host->regs);
1027 eres:
1028         clk_put(host->clk);
1029 eclk:
1030         kfree(host);
1031
1032         return err;
1033 }
1034
1035 static int __exit mxcnd_remove(struct platform_device *pdev)
1036 {
1037         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1038
1039         clk_put(host->clk);
1040
1041         platform_set_drvdata(pdev, NULL);
1042
1043         nand_release(&host->mtd);
1044         free_irq(host->irq, host);
1045         iounmap(host->regs);
1046         kfree(host);
1047
1048         return 0;
1049 }
1050
1051 #ifdef CONFIG_PM
1052 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
1053 {
1054         struct mtd_info *mtd = platform_get_drvdata(pdev);
1055         struct nand_chip *nand_chip = mtd->priv;
1056         struct mxc_nand_host *host = nand_chip->priv;
1057         int ret = 0;
1058
1059         DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
1060         if (mtd) {
1061                 ret = mtd->suspend(mtd);
1062                 /* Disable the NFC clock */
1063                 clk_disable(host->clk);
1064         }
1065
1066         return ret;
1067 }
1068
1069 static int mxcnd_resume(struct platform_device *pdev)
1070 {
1071         struct mtd_info *mtd = platform_get_drvdata(pdev);
1072         struct nand_chip *nand_chip = mtd->priv;
1073         struct mxc_nand_host *host = nand_chip->priv;
1074         int ret = 0;
1075
1076         DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
1077
1078         if (mtd) {
1079                 /* Enable the NFC clock */
1080                 clk_enable(host->clk);
1081                 mtd->resume(mtd);
1082         }
1083
1084         return ret;
1085 }
1086
1087 #else
1088 # define mxcnd_suspend   NULL
1089 # define mxcnd_resume    NULL
1090 #endif                          /* CONFIG_PM */
1091
1092 static struct platform_driver mxcnd_driver = {
1093         .driver = {
1094                    .name = DRIVER_NAME,
1095                    },
1096         .remove = __exit_p(mxcnd_remove),
1097         .suspend = mxcnd_suspend,
1098         .resume = mxcnd_resume,
1099 };
1100
1101 static int __init mxc_nd_init(void)
1102 {
1103         return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1104 }
1105
1106 static void __exit mxc_nd_cleanup(void)
1107 {
1108         /* Unregister the device structure */
1109         platform_driver_unregister(&mxcnd_driver);
1110 }
1111
1112 module_init(mxc_nd_init);
1113 module_exit(mxc_nd_cleanup);
1114
1115 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1116 MODULE_DESCRIPTION("MXC NAND MTD driver");
1117 MODULE_LICENSE("GPL");