2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
38 #define DRIVER_NAME "mxc_nand"
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
43 /* Addresses for NFC registers */
44 #define NFC_BUF_SIZE 0x00
45 #define NFC_BUF_ADDR 0x04
46 #define NFC_FLASH_ADDR 0x06
47 #define NFC_FLASH_CMD 0x08
48 #define NFC_CONFIG 0x0a
49 #define NFC_ECC_STATUS_RESULT 0x0c
50 #define NFC_RSLTMAIN_AREA 0x0e
51 #define NFC_RSLTSPARE_AREA 0x10
52 #define NFC_WRPROT 0x12
53 #define NFC_V1_UNLOCKSTART_BLKADDR 0x14
54 #define NFC_V1_UNLOCKEND_BLKADDR 0x16
55 #define NFC_V21_UNLOCKSTART_BLKADDR 0x20
56 #define NFC_V21_UNLOCKEND_BLKADDR 0x22
57 #define NFC_NF_WRPRST 0x18
58 #define NFC_CONFIG1 0x1a
59 #define NFC_CONFIG2 0x1c
61 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
62 * for Command operation */
65 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
66 * for Address operation */
69 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
70 * for Input operation */
73 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
74 * for Data Output operation */
75 #define NFC_OUTPUT 0x8
77 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
78 * for Read ID operation */
81 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
82 * for Read Status operation */
83 #define NFC_STATUS 0x20
85 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
87 #define NFC_INT 0x8000
89 #define NFC_SP_EN (1 << 2)
90 #define NFC_ECC_EN (1 << 3)
91 #define NFC_INT_MSK (1 << 4)
92 #define NFC_BIG (1 << 5)
93 #define NFC_RST (1 << 6)
94 #define NFC_CE (1 << 7)
95 #define NFC_ONE_CYCLE (1 << 8)
97 struct mxc_nand_host {
99 struct nand_chip nand;
100 struct mtd_partition *parts;
113 wait_queue_head_t irq_waitq;
116 unsigned int buf_start;
119 void (*preset)(struct mtd_info *);
120 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
121 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
122 void (*send_page)(struct mtd_info *, unsigned int);
123 void (*send_read_id)(struct mxc_nand_host *);
124 uint16_t (*get_dev_status)(struct mxc_nand_host *);
127 /* OOB placement block for use with hardware ecc generation */
128 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
130 .eccpos = {6, 7, 8, 9, 10},
131 .oobfree = {{0, 5}, {12, 4}, }
134 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
136 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
137 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
138 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
141 /* OOB description for 512 byte pages with 16 byte OOB */
142 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
145 7, 8, 9, 10, 11, 12, 13, 14, 15
148 {.offset = 0, .length = 5}
152 /* OOB description for 2048 byte pages with 64 byte OOB */
153 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
156 7, 8, 9, 10, 11, 12, 13, 14, 15,
157 23, 24, 25, 26, 27, 28, 29, 30, 31,
158 39, 40, 41, 42, 43, 44, 45, 46, 47,
159 55, 56, 57, 58, 59, 60, 61, 62, 63
162 {.offset = 2, .length = 4},
163 {.offset = 16, .length = 7},
164 {.offset = 32, .length = 7},
165 {.offset = 48, .length = 7}
169 #ifdef CONFIG_MTD_PARTITIONS
170 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
173 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
175 struct mxc_nand_host *host = dev_id;
177 disable_irq_nosync(irq);
179 wake_up(&host->irq_waitq);
184 /* This function polls the NANDFC to wait for the basic operation to
185 * complete by checking the INT bit of config2 register.
187 static void wait_op_done(struct mxc_nand_host *host, int useirq)
190 int max_retries = 8000;
193 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
195 enable_irq(host->irq);
197 wait_event(host->irq_waitq,
198 readw(host->regs + NFC_CONFIG2) & NFC_INT);
200 tmp = readw(host->regs + NFC_CONFIG2);
202 writew(tmp, host->regs + NFC_CONFIG2);
205 while (max_retries-- > 0) {
206 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
207 tmp = readw(host->regs + NFC_CONFIG2);
209 writew(tmp, host->regs + NFC_CONFIG2);
215 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
220 /* This function issues the specified command to the NAND device and
221 * waits for completion. */
222 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
224 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
226 writew(cmd, host->regs + NFC_FLASH_CMD);
227 writew(NFC_CMD, host->regs + NFC_CONFIG2);
229 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
230 int max_retries = 100;
231 /* Reset completion is indicated by NFC_CONFIG2 */
233 while (max_retries-- > 0) {
234 if (readw(host->regs + NFC_CONFIG2) == 0) {
240 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
243 /* Wait for operation to complete */
244 wait_op_done(host, useirq);
248 /* This function sends an address (or partial address) to the
249 * NAND device. The address is used to select the source/destination for
251 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
253 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
255 writew(addr, host->regs + NFC_FLASH_ADDR);
256 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
258 /* Wait for operation to complete */
259 wait_op_done(host, islast);
262 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
264 struct nand_chip *nand_chip = mtd->priv;
265 struct mxc_nand_host *host = nand_chip->priv;
268 if (nfc_is_v1() && mtd->writesize > 512)
273 for (i = 0; i < bufs; i++) {
275 /* NANDFC buffer 0 is used for page read/write */
276 writew(i, host->regs + NFC_BUF_ADDR);
278 writew(ops, host->regs + NFC_CONFIG2);
280 /* Wait for operation to complete */
281 wait_op_done(host, true);
285 /* Request the NANDFC to perform a read of the NAND device ID. */
286 static void send_read_id_v1_v2(struct mxc_nand_host *host)
288 struct nand_chip *this = &host->nand;
290 /* NANDFC buffer 0 is used for device ID output */
291 writew(0x0, host->regs + NFC_BUF_ADDR);
293 writew(NFC_ID, host->regs + NFC_CONFIG2);
295 /* Wait for operation to complete */
296 wait_op_done(host, true);
298 if (this->options & NAND_BUSWIDTH_16) {
299 void __iomem *main_buf = host->main_area0;
300 /* compress the ID info */
301 writeb(readb(main_buf + 2), main_buf + 1);
302 writeb(readb(main_buf + 4), main_buf + 2);
303 writeb(readb(main_buf + 6), main_buf + 3);
304 writeb(readb(main_buf + 8), main_buf + 4);
305 writeb(readb(main_buf + 10), main_buf + 5);
307 memcpy(host->data_buf, host->main_area0, 16);
310 /* This function requests the NANDFC to perform a read of the
311 * NAND device status and returns the current status. */
312 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
314 void __iomem *main_buf = host->main_area0;
318 writew(0x0, NFC_V1_V2_BUF_ADDR);
321 * The device status is stored in main_area0. To
322 * prevent corruption of the buffer save the value
323 * and restore it afterwards.
325 store = readl(main_buf);
327 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
328 wait_op_done(host, true);
330 ret = readw(main_buf);
332 writel(store, main_buf);
337 /* This functions is used by upper layer to checks if device is ready */
338 static int mxc_nand_dev_ready(struct mtd_info *mtd)
341 * NFC handles R/B internally. Therefore, this function
342 * always returns status as ready.
347 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
350 * If HW ECC is enabled, we turn it on during init. There is
351 * no need to enable again here.
355 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
356 u_char *read_ecc, u_char *calc_ecc)
358 struct nand_chip *nand_chip = mtd->priv;
359 struct mxc_nand_host *host = nand_chip->priv;
362 * 1-Bit errors are automatically corrected in HW. No need for
363 * additional correction. 2-Bit errors cannot be corrected by
364 * HW ECC, so we need to return failure
366 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
368 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
369 DEBUG(MTD_DEBUG_LEVEL0,
370 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
377 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
383 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
385 struct nand_chip *nand_chip = mtd->priv;
386 struct mxc_nand_host *host = nand_chip->priv;
389 /* Check for status request */
390 if (host->status_request)
391 return host->get_dev_status(host) & 0xFF;
393 ret = *(uint8_t *)(host->data_buf + host->buf_start);
399 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
401 struct nand_chip *nand_chip = mtd->priv;
402 struct mxc_nand_host *host = nand_chip->priv;
405 ret = *(uint16_t *)(host->data_buf + host->buf_start);
406 host->buf_start += 2;
411 /* Write data of length len to buffer buf. The data to be
412 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
413 * Operation by the NFC, the data is written to NAND Flash */
414 static void mxc_nand_write_buf(struct mtd_info *mtd,
415 const u_char *buf, int len)
417 struct nand_chip *nand_chip = mtd->priv;
418 struct mxc_nand_host *host = nand_chip->priv;
419 u16 col = host->buf_start;
420 int n = mtd->oobsize + mtd->writesize - col;
424 memcpy(host->data_buf + col, buf, n);
426 host->buf_start += n;
429 /* Read the data buffer from the NAND Flash. To read the data from NAND
430 * Flash first the data output cycle is initiated by the NFC, which copies
431 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
433 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
435 struct nand_chip *nand_chip = mtd->priv;
436 struct mxc_nand_host *host = nand_chip->priv;
437 u16 col = host->buf_start;
438 int n = mtd->oobsize + mtd->writesize - col;
442 memcpy(buf, host->data_buf + col, len);
444 host->buf_start += len;
447 /* Used by the upper layer to verify the data in NAND Flash
448 * with the data in the buf. */
449 static int mxc_nand_verify_buf(struct mtd_info *mtd,
450 const u_char *buf, int len)
455 /* This function is used by upper layer for select and
456 * deselect of the NAND chip */
457 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
459 struct nand_chip *nand_chip = mtd->priv;
460 struct mxc_nand_host *host = nand_chip->priv;
464 /* Disable the NFC clock */
466 clk_disable(host->clk);
471 /* Enable the NFC clock */
472 if (!host->clk_act) {
473 clk_enable(host->clk);
484 * Function to transfer data to/from spare area.
486 static void copy_spare(struct mtd_info *mtd, bool bfrom)
488 struct nand_chip *this = mtd->priv;
489 struct mxc_nand_host *host = this->priv;
491 u16 n = mtd->writesize >> 9;
492 u8 *d = host->data_buf + mtd->writesize;
493 u8 *s = host->spare0;
494 u16 t = host->spare_len;
496 j = (mtd->oobsize / n >> 1) << 1;
499 for (i = 0; i < n - 1; i++)
500 memcpy(d + i * j, s + i * t, j);
502 /* the last section */
503 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
505 for (i = 0; i < n - 1; i++)
506 memcpy(&s[i * t], &d[i * j], j);
508 /* the last section */
509 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
513 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
515 struct nand_chip *nand_chip = mtd->priv;
516 struct mxc_nand_host *host = nand_chip->priv;
518 /* Write out column address, if necessary */
521 * MXC NANDFC can only perform full page+spare or
522 * spare-only read/write. When the upper layers
523 * layers perform a read/write buf operation,
524 * we will used the saved column address to index into
527 host->send_addr(host, 0, page_addr == -1);
528 if (mtd->writesize > 512)
529 /* another col addr cycle for 2k page */
530 host->send_addr(host, 0, false);
533 /* Write out page address, if necessary */
534 if (page_addr != -1) {
535 /* paddr_0 - p_addr_7 */
536 host->send_addr(host, (page_addr & 0xff), false);
538 if (mtd->writesize > 512) {
539 if (mtd->size >= 0x10000000) {
540 /* paddr_8 - paddr_15 */
541 host->send_addr(host, (page_addr >> 8) & 0xff, false);
542 host->send_addr(host, (page_addr >> 16) & 0xff, true);
544 /* paddr_8 - paddr_15 */
545 host->send_addr(host, (page_addr >> 8) & 0xff, true);
547 /* One more address cycle for higher density devices */
548 if (mtd->size >= 0x4000000) {
549 /* paddr_8 - paddr_15 */
550 host->send_addr(host, (page_addr >> 8) & 0xff, false);
551 host->send_addr(host, (page_addr >> 16) & 0xff, true);
553 /* paddr_8 - paddr_15 */
554 host->send_addr(host, (page_addr >> 8) & 0xff, true);
559 static void preset_v1_v2(struct mtd_info *mtd)
561 struct nand_chip *nand_chip = mtd->priv;
562 struct mxc_nand_host *host = nand_chip->priv;
565 /* enable interrupt, disable spare enable */
566 tmp = readw(host->regs + NFC_CONFIG1);
569 if (nand_chip->ecc.mode == NAND_ECC_HW) {
574 writew(tmp, host->regs + NFC_CONFIG1);
575 /* preset operation */
577 /* Unlock the internal RAM Buffer */
578 writew(0x2, host->regs + NFC_CONFIG);
580 /* Blocks to be unlocked */
582 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
583 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
584 } else if (nfc_is_v1()) {
585 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
586 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
590 /* Unlock Block Command for given address range */
591 writew(0x4, host->regs + NFC_WRPROT);
594 /* Used by the upper layer to write command to NAND Flash for
595 * different operations to be carried out on NAND Flash */
596 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
597 int column, int page_addr)
599 struct nand_chip *nand_chip = mtd->priv;
600 struct mxc_nand_host *host = nand_chip->priv;
602 DEBUG(MTD_DEBUG_LEVEL3,
603 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
604 command, column, page_addr);
606 /* Reset command state information */
607 host->status_request = false;
609 /* Command pre-processing step */
613 host->send_cmd(host, command, false);
616 case NAND_CMD_STATUS:
618 host->status_request = true;
620 host->send_cmd(host, command, true);
621 mxc_do_addr_cycle(mtd, column, page_addr);
625 case NAND_CMD_READOOB:
626 if (command == NAND_CMD_READ0)
627 host->buf_start = column;
629 host->buf_start = column + mtd->writesize;
631 command = NAND_CMD_READ0; /* only READ0 is valid */
633 host->send_cmd(host, command, false);
634 mxc_do_addr_cycle(mtd, column, page_addr);
636 if (mtd->writesize > 512)
637 host->send_cmd(host, NAND_CMD_READSTART, true);
639 host->send_page(mtd, NFC_OUTPUT);
641 memcpy(host->data_buf, host->main_area0, mtd->writesize);
642 copy_spare(mtd, true);
646 if (column >= mtd->writesize)
647 /* call ourself to read a page */
648 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
650 host->buf_start = column;
652 host->send_cmd(host, command, false);
653 mxc_do_addr_cycle(mtd, column, page_addr);
656 case NAND_CMD_PAGEPROG:
657 memcpy(host->main_area0, host->data_buf, mtd->writesize);
658 copy_spare(mtd, false);
659 host->send_page(mtd, NFC_INPUT);
660 host->send_cmd(host, command, true);
661 mxc_do_addr_cycle(mtd, column, page_addr);
664 case NAND_CMD_READID:
665 host->send_cmd(host, command, true);
666 mxc_do_addr_cycle(mtd, column, page_addr);
667 host->send_read_id(host);
668 host->buf_start = column;
671 case NAND_CMD_ERASE1:
672 case NAND_CMD_ERASE2:
673 host->send_cmd(host, command, false);
674 mxc_do_addr_cycle(mtd, column, page_addr);
681 * The generic flash bbt decriptors overlap with our ecc
682 * hardware, so define some i.MX specific ones.
684 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
685 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
687 static struct nand_bbt_descr bbt_main_descr = {
688 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
689 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
694 .pattern = bbt_pattern,
697 static struct nand_bbt_descr bbt_mirror_descr = {
698 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
699 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
704 .pattern = mirror_pattern,
707 static int __init mxcnd_probe(struct platform_device *pdev)
709 struct nand_chip *this;
710 struct mtd_info *mtd;
711 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
712 struct mxc_nand_host *host;
713 struct resource *res;
714 int err = 0, nr_parts = 0;
715 struct nand_ecclayout *oob_smallpage, *oob_largepage;
717 /* Allocate memory for MTD device structure and private data */
718 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
719 NAND_MAX_OOBSIZE, GFP_KERNEL);
723 host->data_buf = (uint8_t *)(host + 1);
725 host->dev = &pdev->dev;
726 /* structures must be linked */
730 mtd->owner = THIS_MODULE;
731 mtd->dev.parent = &pdev->dev;
732 mtd->name = DRIVER_NAME;
734 /* 50 us command delay time */
735 this->chip_delay = 5;
738 this->dev_ready = mxc_nand_dev_ready;
739 this->cmdfunc = mxc_nand_command;
740 this->select_chip = mxc_nand_select_chip;
741 this->read_byte = mxc_nand_read_byte;
742 this->read_word = mxc_nand_read_word;
743 this->write_buf = mxc_nand_write_buf;
744 this->read_buf = mxc_nand_read_buf;
745 this->verify_buf = mxc_nand_verify_buf;
747 host->clk = clk_get(&pdev->dev, "nfc");
748 if (IS_ERR(host->clk)) {
749 err = PTR_ERR(host->clk);
753 clk_enable(host->clk);
756 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
762 host->base = ioremap(res->start, resource_size(res));
768 host->main_area0 = host->base;
770 if (nfc_is_v1() || nfc_is_v21()) {
771 host->preset = preset_v1_v2;
772 host->send_cmd = send_cmd_v1_v2;
773 host->send_addr = send_addr_v1_v2;
774 host->send_page = send_page_v1_v2;
775 host->send_read_id = send_read_id_v1_v2;
776 host->get_dev_status = get_dev_status_v1_v2;
780 host->regs = host->base + 0x1e00;
781 host->spare0 = host->base + 0x1000;
782 host->spare_len = 64;
783 oob_smallpage = &nandv2_hw_eccoob_smallpage;
784 oob_largepage = &nandv2_hw_eccoob_largepage;
786 } else if (nfc_is_v1()) {
787 host->regs = host->base + 0xe00;
788 host->spare0 = host->base + 0x800;
789 host->spare_len = 16;
790 oob_smallpage = &nandv1_hw_eccoob_smallpage;
791 oob_largepage = &nandv1_hw_eccoob_largepage;
796 this->ecc.size = 512;
797 this->ecc.layout = oob_smallpage;
800 this->ecc.calculate = mxc_nand_calculate_ecc;
801 this->ecc.hwctl = mxc_nand_enable_hwecc;
802 this->ecc.correct = mxc_nand_correct_data;
803 this->ecc.mode = NAND_ECC_HW;
805 this->ecc.mode = NAND_ECC_SOFT;
808 /* NAND bus width determines access funtions used by upper layer */
809 if (pdata->width == 2)
810 this->options |= NAND_BUSWIDTH_16;
812 if (pdata->flash_bbt) {
813 this->bbt_td = &bbt_main_descr;
814 this->bbt_md = &bbt_mirror_descr;
815 /* update flash based bbt */
816 this->options |= NAND_USE_FLASH_BBT;
819 init_waitqueue_head(&host->irq_waitq);
821 host->irq = platform_get_irq(pdev, 0);
823 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
827 /* first scan to find the device and get the page size */
828 if (nand_scan_ident(mtd, 1, NULL)) {
833 if (mtd->writesize == 2048)
834 this->ecc.layout = oob_largepage;
836 /* second phase scan */
837 if (nand_scan_tail(mtd)) {
842 /* Register the partitions */
843 #ifdef CONFIG_MTD_PARTITIONS
845 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
847 add_mtd_partitions(mtd, host->parts, nr_parts);
851 pr_info("Registering %s as whole device\n", mtd->name);
855 platform_set_drvdata(pdev, host);
860 free_irq(host->irq, host);
871 static int __devexit mxcnd_remove(struct platform_device *pdev)
873 struct mxc_nand_host *host = platform_get_drvdata(pdev);
877 platform_set_drvdata(pdev, NULL);
879 nand_release(&host->mtd);
880 free_irq(host->irq, host);
887 static struct platform_driver mxcnd_driver = {
891 .remove = __devexit_p(mxcnd_remove),
894 static int __init mxc_nd_init(void)
896 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
899 static void __exit mxc_nd_cleanup(void)
901 /* Unregister the device structure */
902 platform_driver_unregister(&mxcnd_driver);
905 module_init(mxc_nd_init);
906 module_exit(mxc_nd_cleanup);
908 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
909 MODULE_DESCRIPTION("MXC NAND MTD driver");
910 MODULE_LICENSE("GPL");