2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
38 #define DRIVER_NAME "mxc_nand"
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
43 /* Addresses for NFC registers */
44 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
45 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
46 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
47 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
48 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
49 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
50 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
51 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
52 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
53 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
54 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
55 #define NFC_V21_UNLOCKSTART_BLKADDR (host->regs + 0x20)
56 #define NFC_V21_UNLOCKEND_BLKADDR (host->regs + 0x22)
57 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
58 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
59 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
61 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
62 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
63 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
64 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
65 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
66 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
67 #define NFC_V1_V2_CONFIG1_ONE_CYCLE (1 << 8)
69 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
72 * Operation modes for the NFC. Valid for v1, v2 and v3
75 #define NFC_CMD (1 << 0)
76 #define NFC_ADDR (1 << 1)
77 #define NFC_INPUT (1 << 2)
78 #define NFC_OUTPUT (1 << 3)
79 #define NFC_ID (1 << 4)
80 #define NFC_STATUS (1 << 5)
82 struct mxc_nand_host {
84 struct nand_chip nand;
85 struct mtd_partition *parts;
98 wait_queue_head_t irq_waitq;
101 unsigned int buf_start;
104 void (*preset)(struct mtd_info *);
105 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
106 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
107 void (*send_page)(struct mtd_info *, unsigned int);
108 void (*send_read_id)(struct mxc_nand_host *);
109 uint16_t (*get_dev_status)(struct mxc_nand_host *);
110 int (*check_int)(struct mxc_nand_host *);
113 /* OOB placement block for use with hardware ecc generation */
114 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
116 .eccpos = {6, 7, 8, 9, 10},
117 .oobfree = {{0, 5}, {12, 4}, }
120 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
122 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
123 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
124 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
127 /* OOB description for 512 byte pages with 16 byte OOB */
128 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
131 7, 8, 9, 10, 11, 12, 13, 14, 15
134 {.offset = 0, .length = 5}
138 /* OOB description for 2048 byte pages with 64 byte OOB */
139 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
142 7, 8, 9, 10, 11, 12, 13, 14, 15,
143 23, 24, 25, 26, 27, 28, 29, 30, 31,
144 39, 40, 41, 42, 43, 44, 45, 46, 47,
145 55, 56, 57, 58, 59, 60, 61, 62, 63
148 {.offset = 2, .length = 4},
149 {.offset = 16, .length = 7},
150 {.offset = 32, .length = 7},
151 {.offset = 48, .length = 7}
155 #ifdef CONFIG_MTD_PARTITIONS
156 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
159 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
161 struct mxc_nand_host *host = dev_id;
163 disable_irq_nosync(irq);
165 wake_up(&host->irq_waitq);
170 static int check_int_v1_v2(struct mxc_nand_host *host)
174 tmp = readw(NFC_V1_V2_CONFIG2);
175 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
178 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
183 /* This function polls the NANDFC to wait for the basic operation to
184 * complete by checking the INT bit of config2 register.
186 static void wait_op_done(struct mxc_nand_host *host, int useirq)
188 int max_retries = 8000;
191 if (!host->check_int(host)) {
193 enable_irq(host->irq);
195 wait_event(host->irq_waitq, host->check_int(host));
198 while (max_retries-- > 0) {
199 if (host->check_int(host))
205 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
210 /* This function issues the specified command to the NAND device and
211 * waits for completion. */
212 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
214 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
216 writew(cmd, NFC_V1_V2_FLASH_CMD);
217 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
219 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
220 int max_retries = 100;
221 /* Reset completion is indicated by NFC_CONFIG2 */
223 while (max_retries-- > 0) {
224 if (readw(NFC_V1_V2_CONFIG2) == 0) {
230 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
233 /* Wait for operation to complete */
234 wait_op_done(host, useirq);
238 /* This function sends an address (or partial address) to the
239 * NAND device. The address is used to select the source/destination for
241 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
243 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
245 writew(addr, NFC_V1_V2_FLASH_ADDR);
246 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
248 /* Wait for operation to complete */
249 wait_op_done(host, islast);
252 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
254 struct nand_chip *nand_chip = mtd->priv;
255 struct mxc_nand_host *host = nand_chip->priv;
258 if (nfc_is_v1() && mtd->writesize > 512)
263 for (i = 0; i < bufs; i++) {
265 /* NANDFC buffer 0 is used for page read/write */
266 writew(i, NFC_V1_V2_BUF_ADDR);
268 writew(ops, NFC_V1_V2_CONFIG2);
270 /* Wait for operation to complete */
271 wait_op_done(host, true);
275 /* Request the NANDFC to perform a read of the NAND device ID. */
276 static void send_read_id_v1_v2(struct mxc_nand_host *host)
278 struct nand_chip *this = &host->nand;
280 /* NANDFC buffer 0 is used for device ID output */
281 writew(0x0, NFC_V1_V2_BUF_ADDR);
283 writew(NFC_ID, NFC_V1_V2_CONFIG2);
285 /* Wait for operation to complete */
286 wait_op_done(host, true);
288 if (this->options & NAND_BUSWIDTH_16) {
289 void __iomem *main_buf = host->main_area0;
290 /* compress the ID info */
291 writeb(readb(main_buf + 2), main_buf + 1);
292 writeb(readb(main_buf + 4), main_buf + 2);
293 writeb(readb(main_buf + 6), main_buf + 3);
294 writeb(readb(main_buf + 8), main_buf + 4);
295 writeb(readb(main_buf + 10), main_buf + 5);
297 memcpy(host->data_buf, host->main_area0, 16);
300 /* This function requests the NANDFC to perform a read of the
301 * NAND device status and returns the current status. */
302 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
304 void __iomem *main_buf = host->main_area0;
308 writew(0x0, NFC_V1_V2_BUF_ADDR);
311 * The device status is stored in main_area0. To
312 * prevent corruption of the buffer save the value
313 * and restore it afterwards.
315 store = readl(main_buf);
317 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
318 wait_op_done(host, true);
320 ret = readw(main_buf);
322 writel(store, main_buf);
327 /* This functions is used by upper layer to checks if device is ready */
328 static int mxc_nand_dev_ready(struct mtd_info *mtd)
331 * NFC handles R/B internally. Therefore, this function
332 * always returns status as ready.
337 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
340 * If HW ECC is enabled, we turn it on during init. There is
341 * no need to enable again here.
345 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
346 u_char *read_ecc, u_char *calc_ecc)
348 struct nand_chip *nand_chip = mtd->priv;
349 struct mxc_nand_host *host = nand_chip->priv;
352 * 1-Bit errors are automatically corrected in HW. No need for
353 * additional correction. 2-Bit errors cannot be corrected by
354 * HW ECC, so we need to return failure
356 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
358 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
359 DEBUG(MTD_DEBUG_LEVEL0,
360 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
367 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
373 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
375 struct nand_chip *nand_chip = mtd->priv;
376 struct mxc_nand_host *host = nand_chip->priv;
379 /* Check for status request */
380 if (host->status_request)
381 return host->get_dev_status(host) & 0xFF;
383 ret = *(uint8_t *)(host->data_buf + host->buf_start);
389 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
391 struct nand_chip *nand_chip = mtd->priv;
392 struct mxc_nand_host *host = nand_chip->priv;
395 ret = *(uint16_t *)(host->data_buf + host->buf_start);
396 host->buf_start += 2;
401 /* Write data of length len to buffer buf. The data to be
402 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
403 * Operation by the NFC, the data is written to NAND Flash */
404 static void mxc_nand_write_buf(struct mtd_info *mtd,
405 const u_char *buf, int len)
407 struct nand_chip *nand_chip = mtd->priv;
408 struct mxc_nand_host *host = nand_chip->priv;
409 u16 col = host->buf_start;
410 int n = mtd->oobsize + mtd->writesize - col;
414 memcpy(host->data_buf + col, buf, n);
416 host->buf_start += n;
419 /* Read the data buffer from the NAND Flash. To read the data from NAND
420 * Flash first the data output cycle is initiated by the NFC, which copies
421 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
423 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
425 struct nand_chip *nand_chip = mtd->priv;
426 struct mxc_nand_host *host = nand_chip->priv;
427 u16 col = host->buf_start;
428 int n = mtd->oobsize + mtd->writesize - col;
432 memcpy(buf, host->data_buf + col, len);
434 host->buf_start += len;
437 /* Used by the upper layer to verify the data in NAND Flash
438 * with the data in the buf. */
439 static int mxc_nand_verify_buf(struct mtd_info *mtd,
440 const u_char *buf, int len)
445 /* This function is used by upper layer for select and
446 * deselect of the NAND chip */
447 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
449 struct nand_chip *nand_chip = mtd->priv;
450 struct mxc_nand_host *host = nand_chip->priv;
454 /* Disable the NFC clock */
456 clk_disable(host->clk);
461 /* Enable the NFC clock */
462 if (!host->clk_act) {
463 clk_enable(host->clk);
474 * Function to transfer data to/from spare area.
476 static void copy_spare(struct mtd_info *mtd, bool bfrom)
478 struct nand_chip *this = mtd->priv;
479 struct mxc_nand_host *host = this->priv;
481 u16 n = mtd->writesize >> 9;
482 u8 *d = host->data_buf + mtd->writesize;
483 u8 *s = host->spare0;
484 u16 t = host->spare_len;
486 j = (mtd->oobsize / n >> 1) << 1;
489 for (i = 0; i < n - 1; i++)
490 memcpy(d + i * j, s + i * t, j);
492 /* the last section */
493 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
495 for (i = 0; i < n - 1; i++)
496 memcpy(&s[i * t], &d[i * j], j);
498 /* the last section */
499 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
503 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
505 struct nand_chip *nand_chip = mtd->priv;
506 struct mxc_nand_host *host = nand_chip->priv;
508 /* Write out column address, if necessary */
511 * MXC NANDFC can only perform full page+spare or
512 * spare-only read/write. When the upper layers
513 * layers perform a read/write buf operation,
514 * we will used the saved column address to index into
517 host->send_addr(host, 0, page_addr == -1);
518 if (mtd->writesize > 512)
519 /* another col addr cycle for 2k page */
520 host->send_addr(host, 0, false);
523 /* Write out page address, if necessary */
524 if (page_addr != -1) {
525 /* paddr_0 - p_addr_7 */
526 host->send_addr(host, (page_addr & 0xff), false);
528 if (mtd->writesize > 512) {
529 if (mtd->size >= 0x10000000) {
530 /* paddr_8 - paddr_15 */
531 host->send_addr(host, (page_addr >> 8) & 0xff, false);
532 host->send_addr(host, (page_addr >> 16) & 0xff, true);
534 /* paddr_8 - paddr_15 */
535 host->send_addr(host, (page_addr >> 8) & 0xff, true);
537 /* One more address cycle for higher density devices */
538 if (mtd->size >= 0x4000000) {
539 /* paddr_8 - paddr_15 */
540 host->send_addr(host, (page_addr >> 8) & 0xff, false);
541 host->send_addr(host, (page_addr >> 16) & 0xff, true);
543 /* paddr_8 - paddr_15 */
544 host->send_addr(host, (page_addr >> 8) & 0xff, true);
549 static void preset_v1_v2(struct mtd_info *mtd)
551 struct nand_chip *nand_chip = mtd->priv;
552 struct mxc_nand_host *host = nand_chip->priv;
555 /* enable interrupt, disable spare enable */
556 tmp = readw(NFC_V1_V2_CONFIG1);
557 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
558 tmp &= ~NFC_V1_V2_CONFIG1_SP_EN;
559 if (nand_chip->ecc.mode == NAND_ECC_HW) {
560 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
562 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
564 writew(tmp, NFC_V1_V2_CONFIG1);
565 /* preset operation */
567 /* Unlock the internal RAM Buffer */
568 writew(0x2, NFC_V1_V2_CONFIG);
570 /* Blocks to be unlocked */
572 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR);
573 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR);
574 } else if (nfc_is_v1()) {
575 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
576 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
580 /* Unlock Block Command for given address range */
581 writew(0x4, NFC_V1_V2_WRPROT);
584 /* Used by the upper layer to write command to NAND Flash for
585 * different operations to be carried out on NAND Flash */
586 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
587 int column, int page_addr)
589 struct nand_chip *nand_chip = mtd->priv;
590 struct mxc_nand_host *host = nand_chip->priv;
592 DEBUG(MTD_DEBUG_LEVEL3,
593 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
594 command, column, page_addr);
596 /* Reset command state information */
597 host->status_request = false;
599 /* Command pre-processing step */
603 host->send_cmd(host, command, false);
606 case NAND_CMD_STATUS:
608 host->status_request = true;
610 host->send_cmd(host, command, true);
611 mxc_do_addr_cycle(mtd, column, page_addr);
615 case NAND_CMD_READOOB:
616 if (command == NAND_CMD_READ0)
617 host->buf_start = column;
619 host->buf_start = column + mtd->writesize;
621 command = NAND_CMD_READ0; /* only READ0 is valid */
623 host->send_cmd(host, command, false);
624 mxc_do_addr_cycle(mtd, column, page_addr);
626 if (mtd->writesize > 512)
627 host->send_cmd(host, NAND_CMD_READSTART, true);
629 host->send_page(mtd, NFC_OUTPUT);
631 memcpy(host->data_buf, host->main_area0, mtd->writesize);
632 copy_spare(mtd, true);
636 if (column >= mtd->writesize)
637 /* call ourself to read a page */
638 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
640 host->buf_start = column;
642 host->send_cmd(host, command, false);
643 mxc_do_addr_cycle(mtd, column, page_addr);
646 case NAND_CMD_PAGEPROG:
647 memcpy(host->main_area0, host->data_buf, mtd->writesize);
648 copy_spare(mtd, false);
649 host->send_page(mtd, NFC_INPUT);
650 host->send_cmd(host, command, true);
651 mxc_do_addr_cycle(mtd, column, page_addr);
654 case NAND_CMD_READID:
655 host->send_cmd(host, command, true);
656 mxc_do_addr_cycle(mtd, column, page_addr);
657 host->send_read_id(host);
658 host->buf_start = column;
661 case NAND_CMD_ERASE1:
662 case NAND_CMD_ERASE2:
663 host->send_cmd(host, command, false);
664 mxc_do_addr_cycle(mtd, column, page_addr);
671 * The generic flash bbt decriptors overlap with our ecc
672 * hardware, so define some i.MX specific ones.
674 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
675 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
677 static struct nand_bbt_descr bbt_main_descr = {
678 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
679 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
684 .pattern = bbt_pattern,
687 static struct nand_bbt_descr bbt_mirror_descr = {
688 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
689 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
694 .pattern = mirror_pattern,
697 static int __init mxcnd_probe(struct platform_device *pdev)
699 struct nand_chip *this;
700 struct mtd_info *mtd;
701 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
702 struct mxc_nand_host *host;
703 struct resource *res;
704 int err = 0, nr_parts = 0;
705 struct nand_ecclayout *oob_smallpage, *oob_largepage;
707 /* Allocate memory for MTD device structure and private data */
708 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
709 NAND_MAX_OOBSIZE, GFP_KERNEL);
713 host->data_buf = (uint8_t *)(host + 1);
715 host->dev = &pdev->dev;
716 /* structures must be linked */
720 mtd->owner = THIS_MODULE;
721 mtd->dev.parent = &pdev->dev;
722 mtd->name = DRIVER_NAME;
724 /* 50 us command delay time */
725 this->chip_delay = 5;
728 this->dev_ready = mxc_nand_dev_ready;
729 this->cmdfunc = mxc_nand_command;
730 this->select_chip = mxc_nand_select_chip;
731 this->read_byte = mxc_nand_read_byte;
732 this->read_word = mxc_nand_read_word;
733 this->write_buf = mxc_nand_write_buf;
734 this->read_buf = mxc_nand_read_buf;
735 this->verify_buf = mxc_nand_verify_buf;
737 host->clk = clk_get(&pdev->dev, "nfc");
738 if (IS_ERR(host->clk)) {
739 err = PTR_ERR(host->clk);
743 clk_enable(host->clk);
746 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
752 host->base = ioremap(res->start, resource_size(res));
758 host->main_area0 = host->base;
760 if (nfc_is_v1() || nfc_is_v21()) {
761 host->preset = preset_v1_v2;
762 host->send_cmd = send_cmd_v1_v2;
763 host->send_addr = send_addr_v1_v2;
764 host->send_page = send_page_v1_v2;
765 host->send_read_id = send_read_id_v1_v2;
766 host->get_dev_status = get_dev_status_v1_v2;
767 host->check_int = check_int_v1_v2;
771 host->regs = host->base + 0x1e00;
772 host->spare0 = host->base + 0x1000;
773 host->spare_len = 64;
774 oob_smallpage = &nandv2_hw_eccoob_smallpage;
775 oob_largepage = &nandv2_hw_eccoob_largepage;
777 } else if (nfc_is_v1()) {
778 host->regs = host->base + 0xe00;
779 host->spare0 = host->base + 0x800;
780 host->spare_len = 16;
781 oob_smallpage = &nandv1_hw_eccoob_smallpage;
782 oob_largepage = &nandv1_hw_eccoob_largepage;
787 this->ecc.size = 512;
788 this->ecc.layout = oob_smallpage;
791 this->ecc.calculate = mxc_nand_calculate_ecc;
792 this->ecc.hwctl = mxc_nand_enable_hwecc;
793 this->ecc.correct = mxc_nand_correct_data;
794 this->ecc.mode = NAND_ECC_HW;
796 this->ecc.mode = NAND_ECC_SOFT;
799 /* NAND bus width determines access funtions used by upper layer */
800 if (pdata->width == 2)
801 this->options |= NAND_BUSWIDTH_16;
803 if (pdata->flash_bbt) {
804 this->bbt_td = &bbt_main_descr;
805 this->bbt_md = &bbt_mirror_descr;
806 /* update flash based bbt */
807 this->options |= NAND_USE_FLASH_BBT;
810 init_waitqueue_head(&host->irq_waitq);
812 host->irq = platform_get_irq(pdev, 0);
814 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
818 /* first scan to find the device and get the page size */
819 if (nand_scan_ident(mtd, 1, NULL)) {
824 if (mtd->writesize == 2048)
825 this->ecc.layout = oob_largepage;
827 /* second phase scan */
828 if (nand_scan_tail(mtd)) {
833 /* Register the partitions */
834 #ifdef CONFIG_MTD_PARTITIONS
836 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
838 add_mtd_partitions(mtd, host->parts, nr_parts);
842 pr_info("Registering %s as whole device\n", mtd->name);
846 platform_set_drvdata(pdev, host);
851 free_irq(host->irq, host);
862 static int __devexit mxcnd_remove(struct platform_device *pdev)
864 struct mxc_nand_host *host = platform_get_drvdata(pdev);
868 platform_set_drvdata(pdev, NULL);
870 nand_release(&host->mtd);
871 free_irq(host->irq, host);
878 static struct platform_driver mxcnd_driver = {
882 .remove = __devexit_p(mxcnd_remove),
885 static int __init mxc_nd_init(void)
887 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
890 static void __exit mxc_nd_cleanup(void)
892 /* Unregister the device structure */
893 platform_driver_unregister(&mxcnd_driver);
896 module_init(mxc_nd_init);
897 module_exit(mxc_nd_cleanup);
899 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
900 MODULE_DESCRIPTION("MXC NAND MTD driver");
901 MODULE_LICENSE("GPL");