drivers/mtd/nand/bf5xx_nand.c

   1 /* linux/drivers/mtd/nand/bf5xx_nand.c
   2  *
   3  * Copyright 2006-2008 Analog Devices Inc.
   4  *      http://blackfin.uclinux.org/
   5  *      Bryan Wu <bryan.wu@analog.com>
   6  *
   7  * Blackfin BF5xx on-chip NAND flash controller driver
   8  *
   9  * Derived from drivers/mtd/nand/s3c2410.c
  10  * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
  11  *
  12  * Derived from drivers/mtd/nand/cafe.c
  13  * Copyright © 2006 Red Hat, Inc.
  14  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
  15  *
  16  * Changelog:
  17  *      12-Jun-2007  Bryan Wu:  Initial version
  18  *      18-Jul-2007  Bryan Wu:
  19  *              - ECC_HW and ECC_SW supported
  20  *              - DMA supported in ECC_HW
  21  *              - YAFFS tested as rootfs in both ECC_HW and ECC_SW
  22  *
  23  * This program is free software; you can redistribute it and/or modify
  24  * it under the terms of the GNU General Public License as published by
  25  * the Free Software Foundation; either version 2 of the License, or
  26  * (at your option) any later version.
  27  *
  28  * This program is distributed in the hope that it will be useful,
  29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31  * GNU General Public License for more details.
  32  *
  33  * You should have received a copy of the GNU General Public License
  34  * along with this program; if not, write to the Free Software
  35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  36 */
  37
  38 #include <linux/module.h>
  39 #include <linux/types.h>
  40 #include <linux/init.h>
  41 #include <linux/kernel.h>
  42 #include <linux/string.h>
  43 #include <linux/ioport.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/delay.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/err.h>
  48 #include <linux/slab.h>
  49 #include <linux/io.h>
  50 #include <linux/bitops.h>
  51
  52 #include <linux/mtd/mtd.h>
  53 #include <linux/mtd/nand.h>
  54 #include <linux/mtd/nand_ecc.h>
  55 #include <linux/mtd/partitions.h>
  56
  57 #include <asm/blackfin.h>
  58 #include <asm/dma.h>
  59 #include <asm/cacheflush.h>
  60 #include <asm/nand.h>
  61 #include <asm/portmux.h>
  62
  63 #define DRV_NAME        "bf5xx-nand"
  64 #define DRV_VERSION     "1.2"
  65 #define DRV_AUTHOR      "Bryan Wu <bryan.wu@analog.com>"
  66 #define DRV_DESC        "BF5xx on-chip NAND FLash Controller Driver"
  67
  68 /* NFC_STAT Masks */
  69 #define NBUSY       0x01  /* Not Busy */
  70 #define WB_FULL     0x02  /* Write Buffer Full */
  71 #define PG_WR_STAT  0x04  /* Page Write Pending */
  72 #define PG_RD_STAT  0x08  /* Page Read Pending */
  73 #define WB_EMPTY    0x10  /* Write Buffer Empty */
  74
  75 /* NFC_IRQSTAT Masks */
  76 #define NBUSYIRQ    0x01  /* Not Busy IRQ */
  77 #define WB_OVF      0x02  /* Write Buffer Overflow */
  78 #define WB_EDGE     0x04  /* Write Buffer Edge Detect */
  79 #define RD_RDY      0x08  /* Read Data Ready */
  80 #define WR_DONE     0x10  /* Page Write Done */
  81
  82 /* NFC_RST Masks */
  83 #define ECC_RST     0x01  /* ECC (and NFC counters) Reset */
  84
  85 /* NFC_PGCTL Masks */
  86 #define PG_RD_START 0x01  /* Page Read Start */
  87 #define PG_WR_START 0x02  /* Page Write Start */
  88
  89 #ifdef CONFIG_MTD_NAND_BF5XX_HWECC
  90 static int hardware_ecc = 1;
  91 #else
  92 static int hardware_ecc;
  93 #endif
  94
  95 static const unsigned short bfin_nfc_pin_req[] =
  96         {P_NAND_CE,
  97          P_NAND_RB,
  98          P_NAND_D0,
  99          P_NAND_D1,
 100          P_NAND_D2,
 101          P_NAND_D3,
 102          P_NAND_D4,
 103          P_NAND_D5,
 104          P_NAND_D6,
 105          P_NAND_D7,
 106          P_NAND_WE,
 107          P_NAND_RE,
 108          P_NAND_CLE,
 109          P_NAND_ALE,
 110          0};
 111
 112 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 113 static uint8_t bbt_pattern[] = { 0xff };
 114
 115 static struct nand_bbt_descr bootrom_bbt = {
 116         .options = 0,
 117         .offs = 63,
 118         .len = 1,
 119         .pattern = bbt_pattern,
 120 };
 121
 122 static struct nand_ecclayout bootrom_ecclayout = {
 123         .eccbytes = 24,
 124         .eccpos = {
 125                 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
 126                 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
 127                 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
 128                 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
 129                 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
 130                 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
 131                 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
 132                 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
 133         },
 134         .oobfree = {
 135                 { 0x8 * 0 + 3, 5 },
 136                 { 0x8 * 1 + 3, 5 },
 137                 { 0x8 * 2 + 3, 5 },
 138                 { 0x8 * 3 + 3, 5 },
 139                 { 0x8 * 4 + 3, 5 },
 140                 { 0x8 * 5 + 3, 5 },
 141                 { 0x8 * 6 + 3, 5 },
 142                 { 0x8 * 7 + 3, 5 },
 143         }
 144 };
 145 #endif
 146
 147 /*
 148  * Data structures for bf5xx nand flash controller driver
 149  */
 150
 151 /* bf5xx nand info */
 152 struct bf5xx_nand_info {
 153         /* mtd info */
 154         struct nand_hw_control          controller;
 155         struct mtd_info                 mtd;
 156         struct nand_chip                chip;
 157
 158         /* platform info */
 159         struct bf5xx_nand_platform      *platform;
 160
 161         /* device info */
 162         struct device                   *device;
 163
 164         /* DMA stuff */
 165         struct completion               dma_completion;
 166 };
 167
 168 /*
 169  * Conversion functions
 170  */
 171 static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
 172 {
 173         return container_of(mtd, struct bf5xx_nand_info, mtd);
 174 }
 175
 176 static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
 177 {
 178         return platform_get_drvdata(pdev);
 179 }
 180
 181 static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
 182 {
 183         return pdev->dev.platform_data;
 184 }
 185
 186 /*
 187  * struct nand_chip interface function pointers
 188  */
 189
 190 /*
 191  * bf5xx_nand_hwcontrol
 192  *
 193  * Issue command and address cycles to the chip
 194  */
 195 static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 196                                    unsigned int ctrl)
 197 {
 198         if (cmd == NAND_CMD_NONE)
 199                 return;
 200
 201         while (bfin_read_NFC_STAT() & WB_FULL)
 202                 cpu_relax();
 203
 204         if (ctrl & NAND_CLE)
 205                 bfin_write_NFC_CMD(cmd);
 206         else if (ctrl & NAND_ALE)
 207                 bfin_write_NFC_ADDR(cmd);
 208         SSYNC();
 209 }
 210
 211 /*
 212  * bf5xx_nand_devready()
 213  *
 214  * returns 0 if the nand is busy, 1 if it is ready
 215  */
 216 static int bf5xx_nand_devready(struct mtd_info *mtd)
 217 {
 218         unsigned short val = bfin_read_NFC_IRQSTAT();
 219
 220         if ((val & NBUSYIRQ) == NBUSYIRQ)
 221                 return 1;
 222         else
 223                 return 0;
 224 }
 225
 226 /*
 227  * ECC functions
 228  * These allow the bf5xx to use the controller's ECC
 229  * generator block to ECC the data as it passes through
 230  */
 231
 232 /*
 233  * ECC error correction function
 234  */
 235 static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
 236                                         u_char *read_ecc, u_char *calc_ecc)
 237 {
 238         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 239         u32 syndrome[5];
 240         u32 calced, stored;
 241         int i;
 242         unsigned short failing_bit, failing_byte;
 243         u_char data;
 244
 245         calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
 246         stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
 247
 248         syndrome[0] = (calced ^ stored);
 249
 250         /*
 251          * syndrome 0: all zero
 252          * No error in data
 253          * No action
 254          */
 255         if (!syndrome[0] || !calced || !stored)
 256                 return 0;
 257
 258         /*
 259          * sysdrome 0: only one bit is one
 260          * ECC data was incorrect
 261          * No action
 262          */
 263         if (hweight32(syndrome[0]) == 1) {
 264                 dev_err(info->device, "ECC data was incorrect!\n");
 265                 return 1;
 266         }
 267
 268         syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
 269         syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
 270         syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
 271         syndrome[4] = syndrome[2] ^ syndrome[3];
 272
 273         for (i = 0; i < 5; i++)
 274                 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
 275
 276         dev_info(info->device,
 277                 "calced[0x%08x], stored[0x%08x]\n",
 278                 calced, stored);
 279
 280         /*
 281          * sysdrome 0: exactly 11 bits are one, each parity
 282          * and parity' pair is 1 & 0 or 0 & 1.
 283          * 1-bit correctable error
 284          * Correct the error
 285          */
 286         if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
 287                 dev_info(info->device,
 288                         "1-bit correctable error, correct it.\n");
 289                 dev_info(info->device,
 290                         "syndrome[1] 0x%08x\n", syndrome[1]);
 291
 292                 failing_bit = syndrome[1] & 0x7;
 293                 failing_byte = syndrome[1] >> 0x3;
 294                 data = *(dat + failing_byte);
 295                 data = data ^ (0x1 << failing_bit);
 296                 *(dat + failing_byte) = data;
 297
 298                 return 0;
 299         }
 300
 301         /*
 302          * sysdrome 0: random data
 303          * More than 1-bit error, non-correctable error
 304          * Discard data, mark bad block
 305          */
 306         dev_err(info->device,
 307                 "More than 1-bit error, non-correctable error.\n");
 308         dev_err(info->device,
 309                 "Please discard data, mark bad block\n");
 310
 311         return 1;
 312 }
 313
 314 static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 315                                         u_char *read_ecc, u_char *calc_ecc)
 316 {
 317         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 318         struct bf5xx_nand_platform *plat = info->platform;
 319         unsigned short page_size = (plat->page_size ? 512 : 256);
 320         int ret;
 321
 322         ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 323
 324         /* If page size is 512, correct second 256 bytes */
 325         if (page_size == 512) {
 326                 dat += 256;
 327                 read_ecc += 8;
 328                 calc_ecc += 8;
 329                 ret |= bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 330         }
 331
 332         return ret;
 333 }
 334
 335 static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 336 {
 337         return;
 338 }
 339
 340 static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
 341                 const u_char *dat, u_char *ecc_code)
 342 {
 343         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 344         struct bf5xx_nand_platform *plat = info->platform;
 345         u16 page_size = (plat->page_size ? 512 : 256);
 346         u16 ecc0, ecc1;
 347         u32 code[2];
 348         u8 *p;
 349
 350         /* first 4 bytes ECC code for 256 page size */
 351         ecc0 = bfin_read_NFC_ECC0();
 352         ecc1 = bfin_read_NFC_ECC1();
 353
 354         code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 355
 356         dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
 357
 358         /* first 3 bytes in ecc_code for 256 page size */
 359         p = (u8 *) code;
 360         memcpy(ecc_code, p, 3);
 361
 362         /* second 4 bytes ECC code for 512 page size */
 363         if (page_size == 512) {
 364                 ecc0 = bfin_read_NFC_ECC2();
 365                 ecc1 = bfin_read_NFC_ECC3();
 366                 code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 367
 368                 /* second 3 bytes in ecc_code for second 256
 369                  * bytes of 512 page size
 370                  */
 371                 p = (u8 *) (code + 1);
 372                 memcpy((ecc_code + 3), p, 3);
 373                 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
 374         }
 375
 376         return 0;
 377 }
 378
 379 /*
 380  * PIO mode for buffer writing and reading
 381  */
 382 static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 383 {
 384         int i;
 385         unsigned short val;
 386
 387         /*
 388          * Data reads are requested by first writing to NFC_DATA_RD
 389          * and then reading back from NFC_READ.
 390          */
 391         for (i = 0; i < len; i++) {
 392                 while (bfin_read_NFC_STAT() & WB_FULL)
 393                         cpu_relax();
 394
 395                 /* Contents do not matter */
 396                 bfin_write_NFC_DATA_RD(0x0000);
 397                 SSYNC();
 398
 399                 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
 400                         cpu_relax();
 401
 402                 buf[i] = bfin_read_NFC_READ();
 403
 404                 val = bfin_read_NFC_IRQSTAT();
 405                 val |= RD_RDY;
 406                 bfin_write_NFC_IRQSTAT(val);
 407                 SSYNC();
 408         }
 409 }
 410
 411 static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
 412 {
 413         uint8_t val;
 414
 415         bf5xx_nand_read_buf(mtd, &val, 1);
 416
 417         return val;
 418 }
 419
 420 static void bf5xx_nand_write_buf(struct mtd_info *mtd,
 421                                 const uint8_t *buf, int len)
 422 {
 423         int i;
 424
 425         for (i = 0; i < len; i++) {
 426                 while (bfin_read_NFC_STAT() & WB_FULL)
 427                         cpu_relax();
 428
 429                 bfin_write_NFC_DATA_WR(buf[i]);
 430                 SSYNC();
 431         }
 432 }
 433
 434 static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 435 {
 436         int i;
 437         u16 *p = (u16 *) buf;
 438         len >>= 1;
 439
 440         /*
 441          * Data reads are requested by first writing to NFC_DATA_RD
 442          * and then reading back from NFC_READ.
 443          */
 444         bfin_write_NFC_DATA_RD(0x5555);
 445
 446         SSYNC();
 447
 448         for (i = 0; i < len; i++)
 449                 p[i] = bfin_read_NFC_READ();
 450 }
 451
 452 static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
 453                                 const uint8_t *buf, int len)
 454 {
 455         int i;
 456         u16 *p = (u16 *) buf;
 457         len >>= 1;
 458
 459         for (i = 0; i < len; i++)
 460                 bfin_write_NFC_DATA_WR(p[i]);
 461
 462         SSYNC();
 463 }
 464
 465 /*
 466  * DMA functions for buffer writing and reading
 467  */
 468 static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
 469 {
 470         struct bf5xx_nand_info *info = dev_id;
 471
 472         clear_dma_irqstat(CH_NFC);
 473         disable_dma(CH_NFC);
 474         complete(&info->dma_completion);
 475
 476         return IRQ_HANDLED;
 477 }
 478
 479 static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
 480                                 uint8_t *buf, int is_read)
 481 {
 482         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 483         struct bf5xx_nand_platform *plat = info->platform;
 484         unsigned short page_size = (plat->page_size ? 512 : 256);
 485         unsigned short val;
 486
 487         dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
 488                         mtd, buf, is_read);
 489
 490         /*
 491          * Before starting a dma transfer, be sure to invalidate/flush
 492          * the cache over the address range of your DMA buffer to
 493          * prevent cache coherency problems. Otherwise very subtle bugs
 494          * can be introduced to your driver.
 495          */
 496         if (is_read)
 497                 invalidate_dcache_range((unsigned int)buf,
 498                                 (unsigned int)(buf + page_size));
 499         else
 500                 flush_dcache_range((unsigned int)buf,
 501                                 (unsigned int)(buf + page_size));
 502
 503         /*
 504          * This register must be written before each page is
 505          * transferred to generate the correct ECC register
 506          * values.
 507          */
 508         bfin_write_NFC_RST(ECC_RST);
 509         SSYNC();
 510
 511         disable_dma(CH_NFC);
 512         clear_dma_irqstat(CH_NFC);
 513
 514         /* setup DMA register with Blackfin DMA API */
 515         set_dma_config(CH_NFC, 0x0);
 516         set_dma_start_addr(CH_NFC, (unsigned long) buf);
 517
 518         /* The DMAs have different size on BF52x and BF54x */
 519 #ifdef CONFIG_BF52x
 520         set_dma_x_count(CH_NFC, (page_size >> 1));
 521         set_dma_x_modify(CH_NFC, 2);
 522         val = DI_EN | WDSIZE_16;
 523 #endif
 524
 525 #ifdef CONFIG_BF54x
 526         set_dma_x_count(CH_NFC, (page_size >> 2));
 527         set_dma_x_modify(CH_NFC, 4);
 528         val = DI_EN | WDSIZE_32;
 529 #endif
 530         /* setup write or read operation */
 531         if (is_read)
 532                 val |= WNR;
 533         set_dma_config(CH_NFC, val);
 534         enable_dma(CH_NFC);
 535
 536         /* Start PAGE read/write operation */
 537         if (is_read)
 538                 bfin_write_NFC_PGCTL(PG_RD_START);
 539         else
 540                 bfin_write_NFC_PGCTL(PG_WR_START);
 541         wait_for_completion(&info->dma_completion);
 542 }
 543
 544 static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
 545                                         uint8_t *buf, int len)
 546 {
 547         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 548         struct bf5xx_nand_platform *plat = info->platform;
 549         unsigned short page_size = (plat->page_size ? 512 : 256);
 550
 551         dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
 552
 553         if (len == page_size)
 554                 bf5xx_nand_dma_rw(mtd, buf, 1);
 555         else
 556                 bf5xx_nand_read_buf(mtd, buf, len);
 557 }
 558
 559 static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
 560                                 const uint8_t *buf, int len)
 561 {
 562         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 563         struct bf5xx_nand_platform *plat = info->platform;
 564         unsigned short page_size = (plat->page_size ? 512 : 256);
 565
 566         dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
 567
 568         if (len == page_size)
 569                 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
 570         else
 571                 bf5xx_nand_write_buf(mtd, buf, len);
 572 }
 573
 574 static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 575                 uint8_t *buf, int page)
 576 {
 577         bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
 578         bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 579
 580         return 0;
 581 }
 582
 583 static void bf5xx_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 584                 const uint8_t *buf)
 585 {
 586         bf5xx_nand_write_buf(mtd, buf, mtd->writesize);
 587         bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 588 }
 589
 590 /*
 591  * System initialization functions
 592  */
 593 static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
 594 {
 595         int ret;
 596
 597         /* Do not use dma */
 598         if (!hardware_ecc)
 599                 return 0;
 600
 601         init_completion(&info->dma_completion);
 602
 603         /* Request NFC DMA channel */
 604         ret = request_dma(CH_NFC, "BF5XX NFC driver");
 605         if (ret < 0) {
 606                 dev_err(info->device, " unable to get DMA channel\n");
 607                 return ret;
 608         }
 609
 610 #ifdef CONFIG_BF54x
 611         /* Setup DMAC1 channel mux for NFC which shared with SDH */
 612         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
 613         SSYNC();
 614 #endif
 615
 616         set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
 617
 618         /* Turn off the DMA channel first */
 619         disable_dma(CH_NFC);
 620         return 0;
 621 }
 622
 623 static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
 624 {
 625         /* Free NFC DMA channel */
 626         if (hardware_ecc)
 627                 free_dma(CH_NFC);
 628 }
 629
 630 /*
 631  * BF5XX NFC hardware initialization
 632  *  - pin mux setup
 633  *  - clear interrupt status
 634  */
 635 static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
 636 {
 637         int err = 0;
 638         unsigned short val;
 639         struct bf5xx_nand_platform *plat = info->platform;
 640
 641         /* setup NFC_CTL register */
 642         dev_info(info->device,
 643                 "page_size=%d, data_width=%d, wr_dly=%d, rd_dly=%d\n",
 644                 (plat->page_size ? 512 : 256),
 645                 (plat->data_width ? 16 : 8),
 646                 plat->wr_dly, plat->rd_dly);
 647
 648         val = (plat->page_size << NFC_PG_SIZE_OFFSET) |
 649                 (plat->data_width << NFC_NWIDTH_OFFSET) |
 650                 (plat->rd_dly << NFC_RDDLY_OFFSET) |
 651                 (plat->wr_dly << NFC_WRDLY_OFFSET);
 652         dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
 653
 654         bfin_write_NFC_CTL(val);
 655         SSYNC();
 656
 657         /* clear interrupt status */
 658         bfin_write_NFC_IRQMASK(0x0);
 659         SSYNC();
 660         val = bfin_read_NFC_IRQSTAT();
 661         bfin_write_NFC_IRQSTAT(val);
 662         SSYNC();
 663
 664         /* DMA initialization  */
 665         if (bf5xx_nand_dma_init(info))
 666                 err = -ENXIO;
 667
 668         return err;
 669 }
 670
 671 /*
 672  * Device management interface
 673  */
 674 static int __devinit bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
 675 {
 676         struct mtd_info *mtd = &info->mtd;
 677
 678 #ifdef CONFIG_MTD_PARTITIONS
 679         struct mtd_partition *parts = info->platform->partitions;
 680         int nr = info->platform->nr_partitions;
 681
 682         return add_mtd_partitions(mtd, parts, nr);
 683 #else
 684         return add_mtd_device(mtd);
 685 #endif
 686 }
 687
 688 static int __devexit bf5xx_nand_remove(struct platform_device *pdev)
 689 {
 690         struct bf5xx_nand_info *info = to_nand_info(pdev);
 691         struct mtd_info *mtd = NULL;
 692
 693         platform_set_drvdata(pdev, NULL);
 694
 695         /* first thing we need to do is release all our mtds
 696          * and their partitions, then go through freeing the
 697          * resources used
 698          */
 699         mtd = &info->mtd;
 700         if (mtd) {
 701                 nand_release(mtd);
 702                 kfree(mtd);
 703         }
 704
 705         peripheral_free_list(bfin_nfc_pin_req);
 706         bf5xx_nand_dma_remove(info);
 707
 708         /* free the common resources */
 709         kfree(info);
 710
 711         return 0;
 712 }
 713
 714 /*
 715  * bf5xx_nand_probe
 716  *
 717  * called by device layer when it finds a device matching
 718  * one our driver can handled. This code checks to see if
 719  * it can allocate all necessary resources then calls the
 720  * nand layer to look for devices
 721  */
 722 static int __devinit bf5xx_nand_probe(struct platform_device *pdev)
 723 {
 724         struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
 725         struct bf5xx_nand_info *info = NULL;
 726         struct nand_chip *chip = NULL;
 727         struct mtd_info *mtd = NULL;
 728         int err = 0;
 729
 730         dev_dbg(&pdev->dev, "(%p)\n", pdev);
 731
 732         if (!plat) {
 733                 dev_err(&pdev->dev, "no platform specific information\n");
 734                 return -EINVAL;
 735         }
 736
 737         if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
 738                 dev_err(&pdev->dev, "requesting Peripherals failed\n");
 739                 return -EFAULT;
 740         }
 741
 742         info = kzalloc(sizeof(*info), GFP_KERNEL);
 743         if (info == NULL) {
 744                 dev_err(&pdev->dev, "no memory for flash info\n");
 745                 err = -ENOMEM;
 746                 goto out_err_kzalloc;
 747         }
 748
 749         platform_set_drvdata(pdev, info);
 750
 751         spin_lock_init(&info->controller.lock);
 752         init_waitqueue_head(&info->controller.wq);
 753
 754         info->device     = &pdev->dev;
 755         info->platform   = plat;
 756
 757         /* initialise chip data struct */
 758         chip = &info->chip;
 759
 760         if (plat->data_width)
 761                 chip->options |= NAND_BUSWIDTH_16;
 762
 763         chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
 764
 765         chip->read_buf = (plat->data_width) ?
 766                 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
 767         chip->write_buf = (plat->data_width) ?
 768                 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
 769
 770         chip->read_byte    = bf5xx_nand_read_byte;
 771
 772         chip->cmd_ctrl     = bf5xx_nand_hwcontrol;
 773         chip->dev_ready    = bf5xx_nand_devready;
 774
 775         chip->priv         = &info->mtd;
 776         chip->controller   = &info->controller;
 777
 778         chip->IO_ADDR_R    = (void __iomem *) NFC_READ;
 779         chip->IO_ADDR_W    = (void __iomem *) NFC_DATA_WR;
 780
 781         chip->chip_delay   = 0;
 782
 783         /* initialise mtd info data struct */
 784         mtd             = &info->mtd;
 785         mtd->priv       = chip;
 786         mtd->owner      = THIS_MODULE;
 787
 788         /* initialise the hardware */
 789         err = bf5xx_nand_hw_init(info);
 790         if (err)
 791                 goto out_err_hw_init;
 792
 793         /* setup hardware ECC data struct */
 794         if (hardware_ecc) {
 795 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 796                 chip->badblock_pattern = &bootrom_bbt;
 797                 chip->ecc.layout = &bootrom_ecclayout;
 798 #endif
 799
 800                 if (plat->page_size == NFC_PG_SIZE_256) {
 801                         chip->ecc.bytes = 3;
 802                         chip->ecc.size = 256;
 803                 } else if (plat->page_size == NFC_PG_SIZE_512) {
 804                         chip->ecc.bytes = 6;
 805                         chip->ecc.size = 512;
 806                 }
 807
 808                 chip->read_buf      = bf5xx_nand_dma_read_buf;
 809                 chip->write_buf     = bf5xx_nand_dma_write_buf;
 810                 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
 811                 chip->ecc.correct   = bf5xx_nand_correct_data;
 812                 chip->ecc.mode      = NAND_ECC_HW;
 813                 chip->ecc.hwctl     = bf5xx_nand_enable_hwecc;
 814                 chip->ecc.read_page_raw = bf5xx_nand_read_page_raw;
 815                 chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
 816         } else {
 817                 chip->ecc.mode      = NAND_ECC_SOFT;
 818         }
 819
 820         /* scan hardware nand chip and setup mtd info data struct */
 821         if (nand_scan(mtd, 1)) {
 822                 err = -ENXIO;
 823                 goto out_err_nand_scan;
 824         }
 825
 826         /* add NAND partition */
 827         bf5xx_nand_add_partition(info);
 828
 829         dev_dbg(&pdev->dev, "initialised ok\n");
 830         return 0;
 831
 832 out_err_nand_scan:
 833         bf5xx_nand_dma_remove(info);
 834 out_err_hw_init:
 835         platform_set_drvdata(pdev, NULL);
 836         kfree(info);
 837 out_err_kzalloc:
 838         peripheral_free_list(bfin_nfc_pin_req);
 839
 840         return err;
 841 }
 842
 843 /* PM Support */
 844 #ifdef CONFIG_PM
 845
 846 static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
 847 {
 848         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
 849
 850         return 0;
 851 }
 852
 853 static int bf5xx_nand_resume(struct platform_device *dev)
 854 {
 855         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
 856
 857         return 0;
 858 }
 859
 860 #else
 861 #define bf5xx_nand_suspend NULL
 862 #define bf5xx_nand_resume NULL
 863 #endif
 864
 865 /* driver device registration */
 866 static struct platform_driver bf5xx_nand_driver = {
 867         .probe          = bf5xx_nand_probe,
 868         .remove         = __devexit_p(bf5xx_nand_remove),
 869         .suspend        = bf5xx_nand_suspend,
 870         .resume         = bf5xx_nand_resume,
 871         .driver         = {
 872                 .name   = DRV_NAME,
 873                 .owner  = THIS_MODULE,
 874         },
 875 };
 876
 877 static int __init bf5xx_nand_init(void)
 878 {
 879         printk(KERN_INFO "%s, Version %s (c) 2007 Analog Devices, Inc.\n",
 880                 DRV_DESC, DRV_VERSION);
 881
 882         return platform_driver_register(&bf5xx_nand_driver);
 883 }
 884
 885 static void __exit bf5xx_nand_exit(void)
 886 {
 887         platform_driver_unregister(&bf5xx_nand_driver);
 888 }
 889
 890 module_init(bf5xx_nand_init);
 891 module_exit(bf5xx_nand_exit);
 892
 893 MODULE_LICENSE("GPL");
 894 MODULE_AUTHOR(DRV_AUTHOR);
 895 MODULE_DESCRIPTION(DRV_DESC);
 896 MODULE_ALIAS("platform:" DRV_NAME);