drivers/mtd/nand/bcm_umi_nand.c

   1 /*****************************************************************************
   2 * Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
   3 *
   4 * Unless you and Broadcom execute a separate written software license
   5 * agreement governing use of this software, this software is licensed to you
   6 * under the terms of the GNU General Public License version 2, available at
   7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
   8 *
   9 * Notwithstanding the above, under no circumstances may you combine this
  10 * software in any way with any other Broadcom software provided under a
  11 * license other than the GPL, without Broadcom's express prior written
  12 * consent.
  13 *****************************************************************************/
  14
  15 /* ---- Include Files ---------------------------------------------------- */
  16 #include <linux/module.h>
  17 #include <linux/types.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/string.h>
  21 #include <linux/ioport.h>
  22 #include <linux/device.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/mtd/mtd.h>
  28 #include <linux/mtd/nand.h>
  29 #include <linux/mtd/nand_ecc.h>
  30 #include <linux/mtd/partitions.h>
  31
  32 #include <asm/mach-types.h>
  33 #include <asm/system.h>
  34
  35 #include <mach/reg_nand.h>
  36 #include <mach/reg_umi.h>
  37
  38 #include "nand_bcm_umi.h"
  39
  40 #include <mach/memory_settings.h>
  41
  42 #define USE_DMA 1
  43 #include <mach/dma.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/completion.h>
  46
  47 /* ---- External Variable Declarations ----------------------------------- */
  48 /* ---- External Function Prototypes ------------------------------------- */
  49 /* ---- Public Variables ------------------------------------------------- */
  50 /* ---- Private Constants and Types -------------------------------------- */
  51 static const __devinitconst char gBanner[] = KERN_INFO \
  52         "BCM UMI MTD NAND Driver: 1.00\n";
  53
  54 #ifdef CONFIG_MTD_PARTITIONS
  55 const char *part_probes[] = { "cmdlinepart", NULL };
  56 #endif
  57
  58 #if NAND_ECC_BCH
  59 static uint8_t scan_ff_pattern[] = { 0xff };
  60
  61 static struct nand_bbt_descr largepage_bbt = {
  62         .options = 0,
  63         .offs = 0,
  64         .len = 1,
  65         .pattern = scan_ff_pattern
  66 };
  67 #endif
  68
  69 /*
  70 ** Preallocate a buffer to avoid having to do this every dma operation.
  71 ** This is the size of the preallocated coherent DMA buffer.
  72 */
  73 #if USE_DMA
  74 #define DMA_MIN_BUFLEN  512
  75 #define DMA_MAX_BUFLEN  PAGE_SIZE
  76 #define USE_DIRECT_IO(len)      (((len) < DMA_MIN_BUFLEN) || \
  77         ((len) > DMA_MAX_BUFLEN))
  78
  79 /*
  80  * The current NAND data space goes from 0x80001900 to 0x80001FFF,
  81  * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
  82  * size NAND flash. Need to break the DMA down to multiple 1Ks.
  83  *
  84  * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
  85  */
  86 #define DMA_MAX_LEN             1024
  87
  88 #else /* !USE_DMA */
  89 #define DMA_MIN_BUFLEN          0
  90 #define DMA_MAX_BUFLEN          0
  91 #define USE_DIRECT_IO(len)      1
  92 #endif
  93 /* ---- Private Function Prototypes -------------------------------------- */
  94 static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);
  95 static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
  96                                    int len);
  97
  98 /* ---- Private Variables ------------------------------------------------ */
  99 static struct mtd_info *board_mtd;
 100 static void __iomem *bcm_umi_io_base;
 101 static void *virtPtr;
 102 static dma_addr_t physPtr;
 103 static struct completion nand_comp;
 104
 105 /* ---- Private Functions ------------------------------------------------ */
 106 #if NAND_ECC_BCH
 107 #include "bcm_umi_bch.c"
 108 #else
 109 #include "bcm_umi_hamming.c"
 110 #endif
 111
 112 #if USE_DMA
 113
 114 /* Handler called when the DMA finishes. */
 115 static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
 116 {
 117         complete(&nand_comp);
 118 }
 119
 120 static int nand_dma_init(void)
 121 {
 122         int rc;
 123
 124         rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
 125                 nand_dma_handler, NULL);
 126         if (rc != 0) {
 127                 printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
 128                 return rc;
 129         }
 130
 131         virtPtr =
 132             dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
 133         if (virtPtr == NULL) {
 134                 printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
 135                 return -ENOMEM;
 136         }
 137
 138         return 0;
 139 }
 140
 141 static void nand_dma_term(void)
 142 {
 143         if (virtPtr != NULL)
 144                 dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
 145 }
 146
 147 static void nand_dma_read(void *buf, int len)
 148 {
 149         int offset = 0;
 150         int tmp_len = 0;
 151         int len_left = len;
 152         DMA_Handle_t hndl;
 153
 154         if (virtPtr == NULL)
 155                 panic("nand_dma_read: virtPtr == NULL\n");
 156
 157         if ((void *)physPtr == NULL)
 158                 panic("nand_dma_read: physPtr == NULL\n");
 159
 160         hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
 161         if (hndl < 0) {
 162                 printk(KERN_ERR
 163                        "nand_dma_read: unable to allocate dma channel: %d\n",
 164                        (int)hndl);
 165                 panic("\n");
 166         }
 167
 168         while (len_left > 0) {
 169                 if (len_left > DMA_MAX_LEN) {
 170                         tmp_len = DMA_MAX_LEN;
 171                         len_left -= DMA_MAX_LEN;
 172                 } else {
 173                         tmp_len = len_left;
 174                         len_left = 0;
 175                 }
 176
 177                 init_completion(&nand_comp);
 178                 dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
 179                                         physPtr + offset, tmp_len);
 180                 wait_for_completion(&nand_comp);
 181
 182                 offset += tmp_len;
 183         }
 184
 185         dma_free_channel(hndl);
 186
 187         if (buf != NULL)
 188                 memcpy(buf, virtPtr, len);
 189 }
 190
 191 static void nand_dma_write(const void *buf, int len)
 192 {
 193         int offset = 0;
 194         int tmp_len = 0;
 195         int len_left = len;
 196         DMA_Handle_t hndl;
 197
 198         if (buf == NULL)
 199                 panic("nand_dma_write: buf == NULL\n");
 200
 201         if (virtPtr == NULL)
 202                 panic("nand_dma_write: virtPtr == NULL\n");
 203
 204         if ((void *)physPtr == NULL)
 205                 panic("nand_dma_write: physPtr == NULL\n");
 206
 207         memcpy(virtPtr, buf, len);
 208
 209
 210         hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
 211         if (hndl < 0) {
 212                 printk(KERN_ERR
 213                        "nand_dma_write: unable to allocate dma channel: %d\n",
 214                        (int)hndl);
 215                 panic("\n");
 216         }
 217
 218         while (len_left > 0) {
 219                 if (len_left > DMA_MAX_LEN) {
 220                         tmp_len = DMA_MAX_LEN;
 221                         len_left -= DMA_MAX_LEN;
 222                 } else {
 223                         tmp_len = len_left;
 224                         len_left = 0;
 225                 }
 226
 227                 init_completion(&nand_comp);
 228                 dma_transfer_mem_to_mem(hndl, physPtr + offset,
 229                                         REG_NAND_DATA_PADDR, tmp_len);
 230                 wait_for_completion(&nand_comp);
 231
 232                 offset += tmp_len;
 233         }
 234
 235         dma_free_channel(hndl);
 236 }
 237
 238 #endif
 239
 240 static int nand_dev_ready(struct mtd_info *mtd)
 241 {
 242         return nand_bcm_umi_dev_ready();
 243 }
 244
 245 /****************************************************************************
 246 *
 247 *  bcm_umi_nand_inithw
 248 *
 249 *   This routine does the necessary hardware (board-specific)
 250 *   initializations.  This includes setting up the timings, etc.
 251 *
 252 ***************************************************************************/
 253 int bcm_umi_nand_inithw(void)
 254 {
 255         /* Configure nand timing parameters */
 256         REG_UMI_NAND_TCR &= ~0x7ffff;
 257         REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
 258
 259 #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
 260         /* enable software control of CS */
 261         REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
 262 #endif
 263
 264         /* keep NAND chip select asserted */
 265         REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
 266
 267         REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
 268         /* enable writes to flash */
 269         REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
 270
 271         writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
 272         nand_bcm_umi_wait_till_ready();
 273
 274 #if NAND_ECC_BCH
 275         nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
 276 #endif
 277
 278         return 0;
 279 }
 280
 281 /* Used to turn latch the proper register for access. */
 282 static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 283                                    unsigned int ctrl)
 284 {
 285         /* send command to hardware */
 286         struct nand_chip *chip = mtd->priv;
 287         if (ctrl & NAND_CTRL_CHANGE) {
 288                 if (ctrl & NAND_CLE) {
 289                         chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
 290                         goto CMD;
 291                 }
 292                 if (ctrl & NAND_ALE) {
 293                         chip->IO_ADDR_W =
 294                             bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
 295                         goto CMD;
 296                 }
 297                 chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
 298         }
 299
 300 CMD:
 301         /* Send command to chip directly */
 302         if (cmd != NAND_CMD_NONE)
 303                 writeb(cmd, chip->IO_ADDR_W);
 304 }
 305
 306 static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
 307                                    int len)
 308 {
 309         if (USE_DIRECT_IO(len)) {
 310                 /* Do it the old way if the buffer is small or too large.
 311                  * Probably quicker than starting and checking dma. */
 312                 int i;
 313                 struct nand_chip *this = mtd->priv;
 314
 315                 for (i = 0; i < len; i++)
 316                         writeb(buf[i], this->IO_ADDR_W);
 317         }
 318 #if USE_DMA
 319         else
 320                 nand_dma_write(buf, len);
 321 #endif
 322 }
 323
 324 static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
 325 {
 326         if (USE_DIRECT_IO(len)) {
 327                 int i;
 328                 struct nand_chip *this = mtd->priv;
 329
 330                 for (i = 0; i < len; i++)
 331                         buf[i] = readb(this->IO_ADDR_R);
 332         }
 333 #if USE_DMA
 334         else
 335                 nand_dma_read(buf, len);
 336 #endif
 337 }
 338
 339 static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
 340 static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
 341                                    int len)
 342 {
 343         /*
 344          * Try to readback page with ECC correction. This is necessary
 345          * for MLC parts which may have permanently stuck bits.
 346          */
 347         struct nand_chip *chip = mtd->priv;
 348         int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0);
 349         if (ret < 0)
 350                 return -EFAULT;
 351         else {
 352                 if (memcmp(readbackbuf, buf, len) == 0)
 353                         return 0;
 354
 355                 return -EFAULT;
 356         }
 357         return 0;
 358 }
 359
 360 static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
 361 {
 362         struct nand_chip *this;
 363         struct resource *r;
 364         int err = 0;
 365
 366         printk(gBanner);
 367
 368         /* Allocate memory for MTD device structure and private data */
 369         board_mtd =
 370             kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
 371                     GFP_KERNEL);
 372         if (!board_mtd) {
 373                 printk(KERN_WARNING
 374                        "Unable to allocate NAND MTD device structure.\n");
 375                 return -ENOMEM;
 376         }
 377
 378         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 379
 380         if (!r)
 381                 return -ENXIO;
 382
 383         /* map physical address */
 384         bcm_umi_io_base = ioremap(r->start, r->end - r->start + 1);
 385
 386         if (!bcm_umi_io_base) {
 387                 printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
 388                 kfree(board_mtd);
 389                 return -EIO;
 390         }
 391
 392         /* Get pointer to private data */
 393         this = (struct nand_chip *)(&board_mtd[1]);
 394
 395         /* Initialize structures */
 396         memset((char *)board_mtd, 0, sizeof(struct mtd_info));
 397         memset((char *)this, 0, sizeof(struct nand_chip));
 398
 399         /* Link the private data with the MTD structure */
 400         board_mtd->priv = this;
 401
 402         /* Initialize the NAND hardware.  */
 403         if (bcm_umi_nand_inithw() < 0) {
 404                 printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
 405                 iounmap(bcm_umi_io_base);
 406                 kfree(board_mtd);
 407                 return -EIO;
 408         }
 409
 410         /* Set address of NAND IO lines */
 411         this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
 412         this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
 413
 414         /* Set command delay time, see datasheet for correct value */
 415         this->chip_delay = 0;
 416         /* Assign the device ready function, if available */
 417         this->dev_ready = nand_dev_ready;
 418         this->options = 0;
 419
 420         this->write_buf = bcm_umi_nand_write_buf;
 421         this->read_buf = bcm_umi_nand_read_buf;
 422         this->verify_buf = bcm_umi_nand_verify_buf;
 423
 424         this->cmd_ctrl = bcm_umi_nand_hwcontrol;
 425         this->ecc.mode = NAND_ECC_HW;
 426         this->ecc.size = 512;
 427         this->ecc.bytes = NAND_ECC_NUM_BYTES;
 428 #if NAND_ECC_BCH
 429         this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
 430         this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
 431 #else
 432         this->ecc.correct = nand_correct_data512;
 433         this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
 434         this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
 435 #endif
 436
 437 #if USE_DMA
 438         err = nand_dma_init();
 439         if (err != 0)
 440                 return err;
 441 #endif
 442
 443         /* Figure out the size of the device that we have.
 444          * We need to do this to figure out which ECC
 445          * layout we'll be using.
 446          */
 447
 448         err = nand_scan_ident(board_mtd, 1, NULL);
 449         if (err) {
 450                 printk(KERN_ERR "nand_scan failed: %d\n", err);
 451                 iounmap(bcm_umi_io_base);
 452                 kfree(board_mtd);
 453                 return err;
 454         }
 455
 456         /* Now that we know the nand size, we can setup the ECC layout */
 457
 458         switch (board_mtd->writesize) { /* writesize is the pagesize */
 459         case 4096:
 460                 this->ecc.layout = &nand_hw_eccoob_4096;
 461                 break;
 462         case 2048:
 463                 this->ecc.layout = &nand_hw_eccoob_2048;
 464                 break;
 465         case 512:
 466                 this->ecc.layout = &nand_hw_eccoob_512;
 467                 break;
 468         default:
 469                 {
 470                         printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
 471                                          board_mtd->writesize);
 472                         return -EINVAL;
 473                 }
 474         }
 475
 476 #if NAND_ECC_BCH
 477         if (board_mtd->writesize > 512) {
 478                 if (this->options & NAND_USE_FLASH_BBT)
 479                         largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
 480                 this->badblock_pattern = &largepage_bbt;
 481         }
 482 #endif
 483
 484         /* Now finish off the scan, now that ecc.layout has been initialized. */
 485
 486         err = nand_scan_tail(board_mtd);
 487         if (err) {
 488                 printk(KERN_ERR "nand_scan failed: %d\n", err);
 489                 iounmap(bcm_umi_io_base);
 490                 kfree(board_mtd);
 491                 return err;
 492         }
 493
 494         /* Register the partitions */
 495         {
 496                 int nr_partitions;
 497                 struct mtd_partition *partition_info;
 498
 499                 board_mtd->name = "bcm_umi-nand";
 500                 nr_partitions =
 501                     parse_mtd_partitions(board_mtd, part_probes,
 502                                          &partition_info, 0);
 503
 504                 if (nr_partitions <= 0) {
 505                         printk(KERN_ERR "BCM UMI NAND: Too few partitions - %d\n",
 506                                nr_partitions);
 507                         iounmap(bcm_umi_io_base);
 508                         kfree(board_mtd);
 509                         return -EIO;
 510                 }
 511                 add_mtd_partitions(board_mtd, partition_info, nr_partitions);
 512         }
 513
 514         /* Return happy */
 515         return 0;
 516 }
 517
 518 static int bcm_umi_nand_remove(struct platform_device *pdev)
 519 {
 520 #if USE_DMA
 521         nand_dma_term();
 522 #endif
 523
 524         /* Release resources, unregister device */
 525         nand_release(board_mtd);
 526
 527         /* unmap physical address */
 528         iounmap(bcm_umi_io_base);
 529
 530         /* Free the MTD device structure */
 531         kfree(board_mtd);
 532
 533         return 0;
 534 }
 535
 536 #ifdef CONFIG_PM
 537 static int bcm_umi_nand_suspend(struct platform_device *pdev,
 538                                 pm_message_t state)
 539 {
 540         printk(KERN_ERR "MTD NAND suspend is being called\n");
 541         return 0;
 542 }
 543
 544 static int bcm_umi_nand_resume(struct platform_device *pdev)
 545 {
 546         printk(KERN_ERR "MTD NAND resume is being called\n");
 547         return 0;
 548 }
 549 #else
 550 #define bcm_umi_nand_suspend   NULL
 551 #define bcm_umi_nand_resume    NULL
 552 #endif
 553
 554 static struct platform_driver nand_driver = {
 555         .driver = {
 556                    .name = "bcm-nand",
 557                    .owner = THIS_MODULE,
 558                    },
 559         .probe = bcm_umi_nand_probe,
 560         .remove = bcm_umi_nand_remove,
 561         .suspend = bcm_umi_nand_suspend,
 562         .resume = bcm_umi_nand_resume,
 563 };
 564
 565 static int __init nand_init(void)
 566 {
 567         return platform_driver_register(&nand_driver);
 568 }
 569
 570 static void __exit nand_exit(void)
 571 {
 572         platform_driver_unregister(&nand_driver);
 573 }
 574
 575 module_init(nand_init);
 576 module_exit(nand_exit);
 577
 578 MODULE_LICENSE("GPL");
 579 MODULE_AUTHOR("Broadcom");
 580 MODULE_DESCRIPTION("BCM UMI MTD NAND driver");