2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
32 #include <linux/semaphore.h>
34 #include <mach/hardware.h>
35 #include <mach/board.h>
39 /* OMAP HSMMC Host Controller Registers */
40 #define OMAP_HSMMC_SYSCONFIG 0x0010
41 #define OMAP_HSMMC_SYSSTATUS 0x0014
42 #define OMAP_HSMMC_CON 0x002C
43 #define OMAP_HSMMC_BLK 0x0104
44 #define OMAP_HSMMC_ARG 0x0108
45 #define OMAP_HSMMC_CMD 0x010C
46 #define OMAP_HSMMC_RSP10 0x0110
47 #define OMAP_HSMMC_RSP32 0x0114
48 #define OMAP_HSMMC_RSP54 0x0118
49 #define OMAP_HSMMC_RSP76 0x011C
50 #define OMAP_HSMMC_DATA 0x0120
51 #define OMAP_HSMMC_HCTL 0x0128
52 #define OMAP_HSMMC_SYSCTL 0x012C
53 #define OMAP_HSMMC_STAT 0x0130
54 #define OMAP_HSMMC_IE 0x0134
55 #define OMAP_HSMMC_ISE 0x0138
56 #define OMAP_HSMMC_CAPA 0x0140
58 #define VS18 (1 << 26)
59 #define VS30 (1 << 25)
60 #define SDVS18 (0x5 << 9)
61 #define SDVS30 (0x6 << 9)
62 #define SDVS33 (0x7 << 9)
63 #define SDVS_MASK 0x00000E00
64 #define SDVSCLR 0xFFFFF1FF
65 #define SDVSDET 0x00000400
72 #define CLKD_MASK 0x0000FFC0
74 #define DTO_MASK 0x000F0000
76 #define INT_EN_MASK 0x307F0033
77 #define BWR_ENABLE (1 << 4)
78 #define BRR_ENABLE (1 << 5)
79 #define INIT_STREAM (1 << 1)
80 #define DP_SELECT (1 << 21)
85 #define FOUR_BIT (1 << 1)
91 #define CMD_TIMEOUT (1 << 16)
92 #define DATA_TIMEOUT (1 << 20)
93 #define CMD_CRC (1 << 17)
94 #define DATA_CRC (1 << 21)
95 #define CARD_ERR (1 << 28)
96 #define STAT_CLEAR 0xFFFFFFFF
97 #define INIT_STREAM_CMD 0x00000000
98 #define DUAL_VOLT_OCR_BIT 7
100 #define SRD (1 << 26)
101 #define SOFTRESET (1 << 1)
102 #define RESETDONE (1 << 0)
105 * FIXME: Most likely all the data using these _DEVID defines should come
106 * from the platform_data, or implemented in controller and slot specific
109 #define OMAP_MMC1_DEVID 0
110 #define OMAP_MMC2_DEVID 1
111 #define OMAP_MMC3_DEVID 2
113 #define MMC_TIMEOUT_MS 20
114 #define OMAP_MMC_MASTER_CLOCK 96000000
115 #define DRIVER_NAME "mmci-omap-hs"
117 /* Timeouts for entering power saving states on inactivity, msec */
118 #define OMAP_MMC_DISABLED_TIMEOUT 100
119 #define OMAP_MMC_SLEEP_TIMEOUT 1000
120 #define OMAP_MMC_OFF_TIMEOUT 8000
123 * One controller can have multiple slots, like on some omap boards using
124 * omap.c controller driver. Luckily this is not currently done on any known
125 * omap_hsmmc.c device.
127 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
130 * MMC Host controller read/write API's
132 #define OMAP_HSMMC_READ(base, reg) \
133 __raw_readl((base) + OMAP_HSMMC_##reg)
135 #define OMAP_HSMMC_WRITE(base, reg, val) \
136 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
138 struct omap_hsmmc_host {
140 struct mmc_host *mmc;
141 struct mmc_request *mrq;
142 struct mmc_command *cmd;
143 struct mmc_data *data;
147 struct semaphore sem;
148 struct work_struct mmc_carddetect_work;
150 resource_size_t mapbase;
151 spinlock_t irq_lock; /* Prevent races with irq handler */
154 unsigned int dma_len;
155 unsigned int dma_sg_idx;
156 unsigned char bus_mode;
157 unsigned char power_mode;
163 int dma_line_tx, dma_line_rx;
173 struct omap_mmc_platform_data *pdata;
177 * Stop clock to the card
179 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
181 OMAP_HSMMC_WRITE(host->base, SYSCTL,
182 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
183 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
184 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
190 * Restore the MMC host context, if it was lost as result of a
191 * power state change.
193 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
195 struct mmc_ios *ios = &host->mmc->ios;
196 struct omap_mmc_platform_data *pdata = host->pdata;
197 int context_loss = 0;
200 unsigned long timeout;
202 if (pdata->get_context_loss_count) {
203 context_loss = pdata->get_context_loss_count(host->dev);
204 if (context_loss < 0)
208 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
209 context_loss == host->context_loss ? "not " : "");
210 if (host->context_loss == context_loss)
213 /* Wait for hardware reset */
214 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
215 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
216 && time_before(jiffies, timeout))
219 /* Do software reset */
220 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
221 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
222 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
223 && time_before(jiffies, timeout))
226 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
227 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
229 if (host->id == OMAP_MMC1_DEVID) {
230 if (host->power_mode != MMC_POWER_OFF &&
231 (1 << ios->vdd) <= MMC_VDD_23_24)
241 OMAP_HSMMC_WRITE(host->base, HCTL,
242 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
244 OMAP_HSMMC_WRITE(host->base, CAPA,
245 OMAP_HSMMC_READ(host->base, CAPA) | capa);
247 OMAP_HSMMC_WRITE(host->base, HCTL,
248 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
250 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
251 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
252 && time_before(jiffies, timeout))
255 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
256 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
257 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
259 /* Do not initialize card-specific things if the power is off */
260 if (host->power_mode == MMC_POWER_OFF)
263 con = OMAP_HSMMC_READ(host->base, CON);
264 switch (ios->bus_width) {
265 case MMC_BUS_WIDTH_8:
266 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
268 case MMC_BUS_WIDTH_4:
269 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
270 OMAP_HSMMC_WRITE(host->base, HCTL,
271 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
273 case MMC_BUS_WIDTH_1:
274 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
275 OMAP_HSMMC_WRITE(host->base, HCTL,
276 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
281 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
285 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
292 OMAP_HSMMC_WRITE(host->base, SYSCTL,
293 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
294 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
295 OMAP_HSMMC_WRITE(host->base, SYSCTL,
296 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
298 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
299 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
300 && time_before(jiffies, timeout))
303 OMAP_HSMMC_WRITE(host->base, SYSCTL,
304 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
306 con = OMAP_HSMMC_READ(host->base, CON);
307 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
308 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
310 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
312 host->context_loss = context_loss;
314 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
319 * Save the MMC host context (store the number of power state changes so far).
321 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
323 struct omap_mmc_platform_data *pdata = host->pdata;
326 if (pdata->get_context_loss_count) {
327 context_loss = pdata->get_context_loss_count(host->dev);
328 if (context_loss < 0)
330 host->context_loss = context_loss;
336 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
341 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
348 * Send init stream sequence to card
349 * before sending IDLE command
351 static void send_init_stream(struct omap_hsmmc_host *host)
354 unsigned long timeout;
356 if (host->protect_card)
359 disable_irq(host->irq);
360 OMAP_HSMMC_WRITE(host->base, CON,
361 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
362 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
364 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
365 while ((reg != CC) && time_before(jiffies, timeout))
366 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
368 OMAP_HSMMC_WRITE(host->base, CON,
369 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
371 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
372 OMAP_HSMMC_READ(host->base, STAT);
374 enable_irq(host->irq);
378 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
382 if (mmc_slot(host).get_cover_state)
383 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
388 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
391 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
392 struct omap_hsmmc_host *host = mmc_priv(mmc);
394 return sprintf(buf, "%s\n",
395 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
398 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
401 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
404 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
405 struct omap_hsmmc_host *host = mmc_priv(mmc);
407 return sprintf(buf, "%s\n", mmc_slot(host).name);
410 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
413 * Configure the response type and send the cmd.
416 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
417 struct mmc_data *data)
419 int cmdreg = 0, resptype = 0, cmdtype = 0;
421 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
422 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
426 * Clear status bits and enable interrupts
428 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
429 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
432 OMAP_HSMMC_WRITE(host->base, IE,
433 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
435 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
437 host->response_busy = 0;
438 if (cmd->flags & MMC_RSP_PRESENT) {
439 if (cmd->flags & MMC_RSP_136)
441 else if (cmd->flags & MMC_RSP_BUSY) {
443 host->response_busy = 1;
449 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
450 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
451 * a val of 0x3, rest 0x0.
453 if (cmd == host->mrq->stop)
456 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
459 cmdreg |= DP_SELECT | MSBS | BCE;
460 if (data->flags & MMC_DATA_READ)
470 * In an interrupt context (i.e. STOP command), the spinlock is unlocked
471 * by the interrupt handler, otherwise (i.e. for a new request) it is
475 spin_unlock_irqrestore(&host->irq_lock, host->flags);
477 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
478 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
482 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
484 if (data->flags & MMC_DATA_WRITE)
485 return DMA_TO_DEVICE;
487 return DMA_FROM_DEVICE;
491 * Notify the transfer complete to MMC core
494 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
497 struct mmc_request *mrq = host->mrq;
499 /* TC before CC from CMD6 - don't know why, but it happens */
500 if (host->cmd && host->cmd->opcode == 6 &&
501 host->response_busy) {
502 host->response_busy = 0;
507 mmc_request_done(host->mmc, mrq);
513 if (host->use_dma && host->dma_ch != -1)
514 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
515 omap_hsmmc_get_dma_dir(host, data));
518 data->bytes_xfered += data->blocks * (data->blksz);
520 data->bytes_xfered = 0;
524 mmc_request_done(host->mmc, data->mrq);
527 omap_hsmmc_start_command(host, data->stop, NULL);
531 * Notify the core about command completion
534 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
538 if (cmd->flags & MMC_RSP_PRESENT) {
539 if (cmd->flags & MMC_RSP_136) {
540 /* response type 2 */
541 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
542 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
543 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
544 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
546 /* response types 1, 1b, 3, 4, 5, 6 */
547 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
550 if ((host->data == NULL && !host->response_busy) || cmd->error) {
552 mmc_request_done(host->mmc, cmd->mrq);
557 * DMA clean up for command errors
559 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
561 host->data->error = errno;
563 if (host->use_dma && host->dma_ch != -1) {
564 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
565 omap_hsmmc_get_dma_dir(host, host->data));
566 omap_free_dma(host->dma_ch);
574 * Readable error output
576 #ifdef CONFIG_MMC_DEBUG
577 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
579 /* --- means reserved bit without definition at documentation */
580 static const char *omap_hsmmc_status_bits[] = {
581 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
582 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
583 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
584 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
590 len = sprintf(buf, "MMC IRQ 0x%x :", status);
593 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
594 if (status & (1 << i)) {
595 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
599 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
601 #endif /* CONFIG_MMC_DEBUG */
604 * MMC controller internal state machines reset
606 * Used to reset command or data internal state machines, using respectively
607 * SRC or SRD bit of SYSCTL register
608 * Can be called from interrupt context
610 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
614 unsigned long limit = (loops_per_jiffy *
615 msecs_to_jiffies(MMC_TIMEOUT_MS));
617 OMAP_HSMMC_WRITE(host->base, SYSCTL,
618 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
620 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
624 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
625 dev_err(mmc_dev(host->mmc),
626 "Timeout waiting on controller reset in %s\n",
631 * MMC controller IRQ handler
633 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
635 struct omap_hsmmc_host *host = dev_id;
636 struct mmc_data *data;
637 int end_cmd = 0, end_trans = 0, status;
639 spin_lock(&host->irq_lock);
641 if (host->mrq == NULL) {
642 OMAP_HSMMC_WRITE(host->base, STAT,
643 OMAP_HSMMC_READ(host->base, STAT));
644 /* Flush posted write */
645 OMAP_HSMMC_READ(host->base, STAT);
646 spin_unlock(&host->irq_lock);
651 status = OMAP_HSMMC_READ(host->base, STAT);
652 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
655 #ifdef CONFIG_MMC_DEBUG
656 omap_hsmmc_report_irq(host, status);
658 if ((status & CMD_TIMEOUT) ||
659 (status & CMD_CRC)) {
661 if (status & CMD_TIMEOUT) {
662 omap_hsmmc_reset_controller_fsm(host,
664 host->cmd->error = -ETIMEDOUT;
666 host->cmd->error = -EILSEQ;
670 if (host->data || host->response_busy) {
672 omap_hsmmc_dma_cleanup(host,
674 host->response_busy = 0;
675 omap_hsmmc_reset_controller_fsm(host, SRD);
678 if ((status & DATA_TIMEOUT) ||
679 (status & DATA_CRC)) {
680 if (host->data || host->response_busy) {
681 int err = (status & DATA_TIMEOUT) ?
682 -ETIMEDOUT : -EILSEQ;
685 omap_hsmmc_dma_cleanup(host, err);
687 host->mrq->cmd->error = err;
688 host->response_busy = 0;
689 omap_hsmmc_reset_controller_fsm(host, SRD);
693 if (status & CARD_ERR) {
694 dev_dbg(mmc_dev(host->mmc),
695 "Ignoring card err CMD%d\n", host->cmd->opcode);
703 OMAP_HSMMC_WRITE(host->base, STAT, status);
704 /* Flush posted write */
705 OMAP_HSMMC_READ(host->base, STAT);
707 if (end_cmd || ((status & CC) && host->cmd))
708 omap_hsmmc_cmd_done(host, host->cmd);
709 if ((end_trans || (status & TC)) && host->mrq)
710 omap_hsmmc_xfer_done(host, data);
712 spin_unlock(&host->irq_lock);
717 static void set_sd_bus_power(struct omap_hsmmc_host *host)
721 OMAP_HSMMC_WRITE(host->base, HCTL,
722 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
723 for (i = 0; i < loops_per_jiffy; i++) {
724 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
731 * Switch MMC interface voltage ... only relevant for MMC1.
733 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
734 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
735 * Some chips, like eMMC ones, use internal transceivers.
737 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
742 /* Disable the clocks */
743 clk_disable(host->fclk);
744 clk_disable(host->iclk);
746 clk_disable(host->dbclk);
748 /* Turn the power off */
749 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
751 /* Turn the power ON with given VDD 1.8 or 3.0v */
753 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
755 clk_enable(host->iclk);
756 clk_enable(host->fclk);
758 clk_enable(host->dbclk);
763 OMAP_HSMMC_WRITE(host->base, HCTL,
764 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
765 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
768 * If a MMC dual voltage card is detected, the set_ios fn calls
769 * this fn with VDD bit set for 1.8V. Upon card removal from the
770 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
772 * Cope with a bit of slop in the range ... per data sheets:
773 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
774 * but recommended values are 1.71V to 1.89V
775 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
776 * but recommended values are 2.7V to 3.3V
778 * Board setup code shouldn't permit anything very out-of-range.
779 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
780 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
782 if ((1 << vdd) <= MMC_VDD_23_24)
787 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
788 set_sd_bus_power(host);
792 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
796 /* Protect the card while the cover is open */
797 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
799 if (!mmc_slot(host).get_cover_state)
802 host->reqs_blocked = 0;
803 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
804 if (host->protect_card) {
805 printk(KERN_INFO "%s: cover is closed, "
806 "card is now accessible\n",
807 mmc_hostname(host->mmc));
808 host->protect_card = 0;
811 if (!host->protect_card) {
812 printk(KERN_INFO "%s: cover is open, "
813 "card is now inaccessible\n",
814 mmc_hostname(host->mmc));
815 host->protect_card = 1;
821 * Work Item to notify the core about card insertion/removal
823 static void omap_hsmmc_detect(struct work_struct *work)
825 struct omap_hsmmc_host *host =
826 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
827 struct omap_mmc_slot_data *slot = &mmc_slot(host);
833 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
835 if (slot->card_detect)
836 carddetect = slot->card_detect(slot->card_detect_irq);
838 omap_hsmmc_protect_card(host);
839 carddetect = -ENOSYS;
843 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
845 mmc_host_enable(host->mmc);
846 omap_hsmmc_reset_controller_fsm(host, SRD);
847 mmc_host_lazy_disable(host->mmc);
849 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
854 * ISR for handling card insertion and removal
856 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
858 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
862 schedule_work(&host->mmc_carddetect_work);
867 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
868 struct mmc_data *data)
872 if (data->flags & MMC_DATA_WRITE)
873 sync_dev = host->dma_line_tx;
875 sync_dev = host->dma_line_rx;
879 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
880 struct mmc_data *data,
881 struct scatterlist *sgl)
883 int blksz, nblk, dma_ch;
885 dma_ch = host->dma_ch;
886 if (data->flags & MMC_DATA_WRITE) {
887 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
888 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
889 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
890 sg_dma_address(sgl), 0, 0);
892 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
893 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
894 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
895 sg_dma_address(sgl), 0, 0);
898 blksz = host->data->blksz;
899 nblk = sg_dma_len(sgl) / blksz;
901 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
902 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
903 omap_hsmmc_get_dma_sync_dev(host, data),
904 !(data->flags & MMC_DATA_WRITE));
906 omap_start_dma(dma_ch);
910 * DMA call back function
912 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
914 struct omap_hsmmc_host *host = data;
916 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
917 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
919 if (host->dma_ch < 0)
923 if (host->dma_sg_idx < host->dma_len) {
924 /* Fire up the next transfer. */
925 omap_hsmmc_config_dma_params(host, host->data,
926 host->data->sg + host->dma_sg_idx);
930 omap_free_dma(host->dma_ch);
933 * DMA Callback: run in interrupt context.
934 * mutex_unlock will throw a kernel warning if used.
940 * Routine to configure and start DMA for the MMC card
942 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
943 struct mmc_request *req)
945 int dma_ch = 0, ret = 0, err = 1, i;
946 struct mmc_data *data = req->data;
948 /* Sanity check: all the SG entries must be aligned by block size. */
949 for (i = 0; i < data->sg_len; i++) {
950 struct scatterlist *sgl;
953 if (sgl->length % data->blksz)
956 if ((data->blksz % 4) != 0)
957 /* REVISIT: The MMC buffer increments only when MSB is written.
958 * Return error for blksz which is non multiple of four.
963 * If for some reason the DMA transfer is still active,
964 * we wait for timeout period and free the dma
966 if (host->dma_ch != -1) {
967 set_current_state(TASK_UNINTERRUPTIBLE);
968 schedule_timeout(100);
969 if (down_trylock(&host->sem)) {
970 omap_free_dma(host->dma_ch);
976 if (down_trylock(&host->sem))
980 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
981 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
983 dev_err(mmc_dev(host->mmc),
984 "%s: omap_request_dma() failed with %d\n",
985 mmc_hostname(host->mmc), ret);
989 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
990 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
991 host->dma_ch = dma_ch;
992 host->dma_sg_idx = 0;
994 omap_hsmmc_config_dma_params(host, data, data->sg);
999 static void set_data_timeout(struct omap_hsmmc_host *host,
1000 unsigned int timeout_ns,
1001 unsigned int timeout_clks)
1003 unsigned int timeout, cycle_ns;
1004 uint32_t reg, clkd, dto = 0;
1006 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1007 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1011 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1012 timeout = timeout_ns / cycle_ns;
1013 timeout += timeout_clks;
1015 while ((timeout & 0x80000000) == 0) {
1032 reg |= dto << DTO_SHIFT;
1033 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1037 * Configure block length for MMC/SD cards and initiate the transfer.
1040 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1043 host->data = req->data;
1045 if (req->data == NULL) {
1046 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1048 * Set an arbitrary 100ms data timeout for commands with
1051 if (req->cmd->flags & MMC_RSP_BUSY)
1052 set_data_timeout(host, 100000000U, 0);
1056 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1057 | (req->data->blocks << 16));
1058 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1060 if (host->use_dma) {
1061 ret = omap_hsmmc_start_dma_transfer(host, req);
1063 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1071 * Request function. for read/write operation
1073 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1075 struct omap_hsmmc_host *host = mmc_priv(mmc);
1079 * Prevent races with the interrupt handler because of unexpected
1080 * interrupts, but not if we are already in interrupt context i.e.
1083 if (!in_interrupt()) {
1084 spin_lock_irqsave(&host->irq_lock, host->flags);
1086 * Protect the card from I/O if there is a possibility
1087 * it can be removed.
1089 if (host->protect_card) {
1090 if (host->reqs_blocked < 3) {
1092 * Ensure the controller is left in a consistent
1093 * state by resetting the command and data state
1096 omap_hsmmc_reset_controller_fsm(host, SRD);
1097 omap_hsmmc_reset_controller_fsm(host, SRC);
1098 host->reqs_blocked += 1;
1100 req->cmd->error = -EBADF;
1102 req->data->error = -EBADF;
1103 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1104 mmc_request_done(mmc, req);
1106 } else if (host->reqs_blocked)
1107 host->reqs_blocked = 0;
1109 WARN_ON(host->mrq != NULL);
1111 err = omap_hsmmc_prepare_data(host, req);
1113 req->cmd->error = err;
1115 req->data->error = err;
1117 if (!in_interrupt())
1118 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1119 mmc_request_done(mmc, req);
1123 omap_hsmmc_start_command(host, req->cmd, req->data);
1126 /* Routine to configure clock values. Exposed API to core */
1127 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1129 struct omap_hsmmc_host *host = mmc_priv(mmc);
1131 unsigned long regval;
1132 unsigned long timeout;
1134 int do_send_init_stream = 0;
1136 mmc_host_enable(host->mmc);
1138 if (ios->power_mode != host->power_mode) {
1139 switch (ios->power_mode) {
1141 mmc_slot(host).set_power(host->dev, host->slot_id,
1146 mmc_slot(host).set_power(host->dev, host->slot_id,
1148 host->vdd = ios->vdd;
1151 do_send_init_stream = 1;
1154 host->power_mode = ios->power_mode;
1157 /* FIXME: set registers based only on changes to ios */
1159 con = OMAP_HSMMC_READ(host->base, CON);
1160 switch (mmc->ios.bus_width) {
1161 case MMC_BUS_WIDTH_8:
1162 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1164 case MMC_BUS_WIDTH_4:
1165 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1166 OMAP_HSMMC_WRITE(host->base, HCTL,
1167 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1169 case MMC_BUS_WIDTH_1:
1170 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1171 OMAP_HSMMC_WRITE(host->base, HCTL,
1172 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1176 if (host->id == OMAP_MMC1_DEVID) {
1177 /* Only MMC1 can interface at 3V without some flavor
1178 * of external transceiver; but they all handle 1.8V.
1180 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1181 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1183 * The mmc_select_voltage fn of the core does
1184 * not seem to set the power_mode to
1185 * MMC_POWER_UP upon recalculating the voltage.
1188 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1189 dev_dbg(mmc_dev(host->mmc),
1190 "Switch operation failed\n");
1195 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1199 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1205 omap_hsmmc_stop_clock(host);
1206 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1207 regval = regval & ~(CLKD_MASK);
1208 regval = regval | (dsor << 6) | (DTO << 16);
1209 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1210 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1211 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1213 /* Wait till the ICS bit is set */
1214 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1215 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1216 && time_before(jiffies, timeout))
1219 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1220 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1222 if (do_send_init_stream)
1223 send_init_stream(host);
1225 con = OMAP_HSMMC_READ(host->base, CON);
1226 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1227 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1229 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1231 if (host->power_mode == MMC_POWER_OFF)
1232 mmc_host_disable(host->mmc);
1234 mmc_host_lazy_disable(host->mmc);
1237 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1239 struct omap_hsmmc_host *host = mmc_priv(mmc);
1241 if (!mmc_slot(host).card_detect)
1243 return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq);
1246 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1248 struct omap_hsmmc_host *host = mmc_priv(mmc);
1250 if (!mmc_slot(host).get_ro)
1252 return mmc_slot(host).get_ro(host->dev, 0);
1255 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1257 u32 hctl, capa, value;
1259 /* Only MMC1 supports 3.0V */
1260 if (host->id == OMAP_MMC1_DEVID) {
1268 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1269 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1271 value = OMAP_HSMMC_READ(host->base, CAPA);
1272 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1274 /* Set the controller to AUTO IDLE mode */
1275 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1276 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1278 /* Set SD bus power bit */
1279 set_sd_bus_power(host);
1283 * Dynamic power saving handling, FSM:
1284 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1286 * |______________________|______________________|
1288 * ENABLED: mmc host is fully functional
1289 * DISABLED: fclk is off
1290 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1291 * REGSLEEP: fclk is off, voltage regulator is asleep
1292 * OFF: fclk is off, voltage regulator is off
1294 * Transition handlers return the timeout for the next state transition
1295 * or negative error.
1298 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1300 /* Handler for [ENABLED -> DISABLED] transition */
1301 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1303 omap_hsmmc_context_save(host);
1304 clk_disable(host->fclk);
1305 host->dpm_state = DISABLED;
1307 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1309 if (host->power_mode == MMC_POWER_OFF)
1312 return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
1315 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1316 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1320 if (!mmc_try_claim_host(host->mmc))
1323 clk_enable(host->fclk);
1324 omap_hsmmc_context_restore(host);
1325 if (mmc_card_can_sleep(host->mmc)) {
1326 err = mmc_card_sleep(host->mmc);
1328 clk_disable(host->fclk);
1329 mmc_release_host(host->mmc);
1332 new_state = CARDSLEEP;
1334 new_state = REGSLEEP;
1336 if (mmc_slot(host).set_sleep)
1337 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1338 new_state == CARDSLEEP);
1339 /* FIXME: turn off bus power and perhaps interrupts too */
1340 clk_disable(host->fclk);
1341 host->dpm_state = new_state;
1343 mmc_release_host(host->mmc);
1345 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1346 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1348 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1349 mmc_slot(host).card_detect ||
1350 (mmc_slot(host).get_cover_state &&
1351 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1352 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1357 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1358 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1360 if (!mmc_try_claim_host(host->mmc))
1363 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1364 mmc_slot(host).card_detect ||
1365 (mmc_slot(host).get_cover_state &&
1366 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1367 mmc_release_host(host->mmc);
1371 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1373 host->power_mode = MMC_POWER_OFF;
1375 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1376 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1378 host->dpm_state = OFF;
1380 mmc_release_host(host->mmc);
1385 /* Handler for [DISABLED -> ENABLED] transition */
1386 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1390 err = clk_enable(host->fclk);
1394 omap_hsmmc_context_restore(host);
1395 host->dpm_state = ENABLED;
1397 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1402 /* Handler for [SLEEP -> ENABLED] transition */
1403 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1405 if (!mmc_try_claim_host(host->mmc))
1408 clk_enable(host->fclk);
1409 omap_hsmmc_context_restore(host);
1410 if (mmc_slot(host).set_sleep)
1411 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1412 host->vdd, host->dpm_state == CARDSLEEP);
1413 if (mmc_card_can_sleep(host->mmc))
1414 mmc_card_awake(host->mmc);
1416 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1417 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1419 host->dpm_state = ENABLED;
1421 mmc_release_host(host->mmc);
1426 /* Handler for [OFF -> ENABLED] transition */
1427 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1429 clk_enable(host->fclk);
1431 omap_hsmmc_context_restore(host);
1432 omap_hsmmc_conf_bus_power(host);
1433 mmc_power_restore_host(host->mmc);
1435 host->dpm_state = ENABLED;
1437 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1443 * Bring MMC host to ENABLED from any other PM state.
1445 static int omap_hsmmc_enable(struct mmc_host *mmc)
1447 struct omap_hsmmc_host *host = mmc_priv(mmc);
1449 switch (host->dpm_state) {
1451 return omap_hsmmc_disabled_to_enabled(host);
1454 return omap_hsmmc_sleep_to_enabled(host);
1456 return omap_hsmmc_off_to_enabled(host);
1458 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1464 * Bring MMC host in PM state (one level deeper).
1466 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1468 struct omap_hsmmc_host *host = mmc_priv(mmc);
1470 switch (host->dpm_state) {
1474 delay = omap_hsmmc_enabled_to_disabled(host);
1475 if (lazy || delay < 0)
1480 return omap_hsmmc_disabled_to_sleep(host);
1483 return omap_hsmmc_sleep_to_off(host);
1485 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1490 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1492 struct omap_hsmmc_host *host = mmc_priv(mmc);
1495 err = clk_enable(host->fclk);
1498 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1499 omap_hsmmc_context_restore(host);
1503 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1505 struct omap_hsmmc_host *host = mmc_priv(mmc);
1507 omap_hsmmc_context_save(host);
1508 clk_disable(host->fclk);
1509 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1513 static const struct mmc_host_ops omap_hsmmc_ops = {
1514 .enable = omap_hsmmc_enable_fclk,
1515 .disable = omap_hsmmc_disable_fclk,
1516 .request = omap_hsmmc_request,
1517 .set_ios = omap_hsmmc_set_ios,
1518 .get_cd = omap_hsmmc_get_cd,
1519 .get_ro = omap_hsmmc_get_ro,
1520 /* NYET -- enable_sdio_irq */
1523 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1524 .enable = omap_hsmmc_enable,
1525 .disable = omap_hsmmc_disable,
1526 .request = omap_hsmmc_request,
1527 .set_ios = omap_hsmmc_set_ios,
1528 .get_cd = omap_hsmmc_get_cd,
1529 .get_ro = omap_hsmmc_get_ro,
1530 /* NYET -- enable_sdio_irq */
1533 #ifdef CONFIG_DEBUG_FS
1535 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1537 struct mmc_host *mmc = s->private;
1538 struct omap_hsmmc_host *host = mmc_priv(mmc);
1539 int context_loss = 0;
1541 if (host->pdata->get_context_loss_count)
1542 context_loss = host->pdata->get_context_loss_count(host->dev);
1544 seq_printf(s, "mmc%d:\n"
1547 " nesting_cnt:\t%d\n"
1548 " ctx_loss:\t%d:%d\n"
1550 mmc->index, mmc->enabled ? 1 : 0,
1551 host->dpm_state, mmc->nesting_cnt,
1552 host->context_loss, context_loss);
1554 if (host->suspended || host->dpm_state == OFF) {
1555 seq_printf(s, "host suspended, can't read registers\n");
1559 if (clk_enable(host->fclk) != 0) {
1560 seq_printf(s, "can't read the regs\n");
1564 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1565 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1566 seq_printf(s, "CON:\t\t0x%08x\n",
1567 OMAP_HSMMC_READ(host->base, CON));
1568 seq_printf(s, "HCTL:\t\t0x%08x\n",
1569 OMAP_HSMMC_READ(host->base, HCTL));
1570 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1571 OMAP_HSMMC_READ(host->base, SYSCTL));
1572 seq_printf(s, "IE:\t\t0x%08x\n",
1573 OMAP_HSMMC_READ(host->base, IE));
1574 seq_printf(s, "ISE:\t\t0x%08x\n",
1575 OMAP_HSMMC_READ(host->base, ISE));
1576 seq_printf(s, "CAPA:\t\t0x%08x\n",
1577 OMAP_HSMMC_READ(host->base, CAPA));
1579 clk_disable(host->fclk);
1584 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1586 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1589 static const struct file_operations mmc_regs_fops = {
1590 .open = omap_hsmmc_regs_open,
1592 .llseek = seq_lseek,
1593 .release = single_release,
1596 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1598 if (mmc->debugfs_root)
1599 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1600 mmc, &mmc_regs_fops);
1605 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1611 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1613 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1614 struct mmc_host *mmc;
1615 struct omap_hsmmc_host *host = NULL;
1616 struct resource *res;
1619 if (pdata == NULL) {
1620 dev_err(&pdev->dev, "Platform Data is missing\n");
1624 if (pdata->nr_slots == 0) {
1625 dev_err(&pdev->dev, "No Slots\n");
1629 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1630 irq = platform_get_irq(pdev, 0);
1631 if (res == NULL || irq < 0)
1634 res = request_mem_region(res->start, res->end - res->start + 1,
1639 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1645 host = mmc_priv(mmc);
1647 host->pdata = pdata;
1648 host->dev = &pdev->dev;
1650 host->dev->dma_mask = &pdata->dma_mask;
1653 host->id = pdev->id;
1655 host->mapbase = res->start;
1656 host->base = ioremap(host->mapbase, SZ_4K);
1657 host->power_mode = -1;
1659 platform_set_drvdata(pdev, host);
1660 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1662 if (mmc_slot(host).power_saving)
1663 mmc->ops = &omap_hsmmc_ps_ops;
1665 mmc->ops = &omap_hsmmc_ops;
1667 mmc->f_min = 400000;
1668 mmc->f_max = 52000000;
1670 sema_init(&host->sem, 1);
1671 spin_lock_init(&host->irq_lock);
1673 host->iclk = clk_get(&pdev->dev, "ick");
1674 if (IS_ERR(host->iclk)) {
1675 ret = PTR_ERR(host->iclk);
1679 host->fclk = clk_get(&pdev->dev, "fck");
1680 if (IS_ERR(host->fclk)) {
1681 ret = PTR_ERR(host->fclk);
1683 clk_put(host->iclk);
1687 omap_hsmmc_context_save(host);
1689 mmc->caps |= MMC_CAP_DISABLE;
1690 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1691 /* we start off in DISABLED state */
1692 host->dpm_state = DISABLED;
1694 if (mmc_host_enable(host->mmc) != 0) {
1695 clk_put(host->iclk);
1696 clk_put(host->fclk);
1700 if (clk_enable(host->iclk) != 0) {
1701 mmc_host_disable(host->mmc);
1702 clk_put(host->iclk);
1703 clk_put(host->fclk);
1707 if (cpu_is_omap2430()) {
1708 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1710 * MMC can still work without debounce clock.
1712 if (IS_ERR(host->dbclk))
1713 dev_warn(mmc_dev(host->mmc),
1714 "Failed to get debounce clock\n");
1716 host->got_dbclk = 1;
1718 if (host->got_dbclk)
1719 if (clk_enable(host->dbclk) != 0)
1720 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1724 /* Since we do only SG emulation, we can have as many segs
1726 mmc->max_phys_segs = 1024;
1727 mmc->max_hw_segs = 1024;
1729 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1730 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1731 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1732 mmc->max_seg_size = mmc->max_req_size;
1734 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1735 MMC_CAP_WAIT_WHILE_BUSY;
1737 if (mmc_slot(host).wires >= 8)
1738 mmc->caps |= MMC_CAP_8_BIT_DATA;
1739 else if (mmc_slot(host).wires >= 4)
1740 mmc->caps |= MMC_CAP_4_BIT_DATA;
1742 if (mmc_slot(host).nonremovable)
1743 mmc->caps |= MMC_CAP_NONREMOVABLE;
1745 omap_hsmmc_conf_bus_power(host);
1747 /* Select DMA lines */
1749 case OMAP_MMC1_DEVID:
1750 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1751 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1753 case OMAP_MMC2_DEVID:
1754 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1755 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1757 case OMAP_MMC3_DEVID:
1758 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1759 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1762 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1766 /* Request IRQ for MMC operations */
1767 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
1768 mmc_hostname(mmc), host);
1770 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1774 /* initialize power supplies, gpios, etc */
1775 if (pdata->init != NULL) {
1776 if (pdata->init(&pdev->dev) != 0) {
1777 dev_dbg(mmc_dev(host->mmc),
1778 "Unable to configure MMC IRQs\n");
1779 goto err_irq_cd_init;
1782 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1784 /* Request IRQ for card detect */
1785 if ((mmc_slot(host).card_detect_irq)) {
1786 ret = request_irq(mmc_slot(host).card_detect_irq,
1787 omap_hsmmc_cd_handler,
1788 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1790 mmc_hostname(mmc), host);
1792 dev_dbg(mmc_dev(host->mmc),
1793 "Unable to grab MMC CD IRQ\n");
1798 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1799 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1801 mmc_host_lazy_disable(host->mmc);
1803 omap_hsmmc_protect_card(host);
1807 if (mmc_slot(host).name != NULL) {
1808 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1812 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1813 ret = device_create_file(&mmc->class_dev,
1814 &dev_attr_cover_switch);
1816 goto err_cover_switch;
1819 omap_hsmmc_debugfs(mmc);
1824 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1826 mmc_remove_host(mmc);
1828 free_irq(mmc_slot(host).card_detect_irq, host);
1830 free_irq(host->irq, host);
1832 mmc_host_disable(host->mmc);
1833 clk_disable(host->iclk);
1834 clk_put(host->fclk);
1835 clk_put(host->iclk);
1836 if (host->got_dbclk) {
1837 clk_disable(host->dbclk);
1838 clk_put(host->dbclk);
1842 iounmap(host->base);
1844 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1845 release_mem_region(res->start, res->end - res->start + 1);
1851 static int omap_hsmmc_remove(struct platform_device *pdev)
1853 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1854 struct resource *res;
1857 mmc_host_enable(host->mmc);
1858 mmc_remove_host(host->mmc);
1859 if (host->pdata->cleanup)
1860 host->pdata->cleanup(&pdev->dev);
1861 free_irq(host->irq, host);
1862 if (mmc_slot(host).card_detect_irq)
1863 free_irq(mmc_slot(host).card_detect_irq, host);
1864 flush_scheduled_work();
1866 mmc_host_disable(host->mmc);
1867 clk_disable(host->iclk);
1868 clk_put(host->fclk);
1869 clk_put(host->iclk);
1870 if (host->got_dbclk) {
1871 clk_disable(host->dbclk);
1872 clk_put(host->dbclk);
1875 mmc_free_host(host->mmc);
1876 iounmap(host->base);
1879 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1881 release_mem_region(res->start, res->end - res->start + 1);
1882 platform_set_drvdata(pdev, NULL);
1888 static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
1891 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1893 if (host && host->suspended)
1897 host->suspended = 1;
1898 if (host->pdata->suspend) {
1899 ret = host->pdata->suspend(&pdev->dev,
1902 dev_dbg(mmc_dev(host->mmc),
1903 "Unable to handle MMC board"
1904 " level suspend\n");
1905 host->suspended = 0;
1909 cancel_work_sync(&host->mmc_carddetect_work);
1910 mmc_host_enable(host->mmc);
1911 ret = mmc_suspend_host(host->mmc, state);
1913 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1914 OMAP_HSMMC_WRITE(host->base, IE, 0);
1917 OMAP_HSMMC_WRITE(host->base, HCTL,
1918 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1919 mmc_host_disable(host->mmc);
1920 clk_disable(host->iclk);
1921 if (host->got_dbclk)
1922 clk_disable(host->dbclk);
1924 host->suspended = 0;
1925 if (host->pdata->resume) {
1926 ret = host->pdata->resume(&pdev->dev,
1929 dev_dbg(mmc_dev(host->mmc),
1930 "Unmask interrupt failed\n");
1932 mmc_host_disable(host->mmc);
1939 /* Routine to resume the MMC device */
1940 static int omap_hsmmc_resume(struct platform_device *pdev)
1943 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1945 if (host && !host->suspended)
1949 ret = clk_enable(host->iclk);
1953 if (mmc_host_enable(host->mmc) != 0) {
1954 clk_disable(host->iclk);
1958 if (host->got_dbclk)
1959 clk_enable(host->dbclk);
1961 omap_hsmmc_conf_bus_power(host);
1963 if (host->pdata->resume) {
1964 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1966 dev_dbg(mmc_dev(host->mmc),
1967 "Unmask interrupt failed\n");
1970 omap_hsmmc_protect_card(host);
1972 /* Notify the core to resume the host */
1973 ret = mmc_resume_host(host->mmc);
1975 host->suspended = 0;
1977 mmc_host_lazy_disable(host->mmc);
1983 dev_dbg(mmc_dev(host->mmc),
1984 "Failed to enable MMC clocks during resume\n");
1989 #define omap_hsmmc_suspend NULL
1990 #define omap_hsmmc_resume NULL
1993 static struct platform_driver omap_hsmmc_driver = {
1994 .remove = omap_hsmmc_remove,
1995 .suspend = omap_hsmmc_suspend,
1996 .resume = omap_hsmmc_resume,
1998 .name = DRIVER_NAME,
1999 .owner = THIS_MODULE,
2003 static int __init omap_hsmmc_init(void)
2005 /* Register the MMC driver */
2006 return platform_driver_register(&omap_hsmmc_driver);
2009 static void __exit omap_hsmmc_cleanup(void)
2011 /* Unregister MMC driver */
2012 platform_driver_unregister(&omap_hsmmc_driver);
2015 module_init(omap_hsmmc_init);
2016 module_exit(omap_hsmmc_cleanup);
2018 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2019 MODULE_LICENSE("GPL");
2020 MODULE_ALIAS("platform:" DRIVER_NAME);
2021 MODULE_AUTHOR("Texas Instruments Inc");