2 * Base driver for Maxim MAX8925
4 * Copyright (C) 2009 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/mfd/core.h>
18 #include <linux/mfd/max8925.h>
20 #define IRQ_MODE_STATUS 0
21 #define IRQ_MODE_MASK 1
23 static int __get_irq_offset(struct max8925_chip *chip, int irq, int mode,
24 int *offset, int *bit)
29 switch (chip->chip_id) {
31 *bit = irq % BITS_PER_BYTE;
32 if (irq < (BITS_PER_BYTE << 1)) { /* irq = [0,15] */
33 *offset = (mode) ? MAX8925_CHG_IRQ1_MASK
35 if (irq >= BITS_PER_BYTE)
37 } else { /* irq = [16,31] */
38 *offset = (mode) ? MAX8925_ON_OFF_IRQ1_MASK
39 : MAX8925_ON_OFF_IRQ1;
40 if (irq >= (BITS_PER_BYTE * 3))
45 *bit = irq % BITS_PER_BYTE;
46 *offset = (mode) ? MAX8925_TSC_IRQ_MASK : MAX8925_TSC_IRQ;
53 dev_err(chip->dev, "Wrong irq #%d is assigned\n", irq);
57 static int __check_irq(int irq)
59 if ((irq < 0) || (irq >= MAX8925_NUM_IRQ))
64 int max8925_mask_irq(struct max8925_chip *chip, int irq)
68 ret = __get_irq_offset(chip, irq, IRQ_MODE_MASK, &offset, &bit);
71 ret = max8925_set_bits(chip->i2c, offset, 1 << bit, 1 << bit);
75 int max8925_unmask_irq(struct max8925_chip *chip, int irq)
79 ret = __get_irq_offset(chip, irq, IRQ_MODE_MASK, &offset, &bit);
82 ret = max8925_set_bits(chip->i2c, offset, 1 << bit, 0);
86 #define INT_STATUS_NUM (MAX8925_NUM_IRQ / BITS_PER_BYTE)
88 static irqreturn_t max8925_irq_thread(int irq, void *data)
90 struct max8925_chip *chip = data;
91 unsigned long irq_status[INT_STATUS_NUM];
92 unsigned char status_buf[INT_STATUS_NUM << 1];
95 memset(irq_status, 0, sizeof(unsigned long) * INT_STATUS_NUM);
97 /* all these interrupt status registers are read-only */
98 switch (chip->chip_id) {
100 ret = max8925_bulk_read(chip->i2c, MAX8925_CHG_IRQ1,
104 ret = max8925_bulk_read(chip->i2c, MAX8925_ON_OFF_IRQ1,
108 ret = max8925_bulk_read(chip->i2c, MAX8925_ON_OFF_IRQ2,
112 /* clear masked interrupt status */
113 status_buf[0] &= (~status_buf[2] & CHG_IRQ1_MASK);
114 irq_status[0] |= status_buf[0];
115 status_buf[1] &= (~status_buf[3] & CHG_IRQ2_MASK);
116 irq_status[0] |= (status_buf[1] << BITS_PER_BYTE);
117 status_buf[4] &= (~status_buf[5] & ON_OFF_IRQ1_MASK);
118 irq_status[0] |= (status_buf[4] << (BITS_PER_BYTE * 2));
119 status_buf[6] &= (~status_buf[7] & ON_OFF_IRQ2_MASK);
120 irq_status[0] |= (status_buf[6] << (BITS_PER_BYTE * 3));
123 ret = max8925_bulk_read(chip->i2c, MAX8925_TSC_IRQ,
127 /* clear masked interrupt status */
128 status_buf[0] &= (~status_buf[1] & TSC_IRQ_MASK);
129 irq_status[0] |= status_buf[0];
135 for_each_bit(i, &irq_status[0], MAX8925_NUM_IRQ) {
136 clear_bit(i, irq_status);
137 dev_dbg(chip->dev, "Servicing IRQ #%d in %s\n", i, chip->name);
139 mutex_lock(&chip->irq_lock);
140 if (chip->irq[i].handler)
141 chip->irq[i].handler(i, chip->irq[i].data);
143 max8925_mask_irq(chip, i);
144 dev_err(chip->dev, "Noboday cares IRQ #%d in %s. "
145 "Now mask it.\n", i, chip->name);
147 mutex_unlock(&chip->irq_lock);
153 int max8925_request_irq(struct max8925_chip *chip, int irq,
154 irq_handler_t handler, void *data)
156 if ((__check_irq(irq) < 0) || !handler)
159 mutex_lock(&chip->irq_lock);
160 chip->irq[irq].handler = handler;
161 chip->irq[irq].data = data;
162 mutex_unlock(&chip->irq_lock);
165 EXPORT_SYMBOL(max8925_request_irq);
167 int max8925_free_irq(struct max8925_chip *chip, int irq)
169 if (__check_irq(irq) < 0)
172 mutex_lock(&chip->irq_lock);
173 chip->irq[irq].handler = NULL;
174 chip->irq[irq].data = NULL;
175 mutex_unlock(&chip->irq_lock);
178 EXPORT_SYMBOL(max8925_free_irq);
180 static int __devinit device_gpm_init(struct max8925_chip *chip,
181 struct i2c_client *i2c,
182 struct max8925_platform_data *pdata)
187 ret = max8925_set_bits(i2c, MAX8925_CHG_IRQ1_MASK, 0x7, 0x7);
190 ret = max8925_set_bits(i2c, MAX8925_CHG_IRQ2_MASK, 0xff, 0xff);
193 ret = max8925_set_bits(i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff, 0xff);
196 ret = max8925_set_bits(i2c, MAX8925_ON_OFF_IRQ2_MASK, 0x3, 0x3);
201 memset(chip->irq, 0, sizeof(struct max8925_irq) * MAX8925_NUM_IRQ);
202 ret = request_threaded_irq(i2c->irq, NULL, max8925_irq_thread,
203 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
204 "max8925-gpm", chip);
206 dev_err(chip->dev, "Failed to request IRQ #%d.\n", i2c->irq);
209 chip->chip_irq = i2c->irq;
211 /* enable hard-reset for ONKEY power-off */
212 max8925_set_bits(i2c, MAX8925_SYSENSEL, 0x80, 0x80);
217 static int __devinit device_adc_init(struct max8925_chip *chip,
218 struct i2c_client *i2c,
219 struct max8925_platform_data *pdata)
224 ret = max8925_set_bits(i2c, MAX8925_TSC_IRQ_MASK, 3, 3);
227 memset(chip->irq, 0, sizeof(struct max8925_irq) * MAX8925_NUM_IRQ);
228 ret = request_threaded_irq(i2c->irq, NULL, max8925_irq_thread,
229 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
230 "max8925-adc", chip);
232 dev_err(chip->dev, "Failed to request IRQ #%d.\n", i2c->irq);
235 chip->chip_irq = i2c->irq;
240 int __devinit max8925_device_init(struct max8925_chip *chip,
241 struct max8925_platform_data *pdata)
243 switch (chip->chip_id) {
245 device_gpm_init(chip, chip->i2c, pdata);
248 device_adc_init(chip, chip->i2c, pdata);
254 void max8925_device_exit(struct max8925_chip *chip)
256 if (chip->chip_irq >= 0)
257 free_irq(chip->chip_irq, chip);
260 MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925");
261 MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com");
262 MODULE_LICENSE("GPL");