drivers/media/video/cx231xx/cx231xx-avcore.c

   1 /*
   2    cx231xx_avcore.c - driver for Conexant Cx23100/101/102
   3                       USB video capture devices
   4
   5    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   6
   7    This program contains the specific code to control the avdecoder chip and
   8    other related usb control functions for cx231xx based chipset.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/bitmap.h>
  30 #include <linux/usb.h>
  31 #include <linux/i2c.h>
  32 #include <linux/mm.h>
  33 #include <linux/mutex.h>
  34
  35 #include <media/v4l2-common.h>
  36 #include <media/v4l2-ioctl.h>
  37 #include <media/v4l2-chip-ident.h>
  38
  39 #include "cx231xx.h"
  40
  41 /******************************************************************************
  42                         -: BLOCK ARRANGEMENT :-
  43         I2S block ----------------------|
  44         [I2S audio]                     |
  45                                         |
  46         Analog Front End --> Direct IF -|-> Cx25840 --> Audio
  47         [video & audio]                 |   [Audio]
  48                                         |
  49                                         |-> Cx25840 --> Video
  50                                             [Video]
  51
  52 *******************************************************************************/
  53
  54 /******************************************************************************
  55  *                    A F E - B L O C K    C O N T R O L   functions          *
  56  *                              [ANALOG FRONT END]                            *
  57  ******************************************************************************/
  58 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
  59 {
  60         return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
  61                                         saddr, 2, data, 1);
  62 }
  63
  64 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
  65 {
  66         int status;
  67         u32 temp = 0;
  68
  69         status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
  70                                         saddr, 2, &temp, 1);
  71         *data = (u8) temp;
  72         return status;
  73 }
  74
  75 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
  76 {
  77         int status = 0;
  78         u8 temp = 0;
  79         u8 afe_power_status = 0;
  80         int i = 0;
  81
  82         /* super block initialize */
  83         temp = (u8) (ref_count & 0xff);
  84         status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
  85         if (status < 0)
  86                 return status;
  87
  88         status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
  89         if (status < 0)
  90                 return status;
  91
  92         temp = (u8) ((ref_count & 0x300) >> 8);
  93         temp |= 0x40;
  94         status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
  95         if (status < 0)
  96                 return status;
  97
  98         status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
  99         if (status < 0)
 100                 return status;
 101
 102         /* enable pll     */
 103         while (afe_power_status != 0x18) {
 104                 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
 105                 if (status < 0) {
 106                         cx231xx_info(
 107                         ": Init Super Block failed in send cmd\n");
 108                         break;
 109                 }
 110
 111                 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
 112                 afe_power_status &= 0xff;
 113                 if (status < 0) {
 114                         cx231xx_info(
 115                         ": Init Super Block failed in receive cmd\n");
 116                         break;
 117                 }
 118                 i++;
 119                 if (i == 10) {
 120                         cx231xx_info(
 121                         ": Init Super Block force break in loop !!!!\n");
 122                         status = -1;
 123                         break;
 124                 }
 125         }
 126
 127         if (status < 0)
 128                 return status;
 129
 130         /* start tuning filter */
 131         status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
 132         if (status < 0)
 133                 return status;
 134
 135         msleep(5);
 136
 137         /* exit tuning */
 138         status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
 139
 140         return status;
 141 }
 142
 143 int cx231xx_afe_init_channels(struct cx231xx *dev)
 144 {
 145         int status = 0;
 146
 147         /* power up all 3 channels, clear pd_buffer */
 148         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
 149         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
 150         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
 151
 152         /* Enable quantizer calibration */
 153         status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
 154
 155         /* channel initialize, force modulator (fb) reset */
 156         status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
 157         status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
 158         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
 159
 160         /* start quantilizer calibration  */
 161         status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
 162         status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
 163         status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
 164         msleep(5);
 165
 166         /* exit modulator (fb) reset */
 167         status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
 168         status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
 169         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
 170
 171         /* enable the pre_clamp in each channel for single-ended input */
 172         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
 173         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
 174         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
 175
 176         /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
 177         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 178                                    ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
 179         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 180                                    ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
 181         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 182                                    ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
 183
 184         /* dynamic element matching off */
 185         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
 186         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
 187         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
 188
 189         return status;
 190 }
 191
 192 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
 193 {
 194         u8 c_value = 0;
 195         int status = 0;
 196
 197         status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
 198         c_value &= (~(0x50));
 199         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
 200
 201         return status;
 202 }
 203
 204 /*
 205         The Analog Front End in Cx231xx has 3 channels. These
 206         channels are used to share between different inputs
 207         like tuner, s-video and composite inputs.
 208
 209         channel 1 ----- pin 1  to pin4(in reg is 1-4)
 210         channel 2 ----- pin 5  to pin8(in reg is 5-8)
 211         channel 3 ----- pin 9 to pin 12(in reg is 9-11)
 212 */
 213 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
 214 {
 215         u8 ch1_setting = (u8) input_mux;
 216         u8 ch2_setting = (u8) (input_mux >> 8);
 217         u8 ch3_setting = (u8) (input_mux >> 16);
 218         int status = 0;
 219         u8 value = 0;
 220
 221         if (ch1_setting != 0) {
 222                 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
 223                 value &= (!INPUT_SEL_MASK);
 224                 value |= (ch1_setting - 1) << 4;
 225                 value &= 0xff;
 226                 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
 227         }
 228
 229         if (ch2_setting != 0) {
 230                 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
 231                 value &= (!INPUT_SEL_MASK);
 232                 value |= (ch2_setting - 1) << 4;
 233                 value &= 0xff;
 234                 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
 235         }
 236
 237         /* For ch3_setting, the value to put in the register is
 238            7 less than the input number */
 239         if (ch3_setting != 0) {
 240                 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
 241                 value &= (!INPUT_SEL_MASK);
 242                 value |= (ch3_setting - 1) << 4;
 243                 value &= 0xff;
 244                 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
 245         }
 246
 247         return status;
 248 }
 249
 250 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
 251 {
 252         int status = 0;
 253
 254         /*
 255         * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
 256         * Currently, only baseband works.
 257         */
 258
 259         switch (mode) {
 260         case AFE_MODE_LOW_IF:
 261                 /* SetupAFEforLowIF();  */
 262                 break;
 263         case AFE_MODE_BASEBAND:
 264                 status = cx231xx_afe_setup_AFE_for_baseband(dev);
 265                 break;
 266         case AFE_MODE_EU_HI_IF:
 267                 /* SetupAFEforEuHiIF(); */
 268                 break;
 269         case AFE_MODE_US_HI_IF:
 270                 /* SetupAFEforUsHiIF(); */
 271                 break;
 272         case AFE_MODE_JAPAN_HI_IF:
 273                 /* SetupAFEforJapanHiIF(); */
 274                 break;
 275         }
 276
 277         if ((mode != dev->afe_mode) &&
 278                 (dev->video_input == CX231XX_VMUX_TELEVISION))
 279                 status = cx231xx_afe_adjust_ref_count(dev,
 280                                                      CX231XX_VMUX_TELEVISION);
 281
 282         dev->afe_mode = mode;
 283
 284         return status;
 285 }
 286
 287 int cx231xx_afe_update_power_control(struct cx231xx *dev,
 288                                         enum AV_MODE avmode)
 289 {
 290         u8 afe_power_status = 0;
 291         int status = 0;
 292
 293         switch (dev->model) {
 294         case CX231XX_BOARD_CNXT_RDE_250:
 295         case CX231XX_BOARD_CNXT_RDU_250:
 296                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 297                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 298                                                 FLD_PWRDN_ENABLE_PLL)) {
 299                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 300                                                         FLD_PWRDN_TUNING_BIAS |
 301                                                         FLD_PWRDN_ENABLE_PLL);
 302                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 303                                                         &afe_power_status);
 304                                 if (status < 0)
 305                                         break;
 306                         }
 307
 308                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 309                                                         0x00);
 310                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 311                                                         0x00);
 312                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 313                                                         0x00);
 314                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 315                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 316                                                         0x70);
 317                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 318                                                         0x70);
 319                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 320                                                         0x70);
 321
 322                         status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 323                                                   &afe_power_status);
 324                         afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 325                                                 FLD_PWRDN_PD_BIAS |
 326                                                 FLD_PWRDN_PD_TUNECK;
 327                         status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 328                                                    afe_power_status);
 329                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 330                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 331                                                 FLD_PWRDN_ENABLE_PLL)) {
 332                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 333                                                         FLD_PWRDN_TUNING_BIAS |
 334                                                         FLD_PWRDN_ENABLE_PLL);
 335                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 336                                                         &afe_power_status);
 337                                 if (status < 0)
 338                                         break;
 339                         }
 340
 341                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 342                                                 0x00);
 343                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 344                                                 0x00);
 345                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 346                                                 0x00);
 347                 } else {
 348                         cx231xx_info("Invalid AV mode input\n");
 349                         status = -1;
 350                 }
 351                 break;
 352         default:
 353                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 354                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 355                                                 FLD_PWRDN_ENABLE_PLL)) {
 356                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 357                                                         FLD_PWRDN_TUNING_BIAS |
 358                                                         FLD_PWRDN_ENABLE_PLL);
 359                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 360                                                         &afe_power_status);
 361                                 if (status < 0)
 362                                         break;
 363                         }
 364
 365                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 366                                                         0x40);
 367                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 368                                                         0x40);
 369                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 370                                                         0x00);
 371                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 372                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 373                                                         0x70);
 374                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 375                                                         0x70);
 376                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 377                                                         0x70);
 378
 379                         status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 380                                                        &afe_power_status);
 381                         afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 382                                                 FLD_PWRDN_PD_BIAS |
 383                                                 FLD_PWRDN_PD_TUNECK;
 384                         status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 385                                                         afe_power_status);
 386                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 387                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 388                                                 FLD_PWRDN_ENABLE_PLL)) {
 389                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 390                                                         FLD_PWRDN_TUNING_BIAS |
 391                                                         FLD_PWRDN_ENABLE_PLL);
 392                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 393                                                         &afe_power_status);
 394                                 if (status < 0)
 395                                         break;
 396                         }
 397
 398                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 399                                                         0x00);
 400                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 401                                                         0x00);
 402                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 403                                                         0x40);
 404                 } else {
 405                         cx231xx_info("Invalid AV mode input\n");
 406                         status = -1;
 407                 }
 408         }                       /* switch  */
 409
 410         return status;
 411 }
 412
 413 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
 414 {
 415         u8 input_mode = 0;
 416         u8 ntf_mode = 0;
 417         int status = 0;
 418
 419         dev->video_input = video_input;
 420
 421         if (video_input == CX231XX_VMUX_TELEVISION) {
 422                 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
 423                 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
 424                                         &ntf_mode);
 425         } else {
 426                 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
 427                 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
 428                                         &ntf_mode);
 429         }
 430
 431         input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
 432
 433         switch (input_mode) {
 434         case SINGLE_ENDED:
 435                 dev->afe_ref_count = 0x23C;
 436                 break;
 437         case LOW_IF:
 438                 dev->afe_ref_count = 0x24C;
 439                 break;
 440         case EU_IF:
 441                 dev->afe_ref_count = 0x258;
 442                 break;
 443         case US_IF:
 444                 dev->afe_ref_count = 0x260;
 445                 break;
 446         default:
 447                 break;
 448         }
 449
 450         status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
 451
 452         return status;
 453 }
 454
 455 /******************************************************************************
 456  *     V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions    *
 457  ******************************************************************************/
 458 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
 459 {
 460         return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 461                                         saddr, 2, data, 1);
 462 }
 463
 464 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
 465 {
 466         int status;
 467         u32 temp = 0;
 468
 469         status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 470                                         saddr, 2, &temp, 1);
 471         *data = (u8) temp;
 472         return status;
 473 }
 474
 475 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
 476 {
 477         return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 478                                         saddr, 2, data, 4);
 479 }
 480
 481 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
 482 {
 483         return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 484                                         saddr, 2, data, 4);
 485 }
 486
 487 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
 488 {
 489         int status = 0;
 490
 491         switch (INPUT(input)->type) {
 492         case CX231XX_VMUX_COMPOSITE1:
 493         case CX231XX_VMUX_SVIDEO:
 494                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 495                     (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
 496                         /* External AV */
 497                         status = cx231xx_set_power_mode(dev,
 498                                         POLARIS_AVMODE_ENXTERNAL_AV);
 499                         if (status < 0) {
 500                                 cx231xx_errdev("%s: set_power_mode : Failed to"
 501                                                 " set Power - errCode [%d]!\n",
 502                                                 __func__, status);
 503                                 return status;
 504                         }
 505                 }
 506                 status = cx231xx_set_decoder_video_input(dev,
 507                                                          INPUT(input)->type,
 508                                                          INPUT(input)->vmux);
 509                 break;
 510         case CX231XX_VMUX_TELEVISION:
 511         case CX231XX_VMUX_CABLE:
 512                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 513                     (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
 514                         /* Tuner */
 515                         status = cx231xx_set_power_mode(dev,
 516                                                 POLARIS_AVMODE_ANALOGT_TV);
 517                         if (status < 0) {
 518                                 cx231xx_errdev("%s: set_power_mode:Failed"
 519                                         " to set Power - errCode [%d]!\n",
 520                                         __func__, status);
 521                                 return status;
 522                         }
 523                 }
 524                 status = cx231xx_set_decoder_video_input(dev,
 525                                                         CX231XX_VMUX_COMPOSITE1,
 526                                                         INPUT(input)->vmux);
 527                 break;
 528         default:
 529                 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
 530                      __func__, INPUT(input)->type);
 531                 break;
 532         }
 533
 534         /* save the selection */
 535         dev->video_input = input;
 536
 537         return status;
 538 }
 539
 540 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
 541                                 u8 pin_type, u8 input)
 542 {
 543         int status = 0;
 544         u32 value = 0;
 545
 546         if (pin_type != dev->video_input) {
 547                 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
 548                 if (status < 0) {
 549                         cx231xx_errdev("%s: adjust_ref_count :Failed to set"
 550                                 "AFE input mux - errCode [%d]!\n",
 551                                 __func__, status);
 552                         return status;
 553                 }
 554         }
 555
 556         /* call afe block to set video inputs */
 557         status = cx231xx_afe_set_input_mux(dev, input);
 558         if (status < 0) {
 559                 cx231xx_errdev("%s: set_input_mux :Failed to set"
 560                                 " AFE input mux - errCode [%d]!\n",
 561                                 __func__, status);
 562                 return status;
 563         }
 564
 565         switch (pin_type) {
 566         case CX231XX_VMUX_COMPOSITE1:
 567                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 568                 value |= (0 << 13) | (1 << 4);
 569                 value &= ~(1 << 5);
 570
 571                 /* set [24:23] [22:15] to 0  */
 572                 value &= (~(0x1ff8000));
 573                 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
 574                 value |= 0x1000000;
 575                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 576
 577                 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 578                 value |= (1 << 7);
 579                 status = vid_blk_write_word(dev, OUT_CTRL1, value);
 580
 581                 /* Set vip 1.1 output mode */
 582                 status = cx231xx_read_modify_write_i2c_dword(dev,
 583                                                         VID_BLK_I2C_ADDRESS,
 584                                                         OUT_CTRL1,
 585                                                         FLD_OUT_MODE,
 586                                                         OUT_MODE_VIP11);
 587
 588                 /* Tell DIF object to go to baseband mode  */
 589                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 590                 if (status < 0) {
 591                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 592                                                    " mode- errCode [%d]!\n",
 593                                 __func__, status);
 594                         return status;
 595                 }
 596
 597                 /* Read the DFE_CTRL1 register */
 598                 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 599
 600                 /* enable the VBI_GATE_EN */
 601                 value |= FLD_VBI_GATE_EN;
 602
 603                 /* Enable the auto-VGA enable */
 604                 value |= FLD_VGA_AUTO_EN;
 605
 606                 /* Write it back */
 607                 status = vid_blk_write_word(dev, DFE_CTRL1, value);
 608
 609                 /* Disable auto config of registers */
 610                 status = cx231xx_read_modify_write_i2c_dword(dev,
 611                                         VID_BLK_I2C_ADDRESS,
 612                                         MODE_CTRL, FLD_ACFG_DIS,
 613                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 614
 615                 /* Set CVBS input mode */
 616                 status = cx231xx_read_modify_write_i2c_dword(dev,
 617                         VID_BLK_I2C_ADDRESS,
 618                         MODE_CTRL, FLD_INPUT_MODE,
 619                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 620                 break;
 621         case CX231XX_VMUX_SVIDEO:
 622                 /* Disable the use of  DIF */
 623
 624                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 625
 626                 /* set [24:23] [22:15] to 0 */
 627                 value &= (~(0x1ff8000));
 628                 /* set FUNC_MODE[24:23] = 2
 629                 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
 630                 value |= 0x1000010;
 631                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 632
 633                 /* Tell DIF object to go to baseband mode */
 634                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 635                 if (status < 0) {
 636                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 637                                                    " mode- errCode [%d]!\n",
 638                                 __func__, status);
 639                         return status;
 640                 }
 641
 642                 /* Read the DFE_CTRL1 register */
 643                 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 644
 645                 /* enable the VBI_GATE_EN */
 646                 value |= FLD_VBI_GATE_EN;
 647
 648                 /* Enable the auto-VGA enable */
 649                 value |= FLD_VGA_AUTO_EN;
 650
 651                 /* Write it back */
 652                 status = vid_blk_write_word(dev, DFE_CTRL1, value);
 653
 654                 /* Disable auto config of registers  */
 655                 status =  cx231xx_read_modify_write_i2c_dword(dev,
 656                                         VID_BLK_I2C_ADDRESS,
 657                                         MODE_CTRL, FLD_ACFG_DIS,
 658                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 659
 660                 /* Set YC input mode */
 661                 status = cx231xx_read_modify_write_i2c_dword(dev,
 662                         VID_BLK_I2C_ADDRESS,
 663                         MODE_CTRL,
 664                         FLD_INPUT_MODE,
 665                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
 666
 667                 /* Chroma to ADC2 */
 668                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 669                 value |= FLD_CHROMA_IN_SEL;     /* set the chroma in select */
 670
 671                 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
 672                    This sets them to use video
 673                    rather than audio.  Only one of the two will be in use. */
 674                 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
 675
 676                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 677
 678                 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
 679                 break;
 680         case CX231XX_VMUX_TELEVISION:
 681         case CX231XX_VMUX_CABLE:
 682         default:
 683                 switch (dev->model) {
 684                 case CX231XX_BOARD_CNXT_RDE_250:
 685                 case CX231XX_BOARD_CNXT_RDU_250:
 686                         /* Disable the use of  DIF   */
 687
 688                         status = vid_blk_read_word(dev, AFE_CTRL, &value);
 689                         value |= (0 << 13) | (1 << 4);
 690                         value &= ~(1 << 5);
 691
 692                         /* set [24:23] [22:15] to 0 */
 693                         value &= (~(0x1FF8000));
 694                         /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
 695                         value |= 0x1000000;
 696                         status = vid_blk_write_word(dev, AFE_CTRL, value);
 697
 698                         status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 699                         value |= (1 << 7);
 700                         status = vid_blk_write_word(dev, OUT_CTRL1, value);
 701
 702                         /* Set vip 1.1 output mode */
 703                         status = cx231xx_read_modify_write_i2c_dword(dev,
 704                                                         VID_BLK_I2C_ADDRESS,
 705                                                         OUT_CTRL1, FLD_OUT_MODE,
 706                                                         OUT_MODE_VIP11);
 707
 708                         /* Tell DIF object to go to baseband mode */
 709                         status = cx231xx_dif_set_standard(dev,
 710                                                           DIF_USE_BASEBAND);
 711                         if (status < 0) {
 712                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 713                                                 " mode- errCode [%d]!\n",
 714                                                 __func__, status);
 715                                 return status;
 716                         }
 717
 718                         /* Read the DFE_CTRL1 register */
 719                         status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 720
 721                         /* enable the VBI_GATE_EN */
 722                         value |= FLD_VBI_GATE_EN;
 723
 724                         /* Enable the auto-VGA enable */
 725                         value |= FLD_VGA_AUTO_EN;
 726
 727                         /* Write it back */
 728                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 729
 730                         /* Disable auto config of registers */
 731                         status = cx231xx_read_modify_write_i2c_dword(dev,
 732                                         VID_BLK_I2C_ADDRESS,
 733                                         MODE_CTRL, FLD_ACFG_DIS,
 734                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 735
 736                         /* Set CVBS input mode */
 737                         status = cx231xx_read_modify_write_i2c_dword(dev,
 738                                 VID_BLK_I2C_ADDRESS,
 739                                 MODE_CTRL, FLD_INPUT_MODE,
 740                                 cx231xx_set_field(FLD_INPUT_MODE,
 741                                                 INPUT_MODE_CVBS_0));
 742                         break;
 743                 default:
 744                         /* Enable the DIF for the tuner */
 745
 746                         /* Reinitialize the DIF */
 747                         status = cx231xx_dif_set_standard(dev, dev->norm);
 748                         if (status < 0) {
 749                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 750                                                 " mode- errCode [%d]!\n",
 751                                                 __func__, status);
 752                                 return status;
 753                         }
 754
 755                         /* Make sure bypass is cleared */
 756                         status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
 757
 758                         /* Clear the bypass bit */
 759                         value &= ~FLD_DIF_DIF_BYPASS;
 760
 761                         /* Enable the use of the DIF block */
 762                         status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
 763
 764                         /* Read the DFE_CTRL1 register */
 765                         status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 766
 767                         /* Disable the VBI_GATE_EN */
 768                         value &= ~FLD_VBI_GATE_EN;
 769
 770                         /* Enable the auto-VGA enable, AGC, and
 771                            set the skip count to 2 */
 772                         value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
 773
 774                         /* Write it back */
 775                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 776
 777                         /* Wait until AGC locks up */
 778                         msleep(1);
 779
 780                         /* Disable the auto-VGA enable AGC */
 781                         value &= ~(FLD_VGA_AUTO_EN);
 782
 783                         /* Write it back */
 784                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 785
 786                         /* Enable Polaris B0 AGC output */
 787                         status = vid_blk_read_word(dev, PIN_CTRL, &value);
 788                         value |= (FLD_OEF_AGC_RF) |
 789                                  (FLD_OEF_AGC_IFVGA) |
 790                                  (FLD_OEF_AGC_IF);
 791                         status = vid_blk_write_word(dev, PIN_CTRL, value);
 792
 793                         /* Set vip 1.1 output mode */
 794                         status = cx231xx_read_modify_write_i2c_dword(dev,
 795                                                 VID_BLK_I2C_ADDRESS,
 796                                                 OUT_CTRL1, FLD_OUT_MODE,
 797                                                 OUT_MODE_VIP11);
 798
 799                         /* Disable auto config of registers */
 800                         status = cx231xx_read_modify_write_i2c_dword(dev,
 801                                         VID_BLK_I2C_ADDRESS,
 802                                         MODE_CTRL, FLD_ACFG_DIS,
 803                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 804
 805                         /* Set CVBS input mode */
 806                         status = cx231xx_read_modify_write_i2c_dword(dev,
 807                                 VID_BLK_I2C_ADDRESS,
 808                                 MODE_CTRL, FLD_INPUT_MODE,
 809                                 cx231xx_set_field(FLD_INPUT_MODE,
 810                                                 INPUT_MODE_CVBS_0));
 811
 812                         /* Set some bits in AFE_CTRL so that channel 2 or 3
 813                          * is ready to receive audio */
 814                         /* Clear clamp for channels 2 and 3      (bit 16-17) */
 815                         /* Clear droop comp                      (bit 19-20) */
 816                         /* Set VGA_SEL (for audio control)       (bit 7-8) */
 817                         status = vid_blk_read_word(dev, AFE_CTRL, &value);
 818
 819                         value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
 820
 821                         status = vid_blk_write_word(dev, AFE_CTRL, value);
 822                         break;
 823
 824                 }
 825                 break;
 826         }
 827
 828         /* Set raw VBI mode */
 829         status = cx231xx_read_modify_write_i2c_dword(dev,
 830                                 VID_BLK_I2C_ADDRESS,
 831                                 OUT_CTRL1, FLD_VBIHACTRAW_EN,
 832                                 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
 833
 834         status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 835         if (value & 0x02) {
 836                 value |= (1 << 19);
 837                 status = vid_blk_write_word(dev, OUT_CTRL1, value);
 838         }
 839
 840         return status;
 841 }
 842
 843 /*
 844  * Handle any video-mode specific overrides that are different
 845  * on a per video standards basis after touching the MODE_CTRL
 846  * register which resets many values for autodetect
 847  */
 848 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
 849 {
 850         int status = 0;
 851
 852         cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
 853                      (unsigned int)dev->norm);
 854
 855         /* Change the DFE_CTRL3 bp_percent to fix flagging */
 856         status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
 857
 858         if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
 859                 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
 860
 861                 /* Move the close caption lines out of active video,
 862                    adjust the active video start point */
 863                 status = cx231xx_read_modify_write_i2c_dword(dev,
 864                                                         VID_BLK_I2C_ADDRESS,
 865                                                         VERT_TIM_CTRL,
 866                                                         FLD_VBLANK_CNT, 0x18);
 867                 status = cx231xx_read_modify_write_i2c_dword(dev,
 868                                                         VID_BLK_I2C_ADDRESS,
 869                                                         VERT_TIM_CTRL,
 870                                                         FLD_VACTIVE_CNT,
 871                                                         0x1E6000);
 872                 status = cx231xx_read_modify_write_i2c_dword(dev,
 873                                                         VID_BLK_I2C_ADDRESS,
 874                                                         VERT_TIM_CTRL,
 875                                                         FLD_V656BLANK_CNT,
 876                                                         0x1E000000);
 877
 878                 status = cx231xx_read_modify_write_i2c_dword(dev,
 879                                                         VID_BLK_I2C_ADDRESS,
 880                                                         HORIZ_TIM_CTRL,
 881                                                         FLD_HBLANK_CNT,
 882                                                         cx231xx_set_field
 883                                                         (FLD_HBLANK_CNT, 0x79));
 884         } else if (dev->norm & V4L2_STD_SECAM) {
 885                 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
 886                 status =  cx231xx_read_modify_write_i2c_dword(dev,
 887                                                         VID_BLK_I2C_ADDRESS,
 888                                                         VERT_TIM_CTRL,
 889                                                         FLD_VBLANK_CNT, 0x24);
 890                 /* Adjust the active video horizontal start point */
 891                 status = cx231xx_read_modify_write_i2c_dword(dev,
 892                                                         VID_BLK_I2C_ADDRESS,
 893                                                         HORIZ_TIM_CTRL,
 894                                                         FLD_HBLANK_CNT,
 895                                                         cx231xx_set_field
 896                                                         (FLD_HBLANK_CNT, 0x85));
 897         } else {
 898                 cx231xx_info("do_mode_ctrl_overrides PAL\n");
 899                 status = cx231xx_read_modify_write_i2c_dword(dev,
 900                                                         VID_BLK_I2C_ADDRESS,
 901                                                         VERT_TIM_CTRL,
 902                                                         FLD_VBLANK_CNT, 0x24);
 903                 /* Adjust the active video horizontal start point */
 904                 status = cx231xx_read_modify_write_i2c_dword(dev,
 905                                                         VID_BLK_I2C_ADDRESS,
 906                                                         HORIZ_TIM_CTRL,
 907                                                         FLD_HBLANK_CNT,
 908                                                         cx231xx_set_field
 909                                                         (FLD_HBLANK_CNT, 0x85));
 910         }
 911
 912         return status;
 913 }
 914
 915 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
 916 {
 917         int status = 0;
 918         enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
 919
 920         switch (INPUT(input)->amux) {
 921         case CX231XX_AMUX_VIDEO:
 922                 ainput = AUDIO_INPUT_TUNER_TV;
 923                 break;
 924         case CX231XX_AMUX_LINE_IN:
 925                 status = cx231xx_i2s_blk_set_audio_input(dev, input);
 926                 ainput = AUDIO_INPUT_LINE;
 927                 break;
 928         default:
 929                 break;
 930         }
 931
 932         status = cx231xx_set_audio_decoder_input(dev, ainput);
 933
 934         return status;
 935 }
 936
 937 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
 938                                     enum AUDIO_INPUT audio_input)
 939 {
 940         u32 dwval;
 941         int status;
 942         u8 gen_ctrl;
 943         u32 value = 0;
 944
 945         /* Put it in soft reset   */
 946         status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
 947         gen_ctrl |= 1;
 948         status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
 949
 950         switch (audio_input) {
 951         case AUDIO_INPUT_LINE:
 952                 /* setup AUD_IO control from Merlin paralle output */
 953                 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
 954                                           AUD_CHAN_SRC_PARALLEL);
 955                 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
 956
 957                 /* setup input to Merlin, SRC2 connect to AC97
 958                    bypass upsample-by-2, slave mode, sony mode, left justify
 959                    adr 091c, dat 01000000 */
 960                 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
 961
 962                 status = vid_blk_write_word(dev, AC97_CTL,
 963                                            (dwval | FLD_AC97_UP2X_BYPASS));
 964
 965                 /* select the parallel1 and SRC3 */
 966                 status = vid_blk_write_word(dev, BAND_OUT_SEL,
 967                                 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
 968                                 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
 969                                 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
 970
 971                 /* unmute all, AC97 in, independence mode
 972                    adr 08d0, data 0x00063073 */
 973                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
 974
 975                 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
 976                 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
 977                 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
 978                                            (dwval | FLD_PATH1_AVC_THRESHOLD));
 979
 980                 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
 981                 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
 982                 status = vid_blk_write_word(dev, PATH1_SC_CTL,
 983                                            (dwval | FLD_PATH1_SC_THRESHOLD));
 984                 break;
 985
 986         case AUDIO_INPUT_TUNER_TV:
 987         default:
 988
 989                 /* Setup SRC sources and clocks */
 990                 status = vid_blk_write_word(dev, BAND_OUT_SEL,
 991                         cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)         |
 992                         cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)        |
 993                         cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)         |
 994                         cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)        |
 995                         cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)         |
 996                         cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)        |
 997                         cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)         |
 998                         cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)        |
 999                         cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1000                         cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)        |
1001                         cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)         |
1002                         cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)   |
1003                         cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1004
1005                 /* Setup the AUD_IO control */
1006                 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1007                         cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)  |
1008                         cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)   |
1009                         cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1010                         cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1011                         cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1012
1013                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1014
1015                 /* setAudioStandard(_audio_standard); */
1016
1017                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1018                 switch (dev->model) {
1019                 case CX231XX_BOARD_CNXT_RDE_250:
1020                 case CX231XX_BOARD_CNXT_RDU_250:
1021                         status = cx231xx_read_modify_write_i2c_dword(dev,
1022                                         VID_BLK_I2C_ADDRESS,
1023                                         CHIP_CTRL,
1024                                         FLD_SIF_EN,
1025                                         cx231xx_set_field(FLD_SIF_EN, 1));
1026                         break;
1027                 default:
1028                         break;
1029                 }
1030                 break;
1031
1032         case AUDIO_INPUT_TUNER_FM:
1033                 /*  use SIF for FM radio
1034                    setupFM();
1035                    setAudioStandard(_audio_standard);
1036                  */
1037                 break;
1038
1039         case AUDIO_INPUT_MUTE:
1040                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1041                 break;
1042         }
1043
1044         /* Take it out of soft reset */
1045         status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1046         gen_ctrl &= ~1;
1047         status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1048
1049         return status;
1050 }
1051
1052 /* Set resolution of the video */
1053 int cx231xx_resolution_set(struct cx231xx *dev)
1054 {
1055         int width, height;
1056         u32 hscale, vscale;
1057         int status = 0;
1058
1059         width = dev->width;
1060         height = dev->height;
1061
1062         get_scale(dev, width, height, &hscale, &vscale);
1063
1064         /* set horzontal scale */
1065         status = vid_blk_write_word(dev, HSCALE_CTRL, hscale);
1066
1067         /* set vertical scale */
1068         status = vid_blk_write_word(dev, VSCALE_CTRL, vscale);
1069
1070         return status;
1071 }
1072
1073 /******************************************************************************
1074  *                    C H I P Specific  C O N T R O L   functions             *
1075  ******************************************************************************/
1076 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1077 {
1078         u32 value;
1079         int status = 0;
1080
1081         status = vid_blk_read_word(dev, PIN_CTRL, &value);
1082         value |= (~dev->board.ctl_pin_status_mask);
1083         status = vid_blk_write_word(dev, PIN_CTRL, value);
1084
1085         return status;
1086 }
1087
1088 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1089                                               u8 analog_or_digital)
1090 {
1091         int status = 0;
1092
1093         /* first set the direction to output */
1094         status = cx231xx_set_gpio_direction(dev,
1095                                             dev->board.
1096                                             agc_analog_digital_select_gpio, 1);
1097
1098         /* 0 - demod ; 1 - Analog mode */
1099         status = cx231xx_set_gpio_value(dev,
1100                                    dev->board.agc_analog_digital_select_gpio,
1101                                    analog_or_digital);
1102
1103         return status;
1104 }
1105
1106 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1107 {
1108         u8 value[4] = { 0, 0, 0, 0 };
1109         int status = 0;
1110
1111         cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1112
1113         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1114                                        PWR_CTL_EN, value, 4);
1115         if (status < 0)
1116                 return status;
1117
1118         if (I2CIndex == I2C_1) {
1119                 if (value[0] & I2C_DEMOD_EN) {
1120                         value[0] &= ~I2C_DEMOD_EN;
1121                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1122                                                    PWR_CTL_EN, value, 4);
1123                 }
1124         } else {
1125                 if (!(value[0] & I2C_DEMOD_EN)) {
1126                         value[0] |= I2C_DEMOD_EN;
1127                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1128                                                    PWR_CTL_EN, value, 4);
1129                 }
1130         }
1131
1132         return status;
1133
1134 }
1135
1136 /******************************************************************************
1137  *                 D I F - B L O C K    C O N T R O L   functions             *
1138  ******************************************************************************/
1139 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1140                                           u32 function_mode, u32 standard)
1141 {
1142         int status = 0;
1143
1144         if (mode == V4L2_TUNER_RADIO) {
1145                 /* C2HH */
1146                 /* lo if big signal */
1147                 status = cx231xx_reg_mask_write(dev,
1148                                 VID_BLK_I2C_ADDRESS, 32,
1149                                 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1150                 /* FUNC_MODE = DIF */
1151                 status = cx231xx_reg_mask_write(dev,
1152                                 VID_BLK_I2C_ADDRESS, 32,
1153                                 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1154                 /* IF_MODE */
1155                 status = cx231xx_reg_mask_write(dev,
1156                                 VID_BLK_I2C_ADDRESS, 32,
1157                                 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1158                 /* no inv */
1159                 status = cx231xx_reg_mask_write(dev,
1160                                 VID_BLK_I2C_ADDRESS, 32,
1161                                 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1162         } else if (standard != DIF_USE_BASEBAND) {
1163                 if (standard & V4L2_STD_MN) {
1164                         /* lo if big signal */
1165                         status = cx231xx_reg_mask_write(dev,
1166                                         VID_BLK_I2C_ADDRESS, 32,
1167                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1168                         /* FUNC_MODE = DIF */
1169                         status = cx231xx_reg_mask_write(dev,
1170                                         VID_BLK_I2C_ADDRESS, 32,
1171                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1172                                         function_mode);
1173                         /* IF_MODE */
1174                         status = cx231xx_reg_mask_write(dev,
1175                                         VID_BLK_I2C_ADDRESS, 32,
1176                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1177                         /* no inv */
1178                         status = cx231xx_reg_mask_write(dev,
1179                                         VID_BLK_I2C_ADDRESS, 32,
1180                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1181                         /* 0x124, AUD_CHAN1_SRC = 0x3 */
1182                         status = cx231xx_reg_mask_write(dev,
1183                                         VID_BLK_I2C_ADDRESS, 32,
1184                                         AUD_IO_CTRL, 0, 31, 0x00000003);
1185                 } else if ((standard == V4L2_STD_PAL_I) |
1186                         (standard & V4L2_STD_SECAM)) {
1187                         /* C2HH setup */
1188                         /* lo if big signal */
1189                         status = cx231xx_reg_mask_write(dev,
1190                                         VID_BLK_I2C_ADDRESS, 32,
1191                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1192                         /* FUNC_MODE = DIF */
1193                         status = cx231xx_reg_mask_write(dev,
1194                                         VID_BLK_I2C_ADDRESS, 32,
1195                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1196                                         function_mode);
1197                         /* IF_MODE */
1198                         status = cx231xx_reg_mask_write(dev,
1199                                         VID_BLK_I2C_ADDRESS, 32,
1200                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1201                         /* no inv */
1202                         status = cx231xx_reg_mask_write(dev,
1203                                         VID_BLK_I2C_ADDRESS, 32,
1204                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1205                 } else {
1206                         /* default PAL BG */
1207                         /* C2HH setup */
1208                         /* lo if big signal */
1209                         status = cx231xx_reg_mask_write(dev,
1210                                         VID_BLK_I2C_ADDRESS, 32,
1211                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1212                         /* FUNC_MODE = DIF */
1213                         status = cx231xx_reg_mask_write(dev,
1214                                         VID_BLK_I2C_ADDRESS, 32,
1215                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1216                                         function_mode);
1217                         /* IF_MODE */
1218                         status = cx231xx_reg_mask_write(dev,
1219                                         VID_BLK_I2C_ADDRESS, 32,
1220                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1221                         /* no inv */
1222                         status = cx231xx_reg_mask_write(dev,
1223                                         VID_BLK_I2C_ADDRESS, 32,
1224                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1225                 }
1226         }
1227
1228         return status;
1229 }
1230
1231 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1232 {
1233         int status = 0;
1234         u32 dif_misc_ctrl_value = 0;
1235         u32 func_mode = 0;
1236
1237         cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1238
1239         status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1240         if (standard != DIF_USE_BASEBAND)
1241                 dev->norm = standard;
1242
1243         switch (dev->model) {
1244         case CX231XX_BOARD_CNXT_RDE_250:
1245         case CX231XX_BOARD_CNXT_RDU_250:
1246                 func_mode = 0x03;
1247                 break;
1248         default:
1249                 func_mode = 0x01;
1250         }
1251
1252         status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1253                                                   func_mode, standard);
1254
1255         if (standard == DIF_USE_BASEBAND) {     /* base band */
1256                 /* There is a different SRC_PHASE_INC value
1257                    for baseband vs. DIF */
1258                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1259                 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1260                                                 &dif_misc_ctrl_value);
1261                 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1262                 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1263                                                 dif_misc_ctrl_value);
1264         } else if (standard & V4L2_STD_PAL_D) {
1265                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1266                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1267                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1268                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1269                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1270                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1271                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1272                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1273                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1274                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1275                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1276                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1277                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1278                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1279                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1280                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1281                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1282                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1283                                            0x26001700);
1284                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1285                                            DIF_AGC_RF_CURRENT, 0, 31,
1286                                            0x00002660);
1287                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1288                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1289                                            0x72500800);
1290                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1291                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1292                                            0x27000100);
1293                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1294                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1295                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1296                                            DIF_COMP_FLT_CTRL, 0, 31,
1297                                            0x00000000);
1298                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1299                                            DIF_SRC_PHASE_INC, 0, 31,
1300                                            0x1befbf06);
1301                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1302                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1303                                            0x000035e8);
1304                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1305                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1306                 /* Save the Spec Inversion value */
1307                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1308                 dif_misc_ctrl_value |= 0x3a023F11;
1309         } else if (standard & V4L2_STD_PAL_I) {
1310                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1311                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1312                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1313                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1314                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1315                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1316                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1317                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1318                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1319                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1320                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1321                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1322                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1323                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1324                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1325                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1326                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1327                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1328                                            0x26001700);
1329                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1330                                            DIF_AGC_RF_CURRENT, 0, 31,
1331                                            0x00002660);
1332                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1333                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1334                                            0x72500800);
1335                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1336                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1337                                            0x27000100);
1338                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1339                                            DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1340                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1341                                            DIF_COMP_FLT_CTRL, 0, 31,
1342                                            0x00000000);
1343                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1344                                            DIF_SRC_PHASE_INC, 0, 31,
1345                                            0x1befbf06);
1346                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1347                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1348                                            0x000035e8);
1349                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1350                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1351                 /* Save the Spec Inversion value */
1352                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1353                 dif_misc_ctrl_value |= 0x3a033F11;
1354         } else if (standard & V4L2_STD_PAL_M) {
1355                 /* improved Low Frequency Phase Noise */
1356                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1357                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1358                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1359                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1360                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1361                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1362                                                 0x26001700);
1363                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1364                                                 0x00002660);
1365                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1366                                                 0x72500800);
1367                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1368                                                 0x27000100);
1369                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1370                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1371                                                 0x009f50c1);
1372                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1373                                                 0x1befbf06);
1374                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1375                                                 0x000035e8);
1376                 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1377                                                 0x00000000);
1378                 /* Save the Spec Inversion value */
1379                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1380                 dif_misc_ctrl_value |= 0x3A0A3F10;
1381         } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1382                 /* improved Low Frequency Phase Noise */
1383                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1384                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1385                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1386                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1387                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1388                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1389                                                 0x26001700);
1390                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1391                                                 0x00002660);
1392                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1393                                                 0x72500800);
1394                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1395                                                 0x27000100);
1396                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1397                                                 0x012c405d);
1398                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1399                                                 0x009f50c1);
1400                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1401                                                 0x1befbf06);
1402                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1403                                                 0x000035e8);
1404                 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1405                                                 0x00000000);
1406                 /* Save the Spec Inversion value */
1407                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1408                 dif_misc_ctrl_value = 0x3A093F10;
1409         } else if (standard &
1410                   (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1411                    V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1412
1413                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1414                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1415                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1416                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1417                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1418                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1419                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1420                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1421                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1422                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1423                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1424                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1425                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1426                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1427                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1428                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1429                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1430                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1431                                            0x26001700);
1432                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1433                                            DIF_AGC_RF_CURRENT, 0, 31,
1434                                            0x00002660);
1435                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1436                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1437                                            0x27000100);
1438                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1439                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1440                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1441                                            DIF_COMP_FLT_CTRL, 0, 31,
1442                                            0x00000000);
1443                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1444                                            DIF_SRC_PHASE_INC, 0, 31,
1445                                            0x1befbf06);
1446                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1447                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1448                                            0x000035e8);
1449                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1450                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1451                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1452                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1453                                            0xf4000000);
1454
1455                 /* Save the Spec Inversion value */
1456                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1457                 dif_misc_ctrl_value |= 0x3a023F11;
1458         } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1459                 /* Is it SECAM_L1? */
1460                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1461                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1462                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1463                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1464                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1465                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1466                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1467                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1468                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1469                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1470                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1471                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1472                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1473                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1474                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1475                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1476                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1477                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1478                                            0x26001700);
1479                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1480                                            DIF_AGC_RF_CURRENT, 0, 31,
1481                                            0x00002660);
1482                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1483                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1484                                            0x27000100);
1485                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1486                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1487                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1488                                            DIF_COMP_FLT_CTRL, 0, 31,
1489                                            0x00000000);
1490                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1491                                            DIF_SRC_PHASE_INC, 0, 31,
1492                                            0x1befbf06);
1493                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1494                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1495                                            0x000035e8);
1496                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1497                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1498                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1499                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1500                                            0xf2560000);
1501
1502                 /* Save the Spec Inversion value */
1503                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1504                 dif_misc_ctrl_value |= 0x3a023F11;
1505
1506         } else if (standard & V4L2_STD_NTSC_M) {
1507                 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1508                    V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
1509
1510                 /* For NTSC the centre frequency of video coming out of
1511                    sidewinder is around 7.1MHz or 3.6MHz depending on the
1512                    spectral inversion. so for a non spectrally inverted channel
1513                    the pll freq word is 0x03420c49
1514                  */
1515
1516                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
1517                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
1518                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
1519                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1520                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
1521                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1522                                                 0x26001700);
1523                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1524                                                 0x00002660);
1525                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1526                                                 0x04000800);
1527                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1528                                                 0x27000100);
1529                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
1530
1531                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1532                                                 0x009f50c1);
1533                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1534                                                 0x1befbf06);
1535                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1536                                                 0x000035e8);
1537
1538                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
1539                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
1540                                                 0xC2262600);
1541                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
1542
1543                 /* Save the Spec Inversion value */
1544                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1545                 dif_misc_ctrl_value |= 0x3a003F10;
1546         } else {
1547                 /* default PAL BG */
1548                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1549                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1550                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1551                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1552                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1553                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1554                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1555                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1556                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1557                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1558                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1559                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1560                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1561                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1562                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1563                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1564                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1565                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1566                                            0x26001700);
1567                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1568                                            DIF_AGC_RF_CURRENT, 0, 31,
1569                                            0x00002660);
1570                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1571                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1572                                            0x72500800);
1573                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1574                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1575                                            0x27000100);
1576                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1577                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1578                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1579                                            DIF_COMP_FLT_CTRL, 0, 31,
1580                                            0x00A653A8);
1581                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1582                                            DIF_SRC_PHASE_INC, 0, 31,
1583                                            0x1befbf06);
1584                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1585                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1586                                            0x000035e8);
1587                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1588                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1589                 /* Save the Spec Inversion value */
1590                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1591                 dif_misc_ctrl_value |= 0x3a013F11;
1592         }
1593
1594         /* The AGC values should be the same for all standards,
1595            AUD_SRC_SEL[19] should always be disabled    */
1596         dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
1597
1598         /* It is still possible to get Set Standard calls even when we
1599            are in FM mode.
1600            This is done to override the value for FM. */
1601         if (dev->active_mode == V4L2_TUNER_RADIO)
1602                 dif_misc_ctrl_value = 0x7a080000;
1603
1604         /* Write the calculated value for misc ontrol register      */
1605         status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
1606
1607         return status;
1608 }
1609
1610 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
1611 {
1612         int status = 0;
1613         u32 dwval;
1614
1615         /* Set the RF and IF k_agc values to 3 */
1616         status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1617         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1618         dwval |= 0x33000000;
1619
1620         status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1621
1622         return status;
1623 }
1624
1625 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1626 {
1627         int status = 0;
1628         u32 dwval;
1629
1630         /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1631          * SECAM L/B/D standards */
1632         status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1633         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1634
1635         if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
1636                          V4L2_STD_SECAM_D))
1637                 dwval |= 0x88000000;
1638         else
1639                 dwval |= 0x44000000;
1640
1641         status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1642
1643         return status;
1644 }
1645
1646 /******************************************************************************
1647  *                  I 2 S - B L O C K    C O N T R O L   functions            *
1648  ******************************************************************************/
1649 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
1650 {
1651         int status = 0;
1652         u32 value;
1653
1654         status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1655                                        CH_PWR_CTRL1, 1, &value, 1);
1656         /* enables clock to delta-sigma and decimation filter */
1657         value |= 0x80;
1658         status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1659                                         CH_PWR_CTRL1, 1, value, 1);
1660         /* power up all channel */
1661         status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1662                                         CH_PWR_CTRL2, 1, 0x00, 1);
1663
1664         return status;
1665 }
1666
1667 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
1668                                         enum AV_MODE avmode)
1669 {
1670         int status = 0;
1671         u32 value = 0;
1672
1673         if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
1674                 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1675                                           CH_PWR_CTRL2, 1, &value, 1);
1676                 value |= 0xfe;
1677                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1678                                                 CH_PWR_CTRL2, 1, value, 1);
1679         } else {
1680                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1681                                                 CH_PWR_CTRL2, 1, 0x00, 1);
1682         }
1683
1684         return status;
1685 }
1686
1687 /* set i2s_blk for audio input types */
1688 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
1689 {
1690         int status = 0;
1691
1692         switch (audio_input) {
1693         case CX231XX_AMUX_LINE_IN:
1694                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1695                                                 CH_PWR_CTRL2, 1, 0x00, 1);
1696                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1697                                                 CH_PWR_CTRL1, 1, 0x80, 1);
1698                 break;
1699         case CX231XX_AMUX_VIDEO:
1700         default:
1701                 break;
1702         }
1703
1704         dev->ctl_ainput = audio_input;
1705
1706         return status;
1707 }
1708
1709 /******************************************************************************
1710  *                  P O W E R      C O N T R O L   functions                  *
1711  ******************************************************************************/
1712 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1713 {
1714         u8 value[4] = { 0, 0, 0, 0 };
1715         u32 tmp = 0;
1716         int status = 0;
1717
1718         if (dev->power_mode != mode)
1719                 dev->power_mode = mode;
1720         else {
1721                 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
1722                              mode);
1723                 return 0;
1724         }
1725
1726         cx231xx_info(" setPowerMode::mode = %d\n", mode);
1727
1728         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1729                                        4);
1730         if (status < 0)
1731                 return status;
1732
1733         tmp = *((u32 *) value);
1734
1735         switch (mode) {
1736         case POLARIS_AVMODE_ENXTERNAL_AV:
1737
1738                 tmp &= (~PWR_MODE_MASK);
1739
1740                 tmp |= PWR_AV_EN;
1741                 value[0] = (u8) tmp;
1742                 value[1] = (u8) (tmp >> 8);
1743                 value[2] = (u8) (tmp >> 16);
1744                 value[3] = (u8) (tmp >> 24);
1745                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1746                                                 PWR_CTL_EN, value, 4);
1747                 msleep(PWR_SLEEP_INTERVAL);
1748
1749                 tmp |= PWR_ISO_EN;
1750                 value[0] = (u8) tmp;
1751                 value[1] = (u8) (tmp >> 8);
1752                 value[2] = (u8) (tmp >> 16);
1753                 value[3] = (u8) (tmp >> 24);
1754                 status =
1755                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1756                                            value, 4);
1757                 msleep(PWR_SLEEP_INTERVAL);
1758
1759                 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
1760                 value[0] = (u8) tmp;
1761                 value[1] = (u8) (tmp >> 8);
1762                 value[2] = (u8) (tmp >> 16);
1763                 value[3] = (u8) (tmp >> 24);
1764                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1765                                                 PWR_CTL_EN, value, 4);
1766
1767                 /* reset state of xceive tuner */
1768                 dev->xc_fw_load_done = 0;
1769                 break;
1770
1771         case POLARIS_AVMODE_ANALOGT_TV:
1772
1773                 tmp &= (~PWR_DEMOD_EN);
1774                 tmp |= (I2C_DEMOD_EN);
1775                 value[0] = (u8) tmp;
1776                 value[1] = (u8) (tmp >> 8);
1777                 value[2] = (u8) (tmp >> 16);
1778                 value[3] = (u8) (tmp >> 24);
1779                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1780                                                 PWR_CTL_EN, value, 4);
1781                 msleep(PWR_SLEEP_INTERVAL);
1782
1783                 if (!(tmp & PWR_TUNER_EN)) {
1784                         tmp |= (PWR_TUNER_EN);
1785                         value[0] = (u8) tmp;
1786                         value[1] = (u8) (tmp >> 8);
1787                         value[2] = (u8) (tmp >> 16);
1788                         value[3] = (u8) (tmp >> 24);
1789                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1790                                                         PWR_CTL_EN, value, 4);
1791                         msleep(PWR_SLEEP_INTERVAL);
1792                 }
1793
1794                 if (!(tmp & PWR_AV_EN)) {
1795                         tmp |= PWR_AV_EN;
1796                         value[0] = (u8) tmp;
1797                         value[1] = (u8) (tmp >> 8);
1798                         value[2] = (u8) (tmp >> 16);
1799                         value[3] = (u8) (tmp >> 24);
1800                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1801                                                         PWR_CTL_EN, value, 4);
1802                         msleep(PWR_SLEEP_INTERVAL);
1803                 }
1804                 if (!(tmp & PWR_ISO_EN)) {
1805                         tmp |= PWR_ISO_EN;
1806                         value[0] = (u8) tmp;
1807                         value[1] = (u8) (tmp >> 8);
1808                         value[2] = (u8) (tmp >> 16);
1809                         value[3] = (u8) (tmp >> 24);
1810                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1811                                                         PWR_CTL_EN, value, 4);
1812                         msleep(PWR_SLEEP_INTERVAL);
1813                 }
1814
1815                 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
1816                         tmp |= POLARIS_AVMODE_ANALOGT_TV;
1817                         value[0] = (u8) tmp;
1818                         value[1] = (u8) (tmp >> 8);
1819                         value[2] = (u8) (tmp >> 16);
1820                         value[3] = (u8) (tmp >> 24);
1821                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1822                                                         PWR_CTL_EN, value, 4);
1823                         msleep(PWR_SLEEP_INTERVAL);
1824                 }
1825
1826                 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1827                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1828                         /* tuner path to channel 1 from port 3 */
1829                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1830
1831                         if (dev->cx231xx_reset_analog_tuner)
1832                                 dev->cx231xx_reset_analog_tuner(dev);
1833                 }
1834                 break;
1835
1836         case POLARIS_AVMODE_DIGITAL:
1837                 if (!(tmp & PWR_TUNER_EN)) {
1838                         tmp |= (PWR_TUNER_EN);
1839                         value[0] = (u8) tmp;
1840                         value[1] = (u8) (tmp >> 8);
1841                         value[2] = (u8) (tmp >> 16);
1842                         value[3] = (u8) (tmp >> 24);
1843                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1844                                                         PWR_CTL_EN, value, 4);
1845                         msleep(PWR_SLEEP_INTERVAL);
1846                 }
1847                 if (!(tmp & PWR_AV_EN)) {
1848                         tmp |= PWR_AV_EN;
1849                         value[0] = (u8) tmp;
1850                         value[1] = (u8) (tmp >> 8);
1851                         value[2] = (u8) (tmp >> 16);
1852                         value[3] = (u8) (tmp >> 24);
1853                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1854                                                         PWR_CTL_EN, value, 4);
1855                         msleep(PWR_SLEEP_INTERVAL);
1856                 }
1857                 if (!(tmp & PWR_ISO_EN)) {
1858                         tmp |= PWR_ISO_EN;
1859                         value[0] = (u8) tmp;
1860                         value[1] = (u8) (tmp >> 8);
1861                         value[2] = (u8) (tmp >> 16);
1862                         value[3] = (u8) (tmp >> 24);
1863                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1864                                                         PWR_CTL_EN, value, 4);
1865                         msleep(PWR_SLEEP_INTERVAL);
1866                 }
1867
1868                 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
1869                 value[0] = (u8) tmp;
1870                 value[1] = (u8) (tmp >> 8);
1871                 value[2] = (u8) (tmp >> 16);
1872                 value[3] = (u8) (tmp >> 24);
1873                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1874                                                 PWR_CTL_EN, value, 4);
1875                 msleep(PWR_SLEEP_INTERVAL);
1876
1877                 if (!(tmp & PWR_DEMOD_EN)) {
1878                         tmp |= PWR_DEMOD_EN;
1879                         value[0] = (u8) tmp;
1880                         value[1] = (u8) (tmp >> 8);
1881                         value[2] = (u8) (tmp >> 16);
1882                         value[3] = (u8) (tmp >> 24);
1883                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1884                                                         PWR_CTL_EN, value, 4);
1885                         msleep(PWR_SLEEP_INTERVAL);
1886                 }
1887
1888                 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1889                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1890                         /* tuner path to channel 1 from port 3 */
1891                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1892
1893                         if (dev->cx231xx_reset_analog_tuner)
1894                                 dev->cx231xx_reset_analog_tuner(dev);
1895                 }
1896                 break;
1897
1898         default:
1899                 break;
1900         }
1901
1902         msleep(PWR_SLEEP_INTERVAL);
1903
1904         /* For power saving, only enable Pwr_resetout_n
1905            when digital TV is selected. */
1906         if (mode == POLARIS_AVMODE_DIGITAL) {
1907                 tmp |= PWR_RESETOUT_EN;
1908                 value[0] = (u8) tmp;
1909                 value[1] = (u8) (tmp >> 8);
1910                 value[2] = (u8) (tmp >> 16);
1911                 value[3] = (u8) (tmp >> 24);
1912                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1913                                                 PWR_CTL_EN, value, 4);
1914                 msleep(PWR_SLEEP_INTERVAL);
1915         }
1916
1917         /* update power control for afe */
1918         status = cx231xx_afe_update_power_control(dev, mode);
1919
1920         /* update power control for i2s_blk */
1921         status = cx231xx_i2s_blk_update_power_control(dev, mode);
1922
1923         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1924                                        4);
1925         cx231xx_info(" The data of PWR_CTL_EN register 0x74"
1926                                  "=0x%0x,0x%0x,0x%0x,0x%0x\n",
1927                      value[0], value[1], value[2], value[3]);
1928
1929         return status;
1930 }
1931
1932 int cx231xx_power_suspend(struct cx231xx *dev)
1933 {
1934         u8 value[4] = { 0, 0, 0, 0 };
1935         u32 tmp = 0;
1936         int status = 0;
1937
1938         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1939                                        value, 4);
1940         if (status > 0)
1941                 return status;
1942
1943         tmp = *((u32 *) value);
1944         tmp &= (~PWR_MODE_MASK);
1945
1946         value[0] = (u8) tmp;
1947         value[1] = (u8) (tmp >> 8);
1948         value[2] = (u8) (tmp >> 16);
1949         value[3] = (u8) (tmp >> 24);
1950         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1951                                         value, 4);
1952
1953         return status;
1954 }
1955
1956 /******************************************************************************
1957  *                  S T R E A M    C O N T R O L   functions                  *
1958  ******************************************************************************/
1959 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
1960 {
1961         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1962         u32 tmp = 0;
1963         int status = 0;
1964
1965         cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
1966         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1967                                        value, 4);
1968         if (status < 0)
1969                 return status;
1970
1971         tmp = *((u32 *) value);
1972         tmp |= ep_mask;
1973         value[0] = (u8) tmp;
1974         value[1] = (u8) (tmp >> 8);
1975         value[2] = (u8) (tmp >> 16);
1976         value[3] = (u8) (tmp >> 24);
1977
1978         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1979                                         value, 4);
1980
1981         return status;
1982 }
1983
1984 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
1985 {
1986         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1987         u32 tmp = 0;
1988         int status = 0;
1989
1990         cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
1991         status =
1992             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
1993         if (status < 0)
1994                 return status;
1995
1996         tmp = *((u32 *) value);
1997         tmp &= (~ep_mask);
1998         value[0] = (u8) tmp;
1999         value[1] = (u8) (tmp >> 8);
2000         value[2] = (u8) (tmp >> 16);
2001         value[3] = (u8) (tmp >> 24);
2002
2003         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2004                                         value, 4);
2005
2006         return status;
2007 }
2008
2009 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2010 {
2011         int status = 0;
2012
2013         if (dev->udev->speed == USB_SPEED_HIGH) {
2014                 switch (media_type) {
2015                 case 81: /* audio */
2016                         cx231xx_info("%s: Audio enter HANC\n", __func__);
2017                         status =
2018                             cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2019                         break;
2020
2021                 case 2: /* vbi */
2022                         cx231xx_info("%s: set vanc registers\n", __func__);
2023                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2024                         break;
2025
2026                 case 3: /* sliced cc */
2027                         cx231xx_info("%s: set hanc registers\n", __func__);
2028                         status =
2029                             cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2030                         break;
2031
2032                 case 0: /* video */
2033                         cx231xx_info("%s: set video registers\n", __func__);
2034                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2035                         break;
2036
2037                 case 4: /* ts1 */
2038                         cx231xx_info("%s: set ts1 registers\n", __func__);
2039                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2040                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2041                         break;
2042                 case 6: /* ts1 parallel mode */
2043                         cx231xx_info("%s: set ts1 parrallel mode registers\n",
2044                                      __func__);
2045                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2046                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2047                         break;
2048                 }
2049         } else {
2050                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2051         }
2052
2053         return status;
2054 }
2055
2056 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2057 {
2058         int rc;
2059         u32 ep_mask = -1;
2060         struct pcb_config *pcb_config;
2061
2062         /* get EP for media type */
2063         pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2064
2065         if (pcb_config->config_num == 1) {
2066                 switch (media_type) {
2067                 case 0: /* Video */
2068                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2069                         break;
2070                 case 1: /* Audio */
2071                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2072                         break;
2073                 case 2: /* Vbi */
2074                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2075                         break;
2076                 case 3: /* Sliced_cc */
2077                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2078                         break;
2079                 case 4: /* ts1 */
2080                 case 6: /* ts1 parallel mode */
2081                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2082                         break;
2083                 case 5: /* ts2 */
2084                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2085                         break;
2086                 }
2087
2088         } else if (pcb_config->config_num > 1) {
2089                 switch (media_type) {
2090                 case 0: /* Video */
2091                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2092                         break;
2093                 case 1: /* Audio */
2094                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2095                         break;
2096                 case 2: /* Vbi */
2097                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2098                         break;
2099                 case 3: /* Sliced_cc */
2100                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2101                         break;
2102                 case 4: /* ts1 */
2103                 case 6: /* ts1 parallel mode */
2104                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2105                         break;
2106                 case 5: /* ts2 */
2107                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2108                         break;
2109                 }
2110
2111         }
2112
2113         if (start) {
2114                 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2115
2116                 if (rc < 0)
2117                         return rc;
2118
2119                 /* enable video capture */
2120                 if (ep_mask > 0)
2121                         rc = cx231xx_start_stream(dev, ep_mask);
2122         } else {
2123                 /* disable video capture */
2124                 if (ep_mask > 0)
2125                         rc = cx231xx_stop_stream(dev, ep_mask);
2126         }
2127
2128         if (dev->mode == CX231XX_ANALOG_MODE)
2129                 ;/* do any in Analog mode */
2130         else
2131                 ;/* do any in digital mode */
2132
2133         return rc;
2134 }
2135 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2136
2137 /*****************************************************************************
2138 *                   G P I O   B I T control functions                        *
2139 ******************************************************************************/
2140 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2141 {
2142         int status = 0;
2143
2144         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2145
2146         return status;
2147 }
2148
2149 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2150 {
2151         int status = 0;
2152
2153         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2154
2155         return status;
2156 }
2157
2158 /*
2159 * cx231xx_set_gpio_direction
2160 *      Sets the direction of the GPIO pin to input or output
2161 *
2162 * Parameters :
2163 *      pin_number : The GPIO Pin number to program the direction for
2164 *                   from 0 to 31
2165 *      pin_value : The Direction of the GPIO Pin under reference.
2166 *                      0 = Input direction
2167 *                      1 = Output direction
2168 */
2169 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2170                                int pin_number, int pin_value)
2171 {
2172         int status = 0;
2173         u32 value = 0;
2174
2175         /* Check for valid pin_number - if 32 , bail out */
2176         if (pin_number >= 32)
2177                 return -EINVAL;
2178
2179         /* input */
2180         if (pin_value == 0)
2181                 value = dev->gpio_dir & (~(1 << pin_number));   /* clear */
2182         else
2183                 value = dev->gpio_dir | (1 << pin_number);
2184
2185         status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2186
2187         /* cache the value for future */
2188         dev->gpio_dir = value;
2189
2190         return status;
2191 }
2192
2193 /*
2194 * cx231xx_set_gpio_value
2195 *      Sets the value of the GPIO pin to Logic high or low. The Pin under
2196 *      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2197 *
2198 * Parameters :
2199 *      pin_number : The GPIO Pin number to program the direction for
2200 *      pin_value : The value of the GPIO Pin under reference.
2201 *                      0 = set it to 0
2202 *                      1 = set it to 1
2203 */
2204 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2205 {
2206         int status = 0;
2207         u32 value = 0;
2208
2209         /* Check for valid pin_number - if 0xFF , bail out */
2210         if (pin_number >= 32)
2211                 return -EINVAL;
2212
2213         /* first do a sanity check - if the Pin is not output, make it output */
2214         if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2215                 /* It was in input mode */
2216                 value = dev->gpio_dir | (1 << pin_number);
2217                 dev->gpio_dir = value;
2218                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2219                                               (u8 *) &dev->gpio_val);
2220                 value = 0;
2221         }
2222
2223         if (pin_value == 0)
2224                 value = dev->gpio_val & (~(1 << pin_number));
2225         else
2226                 value = dev->gpio_val | (1 << pin_number);
2227
2228         /* store the value */
2229         dev->gpio_val = value;
2230
2231         /* toggle bit0 of GP_IO */
2232         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2233
2234         return status;
2235 }
2236
2237 /*****************************************************************************
2238 *                      G P I O I2C related functions                         *
2239 ******************************************************************************/
2240 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2241 {
2242         int status = 0;
2243
2244         /* set SCL to output 1 ; set SDA to output 1 */
2245         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2246         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2247         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2248         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2249
2250         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2251         if (status < 0)
2252                 return -EINVAL;
2253
2254         /* set SCL to output 1; set SDA to output 0 */
2255         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2256         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2257
2258         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2259         if (status < 0)
2260                 return -EINVAL;
2261
2262         /* set SCL to output 0; set SDA to output 0      */
2263         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2264         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2265
2266         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2267         if (status < 0)
2268                 return -EINVAL;
2269
2270         return status;
2271 }
2272
2273 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2274 {
2275         int status = 0;
2276
2277         /* set SCL to output 0; set SDA to output 0      */
2278         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2279         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2280
2281         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2282         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2283
2284         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2285         if (status < 0)
2286                 return -EINVAL;
2287
2288         /* set SCL to output 1; set SDA to output 0      */
2289         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2290         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2291
2292         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2293         if (status < 0)
2294                 return -EINVAL;
2295
2296         /* set SCL to input ,release SCL cable control
2297            set SDA to input ,release SDA cable control */
2298         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2299         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2300
2301         status =
2302             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2303         if (status < 0)
2304                 return -EINVAL;
2305
2306         return status;
2307 }
2308
2309 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2310 {
2311         int status = 0;
2312         u8 i;
2313
2314         /* set SCL to output ; set SDA to output */
2315         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2316         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2317
2318         for (i = 0; i < 8; i++) {
2319                 if (((data << i) & 0x80) == 0) {
2320                         /* set SCL to output 0; set SDA to output 0     */
2321                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2322                         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2323                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2324                                                       (u8 *)&dev->gpio_val);
2325
2326                         /* set SCL to output 1; set SDA to output 0     */
2327                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2328                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2329                                                       (u8 *)&dev->gpio_val);
2330
2331                         /* set SCL to output 0; set SDA to output 0     */
2332                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2333                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2334                                                       (u8 *)&dev->gpio_val);
2335                 } else {
2336                         /* set SCL to output 0; set SDA to output 1     */
2337                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2338                         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2339                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2340                                                       (u8 *)&dev->gpio_val);
2341
2342                         /* set SCL to output 1; set SDA to output 1     */
2343                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2344                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2345                                                       (u8 *)&dev->gpio_val);
2346
2347                         /* set SCL to output 0; set SDA to output 1     */
2348                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2349                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2350                                                       (u8 *)&dev->gpio_val);
2351                 }
2352         }
2353         return status;
2354 }
2355
2356 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf)
2357 {
2358         u8 value = 0;
2359         int status = 0;
2360         u32 gpio_logic_value = 0;
2361         u8 i;
2362
2363         /* read byte */
2364         for (i = 0; i < 8; i++) {       /* send write I2c addr */
2365
2366                 /* set SCL to output 0; set SDA to input */
2367                 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2368                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2369                                               (u8 *)&dev->gpio_val);
2370
2371                 /* set SCL to output 1; set SDA to input */
2372                 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2373                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2374                                               (u8 *)&dev->gpio_val);
2375
2376                 /* get SDA data bit */
2377                 gpio_logic_value = dev->gpio_val;
2378                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2379                                               (u8 *)&dev->gpio_val);
2380                 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2381                         value |= (1 << (8 - i - 1));
2382
2383                 dev->gpio_val = gpio_logic_value;
2384         }
2385
2386         /* set SCL to output 0,finish the read latest SCL signal.
2387            !!!set SDA to input, never to modify SDA direction at
2388            the same times */
2389         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2390         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2391
2392         /* store the value */
2393         *buf = value & 0xff;
2394
2395         return status;
2396 }
2397
2398 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2399 {
2400         int status = 0;
2401         u32 gpio_logic_value = 0;
2402         int nCnt = 10;
2403         int nInit = nCnt;
2404
2405         /* clock stretch; set SCL to input; set SDA to input;
2406            get SCL value till SCL = 1 */
2407         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2408         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2409
2410         gpio_logic_value = dev->gpio_val;
2411         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2412
2413         do {
2414                 msleep(2);
2415                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2416                                               (u8 *)&dev->gpio_val);
2417                 nCnt--;
2418         } while (((dev->gpio_val &
2419                           (1 << dev->board.tuner_scl_gpio)) == 0) &&
2420                          (nCnt > 0));
2421
2422         if (nCnt == 0)
2423                 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2424                              nInit * 10);
2425
2426         /* readAck
2427            throuth clock stretch ,slave has given a SCL signal,
2428            so the SDA data can be directly read.  */
2429         status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2430
2431         if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2432                 dev->gpio_val = gpio_logic_value;
2433                 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2434                 status = 0;
2435         } else {
2436                 dev->gpio_val = gpio_logic_value;
2437                 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2438         }
2439
2440         /* read SDA end, set the SCL to output 0, after this operation,
2441            SDA direction can be changed. */
2442         dev->gpio_val = gpio_logic_value;
2443         dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2444         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2445         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2446
2447         return status;
2448 }
2449
2450 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2451 {
2452         int status = 0;
2453
2454         /* set SDA to ouput */
2455         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2456         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2457
2458         /* set SCL = 0 (output); set SDA = 0 (output) */
2459         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2460         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2461         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2462
2463         /* set SCL = 1 (output); set SDA = 0 (output) */
2464         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2465         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2466
2467         /* set SCL = 0 (output); set SDA = 0 (output) */
2468         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2469         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2470
2471         /* set SDA to input,and then the slave will read data from SDA. */
2472         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2473         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2474
2475         return status;
2476 }
2477
2478 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2479 {
2480         int status = 0;
2481
2482         /* set scl to output ; set sda to input */
2483         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2484         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2485         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2486
2487         /* set scl to output 0; set sda to input */
2488         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2489         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2490
2491         /* set scl to output 1; set sda to input */
2492         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2493         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2494
2495         return status;
2496 }
2497
2498 /*****************************************************************************
2499 *                      G P I O I2C related functions                         *
2500 ******************************************************************************/
2501 /* cx231xx_gpio_i2c_read
2502  * Function to read data from gpio based I2C interface
2503  */
2504 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2505 {
2506         int status = 0;
2507         int i = 0;
2508
2509         /* get the lock */
2510         mutex_lock(&dev->gpio_i2c_lock);
2511
2512         /* start */
2513         status = cx231xx_gpio_i2c_start(dev);
2514
2515         /* write dev_addr */
2516         status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
2517
2518         /* readAck */
2519         status = cx231xx_gpio_i2c_read_ack(dev);
2520
2521         /* read data */
2522         for (i = 0; i < len; i++) {
2523                 /* read data */
2524                 buf[i] = 0;
2525                 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
2526
2527                 if ((i + 1) != len) {
2528                         /* only do write ack if we more length */
2529                         status = cx231xx_gpio_i2c_write_ack(dev);
2530                 }
2531         }
2532
2533         /* write NAK - inform reads are complete */
2534         status = cx231xx_gpio_i2c_write_nak(dev);
2535
2536         /* write end */
2537         status = cx231xx_gpio_i2c_end(dev);
2538
2539         /* release the lock */
2540         mutex_unlock(&dev->gpio_i2c_lock);
2541
2542         return status;
2543 }
2544
2545 /* cx231xx_gpio_i2c_write
2546  * Function to write data to gpio based I2C interface
2547  */
2548 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2549 {
2550         int status = 0;
2551         int i = 0;
2552
2553         /* get the lock */
2554         mutex_lock(&dev->gpio_i2c_lock);
2555
2556         /* start */
2557         status = cx231xx_gpio_i2c_start(dev);
2558
2559         /* write dev_addr */
2560         status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
2561
2562         /* read Ack */
2563         status = cx231xx_gpio_i2c_read_ack(dev);
2564
2565         for (i = 0; i < len; i++) {
2566                 /* Write data */
2567                 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
2568
2569                 /* read Ack */
2570                 status = cx231xx_gpio_i2c_read_ack(dev);
2571         }
2572
2573         /* write End */
2574         status = cx231xx_gpio_i2c_end(dev);
2575
2576         /* release the lock */
2577         mutex_unlock(&dev->gpio_i2c_lock);
2578
2579         return 0;
2580 }