drivers/media/dvb/ngene/ngene-core.c

   1 /*
   2  * ngene.c: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
   7  *                         Modifications for new nGene firmware,
   8  *                         support for EEPROM-copying,
   9  *                         support for new dual DVB-S2 card prototype
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * version 2 only, as published by the Free Software Foundation.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  26  * 02110-1301, USA
  27  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/init.h>
  32 #include <linux/delay.h>
  33 #include <linux/poll.h>
  34 #include <linux/io.h>
  35 #include <asm/div64.h>
  36 #include <linux/pci.h>
  37 #include <linux/pci_ids.h>
  38 #include <linux/smp_lock.h>
  39 #include <linux/timer.h>
  40 #include <linux/byteorder/generic.h>
  41 #include <linux/firmware.h>
  42 #include <linux/vmalloc.h>
  43
  44 #include "ngene.h"
  45
  46 #include "stv6110x.h"
  47 #include "stv090x.h"
  48 #include "lnbh24.h"
  49
  50 static int one_adapter = 1;
  51 module_param(one_adapter, int, 0444);
  52 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
  53
  54
  55 static int debug;
  56 module_param(debug, int, 0444);
  57 MODULE_PARM_DESC(debug, "Print debugging information.");
  58
  59 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  60
  61 #define COMMAND_TIMEOUT_WORKAROUND
  62
  63 #define dprintk if (debug) printk
  64
  65 #define DEVICE_NAME "ngene"
  66
  67 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  68 #define ngwritel(dat, adr)         writel((dat), (char *)(dev->iomem + (adr)))
  69 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  70 #define ngreadl(adr)               readl(dev->iomem + (adr))
  71 #define ngreadb(adr)               readb(dev->iomem + (adr))
  72 #define ngcpyto(adr, src, count)   memcpy_toio((char *) \
  73                                    (dev->iomem + (adr)), (src), (count))
  74 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
  75                                    (dev->iomem + (adr)), (count))
  76
  77 /****************************************************************************/
  78 /* nGene interrupt handler **************************************************/
  79 /****************************************************************************/
  80
  81 static void event_tasklet(unsigned long data)
  82 {
  83         struct ngene *dev = (struct ngene *)data;
  84
  85         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
  86                 struct EVENT_BUFFER Event =
  87                         dev->EventQueue[dev->EventQueueReadIndex];
  88                 dev->EventQueueReadIndex =
  89                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
  90
  91                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
  92                         dev->TxEventNotify(dev, Event.TimeStamp);
  93                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
  94                         dev->RxEventNotify(dev, Event.TimeStamp,
  95                                            Event.RXCharacter);
  96         }
  97 }
  98
  99 static void demux_tasklet(unsigned long data)
 100 {
 101         struct ngene_channel *chan = (struct ngene_channel *)data;
 102         struct SBufferHeader *Cur = chan->nextBuffer;
 103
 104         spin_lock_irq(&chan->state_lock);
 105
 106         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
 107                 if (chan->mode & NGENE_IO_TSOUT) {
 108                         u32 Flags = chan->DataFormatFlags;
 109                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
 110                                 Flags |= BEF_OVERFLOW;
 111                         if (chan->pBufferExchange) {
 112                                 if (!chan->pBufferExchange(chan,
 113                                                            Cur->Buffer1,
 114                                                            chan->Capture1Length,
 115                                                            Cur->ngeneBuffer.SR.
 116                                                            Clock, Flags)) {
 117                                         /*
 118                                            We didn't get data
 119                                            Clear in service flag to make sure we
 120                                            get called on next interrupt again.
 121                                            leave fill/empty (0x80) flag alone
 122                                            to avoid hardware running out of
 123                                            buffers during startup, we hold only
 124                                            in run state ( the source may be late
 125                                            delivering data )
 126                                         */
 127
 128                                         if (chan->HWState == HWSTATE_RUN) {
 129                                                 Cur->ngeneBuffer.SR.Flags &=
 130                                                         ~0x40;
 131                                                 break;
 132                                                 /* Stop proccessing stream */
 133                                         }
 134                                 } else {
 135                                         /* We got a valid buffer,
 136                                            so switch to run state */
 137                                         chan->HWState = HWSTATE_RUN;
 138                                 }
 139                         } else {
 140                                 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
 141                                 if (chan->HWState == HWSTATE_RUN) {
 142                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
 143                                         break;  /* Stop proccessing stream */
 144                                 }
 145                         }
 146                         if (chan->AudioDTOUpdated) {
 147                                 printk(KERN_INFO DEVICE_NAME
 148                                        ": Update AudioDTO = %d\n",
 149                                        chan->AudioDTOValue);
 150                                 Cur->ngeneBuffer.SR.DTOUpdate =
 151                                         chan->AudioDTOValue;
 152                                 chan->AudioDTOUpdated = 0;
 153                         }
 154                 } else {
 155                         if (chan->HWState == HWSTATE_RUN) {
 156                                 u32 Flags = 0;
 157                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
 158                                         Flags |= BEF_EVEN_FIELD;
 159                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
 160                                         Flags |= BEF_OVERFLOW;
 161                                 if (chan->pBufferExchange)
 162                                         chan->pBufferExchange(chan,
 163                                                               Cur->Buffer1,
 164                                                               chan->
 165                                                               Capture1Length,
 166                                                               Cur->ngeneBuffer.
 167                                                               SR.Clock, Flags);
 168                                 if (chan->pBufferExchange2)
 169                                         chan->pBufferExchange2(chan,
 170                                                                Cur->Buffer2,
 171                                                                chan->
 172                                                                Capture2Length,
 173                                                                Cur->ngeneBuffer.
 174                                                                SR.Clock, Flags);
 175                         } else if (chan->HWState != HWSTATE_STOP)
 176                                 chan->HWState = HWSTATE_RUN;
 177                 }
 178                 Cur->ngeneBuffer.SR.Flags = 0x00;
 179                 Cur = Cur->Next;
 180         }
 181         chan->nextBuffer = Cur;
 182
 183         spin_unlock_irq(&chan->state_lock);
 184 }
 185
 186 static irqreturn_t irq_handler(int irq, void *dev_id)
 187 {
 188         struct ngene *dev = (struct ngene *)dev_id;
 189         u32 icounts = 0;
 190         irqreturn_t rc = IRQ_NONE;
 191         u32 i = MAX_STREAM;
 192         u8 *tmpCmdDoneByte;
 193
 194         if (dev->BootFirmware) {
 195                 icounts = ngreadl(NGENE_INT_COUNTS);
 196                 if (icounts != dev->icounts) {
 197                         ngwritel(0, FORCE_NMI);
 198                         dev->cmd_done = 1;
 199                         wake_up(&dev->cmd_wq);
 200                         dev->icounts = icounts;
 201                         rc = IRQ_HANDLED;
 202                 }
 203                 return rc;
 204         }
 205
 206         ngwritel(0, FORCE_NMI);
 207
 208         spin_lock(&dev->cmd_lock);
 209         tmpCmdDoneByte = dev->CmdDoneByte;
 210         if (tmpCmdDoneByte &&
 211             (*tmpCmdDoneByte ||
 212             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
 213                 dev->CmdDoneByte = NULL;
 214                 dev->cmd_done = 1;
 215                 wake_up(&dev->cmd_wq);
 216                 rc = IRQ_HANDLED;
 217         }
 218         spin_unlock(&dev->cmd_lock);
 219
 220         if (dev->EventBuffer->EventStatus & 0x80) {
 221                 u8 nextWriteIndex =
 222                         (dev->EventQueueWriteIndex + 1) &
 223                         (EVENT_QUEUE_SIZE - 1);
 224                 if (nextWriteIndex != dev->EventQueueReadIndex) {
 225                         dev->EventQueue[dev->EventQueueWriteIndex] =
 226                                 *(dev->EventBuffer);
 227                         dev->EventQueueWriteIndex = nextWriteIndex;
 228                 } else {
 229                         printk(KERN_ERR DEVICE_NAME ": event overflow\n");
 230                         dev->EventQueueOverflowCount += 1;
 231                         dev->EventQueueOverflowFlag = 1;
 232                 }
 233                 dev->EventBuffer->EventStatus &= ~0x80;
 234                 tasklet_schedule(&dev->event_tasklet);
 235                 rc = IRQ_HANDLED;
 236         }
 237
 238         while (i > 0) {
 239                 i--;
 240                 spin_lock(&dev->channel[i].state_lock);
 241                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
 242                 if (dev->channel[i].nextBuffer) {
 243                         if ((dev->channel[i].nextBuffer->
 244                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
 245                                 dev->channel[i].nextBuffer->
 246                                         ngeneBuffer.SR.Flags |= 0x40;
 247                                 tasklet_schedule(
 248                                         &dev->channel[i].demux_tasklet);
 249                                 rc = IRQ_HANDLED;
 250                         }
 251                 }
 252                 spin_unlock(&dev->channel[i].state_lock);
 253         }
 254
 255         /* Request might have been processed by a previous call. */
 256         return IRQ_HANDLED;
 257 }
 258
 259 /****************************************************************************/
 260 /* nGene command interface **************************************************/
 261 /****************************************************************************/
 262
 263 static void dump_command_io(struct ngene *dev)
 264 {
 265         u8 buf[8], *b;
 266
 267         ngcpyfrom(buf, HOST_TO_NGENE, 8);
 268         printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 269                 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
 270                 buf[4], buf[5], buf[6], buf[7]);
 271
 272         ngcpyfrom(buf, NGENE_TO_HOST, 8);
 273         printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 274                 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
 275                 buf[4], buf[5], buf[6], buf[7]);
 276
 277         b = dev->hosttongene;
 278         printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 279                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 280
 281         b = dev->ngenetohost;
 282         printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 283                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 284 }
 285
 286 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
 287 {
 288         int ret;
 289         u8 *tmpCmdDoneByte;
 290
 291         dev->cmd_done = 0;
 292
 293         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
 294                 dev->BootFirmware = 1;
 295                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
 296                 ngwritel(0, NGENE_COMMAND);
 297                 ngwritel(0, NGENE_COMMAND_HI);
 298                 ngwritel(0, NGENE_STATUS);
 299                 ngwritel(0, NGENE_STATUS_HI);
 300                 ngwritel(0, NGENE_EVENT);
 301                 ngwritel(0, NGENE_EVENT_HI);
 302         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
 303                 u64 fwio = dev->PAFWInterfaceBuffer;
 304
 305                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
 306                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
 307                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
 308                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
 309                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
 310                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
 311         }
 312
 313         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
 314
 315         if (dev->BootFirmware)
 316                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
 317
 318         spin_lock_irq(&dev->cmd_lock);
 319         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
 320         if (!com->out_len)
 321                 tmpCmdDoneByte++;
 322         *tmpCmdDoneByte = 0;
 323         dev->ngenetohost[0] = 0;
 324         dev->ngenetohost[1] = 0;
 325         dev->CmdDoneByte = tmpCmdDoneByte;
 326         spin_unlock_irq(&dev->cmd_lock);
 327
 328         /* Notify 8051. */
 329         ngwritel(1, FORCE_INT);
 330
 331         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
 332         if (!ret) {
 333                 /*ngwritel(0, FORCE_NMI);*/
 334
 335                 printk(KERN_ERR DEVICE_NAME
 336                        ": Command timeout cmd=%02x prev=%02x\n",
 337                        com->cmd.hdr.Opcode, dev->prev_cmd);
 338                 dump_command_io(dev);
 339                 return -1;
 340         }
 341         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
 342                 dev->BootFirmware = 0;
 343
 344         dev->prev_cmd = com->cmd.hdr.Opcode;
 345
 346         if (!com->out_len)
 347                 return 0;
 348
 349         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
 350
 351         return 0;
 352 }
 353
 354 static int ngene_command(struct ngene *dev, struct ngene_command *com)
 355 {
 356         int result;
 357
 358         down(&dev->cmd_mutex);
 359         result = ngene_command_mutex(dev, com);
 360         up(&dev->cmd_mutex);
 361         return result;
 362 }
 363
 364
 365 static int ngene_command_i2c_read(struct ngene *dev, u8 adr,
 366                            u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
 367 {
 368         struct ngene_command com;
 369
 370         com.cmd.hdr.Opcode = CMD_I2C_READ;
 371         com.cmd.hdr.Length = outlen + 3;
 372         com.cmd.I2CRead.Device = adr << 1;
 373         memcpy(com.cmd.I2CRead.Data, out, outlen);
 374         com.cmd.I2CRead.Data[outlen] = inlen;
 375         com.cmd.I2CRead.Data[outlen + 1] = 0;
 376         com.in_len = outlen + 3;
 377         com.out_len = inlen + 1;
 378
 379         if (ngene_command(dev, &com) < 0)
 380                 return -EIO;
 381
 382         if ((com.cmd.raw8[0] >> 1) != adr)
 383                 return -EIO;
 384
 385         if (flag)
 386                 memcpy(in, com.cmd.raw8, inlen + 1);
 387         else
 388                 memcpy(in, com.cmd.raw8 + 1, inlen);
 389         return 0;
 390 }
 391
 392 static int ngene_command_i2c_write(struct ngene *dev, u8 adr,
 393                                    u8 *out, u8 outlen)
 394 {
 395         struct ngene_command com;
 396
 397
 398         com.cmd.hdr.Opcode = CMD_I2C_WRITE;
 399         com.cmd.hdr.Length = outlen + 1;
 400         com.cmd.I2CRead.Device = adr << 1;
 401         memcpy(com.cmd.I2CRead.Data, out, outlen);
 402         com.in_len = outlen + 1;
 403         com.out_len = 1;
 404
 405         if (ngene_command(dev, &com) < 0)
 406                 return -EIO;
 407
 408         if (com.cmd.raw8[0] == 1)
 409                 return -EIO;
 410
 411         return 0;
 412 }
 413
 414 static int ngene_command_load_firmware(struct ngene *dev,
 415                                        u8 *ngene_fw, u32 size)
 416 {
 417 #define FIRSTCHUNK (1024)
 418         u32 cleft;
 419         struct ngene_command com;
 420
 421         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
 422         com.cmd.hdr.Length = 0;
 423         com.in_len = 0;
 424         com.out_len = 0;
 425
 426         ngene_command(dev, &com);
 427
 428         cleft = (size + 3) & ~3;
 429         if (cleft > FIRSTCHUNK) {
 430                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
 431                         cleft - FIRSTCHUNK);
 432                 cleft = FIRSTCHUNK;
 433         }
 434         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
 435
 436         memset(&com, 0, sizeof(struct ngene_command));
 437         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
 438         com.cmd.hdr.Length = 4;
 439         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
 440         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
 441         com.in_len = 4;
 442         com.out_len = 0;
 443
 444         return ngene_command(dev, &com);
 445 }
 446
 447
 448 static int ngene_command_config_buf(struct ngene *dev, u8 config)
 449 {
 450         struct ngene_command com;
 451
 452         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
 453         com.cmd.hdr.Length = 1;
 454         com.cmd.ConfigureBuffers.config = config;
 455         com.in_len = 1;
 456         com.out_len = 0;
 457
 458         if (ngene_command(dev, &com) < 0)
 459                 return -EIO;
 460         return 0;
 461 }
 462
 463 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
 464 {
 465         struct ngene_command com;
 466
 467         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
 468         com.cmd.hdr.Length = 6;
 469         memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
 470         com.in_len = 6;
 471         com.out_len = 0;
 472
 473         if (ngene_command(dev, &com) < 0)
 474                 return -EIO;
 475
 476         return 0;
 477 }
 478
 479 static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
 480 {
 481         struct ngene_command com;
 482
 483         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
 484         com.cmd.hdr.Length = 1;
 485         com.cmd.SetGpioPin.select = select | (level << 7);
 486         com.in_len = 1;
 487         com.out_len = 0;
 488
 489         return ngene_command(dev, &com);
 490 }
 491
 492
 493 /*
 494  02000640 is sample on rising edge.
 495  02000740 is sample on falling edge.
 496  02000040 is ignore "valid" signal
 497
 498  0: FD_CTL1 Bit 7,6 must be 0,1
 499     7   disable(fw controlled)
 500     6   0-AUX,1-TS
 501     5   0-par,1-ser
 502     4   0-lsb/1-msb
 503     3,2 reserved
 504     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
 505  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
 506  2: FD_STA is read-only. 0-sync
 507  3: FD_INSYNC is number of 47s to trigger "in sync".
 508  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
 509  5: FD_MAXBYTE1 is low-order of bytes per packet.
 510  6: FD_MAXBYTE2 is high-order of bytes per packet.
 511  7: Top byte is unused.
 512 */
 513
 514 /****************************************************************************/
 515
 516 static u8 TSFeatureDecoderSetup[8 * 4] = {
 517         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
 518         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
 519         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
 520         0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
 521 };
 522
 523 /* Set NGENE I2S Config to 16 bit packed */
 524 static u8 I2SConfiguration[] = {
 525         0x00, 0x10, 0x00, 0x00,
 526         0x80, 0x10, 0x00, 0x00,
 527 };
 528
 529 static u8 SPDIFConfiguration[10] = {
 530         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 531 };
 532
 533 /* Set NGENE I2S Config to transport stream compatible mode */
 534
 535 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
 536
 537 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
 538
 539 static u8 ITUDecoderSetup[4][16] = {
 540         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
 541          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
 542         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
 543          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 544         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
 545          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 546         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
 547          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 548 };
 549
 550 /*
 551  * 50 48 60 gleich
 552  * 27p50 9f 00 22 80 42 69 18 ...
 553  * 27p60 93 00 22 80 82 69 1c ...
 554  */
 555
 556 /* Maxbyte to 1144 (for raw data) */
 557 static u8 ITUFeatureDecoderSetup[8] = {
 558         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
 559 };
 560
 561 static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
 562 {
 563         u32 *ptr = Buffer;
 564
 565         memset(Buffer, 0xff, Length);
 566         while (Length > 0) {
 567                 if (Flags & DF_SWAP32)
 568                         *ptr = 0x471FFF10;
 569                 else
 570                         *ptr = 0x10FF1F47;
 571                 ptr += (188 / 4);
 572                 Length -= 188;
 573         }
 574 }
 575
 576
 577 static void flush_buffers(struct ngene_channel *chan)
 578 {
 579         u8 val;
 580
 581         do {
 582                 msleep(1);
 583                 spin_lock_irq(&chan->state_lock);
 584                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
 585                 spin_unlock_irq(&chan->state_lock);
 586         } while (val);
 587 }
 588
 589 static void clear_buffers(struct ngene_channel *chan)
 590 {
 591         struct SBufferHeader *Cur = chan->nextBuffer;
 592
 593         do {
 594                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
 595                 if (chan->mode & NGENE_IO_TSOUT)
 596                         FillTSBuffer(Cur->Buffer1,
 597                                      chan->Capture1Length,
 598                                      chan->DataFormatFlags);
 599                 Cur = Cur->Next;
 600         } while (Cur != chan->nextBuffer);
 601
 602         if (chan->mode & NGENE_IO_TSOUT) {
 603                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
 604                         chan->AudioDTOValue;
 605                 chan->AudioDTOUpdated = 0;
 606
 607                 Cur = chan->TSIdleBuffer.Head;
 608
 609                 do {
 610                         memset(&Cur->ngeneBuffer.SR, 0,
 611                                sizeof(Cur->ngeneBuffer.SR));
 612                         FillTSBuffer(Cur->Buffer1,
 613                                      chan->Capture1Length,
 614                                      chan->DataFormatFlags);
 615                         Cur = Cur->Next;
 616                 } while (Cur != chan->TSIdleBuffer.Head);
 617         }
 618 }
 619
 620 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
 621                                         u8 control, u8 mode, u8 flags)
 622 {
 623         struct ngene_channel *chan = &dev->channel[stream];
 624         struct ngene_command com;
 625         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
 626         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
 627         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
 628         u16 BsSDO = 0x9B00;
 629
 630         /* down(&dev->stream_mutex); */
 631         while (down_trylock(&dev->stream_mutex)) {
 632                 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
 633                 msleep(1);
 634         }
 635         memset(&com, 0, sizeof(com));
 636         com.cmd.hdr.Opcode = CMD_CONTROL;
 637         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
 638         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
 639         if (chan->mode & NGENE_IO_TSOUT)
 640                 com.cmd.StreamControl.Stream |= 0x07;
 641         com.cmd.StreamControl.Control = control |
 642                 (flags & SFLAG_ORDER_LUMA_CHROMA);
 643         com.cmd.StreamControl.Mode = mode;
 644         com.in_len = sizeof(struct FW_STREAM_CONTROL);
 645         com.out_len = 0;
 646
 647         dprintk(KERN_INFO DEVICE_NAME
 648                 ": Stream=%02x, Control=%02x, Mode=%02x\n",
 649                 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
 650                 com.cmd.StreamControl.Mode);
 651
 652         chan->Mode = mode;
 653
 654         if (!(control & 0x80)) {
 655                 spin_lock_irq(&chan->state_lock);
 656                 if (chan->State == KSSTATE_RUN) {
 657                         chan->State = KSSTATE_ACQUIRE;
 658                         chan->HWState = HWSTATE_STOP;
 659                         spin_unlock_irq(&chan->state_lock);
 660                         if (ngene_command(dev, &com) < 0) {
 661                                 up(&dev->stream_mutex);
 662                                 return -1;
 663                         }
 664                         /* clear_buffers(chan); */
 665                         flush_buffers(chan);
 666                         up(&dev->stream_mutex);
 667                         return 0;
 668                 }
 669                 spin_unlock_irq(&chan->state_lock);
 670                 up(&dev->stream_mutex);
 671                 return 0;
 672         }
 673
 674         if (mode & SMODE_AUDIO_CAPTURE) {
 675                 com.cmd.StreamControl.CaptureBlockCount =
 676                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
 677                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 678         } else if (mode & SMODE_TRANSPORT_STREAM) {
 679                 com.cmd.StreamControl.CaptureBlockCount =
 680                         chan->Capture1Length / TS_BLOCK_SIZE;
 681                 com.cmd.StreamControl.MaxLinesPerField =
 682                         chan->Capture1Length / TS_BLOCK_SIZE;
 683                 com.cmd.StreamControl.Buffer_Address =
 684                         chan->TSRingBuffer.PAHead;
 685                 if (chan->mode & NGENE_IO_TSOUT) {
 686                         com.cmd.StreamControl.BytesPerVBILine =
 687                                 chan->Capture1Length / TS_BLOCK_SIZE;
 688                         com.cmd.StreamControl.Stream |= 0x07;
 689                 }
 690         } else {
 691                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
 692                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
 693                 com.cmd.StreamControl.MinLinesPerField = 100;
 694                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 695
 696                 if (mode & SMODE_VBI_CAPTURE) {
 697                         com.cmd.StreamControl.MaxVBILinesPerField =
 698                                 chan->nVBILines;
 699                         com.cmd.StreamControl.MinVBILinesPerField = 0;
 700                         com.cmd.StreamControl.BytesPerVBILine =
 701                                 chan->nBytesPerVBILine;
 702                 }
 703                 if (flags & SFLAG_COLORBAR)
 704                         com.cmd.StreamControl.Stream |= 0x04;
 705         }
 706
 707         spin_lock_irq(&chan->state_lock);
 708         if (mode & SMODE_AUDIO_CAPTURE) {
 709                 chan->nextBuffer = chan->RingBuffer.Head;
 710                 if (mode & SMODE_AUDIO_SPDIF) {
 711                         com.cmd.StreamControl.SetupDataLen =
 712                                 sizeof(SPDIFConfiguration);
 713                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
 714                         memcpy(com.cmd.StreamControl.SetupData,
 715                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
 716                 } else {
 717                         com.cmd.StreamControl.SetupDataLen = 4;
 718                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
 719                         memcpy(com.cmd.StreamControl.SetupData,
 720                                I2SConfiguration +
 721                                4 * dev->card_info->i2s[stream], 4);
 722                 }
 723         } else if (mode & SMODE_TRANSPORT_STREAM) {
 724                 chan->nextBuffer = chan->TSRingBuffer.Head;
 725                 if (stream >= STREAM_AUDIOIN1) {
 726                         if (chan->mode & NGENE_IO_TSOUT) {
 727                                 com.cmd.StreamControl.SetupDataLen =
 728                                         sizeof(TS_I2SOutConfiguration);
 729                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
 730                                 memcpy(com.cmd.StreamControl.SetupData,
 731                                        TS_I2SOutConfiguration,
 732                                        sizeof(TS_I2SOutConfiguration));
 733                         } else {
 734                                 com.cmd.StreamControl.SetupDataLen =
 735                                         sizeof(TS_I2SConfiguration);
 736                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
 737                                 memcpy(com.cmd.StreamControl.SetupData,
 738                                        TS_I2SConfiguration,
 739                                        sizeof(TS_I2SConfiguration));
 740                         }
 741                 } else {
 742                         com.cmd.StreamControl.SetupDataLen = 8;
 743                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
 744                         memcpy(com.cmd.StreamControl.SetupData,
 745                                TSFeatureDecoderSetup +
 746                                8 * dev->card_info->tsf[stream], 8);
 747                 }
 748         } else {
 749                 chan->nextBuffer = chan->RingBuffer.Head;
 750                 com.cmd.StreamControl.SetupDataLen =
 751                         16 + sizeof(ITUFeatureDecoderSetup);
 752                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
 753                 memcpy(com.cmd.StreamControl.SetupData,
 754                        ITUDecoderSetup[chan->itumode], 16);
 755                 memcpy(com.cmd.StreamControl.SetupData + 16,
 756                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
 757         }
 758         clear_buffers(chan);
 759         chan->State = KSSTATE_RUN;
 760         if (mode & SMODE_TRANSPORT_STREAM)
 761                 chan->HWState = HWSTATE_RUN;
 762         else
 763                 chan->HWState = HWSTATE_STARTUP;
 764         spin_unlock_irq(&chan->state_lock);
 765
 766         if (ngene_command(dev, &com) < 0) {
 767                 up(&dev->stream_mutex);
 768                 return -1;
 769         }
 770         up(&dev->stream_mutex);
 771         return 0;
 772 }
 773
 774
 775 /****************************************************************************/
 776 /* I2C **********************************************************************/
 777 /****************************************************************************/
 778
 779 static void ngene_i2c_set_bus(struct ngene *dev, int bus)
 780 {
 781         if (!(dev->card_info->i2c_access & 2))
 782                 return;
 783         if (dev->i2c_current_bus == bus)
 784                 return;
 785
 786         switch (bus) {
 787         case 0:
 788                 ngene_command_gpio_set(dev, 3, 0);
 789                 ngene_command_gpio_set(dev, 2, 1);
 790                 break;
 791
 792         case 1:
 793                 ngene_command_gpio_set(dev, 2, 0);
 794                 ngene_command_gpio_set(dev, 3, 1);
 795                 break;
 796         }
 797         dev->i2c_current_bus = bus;
 798 }
 799
 800 static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
 801                                  struct i2c_msg msg[], int num)
 802 {
 803         struct ngene_channel *chan =
 804                 (struct ngene_channel *)i2c_get_adapdata(adapter);
 805         struct ngene *dev = chan->dev;
 806
 807         down(&dev->i2c_switch_mutex);
 808         ngene_i2c_set_bus(dev, chan->number);
 809
 810         if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
 811                 if (!ngene_command_i2c_read(dev, msg[0].addr,
 812                                             msg[0].buf, msg[0].len,
 813                                             msg[1].buf, msg[1].len, 0))
 814                         goto done;
 815
 816         if (num == 1 && !(msg[0].flags & I2C_M_RD))
 817                 if (!ngene_command_i2c_write(dev, msg[0].addr,
 818                                              msg[0].buf, msg[0].len))
 819                         goto done;
 820         if (num == 1 && (msg[0].flags & I2C_M_RD))
 821                 if (!ngene_command_i2c_read(dev, msg[0].addr, NULL, 0,
 822                                             msg[0].buf, msg[0].len, 0))
 823                         goto done;
 824
 825         up(&dev->i2c_switch_mutex);
 826         return -EIO;
 827
 828 done:
 829         up(&dev->i2c_switch_mutex);
 830         return num;
 831 }
 832
 833
 834 static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
 835 {
 836         return I2C_FUNC_SMBUS_EMUL;
 837 }
 838
 839 static struct i2c_algorithm ngene_i2c_algo = {
 840         .master_xfer = ngene_i2c_master_xfer,
 841         .functionality = ngene_i2c_functionality,
 842 };
 843
 844 static int ngene_i2c_init(struct ngene *dev, int dev_nr)
 845 {
 846         struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
 847
 848         i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
 849         adap->class = I2C_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
 850
 851         strcpy(adap->name, "nGene");
 852
 853         adap->algo = &ngene_i2c_algo;
 854         adap->algo_data = (void *)&(dev->channel[dev_nr]);
 855         adap->dev.parent = &dev->pci_dev->dev;
 856
 857         return i2c_add_adapter(adap);
 858 }
 859
 860
 861 /****************************************************************************/
 862 /* DVB functions and API interface ******************************************/
 863 /****************************************************************************/
 864
 865 static void swap_buffer(u32 *p, u32 len)
 866 {
 867         while (len) {
 868                 *p = swab32(*p);
 869                 p++;
 870                 len -= 4;
 871         }
 872 }
 873
 874
 875 static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
 876 {
 877         struct ngene_channel *chan = priv;
 878
 879
 880 #ifdef COMMAND_TIMEOUT_WORKAROUND
 881         if (chan->users > 0)
 882 #endif
 883                 dvb_dmx_swfilter(&chan->demux, buf, len);
 884         return NULL;
 885 }
 886
 887 u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
 888
 889 static void *tsout_exchange(void *priv, void *buf, u32 len,
 890                             u32 clock, u32 flags)
 891 {
 892         struct ngene_channel *chan = priv;
 893         struct ngene *dev = chan->dev;
 894         u32 alen;
 895
 896         alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
 897         alen -= alen % 188;
 898
 899         if (alen < len)
 900                 FillTSBuffer(buf + alen, len - alen, flags);
 901         else
 902                 alen = len;
 903         dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
 904         if (flags & DF_SWAP32)
 905                 swap_buffer((u32 *)buf, alen);
 906         wake_up_interruptible(&dev->tsout_rbuf.queue);
 907         return buf;
 908 }
 909
 910
 911 static void set_transfer(struct ngene_channel *chan, int state)
 912 {
 913         u8 control = 0, mode = 0, flags = 0;
 914         struct ngene *dev = chan->dev;
 915         int ret;
 916
 917         /*
 918         printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
 919         msleep(100);
 920         */
 921
 922         if (state) {
 923                 if (chan->running) {
 924                         printk(KERN_INFO DEVICE_NAME ": already running\n");
 925                         return;
 926                 }
 927         } else {
 928                 if (!chan->running) {
 929                         printk(KERN_INFO DEVICE_NAME ": already stopped\n");
 930                         return;
 931                 }
 932         }
 933
 934         if (dev->card_info->switch_ctrl)
 935                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
 936
 937         if (state) {
 938                 spin_lock_irq(&chan->state_lock);
 939
 940                 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 941                           ngreadl(0x9310)); */
 942                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 943                 control = 0x80;
 944                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
 945                         chan->Capture1Length = 512 * 188;
 946                         mode = SMODE_TRANSPORT_STREAM;
 947                 }
 948                 if (chan->mode & NGENE_IO_TSOUT) {
 949                         chan->pBufferExchange = tsout_exchange;
 950                         /* 0x66666666 = 50MHz *2^33 /250MHz */
 951                         chan->AudioDTOValue = 0x66666666;
 952                         /* set_dto(chan, 38810700+1000); */
 953                         /* set_dto(chan, 19392658); */
 954                 }
 955                 if (chan->mode & NGENE_IO_TSIN)
 956                         chan->pBufferExchange = tsin_exchange;
 957                 /* ngwritel(0, 0x9310); */
 958                 spin_unlock_irq(&chan->state_lock);
 959         } else
 960                 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 961                            ngreadl(0x9310)); */
 962
 963         ret = ngene_command_stream_control(dev, chan->number,
 964                                            control, mode, flags);
 965         if (!ret)
 966                 chan->running = state;
 967         else
 968                 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
 969                        state);
 970         if (!state) {
 971                 spin_lock_irq(&chan->state_lock);
 972                 chan->pBufferExchange = NULL;
 973                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 974                 spin_unlock_irq(&chan->state_lock);
 975         }
 976 }
 977
 978 static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
 979 {
 980         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
 981         struct ngene_channel *chan = dvbdmx->priv;
 982
 983         if (chan->users == 0) {
 984 #ifdef COMMAND_TIMEOUT_WORKAROUND
 985                 if (!chan->running)
 986 #endif
 987                         set_transfer(chan, 1);
 988                 /* msleep(10); */
 989         }
 990
 991         return ++chan->users;
 992 }
 993
 994 static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
 995 {
 996         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
 997         struct ngene_channel *chan = dvbdmx->priv;
 998
 999         if (--chan->users)
1000                 return chan->users;
1001
1002 #ifndef COMMAND_TIMEOUT_WORKAROUND
1003         set_transfer(chan, 0);
1004 #endif
1005
1006         return 0;
1007 }
1008
1009
1010
1011 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
1012                                    int (*start_feed)(struct dvb_demux_feed *),
1013                                    int (*stop_feed)(struct dvb_demux_feed *),
1014                                    void *priv)
1015 {
1016         dvbdemux->priv = priv;
1017
1018         dvbdemux->filternum = 256;
1019         dvbdemux->feednum = 256;
1020         dvbdemux->start_feed = start_feed;
1021         dvbdemux->stop_feed = stop_feed;
1022         dvbdemux->write_to_decoder = NULL;
1023         dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1024                                       DMX_SECTION_FILTERING |
1025                                       DMX_MEMORY_BASED_FILTERING);
1026         return dvb_dmx_init(dvbdemux);
1027 }
1028
1029 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1030                                       struct dvb_demux *dvbdemux,
1031                                       struct dmx_frontend *hw_frontend,
1032                                       struct dmx_frontend *mem_frontend,
1033                                       struct dvb_adapter *dvb_adapter)
1034 {
1035         int ret;
1036
1037         dmxdev->filternum = 256;
1038         dmxdev->demux = &dvbdemux->dmx;
1039         dmxdev->capabilities = 0;
1040         ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1041         if (ret < 0)
1042                 return ret;
1043
1044         hw_frontend->source = DMX_FRONTEND_0;
1045         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1046         mem_frontend->source = DMX_MEMORY_FE;
1047         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1048         return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1049 }
1050
1051
1052 /****************************************************************************/
1053 /* nGene hardware init and release functions ********************************/
1054 /****************************************************************************/
1055
1056 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
1057 {
1058         struct SBufferHeader *Cur = rb->Head;
1059         u32 j;
1060
1061         if (!Cur)
1062                 return;
1063
1064         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1065                 if (Cur->Buffer1)
1066                         pci_free_consistent(dev->pci_dev,
1067                                             rb->Buffer1Length,
1068                                             Cur->Buffer1,
1069                                             Cur->scList1->Address);
1070
1071                 if (Cur->Buffer2)
1072                         pci_free_consistent(dev->pci_dev,
1073                                             rb->Buffer2Length,
1074                                             Cur->Buffer2,
1075                                             Cur->scList2->Address);
1076         }
1077
1078         if (rb->SCListMem)
1079                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1080                                     rb->SCListMem, rb->PASCListMem);
1081
1082         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1083 }
1084
1085 static void free_idlebuffer(struct ngene *dev,
1086                      struct SRingBufferDescriptor *rb,
1087                      struct SRingBufferDescriptor *tb)
1088 {
1089         int j;
1090         struct SBufferHeader *Cur = tb->Head;
1091
1092         if (!rb->Head)
1093                 return;
1094         free_ringbuffer(dev, rb);
1095         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1096                 Cur->Buffer2 = NULL;
1097                 Cur->scList2 = NULL;
1098                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1099                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1100         }
1101 }
1102
1103 static void free_common_buffers(struct ngene *dev)
1104 {
1105         u32 i;
1106         struct ngene_channel *chan;
1107
1108         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1109                 chan = &dev->channel[i];
1110                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1111                 free_ringbuffer(dev, &chan->RingBuffer);
1112                 free_ringbuffer(dev, &chan->TSRingBuffer);
1113         }
1114
1115         if (dev->OverflowBuffer)
1116                 pci_free_consistent(dev->pci_dev,
1117                                     OVERFLOW_BUFFER_SIZE,
1118                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
1119
1120         if (dev->FWInterfaceBuffer)
1121                 pci_free_consistent(dev->pci_dev,
1122                                     4096,
1123                                     dev->FWInterfaceBuffer,
1124                                     dev->PAFWInterfaceBuffer);
1125 }
1126
1127 /****************************************************************************/
1128 /* Ring buffer handling *****************************************************/
1129 /****************************************************************************/
1130
1131 static int create_ring_buffer(struct pci_dev *pci_dev,
1132                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
1133 {
1134         dma_addr_t tmp;
1135         struct SBufferHeader *Head;
1136         u32 i;
1137         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1138         u64 PARingBufferHead;
1139         u64 PARingBufferCur;
1140         u64 PARingBufferNext;
1141         struct SBufferHeader *Cur, *Next;
1142
1143         descr->Head = NULL;
1144         descr->MemSize = 0;
1145         descr->PAHead = 0;
1146         descr->NumBuffers = 0;
1147
1148         if (MemSize < 4096)
1149                 MemSize = 4096;
1150
1151         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1152         PARingBufferHead = tmp;
1153
1154         if (!Head)
1155                 return -ENOMEM;
1156
1157         memset(Head, 0, MemSize);
1158
1159         PARingBufferCur = PARingBufferHead;
1160         Cur = Head;
1161
1162         for (i = 0; i < NumBuffers - 1; i++) {
1163                 Next = (struct SBufferHeader *)
1164                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
1165                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1166                 Cur->Next = Next;
1167                 Cur->ngeneBuffer.Next = PARingBufferNext;
1168                 Cur = Next;
1169                 PARingBufferCur = PARingBufferNext;
1170         }
1171         /* Last Buffer points back to first one */
1172         Cur->Next = Head;
1173         Cur->ngeneBuffer.Next = PARingBufferHead;
1174
1175         descr->Head       = Head;
1176         descr->MemSize    = MemSize;
1177         descr->PAHead     = PARingBufferHead;
1178         descr->NumBuffers = NumBuffers;
1179
1180         return 0;
1181 }
1182
1183 static int AllocateRingBuffers(struct pci_dev *pci_dev,
1184                                dma_addr_t of,
1185                                struct SRingBufferDescriptor *pRingBuffer,
1186                                u32 Buffer1Length, u32 Buffer2Length)
1187 {
1188         dma_addr_t tmp;
1189         u32 i, j;
1190         int status = 0;
1191         u32 SCListMemSize = pRingBuffer->NumBuffers
1192                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1193                     NUM_SCATTER_GATHER_ENTRIES)
1194                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1195
1196         u64 PASCListMem;
1197         struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
1198         u64 PASCListEntry;
1199         struct SBufferHeader *Cur;
1200         void *SCListMem;
1201
1202         if (SCListMemSize < 4096)
1203                 SCListMemSize = 4096;
1204
1205         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1206
1207         PASCListMem = tmp;
1208         if (SCListMem == NULL)
1209                 return -ENOMEM;
1210
1211         memset(SCListMem, 0, SCListMemSize);
1212
1213         pRingBuffer->SCListMem = SCListMem;
1214         pRingBuffer->PASCListMem = PASCListMem;
1215         pRingBuffer->SCListMemSize = SCListMemSize;
1216         pRingBuffer->Buffer1Length = Buffer1Length;
1217         pRingBuffer->Buffer2Length = Buffer2Length;
1218
1219         SCListEntry = SCListMem;
1220         PASCListEntry = PASCListMem;
1221         Cur = pRingBuffer->Head;
1222
1223         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1224                 u64 PABuffer;
1225
1226                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1227                                                     &tmp);
1228                 PABuffer = tmp;
1229
1230                 if (Buffer == NULL)
1231                         return -ENOMEM;
1232
1233                 Cur->Buffer1 = Buffer;
1234
1235                 SCListEntry->Address = PABuffer;
1236                 SCListEntry->Length  = Buffer1Length;
1237
1238                 Cur->scList1 = SCListEntry;
1239                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1240                 Cur->ngeneBuffer.Number_of_entries_1 =
1241                         NUM_SCATTER_GATHER_ENTRIES;
1242
1243                 SCListEntry += 1;
1244                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1245
1246 #if NUM_SCATTER_GATHER_ENTRIES > 1
1247                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1248                         SCListEntry->Address = of;
1249                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1250                         SCListEntry += 1;
1251                         PASCListEntry +=
1252                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1253                 }
1254 #endif
1255
1256                 if (!Buffer2Length)
1257                         continue;
1258
1259                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1260                 PABuffer = tmp;
1261
1262                 if (Buffer == NULL)
1263                         return -ENOMEM;
1264
1265                 Cur->Buffer2 = Buffer;
1266
1267                 SCListEntry->Address = PABuffer;
1268                 SCListEntry->Length  = Buffer2Length;
1269
1270                 Cur->scList2 = SCListEntry;
1271                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1272                 Cur->ngeneBuffer.Number_of_entries_2 =
1273                         NUM_SCATTER_GATHER_ENTRIES;
1274
1275                 SCListEntry   += 1;
1276                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1277
1278 #if NUM_SCATTER_GATHER_ENTRIES > 1
1279                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1280                         SCListEntry->Address = of;
1281                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1282                         SCListEntry += 1;
1283                         PASCListEntry +=
1284                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1285                 }
1286 #endif
1287
1288         }
1289
1290         return status;
1291 }
1292
1293 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1294                             struct SRingBufferDescriptor *pRingBuffer)
1295 {
1296         int status = 0;
1297
1298         /* Copy pointer to scatter gather list in TSRingbuffer
1299            structure for buffer 2
1300            Load number of buffer
1301         */
1302         u32 n = pRingBuffer->NumBuffers;
1303
1304         /* Point to first buffer entry */
1305         struct SBufferHeader *Cur = pRingBuffer->Head;
1306         int i;
1307         /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1308         for (i = 0; i < n; i++) {
1309                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1310                 Cur->scList2 = pIdleBuffer->Head->scList1;
1311                 Cur->ngeneBuffer.Address_of_first_entry_2 =
1312                         pIdleBuffer->Head->ngeneBuffer.
1313                         Address_of_first_entry_1;
1314                 Cur->ngeneBuffer.Number_of_entries_2 =
1315                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1316                 Cur = Cur->Next;
1317         }
1318         return status;
1319 }
1320
1321 static u32 RingBufferSizes[MAX_STREAM] = {
1322         RING_SIZE_VIDEO,
1323         RING_SIZE_VIDEO,
1324         RING_SIZE_AUDIO,
1325         RING_SIZE_AUDIO,
1326         RING_SIZE_AUDIO,
1327 };
1328
1329 static u32 Buffer1Sizes[MAX_STREAM] = {
1330         MAX_VIDEO_BUFFER_SIZE,
1331         MAX_VIDEO_BUFFER_SIZE,
1332         MAX_AUDIO_BUFFER_SIZE,
1333         MAX_AUDIO_BUFFER_SIZE,
1334         MAX_AUDIO_BUFFER_SIZE
1335 };
1336
1337 static u32 Buffer2Sizes[MAX_STREAM] = {
1338         MAX_VBI_BUFFER_SIZE,
1339         MAX_VBI_BUFFER_SIZE,
1340         0,
1341         0,
1342         0
1343 };
1344
1345
1346 static int AllocCommonBuffers(struct ngene *dev)
1347 {
1348         int status = 0, i;
1349
1350         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1351                                                      &dev->PAFWInterfaceBuffer);
1352         if (!dev->FWInterfaceBuffer)
1353                 return -ENOMEM;
1354         dev->hosttongene = dev->FWInterfaceBuffer;
1355         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1356         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1357
1358         dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1359                                                    OVERFLOW_BUFFER_SIZE,
1360                                                    &dev->PAOverflowBuffer);
1361         if (!dev->OverflowBuffer)
1362                 return -ENOMEM;
1363         memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1364
1365         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1366                 int type = dev->card_info->io_type[i];
1367
1368                 dev->channel[i].State = KSSTATE_STOP;
1369
1370                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1371                         status = create_ring_buffer(dev->pci_dev,
1372                                                     &dev->channel[i].RingBuffer,
1373                                                     RingBufferSizes[i]);
1374                         if (status < 0)
1375                                 break;
1376
1377                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1378                                 status = AllocateRingBuffers(dev->pci_dev,
1379                                                              dev->
1380                                                              PAOverflowBuffer,
1381                                                              &dev->channel[i].
1382                                                              RingBuffer,
1383                                                              Buffer1Sizes[i],
1384                                                              Buffer2Sizes[i]);
1385                                 if (status < 0)
1386                                         break;
1387                         } else if (type & NGENE_IO_HDTV) {
1388                                 status = AllocateRingBuffers(dev->pci_dev,
1389                                                              dev->
1390                                                              PAOverflowBuffer,
1391                                                              &dev->channel[i].
1392                                                              RingBuffer,
1393                                                            MAX_HDTV_BUFFER_SIZE,
1394                                                              0);
1395                                 if (status < 0)
1396                                         break;
1397                         }
1398                 }
1399
1400                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1401
1402                         status = create_ring_buffer(dev->pci_dev,
1403                                                     &dev->channel[i].
1404                                                     TSRingBuffer, RING_SIZE_TS);
1405                         if (status < 0)
1406                                 break;
1407
1408                         status = AllocateRingBuffers(dev->pci_dev,
1409                                                      dev->PAOverflowBuffer,
1410                                                      &dev->channel[i].
1411                                                      TSRingBuffer,
1412                                                      MAX_TS_BUFFER_SIZE, 0);
1413                         if (status)
1414                                 break;
1415                 }
1416
1417                 if (type & NGENE_IO_TSOUT) {
1418                         status = create_ring_buffer(dev->pci_dev,
1419                                                     &dev->channel[i].
1420                                                     TSIdleBuffer, 1);
1421                         if (status < 0)
1422                                 break;
1423                         status = AllocateRingBuffers(dev->pci_dev,
1424                                                      dev->PAOverflowBuffer,
1425                                                      &dev->channel[i].
1426                                                      TSIdleBuffer,
1427                                                      MAX_TS_BUFFER_SIZE, 0);
1428                         if (status)
1429                                 break;
1430                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1431                                          &dev->channel[i].TSRingBuffer);
1432                 }
1433         }
1434         return status;
1435 }
1436
1437 static void ngene_release_buffers(struct ngene *dev)
1438 {
1439         if (dev->iomem)
1440                 iounmap(dev->iomem);
1441         free_common_buffers(dev);
1442         vfree(dev->tsout_buf);
1443         vfree(dev->ain_buf);
1444         vfree(dev->vin_buf);
1445         vfree(dev);
1446 }
1447
1448 static int ngene_get_buffers(struct ngene *dev)
1449 {
1450         if (AllocCommonBuffers(dev))
1451                 return -ENOMEM;
1452         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1453                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1454                 if (!dev->tsout_buf)
1455                         return -ENOMEM;
1456                 dvb_ringbuffer_init(&dev->tsout_rbuf,
1457                                     dev->tsout_buf, TSOUT_BUF_SIZE);
1458         }
1459         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1460                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1461                 if (!dev->ain_buf)
1462                         return -ENOMEM;
1463                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1464         }
1465         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1466                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1467                 if (!dev->vin_buf)
1468                         return -ENOMEM;
1469                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1470         }
1471         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1472                              pci_resource_len(dev->pci_dev, 0));
1473         if (!dev->iomem)
1474                 return -ENOMEM;
1475
1476         return 0;
1477 }
1478
1479 static void ngene_init(struct ngene *dev)
1480 {
1481         int i;
1482
1483         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1484
1485         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1486         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1487
1488         for (i = 0; i < MAX_STREAM; i++) {
1489                 dev->channel[i].dev = dev;
1490                 dev->channel[i].number = i;
1491         }
1492
1493         dev->fw_interface_version = 0;
1494
1495         ngwritel(0, NGENE_INT_ENABLE);
1496
1497         dev->icounts = ngreadl(NGENE_INT_COUNTS);
1498
1499         dev->device_version = ngreadl(DEV_VER) & 0x0f;
1500         printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1501                dev->device_version);
1502 }
1503
1504 static int ngene_load_firm(struct ngene *dev)
1505 {
1506         u32 size;
1507         const struct firmware *fw = NULL;
1508         u8 *ngene_fw;
1509         char *fw_name;
1510         int err, version;
1511
1512         version = dev->card_info->fw_version;
1513
1514         switch (version) {
1515         default:
1516         case 15:
1517                 version = 15;
1518                 size = 23466;
1519                 fw_name = "ngene_15.fw";
1520                 break;
1521         case 16:
1522                 size = 23498;
1523                 fw_name = "ngene_16.fw";
1524                 break;
1525         case 17:
1526                 size = 24446;
1527                 fw_name = "ngene_17.fw";
1528                 break;
1529         }
1530
1531         if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1532                 printk(KERN_ERR DEVICE_NAME
1533                         ": Could not load firmware file %s.\n", fw_name);
1534                 printk(KERN_INFO DEVICE_NAME
1535                         ": Copy %s to your hotplug directory!\n", fw_name);
1536                 return -1;
1537         }
1538         if (size != fw->size) {
1539                 printk(KERN_ERR DEVICE_NAME
1540                         ": Firmware %s has invalid size!", fw_name);
1541                 err = -1;
1542         } else {
1543                 printk(KERN_INFO DEVICE_NAME
1544                         ": Loading firmware file %s.\n", fw_name);
1545                 ngene_fw = (u8 *) fw->data;
1546                 err = ngene_command_load_firmware(dev, ngene_fw, size);
1547         }
1548
1549         release_firmware(fw);
1550
1551         return err;
1552 }
1553
1554 static void ngene_stop(struct ngene *dev)
1555 {
1556         down(&dev->cmd_mutex);
1557         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1558         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1559         ngwritel(0, NGENE_INT_ENABLE);
1560         ngwritel(0, NGENE_COMMAND);
1561         ngwritel(0, NGENE_COMMAND_HI);
1562         ngwritel(0, NGENE_STATUS);
1563         ngwritel(0, NGENE_STATUS_HI);
1564         ngwritel(0, NGENE_EVENT);
1565         ngwritel(0, NGENE_EVENT_HI);
1566         free_irq(dev->pci_dev->irq, dev);
1567 }
1568
1569 static int ngene_start(struct ngene *dev)
1570 {
1571         int stat;
1572         int i;
1573
1574         pci_set_master(dev->pci_dev);
1575         ngene_init(dev);
1576
1577         stat = request_irq(dev->pci_dev->irq, irq_handler,
1578                            IRQF_SHARED, "nGene",
1579                            (void *)dev);
1580         if (stat < 0)
1581                 return stat;
1582
1583         init_waitqueue_head(&dev->cmd_wq);
1584         init_waitqueue_head(&dev->tx_wq);
1585         init_waitqueue_head(&dev->rx_wq);
1586         sema_init(&dev->cmd_mutex, 1);
1587         sema_init(&dev->stream_mutex, 1);
1588         sema_init(&dev->pll_mutex, 1);
1589         sema_init(&dev->i2c_switch_mutex, 1);
1590         spin_lock_init(&dev->cmd_lock);
1591         for (i = 0; i < MAX_STREAM; i++)
1592                 spin_lock_init(&dev->channel[i].state_lock);
1593         ngwritel(1, TIMESTAMPS);
1594
1595         ngwritel(1, NGENE_INT_ENABLE);
1596
1597         stat = ngene_load_firm(dev);
1598         if (stat < 0)
1599                 goto fail;
1600
1601         stat = ngene_i2c_init(dev, 0);
1602         if (stat < 0)
1603                 goto fail;
1604
1605         stat = ngene_i2c_init(dev, 1);
1606         if (stat < 0)
1607                 goto fail;
1608
1609         if (dev->card_info->fw_version == 17) {
1610                 u8 tsin4_config[6] = {
1611                         3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1612                 u8 default_config[6] = {
1613                         4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
1614                 u8 *bconf = default_config;
1615
1616                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1617                         bconf = tsin4_config;
1618                 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
1619                 stat = ngene_command_config_free_buf(dev, bconf);
1620         } else {
1621                 int bconf = BUFFER_CONFIG_4422;
1622                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1623                         bconf = BUFFER_CONFIG_3333;
1624                 stat = ngene_command_config_buf(dev, bconf);
1625         }
1626         return stat;
1627 fail:
1628         ngwritel(0, NGENE_INT_ENABLE);
1629         free_irq(dev->pci_dev->irq, dev);
1630         return stat;
1631 }
1632
1633
1634
1635 /****************************************************************************/
1636 /* Switch control (I2C gates, etc.) *****************************************/
1637 /****************************************************************************/
1638
1639
1640 /****************************************************************************/
1641 /* Demod/tuner attachment ***************************************************/
1642 /****************************************************************************/
1643
1644 static int tuner_attach_stv6110(struct ngene_channel *chan)
1645 {
1646         struct stv090x_config *feconf = (struct stv090x_config *)
1647                 chan->dev->card_info->fe_config[chan->number];
1648         struct stv6110x_config *tunerconf = (struct stv6110x_config *)
1649                 chan->dev->card_info->tuner_config[chan->number];
1650         struct stv6110x_devctl *ctl;
1651
1652         ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
1653                          &chan->i2c_adapter);
1654         if (ctl == NULL) {
1655                 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
1656                 return -ENODEV;
1657         }
1658
1659         feconf->tuner_init          = ctl->tuner_init;
1660         feconf->tuner_set_mode      = ctl->tuner_set_mode;
1661         feconf->tuner_set_frequency = ctl->tuner_set_frequency;
1662         feconf->tuner_get_frequency = ctl->tuner_get_frequency;
1663         feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
1664         feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
1665         feconf->tuner_set_bbgain    = ctl->tuner_set_bbgain;
1666         feconf->tuner_get_bbgain    = ctl->tuner_get_bbgain;
1667         feconf->tuner_set_refclk    = ctl->tuner_set_refclk;
1668         feconf->tuner_get_status    = ctl->tuner_get_status;
1669
1670         return 0;
1671 }
1672
1673
1674 static int demod_attach_stv0900(struct ngene_channel *chan)
1675 {
1676         struct stv090x_config *feconf = (struct stv090x_config *)
1677                 chan->dev->card_info->fe_config[chan->number];
1678
1679         chan->fe = dvb_attach(stv090x_attach,
1680                         feconf,
1681                         &chan->i2c_adapter,
1682                         chan->number == 0 ? STV090x_DEMODULATOR_0 :
1683                                             STV090x_DEMODULATOR_1);
1684         if (chan->fe == NULL) {
1685                 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
1686                 return -ENODEV;
1687         }
1688
1689         if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
1690                         0, chan->dev->card_info->lnb[chan->number])) {
1691                 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
1692                 dvb_frontend_detach(chan->fe);
1693                 return -ENODEV;
1694         }
1695
1696         return 0;
1697 }
1698
1699 /****************************************************************************/
1700 /****************************************************************************/
1701 /****************************************************************************/
1702
1703 static void release_channel(struct ngene_channel *chan)
1704 {
1705         struct dvb_demux *dvbdemux = &chan->demux;
1706         struct ngene *dev = chan->dev;
1707         struct ngene_info *ni = dev->card_info;
1708         int io = ni->io_type[chan->number];
1709
1710 #ifdef COMMAND_TIMEOUT_WORKAROUND
1711         if (chan->running)
1712                 set_transfer(chan, 0);
1713 #endif
1714
1715         tasklet_kill(&chan->demux_tasklet);
1716
1717         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1718                 if (chan->fe) {
1719                         dvb_unregister_frontend(chan->fe);
1720                         dvb_frontend_detach(chan->fe);
1721                         chan->fe = NULL;
1722                 }
1723                 dvbdemux->dmx.close(&dvbdemux->dmx);
1724                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1725                                               &chan->hw_frontend);
1726                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1727                                               &chan->mem_frontend);
1728                 dvb_dmxdev_release(&chan->dmxdev);
1729                 dvb_dmx_release(&chan->demux);
1730
1731                 if (chan->number == 0 || !one_adapter)
1732                         dvb_unregister_adapter(&dev->adapter[chan->number]);
1733         }
1734 }
1735
1736 static int init_channel(struct ngene_channel *chan)
1737 {
1738         int ret = 0, nr = chan->number;
1739         struct dvb_adapter *adapter = NULL;
1740         struct dvb_demux *dvbdemux = &chan->demux;
1741         struct ngene *dev = chan->dev;
1742         struct ngene_info *ni = dev->card_info;
1743         int io = ni->io_type[nr];
1744
1745         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1746         chan->users = 0;
1747         chan->type = io;
1748         chan->mode = chan->type;        /* for now only one mode */
1749
1750         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1751                 if (nr >= STREAM_AUDIOIN1)
1752                         chan->DataFormatFlags = DF_SWAP32;
1753                 if (nr == 0 || !one_adapter) {
1754                         adapter = &dev->adapter[nr];
1755                         ret = dvb_register_adapter(adapter, "nGene",
1756                                                    THIS_MODULE,
1757                                                    &chan->dev->pci_dev->dev,
1758                                                    adapter_nr);
1759                         if (ret < 0)
1760                                 return ret;
1761                 } else {
1762                         adapter = &dev->adapter[0];
1763                 }
1764
1765                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1766                                               ngene_start_feed,
1767                                               ngene_stop_feed, chan);
1768                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1769                                                  &chan->hw_frontend,
1770                                                  &chan->mem_frontend, adapter);
1771         }
1772
1773         if (io & NGENE_IO_TSIN) {
1774                 chan->fe = NULL;
1775                 if (ni->demod_attach[nr])
1776                         ni->demod_attach[nr](chan);
1777                 if (chan->fe) {
1778                         if (dvb_register_frontend(adapter, chan->fe) < 0) {
1779                                 if (chan->fe->ops.release)
1780                                         chan->fe->ops.release(chan->fe);
1781                                 chan->fe = NULL;
1782                         }
1783                 }
1784                 if (chan->fe && ni->tuner_attach[nr])
1785                         if (ni->tuner_attach[nr] (chan) < 0) {
1786                                 printk(KERN_ERR DEVICE_NAME
1787                                        ": Tuner attach failed on channel %d!\n",
1788                                        nr);
1789                         }
1790         }
1791         return ret;
1792 }
1793
1794 static int init_channels(struct ngene *dev)
1795 {
1796         int i, j;
1797
1798         for (i = 0; i < MAX_STREAM; i++) {
1799                 if (init_channel(&dev->channel[i]) < 0) {
1800                         for (j = i - 1; j >= 0; j--)
1801                                 release_channel(&dev->channel[j]);
1802                         return -1;
1803                 }
1804         }
1805         return 0;
1806 }
1807
1808 /****************************************************************************/
1809 /* device probe/remove calls ************************************************/
1810 /****************************************************************************/
1811
1812 static void __devexit ngene_remove(struct pci_dev *pdev)
1813 {
1814         struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1815         int i;
1816
1817         tasklet_kill(&dev->event_tasklet);
1818         for (i = MAX_STREAM - 1; i >= 0; i--)
1819                 release_channel(&dev->channel[i]);
1820         ngene_stop(dev);
1821         ngene_release_buffers(dev);
1822         pci_set_drvdata(pdev, NULL);
1823         pci_disable_device(pdev);
1824 }
1825
1826 static int __devinit ngene_probe(struct pci_dev *pci_dev,
1827                                  const struct pci_device_id *id)
1828 {
1829         struct ngene *dev;
1830         int stat = 0;
1831
1832         if (pci_enable_device(pci_dev) < 0)
1833                 return -ENODEV;
1834
1835         dev = vmalloc(sizeof(struct ngene));
1836         if (dev == NULL) {
1837                 stat = -ENOMEM;
1838                 goto fail0;
1839         }
1840         memset(dev, 0, sizeof(struct ngene));
1841
1842         dev->pci_dev = pci_dev;
1843         dev->card_info = (struct ngene_info *)id->driver_data;
1844         printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1845
1846         pci_set_drvdata(pci_dev, dev);
1847
1848         /* Alloc buffers and start nGene */
1849         stat = ngene_get_buffers(dev);
1850         if (stat < 0)
1851                 goto fail1;
1852         stat = ngene_start(dev);
1853         if (stat < 0)
1854                 goto fail1;
1855
1856         dev->i2c_current_bus = -1;
1857
1858         /* Register DVB adapters and devices for both channels */
1859         if (init_channels(dev) < 0)
1860                 goto fail2;
1861
1862         return 0;
1863
1864 fail2:
1865         ngene_stop(dev);
1866 fail1:
1867         ngene_release_buffers(dev);
1868 fail0:
1869         pci_disable_device(pci_dev);
1870         pci_set_drvdata(pci_dev, NULL);
1871         return stat;
1872 }
1873
1874 /****************************************************************************/
1875 /* Card configs *************************************************************/
1876 /****************************************************************************/
1877
1878 static struct stv090x_config fe_cineS2 = {
1879         .device         = STV0900,
1880         .demod_mode     = STV090x_DUAL,
1881         .clk_mode       = STV090x_CLK_EXT,
1882
1883         .xtal           = 27000000,
1884         .address        = 0x68,
1885
1886         .ts1_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
1887         .ts2_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
1888
1889         .repeater_level = STV090x_RPTLEVEL_16,
1890
1891         .adc1_range     = STV090x_ADC_1Vpp,
1892         .adc2_range     = STV090x_ADC_1Vpp,
1893
1894         .diseqc_envelope_mode = true,
1895 };
1896
1897 static struct stv6110x_config tuner_cineS2_0 = {
1898         .addr   = 0x60,
1899         .refclk = 27000000,
1900         .clk_div = 1,
1901 };
1902
1903 static struct stv6110x_config tuner_cineS2_1 = {
1904         .addr   = 0x63,
1905         .refclk = 27000000,
1906         .clk_div = 1,
1907 };
1908
1909 static struct ngene_info ngene_info_cineS2 = {
1910         .type           = NGENE_SIDEWINDER,
1911         .name           = "Linux4Media cineS2 DVB-S2 Twin Tuner",
1912         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1913         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1914         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1915         .fe_config      = {&fe_cineS2, &fe_cineS2},
1916         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1917         .lnb            = {0x0b, 0x08},
1918         .tsf            = {3, 3},
1919         .fw_version     = 15,
1920 };
1921
1922 static struct ngene_info ngene_info_satixS2 = {
1923         .type           = NGENE_SIDEWINDER,
1924         .name           = "Mystique SaTiX-S2 Dual",
1925         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1926         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1927         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1928         .fe_config      = {&fe_cineS2, &fe_cineS2},
1929         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1930         .lnb            = {0x0b, 0x08},
1931         .tsf            = {3, 3},
1932         .fw_version     = 15,
1933 };
1934
1935 static struct ngene_info ngene_info_satixS2v2 = {
1936         .type           = NGENE_SIDEWINDER,
1937         .name           = "Mystique SaTiX-S2 Dual (v2)",
1938         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1939         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1940         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1941         .fe_config      = {&fe_cineS2, &fe_cineS2},
1942         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1943         .lnb            = {0x0a, 0x08},
1944         .tsf            = {3, 3},
1945         .fw_version     = 15,
1946 };
1947
1948 static struct ngene_info ngene_info_cineS2v5 = {
1949         .type           = NGENE_SIDEWINDER,
1950         .name           = "Linux4Media cineS2 DVB-S2 Twin Tuner (v5)",
1951         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1952         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1953         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1954         .fe_config      = {&fe_cineS2, &fe_cineS2},
1955         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1956         .lnb            = {0x0a, 0x08},
1957         .tsf            = {3, 3},
1958         .fw_version     = 15,
1959 };
1960
1961 /****************************************************************************/
1962
1963
1964
1965 /****************************************************************************/
1966 /* PCI Subsystem ID *********************************************************/
1967 /****************************************************************************/
1968
1969 #define NGENE_ID(_subvend, _subdev, _driverdata) { \
1970         .vendor = NGENE_VID, .device = NGENE_PID, \
1971         .subvendor = _subvend, .subdevice = _subdev, \
1972         .driver_data = (unsigned long) &_driverdata }
1973
1974 /****************************************************************************/
1975
1976 static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
1977         NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2),
1978         NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2),
1979         NGENE_ID(0x18c3, 0xdb01, ngene_info_satixS2),
1980         NGENE_ID(0x18c3, 0xdb02, ngene_info_satixS2v2),
1981         NGENE_ID(0x18c3, 0xdd00, ngene_info_cineS2v5),
1982         {0}
1983 };
1984 MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
1985
1986 /****************************************************************************/
1987 /* Init/Exit ****************************************************************/
1988 /****************************************************************************/
1989
1990 static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
1991                                              enum pci_channel_state state)
1992 {
1993         printk(KERN_ERR DEVICE_NAME ": PCI error\n");
1994         if (state == pci_channel_io_perm_failure)
1995                 return PCI_ERS_RESULT_DISCONNECT;
1996         if (state == pci_channel_io_frozen)
1997                 return PCI_ERS_RESULT_NEED_RESET;
1998         return PCI_ERS_RESULT_CAN_RECOVER;
1999 }
2000
2001 static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
2002 {
2003         printk(KERN_INFO DEVICE_NAME ": link reset\n");
2004         return 0;
2005 }
2006
2007 static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
2008 {
2009         printk(KERN_INFO DEVICE_NAME ": slot reset\n");
2010         return 0;
2011 }
2012
2013 static void ngene_resume(struct pci_dev *dev)
2014 {
2015         printk(KERN_INFO DEVICE_NAME ": resume\n");
2016 }
2017
2018 static struct pci_error_handlers ngene_errors = {
2019         .error_detected = ngene_error_detected,
2020         .link_reset = ngene_link_reset,
2021         .slot_reset = ngene_slot_reset,
2022         .resume = ngene_resume,
2023 };
2024
2025 static struct pci_driver ngene_pci_driver = {
2026         .name        = "ngene",
2027         .id_table    = ngene_id_tbl,
2028         .probe       = ngene_probe,
2029         .remove      = __devexit_p(ngene_remove),
2030         .err_handler = &ngene_errors,
2031 };
2032
2033 static __init int module_init_ngene(void)
2034 {
2035         printk(KERN_INFO
2036                "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
2037         return pci_register_driver(&ngene_pci_driver);
2038 }
2039
2040 static __exit void module_exit_ngene(void)
2041 {
2042         pci_unregister_driver(&ngene_pci_driver);
2043 }
2044
2045 module_init(module_init_ngene);
2046 module_exit(module_exit_ngene);
2047
2048 MODULE_DESCRIPTION("nGene");
2049 MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
2050 MODULE_LICENSE("GPL");