drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static const struct {
 290         int trans;
 291         u32 req_param[NUM_TRANS];
 292         u32 opt_param[NUM_TRANS];
 293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 294         [IB_QPS_RESET] = {
 295                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 296                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 297                 [IB_QPS_INIT]  = {
 298                         .trans = MTHCA_TRANS_RST2INIT,
 299                         .req_param = {
 300                                 [UD]  = (IB_QP_PKEY_INDEX |
 301                                          IB_QP_PORT       |
 302                                          IB_QP_QKEY),
 303                                 [UC]  = (IB_QP_PKEY_INDEX |
 304                                          IB_QP_PORT       |
 305                                          IB_QP_ACCESS_FLAGS),
 306                                 [RC]  = (IB_QP_PKEY_INDEX |
 307                                          IB_QP_PORT       |
 308                                          IB_QP_ACCESS_FLAGS),
 309                                 [MLX] = (IB_QP_PKEY_INDEX |
 310                                          IB_QP_QKEY),
 311                         },
 312                         /* bug-for-bug compatibility with VAPI: */
 313                         .opt_param = {
 314                                 [MLX] = IB_QP_PORT
 315                         }
 316                 },
 317         },
 318         [IB_QPS_INIT]  = {
 319                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 320                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 321                 [IB_QPS_INIT]  = {
 322                         .trans = MTHCA_TRANS_INIT2INIT,
 323                         .opt_param = {
 324                                 [UD]  = (IB_QP_PKEY_INDEX |
 325                                          IB_QP_PORT       |
 326                                          IB_QP_QKEY),
 327                                 [UC]  = (IB_QP_PKEY_INDEX |
 328                                          IB_QP_PORT       |
 329                                          IB_QP_ACCESS_FLAGS),
 330                                 [RC]  = (IB_QP_PKEY_INDEX |
 331                                          IB_QP_PORT       |
 332                                          IB_QP_ACCESS_FLAGS),
 333                                 [MLX] = (IB_QP_PKEY_INDEX |
 334                                          IB_QP_QKEY),
 335                         }
 336                 },
 337                 [IB_QPS_RTR]   = {
 338                         .trans = MTHCA_TRANS_INIT2RTR,
 339                         .req_param = {
 340                                 [UC]  = (IB_QP_AV                  |
 341                                          IB_QP_PATH_MTU            |
 342                                          IB_QP_DEST_QPN            |
 343                                          IB_QP_RQ_PSN),
 344                                 [RC]  = (IB_QP_AV                  |
 345                                          IB_QP_PATH_MTU            |
 346                                          IB_QP_DEST_QPN            |
 347                                          IB_QP_RQ_PSN              |
 348                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 349                                          IB_QP_MIN_RNR_TIMER),
 350                         },
 351                         .opt_param = {
 352                                 [UD]  = (IB_QP_PKEY_INDEX |
 353                                          IB_QP_QKEY),
 354                                 [UC]  = (IB_QP_ALT_PATH     |
 355                                          IB_QP_ACCESS_FLAGS |
 356                                          IB_QP_PKEY_INDEX),
 357                                 [RC]  = (IB_QP_ALT_PATH     |
 358                                          IB_QP_ACCESS_FLAGS |
 359                                          IB_QP_PKEY_INDEX),
 360                                 [MLX] = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_QKEY),
 362                         }
 363                 }
 364         },
 365         [IB_QPS_RTR]   = {
 366                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 367                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 368                 [IB_QPS_RTS]   = {
 369                         .trans = MTHCA_TRANS_RTR2RTS,
 370                         .req_param = {
 371                                 [UD]  = IB_QP_SQ_PSN,
 372                                 [UC]  = IB_QP_SQ_PSN,
 373                                 [RC]  = (IB_QP_TIMEOUT           |
 374                                          IB_QP_RETRY_CNT         |
 375                                          IB_QP_RNR_RETRY         |
 376                                          IB_QP_SQ_PSN            |
 377                                          IB_QP_MAX_QP_RD_ATOMIC),
 378                                 [MLX] = IB_QP_SQ_PSN,
 379                         },
 380                         .opt_param = {
 381                                 [UD]  = (IB_QP_CUR_STATE             |
 382                                          IB_QP_QKEY),
 383                                 [UC]  = (IB_QP_CUR_STATE             |
 384                                          IB_QP_ALT_PATH              |
 385                                          IB_QP_ACCESS_FLAGS          |
 386                                          IB_QP_PKEY_INDEX            |
 387                                          IB_QP_PATH_MIG_STATE),
 388                                 [RC]  = (IB_QP_CUR_STATE             |
 389                                          IB_QP_ALT_PATH              |
 390                                          IB_QP_ACCESS_FLAGS          |
 391                                          IB_QP_PKEY_INDEX            |
 392                                          IB_QP_MIN_RNR_TIMER         |
 393                                          IB_QP_PATH_MIG_STATE),
 394                                 [MLX] = (IB_QP_CUR_STATE             |
 395                                          IB_QP_QKEY),
 396                         }
 397                 }
 398         },
 399         [IB_QPS_RTS]   = {
 400                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 401                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 402                 [IB_QPS_RTS]   = {
 403                         .trans = MTHCA_TRANS_RTS2RTS,
 404                         .opt_param = {
 405                                 [UD]  = (IB_QP_CUR_STATE             |
 406                                          IB_QP_QKEY),
 407                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 408                                          IB_QP_ALT_PATH              |
 409                                          IB_QP_PATH_MIG_STATE),
 410                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 411                                          IB_QP_ALT_PATH              |
 412                                          IB_QP_PATH_MIG_STATE        |
 413                                          IB_QP_MIN_RNR_TIMER),
 414                                 [MLX] = (IB_QP_CUR_STATE             |
 415                                          IB_QP_QKEY),
 416                         }
 417                 },
 418                 [IB_QPS_SQD]   = {
 419                         .trans = MTHCA_TRANS_RTS2SQD,
 420                 },
 421         },
 422         [IB_QPS_SQD]   = {
 423                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 424                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 425                 [IB_QPS_RTS]   = {
 426                         .trans = MTHCA_TRANS_SQD2RTS,
 427                         .opt_param = {
 428                                 [UD]  = (IB_QP_CUR_STATE             |
 429                                          IB_QP_QKEY),
 430                                 [UC]  = (IB_QP_CUR_STATE             |
 431                                          IB_QP_ALT_PATH              |
 432                                          IB_QP_ACCESS_FLAGS          |
 433                                          IB_QP_PATH_MIG_STATE),
 434                                 [RC]  = (IB_QP_CUR_STATE             |
 435                                          IB_QP_ALT_PATH              |
 436                                          IB_QP_ACCESS_FLAGS          |
 437                                          IB_QP_MIN_RNR_TIMER         |
 438                                          IB_QP_PATH_MIG_STATE),
 439                                 [MLX] = (IB_QP_CUR_STATE             |
 440                                          IB_QP_QKEY),
 441                         }
 442                 },
 443                 [IB_QPS_SQD]   = {
 444                         .trans = MTHCA_TRANS_SQD2SQD,
 445                         .opt_param = {
 446                                 [UD]  = (IB_QP_PKEY_INDEX            |
 447                                          IB_QP_QKEY),
 448                                 [UC]  = (IB_QP_AV                    |
 449                                          IB_QP_CUR_STATE             |
 450                                          IB_QP_ALT_PATH              |
 451                                          IB_QP_ACCESS_FLAGS          |
 452                                          IB_QP_PKEY_INDEX            |
 453                                          IB_QP_PATH_MIG_STATE),
 454                                 [RC]  = (IB_QP_AV                    |
 455                                          IB_QP_TIMEOUT               |
 456                                          IB_QP_RETRY_CNT             |
 457                                          IB_QP_RNR_RETRY             |
 458                                          IB_QP_MAX_QP_RD_ATOMIC      |
 459                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 460                                          IB_QP_CUR_STATE             |
 461                                          IB_QP_ALT_PATH              |
 462                                          IB_QP_ACCESS_FLAGS          |
 463                                          IB_QP_PKEY_INDEX            |
 464                                          IB_QP_MIN_RNR_TIMER         |
 465                                          IB_QP_PATH_MIG_STATE),
 466                                 [MLX] = (IB_QP_PKEY_INDEX            |
 467                                          IB_QP_QKEY),
 468                         }
 469                 }
 470         },
 471         [IB_QPS_SQE]   = {
 472                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 473                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 474                 [IB_QPS_RTS]   = {
 475                         .trans = MTHCA_TRANS_SQERR2RTS,
 476                         .opt_param = {
 477                                 [UD]  = (IB_QP_CUR_STATE             |
 478                                          IB_QP_QKEY),
 479                                 [UC]  = IB_QP_CUR_STATE,
 480                                 [RC]  = (IB_QP_CUR_STATE             |
 481                                          IB_QP_MIN_RNR_TIMER),
 482                                 [MLX] = (IB_QP_CUR_STATE             |
 483                                          IB_QP_QKEY),
 484                         }
 485                 }
 486         },
 487         [IB_QPS_ERR] = {
 488                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 489                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 490         }
 491 };
 492
 493 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 494                         int attr_mask)
 495 {
 496         if (attr_mask & IB_QP_PKEY_INDEX)
 497                 sqp->pkey_index = attr->pkey_index;
 498         if (attr_mask & IB_QP_QKEY)
 499                 sqp->qkey = attr->qkey;
 500         if (attr_mask & IB_QP_SQ_PSN)
 501                 sqp->send_psn = attr->sq_psn;
 502 }
 503
 504 static void init_port(struct mthca_dev *dev, int port)
 505 {
 506         int err;
 507         u8 status;
 508         struct mthca_init_ib_param param;
 509
 510         memset(&param, 0, sizeof param);
 511
 512         param.port_width = dev->limits.port_width_cap;
 513         param.vl_cap     = dev->limits.vl_cap;
 514         param.mtu_cap    = dev->limits.mtu_cap;
 515         param.gid_cap    = dev->limits.gid_table_len;
 516         param.pkey_cap   = dev->limits.pkey_table_len;
 517
 518         err = mthca_INIT_IB(dev, &param, port, &status);
 519         if (err)
 520                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 521         if (status)
 522                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 523 }
 524
 525 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 526 {
 527         struct mthca_dev *dev = to_mdev(ibqp->device);
 528         struct mthca_qp *qp = to_mqp(ibqp);
 529         enum ib_qp_state cur_state, new_state;
 530         struct mthca_mailbox *mailbox;
 531         struct mthca_qp_param *qp_param;
 532         struct mthca_qp_context *qp_context;
 533         u32 req_param, opt_param;
 534         u8 status;
 535         int err;
 536
 537         if (attr_mask & IB_QP_CUR_STATE) {
 538                 if (attr->cur_qp_state != IB_QPS_RTR &&
 539                     attr->cur_qp_state != IB_QPS_RTS &&
 540                     attr->cur_qp_state != IB_QPS_SQD &&
 541                     attr->cur_qp_state != IB_QPS_SQE)
 542                         return -EINVAL;
 543                 else
 544                         cur_state = attr->cur_qp_state;
 545         } else {
 546                 spin_lock_irq(&qp->sq.lock);
 547                 spin_lock(&qp->rq.lock);
 548                 cur_state = qp->state;
 549                 spin_unlock(&qp->rq.lock);
 550                 spin_unlock_irq(&qp->sq.lock);
 551         }
 552
 553         if (attr_mask & IB_QP_STATE) {
 554                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 555                         return -EINVAL;
 556                 new_state = attr->qp_state;
 557         } else
 558                 new_state = cur_state;
 559
 560         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 561                 mthca_dbg(dev, "Illegal QP transition "
 562                           "%d->%d\n", cur_state, new_state);
 563                 return -EINVAL;
 564         }
 565
 566         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 567         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 568
 569         if ((req_param & attr_mask) != req_param) {
 570                 mthca_dbg(dev, "QP transition "
 571                           "%d->%d missing req attr 0x%08x\n",
 572                           cur_state, new_state,
 573                           req_param & ~attr_mask);
 574                 return -EINVAL;
 575         }
 576
 577         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 578                 mthca_dbg(dev, "QP transition (transport %d) "
 579                           "%d->%d has extra attr 0x%08x\n",
 580                           qp->transport,
 581                           cur_state, new_state,
 582                           attr_mask & ~(req_param | opt_param |
 583                                                  IB_QP_STATE));
 584                 return -EINVAL;
 585         }
 586
 587         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 588              attr->pkey_index >= dev->limits.pkey_table_len) {
 589                 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
 590                           attr->pkey_index,dev->limits.pkey_table_len-1);
 591                 return -EINVAL;
 592         }
 593
 594         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 595             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 596                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 597                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 598                 return -EINVAL;
 599         }
 600
 601         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 602             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 603                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 604                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 605                 return -EINVAL;
 606         }
 607
 608         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 609         if (IS_ERR(mailbox))
 610                 return PTR_ERR(mailbox);
 611         qp_param = mailbox->buf;
 612         qp_context = &qp_param->context;
 613         memset(qp_param, 0, sizeof *qp_param);
 614
 615         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 616                                              (to_mthca_st(qp->transport) << 16));
 617         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 618         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 619                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 620         else {
 621                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 622                 switch (attr->path_mig_state) {
 623                 case IB_MIG_MIGRATED:
 624                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 625                         break;
 626                 case IB_MIG_REARM:
 627                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 628                         break;
 629                 case IB_MIG_ARMED:
 630                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 631                         break;
 632                 }
 633         }
 634
 635         /* leave tavor_sched_queue as 0 */
 636
 637         if (qp->transport == MLX || qp->transport == UD)
 638                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 639         else if (attr_mask & IB_QP_PATH_MTU)
 640                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 641
 642         if (mthca_is_memfree(dev)) {
 643                 if (qp->rq.max)
 644                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 645                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 646
 647                 if (qp->sq.max)
 648                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 649                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 650         }
 651
 652         /* leave arbel_sched_queue as 0 */
 653
 654         if (qp->ibqp.uobject)
 655                 qp_context->usr_page =
 656                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 657         else
 658                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 659         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 660         if (attr_mask & IB_QP_DEST_QPN) {
 661                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 662         }
 663
 664         if (qp->transport == MLX)
 665                 qp_context->pri_path.port_pkey |=
 666                         cpu_to_be32(to_msqp(qp)->port << 24);
 667         else {
 668                 if (attr_mask & IB_QP_PORT) {
 669                         qp_context->pri_path.port_pkey |=
 670                                 cpu_to_be32(attr->port_num << 24);
 671                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 672                 }
 673         }
 674
 675         if (attr_mask & IB_QP_PKEY_INDEX) {
 676                 qp_context->pri_path.port_pkey |=
 677                         cpu_to_be32(attr->pkey_index);
 678                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 679         }
 680
 681         if (attr_mask & IB_QP_RNR_RETRY) {
 682                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 683                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 684         }
 685
 686         if (attr_mask & IB_QP_AV) {
 687                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 688                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 689                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 690                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 691                         qp_context->pri_path.g_mylmc |= 1 << 7;
 692                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 693                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 694                         qp_context->pri_path.sl_tclass_flowlabel =
 695                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 696                                             (attr->ah_attr.grh.traffic_class << 20) |
 697                                             (attr->ah_attr.grh.flow_label));
 698                         memcpy(qp_context->pri_path.rgid,
 699                                attr->ah_attr.grh.dgid.raw, 16);
 700                 } else {
 701                         qp_context->pri_path.sl_tclass_flowlabel =
 702                                 cpu_to_be32(attr->ah_attr.sl << 28);
 703                 }
 704                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 705         }
 706
 707         if (attr_mask & IB_QP_TIMEOUT) {
 708                 qp_context->pri_path.ackto = attr->timeout << 3;
 709                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 710         }
 711
 712         /* XXX alt_path */
 713
 714         /* leave rdd as 0 */
 715         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 716         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 717         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 718         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 719                                              (MTHCA_FLIGHT_LIMIT << 24) |
 720                                              MTHCA_QP_BIT_SRE           |
 721                                              MTHCA_QP_BIT_SWE           |
 722                                              MTHCA_QP_BIT_SAE);
 723         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 724                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 725         if (attr_mask & IB_QP_RETRY_CNT) {
 726                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 727                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 728         }
 729
 730         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 731                 if (attr->max_rd_atomic)
 732                         qp_context->params1 |=
 733                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 734                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 735         }
 736
 737         if (attr_mask & IB_QP_SQ_PSN)
 738                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 739         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 740
 741         if (mthca_is_memfree(dev)) {
 742                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 743                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 744         }
 745
 746         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 747                 qp_context->params2 |=
 748                         cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 749                                     MTHCA_QP_BIT_RWE : 0);
 750
 751                 /*
 752                  * Only enable RDMA reads and atomics if we have
 753                  * responder resources set to a non-zero value.
 754                  */
 755                 if (qp->resp_depth) {
 756                         qp_context->params2 |=
 757                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 758                                             MTHCA_QP_BIT_RRE : 0);
 759                         qp_context->params2 |=
 760                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 761                                             MTHCA_QP_BIT_RAE : 0);
 762                 }
 763
 764                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 765                                                         MTHCA_QP_OPTPAR_RRE |
 766                                                         MTHCA_QP_OPTPAR_RAE);
 767         }
 768
 769         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 770                 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
 771                         /*
 772                          * Lowering our responder resources to zero.
 773                          * Turn off reads RDMA and atomics as responder.
 774                          * (RRE/RAE in params2 already zero)
 775                          */
 776                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRE |
 777                                                                 MTHCA_QP_OPTPAR_RAE);
 778                 }
 779
 780                 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
 781                         /*
 782                          * Increasing our responder resources from
 783                          * zero.  Turn on RDMA reads and atomics as
 784                          * appropriate.
 785                          */
 786                         qp_context->params2 |=
 787                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 788                                             MTHCA_QP_BIT_RRE : 0);
 789                         qp_context->params2 |=
 790                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 791                                             MTHCA_QP_BIT_RAE : 0);
 792
 793                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRE |
 794                                                                 MTHCA_QP_OPTPAR_RAE);
 795                 }
 796
 797                 if (attr->max_dest_rd_atomic)
 798                         qp_context->params2 |=
 799                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 800
 801                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 802         }
 803
 804         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 805
 806         if (ibqp->srq)
 807                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 808
 809         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 810                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 811                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 812         }
 813         if (attr_mask & IB_QP_RQ_PSN)
 814                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 815
 816         qp_context->ra_buff_indx =
 817                 cpu_to_be32(dev->qp_table.rdb_base +
 818                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 819                              dev->qp_table.rdb_shift));
 820
 821         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 822
 823         if (mthca_is_memfree(dev))
 824                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 825
 826         if (attr_mask & IB_QP_QKEY) {
 827                 qp_context->qkey = cpu_to_be32(attr->qkey);
 828                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 829         }
 830
 831         if (ibqp->srq)
 832                 qp_context->srqn = cpu_to_be32(1 << 24 |
 833                                                to_msrq(ibqp->srq)->srqn);
 834
 835         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 836                               qp->qpn, 0, mailbox, 0, &status);
 837         if (status) {
 838                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 839                            state_table[cur_state][new_state].trans, status);
 840                 err = -EINVAL;
 841         }
 842
 843         if (!err) {
 844                 qp->state = new_state;
 845                 if (attr_mask & IB_QP_ACCESS_FLAGS)
 846                         qp->atomic_rd_en = attr->qp_access_flags;
 847                 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 848                         qp->resp_depth = attr->max_dest_rd_atomic;
 849         }
 850
 851         mthca_free_mailbox(dev, mailbox);
 852
 853         if (is_sqp(dev, qp))
 854                 store_attrs(to_msqp(qp), attr, attr_mask);
 855
 856         /*
 857          * If we moved QP0 to RTR, bring the IB link up; if we moved
 858          * QP0 to RESET or ERROR, bring the link back down.
 859          */
 860         if (is_qp0(dev, qp)) {
 861                 if (cur_state != IB_QPS_RTR &&
 862                     new_state == IB_QPS_RTR)
 863                         init_port(dev, to_msqp(qp)->port);
 864
 865                 if (cur_state != IB_QPS_RESET &&
 866                     cur_state != IB_QPS_ERR &&
 867                     (new_state == IB_QPS_RESET ||
 868                      new_state == IB_QPS_ERR))
 869                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 870         }
 871
 872         /*
 873          * If we moved a kernel QP to RESET, clean up all old CQ
 874          * entries and reinitialize the QP.
 875          */
 876         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 877                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 878                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 879                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 880                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 881                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 882
 883                 mthca_wq_init(&qp->sq);
 884                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 885
 886                 mthca_wq_init(&qp->rq);
 887                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 888
 889                 if (mthca_is_memfree(dev)) {
 890                         *qp->sq.db = 0;
 891                         *qp->rq.db = 0;
 892                 }
 893         }
 894
 895         return err;
 896 }
 897
 898 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 899                                  struct mthca_pd *pd,
 900                                  struct mthca_qp *qp)
 901 {
 902         int max_data_size;
 903
 904         /*
 905          * Calculate the maximum size of WQE s/g segments, excluding
 906          * the next segment and other non-data segments.
 907          */
 908         max_data_size = min(dev->limits.max_desc_sz, 1 << qp->sq.wqe_shift) -
 909                 sizeof (struct mthca_next_seg);
 910
 911         switch (qp->transport) {
 912         case MLX:
 913                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 914                 break;
 915
 916         case UD:
 917                 if (mthca_is_memfree(dev))
 918                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 919                 else
 920                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 921                 break;
 922
 923         default:
 924                 max_data_size -= sizeof (struct mthca_raddr_seg);
 925                 break;
 926         }
 927
 928         /* We don't support inline data for kernel QPs (yet). */
 929         if (!pd->ibpd.uobject)
 930                 qp->max_inline_data = 0;
 931         else
 932                 qp->max_inline_data = max_data_size - MTHCA_INLINE_HEADER_SIZE;
 933
 934         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 935                               max_data_size / sizeof (struct mthca_data_seg));
 936         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 937                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 938                                 sizeof (struct mthca_next_seg)) /
 939                                sizeof (struct mthca_data_seg));
 940 }
 941
 942 /*
 943  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 944  * rq.max_gs and sq.max_gs must all be assigned.
 945  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 946  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 947  * queue)
 948  */
 949 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 950                                struct mthca_pd *pd,
 951                                struct mthca_qp *qp)
 952 {
 953         int size;
 954         int err = -ENOMEM;
 955
 956         size = sizeof (struct mthca_next_seg) +
 957                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 958
 959         if (size > dev->limits.max_desc_sz)
 960                 return -EINVAL;
 961
 962         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 963              qp->rq.wqe_shift++)
 964                 ; /* nothing */
 965
 966         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 967         switch (qp->transport) {
 968         case MLX:
 969                 size += 2 * sizeof (struct mthca_data_seg);
 970                 break;
 971
 972         case UD:
 973                 size += mthca_is_memfree(dev) ?
 974                         sizeof (struct mthca_arbel_ud_seg) :
 975                         sizeof (struct mthca_tavor_ud_seg);
 976                 break;
 977
 978         case UC:
 979                 size += sizeof (struct mthca_raddr_seg);
 980                 break;
 981
 982         case RC:
 983                 size += sizeof (struct mthca_raddr_seg);
 984                 /*
 985                  * An atomic op will require an atomic segment, a
 986                  * remote address segment and one scatter entry.
 987                  */
 988                 size = max_t(int, size,
 989                              sizeof (struct mthca_atomic_seg) +
 990                              sizeof (struct mthca_raddr_seg) +
 991                              sizeof (struct mthca_data_seg));
 992                 break;
 993
 994         default:
 995                 break;
 996         }
 997
 998         /* Make sure that we have enough space for a bind request */
 999         size = max_t(int, size, sizeof (struct mthca_bind_seg));
1000
1001         size += sizeof (struct mthca_next_seg);
1002
1003         if (size > dev->limits.max_desc_sz)
1004                 return -EINVAL;
1005
1006         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1007              qp->sq.wqe_shift++)
1008                 ; /* nothing */
1009
1010         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1011                                     1 << qp->sq.wqe_shift);
1012
1013         /*
1014          * If this is a userspace QP, we don't actually have to
1015          * allocate anything.  All we need is to calculate the WQE
1016          * sizes and the send_wqe_offset, so we're done now.
1017          */
1018         if (pd->ibpd.uobject)
1019                 return 0;
1020
1021         size = PAGE_ALIGN(qp->send_wqe_offset +
1022                           (qp->sq.max << qp->sq.wqe_shift));
1023
1024         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1025                            GFP_KERNEL);
1026         if (!qp->wrid)
1027                 goto err_out;
1028
1029         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1030                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1031         if (err)
1032                 goto err_out;
1033
1034         return 0;
1035
1036 err_out:
1037         kfree(qp->wrid);
1038         return err;
1039 }
1040
1041 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1042                                struct mthca_qp *qp)
1043 {
1044         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1045                                        (qp->sq.max << qp->sq.wqe_shift)),
1046                        &qp->queue, qp->is_direct, &qp->mr);
1047         kfree(qp->wrid);
1048 }
1049
1050 static int mthca_map_memfree(struct mthca_dev *dev,
1051                              struct mthca_qp *qp)
1052 {
1053         int ret;
1054
1055         if (mthca_is_memfree(dev)) {
1056                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1057                 if (ret)
1058                         return ret;
1059
1060                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1061                 if (ret)
1062                         goto err_qpc;
1063
1064                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1065                                       qp->qpn << dev->qp_table.rdb_shift);
1066                 if (ret)
1067                         goto err_eqpc;
1068
1069         }
1070
1071         return 0;
1072
1073 err_eqpc:
1074         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1075
1076 err_qpc:
1077         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1078
1079         return ret;
1080 }
1081
1082 static void mthca_unmap_memfree(struct mthca_dev *dev,
1083                                 struct mthca_qp *qp)
1084 {
1085         mthca_table_put(dev, dev->qp_table.rdb_table,
1086                         qp->qpn << dev->qp_table.rdb_shift);
1087         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1088         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1089 }
1090
1091 static int mthca_alloc_memfree(struct mthca_dev *dev,
1092                                struct mthca_qp *qp)
1093 {
1094         int ret = 0;
1095
1096         if (mthca_is_memfree(dev)) {
1097                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1098                                                  qp->qpn, &qp->rq.db);
1099                 if (qp->rq.db_index < 0)
1100                         return ret;
1101
1102                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1103                                                  qp->qpn, &qp->sq.db);
1104                 if (qp->sq.db_index < 0)
1105                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1106         }
1107
1108         return ret;
1109 }
1110
1111 static void mthca_free_memfree(struct mthca_dev *dev,
1112                                struct mthca_qp *qp)
1113 {
1114         if (mthca_is_memfree(dev)) {
1115                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1116                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1117         }
1118 }
1119
1120 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1121                                  struct mthca_pd *pd,
1122                                  struct mthca_cq *send_cq,
1123                                  struct mthca_cq *recv_cq,
1124                                  enum ib_sig_type send_policy,
1125                                  struct mthca_qp *qp)
1126 {
1127         int ret;
1128         int i;
1129
1130         atomic_set(&qp->refcount, 1);
1131         init_waitqueue_head(&qp->wait);
1132         qp->state        = IB_QPS_RESET;
1133         qp->atomic_rd_en = 0;
1134         qp->resp_depth   = 0;
1135         qp->sq_policy    = send_policy;
1136         mthca_wq_init(&qp->sq);
1137         mthca_wq_init(&qp->rq);
1138
1139         ret = mthca_map_memfree(dev, qp);
1140         if (ret)
1141                 return ret;
1142
1143         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1144         if (ret) {
1145                 mthca_unmap_memfree(dev, qp);
1146                 return ret;
1147         }
1148
1149         mthca_adjust_qp_caps(dev, pd, qp);
1150
1151         /*
1152          * If this is a userspace QP, we're done now.  The doorbells
1153          * will be allocated and buffers will be initialized in
1154          * userspace.
1155          */
1156         if (pd->ibpd.uobject)
1157                 return 0;
1158
1159         ret = mthca_alloc_memfree(dev, qp);
1160         if (ret) {
1161                 mthca_free_wqe_buf(dev, qp);
1162                 mthca_unmap_memfree(dev, qp);
1163                 return ret;
1164         }
1165
1166         if (mthca_is_memfree(dev)) {
1167                 struct mthca_next_seg *next;
1168                 struct mthca_data_seg *scatter;
1169                 int size = (sizeof (struct mthca_next_seg) +
1170                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1171
1172                 for (i = 0; i < qp->rq.max; ++i) {
1173                         next = get_recv_wqe(qp, i);
1174                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1175                                                    qp->rq.wqe_shift);
1176                         next->ee_nds = cpu_to_be32(size);
1177
1178                         for (scatter = (void *) (next + 1);
1179                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1180                              ++scatter)
1181                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1182                 }
1183
1184                 for (i = 0; i < qp->sq.max; ++i) {
1185                         next = get_send_wqe(qp, i);
1186                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1187                                                     qp->sq.wqe_shift) +
1188                                                    qp->send_wqe_offset);
1189                 }
1190         }
1191
1192         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1193         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1194
1195         return 0;
1196 }
1197
1198 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1199                              struct mthca_qp *qp)
1200 {
1201         /* Sanity check QP size before proceeding */
1202         if (cap->max_send_wr  > dev->limits.max_wqes ||
1203             cap->max_recv_wr  > dev->limits.max_wqes ||
1204             cap->max_send_sge > dev->limits.max_sg   ||
1205             cap->max_recv_sge > dev->limits.max_sg)
1206                 return -EINVAL;
1207
1208         if (mthca_is_memfree(dev)) {
1209                 qp->rq.max = cap->max_recv_wr ?
1210                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1211                 qp->sq.max = cap->max_send_wr ?
1212                         roundup_pow_of_two(cap->max_send_wr) : 0;
1213         } else {
1214                 qp->rq.max = cap->max_recv_wr;
1215                 qp->sq.max = cap->max_send_wr;
1216         }
1217
1218         qp->rq.max_gs = cap->max_recv_sge;
1219         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1220                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1221                                     MTHCA_INLINE_CHUNK_SIZE) /
1222                               sizeof (struct mthca_data_seg));
1223
1224         /*
1225          * For MLX transport we need 2 extra S/G entries:
1226          * one for the header and one for the checksum at the end
1227          */
1228         if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1229             qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1230                 return -EINVAL;
1231
1232         return 0;
1233 }
1234
1235 int mthca_alloc_qp(struct mthca_dev *dev,
1236                    struct mthca_pd *pd,
1237                    struct mthca_cq *send_cq,
1238                    struct mthca_cq *recv_cq,
1239                    enum ib_qp_type type,
1240                    enum ib_sig_type send_policy,
1241                    struct ib_qp_cap *cap,
1242                    struct mthca_qp *qp)
1243 {
1244         int err;
1245
1246         err = mthca_set_qp_size(dev, cap, qp);
1247         if (err)
1248                 return err;
1249
1250         switch (type) {
1251         case IB_QPT_RC: qp->transport = RC; break;
1252         case IB_QPT_UC: qp->transport = UC; break;
1253         case IB_QPT_UD: qp->transport = UD; break;
1254         default: return -EINVAL;
1255         }
1256
1257         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1258         if (qp->qpn == -1)
1259                 return -ENOMEM;
1260
1261         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1262                                     send_policy, qp);
1263         if (err) {
1264                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1265                 return err;
1266         }
1267
1268         spin_lock_irq(&dev->qp_table.lock);
1269         mthca_array_set(&dev->qp_table.qp,
1270                         qp->qpn & (dev->limits.num_qps - 1), qp);
1271         spin_unlock_irq(&dev->qp_table.lock);
1272
1273         return 0;
1274 }
1275
1276 int mthca_alloc_sqp(struct mthca_dev *dev,
1277                     struct mthca_pd *pd,
1278                     struct mthca_cq *send_cq,
1279                     struct mthca_cq *recv_cq,
1280                     enum ib_sig_type send_policy,
1281                     struct ib_qp_cap *cap,
1282                     int qpn,
1283                     int port,
1284                     struct mthca_sqp *sqp)
1285 {
1286         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1287         int err;
1288
1289         err = mthca_set_qp_size(dev, cap, &sqp->qp);
1290         if (err)
1291                 return err;
1292
1293         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1294         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1295                                              &sqp->header_dma, GFP_KERNEL);
1296         if (!sqp->header_buf)
1297                 return -ENOMEM;
1298
1299         spin_lock_irq(&dev->qp_table.lock);
1300         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1301                 err = -EBUSY;
1302         else
1303                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1304         spin_unlock_irq(&dev->qp_table.lock);
1305
1306         if (err)
1307                 goto err_out;
1308
1309         sqp->port = port;
1310         sqp->qp.qpn       = mqpn;
1311         sqp->qp.transport = MLX;
1312
1313         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1314                                     send_policy, &sqp->qp);
1315         if (err)
1316                 goto err_out_free;
1317
1318         atomic_inc(&pd->sqp_count);
1319
1320         return 0;
1321
1322  err_out_free:
1323         /*
1324          * Lock CQs here, so that CQ polling code can do QP lookup
1325          * without taking a lock.
1326          */
1327         spin_lock_irq(&send_cq->lock);
1328         if (send_cq != recv_cq)
1329                 spin_lock(&recv_cq->lock);
1330
1331         spin_lock(&dev->qp_table.lock);
1332         mthca_array_clear(&dev->qp_table.qp, mqpn);
1333         spin_unlock(&dev->qp_table.lock);
1334
1335         if (send_cq != recv_cq)
1336                 spin_unlock(&recv_cq->lock);
1337         spin_unlock_irq(&send_cq->lock);
1338
1339  err_out:
1340         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1341                           sqp->header_buf, sqp->header_dma);
1342
1343         return err;
1344 }
1345
1346 void mthca_free_qp(struct mthca_dev *dev,
1347                    struct mthca_qp *qp)
1348 {
1349         u8 status;
1350         struct mthca_cq *send_cq;
1351         struct mthca_cq *recv_cq;
1352
1353         send_cq = to_mcq(qp->ibqp.send_cq);
1354         recv_cq = to_mcq(qp->ibqp.recv_cq);
1355
1356         /*
1357          * Lock CQs here, so that CQ polling code can do QP lookup
1358          * without taking a lock.
1359          */
1360         spin_lock_irq(&send_cq->lock);
1361         if (send_cq != recv_cq)
1362                 spin_lock(&recv_cq->lock);
1363
1364         spin_lock(&dev->qp_table.lock);
1365         mthca_array_clear(&dev->qp_table.qp,
1366                           qp->qpn & (dev->limits.num_qps - 1));
1367         spin_unlock(&dev->qp_table.lock);
1368
1369         if (send_cq != recv_cq)
1370                 spin_unlock(&recv_cq->lock);
1371         spin_unlock_irq(&send_cq->lock);
1372
1373         atomic_dec(&qp->refcount);
1374         wait_event(qp->wait, !atomic_read(&qp->refcount));
1375
1376         if (qp->state != IB_QPS_RESET)
1377                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1378
1379         /*
1380          * If this is a userspace QP, the buffers, MR, CQs and so on
1381          * will be cleaned up in userspace, so all we have to do is
1382          * unref the mem-free tables and free the QPN in our table.
1383          */
1384         if (!qp->ibqp.uobject) {
1385                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1386                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1387                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1388                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1389                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1390
1391                 mthca_free_memfree(dev, qp);
1392                 mthca_free_wqe_buf(dev, qp);
1393         }
1394
1395         mthca_unmap_memfree(dev, qp);
1396
1397         if (is_sqp(dev, qp)) {
1398                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1399                 dma_free_coherent(&dev->pdev->dev,
1400                                   to_msqp(qp)->header_buf_size,
1401                                   to_msqp(qp)->header_buf,
1402                                   to_msqp(qp)->header_dma);
1403         } else
1404                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1405 }
1406
1407 /* Create UD header for an MLX send and build a data segment for it */
1408 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1409                             int ind, struct ib_send_wr *wr,
1410                             struct mthca_mlx_seg *mlx,
1411                             struct mthca_data_seg *data)
1412 {
1413         int header_size;
1414         int err;
1415         u16 pkey;
1416
1417         ib_ud_header_init(256, /* assume a MAD */
1418                           sqp->ud_header.grh_present,
1419                           &sqp->ud_header);
1420
1421         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1422         if (err)
1423                 return err;
1424         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1425         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1426                                   (sqp->ud_header.lrh.destination_lid ==
1427                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1428                                   (sqp->ud_header.lrh.service_level << 8));
1429         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1430         mlx->vcrc = 0;
1431
1432         switch (wr->opcode) {
1433         case IB_WR_SEND:
1434                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1435                 sqp->ud_header.immediate_present = 0;
1436                 break;
1437         case IB_WR_SEND_WITH_IMM:
1438                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1439                 sqp->ud_header.immediate_present = 1;
1440                 sqp->ud_header.immediate_data = wr->imm_data;
1441                 break;
1442         default:
1443                 return -EINVAL;
1444         }
1445
1446         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1447         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1448                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1449         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1450         if (!sqp->qp.ibqp.qp_num)
1451                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1452                                    sqp->pkey_index, &pkey);
1453         else
1454                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1455                                    wr->wr.ud.pkey_index, &pkey);
1456         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1457         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1458         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1459         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1460                                                sqp->qkey : wr->wr.ud.remote_qkey);
1461         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1462
1463         header_size = ib_ud_header_pack(&sqp->ud_header,
1464                                         sqp->header_buf +
1465                                         ind * MTHCA_UD_HEADER_SIZE);
1466
1467         data->byte_count = cpu_to_be32(header_size);
1468         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1469         data->addr       = cpu_to_be64(sqp->header_dma +
1470                                        ind * MTHCA_UD_HEADER_SIZE);
1471
1472         return 0;
1473 }
1474
1475 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1476                                     struct ib_cq *ib_cq)
1477 {
1478         unsigned cur;
1479         struct mthca_cq *cq;
1480
1481         cur = wq->head - wq->tail;
1482         if (likely(cur + nreq < wq->max))
1483                 return 0;
1484
1485         cq = to_mcq(ib_cq);
1486         spin_lock(&cq->lock);
1487         cur = wq->head - wq->tail;
1488         spin_unlock(&cq->lock);
1489
1490         return cur + nreq >= wq->max;
1491 }
1492
1493 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1494                           struct ib_send_wr **bad_wr)
1495 {
1496         struct mthca_dev *dev = to_mdev(ibqp->device);
1497         struct mthca_qp *qp = to_mqp(ibqp);
1498         void *wqe;
1499         void *prev_wqe;
1500         unsigned long flags;
1501         int err = 0;
1502         int nreq;
1503         int i;
1504         int size;
1505         int size0 = 0;
1506         u32 f0 = 0;
1507         int ind;
1508         u8 op0 = 0;
1509
1510         spin_lock_irqsave(&qp->sq.lock, flags);
1511
1512         /* XXX check that state is OK to post send */
1513
1514         ind = qp->sq.next_ind;
1515
1516         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1517                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1518                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1519                                         " %d max, %d nreq)\n", qp->qpn,
1520                                         qp->sq.head, qp->sq.tail,
1521                                         qp->sq.max, nreq);
1522                         err = -ENOMEM;
1523                         *bad_wr = wr;
1524                         goto out;
1525                 }
1526
1527                 wqe = get_send_wqe(qp, ind);
1528                 prev_wqe = qp->sq.last;
1529                 qp->sq.last = wqe;
1530
1531                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1532                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1533                 ((struct mthca_next_seg *) wqe)->flags =
1534                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1535                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1536                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1537                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1538                         cpu_to_be32(1);
1539                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1540                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1541                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1542
1543                 wqe += sizeof (struct mthca_next_seg);
1544                 size = sizeof (struct mthca_next_seg) / 16;
1545
1546                 switch (qp->transport) {
1547                 case RC:
1548                         switch (wr->opcode) {
1549                         case IB_WR_ATOMIC_CMP_AND_SWP:
1550                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1551                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1552                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1553                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1554                                         cpu_to_be32(wr->wr.atomic.rkey);
1555                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1556
1557                                 wqe += sizeof (struct mthca_raddr_seg);
1558
1559                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1560                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1561                                                 cpu_to_be64(wr->wr.atomic.swap);
1562                                         ((struct mthca_atomic_seg *) wqe)->compare =
1563                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1564                                 } else {
1565                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1566                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1567                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1568                                 }
1569
1570                                 wqe += sizeof (struct mthca_atomic_seg);
1571                                 size += (sizeof (struct mthca_raddr_seg) +
1572                                          sizeof (struct mthca_atomic_seg)) / 16;
1573                                 break;
1574
1575                         case IB_WR_RDMA_WRITE:
1576                         case IB_WR_RDMA_WRITE_WITH_IMM:
1577                         case IB_WR_RDMA_READ:
1578                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1579                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1580                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1581                                         cpu_to_be32(wr->wr.rdma.rkey);
1582                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1583                                 wqe += sizeof (struct mthca_raddr_seg);
1584                                 size += sizeof (struct mthca_raddr_seg) / 16;
1585                                 break;
1586
1587                         default:
1588                                 /* No extra segments required for sends */
1589                                 break;
1590                         }
1591
1592                         break;
1593
1594                 case UC:
1595                         switch (wr->opcode) {
1596                         case IB_WR_RDMA_WRITE:
1597                         case IB_WR_RDMA_WRITE_WITH_IMM:
1598                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1599                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1600                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1601                                         cpu_to_be32(wr->wr.rdma.rkey);
1602                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1603                                 wqe += sizeof (struct mthca_raddr_seg);
1604                                 size += sizeof (struct mthca_raddr_seg) / 16;
1605                                 break;
1606
1607                         default:
1608                                 /* No extra segments required for sends */
1609                                 break;
1610                         }
1611
1612                         break;
1613
1614                 case UD:
1615                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1616                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1617                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1618                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1619                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1620                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1621                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1622                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1623
1624                         wqe += sizeof (struct mthca_tavor_ud_seg);
1625                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1626                         break;
1627
1628                 case MLX:
1629                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1630                                                wqe - sizeof (struct mthca_next_seg),
1631                                                wqe);
1632                         if (err) {
1633                                 *bad_wr = wr;
1634                                 goto out;
1635                         }
1636                         wqe += sizeof (struct mthca_data_seg);
1637                         size += sizeof (struct mthca_data_seg) / 16;
1638                         break;
1639                 }
1640
1641                 if (wr->num_sge > qp->sq.max_gs) {
1642                         mthca_err(dev, "too many gathers\n");
1643                         err = -EINVAL;
1644                         *bad_wr = wr;
1645                         goto out;
1646                 }
1647
1648                 for (i = 0; i < wr->num_sge; ++i) {
1649                         ((struct mthca_data_seg *) wqe)->byte_count =
1650                                 cpu_to_be32(wr->sg_list[i].length);
1651                         ((struct mthca_data_seg *) wqe)->lkey =
1652                                 cpu_to_be32(wr->sg_list[i].lkey);
1653                         ((struct mthca_data_seg *) wqe)->addr =
1654                                 cpu_to_be64(wr->sg_list[i].addr);
1655                         wqe += sizeof (struct mthca_data_seg);
1656                         size += sizeof (struct mthca_data_seg) / 16;
1657                 }
1658
1659                 /* Add one more inline data segment for ICRC */
1660                 if (qp->transport == MLX) {
1661                         ((struct mthca_data_seg *) wqe)->byte_count =
1662                                 cpu_to_be32((1 << 31) | 4);
1663                         ((u32 *) wqe)[1] = 0;
1664                         wqe += sizeof (struct mthca_data_seg);
1665                         size += sizeof (struct mthca_data_seg) / 16;
1666                 }
1667
1668                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1669
1670                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1671                         mthca_err(dev, "opcode invalid\n");
1672                         err = -EINVAL;
1673                         *bad_wr = wr;
1674                         goto out;
1675                 }
1676
1677                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1678                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1679                                      qp->send_wqe_offset) |
1680                                     mthca_opcode[wr->opcode]);
1681                 wmb();
1682                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1683                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1684
1685                 if (!size0) {
1686                         size0 = size;
1687                         op0   = mthca_opcode[wr->opcode];
1688                 }
1689
1690                 ++ind;
1691                 if (unlikely(ind >= qp->sq.max))
1692                         ind -= qp->sq.max;
1693         }
1694
1695 out:
1696         if (likely(nreq)) {
1697                 __be32 doorbell[2];
1698
1699                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1700                                            qp->send_wqe_offset) | f0 | op0);
1701                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1702
1703                 wmb();
1704
1705                 mthca_write64(doorbell,
1706                               dev->kar + MTHCA_SEND_DOORBELL,
1707                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1708         }
1709
1710         qp->sq.next_ind = ind;
1711         qp->sq.head    += nreq;
1712
1713         spin_unlock_irqrestore(&qp->sq.lock, flags);
1714         return err;
1715 }
1716
1717 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1718                              struct ib_recv_wr **bad_wr)
1719 {
1720         struct mthca_dev *dev = to_mdev(ibqp->device);
1721         struct mthca_qp *qp = to_mqp(ibqp);
1722         __be32 doorbell[2];
1723         unsigned long flags;
1724         int err = 0;
1725         int nreq;
1726         int i;
1727         int size;
1728         int size0 = 0;
1729         int ind;
1730         void *wqe;
1731         void *prev_wqe;
1732
1733         spin_lock_irqsave(&qp->rq.lock, flags);
1734
1735         /* XXX check that state is OK to post receive */
1736
1737         ind = qp->rq.next_ind;
1738
1739         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1740                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1741                         nreq = 0;
1742
1743                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1744                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1745
1746                         wmb();
1747
1748                         mthca_write64(doorbell,
1749                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1750                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1751
1752                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1753                         size0 = 0;
1754                 }
1755
1756                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1757                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1758                                         " %d max, %d nreq)\n", qp->qpn,
1759                                         qp->rq.head, qp->rq.tail,
1760                                         qp->rq.max, nreq);
1761                         err = -ENOMEM;
1762                         *bad_wr = wr;
1763                         goto out;
1764                 }
1765
1766                 wqe = get_recv_wqe(qp, ind);
1767                 prev_wqe = qp->rq.last;
1768                 qp->rq.last = wqe;
1769
1770                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1771                 ((struct mthca_next_seg *) wqe)->ee_nds =
1772                         cpu_to_be32(MTHCA_NEXT_DBD);
1773                 ((struct mthca_next_seg *) wqe)->flags = 0;
1774
1775                 wqe += sizeof (struct mthca_next_seg);
1776                 size = sizeof (struct mthca_next_seg) / 16;
1777
1778                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1779                         err = -EINVAL;
1780                         *bad_wr = wr;
1781                         goto out;
1782                 }
1783
1784                 for (i = 0; i < wr->num_sge; ++i) {
1785                         ((struct mthca_data_seg *) wqe)->byte_count =
1786                                 cpu_to_be32(wr->sg_list[i].length);
1787                         ((struct mthca_data_seg *) wqe)->lkey =
1788                                 cpu_to_be32(wr->sg_list[i].lkey);
1789                         ((struct mthca_data_seg *) wqe)->addr =
1790                                 cpu_to_be64(wr->sg_list[i].addr);
1791                         wqe += sizeof (struct mthca_data_seg);
1792                         size += sizeof (struct mthca_data_seg) / 16;
1793                 }
1794
1795                 qp->wrid[ind] = wr->wr_id;
1796
1797                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1798                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1799                 wmb();
1800                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1801                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1802
1803                 if (!size0)
1804                         size0 = size;
1805
1806                 ++ind;
1807                 if (unlikely(ind >= qp->rq.max))
1808                         ind -= qp->rq.max;
1809         }
1810
1811 out:
1812         if (likely(nreq)) {
1813                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1814                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1815
1816                 wmb();
1817
1818                 mthca_write64(doorbell,
1819                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1820                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1821         }
1822
1823         qp->rq.next_ind = ind;
1824         qp->rq.head    += nreq;
1825
1826         spin_unlock_irqrestore(&qp->rq.lock, flags);
1827         return err;
1828 }
1829
1830 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1831                           struct ib_send_wr **bad_wr)
1832 {
1833         struct mthca_dev *dev = to_mdev(ibqp->device);
1834         struct mthca_qp *qp = to_mqp(ibqp);
1835         __be32 doorbell[2];
1836         void *wqe;
1837         void *prev_wqe;
1838         unsigned long flags;
1839         int err = 0;
1840         int nreq;
1841         int i;
1842         int size;
1843         int size0 = 0;
1844         u32 f0 = 0;
1845         int ind;
1846         u8 op0 = 0;
1847
1848         spin_lock_irqsave(&qp->sq.lock, flags);
1849
1850         /* XXX check that state is OK to post send */
1851
1852         ind = qp->sq.head & (qp->sq.max - 1);
1853
1854         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1855                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1856                         nreq = 0;
1857
1858                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1859                                                   ((qp->sq.head & 0xffff) << 8) |
1860                                                   f0 | op0);
1861                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1862
1863                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1864                         size0 = 0;
1865
1866                         /*
1867                          * Make sure that descriptors are written before
1868                          * doorbell record.
1869                          */
1870                         wmb();
1871                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1872
1873                         /*
1874                          * Make sure doorbell record is written before we
1875                          * write MMIO send doorbell.
1876                          */
1877                         wmb();
1878                         mthca_write64(doorbell,
1879                                       dev->kar + MTHCA_SEND_DOORBELL,
1880                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1881                 }
1882
1883                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1884                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1885                                         " %d max, %d nreq)\n", qp->qpn,
1886                                         qp->sq.head, qp->sq.tail,
1887                                         qp->sq.max, nreq);
1888                         err = -ENOMEM;
1889                         *bad_wr = wr;
1890                         goto out;
1891                 }
1892
1893                 wqe = get_send_wqe(qp, ind);
1894                 prev_wqe = qp->sq.last;
1895                 qp->sq.last = wqe;
1896
1897                 ((struct mthca_next_seg *) wqe)->flags =
1898                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1899                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1900                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1901                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1902                         cpu_to_be32(1);
1903                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1904                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1905                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1906
1907                 wqe += sizeof (struct mthca_next_seg);
1908                 size = sizeof (struct mthca_next_seg) / 16;
1909
1910                 switch (qp->transport) {
1911                 case RC:
1912                         switch (wr->opcode) {
1913                         case IB_WR_ATOMIC_CMP_AND_SWP:
1914                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1915                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1916                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1917                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1918                                         cpu_to_be32(wr->wr.atomic.rkey);
1919                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1920
1921                                 wqe += sizeof (struct mthca_raddr_seg);
1922
1923                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1924                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1925                                                 cpu_to_be64(wr->wr.atomic.swap);
1926                                         ((struct mthca_atomic_seg *) wqe)->compare =
1927                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1928                                 } else {
1929                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1930                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1931                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1932                                 }
1933
1934                                 wqe += sizeof (struct mthca_atomic_seg);
1935                                 size += (sizeof (struct mthca_raddr_seg) +
1936                                          sizeof (struct mthca_atomic_seg)) / 16;
1937                                 break;
1938
1939                         case IB_WR_RDMA_READ:
1940                         case IB_WR_RDMA_WRITE:
1941                         case IB_WR_RDMA_WRITE_WITH_IMM:
1942                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1943                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1944                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1945                                         cpu_to_be32(wr->wr.rdma.rkey);
1946                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1947                                 wqe += sizeof (struct mthca_raddr_seg);
1948                                 size += sizeof (struct mthca_raddr_seg) / 16;
1949                                 break;
1950
1951                         default:
1952                                 /* No extra segments required for sends */
1953                                 break;
1954                         }
1955
1956                         break;
1957
1958                 case UC:
1959                         switch (wr->opcode) {
1960                         case IB_WR_RDMA_WRITE:
1961                         case IB_WR_RDMA_WRITE_WITH_IMM:
1962                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1963                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1964                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1965                                         cpu_to_be32(wr->wr.rdma.rkey);
1966                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1967                                 wqe += sizeof (struct mthca_raddr_seg);
1968                                 size += sizeof (struct mthca_raddr_seg) / 16;
1969                                 break;
1970
1971                         default:
1972                                 /* No extra segments required for sends */
1973                                 break;
1974                         }
1975
1976                         break;
1977
1978                 case UD:
1979                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1980                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1981                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1982                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1983                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1984                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1985
1986                         wqe += sizeof (struct mthca_arbel_ud_seg);
1987                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1988                         break;
1989
1990                 case MLX:
1991                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1992                                                wqe - sizeof (struct mthca_next_seg),
1993                                                wqe);
1994                         if (err) {
1995                                 *bad_wr = wr;
1996                                 goto out;
1997                         }
1998                         wqe += sizeof (struct mthca_data_seg);
1999                         size += sizeof (struct mthca_data_seg) / 16;
2000                         break;
2001                 }
2002
2003                 if (wr->num_sge > qp->sq.max_gs) {
2004                         mthca_err(dev, "too many gathers\n");
2005                         err = -EINVAL;
2006                         *bad_wr = wr;
2007                         goto out;
2008                 }
2009
2010                 for (i = 0; i < wr->num_sge; ++i) {
2011                         ((struct mthca_data_seg *) wqe)->byte_count =
2012                                 cpu_to_be32(wr->sg_list[i].length);
2013                         ((struct mthca_data_seg *) wqe)->lkey =
2014                                 cpu_to_be32(wr->sg_list[i].lkey);
2015                         ((struct mthca_data_seg *) wqe)->addr =
2016                                 cpu_to_be64(wr->sg_list[i].addr);
2017                         wqe += sizeof (struct mthca_data_seg);
2018                         size += sizeof (struct mthca_data_seg) / 16;
2019                 }
2020
2021                 /* Add one more inline data segment for ICRC */
2022                 if (qp->transport == MLX) {
2023                         ((struct mthca_data_seg *) wqe)->byte_count =
2024                                 cpu_to_be32((1 << 31) | 4);
2025                         ((u32 *) wqe)[1] = 0;
2026                         wqe += sizeof (struct mthca_data_seg);
2027                         size += sizeof (struct mthca_data_seg) / 16;
2028                 }
2029
2030                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2031
2032                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2033                         mthca_err(dev, "opcode invalid\n");
2034                         err = -EINVAL;
2035                         *bad_wr = wr;
2036                         goto out;
2037                 }
2038
2039                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2040                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2041                                      qp->send_wqe_offset) |
2042                                     mthca_opcode[wr->opcode]);
2043                 wmb();
2044                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2045                         cpu_to_be32(MTHCA_NEXT_DBD | size);
2046
2047                 if (!size0) {
2048                         size0 = size;
2049                         op0   = mthca_opcode[wr->opcode];
2050                 }
2051
2052                 ++ind;
2053                 if (unlikely(ind >= qp->sq.max))
2054                         ind -= qp->sq.max;
2055         }
2056
2057 out:
2058         if (likely(nreq)) {
2059                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2060                                           ((qp->sq.head & 0xffff) << 8) |
2061                                           f0 | op0);
2062                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2063
2064                 qp->sq.head += nreq;
2065
2066                 /*
2067                  * Make sure that descriptors are written before
2068                  * doorbell record.
2069                  */
2070                 wmb();
2071                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2072
2073                 /*
2074                  * Make sure doorbell record is written before we
2075                  * write MMIO send doorbell.
2076                  */
2077                 wmb();
2078                 mthca_write64(doorbell,
2079                               dev->kar + MTHCA_SEND_DOORBELL,
2080                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2081         }
2082
2083         spin_unlock_irqrestore(&qp->sq.lock, flags);
2084         return err;
2085 }
2086
2087 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2088                              struct ib_recv_wr **bad_wr)
2089 {
2090         struct mthca_dev *dev = to_mdev(ibqp->device);
2091         struct mthca_qp *qp = to_mqp(ibqp);
2092         unsigned long flags;
2093         int err = 0;
2094         int nreq;
2095         int ind;
2096         int i;
2097         void *wqe;
2098
2099         spin_lock_irqsave(&qp->rq.lock, flags);
2100
2101         /* XXX check that state is OK to post receive */
2102
2103         ind = qp->rq.head & (qp->rq.max - 1);
2104
2105         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2106                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2107                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2108                                         " %d max, %d nreq)\n", qp->qpn,
2109                                         qp->rq.head, qp->rq.tail,
2110                                         qp->rq.max, nreq);
2111                         err = -ENOMEM;
2112                         *bad_wr = wr;
2113                         goto out;
2114                 }
2115
2116                 wqe = get_recv_wqe(qp, ind);
2117
2118                 ((struct mthca_next_seg *) wqe)->flags = 0;
2119
2120                 wqe += sizeof (struct mthca_next_seg);
2121
2122                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2123                         err = -EINVAL;
2124                         *bad_wr = wr;
2125                         goto out;
2126                 }
2127
2128                 for (i = 0; i < wr->num_sge; ++i) {
2129                         ((struct mthca_data_seg *) wqe)->byte_count =
2130                                 cpu_to_be32(wr->sg_list[i].length);
2131                         ((struct mthca_data_seg *) wqe)->lkey =
2132                                 cpu_to_be32(wr->sg_list[i].lkey);
2133                         ((struct mthca_data_seg *) wqe)->addr =
2134                                 cpu_to_be64(wr->sg_list[i].addr);
2135                         wqe += sizeof (struct mthca_data_seg);
2136                 }
2137
2138                 if (i < qp->rq.max_gs) {
2139                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2140                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2141                         ((struct mthca_data_seg *) wqe)->addr = 0;
2142                 }
2143
2144                 qp->wrid[ind] = wr->wr_id;
2145
2146                 ++ind;
2147                 if (unlikely(ind >= qp->rq.max))
2148                         ind -= qp->rq.max;
2149         }
2150 out:
2151         if (likely(nreq)) {
2152                 qp->rq.head += nreq;
2153
2154                 /*
2155                  * Make sure that descriptors are written before
2156                  * doorbell record.
2157                  */
2158                 wmb();
2159                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2160         }
2161
2162         spin_unlock_irqrestore(&qp->rq.lock, flags);
2163         return err;
2164 }
2165
2166 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2167                        int index, int *dbd, __be32 *new_wqe)
2168 {
2169         struct mthca_next_seg *next;
2170
2171         /*
2172          * For SRQs, all WQEs generate a CQE, so we're always at the
2173          * end of the doorbell chain.
2174          */
2175         if (qp->ibqp.srq) {
2176                 *new_wqe = 0;
2177                 return 0;
2178         }
2179
2180         if (is_send)
2181                 next = get_send_wqe(qp, index);
2182         else
2183                 next = get_recv_wqe(qp, index);
2184
2185         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2186         if (next->ee_nds & cpu_to_be32(0x3f))
2187                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2188                         (next->ee_nds & cpu_to_be32(0x3f));
2189         else
2190                 *new_wqe = 0;
2191
2192         return 0;
2193 }
2194
2195 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2196 {
2197         int err;
2198         u8 status;
2199         int i;
2200
2201         spin_lock_init(&dev->qp_table.lock);
2202
2203         /*
2204          * We reserve 2 extra QPs per port for the special QPs.  The
2205          * special QP for port 1 has to be even, so round up.
2206          */
2207         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2208         err = mthca_alloc_init(&dev->qp_table.alloc,
2209                                dev->limits.num_qps,
2210                                (1 << 24) - 1,
2211                                dev->qp_table.sqp_start +
2212                                MTHCA_MAX_PORTS * 2);
2213         if (err)
2214                 return err;
2215
2216         err = mthca_array_init(&dev->qp_table.qp,
2217                                dev->limits.num_qps);
2218         if (err) {
2219                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2220                 return err;
2221         }
2222
2223         for (i = 0; i < 2; ++i) {
2224                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2225                                             dev->qp_table.sqp_start + i * 2,
2226                                             &status);
2227                 if (err)
2228                         goto err_out;
2229                 if (status) {
2230                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2231                                    "status %02x, aborting.\n",
2232                                    status);
2233                         err = -EINVAL;
2234                         goto err_out;
2235                 }
2236         }
2237         return 0;
2238
2239  err_out:
2240         for (i = 0; i < 2; ++i)
2241                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2242
2243         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2244         mthca_alloc_cleanup(&dev->qp_table.alloc);
2245
2246         return err;
2247 }
2248
2249 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2250 {
2251         int i;
2252         u8 status;
2253
2254         for (i = 0; i < 2; ++i)
2255                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2256
2257         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2258         mthca_alloc_cleanup(&dev->qp_table.alloc);
2259 }