1 #ifndef _IPATH_KERNEL_H
2 #define _IPATH_KERNEL_H
4 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/mutex.h>
46 #include <rdma/ib_verbs.h>
48 #include "ipath_common.h"
49 #include "ipath_debug.h"
50 #include "ipath_registers.h"
52 /* only s/w major version of InfiniPath we can handle */
53 #define IPATH_CHIP_VERS_MAJ 2U
55 /* don't care about this except printing */
56 #define IPATH_CHIP_VERS_MIN 0U
58 /* temporary, maybe always */
59 extern struct infinipath_stats ipath_stats;
61 #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
63 * First-cut critierion for "device is active" is
64 * two thousand dwords combined Tx, Rx traffic per
65 * 5-second interval. SMA packets are 64 dwords,
66 * and occur "a few per second", presumably each way.
68 #define IPATH_TRAFFIC_ACTIVE_THRESHOLD (2000)
70 * Struct used to indicate which errors are logged in each of the
71 * error-counters that are logged to EEPROM. A counter is incremented
72 * _once_ (saturating at 255) for each event with any bits set in
73 * the error or hwerror register masks below.
75 #define IPATH_EEP_LOG_CNT (4)
76 struct ipath_eep_log_mask {
81 struct ipath_portdata {
82 void **port_rcvegrbuf;
83 dma_addr_t *port_rcvegrbuf_phys;
84 /* rcvhdrq base, needs mmap before useful */
86 /* kernel virtual address where hdrqtail is updated */
87 void *port_rcvhdrtail_kvaddr;
89 * temp buffer for expected send setup, allocated at open, instead
92 void *port_tid_pg_list;
93 /* when waiting for rcv or pioavail */
94 wait_queue_head_t port_wait;
96 * rcvegr bufs base, physical, must fit
97 * in 44 bits so 32 bit programs mmap64 44 bit works)
99 dma_addr_t port_rcvegr_phys;
100 /* mmap of hdrq, must fit in 44 bits */
101 dma_addr_t port_rcvhdrq_phys;
102 dma_addr_t port_rcvhdrqtailaddr_phys;
104 * number of opens (including slave subports) on this instance
105 * (ignoring forks, dup, etc. for now)
109 * how much space to leave at start of eager TID entries for
110 * protocol use, on each TID
112 /* instead of calculating it */
114 /* non-zero if port is being shared. */
115 u16 port_subport_cnt;
116 /* non-zero if port is being shared. */
118 /* chip offset of PIO buffers for this port */
120 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
121 u32 port_rcvegrbuf_chunks;
122 /* how many egrbufs per chunk */
123 u32 port_rcvegrbufs_perchunk;
124 /* order for port_rcvegrbuf_pages */
125 size_t port_rcvegrbuf_size;
126 /* rcvhdrq size (for freeing) */
127 size_t port_rcvhdrq_size;
128 /* next expected TID to check when looking for free */
130 /* next expected TID to check */
131 unsigned long port_flag;
133 unsigned long int_flag;
134 /* WAIT_RCV that timed out, no interrupt */
136 /* WAIT_PIO that timed out, no interrupt */
138 /* WAIT_RCV already happened, no wait */
140 /* WAIT_PIO already happened, no wait */
142 /* total number of rcvhdrqfull errors */
145 * Used to suppress multiple instances of same
146 * port staying stuck at same point.
148 u32 port_lastrcvhdrqtail;
149 /* saved total number of rcvhdrqfull errors for poll edge trigger */
150 u32 port_hdrqfull_poll;
151 /* total number of polled urgent packets */
153 /* saved total number of polled urgent packets for poll edge trigger */
154 u32 port_urgent_poll;
155 /* pid of process using this port */
157 pid_t port_subpid[INFINIPATH_MAX_SUBPORT];
158 /* same size as task_struct .comm[] */
160 /* pkeys set by this use of this port */
162 /* so file ops can get at unit */
163 struct ipath_devdata *port_dd;
164 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
165 void *subport_uregbase;
166 /* An array of pages for the eager receive buffers * N */
167 void *subport_rcvegrbuf;
168 /* An array of pages for the eager header queue entries * N */
169 void *subport_rcvhdr_base;
170 /* The version of the library which opened this port */
172 /* Bitmask of active slaves */
174 /* Type of packets or conditions we want to poll for */
176 /* port rcvhdrq head offset */
183 * control information for layered drivers
185 struct _ipath_layer {
189 struct ipath_skbinfo {
194 /* max dwords in small buffer packet */
195 #define IPATH_SMALLBUF_DWORDS (dd->ipath_piosize2k >> 2)
198 * Possible IB config parameters for ipath_f_get/set_ib_cfg()
200 #define IPATH_IB_CFG_LIDLMC 0 /* Get/set LID (LS16b) and Mask (MS16b) */
201 #define IPATH_IB_CFG_HRTBT 1 /* Get/set Heartbeat off/enable/auto */
202 #define IPATH_IB_HRTBT_ON 3 /* Heartbeat enabled, sent every 100msec */
203 #define IPATH_IB_HRTBT_OFF 0 /* Heartbeat off */
204 #define IPATH_IB_CFG_LWID_ENB 2 /* Get/set allowed Link-width */
205 #define IPATH_IB_CFG_LWID 3 /* Get currently active Link-width */
206 #define IPATH_IB_CFG_SPD_ENB 4 /* Get/set allowed Link speeds */
207 #define IPATH_IB_CFG_SPD 5 /* Get current Link spd */
208 #define IPATH_IB_CFG_RXPOL_ENB 6 /* Get/set Auto-RX-polarity enable */
209 #define IPATH_IB_CFG_LREV_ENB 7 /* Get/set Auto-Lane-reversal enable */
210 #define IPATH_IB_CFG_LINKLATENCY 8 /* Get Auto-Lane-reversal enable */
213 struct ipath_devdata {
214 struct list_head ipath_list;
216 struct ipath_kregs const *ipath_kregs;
217 struct ipath_cregs const *ipath_cregs;
219 /* mem-mapped pointer to base of chip regs */
220 u64 __iomem *ipath_kregbase;
221 /* end of mem-mapped chip space; range checking */
222 u64 __iomem *ipath_kregend;
223 /* physical address of chip for io_remap, etc. */
224 unsigned long ipath_physaddr;
225 /* base of memory alloced for ipath_kregbase, for free */
226 u64 *ipath_kregalloc;
228 * virtual address where port0 rcvhdrqtail updated for this unit.
229 * only written to by the chip, not the driver.
231 volatile __le64 *ipath_hdrqtailptr;
232 /* ipath_cfgports pointers */
233 struct ipath_portdata **ipath_pd;
234 /* sk_buffs used by port 0 eager receive queue */
235 struct ipath_skbinfo *ipath_port0_skbinfo;
236 /* kvirt address of 1st 2k pio buffer */
237 void __iomem *ipath_pio2kbase;
238 /* kvirt address of 1st 4k pio buffer */
239 void __iomem *ipath_pio4kbase;
241 * points to area where PIOavail registers will be DMA'ed.
242 * Has to be on a page of it's own, because the page will be
243 * mapped into user program space. This copy is *ONLY* ever
244 * written by DMA, not by the driver! Need a copy per device
245 * when we get to multiple devices
247 volatile __le64 *ipath_pioavailregs_dma;
248 /* physical address where updates occur */
249 dma_addr_t ipath_pioavailregs_phys;
250 struct _ipath_layer ipath_layer;
252 int (*ipath_f_intrsetup)(struct ipath_devdata *);
253 /* fallback to alternate interrupt type if possible */
254 int (*ipath_f_intr_fallback)(struct ipath_devdata *);
255 /* setup on-chip bus config */
256 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
257 /* hard reset chip */
258 int (*ipath_f_reset)(struct ipath_devdata *);
259 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
261 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
262 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
264 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
265 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
266 int (*ipath_f_early_init)(struct ipath_devdata *);
267 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
268 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
270 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
271 void (*ipath_f_cleanup)(struct ipath_devdata *);
272 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
273 /* fill out chip-specific fields */
274 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
276 void (*ipath_f_free_irq)(struct ipath_devdata *);
277 struct ipath_message_header *(*ipath_f_get_msgheader)
278 (struct ipath_devdata *, __le32 *);
279 void (*ipath_f_config_ports)(struct ipath_devdata *, ushort);
280 int (*ipath_f_get_ib_cfg)(struct ipath_devdata *, int);
281 int (*ipath_f_set_ib_cfg)(struct ipath_devdata *, int, u32);
282 void (*ipath_f_config_jint)(struct ipath_devdata *, u16 , u16);
283 void (*ipath_f_read_counters)(struct ipath_devdata *,
284 struct infinipath_counters *);
285 void (*ipath_f_xgxs_reset)(struct ipath_devdata *);
286 /* per chip actions needed for IB Link up/down changes */
287 int (*ipath_f_ib_updown)(struct ipath_devdata *, int, u64);
289 struct ipath_ibdev *verbs_dev;
290 struct timer_list verbs_timer;
291 /* total dwords sent (summed from counter) */
293 /* total dwords rcvd (summed from counter) */
295 /* total packets sent (summed from counter) */
297 /* total packets rcvd (summed from counter) */
299 /* ipath_statusp initially points to this. */
301 /* GUID for this interface, in network order */
304 * aggregrate of error bits reported since last cleared, for
305 * limiting of error reporting
307 ipath_err_t ipath_lasterror;
309 * aggregrate of error bits reported since last cleared, for
310 * limiting of hwerror reporting
312 ipath_err_t ipath_lasthwerror;
313 /* errors masked because they occur too fast */
314 ipath_err_t ipath_maskederrs;
315 u64 ipath_lastlinkrecov; /* link recoveries at last ACTIVE */
316 /* time in jiffies at which to re-enable maskederrs */
317 unsigned long ipath_unmasktime;
318 /* count of egrfull errors, combined for all ports */
319 u64 ipath_last_tidfull;
320 /* for ipath_qcheck() */
321 u64 ipath_lastport0rcv_cnt;
322 /* template for writing TIDs */
323 u64 ipath_tidtemplate;
324 /* value to write to free TIDs */
325 u64 ipath_tidinvalid;
326 /* IBA6120 rcv interrupt setup */
327 u64 ipath_rhdrhead_intr_off;
329 /* size of memory at ipath_kregbase */
331 /* number of registers used for pioavail */
333 /* IPATH_POLL, etc. */
335 /* ipath_flags driver is waiting for */
336 u32 ipath_state_wanted;
337 /* last buffer for user use, first buf for kernel use is this
339 u32 ipath_lastport_piobuf;
340 /* is a stats timer active */
341 u32 ipath_stats_timer_active;
342 /* number of interrupts for this device -- saturates... */
343 u32 ipath_int_counter;
344 /* dwords sent read from counter */
346 /* dwords received read from counter */
348 /* sent packets read from counter */
350 /* received packets read from counter */
352 /* pio bufs allocated per port */
355 * number of ports configured as max; zero is set to number chip
356 * supports, less gives more pio bufs/port, etc.
359 /* count of port 0 hdrqfull errors */
360 u32 ipath_p0_hdrqfull;
361 /* port 0 number of receive eager buffers */
362 u32 ipath_p0_rcvegrcnt;
365 * index of last piobuffer we used. Speeds up searching, by
366 * starting at this point. Doesn't matter if multiple cpu's use and
367 * update, last updater is only write that matters. Whenever it
368 * wraps, we update shadow copies. Need a copy per device when we
369 * get to multiple devices
371 u32 ipath_lastpioindex;
372 u32 ipath_lastpioindexl;
373 /* max length of freezemsg */
376 * consecutive times we wanted a PIO buffer but were unable to
379 u32 ipath_consec_nopiobuf;
381 * hint that we should update ipath_pioavailshadow before
382 * looking for a PIO buffer
384 u32 ipath_upd_pio_shadow;
385 /* so we can rewrite it after a chip reset */
387 /* so we can rewrite it after a chip reset */
390 /* interrupt number */
392 /* HT/PCI Vendor ID (here for NodeInfo) */
394 /* HT/PCI Device ID (here for NodeInfo) */
396 /* offset in HT config space of slave/primary interface block */
397 u8 ipath_ht_slave_off;
398 /* for write combining settings */
399 unsigned long ipath_wc_cookie;
400 unsigned long ipath_wc_base;
401 unsigned long ipath_wc_len;
402 /* ref count for each pkey */
403 atomic_t ipath_pkeyrefs[4];
404 /* shadow copy of struct page *'s for exp tid pages */
405 struct page **ipath_pageshadow;
406 /* shadow copy of dma handles for exp tid pages */
407 dma_addr_t *ipath_physshadow;
408 u64 __iomem *ipath_egrtidbase;
409 /* lock to workaround chip bug 9437 and others */
410 spinlock_t ipath_kernel_tid_lock;
411 spinlock_t ipath_tid_lock;
412 spinlock_t ipath_sendctrl_lock;
416 * this address is mapped readonly into user processes so they can
417 * get status cheaply, whenever they want.
420 /* freeze msg if hw error put chip in freeze */
421 char *ipath_freezemsg;
422 /* pci access data structure */
423 struct pci_dev *pcidev;
424 struct cdev *user_cdev;
425 struct cdev *diag_cdev;
426 struct class_device *user_class_dev;
427 struct class_device *diag_class_dev;
428 /* timer used to prevent stats overflow, error throttling, etc. */
429 struct timer_list ipath_stats_timer;
430 void *ipath_dummy_hdrq; /* used after port close */
431 dma_addr_t ipath_dummy_hdrq_phys;
433 unsigned long ipath_ureg_align; /* user register alignment */
435 /* HoL blocking / user app forward-progress state */
436 unsigned ipath_hol_state;
437 unsigned ipath_hol_next;
438 struct timer_list ipath_hol_timer;
441 * Shadow copies of registers; size indicates read access size.
442 * Most of them are readonly, but some are write-only register,
443 * where we manipulate the bits in the shadow copy, and then write
444 * the shadow copy to infinipath.
446 * We deliberately make most of these 32 bits, since they have
447 * restricted range. For any that we read, we won't to generate 32
448 * bit accesses, since Opteron will generate 2 separate 32 bit HT
449 * transactions for a 64 bit read, and we want to avoid unnecessary
453 /* This is the 64 bit group */
456 * shadow of pioavail, check to be sure it's large enough at
459 unsigned long ipath_pioavailshadow[8];
460 /* bitmap of send buffers available for the kernel to use with PIO. */
461 unsigned long ipath_pioavailkernel[8];
462 /* shadow of kr_gpio_out, for rmw ops */
464 /* shadow the gpio mask register */
466 /* shadow the gpio output enable, etc... */
468 /* kr_revision shadow */
471 * shadow of ibcctrl, for interrupt handling of link changes,
476 * last ibcstatus, to suppress "duplicate" status change messages,
479 u64 ipath_lastibcstat;
480 /* hwerrmask shadow */
481 ipath_err_t ipath_hwerrmask;
482 ipath_err_t ipath_errormask; /* errormask shadow */
483 /* interrupt config reg shadow */
485 /* kr_sendpiobufbase value */
486 u64 ipath_piobufbase;
488 /* these are the "32 bit" regs */
491 * number of GUIDs in the flash for this interface; may need some
492 * rethinking for setting on other ifaces
496 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
497 * all expect bit fields to be "unsigned long"
499 /* shadow kr_rcvctrl */
500 unsigned long ipath_rcvctrl;
501 /* shadow kr_sendctrl */
502 unsigned long ipath_sendctrl;
503 unsigned long ipath_lastcancel; /* to not count armlaunch after cancel */
505 /* value we put in kr_rcvhdrcnt */
507 /* value we put in kr_rcvhdrsize */
508 u32 ipath_rcvhdrsize;
509 /* value we put in kr_rcvhdrentsize */
510 u32 ipath_rcvhdrentsize;
511 /* offset of last entry in rcvhdrq */
513 /* kr_portcnt value */
515 /* kr_pagealign value */
517 /* number of "2KB" PIO buffers */
519 /* size in bytes of "2KB" PIO buffers */
521 /* number of "4KB" PIO buffers */
523 /* size in bytes of "4KB" PIO buffers */
525 /* kr_rcvegrbase value */
526 u32 ipath_rcvegrbase;
527 /* kr_rcvegrcnt value */
529 /* kr_rcvtidbase value */
530 u32 ipath_rcvtidbase;
531 /* kr_rcvtidcnt value */
537 /* kr_counterregbase */
539 /* shadow the control register contents */
541 /* PCI revision register (HTC rev on FPGA) */
544 /* chip address space used by 4k pio buffers */
546 /* The MTU programmed for this unit */
549 * The max size IB packet, included IB headers that we can send.
550 * Starts same as ipath_piosize, but is affected when ibmtu is
551 * changed, or by size of eager buffers
555 * ibmaxlen at init time, limited by chip and by receive buffer
556 * size. Not changed after init.
558 u32 ipath_init_ibmaxlen;
559 /* size of each rcvegrbuffer */
560 u32 ipath_rcvegrbufsize;
561 /* localbus width (1, 2,4,8,16,32) from config space */
562 u32 ipath_lbus_width;
563 /* localbus speed (HT: 200,400,800,1000; PCIe 2500) */
564 u32 ipath_lbus_speed;
566 * number of sequential ibcstatus change for polling active/quiet
567 * (i.e., link not coming up).
570 /* low and high portions of MSI capability/vector */
572 /* saved after PCIe init for restore after reset */
574 /* MSI data (vector) saved for restore */
576 /* MLID programmed for this instance */
578 /* LID programmed for this instance */
580 /* list of pkeys programmed; 0 if not set */
583 * ASCII serial number, from flash, large enough for original
584 * all digit strings, and longer QLogic serial number format
587 /* human readable board version */
588 u8 ipath_boardversion[80];
589 u8 ipath_lbus_info[32]; /* human readable localbus info */
590 /* chip major rev, from ipath_revision */
592 /* chip minor rev, from ipath_revision */
594 /* board rev, from ipath_revision */
597 u8 ipath_r_portenable_shift;
598 u8 ipath_r_intravail_shift;
599 u8 ipath_r_tailupd_shift;
600 u8 ipath_r_portcfg_shift;
602 /* unit # of this chip, if present */
604 /* saved for restore after reset */
605 u8 ipath_pci_cacheline;
606 /* LID mask control */
608 /* link width supported */
609 u8 ipath_link_width_supported;
610 /* link speed supported */
611 u8 ipath_link_speed_supported;
612 u8 ipath_link_width_enabled;
613 u8 ipath_link_speed_enabled;
614 u8 ipath_link_width_active;
615 u8 ipath_link_speed_active;
616 /* Rx Polarity inversion (compensate for ~tx on partner) */
619 /* local link integrity counter */
620 u32 ipath_lli_counter;
621 /* local link integrity errors */
622 u32 ipath_lli_errors;
624 * Above counts only cases where _successive_ LocalLinkIntegrity
625 * errors were seen in the receive headers of kern-packets.
626 * Below are the three (monotonically increasing) counters
627 * maintained via GPIO interrupts on iba6120-rev2.
629 u32 ipath_rxfc_unsupvl_errs;
630 u32 ipath_overrun_thresh_errs;
633 /* status check work */
634 struct delayed_work status_work;
637 * Not all devices managed by a driver instance are the same
638 * type, so these fields must be per-device.
640 u64 ipath_i_bitsextant;
641 ipath_err_t ipath_e_bitsextant;
642 ipath_err_t ipath_hwe_bitsextant;
645 * Below should be computable from number of ports,
646 * since they are never modified.
648 u32 ipath_i_rcvavail_mask;
649 u32 ipath_i_rcvurg_mask;
650 u16 ipath_i_rcvurg_shift;
651 u16 ipath_i_rcvavail_shift;
654 * Register bits for selecting i2c direction and values, used for
657 u16 ipath_gpio_sda_num;
658 u16 ipath_gpio_scl_num;
662 /* lock for doing RMW of shadows/regs for ExtCtrl and GPIO */
663 spinlock_t ipath_gpio_lock;
666 * IB link and linktraining states and masks that vary per chip in
667 * some way. Set at init, to avoid each IB status change interrupt
676 u16 ipath_rhf_offset; /* offset of RHF within receive header entry */
679 * shift/mask for linkcmd, linkinitcmd, maxpktlen in ibccontol
680 * reg. Changes for IBA7220
682 u8 ibcc_lic_mask; /* LinkInitCmd */
683 u8 ibcc_lc_shift; /* LinkCmd */
684 u8 ibcc_mpl_shift; /* Maxpktlen */
688 /* used to override LED behavior */
689 u8 ipath_led_override; /* Substituted for normal value, if non-zero */
690 u16 ipath_led_override_timeoff; /* delta to next timer event */
691 u8 ipath_led_override_vals[2]; /* Alternates per blink-frame */
692 u8 ipath_led_override_phase; /* Just counts, LSB picks from vals[] */
693 atomic_t ipath_led_override_timer_active;
694 /* Used to flash LEDs in override mode */
695 struct timer_list ipath_led_override_timer;
697 /* Support (including locks) for EEPROM logging of errors and time */
698 /* control access to actual counters, timer */
699 spinlock_t ipath_eep_st_lock;
700 /* control high-level access to EEPROM */
701 struct mutex ipath_eep_lock;
702 /* Below inc'd by ipath_snap_cntrs(), locked by ipath_eep_st_lock */
703 uint64_t ipath_traffic_wds;
704 /* active time is kept in seconds, but logged in hours */
705 atomic_t ipath_active_time;
706 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
707 uint8_t ipath_eep_st_errs[IPATH_EEP_LOG_CNT];
708 uint8_t ipath_eep_st_new_errs[IPATH_EEP_LOG_CNT];
709 uint16_t ipath_eep_hrs;
711 * masks for which bits of errs, hwerrs that cause
712 * each of the counters to increment.
714 struct ipath_eep_log_mask ipath_eep_st_masks[IPATH_EEP_LOG_CNT];
716 /* interrupt mitigation reload register info */
717 u16 ipath_jint_idle_ticks; /* idle clock ticks */
718 u16 ipath_jint_max_packets; /* max packets across all ports */
721 /* ipath_hol_state values (stopping/starting user proc, send flushing) */
722 #define IPATH_HOL_UP 0
723 #define IPATH_HOL_DOWN 1
724 /* ipath_hol_next toggle values, used when hol_state IPATH_HOL_DOWN */
725 #define IPATH_HOL_DOWNSTOP 0
726 #define IPATH_HOL_DOWNCONT 1
728 /* Private data for file operations */
729 struct ipath_filedata {
730 struct ipath_portdata *pd;
734 extern struct list_head ipath_dev_list;
735 extern spinlock_t ipath_devs_lock;
736 extern struct ipath_devdata *ipath_lookup(int unit);
738 int ipath_init_chip(struct ipath_devdata *, int);
739 int ipath_enable_wc(struct ipath_devdata *dd);
740 void ipath_disable_wc(struct ipath_devdata *dd);
741 int ipath_count_units(int *npresentp, int *nupp, int *maxportsp);
742 void ipath_shutdown_device(struct ipath_devdata *);
743 void ipath_clear_freeze(struct ipath_devdata *);
745 struct file_operations;
746 int ipath_cdev_init(int minor, char *name, const struct file_operations *fops,
747 struct cdev **cdevp, struct class_device **class_devp);
748 void ipath_cdev_cleanup(struct cdev **cdevp,
749 struct class_device **class_devp);
751 int ipath_diag_add(struct ipath_devdata *);
752 void ipath_diag_remove(struct ipath_devdata *);
754 extern wait_queue_head_t ipath_state_wait;
756 int ipath_user_add(struct ipath_devdata *dd);
757 void ipath_user_remove(struct ipath_devdata *dd);
759 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
761 extern int ipath_diag_inuse;
763 irqreturn_t ipath_intr(int irq, void *devid);
764 int ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
765 #if __IPATH_INFO || __IPATH_DBG
766 extern const char *ipath_ibcstatus_str[];
769 /* clean up any per-chip chip-specific stuff */
770 void ipath_chip_cleanup(struct ipath_devdata *);
771 /* clean up any chip type-specific stuff */
772 void ipath_chip_done(void);
774 /* check to see if we have to force ordering for write combining */
775 int ipath_unordered_wc(void);
777 void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
779 void ipath_cancel_sends(struct ipath_devdata *, int);
781 int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
782 void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *);
784 int ipath_parse_ushort(const char *str, unsigned short *valp);
786 void ipath_kreceive(struct ipath_portdata *);
787 int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
788 int ipath_reset_device(int);
789 void ipath_get_faststats(unsigned long);
790 int ipath_wait_linkstate(struct ipath_devdata *, u32, int);
791 int ipath_set_linkstate(struct ipath_devdata *, u8);
792 int ipath_set_mtu(struct ipath_devdata *, u16);
793 int ipath_set_lid(struct ipath_devdata *, u32, u8);
794 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv);
795 void ipath_enable_armlaunch(struct ipath_devdata *);
796 void ipath_disable_armlaunch(struct ipath_devdata *);
797 void ipath_hol_down(struct ipath_devdata *);
798 void ipath_hol_up(struct ipath_devdata *);
799 void ipath_hol_event(unsigned long);
801 /* for use in system calls, where we want to know device type, etc. */
802 #define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd
803 #define subport_fp(fp) \
804 ((struct ipath_filedata *)(fp)->private_data)->subport
805 #define tidcursor_fp(fp) \
806 ((struct ipath_filedata *)(fp)->private_data)->tidcursor
809 * values for ipath_flags
811 /* chip can report link latency (IB 1.2) */
812 #define IPATH_HAS_LINK_LATENCY 0x1
813 /* The chip is up and initted */
814 #define IPATH_INITTED 0x2
815 /* set if any user code has set kr_rcvhdrsize */
816 #define IPATH_RCVHDRSZ_SET 0x4
817 /* The chip is present and valid for accesses */
818 #define IPATH_PRESENT 0x8
819 /* HT link0 is only 8 bits wide, ignore upper byte crc
821 #define IPATH_8BIT_IN_HT0 0x10
822 /* HT link1 is only 8 bits wide, ignore upper byte crc
824 #define IPATH_8BIT_IN_HT1 0x20
825 /* The link is down */
826 #define IPATH_LINKDOWN 0x40
827 /* The link level is up (0x11) */
828 #define IPATH_LINKINIT 0x80
829 /* The link is in the armed (0x21) state */
830 #define IPATH_LINKARMED 0x100
831 /* The link is in the active (0x31) state */
832 #define IPATH_LINKACTIVE 0x200
833 /* link current state is unknown */
834 #define IPATH_LINKUNK 0x400
835 /* Write combining flush needed for PIO */
836 #define IPATH_PIO_FLUSH_WC 0x1000
837 /* no IB cable, or no device on IB cable */
838 #define IPATH_NOCABLE 0x4000
839 /* Supports port zero per packet receive interrupts via
841 #define IPATH_GPIO_INTR 0x8000
842 /* uses the coded 4byte TID, not 8 byte */
843 #define IPATH_4BYTE_TID 0x10000
844 /* packet/word counters are 32 bit, else those 4 counters
846 #define IPATH_32BITCOUNTERS 0x20000
847 /* can miss port0 rx interrupts */
848 /* Interrupt register is 64 bits */
849 #define IPATH_INTREG_64 0x40000
850 #define IPATH_DISABLED 0x80000 /* administratively disabled */
851 /* Use GPIO interrupts for new counters */
852 #define IPATH_GPIO_ERRINTRS 0x100000
853 #define IPATH_SWAP_PIOBUFS 0x200000
854 /* Suppress heartbeat, even if turning off loopback */
855 #define IPATH_NO_HRTBT 0x1000000
856 #define IPATH_HAS_MULT_IB_SPEED 0x8000000
857 /* Linkdown-disable intentionally, Do not attempt to bring up */
858 #define IPATH_IB_LINK_DISABLED 0x40000000
859 #define IPATH_IB_FORCE_NOTIFY 0x80000000 /* force notify on next ib change */
861 /* Bits in GPIO for the added interrupts */
862 #define IPATH_GPIO_PORT0_BIT 2
863 #define IPATH_GPIO_RXUVL_BIT 3
864 #define IPATH_GPIO_OVRUN_BIT 4
865 #define IPATH_GPIO_LLI_BIT 5
866 #define IPATH_GPIO_ERRINTR_MASK 0x38
868 /* portdata flag bit offsets */
869 /* waiting for a packet to arrive */
870 #define IPATH_PORT_WAITING_RCV 2
871 /* master has not finished initializing */
872 #define IPATH_PORT_MASTER_UNINIT 4
873 /* waiting for an urgent packet to arrive */
874 #define IPATH_PORT_WAITING_URG 5
876 /* free up any allocated data at closes */
877 void ipath_free_data(struct ipath_portdata *dd);
878 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32, u32 *);
879 void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
880 unsigned len, int avail);
881 void ipath_init_iba6120_funcs(struct ipath_devdata *);
882 void ipath_init_iba6110_funcs(struct ipath_devdata *);
883 void ipath_get_eeprom_info(struct ipath_devdata *);
884 int ipath_update_eeprom_log(struct ipath_devdata *dd);
885 void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr);
886 u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
887 void ipath_force_pio_avail_update(struct ipath_devdata *);
888 void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev);
891 * Set LED override, only the two LSBs have "public" meaning, but
892 * any non-zero value substitutes them for the Link and LinkTrain
895 #define IPATH_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
896 #define IPATH_LED_LOG 2 /* Logical (link) YELLOW LED */
897 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val);
900 * number of words used for protocol header if not set by ipath_userinit();
902 #define IPATH_DFLT_RCVHDRSIZE 9
904 int ipath_get_user_pages(unsigned long, size_t, struct page **);
905 void ipath_release_user_pages(struct page **, size_t);
906 void ipath_release_user_pages_on_close(struct page **, size_t);
907 int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
908 int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
910 /* these are used for the registers that vary with port */
911 void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
915 * We could have a single register get/put routine, that takes a group type,
916 * but this is somewhat clearer and cleaner. It also gives us some error
917 * checking. 64 bit register reads should always work, but are inefficient
918 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
919 * so we use kreg32 wherever possible. User register and counter register
920 * reads are always 32 bit reads, so only one form of those routines.
924 * At the moment, none of the s-registers are writable, so no
925 * ipath_write_sreg(), and none of the c-registers are writable, so no
926 * ipath_write_creg().
930 * ipath_read_ureg32 - read 32-bit virtualized per-port register
932 * @regno: register number
935 * Return the contents of a register that is virtualized to be per port.
936 * Returns -1 on errors (not distinguishable from valid contents at
937 * runtime; we may add a separate error variable at some point).
939 static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
940 ipath_ureg regno, int port)
942 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
945 return readl(regno + (u64 __iomem *)
946 (dd->ipath_uregbase +
947 (char __iomem *)dd->ipath_kregbase +
948 dd->ipath_ureg_align * port));
952 * ipath_write_ureg - write 32-bit virtualized per-port register
954 * @regno: register number
958 * Write the contents of a register that is virtualized to be per port.
960 static inline void ipath_write_ureg(const struct ipath_devdata *dd,
961 ipath_ureg regno, u64 value, int port)
963 u64 __iomem *ubase = (u64 __iomem *)
964 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
965 dd->ipath_ureg_align * port);
966 if (dd->ipath_kregbase)
967 writeq(value, &ubase[regno]);
970 static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
973 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
975 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
978 static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
981 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
984 return readq(&dd->ipath_kregbase[regno]);
987 static inline void ipath_write_kreg(const struct ipath_devdata *dd,
988 ipath_kreg regno, u64 value)
990 if (dd->ipath_kregbase)
991 writeq(value, &dd->ipath_kregbase[regno]);
994 static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
997 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
1000 return readq(regno + (u64 __iomem *)
1001 (dd->ipath_cregbase +
1002 (char __iomem *)dd->ipath_kregbase));
1005 static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
1008 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
1010 return readl(regno + (u64 __iomem *)
1011 (dd->ipath_cregbase +
1012 (char __iomem *)dd->ipath_kregbase));
1015 static inline void ipath_write_creg(const struct ipath_devdata *dd,
1016 ipath_creg regno, u64 value)
1018 if (dd->ipath_kregbase)
1019 writeq(value, regno + (u64 __iomem *)
1020 (dd->ipath_cregbase +
1021 (char __iomem *)dd->ipath_kregbase));
1024 static inline void ipath_clear_rcvhdrtail(const struct ipath_portdata *pd)
1026 *((u64 *) pd->port_rcvhdrtail_kvaddr) = 0ULL;
1029 static inline u32 ipath_get_rcvhdrtail(const struct ipath_portdata *pd)
1031 return (u32) le64_to_cpu(*((volatile __le64 *)
1032 pd->port_rcvhdrtail_kvaddr));
1035 static inline u64 ipath_read_ireg(const struct ipath_devdata *dd, ipath_kreg r)
1037 return (dd->ipath_flags & IPATH_INTREG_64) ?
1038 ipath_read_kreg64(dd, r) : ipath_read_kreg32(dd, r);
1042 * from contents of IBCStatus (or a saved copy), return linkstate
1043 * Report ACTIVE_DEFER as ACTIVE, because we treat them the same
1044 * everywhere, anyway (and should be, for almost all purposes).
1046 static inline u32 ipath_ib_linkstate(struct ipath_devdata *dd, u64 ibcs)
1048 u32 state = (u32)(ibcs >> dd->ibcs_ls_shift) &
1049 INFINIPATH_IBCS_LINKSTATE_MASK;
1050 if (state == INFINIPATH_IBCS_L_STATE_ACT_DEFER)
1051 state = INFINIPATH_IBCS_L_STATE_ACTIVE;
1055 /* from contents of IBCStatus (or a saved copy), return linktrainingstate */
1056 static inline u32 ipath_ib_linktrstate(struct ipath_devdata *dd, u64 ibcs)
1058 return (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1063 * from contents of IBCStatus (or a saved copy), return logical link state
1064 * combination of link state and linktraining state (down, active, init,
1067 static inline u32 ipath_ib_state(struct ipath_devdata *dd, u64 ibcs)
1070 ibs = (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1073 (INFINIPATH_IBCS_LINKSTATE_MASK << dd->ibcs_ls_shift));
1081 struct device_driver;
1083 extern const char ib_ipath_version[];
1085 extern struct attribute_group *ipath_driver_attr_groups[];
1087 int ipath_device_create_group(struct device *, struct ipath_devdata *);
1088 void ipath_device_remove_group(struct device *, struct ipath_devdata *);
1089 int ipath_expose_reset(struct device *);
1091 int ipath_init_ipathfs(void);
1092 void ipath_exit_ipathfs(void);
1093 int ipathfs_add_device(struct ipath_devdata *);
1094 int ipathfs_remove_device(struct ipath_devdata *);
1097 * dma_addr wrappers - all 0's invalid for hw
1099 dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long,
1101 dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int);
1104 * Flush write combining store buffers (if present) and perform a write
1107 #if defined(CONFIG_X86_64)
1108 #define ipath_flush_wc() asm volatile("sfence" ::: "memory")
1110 #define ipath_flush_wc() wmb()
1113 extern unsigned ipath_debug; /* debugging bit mask */
1114 extern unsigned ipath_linkrecovery;
1115 extern unsigned ipath_mtu4096;
1117 #define IPATH_MAX_PARITY_ATTEMPTS 10000 /* max times to try recovery */
1119 const char *ipath_get_unit_name(int unit);
1121 extern struct mutex ipath_mutex;
1123 #define IPATH_DRV_NAME "ib_ipath"
1124 #define IPATH_MAJOR 233
1125 #define IPATH_USER_MINOR_BASE 0
1126 #define IPATH_DIAGPKT_MINOR 127
1127 #define IPATH_DIAG_MINOR_BASE 129
1128 #define IPATH_NMINORS 255
1130 #define ipath_dev_err(dd,fmt,...) \
1132 const struct ipath_devdata *__dd = (dd); \
1134 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
1135 ipath_get_unit_name(__dd->ipath_unit), \
1138 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
1139 ipath_get_unit_name(__dd->ipath_unit), \
1143 #if _IPATH_DEBUGGING
1145 # define __IPATH_DBG_WHICH(which,fmt,...) \
1147 if(unlikely(ipath_debug&(which))) \
1148 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
1149 __func__,##__VA_ARGS__); \
1152 # define ipath_dbg(fmt,...) \
1153 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
1154 # define ipath_cdbg(which,fmt,...) \
1155 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
1157 #else /* ! _IPATH_DEBUGGING */
1159 # define ipath_dbg(fmt,...)
1160 # define ipath_cdbg(which,fmt,...)
1162 #endif /* _IPATH_DEBUGGING */
1165 * this is used for formatting hw error messages...
1167 struct ipath_hwerror_msgs {
1172 #define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b }
1174 /* in ipath_intr.c... */
1175 void ipath_format_hwerrors(u64 hwerrs,
1176 const struct ipath_hwerror_msgs *hwerrmsgs,
1178 char *msg, size_t lmsg);
1180 #endif /* _IPATH_KERNEL_H */