2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
39 #include "ipath_common.h"
42 * min buffers we want to have per port, after driver
44 #define IPATH_MIN_USER_PORT_BUFCNT 8
47 * Number of ports we are configured to use (to allow for more pio
48 * buffers per port, etc.) Zero means use chip value.
50 static ushort ipath_cfgports;
52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
56 * Number of buffers reserved for driver (verbs and layered drivers.)
57 * Reserved at end of buffer list. Initialized based on
58 * number of PIO buffers if not set via module interface.
59 * The problem with this is that it's global, but we'll use different
60 * numbers for different chip types. So the default value is not
61 * very useful. I've redefined it for the 1.3 release so that it's
62 * zero unless set by the user to something else, in which case we
65 static ushort ipath_kpiobufs;
67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
70 &ipath_kpiobufs, S_IWUSR | S_IRUGO);
71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
74 * create_port0_egr - allocate the eager TID buffers
75 * @dd: the infinipath device
77 * This code is now quite different for user and kernel, because
78 * the kernel uses skb's, for the accelerated network performance.
79 * This is the kernel (port0) version.
81 * Allocate the eager TID buffers and program them into infinipath.
82 * We use the network layer alloc_skb() allocator to allocate the
83 * memory, and either use the buffers as is for things like verbs
84 * packets, or pass the buffers up to the ipath layered driver and
85 * thence the network layer, replacing them as we do so (see
88 static int create_port0_egr(struct ipath_devdata *dd)
91 struct ipath_skbinfo *skbinfo;
94 egrcnt = dd->ipath_p0_rcvegrcnt;
96 skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
97 if (skbinfo == NULL) {
98 ipath_dev_err(dd, "allocation error for eager TID "
103 for (e = 0; e < egrcnt; e++) {
105 * This is a bit tricky in that we allocate extra
106 * space for 2 bytes of the 14 byte ethernet header.
107 * These two bytes are passed in the ipath header so
108 * the rest of the data is word aligned. We allocate
109 * 4 bytes so that the data buffer stays word aligned.
110 * See ipath_kreceive() for more details.
112 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
113 if (!skbinfo[e].skb) {
114 ipath_dev_err(dd, "SKB allocation error for "
115 "eager TID %u\n", e);
117 dev_kfree_skb(skbinfo[--e].skb);
124 * After loop above, so we can test non-NULL to see if ready
125 * to use at receive, etc.
127 dd->ipath_port0_skbinfo = skbinfo;
129 for (e = 0; e < egrcnt; e++) {
130 dd->ipath_port0_skbinfo[e].phys =
131 ipath_map_single(dd->pcidev,
132 dd->ipath_port0_skbinfo[e].skb->data,
133 dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
134 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
135 ((char __iomem *) dd->ipath_kregbase +
136 dd->ipath_rcvegrbase),
137 RCVHQ_RCV_TYPE_EAGER,
138 dd->ipath_port0_skbinfo[e].phys);
147 static int bringup_link(struct ipath_devdata *dd)
152 /* hold IBC in reset */
153 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
154 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
158 * set initial max size pkt IBC will send, including ICRC; it's the
159 * PIO buffer size in dwords, less 1; also see ipath_set_mtu()
161 val = (dd->ipath_ibmaxlen >> 2) + 1;
162 ibc = val << dd->ibcc_mpl_shift;
164 /* flowcontrolwatermark is in units of KBytes */
165 ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
167 * How often flowctrl sent. More or less in usecs; balance against
168 * watermark value, so that in theory senders always get a flow
169 * control update in time to not let the IB link go idle.
171 ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
172 /* max error tolerance */
173 ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
174 /* use "real" buffer space for */
175 ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
176 /* IB credit flow control. */
177 ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
178 /* initially come up waiting for TS1, without sending anything. */
179 dd->ipath_ibcctrl = ibc;
181 * Want to start out with both LINKCMD and LINKINITCMD in NOP
182 * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that
183 * to stay a NOP. Flag that we are disabled, for the (unlikely)
184 * case that some recovery path is trying to bring the link up
185 * before we are ready.
187 ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
188 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
189 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
190 ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
191 (unsigned long long) ibc);
192 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
194 // be sure chip saw it
195 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
197 ret = dd->ipath_f_bringup_serdes(dd);
200 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
204 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
205 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
212 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
214 struct ipath_portdata *pd = NULL;
216 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
220 /* The port 0 pkey table is used by the layer interface. */
221 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
222 pd->port_seq_cnt = 1;
227 static int init_chip_first(struct ipath_devdata *dd)
229 struct ipath_portdata *pd;
234 * skip cfgports stuff because we are not allocating memory,
235 * and we don't want problems if the portcnt changed due to
236 * cfgports. We do still check and report a difference, if
237 * not same (should be impossible).
239 dd->ipath_f_config_ports(dd, ipath_cfgports);
241 dd->ipath_cfgports = dd->ipath_portcnt;
242 else if (ipath_cfgports <= dd->ipath_portcnt) {
243 dd->ipath_cfgports = ipath_cfgports;
244 ipath_dbg("Configured to use %u ports out of %u in chip\n",
245 dd->ipath_cfgports, ipath_read_kreg32(dd,
246 dd->ipath_kregs->kr_portcnt));
248 dd->ipath_cfgports = dd->ipath_portcnt;
249 ipath_dbg("Tried to configured to use %u ports; chip "
250 "only supports %u\n", ipath_cfgports,
251 ipath_read_kreg32(dd,
252 dd->ipath_kregs->kr_portcnt));
255 * Allocate full portcnt array, rather than just cfgports, because
256 * cleanup iterates across all possible ports.
258 dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
262 ipath_dev_err(dd, "Unable to allocate portdata array, "
268 pd = create_portdata0(dd);
270 ipath_dev_err(dd, "Unable to allocate portdata for port "
275 dd->ipath_pd[0] = pd;
277 dd->ipath_rcvtidcnt =
278 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
279 dd->ipath_rcvtidbase =
280 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
281 dd->ipath_rcvegrcnt =
282 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
283 dd->ipath_rcvegrbase =
284 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
286 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
287 dd->ipath_piobufbase =
288 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
289 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
290 dd->ipath_piosize2k = val & ~0U;
291 dd->ipath_piosize4k = val >> 32;
292 if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
293 ipath_mtu4096 = 0; /* 4KB not supported by this chip */
294 dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
295 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
296 dd->ipath_piobcnt2k = val & ~0U;
297 dd->ipath_piobcnt4k = val >> 32;
298 dd->ipath_pio2kbase =
299 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
300 (dd->ipath_piobufbase & 0xffffffff));
301 if (dd->ipath_piobcnt4k) {
302 dd->ipath_pio4kbase = (u32 __iomem *)
303 (((char __iomem *) dd->ipath_kregbase) +
304 (dd->ipath_piobufbase >> 32));
306 * 4K buffers take 2 pages; we use roundup just to be
307 * paranoid; we calculate it once here, rather than on
310 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
312 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
314 dd->ipath_piobcnt2k, dd->ipath_piosize2k,
315 dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
316 dd->ipath_piosize4k, dd->ipath_pio4kbase,
319 else ipath_dbg("%u 2k piobufs @ %p\n",
320 dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
322 spin_lock_init(&dd->ipath_tid_lock);
323 spin_lock_init(&dd->ipath_sendctrl_lock);
324 spin_lock_init(&dd->ipath_gpio_lock);
325 spin_lock_init(&dd->ipath_eep_st_lock);
326 mutex_init(&dd->ipath_eep_lock);
333 * init_chip_reset - re-initialize after a reset, or enable
334 * @dd: the infinipath device
336 * sanity check at least some of the values after reset, and
337 * ensure no receive or transmit (explictly, in case reset
340 static int init_chip_reset(struct ipath_devdata *dd)
346 * ensure chip does no sends or receives, tail updates, or
347 * pioavail updates while we re-initialize
349 dd->ipath_rcvctrl &= ~(1ULL << dd->ipath_r_tailupd_shift);
350 for (i = 0; i < dd->ipath_portcnt; i++) {
351 clear_bit(dd->ipath_r_portenable_shift + i,
353 clear_bit(dd->ipath_r_intravail_shift + i,
356 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
359 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
360 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control);
362 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
363 if (rtmp != dd->ipath_rcvtidcnt)
364 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
365 "reset, now %u, using original\n",
366 dd->ipath_rcvtidcnt, rtmp);
367 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
368 if (rtmp != dd->ipath_rcvtidbase)
369 dev_info(&dd->pcidev->dev, "tidbase was %u before "
370 "reset, now %u, using original\n",
371 dd->ipath_rcvtidbase, rtmp);
372 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
373 if (rtmp != dd->ipath_rcvegrcnt)
374 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
375 "reset, now %u, using original\n",
376 dd->ipath_rcvegrcnt, rtmp);
377 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
378 if (rtmp != dd->ipath_rcvegrbase)
379 dev_info(&dd->pcidev->dev, "egrbase was %u before "
380 "reset, now %u, using original\n",
381 dd->ipath_rcvegrbase, rtmp);
386 static int init_pioavailregs(struct ipath_devdata *dd)
390 dd->ipath_pioavailregs_dma = dma_alloc_coherent(
391 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
393 if (!dd->ipath_pioavailregs_dma) {
394 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
401 * we really want L2 cache aligned, but for current CPUs of
402 * interest, they are the same.
404 dd->ipath_statusp = (u64 *)
405 ((char *)dd->ipath_pioavailregs_dma +
406 ((2 * L1_CACHE_BYTES +
407 dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
408 /* copy the current value now that it's really allocated */
409 *dd->ipath_statusp = dd->_ipath_status;
411 * setup buffer to hold freeze msg, accessible to apps,
414 dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
416 dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
425 * init_shadow_tids - allocate the shadow TID array
426 * @dd: the infinipath device
428 * allocate the shadow TID array, so we can ipath_munlock previous
429 * entries. It may make more sense to move the pageshadow to the
430 * port data structure, so we only allocate memory for ports actually
431 * in use, since we at 8k per port, now.
433 static void init_shadow_tids(struct ipath_devdata *dd)
438 pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
439 sizeof(struct page *));
441 ipath_dev_err(dd, "failed to allocate shadow page * "
442 "array, no expected sends!\n");
443 dd->ipath_pageshadow = NULL;
447 addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
450 ipath_dev_err(dd, "failed to allocate shadow dma handle "
451 "array, no expected sends!\n");
452 vfree(dd->ipath_pageshadow);
453 dd->ipath_pageshadow = NULL;
457 memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
458 sizeof(struct page *));
460 dd->ipath_pageshadow = pages;
461 dd->ipath_physshadow = addrs;
464 static void enable_chip(struct ipath_devdata *dd, int reinit)
472 init_waitqueue_head(&ipath_state_wait);
474 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
477 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
478 /* Enable PIO send, and update of PIOavail regs to memory. */
479 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
480 INFINIPATH_S_PIOBUFAVAILUPD;
481 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
482 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
483 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
486 * Enable kernel ports' receive and receive interrupt.
487 * Other ports done as user opens and inits them.
490 dd->ipath_rcvctrl |= (rcvmask << dd->ipath_r_portenable_shift) |
491 (rcvmask << dd->ipath_r_intravail_shift);
492 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL))
493 dd->ipath_rcvctrl |= (1ULL << dd->ipath_r_tailupd_shift);
495 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
499 * now ready for use. this should be cleared whenever we
500 * detect a reset, or initiate one.
502 dd->ipath_flags |= IPATH_INITTED;
505 * Init our shadow copies of head from tail values,
506 * and write head values to match.
508 val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
509 ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
511 /* Initialize so we interrupt on next packet received */
512 ipath_write_ureg(dd, ur_rcvhdrhead,
513 dd->ipath_rhdrhead_intr_off |
514 dd->ipath_pd[0]->port_head, 0);
517 * by now pioavail updates to memory should have occurred, so
518 * copy them into our working/shadow registers; this is in
519 * case something went wrong with abort, but mostly to get the
520 * initial values of the generation bit correct.
522 for (i = 0; i < dd->ipath_pioavregs; i++) {
526 * Chip Errata bug 6641; even and odd qwords>3 are swapped.
528 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
529 pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
531 pioavail = dd->ipath_pioavailregs_dma[i];
532 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail) |
533 (~dd->ipath_pioavailkernel[i] <<
534 INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT);
536 /* can get counters, stats, etc. */
537 dd->ipath_flags |= IPATH_PRESENT;
540 static int init_housekeeping(struct ipath_devdata *dd, int reinit)
546 * have to clear shadow copies of registers at init that are
547 * not otherwise set here, or all kinds of bizarre things
548 * happen with driver on chip reset
550 dd->ipath_rcvhdrsize = 0;
553 * Don't clear ipath_flags as 8bit mode was set before
554 * entering this func. However, we do set the linkstate to
555 * unknown, so we can watch for a transition.
556 * PRESENT is set because we want register reads to work,
557 * and the kernel infrastructure saw it in config space;
558 * We clear it if we have failures.
560 dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
561 dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
562 IPATH_LINKDOWN | IPATH_LINKINIT);
564 ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
566 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
569 * set up fundamental info we need to use the chip; we assume
570 * if the revision reg and these regs are OK, we don't need to
571 * special case the rest
574 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
576 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
578 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
579 ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
580 "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
581 dd->ipath_uregbase, dd->ipath_cregbase);
582 if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
583 || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
584 || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
585 || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
586 ipath_dev_err(dd, "Register read failures from chip, "
587 "giving up initialization\n");
588 dd->ipath_flags &= ~IPATH_PRESENT;
594 /* clear diagctrl register, in case diags were running and crashed */
595 ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
597 /* clear the initial reset flag, in case first driver load */
598 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
601 ipath_cdbg(VERBOSE, "Revision %llx (PCI %x)\n",
602 (unsigned long long) dd->ipath_revision,
605 if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
606 INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
607 ipath_dev_err(dd, "Driver only handles version %d, "
608 "chip swversion is %d (%llx), failng\n",
609 IPATH_CHIP_SWVERSION,
610 (int)(dd->ipath_revision >>
611 INFINIPATH_R_SOFTWARE_SHIFT) &
612 INFINIPATH_R_SOFTWARE_MASK,
613 (unsigned long long) dd->ipath_revision);
617 dd->ipath_majrev = (u8) ((dd->ipath_revision >>
618 INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
619 INFINIPATH_R_CHIPREVMAJOR_MASK);
620 dd->ipath_minrev = (u8) ((dd->ipath_revision >>
621 INFINIPATH_R_CHIPREVMINOR_SHIFT) &
622 INFINIPATH_R_CHIPREVMINOR_MASK);
623 dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
624 INFINIPATH_R_BOARDID_SHIFT) &
625 INFINIPATH_R_BOARDID_MASK);
627 ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
629 snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
630 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
632 IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
633 (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
634 INFINIPATH_R_ARCH_MASK,
635 dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
636 (unsigned)(dd->ipath_revision >>
637 INFINIPATH_R_SOFTWARE_SHIFT) &
638 INFINIPATH_R_SOFTWARE_MASK);
640 ipath_dbg("%s", dd->ipath_boardversion);
646 ret = init_chip_reset(dd);
648 ret = init_chip_first(dd);
655 * ipath_init_chip - do the actual initialization sequence on the chip
656 * @dd: the infinipath device
657 * @reinit: reinitializing, so don't allocate new memory
659 * Do the actual initialization sequence on the chip. This is done
660 * both from the init routine called from the PCI infrastructure, and
661 * when we reset the chip, or detect that it was reset internally,
662 * or it's administratively re-enabled.
664 * Memory allocation here and in called routines is only done in
665 * the first case (reinit == 0). We have to be careful, because even
666 * without memory allocation, we need to re-write all the chip registers
667 * TIDs, etc. after the reset or enable has completed.
669 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
675 struct ipath_portdata *pd;
676 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
679 ret = init_housekeeping(dd, reinit);
684 * we ignore most issues after reporting them, but have to specially
685 * handle hardware-disabled chips.
688 /* unique error, known to ipath_init_one */
694 * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
695 * but then it no longer nicely fits power of two, and since
696 * we now use routines that backend onto __get_free_pages, the
697 * rest would be wasted.
699 dd->ipath_rcvhdrcnt = max(dd->ipath_p0_rcvegrcnt, dd->ipath_rcvegrcnt);
700 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
701 dd->ipath_rcvhdrcnt);
704 * Set up the shadow copies of the piobufavail registers,
705 * which we compare against the chip registers for now, and
706 * the in memory DMA'ed copies of the registers. This has to
707 * be done early, before we calculate lastport, etc.
709 piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
711 * calc number of pioavail registers, and save it; we have 2
714 dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
715 / (sizeof(u64) * BITS_PER_BYTE / 2);
716 uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
717 if (ipath_kpiobufs == 0) {
718 /* not set by user (this is default) */
725 kpiobufs = ipath_kpiobufs;
727 if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
728 int i = (int) piobufs -
729 (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
732 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
733 "%d for kernel leaves too few for %d user ports "
734 "(%d each); using %u\n", kpiobufs,
735 piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
737 * shouldn't change ipath_kpiobufs, because could be
738 * different for different devices...
742 dd->ipath_lastport_piobuf = piobufs - kpiobufs;
743 dd->ipath_pbufsport =
744 uports ? dd->ipath_lastport_piobuf / uports : 0;
745 val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
747 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
748 "add to kernel\n", dd->ipath_pbufsport, val32);
749 dd->ipath_lastport_piobuf -= val32;
751 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
752 dd->ipath_pbufsport, val32);
754 dd->ipath_lastpioindex = 0;
755 dd->ipath_lastpioindexl = dd->ipath_piobcnt2k;
756 ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
757 ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
758 "each for %u user ports\n", kpiobufs,
759 piobufs, dd->ipath_pbufsport, uports);
761 dd->ipath_f_early_init(dd);
763 * Cancel any possible active sends from early driver load.
764 * Follows early_init because some chips have to initialize
765 * PIO buffers in early_init to avoid false parity errors.
767 ipath_cancel_sends(dd, 0);
770 * Early_init sets rcvhdrentsize and rcvhdrsize, so this must be
771 * done after early_init.
774 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
775 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
776 dd->ipath_rcvhdrentsize);
777 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
778 dd->ipath_rcvhdrsize);
781 ret = init_pioavailregs(dd);
782 init_shadow_tids(dd);
787 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
788 dd->ipath_pioavailregs_phys);
790 * this is to detect s/w errors, which the h/w works around by
791 * ignoring the low 6 bits of address, if it wasn't aligned.
793 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
794 if (val != dd->ipath_pioavailregs_phys) {
795 ipath_dev_err(dd, "Catastrophic software error, "
796 "SendPIOAvailAddr written as %lx, "
797 "read back as %llx\n",
798 (unsigned long) dd->ipath_pioavailregs_phys,
799 (unsigned long long) val);
804 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
807 * make sure we are not in freeze, and PIO send enabled, so
808 * writes to pbc happen
810 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
811 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
812 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
813 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
815 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
816 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
817 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
818 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
819 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
822 * before error clears, since we expect serdes pll errors during
823 * this, the first time after reset
825 if (bringup_link(dd)) {
826 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
832 * clear any "expected" hwerrs from reset and/or initialization
833 * clear any that aren't enabled (at least this once), and then
834 * set the enable mask
836 dd->ipath_f_init_hwerrors(dd);
837 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
838 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
839 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
840 dd->ipath_hwerrmask);
843 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
844 /* enable errors that are masked, at least this first time. */
845 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
846 ~dd->ipath_maskederrs);
847 dd->ipath_maskederrs = 0; /* don't re-enable ignored in timer */
848 dd->ipath_errormask =
849 ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask);
850 /* clear any interrupts up to this point (ints still not enabled) */
851 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
853 dd->ipath_f_tidtemplate(dd);
856 * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing
857 * re-init, the simplest way to handle this is to free
858 * existing, and re-allocate.
859 * Need to re-create rest of port 0 portdata as well.
861 pd = dd->ipath_pd[0];
863 struct ipath_portdata *npd;
866 * Alloc and init new ipath_portdata for port0,
867 * Then free old pd. Could lead to fragmentation, but also
868 * makes later support for hot-swap easier.
870 npd = create_portdata0(dd);
872 ipath_free_pddata(dd, pd);
873 dd->ipath_pd[0] = npd;
876 ipath_dev_err(dd, "Unable to allocate portdata"
877 " for port 0, failing\n");
882 ret = ipath_create_rcvhdrq(dd, pd);
884 ret = create_port0_egr(dd);
886 ipath_dev_err(dd, "failed to allocate kernel port's "
887 "rcvhdrq and/or egr bufs\n");
891 enable_chip(dd, reinit);
895 * Used when we close a port, for DMA already in flight
898 dd->ipath_dummy_hdrq = dma_alloc_coherent(
899 &dd->pcidev->dev, dd->ipath_pd[0]->port_rcvhdrq_size,
900 &dd->ipath_dummy_hdrq_phys,
902 if (!dd->ipath_dummy_hdrq) {
903 dev_info(&dd->pcidev->dev,
904 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
905 dd->ipath_pd[0]->port_rcvhdrq_size);
906 /* fallback to just 0'ing */
907 dd->ipath_dummy_hdrq_phys = 0UL;
912 * cause retrigger of pending interrupts ignored during init,
913 * even if we had errors
915 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
917 if (!dd->ipath_stats_timer_active) {
919 * first init, or after an admin disable/enable
920 * set up stats retrieval timer, even if we had errors
921 * in last portion of setup
923 init_timer(&dd->ipath_stats_timer);
924 dd->ipath_stats_timer.function = ipath_get_faststats;
925 dd->ipath_stats_timer.data = (unsigned long) dd;
926 /* every 5 seconds; */
927 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
928 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
929 add_timer(&dd->ipath_stats_timer);
930 dd->ipath_stats_timer_active = 1;
933 /* Set up HoL state */
934 init_timer(&dd->ipath_hol_timer);
935 dd->ipath_hol_timer.function = ipath_hol_event;
936 dd->ipath_hol_timer.data = (unsigned long)dd;
937 dd->ipath_hol_state = IPATH_HOL_UP;
941 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
942 if (!dd->ipath_f_intrsetup(dd)) {
943 /* now we can enable all interrupts from the chip */
944 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
946 /* force re-interrupt of any pending interrupts. */
947 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
949 /* chip is usable; mark it as initialized */
950 *dd->ipath_statusp |= IPATH_STATUS_INITTED;
952 ipath_dev_err(dd, "No interrupts enabled, couldn't "
953 "setup interrupt address\n");
955 if (dd->ipath_cfgports > ipath_stats.sps_nports)
957 * sps_nports is a global, so, we set it to
958 * the highest number of ports of any of the
959 * chips we find; we never decrement it, at
960 * least for now. Since this might have changed
961 * over disable/enable or prior to reset, always
962 * do the check and potentially adjust.
964 ipath_stats.sps_nports = dd->ipath_cfgports;
966 ipath_dbg("Failed (%d) to initialize chip\n", ret);
968 /* if ret is non-zero, we probably should do some cleanup
973 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
975 struct ipath_devdata *dd;
980 ret = ipath_parse_ushort(str, &val);
982 spin_lock_irqsave(&ipath_devs_lock, flags);
992 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
993 if (dd->ipath_kregbase)
995 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
996 (dd->ipath_cfgports *
997 IPATH_MIN_USER_PORT_BUFCNT)))
1001 "Allocating %d PIO bufs for kernel leaves "
1002 "too few for %d user ports (%d each)\n",
1003 val, dd->ipath_cfgports - 1,
1004 IPATH_MIN_USER_PORT_BUFCNT);
1008 dd->ipath_lastport_piobuf =
1009 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1012 ipath_kpiobufs = val;
1015 spin_unlock_irqrestore(&ipath_devs_lock, flags);