2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
39 #include "ipath_common.h"
42 * min buffers we want to have per port, after driver
44 #define IPATH_MIN_USER_PORT_BUFCNT 8
47 * Number of ports we are configured to use (to allow for more pio
48 * buffers per port, etc.) Zero means use chip value.
50 static ushort ipath_cfgports;
52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
56 * Number of buffers reserved for driver (verbs and layered drivers.)
57 * Reserved at end of buffer list. Initialized based on
58 * number of PIO buffers if not set via module interface.
59 * The problem with this is that it's global, but we'll use different
60 * numbers for different chip types. So the default value is not
61 * very useful. I've redefined it for the 1.3 release so that it's
62 * zero unless set by the user to something else, in which case we
65 static ushort ipath_kpiobufs;
67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
70 &ipath_kpiobufs, S_IWUSR | S_IRUGO);
71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
74 * create_port0_egr - allocate the eager TID buffers
75 * @dd: the infinipath device
77 * This code is now quite different for user and kernel, because
78 * the kernel uses skb's, for the accelerated network performance.
79 * This is the kernel (port0) version.
81 * Allocate the eager TID buffers and program them into infinipath.
82 * We use the network layer alloc_skb() allocator to allocate the
83 * memory, and either use the buffers as is for things like verbs
84 * packets, or pass the buffers up to the ipath layered driver and
85 * thence the network layer, replacing them as we do so (see
88 static int create_port0_egr(struct ipath_devdata *dd)
91 struct ipath_skbinfo *skbinfo;
94 egrcnt = dd->ipath_p0_rcvegrcnt;
96 skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
97 if (skbinfo == NULL) {
98 ipath_dev_err(dd, "allocation error for eager TID "
103 for (e = 0; e < egrcnt; e++) {
105 * This is a bit tricky in that we allocate extra
106 * space for 2 bytes of the 14 byte ethernet header.
107 * These two bytes are passed in the ipath header so
108 * the rest of the data is word aligned. We allocate
109 * 4 bytes so that the data buffer stays word aligned.
110 * See ipath_kreceive() for more details.
112 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
113 if (!skbinfo[e].skb) {
114 ipath_dev_err(dd, "SKB allocation error for "
115 "eager TID %u\n", e);
117 dev_kfree_skb(skbinfo[--e].skb);
124 * After loop above, so we can test non-NULL to see if ready
125 * to use at receive, etc.
127 dd->ipath_port0_skbinfo = skbinfo;
129 for (e = 0; e < egrcnt; e++) {
130 dd->ipath_port0_skbinfo[e].phys =
131 ipath_map_single(dd->pcidev,
132 dd->ipath_port0_skbinfo[e].skb->data,
133 dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
134 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
135 ((char __iomem *) dd->ipath_kregbase +
136 dd->ipath_rcvegrbase),
137 RCVHQ_RCV_TYPE_EAGER,
138 dd->ipath_port0_skbinfo[e].phys);
147 static int bringup_link(struct ipath_devdata *dd)
152 /* hold IBC in reset */
153 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
154 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
158 * set initial max size pkt IBC will send, including ICRC; it's the
159 * PIO buffer size in dwords, less 1; also see ipath_set_mtu()
161 val = (dd->ipath_ibmaxlen >> 2) + 1;
162 ibc = val << dd->ibcc_mpl_shift;
164 /* flowcontrolwatermark is in units of KBytes */
165 ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
167 * How often flowctrl sent. More or less in usecs; balance against
168 * watermark value, so that in theory senders always get a flow
169 * control update in time to not let the IB link go idle.
171 ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
172 /* max error tolerance */
173 ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
174 /* use "real" buffer space for */
175 ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
176 /* IB credit flow control. */
177 ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
178 /* initially come up waiting for TS1, without sending anything. */
179 dd->ipath_ibcctrl = ibc;
181 * Want to start out with both LINKCMD and LINKINITCMD in NOP
182 * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that
183 * to stay a NOP. Flag that we are disabled, for the (unlikely)
184 * case that some recovery path is trying to bring the link up
185 * before we are ready.
187 ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
188 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
189 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
190 ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
191 (unsigned long long) ibc);
192 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
194 // be sure chip saw it
195 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
197 ret = dd->ipath_f_bringup_serdes(dd);
200 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
204 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
205 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
212 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
214 struct ipath_portdata *pd = NULL;
216 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
220 /* The port 0 pkey table is used by the layer interface. */
221 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
226 static int init_chip_first(struct ipath_devdata *dd,
227 struct ipath_portdata **pdp)
229 struct ipath_portdata *pd = NULL;
234 * skip cfgports stuff because we are not allocating memory,
235 * and we don't want problems if the portcnt changed due to
236 * cfgports. We do still check and report a difference, if
237 * not same (should be impossible).
239 dd->ipath_f_config_ports(dd, ipath_cfgports);
241 dd->ipath_cfgports = dd->ipath_portcnt;
242 else if (ipath_cfgports <= dd->ipath_portcnt) {
243 dd->ipath_cfgports = ipath_cfgports;
244 ipath_dbg("Configured to use %u ports out of %u in chip\n",
245 dd->ipath_cfgports, dd->ipath_portcnt);
247 dd->ipath_cfgports = dd->ipath_portcnt;
248 ipath_dbg("Tried to configured to use %u ports; chip "
249 "only supports %u\n", ipath_cfgports,
253 * Allocate full portcnt array, rather than just cfgports, because
254 * cleanup iterates across all possible ports.
256 dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
260 ipath_dev_err(dd, "Unable to allocate portdata array, "
266 pd = create_portdata0(dd);
268 ipath_dev_err(dd, "Unable to allocate portdata for port "
273 dd->ipath_pd[0] = pd;
275 dd->ipath_rcvtidcnt =
276 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
277 dd->ipath_rcvtidbase =
278 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
279 dd->ipath_rcvegrcnt =
280 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
281 dd->ipath_rcvegrbase =
282 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
284 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
285 dd->ipath_piobufbase =
286 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
287 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
288 dd->ipath_piosize2k = val & ~0U;
289 dd->ipath_piosize4k = val >> 32;
290 if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
291 ipath_mtu4096 = 0; /* 4KB not supported by this chip */
292 dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
293 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
294 dd->ipath_piobcnt2k = val & ~0U;
295 dd->ipath_piobcnt4k = val >> 32;
296 dd->ipath_pio2kbase =
297 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
298 (dd->ipath_piobufbase & 0xffffffff));
299 if (dd->ipath_piobcnt4k) {
300 dd->ipath_pio4kbase = (u32 __iomem *)
301 (((char __iomem *) dd->ipath_kregbase) +
302 (dd->ipath_piobufbase >> 32));
304 * 4K buffers take 2 pages; we use roundup just to be
305 * paranoid; we calculate it once here, rather than on
308 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
310 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
312 dd->ipath_piobcnt2k, dd->ipath_piosize2k,
313 dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
314 dd->ipath_piosize4k, dd->ipath_pio4kbase,
317 else ipath_dbg("%u 2k piobufs @ %p\n",
318 dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
320 spin_lock_init(&dd->ipath_tid_lock);
321 spin_lock_init(&dd->ipath_sendctrl_lock);
322 spin_lock_init(&dd->ipath_gpio_lock);
323 spin_lock_init(&dd->ipath_eep_st_lock);
324 mutex_init(&dd->ipath_eep_lock);
332 * init_chip_reset - re-initialize after a reset, or enable
333 * @dd: the infinipath device
334 * @pdp: output for port data
336 * sanity check at least some of the values after reset, and
337 * ensure no receive or transmit (explictly, in case reset
340 static int init_chip_reset(struct ipath_devdata *dd,
341 struct ipath_portdata **pdp)
345 *pdp = dd->ipath_pd[0];
346 /* ensure chip does no sends or receives while we re-initialize */
347 dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
348 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, dd->ipath_rcvctrl);
349 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
350 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control);
352 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
353 if (dd->ipath_portcnt != rtmp)
354 dev_info(&dd->pcidev->dev, "portcnt was %u before "
355 "reset, now %u, using original\n",
356 dd->ipath_portcnt, rtmp);
357 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
358 if (rtmp != dd->ipath_rcvtidcnt)
359 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
360 "reset, now %u, using original\n",
361 dd->ipath_rcvtidcnt, rtmp);
362 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
363 if (rtmp != dd->ipath_rcvtidbase)
364 dev_info(&dd->pcidev->dev, "tidbase was %u before "
365 "reset, now %u, using original\n",
366 dd->ipath_rcvtidbase, rtmp);
367 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
368 if (rtmp != dd->ipath_rcvegrcnt)
369 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
370 "reset, now %u, using original\n",
371 dd->ipath_rcvegrcnt, rtmp);
372 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
373 if (rtmp != dd->ipath_rcvegrbase)
374 dev_info(&dd->pcidev->dev, "egrbase was %u before "
375 "reset, now %u, using original\n",
376 dd->ipath_rcvegrbase, rtmp);
381 static int init_pioavailregs(struct ipath_devdata *dd)
385 dd->ipath_pioavailregs_dma = dma_alloc_coherent(
386 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
388 if (!dd->ipath_pioavailregs_dma) {
389 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
396 * we really want L2 cache aligned, but for current CPUs of
397 * interest, they are the same.
399 dd->ipath_statusp = (u64 *)
400 ((char *)dd->ipath_pioavailregs_dma +
401 ((2 * L1_CACHE_BYTES +
402 dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
403 /* copy the current value now that it's really allocated */
404 *dd->ipath_statusp = dd->_ipath_status;
406 * setup buffer to hold freeze msg, accessible to apps,
409 dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
411 dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
420 * init_shadow_tids - allocate the shadow TID array
421 * @dd: the infinipath device
423 * allocate the shadow TID array, so we can ipath_munlock previous
424 * entries. It may make more sense to move the pageshadow to the
425 * port data structure, so we only allocate memory for ports actually
426 * in use, since we at 8k per port, now.
428 static void init_shadow_tids(struct ipath_devdata *dd)
433 pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
434 sizeof(struct page *));
436 ipath_dev_err(dd, "failed to allocate shadow page * "
437 "array, no expected sends!\n");
438 dd->ipath_pageshadow = NULL;
442 addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
445 ipath_dev_err(dd, "failed to allocate shadow dma handle "
446 "array, no expected sends!\n");
447 vfree(dd->ipath_pageshadow);
448 dd->ipath_pageshadow = NULL;
452 memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
453 sizeof(struct page *));
455 dd->ipath_pageshadow = pages;
456 dd->ipath_physshadow = addrs;
459 static void enable_chip(struct ipath_devdata *dd,
460 struct ipath_portdata *pd, int reinit)
467 init_waitqueue_head(&ipath_state_wait);
469 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
472 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
473 /* Enable PIO send, and update of PIOavail regs to memory. */
474 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
475 INFINIPATH_S_PIOBUFAVAILUPD;
476 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
477 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
478 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
481 * enable port 0 receive, and receive interrupt. other ports
482 * done as user opens and inits them.
484 dd->ipath_rcvctrl = (1ULL << dd->ipath_r_tailupd_shift) |
485 (1ULL << dd->ipath_r_portenable_shift) |
486 (1ULL << dd->ipath_r_intravail_shift);
487 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
491 * now ready for use. this should be cleared whenever we
492 * detect a reset, or initiate one.
494 dd->ipath_flags |= IPATH_INITTED;
497 * init our shadow copies of head from tail values, and write
498 * head values to match.
500 val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
501 ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
503 /* Initialize so we interrupt on next packet received */
504 ipath_write_ureg(dd, ur_rcvhdrhead,
505 dd->ipath_rhdrhead_intr_off |
506 dd->ipath_pd[0]->port_head, 0);
509 * by now pioavail updates to memory should have occurred, so
510 * copy them into our working/shadow registers; this is in
511 * case something went wrong with abort, but mostly to get the
512 * initial values of the generation bit correct.
514 for (i = 0; i < dd->ipath_pioavregs; i++) {
518 * Chip Errata bug 6641; even and odd qwords>3 are swapped.
520 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
521 pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
523 pioavail = dd->ipath_pioavailregs_dma[i];
524 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail);
526 /* can get counters, stats, etc. */
527 dd->ipath_flags |= IPATH_PRESENT;
530 static int init_housekeeping(struct ipath_devdata *dd,
531 struct ipath_portdata **pdp, int reinit)
537 * have to clear shadow copies of registers at init that are
538 * not otherwise set here, or all kinds of bizarre things
539 * happen with driver on chip reset
541 dd->ipath_rcvhdrsize = 0;
544 * Don't clear ipath_flags as 8bit mode was set before
545 * entering this func. However, we do set the linkstate to
546 * unknown, so we can watch for a transition.
547 * PRESENT is set because we want register reads to work,
548 * and the kernel infrastructure saw it in config space;
549 * We clear it if we have failures.
551 dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
552 dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
553 IPATH_LINKDOWN | IPATH_LINKINIT);
555 ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
557 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
560 * set up fundamental info we need to use the chip; we assume
561 * if the revision reg and these regs are OK, we don't need to
562 * special case the rest
565 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
567 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
569 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
570 ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
571 "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
572 dd->ipath_uregbase, dd->ipath_cregbase);
573 if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
574 || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
575 || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
576 || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
577 ipath_dev_err(dd, "Register read failures from chip, "
578 "giving up initialization\n");
579 dd->ipath_flags &= ~IPATH_PRESENT;
585 /* clear diagctrl register, in case diags were running and crashed */
586 ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
588 /* clear the initial reset flag, in case first driver load */
589 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
593 ret = init_chip_reset(dd, pdp);
595 ret = init_chip_first(dd, pdp);
600 ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
601 "%u egrtids\n", (unsigned long long) dd->ipath_revision,
602 dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
603 dd->ipath_rcvegrcnt);
605 if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
606 INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
607 ipath_dev_err(dd, "Driver only handles version %d, "
608 "chip swversion is %d (%llx), failng\n",
609 IPATH_CHIP_SWVERSION,
610 (int)(dd->ipath_revision >>
611 INFINIPATH_R_SOFTWARE_SHIFT) &
612 INFINIPATH_R_SOFTWARE_MASK,
613 (unsigned long long) dd->ipath_revision);
617 dd->ipath_majrev = (u8) ((dd->ipath_revision >>
618 INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
619 INFINIPATH_R_CHIPREVMAJOR_MASK);
620 dd->ipath_minrev = (u8) ((dd->ipath_revision >>
621 INFINIPATH_R_CHIPREVMINOR_SHIFT) &
622 INFINIPATH_R_CHIPREVMINOR_MASK);
623 dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
624 INFINIPATH_R_BOARDID_SHIFT) &
625 INFINIPATH_R_BOARDID_MASK);
627 ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
629 snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
630 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
632 IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
633 (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
634 INFINIPATH_R_ARCH_MASK,
635 dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
636 (unsigned)(dd->ipath_revision >>
637 INFINIPATH_R_SOFTWARE_SHIFT) &
638 INFINIPATH_R_SOFTWARE_MASK);
640 ipath_dbg("%s", dd->ipath_boardversion);
648 * ipath_init_chip - do the actual initialization sequence on the chip
649 * @dd: the infinipath device
650 * @reinit: reinitializing, so don't allocate new memory
652 * Do the actual initialization sequence on the chip. This is done
653 * both from the init routine called from the PCI infrastructure, and
654 * when we reset the chip, or detect that it was reset internally,
655 * or it's administratively re-enabled.
657 * Memory allocation here and in called routines is only done in
658 * the first case (reinit == 0). We have to be careful, because even
659 * without memory allocation, we need to re-write all the chip registers
660 * TIDs, etc. after the reset or enable has completed.
662 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
668 struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
669 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
672 ret = init_housekeeping(dd, &pd, reinit);
677 * we ignore most issues after reporting them, but have to specially
678 * handle hardware-disabled chips.
681 /* unique error, known to ipath_init_one */
687 * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
688 * but then it no longer nicely fits power of two, and since
689 * we now use routines that backend onto __get_free_pages, the
690 * rest would be wasted.
692 dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
693 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
694 dd->ipath_rcvhdrcnt);
697 * Set up the shadow copies of the piobufavail registers,
698 * which we compare against the chip registers for now, and
699 * the in memory DMA'ed copies of the registers. This has to
700 * be done early, before we calculate lastport, etc.
702 piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
704 * calc number of pioavail registers, and save it; we have 2
707 dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
708 / (sizeof(u64) * BITS_PER_BYTE / 2);
709 uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
710 if (ipath_kpiobufs == 0) {
711 /* not set by user (this is default) */
718 kpiobufs = ipath_kpiobufs;
720 if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
721 int i = (int) piobufs -
722 (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
725 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
726 "%d for kernel leaves too few for %d user ports "
727 "(%d each); using %u\n", kpiobufs,
728 piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
730 * shouldn't change ipath_kpiobufs, because could be
731 * different for different devices...
735 dd->ipath_lastport_piobuf = piobufs - kpiobufs;
736 dd->ipath_pbufsport =
737 uports ? dd->ipath_lastport_piobuf / uports : 0;
738 val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
740 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
741 "add to kernel\n", dd->ipath_pbufsport, val32);
742 dd->ipath_lastport_piobuf -= val32;
743 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
744 dd->ipath_pbufsport, val32);
746 dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
747 ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
748 "each for %u user ports\n", kpiobufs,
749 piobufs, dd->ipath_pbufsport, uports);
751 dd->ipath_f_early_init(dd);
753 * cancel any possible active sends from early driver load.
754 * Follows early_init because some chips have to initialize
755 * PIO buffers in early_init to avoid false parity errors.
757 ipath_cancel_sends(dd, 0);
759 /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
760 * done after early_init */
762 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
763 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
764 dd->ipath_rcvhdrentsize);
765 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
766 dd->ipath_rcvhdrsize);
769 ret = init_pioavailregs(dd);
770 init_shadow_tids(dd);
775 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
776 dd->ipath_pioavailregs_phys);
778 * this is to detect s/w errors, which the h/w works around by
779 * ignoring the low 6 bits of address, if it wasn't aligned.
781 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
782 if (val != dd->ipath_pioavailregs_phys) {
783 ipath_dev_err(dd, "Catastrophic software error, "
784 "SendPIOAvailAddr written as %lx, "
785 "read back as %llx\n",
786 (unsigned long) dd->ipath_pioavailregs_phys,
787 (unsigned long long) val);
792 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
795 * make sure we are not in freeze, and PIO send enabled, so
796 * writes to pbc happen
798 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
799 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
800 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
801 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
803 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
804 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
805 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
806 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
807 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
810 * before error clears, since we expect serdes pll errors during
811 * this, the first time after reset
813 if (bringup_link(dd)) {
814 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
820 * clear any "expected" hwerrs from reset and/or initialization
821 * clear any that aren't enabled (at least this once), and then
822 * set the enable mask
824 dd->ipath_f_init_hwerrors(dd);
825 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
826 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
827 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
828 dd->ipath_hwerrmask);
831 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
832 /* enable errors that are masked, at least this first time. */
833 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
834 ~dd->ipath_maskederrs);
835 dd->ipath_errormask = ipath_read_kreg64(dd,
836 dd->ipath_kregs->kr_errormask);
837 /* clear any interrupts up to this point (ints still not enabled) */
838 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
841 * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing
842 * re-init, the simplest way to handle this is to free
843 * existing, and re-allocate.
844 * Need to re-create rest of port 0 portdata as well.
847 /* Alloc and init new ipath_portdata for port0,
848 * Then free old pd. Could lead to fragmentation, but also
849 * makes later support for hot-swap easier.
851 struct ipath_portdata *npd;
852 npd = create_portdata0(dd);
854 ipath_free_pddata(dd, pd);
855 dd->ipath_pd[0] = pd = npd;
857 ipath_dev_err(dd, "Unable to allocate portdata for"
858 " port 0, failing\n");
863 dd->ipath_f_tidtemplate(dd);
864 ret = ipath_create_rcvhdrq(dd, pd);
866 dd->ipath_hdrqtailptr =
867 (volatile __le64 *)pd->port_rcvhdrtail_kvaddr;
868 ret = create_port0_egr(dd);
871 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
872 "rcvhdrq and/or egr bufs\n");
874 enable_chip(dd, pd, reinit);
877 if (!ret && !reinit) {
878 /* used when we close a port, for DMA already in flight at close */
879 dd->ipath_dummy_hdrq = dma_alloc_coherent(
880 &dd->pcidev->dev, pd->port_rcvhdrq_size,
881 &dd->ipath_dummy_hdrq_phys,
883 if (!dd->ipath_dummy_hdrq ) {
884 dev_info(&dd->pcidev->dev,
885 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
886 pd->port_rcvhdrq_size);
887 /* fallback to just 0'ing */
888 dd->ipath_dummy_hdrq_phys = 0UL;
893 * cause retrigger of pending interrupts ignored during init,
894 * even if we had errors
896 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
898 if(!dd->ipath_stats_timer_active) {
900 * first init, or after an admin disable/enable
901 * set up stats retrieval timer, even if we had errors
902 * in last portion of setup
904 init_timer(&dd->ipath_stats_timer);
905 dd->ipath_stats_timer.function = ipath_get_faststats;
906 dd->ipath_stats_timer.data = (unsigned long) dd;
907 /* every 5 seconds; */
908 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
909 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
910 add_timer(&dd->ipath_stats_timer);
911 dd->ipath_stats_timer_active = 1;
914 /* Set up HoL state */
915 init_timer(&dd->ipath_hol_timer);
916 dd->ipath_hol_timer.function = ipath_hol_event;
917 dd->ipath_hol_timer.data = (unsigned long)dd;
918 dd->ipath_hol_state = IPATH_HOL_UP;
922 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
923 if (!dd->ipath_f_intrsetup(dd)) {
924 /* now we can enable all interrupts from the chip */
925 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
927 /* force re-interrupt of any pending interrupts. */
928 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
930 /* chip is usable; mark it as initialized */
931 *dd->ipath_statusp |= IPATH_STATUS_INITTED;
933 ipath_dev_err(dd, "No interrupts enabled, couldn't "
934 "setup interrupt address\n");
936 if (dd->ipath_cfgports > ipath_stats.sps_nports)
938 * sps_nports is a global, so, we set it to
939 * the highest number of ports of any of the
940 * chips we find; we never decrement it, at
941 * least for now. Since this might have changed
942 * over disable/enable or prior to reset, always
943 * do the check and potentially adjust.
945 ipath_stats.sps_nports = dd->ipath_cfgports;
947 ipath_dbg("Failed (%d) to initialize chip\n", ret);
949 /* if ret is non-zero, we probably should do some cleanup
954 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
956 struct ipath_devdata *dd;
961 ret = ipath_parse_ushort(str, &val);
963 spin_lock_irqsave(&ipath_devs_lock, flags);
973 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
974 if (dd->ipath_kregbase)
976 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
977 (dd->ipath_cfgports *
978 IPATH_MIN_USER_PORT_BUFCNT)))
982 "Allocating %d PIO bufs for kernel leaves "
983 "too few for %d user ports (%d each)\n",
984 val, dd->ipath_cfgports - 1,
985 IPATH_MIN_USER_PORT_BUFCNT);
989 dd->ipath_lastport_piobuf =
990 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
993 ipath_kpiobufs = val;
996 spin_unlock_irqrestore(&ipath_devs_lock, flags);