drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/blackfin.h>
  25 #include <asm/portmux.h>
  26 #include <asm/irq.h>
  27
  28 /* SMBus mode*/
  29 #define TWI_I2C_MODE_STANDARD           1
  30 #define TWI_I2C_MODE_STANDARDSUB        2
  31 #define TWI_I2C_MODE_COMBINED           3
  32 #define TWI_I2C_MODE_REPEAT             4
  33
  34 struct bfin_twi_iface {
  35         int                     irq;
  36         spinlock_t              lock;
  37         char                    read_write;
  38         u8                      command;
  39         u8                      *transPtr;
  40         int                     readNum;
  41         int                     writeNum;
  42         int                     cur_mode;
  43         int                     manual_stop;
  44         int                     result;
  45         struct i2c_adapter      adap;
  46         struct completion       complete;
  47         struct i2c_msg          *pmsg;
  48         int                     msg_num;
  49         int                     cur_msg;
  50         u16                     saved_clkdiv;
  51         u16                     saved_control;
  52         void __iomem            *regs_base;
  53 };
  54
  55
  56 #define DEFINE_TWI_REG(reg, off) \
  57 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  58         { return bfin_read16(iface->regs_base + (off)); } \
  59 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  60         { bfin_write16(iface->regs_base + (off), v); }
  61
  62 DEFINE_TWI_REG(CLKDIV, 0x00)
  63 DEFINE_TWI_REG(CONTROL, 0x04)
  64 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  65 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  66 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  67 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  68 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  69 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  70 DEFINE_TWI_REG(INT_STAT, 0x20)
  71 DEFINE_TWI_REG(INT_MASK, 0x24)
  72 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  73 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  74 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  75 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  76 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  77 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  78
  79 static const u16 pin_req[2][3] = {
  80         {P_TWI0_SCL, P_TWI0_SDA, 0},
  81         {P_TWI1_SCL, P_TWI1_SDA, 0},
  82 };
  83
  84 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
  85 {
  86         unsigned short twi_int_status = read_INT_STAT(iface);
  87         unsigned short mast_stat = read_MASTER_STAT(iface);
  88
  89         if (twi_int_status & XMTSERV) {
  90                 /* Transmit next data */
  91                 if (iface->writeNum > 0) {
  92                         write_XMT_DATA8(iface, *(iface->transPtr++));
  93                         iface->writeNum--;
  94                 }
  95                 /* start receive immediately after complete sending in
  96                  * combine mode.
  97                  */
  98                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
  99                         write_MASTER_CTL(iface,
 100                                 read_MASTER_CTL(iface) | MDIR | RSTART);
 101                 else if (iface->manual_stop)
 102                         write_MASTER_CTL(iface,
 103                                 read_MASTER_CTL(iface) | STOP);
 104                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 105                          iface->cur_msg + 1 < iface->msg_num) {
 106                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 107                                 write_MASTER_CTL(iface,
 108                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 109                         else
 110                                 write_MASTER_CTL(iface,
 111                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 112                 }
 113                 SSYNC();
 114                 /* Clear status */
 115                 write_INT_STAT(iface, XMTSERV);
 116                 SSYNC();
 117         }
 118         if (twi_int_status & RCVSERV) {
 119                 if (iface->readNum > 0) {
 120                         /* Receive next data */
 121                         *(iface->transPtr) = read_RCV_DATA8(iface);
 122                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 123                                 /* Change combine mode into sub mode after
 124                                  * read first data.
 125                                  */
 126                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 127                                 /* Get read number from first byte in block
 128                                  * combine mode.
 129                                  */
 130                                 if (iface->readNum == 1 && iface->manual_stop)
 131                                         iface->readNum = *iface->transPtr + 1;
 132                         }
 133                         iface->transPtr++;
 134                         iface->readNum--;
 135                 } else if (iface->manual_stop) {
 136                         write_MASTER_CTL(iface,
 137                                 read_MASTER_CTL(iface) | STOP);
 138                         SSYNC();
 139                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 140                            iface->cur_msg + 1 < iface->msg_num) {
 141                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 142                                 write_MASTER_CTL(iface,
 143                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 144                         else
 145                                 write_MASTER_CTL(iface,
 146                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 147                         SSYNC();
 148                 }
 149                 /* Clear interrupt source */
 150                 write_INT_STAT(iface, RCVSERV);
 151                 SSYNC();
 152         }
 153         if (twi_int_status & MERR) {
 154                 write_INT_STAT(iface, MERR);
 155                 write_INT_MASK(iface, 0);
 156                 write_MASTER_STAT(iface, 0x3e);
 157                 write_MASTER_CTL(iface, 0);
 158                 SSYNC();
 159                 iface->result = -EIO;
 160
 161                 if (mast_stat & LOSTARB)
 162                         dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
 163                 if (mast_stat & ANAK)
 164                         dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
 165                 if (mast_stat & DNAK)
 166                         dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
 167                 if (mast_stat & BUFRDERR)
 168                         dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
 169                 if (mast_stat & BUFWRERR)
 170                         dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
 171
 172                 /* if both err and complete int stats are set, return proper
 173                  * results.
 174                  */
 175                 if (twi_int_status & MCOMP) {
 176                         write_INT_STAT(iface, MCOMP);
 177                         write_INT_MASK(iface, 0);
 178                         write_MASTER_CTL(iface, 0);
 179                         SSYNC();
 180                         /* If it is a quick transfer, only address without data,
 181                          * not an err, return 1.
 182                          * If address is acknowledged return 1.
 183                          */
 184                         if ((iface->writeNum == 0 && (mast_stat & BUFRDERR))
 185                                 || !(mast_stat & ANAK))
 186                                 iface->result = 1;
 187                 }
 188                 complete(&iface->complete);
 189                 return;
 190         }
 191         if (twi_int_status & MCOMP) {
 192                 write_INT_STAT(iface, MCOMP);
 193                 SSYNC();
 194                 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 195                         if (iface->readNum == 0) {
 196                                 /* set the read number to 1 and ask for manual
 197                                  * stop in block combine mode
 198                                  */
 199                                 iface->readNum = 1;
 200                                 iface->manual_stop = 1;
 201                                 write_MASTER_CTL(iface,
 202                                         read_MASTER_CTL(iface) | (0xff << 6));
 203                         } else {
 204                                 /* set the readd number in other
 205                                  * combine mode.
 206                                  */
 207                                 write_MASTER_CTL(iface,
 208                                         (read_MASTER_CTL(iface) &
 209                                         (~(0xff << 6))) |
 210                                         (iface->readNum << 6));
 211                         }
 212                         /* remove restart bit and enable master receive */
 213                         write_MASTER_CTL(iface,
 214                                 read_MASTER_CTL(iface) & ~RSTART);
 215                         SSYNC();
 216                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 217                                 iface->cur_msg+1 < iface->msg_num) {
 218                         iface->cur_msg++;
 219                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 220                         iface->writeNum = iface->readNum =
 221                                 iface->pmsg[iface->cur_msg].len;
 222                         /* Set Transmit device address */
 223                         write_MASTER_ADDR(iface,
 224                                 iface->pmsg[iface->cur_msg].addr);
 225                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 226                                 iface->read_write = I2C_SMBUS_READ;
 227                         else {
 228                                 iface->read_write = I2C_SMBUS_WRITE;
 229                                 /* Transmit first data */
 230                                 if (iface->writeNum > 0) {
 231                                         write_XMT_DATA8(iface,
 232                                                 *(iface->transPtr++));
 233                                         iface->writeNum--;
 234                                         SSYNC();
 235                                 }
 236                         }
 237
 238                         if (iface->pmsg[iface->cur_msg].len <= 255)
 239                                         write_MASTER_CTL(iface,
 240                                         (read_MASTER_CTL(iface) &
 241                                         (~(0xff << 6))) |
 242                                 (iface->pmsg[iface->cur_msg].len << 6));
 243                         else {
 244                                 write_MASTER_CTL(iface,
 245                                         (read_MASTER_CTL(iface) |
 246                                         (0xff << 6)));
 247                                 iface->manual_stop = 1;
 248                         }
 249                         /* remove restart bit and enable master receive */
 250                         write_MASTER_CTL(iface,
 251                                 read_MASTER_CTL(iface) & ~RSTART);
 252                         SSYNC();
 253                 } else {
 254                         iface->result = 1;
 255                         write_INT_MASK(iface, 0);
 256                         write_MASTER_CTL(iface, 0);
 257                         SSYNC();
 258                 }
 259         }
 260         complete(&iface->complete);
 261 }
 262
 263 /* Interrupt handler */
 264 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 265 {
 266         struct bfin_twi_iface *iface = dev_id;
 267         unsigned long flags;
 268
 269         spin_lock_irqsave(&iface->lock, flags);
 270         bfin_twi_handle_interrupt(iface);
 271         spin_unlock_irqrestore(&iface->lock, flags);
 272         return IRQ_HANDLED;
 273 }
 274
 275 /*
 276  * One i2c master transfer
 277  */
 278 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 279                                 struct i2c_msg *msgs, int num)
 280 {
 281         struct bfin_twi_iface *iface = adap->algo_data;
 282         struct i2c_msg *pmsg;
 283         int rc = 0;
 284
 285         if (!(read_CONTROL(iface) & TWI_ENA))
 286                 return -ENXIO;
 287
 288         while (read_MASTER_STAT(iface) & BUSBUSY)
 289                 yield();
 290
 291         iface->pmsg = msgs;
 292         iface->msg_num = num;
 293         iface->cur_msg = 0;
 294
 295         pmsg = &msgs[0];
 296         if (pmsg->flags & I2C_M_TEN) {
 297                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 298                 return -EINVAL;
 299         }
 300
 301         iface->cur_mode = TWI_I2C_MODE_REPEAT;
 302         iface->manual_stop = 0;
 303         iface->transPtr = pmsg->buf;
 304         iface->writeNum = iface->readNum = pmsg->len;
 305         iface->result = 0;
 306         init_completion(&(iface->complete));
 307         /* Set Transmit device address */
 308         write_MASTER_ADDR(iface, pmsg->addr);
 309
 310         /* FIFO Initiation. Data in FIFO should be
 311          *  discarded before start a new operation.
 312          */
 313         write_FIFO_CTL(iface, 0x3);
 314         SSYNC();
 315         write_FIFO_CTL(iface, 0);
 316         SSYNC();
 317
 318         if (pmsg->flags & I2C_M_RD)
 319                 iface->read_write = I2C_SMBUS_READ;
 320         else {
 321                 iface->read_write = I2C_SMBUS_WRITE;
 322                 /* Transmit first data */
 323                 if (iface->writeNum > 0) {
 324                         write_XMT_DATA8(iface, *(iface->transPtr++));
 325                         iface->writeNum--;
 326                         SSYNC();
 327                 }
 328         }
 329
 330         /* clear int stat */
 331         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 332
 333         /* Interrupt mask . Enable XMT, RCV interrupt */
 334         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 335         SSYNC();
 336
 337         if (pmsg->len <= 255)
 338                 write_MASTER_CTL(iface, pmsg->len << 6);
 339         else {
 340                 write_MASTER_CTL(iface, 0xff << 6);
 341                 iface->manual_stop = 1;
 342         }
 343
 344         /* Master enable */
 345         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 346                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 347                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 348         SSYNC();
 349
 350         while (!iface->result) {
 351                 if (!wait_for_completion_timeout(&iface->complete,
 352                         adap->timeout)) {
 353                         iface->result = -1;
 354                         dev_err(&adap->dev, "master transfer timeout\n");
 355                 }
 356         }
 357
 358         if (iface->result == 1)
 359                 rc = iface->cur_msg + 1;
 360         else
 361                 rc = iface->result;
 362
 363         return rc;
 364 }
 365
 366 /*
 367  * Generic i2c master transfer entrypoint
 368  */
 369 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 370                                 struct i2c_msg *msgs, int num)
 371 {
 372         int i, ret = 0;
 373
 374         for (i = 0; i < adap->retries; i++) {
 375                 ret = bfin_twi_do_master_xfer(adap, msgs, num);
 376                 if (ret > 0)
 377                         break;
 378         }
 379
 380         return ret;
 381 }
 382
 383 /*
 384  * One I2C SMBus transfer
 385  */
 386 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 387                         unsigned short flags, char read_write,
 388                         u8 command, int size, union i2c_smbus_data *data)
 389 {
 390         struct bfin_twi_iface *iface = adap->algo_data;
 391         int rc = 0;
 392
 393         if (!(read_CONTROL(iface) & TWI_ENA))
 394                 return -ENXIO;
 395
 396         while (read_MASTER_STAT(iface) & BUSBUSY)
 397                 yield();
 398
 399         iface->writeNum = 0;
 400         iface->readNum = 0;
 401
 402         /* Prepare datas & select mode */
 403         switch (size) {
 404         case I2C_SMBUS_QUICK:
 405                 iface->transPtr = NULL;
 406                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 407                 break;
 408         case I2C_SMBUS_BYTE:
 409                 if (data == NULL)
 410                         iface->transPtr = NULL;
 411                 else {
 412                         if (read_write == I2C_SMBUS_READ)
 413                                 iface->readNum = 1;
 414                         else
 415                                 iface->writeNum = 1;
 416                         iface->transPtr = &data->byte;
 417                 }
 418                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 419                 break;
 420         case I2C_SMBUS_BYTE_DATA:
 421                 if (read_write == I2C_SMBUS_READ) {
 422                         iface->readNum = 1;
 423                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 424                 } else {
 425                         iface->writeNum = 1;
 426                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 427                 }
 428                 iface->transPtr = &data->byte;
 429                 break;
 430         case I2C_SMBUS_WORD_DATA:
 431                 if (read_write == I2C_SMBUS_READ) {
 432                         iface->readNum = 2;
 433                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 434                 } else {
 435                         iface->writeNum = 2;
 436                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 437                 }
 438                 iface->transPtr = (u8 *)&data->word;
 439                 break;
 440         case I2C_SMBUS_PROC_CALL:
 441                 iface->writeNum = 2;
 442                 iface->readNum = 2;
 443                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 444                 iface->transPtr = (u8 *)&data->word;
 445                 break;
 446         case I2C_SMBUS_BLOCK_DATA:
 447                 if (read_write == I2C_SMBUS_READ) {
 448                         iface->readNum = 0;
 449                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 450                 } else {
 451                         iface->writeNum = data->block[0] + 1;
 452                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 453                 }
 454                 iface->transPtr = data->block;
 455                 break;
 456         case I2C_SMBUS_I2C_BLOCK_DATA:
 457                 if (read_write == I2C_SMBUS_READ) {
 458                         iface->readNum = data->block[0];
 459                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 460                 } else {
 461                         iface->writeNum = data->block[0];
 462                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 463                 }
 464                 iface->transPtr = (u8 *)&data->block[1];
 465                 break;
 466         default:
 467                 return -1;
 468         }
 469
 470         iface->result = 0;
 471         iface->manual_stop = 0;
 472         iface->read_write = read_write;
 473         iface->command = command;
 474         init_completion(&(iface->complete));
 475
 476         /* FIFO Initiation. Data in FIFO should be discarded before
 477          * start a new operation.
 478          */
 479         write_FIFO_CTL(iface, 0x3);
 480         SSYNC();
 481         write_FIFO_CTL(iface, 0);
 482
 483         /* clear int stat */
 484         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 485
 486         /* Set Transmit device address */
 487         write_MASTER_ADDR(iface, addr);
 488         SSYNC();
 489
 490         switch (iface->cur_mode) {
 491         case TWI_I2C_MODE_STANDARDSUB:
 492                 write_XMT_DATA8(iface, iface->command);
 493                 write_INT_MASK(iface, MCOMP | MERR |
 494                         ((iface->read_write == I2C_SMBUS_READ) ?
 495                         RCVSERV : XMTSERV));
 496                 SSYNC();
 497
 498                 if (iface->writeNum + 1 <= 255)
 499                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 500                 else {
 501                         write_MASTER_CTL(iface, 0xff << 6);
 502                         iface->manual_stop = 1;
 503                 }
 504                 /* Master enable */
 505                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 506                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 507                 break;
 508         case TWI_I2C_MODE_COMBINED:
 509                 write_XMT_DATA8(iface, iface->command);
 510                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 511                 SSYNC();
 512
 513                 if (iface->writeNum > 0)
 514                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 515                 else
 516                         write_MASTER_CTL(iface, 0x1 << 6);
 517                 /* Master enable */
 518                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 519                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 520                 break;
 521         default:
 522                 write_MASTER_CTL(iface, 0);
 523                 if (size != I2C_SMBUS_QUICK) {
 524                         /* Don't access xmit data register when this is a
 525                          * read operation.
 526                          */
 527                         if (iface->read_write != I2C_SMBUS_READ) {
 528                                 if (iface->writeNum > 0) {
 529                                         write_XMT_DATA8(iface,
 530                                                 *(iface->transPtr++));
 531                                         if (iface->writeNum <= 255)
 532                                                 write_MASTER_CTL(iface,
 533                                                         iface->writeNum << 6);
 534                                         else {
 535                                                 write_MASTER_CTL(iface,
 536                                                         0xff << 6);
 537                                                 iface->manual_stop = 1;
 538                                         }
 539                                         iface->writeNum--;
 540                                 } else {
 541                                         write_XMT_DATA8(iface, iface->command);
 542                                         write_MASTER_CTL(iface, 1 << 6);
 543                                 }
 544                         } else {
 545                                 if (iface->readNum > 0 && iface->readNum <= 255)
 546                                         write_MASTER_CTL(iface,
 547                                                 iface->readNum << 6);
 548                                 else if (iface->readNum > 255) {
 549                                         write_MASTER_CTL(iface, 0xff << 6);
 550                                         iface->manual_stop = 1;
 551                                 } else
 552                                         break;
 553                         }
 554                 }
 555                 write_INT_MASK(iface, MCOMP | MERR |
 556                         ((iface->read_write == I2C_SMBUS_READ) ?
 557                         RCVSERV : XMTSERV));
 558                 SSYNC();
 559
 560                 /* Master enable */
 561                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 562                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 563                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 564                 break;
 565         }
 566         SSYNC();
 567
 568         while (!iface->result) {
 569                 if (!wait_for_completion_timeout(&iface->complete,
 570                         adap->timeout)) {
 571                         iface->result = -1;
 572                         dev_err(&adap->dev, "smbus transfer timeout\n");
 573                 }
 574         }
 575
 576         rc = (iface->result >= 0) ? 0 : -1;
 577
 578         return rc;
 579 }
 580
 581 /*
 582  * Generic I2C SMBus transfer entrypoint
 583  */
 584 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 585                         unsigned short flags, char read_write,
 586                         u8 command, int size, union i2c_smbus_data *data)
 587 {
 588         int i, ret = 0;
 589
 590         for (i = 0; i < adap->retries; i++) {
 591                 ret = bfin_twi_do_smbus_xfer(adap, addr, flags,
 592                         read_write, command, size, data);
 593                 if (ret == 0)
 594                         break;
 595         }
 596
 597         return ret;
 598 }
 599
 600 /*
 601  * Return what the adapter supports
 602  */
 603 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 604 {
 605         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 606                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 607                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 608                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 609 }
 610
 611 static struct i2c_algorithm bfin_twi_algorithm = {
 612         .master_xfer   = bfin_twi_master_xfer,
 613         .smbus_xfer    = bfin_twi_smbus_xfer,
 614         .functionality = bfin_twi_functionality,
 615 };
 616
 617 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
 618 {
 619         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 620
 621         iface->saved_clkdiv = read_CLKDIV(iface);
 622         iface->saved_control = read_CONTROL(iface);
 623
 624         free_irq(iface->irq, iface);
 625
 626         /* Disable TWI */
 627         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 628
 629         return 0;
 630 }
 631
 632 static int i2c_bfin_twi_resume(struct platform_device *pdev)
 633 {
 634         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 635
 636         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 637                 IRQF_DISABLED, pdev->name, iface);
 638         if (rc) {
 639                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 640                 return -ENODEV;
 641         }
 642
 643         /* Resume TWI interface clock as specified */
 644         write_CLKDIV(iface, iface->saved_clkdiv);
 645
 646         /* Resume TWI */
 647         write_CONTROL(iface, iface->saved_control);
 648
 649         return 0;
 650 }
 651
 652 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 653 {
 654         struct bfin_twi_iface *iface;
 655         struct i2c_adapter *p_adap;
 656         struct resource *res;
 657         int rc;
 658         unsigned int clkhilow;
 659
 660         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 661         if (!iface) {
 662                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 663                 rc = -ENOMEM;
 664                 goto out_error_nomem;
 665         }
 666
 667         spin_lock_init(&(iface->lock));
 668
 669         /* Find and map our resources */
 670         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 671         if (res == NULL) {
 672                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 673                 rc = -ENOENT;
 674                 goto out_error_get_res;
 675         }
 676
 677         iface->regs_base = ioremap(res->start, resource_size(res));
 678         if (iface->regs_base == NULL) {
 679                 dev_err(&pdev->dev, "Cannot map IO\n");
 680                 rc = -ENXIO;
 681                 goto out_error_ioremap;
 682         }
 683
 684         iface->irq = platform_get_irq(pdev, 0);
 685         if (iface->irq < 0) {
 686                 dev_err(&pdev->dev, "No IRQ specified\n");
 687                 rc = -ENOENT;
 688                 goto out_error_no_irq;
 689         }
 690
 691         p_adap = &iface->adap;
 692         p_adap->nr = pdev->id;
 693         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 694         p_adap->algo = &bfin_twi_algorithm;
 695         p_adap->algo_data = iface;
 696         p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 697         p_adap->dev.parent = &pdev->dev;
 698         p_adap->timeout = 5 * HZ;
 699         p_adap->retries = 3;
 700
 701         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
 702         if (rc) {
 703                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 704                 goto out_error_pin_mux;
 705         }
 706
 707         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 708                 IRQF_DISABLED, pdev->name, iface);
 709         if (rc) {
 710                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 711                 rc = -ENODEV;
 712                 goto out_error_req_irq;
 713         }
 714
 715         /* Set TWI internal clock as 10MHz */
 716         write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
 717
 718         /*
 719          * We will not end up with a CLKDIV=0 because no one will specify
 720          * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 721          */
 722         clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
 723
 724         /* Set Twi interface clock as specified */
 725         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 726
 727         /* Enable TWI */
 728         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 729         SSYNC();
 730
 731         rc = i2c_add_numbered_adapter(p_adap);
 732         if (rc < 0) {
 733                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 734                 goto out_error_add_adapter;
 735         }
 736
 737         platform_set_drvdata(pdev, iface);
 738
 739         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
 740                 "regs_base@%p\n", iface->regs_base);
 741
 742         return 0;
 743
 744 out_error_add_adapter:
 745         free_irq(iface->irq, iface);
 746 out_error_req_irq:
 747 out_error_no_irq:
 748         peripheral_free_list(pin_req[pdev->id]);
 749 out_error_pin_mux:
 750         iounmap(iface->regs_base);
 751 out_error_ioremap:
 752 out_error_get_res:
 753         kfree(iface);
 754 out_error_nomem:
 755         return rc;
 756 }
 757
 758 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 759 {
 760         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 761
 762         platform_set_drvdata(pdev, NULL);
 763
 764         i2c_del_adapter(&(iface->adap));
 765         free_irq(iface->irq, iface);
 766         peripheral_free_list(pin_req[pdev->id]);
 767         iounmap(iface->regs_base);
 768         kfree(iface);
 769
 770         return 0;
 771 }
 772
 773 static struct platform_driver i2c_bfin_twi_driver = {
 774         .probe          = i2c_bfin_twi_probe,
 775         .remove         = i2c_bfin_twi_remove,
 776         .suspend        = i2c_bfin_twi_suspend,
 777         .resume         = i2c_bfin_twi_resume,
 778         .driver         = {
 779                 .name   = "i2c-bfin-twi",
 780                 .owner  = THIS_MODULE,
 781         },
 782 };
 783
 784 static int __init i2c_bfin_twi_init(void)
 785 {
 786         return platform_driver_register(&i2c_bfin_twi_driver);
 787 }
 788
 789 static void __exit i2c_bfin_twi_exit(void)
 790 {
 791         platform_driver_unregister(&i2c_bfin_twi_driver);
 792 }
 793
 794 module_init(i2c_bfin_twi_init);
 795 module_exit(i2c_bfin_twi_exit);
 796
 797 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 798 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
 799 MODULE_LICENSE("GPL");
 800 MODULE_ALIAS("platform:i2c-bfin-twi");