drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26
  27 #define RADEON_IDLE_LOOP_MS 100
  28 #define RADEON_RECLOCK_DELAY_MS 200
  29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  30 #define RADEON_WAIT_IDLE_TIMEOUT 200
  31
  32 static void radeon_pm_idle_work_handler(struct work_struct *work);
  33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  34
  35 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
  36 {
  37         struct radeon_bo *bo, *n;
  38
  39         if (list_empty(&rdev->gem.objects))
  40                 return;
  41
  42         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  43                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
  44                         ttm_bo_unmap_virtual(&bo->tbo);
  45         }
  46
  47         if (rdev->gart.table.vram.robj)
  48                 ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
  49
  50         if (rdev->stollen_vga_memory)
  51                 ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
  52
  53         if (rdev->r600_blit.shader_obj)
  54                 ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
  55 }
  56
  57 static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
  58 {
  59         int i;
  60
  61         if (!static_switch)
  62                 radeon_get_power_state(rdev, rdev->pm.planned_action);
  63
  64         mutex_lock(&rdev->cp.mutex);
  65
  66         /* wait for GPU idle */
  67         rdev->pm.gui_idle = false;
  68         rdev->irq.gui_idle = true;
  69         radeon_irq_set(rdev);
  70         wait_event_interruptible_timeout(
  71                 rdev->irq.idle_queue, rdev->pm.gui_idle,
  72                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
  73         rdev->irq.gui_idle = false;
  74         radeon_irq_set(rdev);
  75
  76         mutex_lock(&rdev->vram_mutex);
  77
  78         radeon_unmap_vram_bos(rdev);
  79
  80         if (!static_switch) {
  81                 for (i = 0; i < rdev->num_crtc; i++) {
  82                         if (rdev->pm.active_crtcs & (1 << i)) {
  83                                 rdev->pm.req_vblank |= (1 << i);
  84                                 drm_vblank_get(rdev->ddev, i);
  85                         }
  86                 }
  87         }
  88
  89         radeon_set_power_state(rdev, static_switch);
  90
  91         if (!static_switch) {
  92                 for (i = 0; i < rdev->num_crtc; i++) {
  93                         if (rdev->pm.req_vblank & (1 << i)) {
  94                                 rdev->pm.req_vblank &= ~(1 << i);
  95                                 drm_vblank_put(rdev->ddev, i);
  96                         }
  97                 }
  98         }
  99
 100         mutex_unlock(&rdev->vram_mutex);
 101
 102         /* update display watermarks based on new power state */
 103         radeon_update_bandwidth_info(rdev);
 104         if (rdev->pm.active_crtc_count)
 105                 radeon_bandwidth_update(rdev);
 106
 107         rdev->pm.planned_action = PM_ACTION_NONE;
 108
 109         mutex_unlock(&rdev->cp.mutex);
 110 }
 111
 112 static ssize_t radeon_get_power_state_static(struct device *dev,
 113                                              struct device_attribute *attr,
 114                                              char *buf)
 115 {
 116         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 117         struct radeon_device *rdev = ddev->dev_private;
 118
 119         return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
 120                         rdev->pm.current_clock_mode_index);
 121 }
 122
 123 static ssize_t radeon_set_power_state_static(struct device *dev,
 124                                              struct device_attribute *attr,
 125                                              const char *buf,
 126                                              size_t count)
 127 {
 128         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 129         struct radeon_device *rdev = ddev->dev_private;
 130         int ps, cm;
 131
 132         if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
 133                 DRM_ERROR("Invalid power state!\n");
 134                 return count;
 135         }
 136
 137         mutex_lock(&rdev->ddev->struct_mutex);
 138         mutex_lock(&rdev->pm.mutex);
 139         if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
 140             (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
 141                 if ((rdev->pm.active_crtc_count > 1) &&
 142                     (rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
 143                         DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
 144                 } else {
 145                         /* disable dynpm */
 146                         rdev->pm.state = PM_STATE_DISABLED;
 147                         rdev->pm.planned_action = PM_ACTION_NONE;
 148                         rdev->pm.requested_power_state_index = ps;
 149                         rdev->pm.requested_clock_mode_index = cm;
 150                         radeon_pm_set_clocks(rdev, true);
 151                 }
 152         } else
 153                 DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
 154         mutex_unlock(&rdev->pm.mutex);
 155         mutex_unlock(&rdev->ddev->struct_mutex);
 156
 157         return count;
 158 }
 159
 160 static ssize_t radeon_get_dynpm(struct device *dev,
 161                                 struct device_attribute *attr,
 162                                 char *buf)
 163 {
 164         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 165         struct radeon_device *rdev = ddev->dev_private;
 166
 167         return snprintf(buf, PAGE_SIZE, "%s\n",
 168                         (rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
 169 }
 170
 171 static ssize_t radeon_set_dynpm(struct device *dev,
 172                                 struct device_attribute *attr,
 173                                 const char *buf,
 174                                 size_t count)
 175 {
 176         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 177         struct radeon_device *rdev = ddev->dev_private;
 178         int tmp = simple_strtoul(buf, NULL, 10);
 179
 180         if (tmp == 0) {
 181                 /* update power mode info */
 182                 radeon_pm_compute_clocks(rdev);
 183                 /* disable dynpm */
 184                 mutex_lock(&rdev->pm.mutex);
 185                 rdev->pm.state = PM_STATE_DISABLED;
 186                 rdev->pm.planned_action = PM_ACTION_NONE;
 187                 mutex_unlock(&rdev->pm.mutex);
 188                 DRM_INFO("radeon: dynamic power management disabled\n");
 189         } else if (tmp == 1) {
 190                 if (rdev->pm.num_power_states > 1) {
 191                         /* enable dynpm */
 192                         mutex_lock(&rdev->ddev->struct_mutex);
 193                         mutex_lock(&rdev->pm.mutex);
 194                         rdev->pm.state = PM_STATE_PAUSED;
 195                         rdev->pm.planned_action = PM_ACTION_DEFAULT;
 196                         radeon_get_power_state(rdev, rdev->pm.planned_action);
 197                         mutex_unlock(&rdev->pm.mutex);
 198                         mutex_unlock(&rdev->ddev->struct_mutex);
 199                         /* update power mode info */
 200                         radeon_pm_compute_clocks(rdev);
 201                         DRM_INFO("radeon: dynamic power management enabled\n");
 202                 } else
 203                         DRM_ERROR("dynpm not valid on this system\n");
 204         } else
 205                 DRM_ERROR("Invalid setting: %d\n", tmp);
 206
 207         return count;
 208 }
 209
 210 static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
 211 static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
 212
 213
 214 static const char *pm_state_names[4] = {
 215         "PM_STATE_DISABLED",
 216         "PM_STATE_MINIMUM",
 217         "PM_STATE_PAUSED",
 218         "PM_STATE_ACTIVE"
 219 };
 220
 221 static const char *pm_state_types[5] = {
 222         "",
 223         "Powersave",
 224         "Battery",
 225         "Balanced",
 226         "Performance",
 227 };
 228
 229 static void radeon_print_power_mode_info(struct radeon_device *rdev)
 230 {
 231         int i, j;
 232         bool is_default;
 233
 234         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
 235         for (i = 0; i < rdev->pm.num_power_states; i++) {
 236                 if (rdev->pm.default_power_state_index == i)
 237                         is_default = true;
 238                 else
 239                         is_default = false;
 240                 DRM_INFO("State %d %s %s\n", i,
 241                          pm_state_types[rdev->pm.power_state[i].type],
 242                          is_default ? "(default)" : "");
 243                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 244                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
 245                 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 246                         DRM_INFO("\tSingle display only\n");
 247                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
 248                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
 249                         if (rdev->flags & RADEON_IS_IGP)
 250                                 DRM_INFO("\t\t%d engine: %d\n",
 251                                          j,
 252                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
 253                         else
 254                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
 255                                          j,
 256                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
 257                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
 258                 }
 259         }
 260 }
 261
 262 void radeon_sync_with_vblank(struct radeon_device *rdev)
 263 {
 264         if (rdev->pm.active_crtcs) {
 265                 rdev->pm.vblank_sync = false;
 266                 wait_event_timeout(
 267                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 268                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 269         }
 270 }
 271
 272 int radeon_pm_init(struct radeon_device *rdev)
 273 {
 274         rdev->pm.state = PM_STATE_DISABLED;
 275         rdev->pm.planned_action = PM_ACTION_NONE;
 276         rdev->pm.can_upclock = true;
 277         rdev->pm.can_downclock = true;
 278
 279         if (rdev->bios) {
 280                 if (rdev->is_atom_bios)
 281                         radeon_atombios_get_power_modes(rdev);
 282                 else
 283                         radeon_combios_get_power_modes(rdev);
 284                 radeon_print_power_mode_info(rdev);
 285         }
 286
 287         if (radeon_debugfs_pm_init(rdev)) {
 288                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 289         }
 290
 291         /* where's the best place to put this? */
 292         device_create_file(rdev->dev, &dev_attr_power_state);
 293         device_create_file(rdev->dev, &dev_attr_dynpm);
 294
 295         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 296
 297         if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
 298                 rdev->pm.state = PM_STATE_PAUSED;
 299                 DRM_INFO("radeon: dynamic power management enabled\n");
 300         }
 301
 302         DRM_INFO("radeon: power management initialized\n");
 303
 304         return 0;
 305 }
 306
 307 void radeon_pm_fini(struct radeon_device *rdev)
 308 {
 309         if (rdev->pm.state != PM_STATE_DISABLED) {
 310                 /* cancel work */
 311                 cancel_delayed_work_sync(&rdev->pm.idle_work);
 312                 /* reset default clocks */
 313                 rdev->pm.state = PM_STATE_DISABLED;
 314                 rdev->pm.planned_action = PM_ACTION_DEFAULT;
 315                 radeon_pm_set_clocks(rdev, false);
 316         } else if ((rdev->pm.current_power_state_index !=
 317                     rdev->pm.default_power_state_index) ||
 318                    (rdev->pm.current_clock_mode_index != 0)) {
 319                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 320                 rdev->pm.requested_clock_mode_index = 0;
 321                 mutex_lock(&rdev->ddev->struct_mutex);
 322                 mutex_lock(&rdev->pm.mutex);
 323                 radeon_pm_set_clocks(rdev, true);
 324                 mutex_unlock(&rdev->pm.mutex);
 325                 mutex_unlock(&rdev->ddev->struct_mutex);
 326         }
 327
 328         device_remove_file(rdev->dev, &dev_attr_power_state);
 329         device_remove_file(rdev->dev, &dev_attr_dynpm);
 330
 331         if (rdev->pm.i2c_bus)
 332                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 333 }
 334
 335 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 336 {
 337         struct drm_device *ddev = rdev->ddev;
 338         struct drm_crtc *crtc;
 339         struct radeon_crtc *radeon_crtc;
 340
 341         if (rdev->pm.state == PM_STATE_DISABLED)
 342                 return;
 343
 344         mutex_lock(&rdev->ddev->struct_mutex);
 345         mutex_lock(&rdev->pm.mutex);
 346
 347         rdev->pm.active_crtcs = 0;
 348         rdev->pm.active_crtc_count = 0;
 349         list_for_each_entry(crtc,
 350                 &ddev->mode_config.crtc_list, head) {
 351                 radeon_crtc = to_radeon_crtc(crtc);
 352                 if (radeon_crtc->enabled) {
 353                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 354                         rdev->pm.active_crtc_count++;
 355                 }
 356         }
 357
 358         if (rdev->pm.active_crtc_count > 1) {
 359                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 360                         cancel_delayed_work(&rdev->pm.idle_work);
 361
 362                         rdev->pm.state = PM_STATE_PAUSED;
 363                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 364                         radeon_pm_set_clocks(rdev, false);
 365
 366                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 367                 }
 368         } else if (rdev->pm.active_crtc_count == 1) {
 369                 /* TODO: Increase clocks if needed for current mode */
 370
 371                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 372                         rdev->pm.state = PM_STATE_ACTIVE;
 373                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 374                         radeon_pm_set_clocks(rdev, false);
 375
 376                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 377                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 378                 } else if (rdev->pm.state == PM_STATE_PAUSED) {
 379                         rdev->pm.state = PM_STATE_ACTIVE;
 380                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 381                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 382                         DRM_DEBUG("radeon: dynamic power management activated\n");
 383                 }
 384         } else { /* count == 0 */
 385                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 386                         cancel_delayed_work(&rdev->pm.idle_work);
 387
 388                         rdev->pm.state = PM_STATE_MINIMUM;
 389                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 390                         radeon_pm_set_clocks(rdev, false);
 391                 }
 392         }
 393
 394         mutex_unlock(&rdev->pm.mutex);
 395         mutex_unlock(&rdev->ddev->struct_mutex);
 396 }
 397
 398 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 399 {
 400         u32 stat_crtc = 0;
 401         bool in_vbl = true;
 402
 403         if (ASIC_IS_DCE4(rdev)) {
 404                 if (rdev->pm.active_crtcs & (1 << 0)) {
 405                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
 406                         if (!(stat_crtc & 1))
 407                                 in_vbl = false;
 408                 }
 409                 if (rdev->pm.active_crtcs & (1 << 1)) {
 410                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
 411                         if (!(stat_crtc & 1))
 412                                 in_vbl = false;
 413                 }
 414                 if (rdev->pm.active_crtcs & (1 << 2)) {
 415                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
 416                         if (!(stat_crtc & 1))
 417                                 in_vbl = false;
 418                 }
 419                 if (rdev->pm.active_crtcs & (1 << 3)) {
 420                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
 421                         if (!(stat_crtc & 1))
 422                                 in_vbl = false;
 423                 }
 424                 if (rdev->pm.active_crtcs & (1 << 4)) {
 425                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
 426                         if (!(stat_crtc & 1))
 427                                 in_vbl = false;
 428                 }
 429                 if (rdev->pm.active_crtcs & (1 << 5)) {
 430                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
 431                         if (!(stat_crtc & 1))
 432                                 in_vbl = false;
 433                 }
 434         } else if (ASIC_IS_AVIVO(rdev)) {
 435                 if (rdev->pm.active_crtcs & (1 << 0)) {
 436                         stat_crtc = RREG32(D1CRTC_STATUS);
 437                         if (!(stat_crtc & 1))
 438                                 in_vbl = false;
 439                 }
 440                 if (rdev->pm.active_crtcs & (1 << 1)) {
 441                         stat_crtc = RREG32(D2CRTC_STATUS);
 442                         if (!(stat_crtc & 1))
 443                                 in_vbl = false;
 444                 }
 445         } else {
 446                 if (rdev->pm.active_crtcs & (1 << 0)) {
 447                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 448                         if (!(stat_crtc & 1))
 449                                 in_vbl = false;
 450                 }
 451                 if (rdev->pm.active_crtcs & (1 << 1)) {
 452                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 453                         if (!(stat_crtc & 1))
 454                                 in_vbl = false;
 455                 }
 456         }
 457         if (in_vbl == false)
 458                 DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
 459                          finish ? "exit" : "entry");
 460         return in_vbl;
 461 }
 462
 463 static void radeon_pm_idle_work_handler(struct work_struct *work)
 464 {
 465         struct radeon_device *rdev;
 466         int resched;
 467         rdev = container_of(work, struct radeon_device,
 468                                 pm.idle_work.work);
 469
 470         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 471         mutex_lock(&rdev->ddev->struct_mutex);
 472         mutex_lock(&rdev->pm.mutex);
 473         if (rdev->pm.state == PM_STATE_ACTIVE) {
 474                 unsigned long irq_flags;
 475                 int not_processed = 0;
 476
 477                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 478                 if (!list_empty(&rdev->fence_drv.emited)) {
 479                         struct list_head *ptr;
 480                         list_for_each(ptr, &rdev->fence_drv.emited) {
 481                                 /* count up to 3, that's enought info */
 482                                 if (++not_processed >= 3)
 483                                         break;
 484                         }
 485                 }
 486                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 487
 488                 if (not_processed >= 3) { /* should upclock */
 489                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 490                                 rdev->pm.planned_action = PM_ACTION_NONE;
 491                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 492                                    rdev->pm.can_upclock) {
 493                                 rdev->pm.planned_action =
 494                                         PM_ACTION_UPCLOCK;
 495                                 rdev->pm.action_timeout = jiffies +
 496                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 497                         }
 498                 } else if (not_processed == 0) { /* should downclock */
 499                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 500                                 rdev->pm.planned_action = PM_ACTION_NONE;
 501                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 502                                    rdev->pm.can_downclock) {
 503                                 rdev->pm.planned_action =
 504                                         PM_ACTION_DOWNCLOCK;
 505                                 rdev->pm.action_timeout = jiffies +
 506                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 507                         }
 508                 }
 509
 510                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 511                     jiffies > rdev->pm.action_timeout) {
 512                         radeon_pm_set_clocks(rdev, false);
 513                 }
 514         }
 515         mutex_unlock(&rdev->pm.mutex);
 516         mutex_unlock(&rdev->ddev->struct_mutex);
 517         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 518
 519         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 520                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 521 }
 522
 523 /*
 524  * Debugfs info
 525  */
 526 #if defined(CONFIG_DEBUG_FS)
 527
 528 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 529 {
 530         struct drm_info_node *node = (struct drm_info_node *) m->private;
 531         struct drm_device *dev = node->minor->dev;
 532         struct radeon_device *rdev = dev->dev_private;
 533
 534         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 535         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 536         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 537         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 538         if (rdev->asic->get_memory_clock)
 539                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 540         if (rdev->asic->get_pcie_lanes)
 541                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 542
 543         return 0;
 544 }
 545
 546 static struct drm_info_list radeon_pm_info_list[] = {
 547         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 548 };
 549 #endif
 550
 551 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 552 {
 553 #if defined(CONFIG_DEBUG_FS)
 554         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 555 #else
 556         return 0;
 557 #endif
 558 }