drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_fixed.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  34                                        struct drm_display_mode *mode,
  35                                        struct drm_display_mode *adjusted_mode)
  36 {
  37         struct drm_device *dev = crtc->dev;
  38         struct radeon_device *rdev = dev->dev_private;
  39         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  40         int xres = mode->hdisplay;
  41         int yres = mode->vdisplay;
  42         bool hscale = true, vscale = true;
  43         int hsync_wid;
  44         int vsync_wid;
  45         int hsync_start;
  46         int blank_width;
  47         u32 scale, inc, crtc_more_cntl;
  48         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  49         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  50         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  51         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  52
  53         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  54                 (RADEON_VERT_STRETCH_RESERVED |
  55                  RADEON_VERT_AUTO_RATIO_INC);
  56         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  57                 (RADEON_HORZ_FP_LOOP_STRETCH |
  58                  RADEON_HORZ_AUTO_RATIO_INC);
  59
  60         crtc_more_cntl = 0;
  61         if ((rdev->family == CHIP_RS100) ||
  62             (rdev->family == CHIP_RS200)) {
  63                 /* This is to workaround the asic bug for RMX, some versions
  64                    of BIOS dosen't have this register initialized correctly. */
  65                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  66         }
  67
  68
  69         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  70                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  71
  72         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  73         if (!hsync_wid)
  74                 hsync_wid = 1;
  75         hsync_start = mode->crtc_hsync_start - 8;
  76
  77         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  78                               | ((hsync_wid & 0x3f) << 16)
  79                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  80                                  ? RADEON_CRTC_H_SYNC_POL
  81                                  : 0));
  82
  83         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  84                                 | ((mode->crtc_vdisplay - 1) << 16));
  85
  86         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  87         if (!vsync_wid)
  88                 vsync_wid = 1;
  89
  90         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
  91                               | ((vsync_wid & 0x1f) << 16)
  92                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
  93                                  ? RADEON_CRTC_V_SYNC_POL
  94                                  : 0));
  95
  96         fp_horz_vert_active = 0;
  97
  98         if (native_mode->hdisplay == 0 ||
  99             native_mode->vdisplay == 0) {
 100                 hscale = false;
 101                 vscale = false;
 102         } else {
 103                 if (xres > native_mode->hdisplay)
 104                         xres = native_mode->hdisplay;
 105                 if (yres > native_mode->vdisplay)
 106                         yres = native_mode->vdisplay;
 107
 108                 if (xres == native_mode->hdisplay)
 109                         hscale = false;
 110                 if (yres == native_mode->vdisplay)
 111                         vscale = false;
 112         }
 113
 114         switch (radeon_crtc->rmx_type) {
 115         case RMX_FULL:
 116         case RMX_ASPECT:
 117                 if (!hscale)
 118                         fp_horz_stretch |= ((xres/8-1) << 16);
 119                 else {
 120                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 121                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 122                                 / native_mode->hdisplay + 1;
 123                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 124                                         RADEON_HORZ_STRETCH_BLEND |
 125                                         RADEON_HORZ_STRETCH_ENABLE |
 126                                         ((native_mode->hdisplay/8-1) << 16));
 127                 }
 128
 129                 if (!vscale)
 130                         fp_vert_stretch |= ((yres-1) << 12);
 131                 else {
 132                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 133                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 134                                 / native_mode->vdisplay + 1;
 135                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 136                                         RADEON_VERT_STRETCH_ENABLE |
 137                                         RADEON_VERT_STRETCH_BLEND |
 138                                         ((native_mode->vdisplay-1) << 12));
 139                 }
 140                 break;
 141         case RMX_CENTER:
 142                 fp_horz_stretch |= ((xres/8-1) << 16);
 143                 fp_vert_stretch |= ((yres-1) << 12);
 144
 145                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 146                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 147
 148                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 149                 if (blank_width > 110)
 150                         blank_width = 110;
 151
 152                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 153                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 154
 155                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 156                 if (!hsync_wid)
 157                         hsync_wid = 1;
 158
 159                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 160                                 | ((hsync_wid & 0x3f) << 16)
 161                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 162                                         ? RADEON_CRTC_H_SYNC_POL
 163                                         : 0));
 164
 165                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 166                                 | ((mode->crtc_vdisplay - 1) << 16));
 167
 168                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 169                 if (!vsync_wid)
 170                         vsync_wid = 1;
 171
 172                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 173                                         | ((vsync_wid & 0x1f) << 16)
 174                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 175                                                 ? RADEON_CRTC_V_SYNC_POL
 176                                                 : 0)));
 177
 178                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 179                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 180                 break;
 181         case RMX_OFF:
 182         default:
 183                 fp_horz_stretch |= ((xres/8-1) << 16);
 184                 fp_vert_stretch |= ((yres-1) << 12);
 185                 break;
 186         }
 187
 188         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 189         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 190         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 191         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 192         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 193         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 194         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 195         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 196 }
 197
 198 void radeon_restore_common_regs(struct drm_device *dev)
 199 {
 200         /* don't need this yet */
 201 }
 202
 203 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 204 {
 205         struct radeon_device *rdev = dev->dev_private;
 206         int i = 0;
 207
 208         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 209            the cause yet, but this workaround will mask the problem for now.
 210            Other chips usually will pass at the very first test, so the
 211            workaround shouldn't have any effect on them. */
 212         for (i = 0;
 213              (i < 10000 &&
 214               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 215              i++);
 216 }
 217
 218 static void radeon_pll_write_update(struct drm_device *dev)
 219 {
 220         struct radeon_device *rdev = dev->dev_private;
 221
 222         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 223
 224         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 225                            RADEON_PPLL_ATOMIC_UPDATE_W,
 226                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 227 }
 228
 229 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 230 {
 231         struct radeon_device *rdev = dev->dev_private;
 232         int i = 0;
 233
 234
 235         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 236            the cause yet, but this workaround will mask the problem for now.
 237            Other chips usually will pass at the very first test, so the
 238            workaround shouldn't have any effect on them. */
 239         for (i = 0;
 240              (i < 10000 &&
 241               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 242              i++);
 243 }
 244
 245 static void radeon_pll2_write_update(struct drm_device *dev)
 246 {
 247         struct radeon_device *rdev = dev->dev_private;
 248
 249         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 250
 251         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 252                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 253                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 254 }
 255
 256 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 257                                        uint16_t fb_div)
 258 {
 259         unsigned int vcoFreq;
 260
 261         if (!ref_div)
 262                 return 1;
 263
 264         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
 265
 266         /*
 267          * This is horribly crude: the VCO frequency range is divided into
 268          * 3 parts, each part having a fixed PLL gain value.
 269          */
 270         if (vcoFreq >= 30000)
 271                 /*
 272                  * [300..max] MHz : 7
 273                  */
 274                 return 7;
 275         else if (vcoFreq >= 18000)
 276                 /*
 277                  * [180..300) MHz : 4
 278                  */
 279                 return 4;
 280         else
 281                 /*
 282                  * [0..180) MHz : 1
 283                  */
 284                 return 1;
 285 }
 286
 287 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 288 {
 289         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 290         struct drm_device *dev = crtc->dev;
 291         struct radeon_device *rdev = dev->dev_private;
 292         uint32_t mask;
 293
 294         if (radeon_crtc->crtc_id)
 295                 mask = (RADEON_CRTC2_EN |
 296                         RADEON_CRTC2_DISP_DIS |
 297                         RADEON_CRTC2_VSYNC_DIS |
 298                         RADEON_CRTC2_HSYNC_DIS |
 299                         RADEON_CRTC2_DISP_REQ_EN_B);
 300         else
 301                 mask = (RADEON_CRTC_DISPLAY_DIS |
 302                         RADEON_CRTC_VSYNC_DIS |
 303                         RADEON_CRTC_HSYNC_DIS);
 304
 305         switch (mode) {
 306         case DRM_MODE_DPMS_ON:
 307                 if (radeon_crtc->crtc_id)
 308                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
 309                 else {
 310                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 311                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 312                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 313                 }
 314                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 315                 radeon_crtc_load_lut(crtc);
 316                 break;
 317         case DRM_MODE_DPMS_STANDBY:
 318         case DRM_MODE_DPMS_SUSPEND:
 319         case DRM_MODE_DPMS_OFF:
 320                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 321                 if (radeon_crtc->crtc_id)
 322                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
 323                 else {
 324                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 325                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 326                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 327                 }
 328                 break;
 329         }
 330 }
 331
 332 /* properly set crtc bpp when using atombios */
 333 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
 334 {
 335         struct drm_device *dev = crtc->dev;
 336         struct radeon_device *rdev = dev->dev_private;
 337         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 338         int format;
 339         uint32_t crtc_gen_cntl;
 340         uint32_t disp_merge_cntl;
 341         uint32_t crtc_pitch;
 342
 343         switch (crtc->fb->bits_per_pixel) {
 344         case 8:
 345                 format = 2;
 346                 break;
 347         case 15:      /*  555 */
 348                 format = 3;
 349                 break;
 350         case 16:      /*  565 */
 351                 format = 4;
 352                 break;
 353         case 24:      /*  RGB */
 354                 format = 5;
 355                 break;
 356         case 32:      /* xRGB */
 357                 format = 6;
 358                 break;
 359         default:
 360                 return;
 361         }
 362
 363         crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 364                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 365                        (crtc->fb->bits_per_pixel * 8));
 366         crtc_pitch |= crtc_pitch << 16;
 367
 368         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 369
 370         switch (radeon_crtc->crtc_id) {
 371         case 0:
 372                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 373                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 374                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 375
 376                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
 377                 crtc_gen_cntl |= (format << 8);
 378                 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
 379                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 380                 break;
 381         case 1:
 382                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 383                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 384                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
 385
 386                 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
 387                 crtc_gen_cntl |= (format << 8);
 388                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
 389                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
 390                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
 391                 break;
 392         }
 393 }
 394
 395 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 396                          struct drm_framebuffer *old_fb)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         struct radeon_device *rdev = dev->dev_private;
 400         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 401         struct radeon_framebuffer *radeon_fb;
 402         struct drm_gem_object *obj;
 403         struct radeon_bo *rbo;
 404         uint64_t base;
 405         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 406         uint32_t crtc_pitch, pitch_pixels;
 407         uint32_t tiling_flags;
 408         int format;
 409         uint32_t gen_cntl_reg, gen_cntl_val;
 410         int r;
 411
 412         DRM_DEBUG("\n");
 413         /* no fb bound */
 414         if (!crtc->fb) {
 415                 DRM_DEBUG("No FB bound\n");
 416                 return 0;
 417         }
 418
 419         radeon_fb = to_radeon_framebuffer(crtc->fb);
 420
 421         switch (crtc->fb->bits_per_pixel) {
 422         case 8:
 423                 format = 2;
 424                 break;
 425         case 15:      /*  555 */
 426                 format = 3;
 427                 break;
 428         case 16:      /*  565 */
 429                 format = 4;
 430                 break;
 431         case 24:      /*  RGB */
 432                 format = 5;
 433                 break;
 434         case 32:      /* xRGB */
 435                 format = 6;
 436                 break;
 437         default:
 438                 return false;
 439         }
 440
 441         /* Pin framebuffer & get tilling informations */
 442         obj = radeon_fb->obj;
 443         rbo = obj->driver_private;
 444         r = radeon_bo_reserve(rbo, false);
 445         if (unlikely(r != 0))
 446                 return r;
 447         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 448         if (unlikely(r != 0)) {
 449                 radeon_bo_unreserve(rbo);
 450                 return -EINVAL;
 451         }
 452         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 453         radeon_bo_unreserve(rbo);
 454         if (tiling_flags & RADEON_TILING_MICRO)
 455                 DRM_ERROR("trying to scanout microtiled buffer\n");
 456
 457         /* if scanout was in GTT this really wouldn't work */
 458         /* crtc offset is from display base addr not FB location */
 459         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
 460
 461         base -= radeon_crtc->legacy_display_base_addr;
 462
 463         crtc_offset_cntl = 0;
 464
 465         pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 466         crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
 467                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 468                        (crtc->fb->bits_per_pixel * 8));
 469         crtc_pitch |= crtc_pitch << 16;
 470
 471
 472         if (tiling_flags & RADEON_TILING_MACRO) {
 473                 if (ASIC_IS_R300(rdev))
 474                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 475                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 476                                              R300_CRTC_MACRO_TILE_EN);
 477                 else
 478                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 479         } else {
 480                 if (ASIC_IS_R300(rdev))
 481                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 482                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 483                                               R300_CRTC_MACRO_TILE_EN);
 484                 else
 485                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 486         }
 487
 488         if (tiling_flags & RADEON_TILING_MACRO) {
 489                 if (ASIC_IS_R300(rdev)) {
 490                         crtc_tile_x0_y0 = x | (y << 16);
 491                         base &= ~0x7ff;
 492                 } else {
 493                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 494                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 495                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 496                         crtc_offset_cntl |= (y % 16);
 497                 }
 498         } else {
 499                 int offset = y * pitch_pixels + x;
 500                 switch (crtc->fb->bits_per_pixel) {
 501                 case 8:
 502                         offset *= 1;
 503                         break;
 504                 case 15:
 505                 case 16:
 506                         offset *= 2;
 507                         break;
 508                 case 24:
 509                         offset *= 3;
 510                         break;
 511                 case 32:
 512                         offset *= 4;
 513                         break;
 514                 default:
 515                         return false;
 516                 }
 517                 base += offset;
 518         }
 519
 520         base &= ~7;
 521
 522         if (radeon_crtc->crtc_id == 1)
 523                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 524         else
 525                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 526
 527         gen_cntl_val = RREG32(gen_cntl_reg);
 528         gen_cntl_val &= ~(0xf << 8);
 529         gen_cntl_val |= (format << 8);
 530         WREG32(gen_cntl_reg, gen_cntl_val);
 531
 532         crtc_offset = (u32)base;
 533
 534         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 535
 536         if (ASIC_IS_R300(rdev)) {
 537                 if (radeon_crtc->crtc_id)
 538                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 539                 else
 540                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 541         }
 542         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 543         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 544         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 545
 546         if (old_fb && old_fb != crtc->fb) {
 547                 radeon_fb = to_radeon_framebuffer(old_fb);
 548                 rbo = radeon_fb->obj->driver_private;
 549                 r = radeon_bo_reserve(rbo, false);
 550                 if (unlikely(r != 0))
 551                         return r;
 552                 radeon_bo_unpin(rbo);
 553                 radeon_bo_unreserve(rbo);
 554         }
 555
 556         /* Bytes per pixel may have changed */
 557         radeon_bandwidth_update(rdev);
 558
 559         return 0;
 560 }
 561
 562 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 563 {
 564         struct drm_device *dev = crtc->dev;
 565         struct radeon_device *rdev = dev->dev_private;
 566         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 567         struct drm_encoder *encoder;
 568         int format;
 569         int hsync_start;
 570         int hsync_wid;
 571         int vsync_wid;
 572         uint32_t crtc_h_total_disp;
 573         uint32_t crtc_h_sync_strt_wid;
 574         uint32_t crtc_v_total_disp;
 575         uint32_t crtc_v_sync_strt_wid;
 576         bool is_tv = false;
 577
 578         DRM_DEBUG("\n");
 579         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 580                 if (encoder->crtc == crtc) {
 581                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 582                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 583                                 is_tv = true;
 584                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 585                                 break;
 586                         }
 587                 }
 588         }
 589
 590         switch (crtc->fb->bits_per_pixel) {
 591         case 8:
 592                 format = 2;
 593                 break;
 594         case 15:      /*  555 */
 595                 format = 3;
 596                 break;
 597         case 16:      /*  565 */
 598                 format = 4;
 599                 break;
 600         case 24:      /*  RGB */
 601                 format = 5;
 602                 break;
 603         case 32:      /* xRGB */
 604                 format = 6;
 605                 break;
 606         default:
 607                 return false;
 608         }
 609
 610         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 611                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 612
 613         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 614         if (!hsync_wid)
 615                 hsync_wid = 1;
 616         hsync_start = mode->crtc_hsync_start - 8;
 617
 618         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 619                                 | ((hsync_wid & 0x3f) << 16)
 620                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 621                                    ? RADEON_CRTC_H_SYNC_POL
 622                                    : 0));
 623
 624         /* This works for double scan mode. */
 625         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 626                              | ((mode->crtc_vdisplay - 1) << 16));
 627
 628         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 629         if (!vsync_wid)
 630                 vsync_wid = 1;
 631
 632         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 633                                 | ((vsync_wid & 0x1f) << 16)
 634                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 635                                    ? RADEON_CRTC_V_SYNC_POL
 636                                    : 0));
 637
 638         /* TODO -> Dell Server */
 639         if (0) {
 640                 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 641                 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 642                 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 643                 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 644
 645                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 646                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 647
 648                 /* For CRT on DAC2, don't turn it on if BIOS didn't
 649                    enable it, even it's detected.
 650                 */
 651                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 652                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 653                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 654
 655                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 656                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 657                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 658                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 659         }
 660
 661         if (radeon_crtc->crtc_id) {
 662                 uint32_t crtc2_gen_cntl;
 663                 uint32_t disp2_merge_cntl;
 664
 665                 /* if TV DAC is enabled for another crtc and keep it enabled */
 666                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 667                 crtc2_gen_cntl |= ((format << 8)
 668                                    | RADEON_CRTC2_VSYNC_DIS
 669                                    | RADEON_CRTC2_HSYNC_DIS
 670                                    | RADEON_CRTC2_DISP_DIS
 671                                    | RADEON_CRTC2_DISP_REQ_EN_B
 672                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 673                                       ? RADEON_CRTC2_DBL_SCAN_EN
 674                                       : 0)
 675                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 676                                       ? RADEON_CRTC2_CSYNC_EN
 677                                       : 0)
 678                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 679                                       ? RADEON_CRTC2_INTERLACE_EN
 680                                       : 0));
 681
 682                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 683                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 684
 685                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 686                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 687
 688                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 689                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 690         } else {
 691                 uint32_t crtc_gen_cntl;
 692                 uint32_t crtc_ext_cntl;
 693                 uint32_t disp_merge_cntl;
 694
 695                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 696                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 697                                  | (format << 8)
 698                                  | RADEON_CRTC_DISP_REQ_EN_B
 699                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 700                                     ? RADEON_CRTC_DBL_SCAN_EN
 701                                     : 0)
 702                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 703                                     ? RADEON_CRTC_CSYNC_EN
 704                                     : 0)
 705                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 706                                     ? RADEON_CRTC_INTERLACE_EN
 707                                     : 0));
 708
 709                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 710                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 711                                   RADEON_CRTC_VSYNC_DIS |
 712                                   RADEON_CRTC_HSYNC_DIS |
 713                                   RADEON_CRTC_DISPLAY_DIS);
 714
 715                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 716                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 717
 718                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 719                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 720                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 721         }
 722
 723         if (is_tv)
 724                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 725                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 726                                                  &crtc_v_sync_strt_wid);
 727
 728         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 729         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 730         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 731         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 732
 733         return true;
 734 }
 735
 736 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 737 {
 738         struct drm_device *dev = crtc->dev;
 739         struct radeon_device *rdev = dev->dev_private;
 740         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 741         struct drm_encoder *encoder;
 742         uint32_t feedback_div = 0;
 743         uint32_t frac_fb_div = 0;
 744         uint32_t reference_div = 0;
 745         uint32_t post_divider = 0;
 746         uint32_t freq = 0;
 747         uint8_t pll_gain;
 748         int pll_flags = RADEON_PLL_LEGACY;
 749         bool use_bios_divs = false;
 750         /* PLL registers */
 751         uint32_t pll_ref_div = 0;
 752         uint32_t pll_fb_post_div = 0;
 753         uint32_t htotal_cntl = 0;
 754         bool is_tv = false;
 755         struct radeon_pll *pll;
 756
 757         struct {
 758                 int divider;
 759                 int bitvalue;
 760         } *post_div, post_divs[]   = {
 761                 /* From RAGE 128 VR/RAGE 128 GL Register
 762                  * Reference Manual (Technical Reference
 763                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 764                  * 3-17 (PLL_DIV_[3:0]).
 765                  */
 766                 {  1, 0 },              /* VCLK_SRC                 */
 767                 {  2, 1 },              /* VCLK_SRC/2               */
 768                 {  4, 2 },              /* VCLK_SRC/4               */
 769                 {  8, 3 },              /* VCLK_SRC/8               */
 770                 {  3, 4 },              /* VCLK_SRC/3               */
 771                 { 16, 5 },              /* VCLK_SRC/16              */
 772                 {  6, 6 },              /* VCLK_SRC/6               */
 773                 { 12, 7 },              /* VCLK_SRC/12              */
 774                 {  0, 0 }
 775         };
 776
 777         if (radeon_crtc->crtc_id)
 778                 pll = &rdev->clock.p2pll;
 779         else
 780                 pll = &rdev->clock.p1pll;
 781
 782         if (mode->clock > 200000) /* range limits??? */
 783                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 784         else
 785                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 786
 787         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 788                 if (encoder->crtc == crtc) {
 789                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 790
 791                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 792                                 is_tv = true;
 793                                 break;
 794                         }
 795
 796                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 797                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 798                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 799                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 800                                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 801                                 if (lvds) {
 802                                         if (lvds->use_bios_dividers) {
 803                                                 pll_ref_div = lvds->panel_ref_divider;
 804                                                 pll_fb_post_div   = (lvds->panel_fb_divider |
 805                                                                      (lvds->panel_post_divider << 16));
 806                                                 htotal_cntl  = 0;
 807                                                 use_bios_divs = true;
 808                                         }
 809                                 }
 810                                 pll_flags |= RADEON_PLL_USE_REF_DIV;
 811                         }
 812                 }
 813         }
 814
 815         DRM_DEBUG("\n");
 816
 817         if (!use_bios_divs) {
 818                 radeon_compute_pll(pll, mode->clock,
 819                                    &freq, &feedback_div, &frac_fb_div,
 820                                    &reference_div, &post_divider,
 821                                    pll_flags);
 822
 823                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 824                         if (post_div->divider == post_divider)
 825                                 break;
 826                 }
 827
 828                 if (!post_div->divider)
 829                         post_div = &post_divs[0];
 830
 831                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 832                           (unsigned)freq,
 833                           feedback_div,
 834                           reference_div,
 835                           post_divider);
 836
 837                 pll_ref_div   = reference_div;
 838 #if defined(__powerpc__) && (0) /* TODO */
 839                 /* apparently programming this otherwise causes a hang??? */
 840                 if (info->MacModel == RADEON_MAC_IBOOK)
 841                         pll_fb_post_div = 0x000600ad;
 842                 else
 843 #endif
 844                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 845
 846                 htotal_cntl    = mode->htotal & 0x7;
 847
 848         }
 849
 850         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 851                                            pll_ref_div & 0x3ff,
 852                                            pll_fb_post_div & 0x7ff);
 853
 854         if (radeon_crtc->crtc_id) {
 855                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 856                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 857                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 858
 859                 if (is_tv) {
 860                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 861                                                      &pll_ref_div, &pll_fb_post_div,
 862                                                      &pixclks_cntl);
 863                 }
 864
 865                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 866                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 867                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 868
 869                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 870                              RADEON_P2PLL_RESET
 871                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 872                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 873                              ~(RADEON_P2PLL_RESET
 874                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 875                                | RADEON_P2PLL_PVG_MASK));
 876
 877                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 878                              pll_ref_div,
 879                              ~RADEON_P2PLL_REF_DIV_MASK);
 880
 881                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 882                              pll_fb_post_div,
 883                              ~RADEON_P2PLL_FB0_DIV_MASK);
 884
 885                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 886                              pll_fb_post_div,
 887                              ~RADEON_P2PLL_POST0_DIV_MASK);
 888
 889                 radeon_pll2_write_update(dev);
 890                 radeon_pll2_wait_for_read_update_complete(dev);
 891
 892                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 893
 894                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 895                              0,
 896                              ~(RADEON_P2PLL_RESET
 897                                | RADEON_P2PLL_SLEEP
 898                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 899
 900                 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 901                           (unsigned)pll_ref_div,
 902                           (unsigned)pll_fb_post_div,
 903                           (unsigned)htotal_cntl,
 904                           RREG32_PLL(RADEON_P2PLL_CNTL));
 905                 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 906                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 907                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 908                           (unsigned)((pll_fb_post_div &
 909                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 910
 911                 mdelay(50); /* Let the clock to lock */
 912
 913                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 914                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 915                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 916
 917                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 918         } else {
 919                 uint32_t pixclks_cntl;
 920
 921
 922                 if (is_tv) {
 923                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 924                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 925                                                      &pll_fb_post_div, &pixclks_cntl);
 926                 }
 927
 928                 if (rdev->flags & RADEON_IS_MOBILITY) {
 929                         /* A temporal workaround for the occational blanking on certain laptop panels.
 930                            This appears to related to the PLL divider registers (fail to lock?).
 931                            It occurs even when all dividers are the same with their old settings.
 932                            In this case we really don't need to fiddle with PLL registers.
 933                            By doing this we can avoid the blanking problem with some panels.
 934                         */
 935                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 936                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 937                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 938                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 939                                          RADEON_PLL_DIV_SEL,
 940                                          ~(RADEON_PLL_DIV_SEL));
 941                                 r100_pll_errata_after_index(rdev);
 942                                 return;
 943                         }
 944                 }
 945
 946                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 947                              RADEON_VCLK_SRC_SEL_CPUCLK,
 948                              ~(RADEON_VCLK_SRC_SEL_MASK));
 949                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 950                              RADEON_PPLL_RESET
 951                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 952                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 953                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 954                              ~(RADEON_PPLL_RESET
 955                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 956                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 957                                | RADEON_PPLL_PVG_MASK));
 958
 959                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 960                          RADEON_PLL_DIV_SEL,
 961                          ~(RADEON_PLL_DIV_SEL));
 962                 r100_pll_errata_after_index(rdev);
 963
 964                 if (ASIC_IS_R300(rdev) ||
 965                     (rdev->family == CHIP_RS300) ||
 966                     (rdev->family == CHIP_RS400) ||
 967                     (rdev->family == CHIP_RS480)) {
 968                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 969                                 /* When restoring console mode, use saved PPLL_REF_DIV
 970                                  * setting.
 971                                  */
 972                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 973                                              pll_ref_div,
 974                                              0);
 975                         } else {
 976                                 /* R300 uses ref_div_acc field as real ref divider */
 977                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 978                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 979                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 980                         }
 981                 } else
 982                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 983                                      pll_ref_div,
 984                                      ~RADEON_PPLL_REF_DIV_MASK);
 985
 986                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 987                              pll_fb_post_div,
 988                              ~RADEON_PPLL_FB3_DIV_MASK);
 989
 990                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 991                              pll_fb_post_div,
 992                              ~RADEON_PPLL_POST3_DIV_MASK);
 993
 994                 radeon_pll_write_update(dev);
 995                 radeon_pll_wait_for_read_update_complete(dev);
 996
 997                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 998
 999                 WREG32_PLL_P(RADEON_PPLL_CNTL,
1000                              0,
1001                              ~(RADEON_PPLL_RESET
1002                                | RADEON_PPLL_SLEEP
1003                                | RADEON_PPLL_ATOMIC_UPDATE_EN
1004                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1005
1006                 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1007                           pll_ref_div,
1008                           pll_fb_post_div,
1009                           (unsigned)htotal_cntl,
1010                           RREG32_PLL(RADEON_PPLL_CNTL));
1011                 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
1012                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1013                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1014                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1015
1016                 mdelay(50); /* Let the clock to lock */
1017
1018                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1019                              RADEON_VCLK_SRC_SEL_PPLLCLK,
1020                              ~(RADEON_VCLK_SRC_SEL_MASK));
1021
1022                 if (is_tv)
1023                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1024         }
1025 }
1026
1027 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1028                                    struct drm_display_mode *mode,
1029                                    struct drm_display_mode *adjusted_mode)
1030 {
1031         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1032                 return false;
1033         return true;
1034 }
1035
1036 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1037                                  struct drm_display_mode *mode,
1038                                  struct drm_display_mode *adjusted_mode,
1039                                  int x, int y, struct drm_framebuffer *old_fb)
1040 {
1041         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1042
1043         /* TODO TV */
1044         radeon_crtc_set_base(crtc, x, y, old_fb);
1045         radeon_set_crtc_timing(crtc, adjusted_mode);
1046         radeon_set_pll(crtc, adjusted_mode);
1047         if (radeon_crtc->crtc_id == 0) {
1048                 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1049         } else {
1050                 if (radeon_crtc->rmx_type != RMX_OFF) {
1051                         /* FIXME: only first crtc has rmx what should we
1052                          * do ?
1053                          */
1054                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1055                 }
1056         }
1057         return 0;
1058 }
1059
1060 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1061 {
1062         struct drm_device *dev = crtc->dev;
1063         struct drm_crtc *crtci;
1064
1065         /*
1066         * The hardware wedges sometimes if you reconfigure one CRTC
1067         * whilst another is running (see fdo bug #24611).
1068         */
1069         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1070                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1071 }
1072
1073 static void radeon_crtc_commit(struct drm_crtc *crtc)
1074 {
1075         struct drm_device *dev = crtc->dev;
1076         struct drm_crtc *crtci;
1077
1078         /*
1079         * Reenable the CRTCs that should be running.
1080         */
1081         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1082                 if (crtci->enabled)
1083                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1084         }
1085 }
1086
1087 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1088         .dpms = radeon_crtc_dpms,
1089         .mode_fixup = radeon_crtc_mode_fixup,
1090         .mode_set = radeon_crtc_mode_set,
1091         .mode_set_base = radeon_crtc_set_base,
1092         .prepare = radeon_crtc_prepare,
1093         .commit = radeon_crtc_commit,
1094         .load_lut = radeon_crtc_load_lut,
1095 };
1096
1097
1098 void radeon_legacy_init_crtc(struct drm_device *dev,
1099                                struct radeon_crtc *radeon_crtc)
1100 {
1101         if (radeon_crtc->crtc_id == 1)
1102                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1103         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1104 }