2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
180 radeon_link_encoder_connector(struct drm_device *dev)
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
215 static struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
225 if (radeon_encoder->active_device & radeon_connector->devices)
231 static struct radeon_connector_atom_dig *
232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct drm_connector *connector;
237 struct radeon_connector *radeon_connector;
238 struct radeon_connector_atom_dig *dig_connector;
240 if (!rdev->is_atom_bios)
243 connector = radeon_get_connector_for_encoder(encoder);
247 radeon_connector = to_radeon_connector(connector);
249 if (!radeon_connector->con_priv)
252 dig_connector = radeon_connector->con_priv;
254 return dig_connector;
257 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *adjusted_mode)
260 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
261 struct drm_device *dev = encoder->dev;
262 struct radeon_device *rdev = dev->dev_private;
263 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
264 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
265 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
266 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
267 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
268 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
269 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
271 adjusted_mode->clock = native_mode->clock;
272 adjusted_mode->flags = native_mode->flags;
274 if (ASIC_IS_AVIVO(rdev)) {
275 adjusted_mode->hdisplay = native_mode->hdisplay;
276 adjusted_mode->vdisplay = native_mode->vdisplay;
279 adjusted_mode->htotal = native_mode->hdisplay + hblank;
280 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
281 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
283 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
284 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
285 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
287 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
289 if (ASIC_IS_AVIVO(rdev)) {
290 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
291 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
294 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
295 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
296 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
298 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
299 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
300 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
304 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
305 struct drm_display_mode *mode,
306 struct drm_display_mode *adjusted_mode)
308 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
309 struct drm_device *dev = encoder->dev;
310 struct radeon_device *rdev = dev->dev_private;
312 /* adjust pm to upcoming mode change */
313 radeon_pm_compute_clocks(rdev);
315 /* set the active encoder to connector routing */
316 radeon_encoder_set_active_device(encoder);
317 drm_mode_set_crtcinfo(adjusted_mode, 0);
320 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
321 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
322 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
324 /* get the native mode for LVDS */
325 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
326 radeon_panel_mode_fixup(encoder, adjusted_mode);
328 /* get the native mode for TV */
329 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
330 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
332 if (tv_dac->tv_std == TV_STD_NTSC ||
333 tv_dac->tv_std == TV_STD_NTSC_J ||
334 tv_dac->tv_std == TV_STD_PAL_M)
335 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
337 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
341 if (ASIC_IS_DCE3(rdev) &&
342 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
343 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
344 radeon_dp_set_link_config(connector, mode);
351 atombios_dac_setup(struct drm_encoder *encoder, int action)
353 struct drm_device *dev = encoder->dev;
354 struct radeon_device *rdev = dev->dev_private;
355 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
356 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
358 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
360 memset(&args, 0, sizeof(args));
362 switch (radeon_encoder->encoder_id) {
363 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
364 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
365 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
367 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
368 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
369 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
373 args.ucAction = action;
375 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
376 args.ucDacStandard = ATOM_DAC1_PS2;
377 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
378 args.ucDacStandard = ATOM_DAC1_CV;
380 switch (dac_info->tv_std) {
383 case TV_STD_SCART_PAL:
386 args.ucDacStandard = ATOM_DAC1_PAL;
392 args.ucDacStandard = ATOM_DAC1_NTSC;
396 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
398 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
403 atombios_tv_setup(struct drm_encoder *encoder, int action)
405 struct drm_device *dev = encoder->dev;
406 struct radeon_device *rdev = dev->dev_private;
407 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
408 TV_ENCODER_CONTROL_PS_ALLOCATION args;
410 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
412 memset(&args, 0, sizeof(args));
414 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
416 args.sTVEncoder.ucAction = action;
418 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
419 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
421 switch (dac_info->tv_std) {
423 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
426 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
429 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
432 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
435 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
437 case TV_STD_SCART_PAL:
438 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
441 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
444 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
447 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
452 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
454 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
459 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
461 struct drm_device *dev = encoder->dev;
462 struct radeon_device *rdev = dev->dev_private;
463 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
464 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
467 memset(&args, 0, sizeof(args));
469 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
471 args.sXTmdsEncoder.ucEnable = action;
473 if (radeon_encoder->pixel_clock > 165000)
474 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
476 /*if (pScrn->rgbBits == 8)*/
477 args.sXTmdsEncoder.ucMisc |= (1 << 1);
479 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
484 atombios_ddia_setup(struct drm_encoder *encoder, int action)
486 struct drm_device *dev = encoder->dev;
487 struct radeon_device *rdev = dev->dev_private;
488 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
489 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
492 memset(&args, 0, sizeof(args));
494 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
496 args.sDVOEncoder.ucAction = action;
497 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
499 if (radeon_encoder->pixel_clock > 165000)
500 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
502 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
506 union lvds_encoder_control {
507 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
508 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
512 atombios_digital_setup(struct drm_encoder *encoder, int action)
514 struct drm_device *dev = encoder->dev;
515 struct radeon_device *rdev = dev->dev_private;
516 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
517 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
518 struct radeon_connector_atom_dig *dig_connector =
519 radeon_get_atom_connector_priv_from_encoder(encoder);
520 union lvds_encoder_control args;
522 int hdmi_detected = 0;
525 if (!dig || !dig_connector)
528 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
531 memset(&args, 0, sizeof(args));
533 switch (radeon_encoder->encoder_id) {
534 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
535 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
537 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
538 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
539 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
541 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
542 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
543 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
545 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
549 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
558 args.v1.ucAction = action;
560 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
561 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
562 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
563 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
564 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
565 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
566 args.v1.ucMisc |= (1 << 1);
568 if (dig_connector->linkb)
569 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
570 if (radeon_encoder->pixel_clock > 165000)
571 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
572 /*if (pScrn->rgbBits == 8) */
573 args.v1.ucMisc |= (1 << 1);
579 args.v2.ucAction = action;
581 if (dig->coherent_mode)
582 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
585 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
586 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
587 args.v2.ucTruncate = 0;
588 args.v2.ucSpatial = 0;
589 args.v2.ucTemporal = 0;
591 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
592 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
593 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
594 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
595 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
596 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
597 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
599 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
600 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
601 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
602 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
603 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
604 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
607 if (dig_connector->linkb)
608 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
609 if (radeon_encoder->pixel_clock > 165000)
610 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
614 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
619 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
623 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
627 atombios_get_encoder_mode(struct drm_encoder *encoder)
629 struct drm_connector *connector;
630 struct radeon_connector *radeon_connector;
631 struct radeon_connector_atom_dig *dig_connector;
633 connector = radeon_get_connector_for_encoder(encoder);
637 radeon_connector = to_radeon_connector(connector);
639 switch (connector->connector_type) {
640 case DRM_MODE_CONNECTOR_DVII:
641 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
642 if (drm_detect_hdmi_monitor(radeon_connector->edid))
643 return ATOM_ENCODER_MODE_HDMI;
644 else if (radeon_connector->use_digital)
645 return ATOM_ENCODER_MODE_DVI;
647 return ATOM_ENCODER_MODE_CRT;
649 case DRM_MODE_CONNECTOR_DVID:
650 case DRM_MODE_CONNECTOR_HDMIA:
652 if (drm_detect_hdmi_monitor(radeon_connector->edid))
653 return ATOM_ENCODER_MODE_HDMI;
655 return ATOM_ENCODER_MODE_DVI;
657 case DRM_MODE_CONNECTOR_LVDS:
658 return ATOM_ENCODER_MODE_LVDS;
660 case DRM_MODE_CONNECTOR_DisplayPort:
661 case DRM_MODE_CONNECTOR_eDP:
662 dig_connector = radeon_connector->con_priv;
663 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
664 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
665 return ATOM_ENCODER_MODE_DP;
666 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
667 return ATOM_ENCODER_MODE_HDMI;
669 return ATOM_ENCODER_MODE_DVI;
671 case DRM_MODE_CONNECTOR_DVIA:
672 case DRM_MODE_CONNECTOR_VGA:
673 return ATOM_ENCODER_MODE_CRT;
675 case DRM_MODE_CONNECTOR_Composite:
676 case DRM_MODE_CONNECTOR_SVIDEO:
677 case DRM_MODE_CONNECTOR_9PinDIN:
679 return ATOM_ENCODER_MODE_TV;
680 /*return ATOM_ENCODER_MODE_CV;*/
686 * DIG Encoder/Transmitter Setup
689 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
690 * Supports up to 3 digital outputs
691 * - 2 DIG encoder blocks.
692 * DIG1 can drive UNIPHY link A or link B
693 * DIG2 can drive UNIPHY link B or LVTMA
696 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
697 * Supports up to 5 digital outputs
698 * - 2 DIG encoder blocks.
699 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
702 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
703 * Supports up to 6 digital outputs
704 * - 6 DIG encoder blocks.
705 * - DIG to PHY mapping is hardcoded
706 * DIG1 drives UNIPHY0 link A, A+B
707 * DIG2 drives UNIPHY0 link B
708 * DIG3 drives UNIPHY1 link A, A+B
709 * DIG4 drives UNIPHY1 link B
710 * DIG5 drives UNIPHY2 link A, A+B
711 * DIG6 drives UNIPHY2 link B
714 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
716 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
717 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
718 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
719 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
722 union dig_encoder_control {
723 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
724 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
725 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
729 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
731 struct drm_device *dev = encoder->dev;
732 struct radeon_device *rdev = dev->dev_private;
733 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
734 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
735 struct radeon_connector_atom_dig *dig_connector =
736 radeon_get_atom_connector_priv_from_encoder(encoder);
737 union dig_encoder_control args;
741 if (!dig || !dig_connector)
744 memset(&args, 0, sizeof(args));
746 if (ASIC_IS_DCE4(rdev))
747 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
749 if (dig->dig_encoder)
750 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
752 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
755 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
758 args.v1.ucAction = action;
759 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
760 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
762 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
763 if (dig_connector->dp_clock == 270000)
764 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
765 args.v1.ucLaneNum = dig_connector->dp_lane_count;
766 } else if (radeon_encoder->pixel_clock > 165000)
767 args.v1.ucLaneNum = 8;
769 args.v1.ucLaneNum = 4;
771 if (ASIC_IS_DCE4(rdev)) {
772 args.v3.acConfig.ucDigSel = dig->dig_encoder;
773 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
775 switch (radeon_encoder->encoder_id) {
776 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
777 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
779 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
780 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
781 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
783 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
784 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
787 if (dig_connector->linkb)
788 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
790 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
793 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
797 union dig_transmitter_control {
798 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
799 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
800 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
804 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
806 struct drm_device *dev = encoder->dev;
807 struct radeon_device *rdev = dev->dev_private;
808 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
809 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
810 struct radeon_connector_atom_dig *dig_connector =
811 radeon_get_atom_connector_priv_from_encoder(encoder);
812 struct drm_connector *connector;
813 struct radeon_connector *radeon_connector;
814 union dig_transmitter_control args;
820 if (!dig || !dig_connector)
823 connector = radeon_get_connector_for_encoder(encoder);
824 radeon_connector = to_radeon_connector(connector);
826 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
829 memset(&args, 0, sizeof(args));
831 if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
832 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
834 switch (radeon_encoder->encoder_id) {
835 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
836 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
838 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
839 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
844 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
847 args.v1.ucAction = action;
848 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
849 args.v1.usInitInfo = radeon_connector->connector_object_id;
850 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
851 args.v1.asMode.ucLaneSel = lane_num;
852 args.v1.asMode.ucLaneSet = lane_set;
855 args.v1.usPixelClock =
856 cpu_to_le16(dig_connector->dp_clock / 10);
857 else if (radeon_encoder->pixel_clock > 165000)
858 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
860 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
862 if (ASIC_IS_DCE4(rdev)) {
864 args.v3.ucLaneNum = dig_connector->dp_lane_count;
865 else if (radeon_encoder->pixel_clock > 165000)
866 args.v3.ucLaneNum = 8;
868 args.v3.ucLaneNum = 4;
870 if (dig_connector->linkb) {
871 args.v3.acConfig.ucLinkSel = 1;
872 args.v3.acConfig.ucEncoderSel = 1;
875 /* Select the PLL for the PHY
876 * DP PHY should be clocked from external src if there is
880 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
881 pll_id = radeon_crtc->pll_id;
883 if (is_dp && rdev->clock.dp_extclk)
884 args.v3.acConfig.ucRefClkSource = 2; /* external src */
886 args.v3.acConfig.ucRefClkSource = pll_id;
888 switch (radeon_encoder->encoder_id) {
889 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
890 args.v3.acConfig.ucTransmitterSel = 0;
892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
893 args.v3.acConfig.ucTransmitterSel = 1;
895 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
896 args.v3.acConfig.ucTransmitterSel = 2;
901 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
902 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
903 if (dig->coherent_mode)
904 args.v3.acConfig.fCoherentMode = 1;
905 if (radeon_encoder->pixel_clock > 165000)
906 args.v3.acConfig.fDualLinkConnector = 1;
908 } else if (ASIC_IS_DCE32(rdev)) {
909 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
910 if (dig_connector->linkb)
911 args.v2.acConfig.ucLinkSel = 1;
913 switch (radeon_encoder->encoder_id) {
914 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
915 args.v2.acConfig.ucTransmitterSel = 0;
917 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
918 args.v2.acConfig.ucTransmitterSel = 1;
920 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
921 args.v2.acConfig.ucTransmitterSel = 2;
926 args.v2.acConfig.fCoherentMode = 1;
927 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
928 if (dig->coherent_mode)
929 args.v2.acConfig.fCoherentMode = 1;
930 if (radeon_encoder->pixel_clock > 165000)
931 args.v2.acConfig.fDualLinkConnector = 1;
934 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
936 if (dig->dig_encoder)
937 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
939 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
941 if ((rdev->flags & RADEON_IS_IGP) &&
942 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
943 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
944 if (dig_connector->igp_lane_info & 0x1)
945 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
946 else if (dig_connector->igp_lane_info & 0x2)
947 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
948 else if (dig_connector->igp_lane_info & 0x4)
949 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
950 else if (dig_connector->igp_lane_info & 0x8)
951 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
953 if (dig_connector->igp_lane_info & 0x3)
954 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
955 else if (dig_connector->igp_lane_info & 0xc)
956 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
960 if (dig_connector->linkb)
961 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
963 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
966 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
967 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
968 if (dig->coherent_mode)
969 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
970 if (radeon_encoder->pixel_clock > 165000)
971 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
979 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
981 struct drm_device *dev = encoder->dev;
982 struct radeon_device *rdev = dev->dev_private;
983 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
984 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
985 ENABLE_YUV_PS_ALLOCATION args;
986 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
989 memset(&args, 0, sizeof(args));
991 if (rdev->family >= CHIP_R600)
992 reg = R600_BIOS_3_SCRATCH;
994 reg = RADEON_BIOS_3_SCRATCH;
996 /* XXX: fix up scratch reg handling */
998 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
999 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1000 (radeon_crtc->crtc_id << 18)));
1001 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1002 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1007 args.ucEnable = ATOM_ENABLE;
1008 args.ucCRTC = radeon_crtc->crtc_id;
1010 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1016 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1018 struct drm_device *dev = encoder->dev;
1019 struct radeon_device *rdev = dev->dev_private;
1020 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1021 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1023 bool is_dig = false;
1025 memset(&args, 0, sizeof(args));
1027 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1028 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1029 radeon_encoder->active_device);
1030 switch (radeon_encoder->encoder_id) {
1031 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1032 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1033 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1036 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1038 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1041 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1042 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1043 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1044 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1046 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1047 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1049 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1050 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1051 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1053 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1055 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1056 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1057 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1058 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1059 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1060 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1062 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1064 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1065 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1066 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1067 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1068 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1069 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1071 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1077 case DRM_MODE_DPMS_ON:
1078 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1079 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1081 dp_link_train(encoder, connector);
1082 if (ASIC_IS_DCE4(rdev))
1083 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1085 if (!ASIC_IS_DCE4(rdev))
1086 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1088 case DRM_MODE_DPMS_STANDBY:
1089 case DRM_MODE_DPMS_SUSPEND:
1090 case DRM_MODE_DPMS_OFF:
1091 if (!ASIC_IS_DCE4(rdev))
1092 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1093 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1094 if (ASIC_IS_DCE4(rdev))
1095 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1101 case DRM_MODE_DPMS_ON:
1102 args.ucAction = ATOM_ENABLE;
1104 case DRM_MODE_DPMS_STANDBY:
1105 case DRM_MODE_DPMS_SUSPEND:
1106 case DRM_MODE_DPMS_OFF:
1107 args.ucAction = ATOM_DISABLE;
1110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1112 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1114 /* adjust pm to dpms change */
1115 radeon_pm_compute_clocks(rdev);
1118 union crtc_source_param {
1119 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1120 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1124 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1126 struct drm_device *dev = encoder->dev;
1127 struct radeon_device *rdev = dev->dev_private;
1128 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1129 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1130 union crtc_source_param args;
1131 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1133 struct radeon_encoder_atom_dig *dig;
1135 memset(&args, 0, sizeof(args));
1137 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1145 if (ASIC_IS_AVIVO(rdev))
1146 args.v1.ucCRTC = radeon_crtc->crtc_id;
1148 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1149 args.v1.ucCRTC = radeon_crtc->crtc_id;
1151 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1154 switch (radeon_encoder->encoder_id) {
1155 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1156 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1157 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1159 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1160 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1161 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1162 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1164 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1166 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1167 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1169 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1171 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1172 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1173 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1174 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1175 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1176 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1178 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1180 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1181 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1182 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1183 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1184 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1185 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1187 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1192 args.v2.ucCRTC = radeon_crtc->crtc_id;
1193 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1194 switch (radeon_encoder->encoder_id) {
1195 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1196 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1197 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1198 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1199 dig = radeon_encoder->enc_priv;
1200 switch (dig->dig_encoder) {
1202 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1205 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1208 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1211 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1214 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1217 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1221 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1222 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1224 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1225 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1226 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1227 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1228 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1230 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1232 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1233 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1234 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1235 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1236 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1238 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1245 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1249 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1251 /* update scratch regs with new routing */
1252 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1256 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1257 struct drm_display_mode *mode)
1259 struct drm_device *dev = encoder->dev;
1260 struct radeon_device *rdev = dev->dev_private;
1261 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1262 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1264 /* Funky macbooks */
1265 if ((dev->pdev->device == 0x71C5) &&
1266 (dev->pdev->subsystem_vendor == 0x106b) &&
1267 (dev->pdev->subsystem_device == 0x0080)) {
1268 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1269 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1271 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1272 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1274 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1278 /* set scaler clears this on some chips */
1279 /* XXX check DCE4 */
1280 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1281 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1282 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1283 AVIVO_D1MODE_INTERLEAVE_EN);
1287 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1289 struct drm_device *dev = encoder->dev;
1290 struct radeon_device *rdev = dev->dev_private;
1291 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1292 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1293 struct drm_encoder *test_encoder;
1294 struct radeon_encoder_atom_dig *dig;
1295 uint32_t dig_enc_in_use = 0;
1297 if (ASIC_IS_DCE4(rdev)) {
1298 struct radeon_connector_atom_dig *dig_connector =
1299 radeon_get_atom_connector_priv_from_encoder(encoder);
1301 switch (radeon_encoder->encoder_id) {
1302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1303 if (dig_connector->linkb)
1308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1309 if (dig_connector->linkb)
1314 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1315 if (dig_connector->linkb)
1323 /* on DCE32 and encoder can driver any block so just crtc id */
1324 if (ASIC_IS_DCE32(rdev)) {
1325 return radeon_crtc->crtc_id;
1328 /* on DCE3 - LVTMA can only be driven by DIGB */
1329 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1330 struct radeon_encoder *radeon_test_encoder;
1332 if (encoder == test_encoder)
1335 if (!radeon_encoder_is_digital(test_encoder))
1338 radeon_test_encoder = to_radeon_encoder(test_encoder);
1339 dig = radeon_test_encoder->enc_priv;
1341 if (dig->dig_encoder >= 0)
1342 dig_enc_in_use |= (1 << dig->dig_encoder);
1345 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1346 if (dig_enc_in_use & 0x2)
1347 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1350 if (!(dig_enc_in_use & 1))
1356 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1357 struct drm_display_mode *mode,
1358 struct drm_display_mode *adjusted_mode)
1360 struct drm_device *dev = encoder->dev;
1361 struct radeon_device *rdev = dev->dev_private;
1362 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1364 radeon_encoder->pixel_clock = adjusted_mode->clock;
1366 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1367 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1368 atombios_yuv_setup(encoder, true);
1370 atombios_yuv_setup(encoder, false);
1373 switch (radeon_encoder->encoder_id) {
1374 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1376 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1377 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1378 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1380 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1382 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1383 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1384 if (ASIC_IS_DCE4(rdev)) {
1385 /* disable the transmitter */
1386 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1387 /* setup and enable the encoder */
1388 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1390 /* init and enable the transmitter */
1391 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1392 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1394 /* disable the encoder and transmitter */
1395 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1396 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1398 /* setup and enable the encoder and transmitter */
1399 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1400 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1401 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1402 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1405 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1406 atombios_ddia_setup(encoder, ATOM_ENABLE);
1408 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1410 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1412 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1413 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1414 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1415 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1416 atombios_dac_setup(encoder, ATOM_ENABLE);
1417 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1418 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1419 atombios_tv_setup(encoder, ATOM_ENABLE);
1421 atombios_tv_setup(encoder, ATOM_DISABLE);
1425 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1427 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1428 r600_hdmi_enable(encoder);
1429 r600_hdmi_setmode(encoder, adjusted_mode);
1434 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1436 struct drm_device *dev = encoder->dev;
1437 struct radeon_device *rdev = dev->dev_private;
1438 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1439 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1441 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1442 ATOM_DEVICE_CV_SUPPORT |
1443 ATOM_DEVICE_CRT_SUPPORT)) {
1444 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1445 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1448 memset(&args, 0, sizeof(args));
1450 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1453 args.sDacload.ucMisc = 0;
1455 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1456 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1457 args.sDacload.ucDacType = ATOM_DAC_A;
1459 args.sDacload.ucDacType = ATOM_DAC_B;
1461 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1462 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1463 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1464 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1465 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1466 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1468 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1469 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1470 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1472 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1475 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1482 static enum drm_connector_status
1483 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1485 struct drm_device *dev = encoder->dev;
1486 struct radeon_device *rdev = dev->dev_private;
1487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1488 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1489 uint32_t bios_0_scratch;
1491 if (!atombios_dac_load_detect(encoder, connector)) {
1492 DRM_DEBUG("detect returned false \n");
1493 return connector_status_unknown;
1496 if (rdev->family >= CHIP_R600)
1497 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1499 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1501 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1502 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1503 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1504 return connector_status_connected;
1506 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1507 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1508 return connector_status_connected;
1510 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1511 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1512 return connector_status_connected;
1514 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1515 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1516 return connector_status_connected; /* CTV */
1517 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1518 return connector_status_connected; /* STV */
1520 return connector_status_disconnected;
1523 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1525 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1527 if (radeon_encoder->active_device &
1528 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1529 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1531 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1534 radeon_atom_output_lock(encoder, true);
1535 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1537 /* this is needed for the pll/ss setup to work correctly in some cases */
1538 atombios_set_encoder_crtc_source(encoder);
1541 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1543 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1544 radeon_atom_output_lock(encoder, false);
1547 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1549 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1550 struct radeon_encoder_atom_dig *dig;
1551 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1553 if (radeon_encoder_is_digital(encoder)) {
1554 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1555 r600_hdmi_disable(encoder);
1556 dig = radeon_encoder->enc_priv;
1557 dig->dig_encoder = -1;
1559 radeon_encoder->active_device = 0;
1562 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1563 .dpms = radeon_atom_encoder_dpms,
1564 .mode_fixup = radeon_atom_mode_fixup,
1565 .prepare = radeon_atom_encoder_prepare,
1566 .mode_set = radeon_atom_encoder_mode_set,
1567 .commit = radeon_atom_encoder_commit,
1568 .disable = radeon_atom_encoder_disable,
1569 /* no detect for TMDS/LVDS yet */
1572 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1573 .dpms = radeon_atom_encoder_dpms,
1574 .mode_fixup = radeon_atom_mode_fixup,
1575 .prepare = radeon_atom_encoder_prepare,
1576 .mode_set = radeon_atom_encoder_mode_set,
1577 .commit = radeon_atom_encoder_commit,
1578 .detect = radeon_atom_dac_detect,
1581 void radeon_enc_destroy(struct drm_encoder *encoder)
1583 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1584 kfree(radeon_encoder->enc_priv);
1585 drm_encoder_cleanup(encoder);
1586 kfree(radeon_encoder);
1589 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1590 .destroy = radeon_enc_destroy,
1593 struct radeon_encoder_atom_dac *
1594 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1596 struct drm_device *dev = radeon_encoder->base.dev;
1597 struct radeon_device *rdev = dev->dev_private;
1598 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1603 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1607 struct radeon_encoder_atom_dig *
1608 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1610 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1615 /* coherent mode by default */
1616 dig->coherent_mode = true;
1617 dig->dig_encoder = -1;
1623 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1625 struct radeon_device *rdev = dev->dev_private;
1626 struct drm_encoder *encoder;
1627 struct radeon_encoder *radeon_encoder;
1629 /* see if we already added it */
1630 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1631 radeon_encoder = to_radeon_encoder(encoder);
1632 if (radeon_encoder->encoder_id == encoder_id) {
1633 radeon_encoder->devices |= supported_device;
1640 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1641 if (!radeon_encoder)
1644 encoder = &radeon_encoder->base;
1645 switch (rdev->num_crtc) {
1647 encoder->possible_crtcs = 0x1;
1651 encoder->possible_crtcs = 0x3;
1654 encoder->possible_crtcs = 0x3f;
1658 radeon_encoder->enc_priv = NULL;
1660 radeon_encoder->encoder_id = encoder_id;
1661 radeon_encoder->devices = supported_device;
1662 radeon_encoder->rmx_type = RMX_OFF;
1664 switch (radeon_encoder->encoder_id) {
1665 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1666 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1667 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1668 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1669 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1670 radeon_encoder->rmx_type = RMX_FULL;
1671 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1672 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1674 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1675 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1677 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1679 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1680 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1681 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1682 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1684 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1685 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1686 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1687 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1688 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1689 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1691 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1692 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1693 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1694 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1695 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1696 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1697 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1698 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1699 radeon_encoder->rmx_type = RMX_FULL;
1700 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1701 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1703 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1704 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1706 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);