drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "atom.h"
  38
  39 static const char radeon_family_name[][16] = {
  40         "R100",
  41         "RV100",
  42         "RS100",
  43         "RV200",
  44         "RS200",
  45         "R200",
  46         "RV250",
  47         "RS300",
  48         "RV280",
  49         "R300",
  50         "R350",
  51         "RV350",
  52         "RV380",
  53         "R420",
  54         "R423",
  55         "RV410",
  56         "RS400",
  57         "RS480",
  58         "RS600",
  59         "RS690",
  60         "RS740",
  61         "RV515",
  62         "R520",
  63         "RV530",
  64         "RV560",
  65         "RV570",
  66         "R580",
  67         "R600",
  68         "RV610",
  69         "RV630",
  70         "RV670",
  71         "RV620",
  72         "RV635",
  73         "RS780",
  74         "RS880",
  75         "RV770",
  76         "RV730",
  77         "RV710",
  78         "RV740",
  79         "CEDAR",
  80         "REDWOOD",
  81         "JUNIPER",
  82         "CYPRESS",
  83         "HEMLOCK",
  84         "LAST",
  85 };
  86
  87 /*
  88  * Clear GPU surface registers.
  89  */
  90 void radeon_surface_init(struct radeon_device *rdev)
  91 {
  92         /* FIXME: check this out */
  93         if (rdev->family < CHIP_R600) {
  94                 int i;
  95
  96                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  97                         if (rdev->surface_regs[i].bo)
  98                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
  99                         else
 100                                 radeon_clear_surface_reg(rdev, i);
 101                 }
 102                 /* enable surfaces */
 103                 WREG32(RADEON_SURFACE_CNTL, 0);
 104         }
 105 }
 106
 107 /*
 108  * GPU scratch registers helpers function.
 109  */
 110 void radeon_scratch_init(struct radeon_device *rdev)
 111 {
 112         int i;
 113
 114         /* FIXME: check this out */
 115         if (rdev->family < CHIP_R300) {
 116                 rdev->scratch.num_reg = 5;
 117         } else {
 118                 rdev->scratch.num_reg = 7;
 119         }
 120         for (i = 0; i < rdev->scratch.num_reg; i++) {
 121                 rdev->scratch.free[i] = true;
 122                 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
 123         }
 124 }
 125
 126 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 127 {
 128         int i;
 129
 130         for (i = 0; i < rdev->scratch.num_reg; i++) {
 131                 if (rdev->scratch.free[i]) {
 132                         rdev->scratch.free[i] = false;
 133                         *reg = rdev->scratch.reg[i];
 134                         return 0;
 135                 }
 136         }
 137         return -EINVAL;
 138 }
 139
 140 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 141 {
 142         int i;
 143
 144         for (i = 0; i < rdev->scratch.num_reg; i++) {
 145                 if (rdev->scratch.reg[i] == reg) {
 146                         rdev->scratch.free[i] = true;
 147                         return;
 148                 }
 149         }
 150 }
 151
 152 /**
 153  * radeon_vram_location - try to find VRAM location
 154  * @rdev: radeon device structure holding all necessary informations
 155  * @mc: memory controller structure holding memory informations
 156  * @base: base address at which to put VRAM
 157  *
 158  * Function will place try to place VRAM at base address provided
 159  * as parameter (which is so far either PCI aperture address or
 160  * for IGP TOM base address).
 161  *
 162  * If there is not enough space to fit the unvisible VRAM in the 32bits
 163  * address space then we limit the VRAM size to the aperture.
 164  *
 165  * If we are using AGP and if the AGP aperture doesn't allow us to have
 166  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 167  * size and print a warning.
 168  *
 169  * This function will never fails, worst case are limiting VRAM.
 170  *
 171  * Note: GTT start, end, size should be initialized before calling this
 172  * function on AGP platform.
 173  *
 174  * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
 175  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 176  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 177  * not IGP.
 178  *
 179  * Note: we use mc_vram_size as on some board we need to program the mc to
 180  * cover the whole aperture even if VRAM size is inferior to aperture size
 181  * Novell bug 204882 + along with lots of ubuntu ones
 182  *
 183  * Note: when limiting vram it's safe to overwritte real_vram_size because
 184  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 185  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 186  * ones)
 187  *
 188  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 189  * explicitly check for that thought.
 190  *
 191  * FIXME: when reducing VRAM size align new size on power of 2.
 192  */
 193 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 194 {
 195         mc->vram_start = base;
 196         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
 197                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 198                 mc->real_vram_size = mc->aper_size;
 199                 mc->mc_vram_size = mc->aper_size;
 200         }
 201         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 202         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
 203                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 204                 mc->real_vram_size = mc->aper_size;
 205                 mc->mc_vram_size = mc->aper_size;
 206         }
 207         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 208         dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 209                         mc->mc_vram_size >> 20, mc->vram_start,
 210                         mc->vram_end, mc->real_vram_size >> 20);
 211 }
 212
 213 /**
 214  * radeon_gtt_location - try to find GTT location
 215  * @rdev: radeon device structure holding all necessary informations
 216  * @mc: memory controller structure holding memory informations
 217  *
 218  * Function will place try to place GTT before or after VRAM.
 219  *
 220  * If GTT size is bigger than space left then we ajust GTT size.
 221  * Thus function will never fails.
 222  *
 223  * FIXME: when reducing GTT size align new size on power of 2.
 224  */
 225 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 226 {
 227         u64 size_af, size_bf;
 228
 229         size_af = 0xFFFFFFFF - mc->vram_end;
 230         size_bf = mc->vram_start;
 231         if (size_bf > size_af) {
 232                 if (mc->gtt_size > size_bf) {
 233                         dev_warn(rdev->dev, "limiting GTT\n");
 234                         mc->gtt_size = size_bf;
 235                 }
 236                 mc->gtt_start = mc->vram_start - mc->gtt_size;
 237         } else {
 238                 if (mc->gtt_size > size_af) {
 239                         dev_warn(rdev->dev, "limiting GTT\n");
 240                         mc->gtt_size = size_af;
 241                 }
 242                 mc->gtt_start = mc->vram_end + 1;
 243         }
 244         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 245         dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
 246                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 247 }
 248
 249 /*
 250  * GPU helpers function.
 251  */
 252 bool radeon_card_posted(struct radeon_device *rdev)
 253 {
 254         uint32_t reg;
 255
 256         /* first check CRTCs */
 257         if (ASIC_IS_DCE4(rdev)) {
 258                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 259                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
 260                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 261                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
 262                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 263                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 264                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 265                         return true;
 266         } else if (ASIC_IS_AVIVO(rdev)) {
 267                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 268                       RREG32(AVIVO_D2CRTC_CONTROL);
 269                 if (reg & AVIVO_CRTC_EN) {
 270                         return true;
 271                 }
 272         } else {
 273                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 274                       RREG32(RADEON_CRTC2_GEN_CNTL);
 275                 if (reg & RADEON_CRTC_EN) {
 276                         return true;
 277                 }
 278         }
 279
 280         /* then check MEM_SIZE, in case the crtcs are off */
 281         if (rdev->family >= CHIP_R600)
 282                 reg = RREG32(R600_CONFIG_MEMSIZE);
 283         else
 284                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 285
 286         if (reg)
 287                 return true;
 288
 289         return false;
 290
 291 }
 292
 293 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 294 {
 295         fixed20_12 a;
 296         u32 sclk, mclk;
 297
 298         if (rdev->flags & RADEON_IS_IGP) {
 299                 sclk = radeon_get_engine_clock(rdev);
 300                 mclk = rdev->clock.default_mclk;
 301
 302                 a.full = dfixed_const(100);
 303                 rdev->pm.sclk.full = dfixed_const(sclk);
 304                 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 305                 rdev->pm.mclk.full = dfixed_const(mclk);
 306                 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 307
 308                 a.full = dfixed_const(16);
 309                 /* core_bandwidth = sclk(Mhz) * 16 */
 310                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 311         } else {
 312                 sclk = radeon_get_engine_clock(rdev);
 313                 mclk = radeon_get_memory_clock(rdev);
 314
 315                 a.full = dfixed_const(100);
 316                 rdev->pm.sclk.full = dfixed_const(sclk);
 317                 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 318                 rdev->pm.mclk.full = dfixed_const(mclk);
 319                 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 320         }
 321 }
 322
 323 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 324 {
 325         if (radeon_card_posted(rdev))
 326                 return true;
 327
 328         if (rdev->bios) {
 329                 DRM_INFO("GPU not posted. posting now...\n");
 330                 if (rdev->is_atom_bios)
 331                         atom_asic_init(rdev->mode_info.atom_context);
 332                 else
 333                         radeon_combios_asic_init(rdev->ddev);
 334                 return true;
 335         } else {
 336                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 337                 return false;
 338         }
 339 }
 340
 341 int radeon_dummy_page_init(struct radeon_device *rdev)
 342 {
 343         if (rdev->dummy_page.page)
 344                 return 0;
 345         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 346         if (rdev->dummy_page.page == NULL)
 347                 return -ENOMEM;
 348         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 349                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 350         if (!rdev->dummy_page.addr) {
 351                 __free_page(rdev->dummy_page.page);
 352                 rdev->dummy_page.page = NULL;
 353                 return -ENOMEM;
 354         }
 355         return 0;
 356 }
 357
 358 void radeon_dummy_page_fini(struct radeon_device *rdev)
 359 {
 360         if (rdev->dummy_page.page == NULL)
 361                 return;
 362         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 363                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 364         __free_page(rdev->dummy_page.page);
 365         rdev->dummy_page.page = NULL;
 366 }
 367
 368
 369 /* ATOM accessor methods */
 370 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 371 {
 372         struct radeon_device *rdev = info->dev->dev_private;
 373         uint32_t r;
 374
 375         r = rdev->pll_rreg(rdev, reg);
 376         return r;
 377 }
 378
 379 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 380 {
 381         struct radeon_device *rdev = info->dev->dev_private;
 382
 383         rdev->pll_wreg(rdev, reg, val);
 384 }
 385
 386 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 387 {
 388         struct radeon_device *rdev = info->dev->dev_private;
 389         uint32_t r;
 390
 391         r = rdev->mc_rreg(rdev, reg);
 392         return r;
 393 }
 394
 395 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 396 {
 397         struct radeon_device *rdev = info->dev->dev_private;
 398
 399         rdev->mc_wreg(rdev, reg, val);
 400 }
 401
 402 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 403 {
 404         struct radeon_device *rdev = info->dev->dev_private;
 405
 406         WREG32(reg*4, val);
 407 }
 408
 409 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 410 {
 411         struct radeon_device *rdev = info->dev->dev_private;
 412         uint32_t r;
 413
 414         r = RREG32(reg*4);
 415         return r;
 416 }
 417
 418 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 419 {
 420         struct radeon_device *rdev = info->dev->dev_private;
 421
 422         WREG32_IO(reg*4, val);
 423 }
 424
 425 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 426 {
 427         struct radeon_device *rdev = info->dev->dev_private;
 428         uint32_t r;
 429
 430         r = RREG32_IO(reg*4);
 431         return r;
 432 }
 433
 434 int radeon_atombios_init(struct radeon_device *rdev)
 435 {
 436         struct card_info *atom_card_info =
 437             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 438
 439         if (!atom_card_info)
 440                 return -ENOMEM;
 441
 442         rdev->mode_info.atom_card_info = atom_card_info;
 443         atom_card_info->dev = rdev->ddev;
 444         atom_card_info->reg_read = cail_reg_read;
 445         atom_card_info->reg_write = cail_reg_write;
 446         /* needed for iio ops */
 447         if (rdev->rio_mem) {
 448                 atom_card_info->ioreg_read = cail_ioreg_read;
 449                 atom_card_info->ioreg_write = cail_ioreg_write;
 450         } else {
 451                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 452                 atom_card_info->ioreg_read = cail_reg_read;
 453                 atom_card_info->ioreg_write = cail_reg_write;
 454         }
 455         atom_card_info->mc_read = cail_mc_read;
 456         atom_card_info->mc_write = cail_mc_write;
 457         atom_card_info->pll_read = cail_pll_read;
 458         atom_card_info->pll_write = cail_pll_write;
 459
 460         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 461         mutex_init(&rdev->mode_info.atom_context->mutex);
 462         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 463         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 464         return 0;
 465 }
 466
 467 void radeon_atombios_fini(struct radeon_device *rdev)
 468 {
 469         if (rdev->mode_info.atom_context) {
 470                 kfree(rdev->mode_info.atom_context->scratch);
 471                 kfree(rdev->mode_info.atom_context);
 472         }
 473         kfree(rdev->mode_info.atom_card_info);
 474 }
 475
 476 int radeon_combios_init(struct radeon_device *rdev)
 477 {
 478         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 479         return 0;
 480 }
 481
 482 void radeon_combios_fini(struct radeon_device *rdev)
 483 {
 484 }
 485
 486 /* if we get transitioned to only one device, tak VGA back */
 487 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 488 {
 489         struct radeon_device *rdev = cookie;
 490         radeon_vga_set_state(rdev, state);
 491         if (state)
 492                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 493                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 494         else
 495                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 496 }
 497
 498 void radeon_check_arguments(struct radeon_device *rdev)
 499 {
 500         /* vramlimit must be a power of two */
 501         switch (radeon_vram_limit) {
 502         case 0:
 503         case 4:
 504         case 8:
 505         case 16:
 506         case 32:
 507         case 64:
 508         case 128:
 509         case 256:
 510         case 512:
 511         case 1024:
 512         case 2048:
 513         case 4096:
 514                 break;
 515         default:
 516                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 517                                 radeon_vram_limit);
 518                 radeon_vram_limit = 0;
 519                 break;
 520         }
 521         radeon_vram_limit = radeon_vram_limit << 20;
 522         /* gtt size must be power of two and greater or equal to 32M */
 523         switch (radeon_gart_size) {
 524         case 4:
 525         case 8:
 526         case 16:
 527                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
 528                                 radeon_gart_size);
 529                 radeon_gart_size = 512;
 530                 break;
 531         case 32:
 532         case 64:
 533         case 128:
 534         case 256:
 535         case 512:
 536         case 1024:
 537         case 2048:
 538         case 4096:
 539                 break;
 540         default:
 541                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 542                                 radeon_gart_size);
 543                 radeon_gart_size = 512;
 544                 break;
 545         }
 546         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 547         /* AGP mode can only be -1, 1, 2, 4, 8 */
 548         switch (radeon_agpmode) {
 549         case -1:
 550         case 0:
 551         case 1:
 552         case 2:
 553         case 4:
 554         case 8:
 555                 break;
 556         default:
 557                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 558                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 559                 radeon_agpmode = 0;
 560                 break;
 561         }
 562 }
 563
 564 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 565 {
 566         struct drm_device *dev = pci_get_drvdata(pdev);
 567         struct radeon_device *rdev = dev->dev_private;
 568         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 569         if (state == VGA_SWITCHEROO_ON) {
 570                 printk(KERN_INFO "radeon: switched on\n");
 571                 /* don't suspend or resume card normally */
 572                 rdev->powered_down = false;
 573                 radeon_resume_kms(dev);
 574                 drm_kms_helper_poll_enable(dev);
 575         } else {
 576                 printk(KERN_INFO "radeon: switched off\n");
 577                 drm_kms_helper_poll_disable(dev);
 578                 radeon_suspend_kms(dev, pmm);
 579                 /* don't suspend or resume card normally */
 580                 rdev->powered_down = true;
 581         }
 582 }
 583
 584 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 585 {
 586         struct drm_device *dev = pci_get_drvdata(pdev);
 587         bool can_switch;
 588
 589         spin_lock(&dev->count_lock);
 590         can_switch = (dev->open_count == 0);
 591         spin_unlock(&dev->count_lock);
 592         return can_switch;
 593 }
 594
 595
 596 int radeon_device_init(struct radeon_device *rdev,
 597                        struct drm_device *ddev,
 598                        struct pci_dev *pdev,
 599                        uint32_t flags)
 600 {
 601         int r, i;
 602         int dma_bits;
 603
 604         rdev->shutdown = false;
 605         rdev->dev = &pdev->dev;
 606         rdev->ddev = ddev;
 607         rdev->pdev = pdev;
 608         rdev->flags = flags;
 609         rdev->family = flags & RADEON_FAMILY_MASK;
 610         rdev->is_atom_bios = false;
 611         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 612         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 613         rdev->gpu_lockup = false;
 614         rdev->accel_working = false;
 615
 616         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
 617                 radeon_family_name[rdev->family], pdev->vendor, pdev->device);
 618
 619         /* mutex initialization are all done here so we
 620          * can recall function without having locking issues */
 621         mutex_init(&rdev->cs_mutex);
 622         mutex_init(&rdev->ib_pool.mutex);
 623         mutex_init(&rdev->cp.mutex);
 624         mutex_init(&rdev->dc_hw_i2c_mutex);
 625         if (rdev->family >= CHIP_R600)
 626                 spin_lock_init(&rdev->ih.lock);
 627         mutex_init(&rdev->gem.mutex);
 628         mutex_init(&rdev->pm.mutex);
 629         mutex_init(&rdev->vram_mutex);
 630         rwlock_init(&rdev->fence_drv.lock);
 631         INIT_LIST_HEAD(&rdev->gem.objects);
 632         init_waitqueue_head(&rdev->irq.vblank_queue);
 633         init_waitqueue_head(&rdev->irq.idle_queue);
 634
 635         /* setup workqueue */
 636         rdev->wq = create_workqueue("radeon");
 637         if (rdev->wq == NULL)
 638                 return -ENOMEM;
 639
 640         /* Set asic functions */
 641         r = radeon_asic_init(rdev);
 642         if (r)
 643                 return r;
 644         radeon_check_arguments(rdev);
 645
 646         /* all of the newer IGP chips have an internal gart
 647          * However some rs4xx report as AGP, so remove that here.
 648          */
 649         if ((rdev->family >= CHIP_RS400) &&
 650             (rdev->flags & RADEON_IS_IGP)) {
 651                 rdev->flags &= ~RADEON_IS_AGP;
 652         }
 653
 654         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 655                 radeon_agp_disable(rdev);
 656         }
 657
 658         /* set DMA mask + need_dma32 flags.
 659          * PCIE - can handle 40-bits.
 660          * IGP - can handle 40-bits (in theory)
 661          * AGP - generally dma32 is safest
 662          * PCI - only dma32
 663          */
 664         rdev->need_dma32 = false;
 665         if (rdev->flags & RADEON_IS_AGP)
 666                 rdev->need_dma32 = true;
 667         if (rdev->flags & RADEON_IS_PCI)
 668                 rdev->need_dma32 = true;
 669
 670         dma_bits = rdev->need_dma32 ? 32 : 40;
 671         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 672         if (r) {
 673                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 674         }
 675
 676         /* Registers mapping */
 677         /* TODO: block userspace mapping of io register */
 678         rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
 679         rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
 680         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 681         if (rdev->rmmio == NULL) {
 682                 return -ENOMEM;
 683         }
 684         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 685         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 686
 687         /* io port mapping */
 688         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 689                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
 690                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
 691                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
 692                         break;
 693                 }
 694         }
 695         if (rdev->rio_mem == NULL)
 696                 DRM_ERROR("Unable to find PCI I/O BAR\n");
 697
 698         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
 699         /* this will fail for cards that aren't VGA class devices, just
 700          * ignore it */
 701         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 702         vga_switcheroo_register_client(rdev->pdev,
 703                                        radeon_switcheroo_set_state,
 704                                        radeon_switcheroo_can_switch);
 705
 706         r = radeon_init(rdev);
 707         if (r)
 708                 return r;
 709
 710         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 711                 /* Acceleration not working on AGP card try again
 712                  * with fallback to PCI or PCIE GART
 713                  */
 714                 radeon_asic_reset(rdev);
 715                 radeon_fini(rdev);
 716                 radeon_agp_disable(rdev);
 717                 r = radeon_init(rdev);
 718                 if (r)
 719                         return r;
 720         }
 721         if (radeon_testing) {
 722                 radeon_test_moves(rdev);
 723         }
 724         if (radeon_benchmarking) {
 725                 radeon_benchmark(rdev);
 726         }
 727         return 0;
 728 }
 729
 730 void radeon_device_fini(struct radeon_device *rdev)
 731 {
 732         DRM_INFO("radeon: finishing device.\n");
 733         rdev->shutdown = true;
 734         /* evict vram memory */
 735         radeon_bo_evict_vram(rdev);
 736         radeon_fini(rdev);
 737         destroy_workqueue(rdev->wq);
 738         vga_switcheroo_unregister_client(rdev->pdev);
 739         vga_client_register(rdev->pdev, NULL, NULL, NULL);
 740         pci_iounmap(rdev->pdev, rdev->rio_mem);
 741         rdev->rio_mem = NULL;
 742         iounmap(rdev->rmmio);
 743         rdev->rmmio = NULL;
 744 }
 745
 746
 747 /*
 748  * Suspend & resume.
 749  */
 750 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 751 {
 752         struct radeon_device *rdev;
 753         struct drm_crtc *crtc;
 754         struct drm_connector *connector;
 755         int r;
 756
 757         if (dev == NULL || dev->dev_private == NULL) {
 758                 return -ENODEV;
 759         }
 760         if (state.event == PM_EVENT_PRETHAW) {
 761                 return 0;
 762         }
 763         rdev = dev->dev_private;
 764
 765         if (rdev->powered_down)
 766                 return 0;
 767
 768         /* turn off display hw */
 769         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 770                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
 771         }
 772
 773         /* unpin the front buffers */
 774         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 775                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 776                 struct radeon_bo *robj;
 777
 778                 if (rfb == NULL || rfb->obj == NULL) {
 779                         continue;
 780                 }
 781                 robj = rfb->obj->driver_private;
 782                 /* don't unpin kernel fb objects */
 783                 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
 784                         r = radeon_bo_reserve(robj, false);
 785                         if (r == 0) {
 786                                 radeon_bo_unpin(robj);
 787                                 radeon_bo_unreserve(robj);
 788                         }
 789                 }
 790         }
 791         /* evict vram memory */
 792         radeon_bo_evict_vram(rdev);
 793         /* wait for gpu to finish processing current batch */
 794         radeon_fence_wait_last(rdev);
 795
 796         radeon_save_bios_scratch_regs(rdev);
 797
 798         radeon_pm_suspend(rdev);
 799         radeon_suspend(rdev);
 800         radeon_hpd_fini(rdev);
 801         /* evict remaining vram memory */
 802         radeon_bo_evict_vram(rdev);
 803
 804         radeon_agp_suspend(rdev);
 805
 806         pci_save_state(dev->pdev);
 807         if (state.event == PM_EVENT_SUSPEND) {
 808                 /* Shut down the device */
 809                 pci_disable_device(dev->pdev);
 810                 pci_set_power_state(dev->pdev, PCI_D3hot);
 811         }
 812         acquire_console_sem();
 813         radeon_fbdev_set_suspend(rdev, 1);
 814         release_console_sem();
 815         return 0;
 816 }
 817
 818 int radeon_resume_kms(struct drm_device *dev)
 819 {
 820         struct drm_connector *connector;
 821         struct radeon_device *rdev = dev->dev_private;
 822
 823         if (rdev->powered_down)
 824                 return 0;
 825
 826         acquire_console_sem();
 827         pci_set_power_state(dev->pdev, PCI_D0);
 828         pci_restore_state(dev->pdev);
 829         if (pci_enable_device(dev->pdev)) {
 830                 release_console_sem();
 831                 return -1;
 832         }
 833         pci_set_master(dev->pdev);
 834         /* resume AGP if in use */
 835         radeon_agp_resume(rdev);
 836         radeon_resume(rdev);
 837         radeon_pm_resume(rdev);
 838         radeon_restore_bios_scratch_regs(rdev);
 839
 840         /* turn on display hw */
 841         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 842                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
 843         }
 844
 845         radeon_fbdev_set_suspend(rdev, 0);
 846         release_console_sem();
 847
 848         /* reset hpd state */
 849         radeon_hpd_init(rdev);
 850         /* blat the mode back in */
 851         drm_helper_resume_force_mode(dev);
 852         return 0;
 853 }
 854
 855 int radeon_gpu_reset(struct radeon_device *rdev)
 856 {
 857         int r;
 858
 859         radeon_save_bios_scratch_regs(rdev);
 860         radeon_suspend(rdev);
 861
 862         r = radeon_asic_reset(rdev);
 863         if (!r) {
 864                 dev_info(rdev->dev, "GPU reset succeed\n");
 865                 radeon_resume(rdev);
 866                 radeon_restore_bios_scratch_regs(rdev);
 867                 drm_helper_resume_force_mode(rdev->ddev);
 868                 return 0;
 869         }
 870         /* bad news, how to tell it to userspace ? */
 871         dev_info(rdev->dev, "GPU reset failed\n");
 872         return r;
 873 }
 874
 875
 876 /*
 877  * Debugfs
 878  */
 879 struct radeon_debugfs {
 880         struct drm_info_list    *files;
 881         unsigned                num_files;
 882 };
 883 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 884 static unsigned _radeon_debugfs_count = 0;
 885
 886 int radeon_debugfs_add_files(struct radeon_device *rdev,
 887                              struct drm_info_list *files,
 888                              unsigned nfiles)
 889 {
 890         unsigned i;
 891
 892         for (i = 0; i < _radeon_debugfs_count; i++) {
 893                 if (_radeon_debugfs[i].files == files) {
 894                         /* Already registered */
 895                         return 0;
 896                 }
 897         }
 898         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 899                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 900                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
 901                 return -EINVAL;
 902         }
 903         _radeon_debugfs[_radeon_debugfs_count].files = files;
 904         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
 905         _radeon_debugfs_count++;
 906 #if defined(CONFIG_DEBUG_FS)
 907         drm_debugfs_create_files(files, nfiles,
 908                                  rdev->ddev->control->debugfs_root,
 909                                  rdev->ddev->control);
 910         drm_debugfs_create_files(files, nfiles,
 911                                  rdev->ddev->primary->debugfs_root,
 912                                  rdev->ddev->primary);
 913 #endif
 914         return 0;
 915 }
 916
 917 #if defined(CONFIG_DEBUG_FS)
 918 int radeon_debugfs_init(struct drm_minor *minor)
 919 {
 920         return 0;
 921 }
 922
 923 void radeon_debugfs_cleanup(struct drm_minor *minor)
 924 {
 925         unsigned i;
 926
 927         for (i = 0; i < _radeon_debugfs_count; i++) {
 928                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
 929                                          _radeon_debugfs[i].num_files, minor);
 930         }
 931 }
 932 #endif