drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
 460         if (edid == NULL)
 461                 return false;
 462
 463         memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
 464
 465         if (!drm_edid_is_valid(edid)) {
 466                 kfree(edid);
 467                 return false;
 468         }
 469
 470         rdev->mode_info.bios_hardcoded_edid = edid;
 471         return true;
 472 }
 473
 474 struct edid *
 475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
 476 {
 477         if (rdev->mode_info.bios_hardcoded_edid)
 478                 return rdev->mode_info.bios_hardcoded_edid;
 479         return NULL;
 480 }
 481
 482 /* standard i2c gpio lines */
 483 #define RADEON_I2C_MONID_ID 0
 484 #define RADEON_I2C_DVI_ID   1
 485 #define RADEON_I2C_VGA_ID   2
 486 #define RADEON_I2C_CRT2_ID  3
 487 #define RADEON_I2C_MM_ID    4
 488 /* custom defined gpio lines */
 489 #define RADEON_I2C_LCD_ID   5 /* ddc for laptop panels */
 490 #define RADEON_I2C_GPIO_ID  6 /* rs4xx gpio ddc */
 491 #define RADEON_I2C_DVO_ID   7 /* i2c bus for dvo */
 492
 493 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 494                                                        int ddc_line)
 495 {
 496         struct radeon_i2c_bus_rec i2c;
 497
 498         if (ddc_line == RADEON_GPIOPAD_MASK) {
 499                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 500                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 501                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 502                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 503                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 504                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 505                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 506                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 507         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 508                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 509                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 510                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 511                 i2c.a_data_reg = RADEON_MDGPIO_A;
 512                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 513                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 514                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 515                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 516         } else {
 517                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 518                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 519                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 520                 i2c.a_data_mask = RADEON_GPIO_A_0;
 521                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 522                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 523                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 524                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 525
 526                 i2c.mask_clk_reg = ddc_line;
 527                 i2c.mask_data_reg = ddc_line;
 528                 i2c.a_clk_reg = ddc_line;
 529                 i2c.a_data_reg = ddc_line;
 530                 i2c.en_clk_reg = ddc_line;
 531                 i2c.en_data_reg = ddc_line;
 532                 i2c.y_clk_reg = ddc_line;
 533                 i2c.y_data_reg = ddc_line;
 534         }
 535
 536         switch (rdev->family) {
 537         case CHIP_R100:
 538         case CHIP_RV100:
 539         case CHIP_RS100:
 540         case CHIP_RV200:
 541         case CHIP_RS200:
 542         case CHIP_RS300:
 543                 switch (ddc_line) {
 544                 case RADEON_GPIO_DVI_DDC:
 545                         i2c.hw_capable = true;
 546                         break;
 547                 default:
 548                         i2c.hw_capable = false;
 549                         break;
 550                 }
 551                 break;
 552         case CHIP_R200:
 553                 switch (ddc_line) {
 554                 case RADEON_GPIO_DVI_DDC:
 555                 case RADEON_GPIO_MONID:
 556                         i2c.hw_capable = true;
 557                         break;
 558                 default:
 559                         i2c.hw_capable = false;
 560                         break;
 561                 }
 562                 break;
 563         case CHIP_RV250:
 564         case CHIP_RV280:
 565                 switch (ddc_line) {
 566                 case RADEON_GPIO_VGA_DDC:
 567                 case RADEON_GPIO_DVI_DDC:
 568                 case RADEON_GPIO_CRT2_DDC:
 569                         i2c.hw_capable = true;
 570                         break;
 571                 default:
 572                         i2c.hw_capable = false;
 573                         break;
 574                 }
 575                 break;
 576         case CHIP_R300:
 577         case CHIP_R350:
 578                 switch (ddc_line) {
 579                 case RADEON_GPIO_VGA_DDC:
 580                 case RADEON_GPIO_DVI_DDC:
 581                         i2c.hw_capable = true;
 582                         break;
 583                 default:
 584                         i2c.hw_capable = false;
 585                         break;
 586                 }
 587                 break;
 588         case CHIP_RV350:
 589         case CHIP_RV380:
 590         case CHIP_RS400:
 591         case CHIP_RS480:
 592                 switch (ddc_line) {
 593                 case RADEON_GPIO_VGA_DDC:
 594                 case RADEON_GPIO_DVI_DDC:
 595                         i2c.hw_capable = true;
 596                         break;
 597                 case RADEON_GPIO_MONID:
 598                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 599                          * reliably on some pre-r4xx hardware; not sure why.
 600                          */
 601                         i2c.hw_capable = false;
 602                         break;
 603                 default:
 604                         i2c.hw_capable = false;
 605                         break;
 606                 }
 607                 break;
 608         default:
 609                 i2c.hw_capable = false;
 610                 break;
 611         }
 612         i2c.mm_i2c = false;
 613
 614         switch (ddc_line) {
 615         case RADEON_GPIO_MONID:
 616                 i2c.i2c_id = RADEON_I2C_MONID_ID;
 617                 break;
 618         case RADEON_GPIO_DVI_DDC:
 619                 i2c.i2c_id = RADEON_I2C_DVI_ID;
 620                 break;
 621         case RADEON_GPIO_VGA_DDC:
 622                 i2c.i2c_id = RADEON_I2C_VGA_ID;
 623                 break;
 624         case RADEON_GPIO_CRT2_DDC:
 625                 i2c.i2c_id = RADEON_I2C_CRT2_ID;
 626                 break;
 627         default:
 628                 i2c.i2c_id = 0xff;
 629                 break;
 630         }
 631         i2c.hpd = RADEON_HPD_NONE;
 632
 633         if (ddc_line)
 634                 i2c.valid = true;
 635         else
 636                 i2c.valid = false;
 637
 638         return i2c;
 639 }
 640
 641 void radeon_combios_i2c_init(struct radeon_device *rdev)
 642 {
 643         struct drm_device *dev = rdev->ddev;
 644         struct radeon_i2c_bus_rec i2c;
 645
 646         i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
 647         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "MONID");
 648
 649         i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
 650         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 651
 652         i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
 653         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 654
 655         i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
 656         rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 657
 658         i2c.valid = true;
 659         i2c.hw_capable = true;
 660         i2c.mm_i2c = true;
 661         i2c.i2c_id = RADEON_I2C_MM_ID;
 662         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 663 }
 664
 665 bool radeon_combios_get_clock_info(struct drm_device *dev)
 666 {
 667         struct radeon_device *rdev = dev->dev_private;
 668         uint16_t pll_info;
 669         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 670         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 671         struct radeon_pll *spll = &rdev->clock.spll;
 672         struct radeon_pll *mpll = &rdev->clock.mpll;
 673         int8_t rev;
 674         uint16_t sclk, mclk;
 675
 676         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 677         if (pll_info) {
 678                 rev = RBIOS8(pll_info);
 679
 680                 /* pixel clocks */
 681                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 682                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 683                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 684                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 685                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 686                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 687
 688                 if (rev > 9) {
 689                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 690                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 691                 } else {
 692                         p1pll->pll_in_min = 40;
 693                         p1pll->pll_in_max = 500;
 694                 }
 695                 *p2pll = *p1pll;
 696
 697                 /* system clock */
 698                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 699                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 700                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 701                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 702
 703                 if (rev > 10) {
 704                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 705                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 706                 } else {
 707                         /* ??? */
 708                         spll->pll_in_min = 40;
 709                         spll->pll_in_max = 500;
 710                 }
 711
 712                 /* memory clock */
 713                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 714                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 715                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 716                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 717
 718                 if (rev > 10) {
 719                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 720                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 721                 } else {
 722                         /* ??? */
 723                         mpll->pll_in_min = 40;
 724                         mpll->pll_in_max = 500;
 725                 }
 726
 727                 /* default sclk/mclk */
 728                 sclk = RBIOS16(pll_info + 0xa);
 729                 mclk = RBIOS16(pll_info + 0x8);
 730                 if (sclk == 0)
 731                         sclk = 200 * 100;
 732                 if (mclk == 0)
 733                         mclk = 200 * 100;
 734
 735                 rdev->clock.default_sclk = sclk;
 736                 rdev->clock.default_mclk = mclk;
 737
 738                 return true;
 739         }
 740         return false;
 741 }
 742
 743 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 744 {
 745         struct drm_device *dev = rdev->ddev;
 746         u16 igp_info;
 747
 748         /* sideport is AMD only */
 749         if (rdev->family == CHIP_RS400)
 750                 return false;
 751
 752         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 753
 754         if (igp_info) {
 755                 if (RBIOS16(igp_info + 0x4))
 756                         return true;
 757         }
 758         return false;
 759 }
 760
 761 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 762         0x00000808,             /* r100  */
 763         0x00000808,             /* rv100 */
 764         0x00000808,             /* rs100 */
 765         0x00000808,             /* rv200 */
 766         0x00000808,             /* rs200 */
 767         0x00000808,             /* r200  */
 768         0x00000808,             /* rv250 */
 769         0x00000000,             /* rs300 */
 770         0x00000808,             /* rv280 */
 771         0x00000808,             /* r300  */
 772         0x00000808,             /* r350  */
 773         0x00000808,             /* rv350 */
 774         0x00000808,             /* rv380 */
 775         0x00000808,             /* r420  */
 776         0x00000808,             /* r423  */
 777         0x00000808,             /* rv410 */
 778         0x00000000,             /* rs400 */
 779         0x00000000,             /* rs480 */
 780 };
 781
 782 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 783                                                           struct radeon_encoder_primary_dac *p_dac)
 784 {
 785         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 786         return;
 787 }
 788
 789 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 790                                                                        radeon_encoder
 791                                                                        *encoder)
 792 {
 793         struct drm_device *dev = encoder->base.dev;
 794         struct radeon_device *rdev = dev->dev_private;
 795         uint16_t dac_info;
 796         uint8_t rev, bg, dac;
 797         struct radeon_encoder_primary_dac *p_dac = NULL;
 798         int found = 0;
 799
 800         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 801                         GFP_KERNEL);
 802
 803         if (!p_dac)
 804                 return NULL;
 805
 806         /* check CRT table */
 807         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 808         if (dac_info) {
 809                 rev = RBIOS8(dac_info) & 0x3;
 810                 if (rev < 2) {
 811                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 812                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 813                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 814                 } else {
 815                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 816                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 817                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 818                 }
 819                 /* if the values are all zeros, use the table */
 820                 if (p_dac->ps2_pdac_adj)
 821                         found = 1;
 822         }
 823
 824         if (!found) /* fallback to defaults */
 825                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 826
 827         return p_dac;
 828 }
 829
 830 enum radeon_tv_std
 831 radeon_combios_get_tv_info(struct radeon_device *rdev)
 832 {
 833         struct drm_device *dev = rdev->ddev;
 834         uint16_t tv_info;
 835         enum radeon_tv_std tv_std = TV_STD_NTSC;
 836
 837         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 838         if (tv_info) {
 839                 if (RBIOS8(tv_info + 6) == 'T') {
 840                         switch (RBIOS8(tv_info + 7) & 0xf) {
 841                         case 1:
 842                                 tv_std = TV_STD_NTSC;
 843                                 DRM_INFO("Default TV standard: NTSC\n");
 844                                 break;
 845                         case 2:
 846                                 tv_std = TV_STD_PAL;
 847                                 DRM_INFO("Default TV standard: PAL\n");
 848                                 break;
 849                         case 3:
 850                                 tv_std = TV_STD_PAL_M;
 851                                 DRM_INFO("Default TV standard: PAL-M\n");
 852                                 break;
 853                         case 4:
 854                                 tv_std = TV_STD_PAL_60;
 855                                 DRM_INFO("Default TV standard: PAL-60\n");
 856                                 break;
 857                         case 5:
 858                                 tv_std = TV_STD_NTSC_J;
 859                                 DRM_INFO("Default TV standard: NTSC-J\n");
 860                                 break;
 861                         case 6:
 862                                 tv_std = TV_STD_SCART_PAL;
 863                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 864                                 break;
 865                         default:
 866                                 tv_std = TV_STD_NTSC;
 867                                 DRM_INFO
 868                                     ("Unknown TV standard; defaulting to NTSC\n");
 869                                 break;
 870                         }
 871
 872                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 873                         case 0:
 874                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 875                                 break;
 876                         case 1:
 877                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 878                                 break;
 879                         case 2:
 880                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 881                                 break;
 882                         case 3:
 883                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 884                                 break;
 885                         default:
 886                                 break;
 887                         }
 888                 }
 889         }
 890         return tv_std;
 891 }
 892
 893 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 894         0x00000000,             /* r100  */
 895         0x00280000,             /* rv100 */
 896         0x00000000,             /* rs100 */
 897         0x00880000,             /* rv200 */
 898         0x00000000,             /* rs200 */
 899         0x00000000,             /* r200  */
 900         0x00770000,             /* rv250 */
 901         0x00290000,             /* rs300 */
 902         0x00560000,             /* rv280 */
 903         0x00780000,             /* r300  */
 904         0x00770000,             /* r350  */
 905         0x00780000,             /* rv350 */
 906         0x00780000,             /* rv380 */
 907         0x01080000,             /* r420  */
 908         0x01080000,             /* r423  */
 909         0x01080000,             /* rv410 */
 910         0x00780000,             /* rs400 */
 911         0x00780000,             /* rs480 */
 912 };
 913
 914 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 915                                                      struct radeon_encoder_tv_dac *tv_dac)
 916 {
 917         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 918         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 919                 tv_dac->ps2_tvdac_adj = 0x00880000;
 920         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 921         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 922         return;
 923 }
 924
 925 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 926                                                              radeon_encoder
 927                                                              *encoder)
 928 {
 929         struct drm_device *dev = encoder->base.dev;
 930         struct radeon_device *rdev = dev->dev_private;
 931         uint16_t dac_info;
 932         uint8_t rev, bg, dac;
 933         struct radeon_encoder_tv_dac *tv_dac = NULL;
 934         int found = 0;
 935
 936         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 937         if (!tv_dac)
 938                 return NULL;
 939
 940         /* first check TV table */
 941         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 942         if (dac_info) {
 943                 rev = RBIOS8(dac_info + 0x3);
 944                 if (rev > 4) {
 945                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 946                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 947                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 948
 949                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 950                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 951                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 952
 953                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 954                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 955                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 956                         /* if the values are all zeros, use the table */
 957                         if (tv_dac->ps2_tvdac_adj)
 958                                 found = 1;
 959                 } else if (rev > 1) {
 960                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 961                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 962                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 963
 964                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 965                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 966                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 967
 968                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 969                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 970                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 971                         /* if the values are all zeros, use the table */
 972                         if (tv_dac->ps2_tvdac_adj)
 973                                 found = 1;
 974                 }
 975                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
 976         }
 977         if (!found) {
 978                 /* then check CRT table */
 979                 dac_info =
 980                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 981                 if (dac_info) {
 982                         rev = RBIOS8(dac_info) & 0x3;
 983                         if (rev < 2) {
 984                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 985                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 986                                 tv_dac->ps2_tvdac_adj =
 987                                     (bg << 16) | (dac << 20);
 988                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 989                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 990                                 /* if the values are all zeros, use the table */
 991                                 if (tv_dac->ps2_tvdac_adj)
 992                                         found = 1;
 993                         } else {
 994                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 995                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 996                                 tv_dac->ps2_tvdac_adj =
 997                                     (bg << 16) | (dac << 20);
 998                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 999                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1000                                 /* if the values are all zeros, use the table */
1001                                 if (tv_dac->ps2_tvdac_adj)
1002                                         found = 1;
1003                         }
1004                 } else {
1005                         DRM_INFO("No TV DAC info found in BIOS\n");
1006                 }
1007         }
1008
1009         if (!found) /* fallback to defaults */
1010                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1011
1012         return tv_dac;
1013 }
1014
1015 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1016                                                                          radeon_device
1017                                                                          *rdev)
1018 {
1019         struct radeon_encoder_lvds *lvds = NULL;
1020         uint32_t fp_vert_stretch, fp_horz_stretch;
1021         uint32_t ppll_div_sel, ppll_val;
1022         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1023
1024         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1025
1026         if (!lvds)
1027                 return NULL;
1028
1029         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1030         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1031
1032         /* These should be fail-safe defaults, fingers crossed */
1033         lvds->panel_pwr_delay = 200;
1034         lvds->panel_vcc_delay = 2000;
1035
1036         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1037         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1038         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1039
1040         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1041                 lvds->native_mode.vdisplay =
1042                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1043                      RADEON_VERT_PANEL_SHIFT) + 1;
1044         else
1045                 lvds->native_mode.vdisplay =
1046                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1047
1048         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1049                 lvds->native_mode.hdisplay =
1050                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1051                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1052         else
1053                 lvds->native_mode.hdisplay =
1054                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1055
1056         if ((lvds->native_mode.hdisplay < 640) ||
1057             (lvds->native_mode.vdisplay < 480)) {
1058                 lvds->native_mode.hdisplay = 640;
1059                 lvds->native_mode.vdisplay = 480;
1060         }
1061
1062         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1063         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1064         if ((ppll_val & 0x000707ff) == 0x1bb)
1065                 lvds->use_bios_dividers = false;
1066         else {
1067                 lvds->panel_ref_divider =
1068                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1069                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1070                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1071
1072                 if ((lvds->panel_ref_divider != 0) &&
1073                     (lvds->panel_fb_divider > 3))
1074                         lvds->use_bios_dividers = true;
1075         }
1076         lvds->panel_vcc_delay = 200;
1077
1078         DRM_INFO("Panel info derived from registers\n");
1079         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1080                  lvds->native_mode.vdisplay);
1081
1082         return lvds;
1083 }
1084
1085 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1086                                                          *encoder)
1087 {
1088         struct drm_device *dev = encoder->base.dev;
1089         struct radeon_device *rdev = dev->dev_private;
1090         uint16_t lcd_info;
1091         uint32_t panel_setup;
1092         char stmp[30];
1093         int tmp, i;
1094         struct radeon_encoder_lvds *lvds = NULL;
1095
1096         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1097
1098         if (lcd_info) {
1099                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1100
1101                 if (!lvds)
1102                         return NULL;
1103
1104                 for (i = 0; i < 24; i++)
1105                         stmp[i] = RBIOS8(lcd_info + i + 1);
1106                 stmp[24] = 0;
1107
1108                 DRM_INFO("Panel ID String: %s\n", stmp);
1109
1110                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1111                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1112
1113                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1114                          lvds->native_mode.vdisplay);
1115
1116                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1117                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1118
1119                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1120                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1121                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1122
1123                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1124                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1125                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1126                 if ((lvds->panel_ref_divider != 0) &&
1127                     (lvds->panel_fb_divider > 3))
1128                         lvds->use_bios_dividers = true;
1129
1130                 panel_setup = RBIOS32(lcd_info + 0x39);
1131                 lvds->lvds_gen_cntl = 0xff00;
1132                 if (panel_setup & 0x1)
1133                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1134
1135                 if ((panel_setup >> 4) & 0x1)
1136                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1137
1138                 switch ((panel_setup >> 8) & 0x7) {
1139                 case 0:
1140                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1141                         break;
1142                 case 1:
1143                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1144                         break;
1145                 case 2:
1146                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1147                         break;
1148                 default:
1149                         break;
1150                 }
1151
1152                 if ((panel_setup >> 16) & 0x1)
1153                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1154
1155                 if ((panel_setup >> 17) & 0x1)
1156                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1157
1158                 if ((panel_setup >> 18) & 0x1)
1159                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1160
1161                 if ((panel_setup >> 23) & 0x1)
1162                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1163
1164                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1165
1166                 for (i = 0; i < 32; i++) {
1167                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1168                         if (tmp == 0)
1169                                 break;
1170
1171                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1172                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1173                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1174                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1175                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1176                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1177                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1178                                         (RBIOS8(tmp + 23) * 8);
1179
1180                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1181                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1182                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1183                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1184                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1185                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1186
1187                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1188                                 lvds->native_mode.flags = 0;
1189                                 /* set crtc values */
1190                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1191
1192                         }
1193                 }
1194         } else {
1195                 DRM_INFO("No panel info found in BIOS\n");
1196                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1197         }
1198
1199         if (lvds)
1200                 encoder->native_mode = lvds->native_mode;
1201         return lvds;
1202 }
1203
1204 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1205         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1206         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1207         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1208         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1209         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1210         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1211         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1212         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1213         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1214         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1215         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1216         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1217         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1218         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1219         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1220         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1221         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1222         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1223 };
1224
1225 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1226                                             struct radeon_encoder_int_tmds *tmds)
1227 {
1228         struct drm_device *dev = encoder->base.dev;
1229         struct radeon_device *rdev = dev->dev_private;
1230         int i;
1231
1232         for (i = 0; i < 4; i++) {
1233                 tmds->tmds_pll[i].value =
1234                         default_tmds_pll[rdev->family][i].value;
1235                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1236         }
1237
1238         return true;
1239 }
1240
1241 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1242                                               struct radeon_encoder_int_tmds *tmds)
1243 {
1244         struct drm_device *dev = encoder->base.dev;
1245         struct radeon_device *rdev = dev->dev_private;
1246         uint16_t tmds_info;
1247         int i, n;
1248         uint8_t ver;
1249
1250         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1251
1252         if (tmds_info) {
1253                 ver = RBIOS8(tmds_info);
1254                 DRM_INFO("DFP table revision: %d\n", ver);
1255                 if (ver == 3) {
1256                         n = RBIOS8(tmds_info + 5) + 1;
1257                         if (n > 4)
1258                                 n = 4;
1259                         for (i = 0; i < n; i++) {
1260                                 tmds->tmds_pll[i].value =
1261                                     RBIOS32(tmds_info + i * 10 + 0x08);
1262                                 tmds->tmds_pll[i].freq =
1263                                     RBIOS16(tmds_info + i * 10 + 0x10);
1264                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1265                                           tmds->tmds_pll[i].freq,
1266                                           tmds->tmds_pll[i].value);
1267                         }
1268                 } else if (ver == 4) {
1269                         int stride = 0;
1270                         n = RBIOS8(tmds_info + 5) + 1;
1271                         if (n > 4)
1272                                 n = 4;
1273                         for (i = 0; i < n; i++) {
1274                                 tmds->tmds_pll[i].value =
1275                                     RBIOS32(tmds_info + stride + 0x08);
1276                                 tmds->tmds_pll[i].freq =
1277                                     RBIOS16(tmds_info + stride + 0x10);
1278                                 if (i == 0)
1279                                         stride += 10;
1280                                 else
1281                                         stride += 6;
1282                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1283                                           tmds->tmds_pll[i].freq,
1284                                           tmds->tmds_pll[i].value);
1285                         }
1286                 }
1287         } else {
1288                 DRM_INFO("No TMDS info found in BIOS\n");
1289                 return false;
1290         }
1291         return true;
1292 }
1293
1294 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1295                                                 struct radeon_encoder_ext_tmds *tmds)
1296 {
1297         struct drm_device *dev = encoder->base.dev;
1298         struct radeon_device *rdev = dev->dev_private;
1299         struct radeon_i2c_bus_rec i2c_bus;
1300
1301         /* default for macs */
1302         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1303         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1304
1305         /* XXX some macs have duallink chips */
1306         switch (rdev->mode_info.connector_table) {
1307         case CT_POWERBOOK_EXTERNAL:
1308         case CT_MINI_EXTERNAL:
1309         default:
1310                 tmds->dvo_chip = DVO_SIL164;
1311                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1312                 break;
1313         }
1314
1315         return true;
1316 }
1317
1318 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1319                                                   struct radeon_encoder_ext_tmds *tmds)
1320 {
1321         struct drm_device *dev = encoder->base.dev;
1322         struct radeon_device *rdev = dev->dev_private;
1323         uint16_t offset;
1324         uint8_t ver, id, blocks, clk, data;
1325         int i;
1326         enum radeon_combios_ddc gpio;
1327         struct radeon_i2c_bus_rec i2c_bus;
1328
1329         tmds->i2c_bus = NULL;
1330         if (rdev->flags & RADEON_IS_IGP) {
1331                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1332                 if (offset) {
1333                         ver = RBIOS8(offset);
1334                         DRM_INFO("GPIO Table revision: %d\n", ver);
1335                         blocks = RBIOS8(offset + 2);
1336                         for (i = 0; i < blocks; i++) {
1337                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
1338                                 if (id == 136) {
1339                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
1340                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
1341                                         i2c_bus.valid = true;
1342                                         i2c_bus.mask_clk_mask = (1 << clk);
1343                                         i2c_bus.mask_data_mask = (1 << data);
1344                                         i2c_bus.a_clk_mask = (1 << clk);
1345                                         i2c_bus.a_data_mask = (1 << data);
1346                                         i2c_bus.en_clk_mask = (1 << clk);
1347                                         i2c_bus.en_data_mask = (1 << data);
1348                                         i2c_bus.y_clk_mask = (1 << clk);
1349                                         i2c_bus.y_data_mask = (1 << data);
1350                                         i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1351                                         i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1352                                         i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1353                                         i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1354                                         i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1355                                         i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1356                                         i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1357                                         i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1358                                         i2c_bus.i2c_id = RADEON_I2C_DVO_ID;
1359                                         radeon_i2c_add(rdev, &i2c_bus, "DVO");
1360                                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1361                                         tmds->dvo_chip = DVO_SIL164;
1362                                         tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1363                                         break;
1364                                 }
1365                         }
1366                 }
1367         } else {
1368                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1369                 if (offset) {
1370                         ver = RBIOS8(offset);
1371                         DRM_INFO("External TMDS Table revision: %d\n", ver);
1372                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1373                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1374                         gpio = RBIOS8(offset + 4 + 3);
1375                         switch (gpio) {
1376                         case DDC_MONID:
1377                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1378                                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1379                                 break;
1380                         case DDC_DVI:
1381                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1382                                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1383                                 break;
1384                         case DDC_VGA:
1385                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1386                                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1387                                 break;
1388                         case DDC_CRT2:
1389                                 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1390                                 if (rdev->family >= CHIP_R300)
1391                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1392                                 else
1393                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1394                                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1395                                 break;
1396                         case DDC_LCD: /* MM i2c */
1397                                 i2c_bus.valid = true;
1398                                 i2c_bus.hw_capable = true;
1399                                 i2c_bus.mm_i2c = true;
1400                                 i2c_bus.i2c_id = RADEON_I2C_MM_ID;
1401                                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1402                                 break;
1403                         default:
1404                                 DRM_ERROR("Unsupported gpio %d\n", gpio);
1405                                 break;
1406                         }
1407                 }
1408         }
1409
1410         if (!tmds->i2c_bus) {
1411                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1412                 return false;
1413         }
1414
1415         return true;
1416 }
1417
1418 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1419 {
1420         struct radeon_device *rdev = dev->dev_private;
1421         struct radeon_i2c_bus_rec ddc_i2c;
1422         struct radeon_hpd hpd;
1423
1424         rdev->mode_info.connector_table = radeon_connector_table;
1425         if (rdev->mode_info.connector_table == CT_NONE) {
1426 #ifdef CONFIG_PPC_PMAC
1427                 if (of_machine_is_compatible("PowerBook3,3")) {
1428                         /* powerbook with VGA */
1429                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1430                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1431                            of_machine_is_compatible("PowerBook3,5")) {
1432                         /* powerbook with internal tmds */
1433                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1434                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1435                            of_machine_is_compatible("PowerBook5,2") ||
1436                            of_machine_is_compatible("PowerBook5,3") ||
1437                            of_machine_is_compatible("PowerBook5,4") ||
1438                            of_machine_is_compatible("PowerBook5,5")) {
1439                         /* powerbook with external single link tmds (sil164) */
1440                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1441                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1442                         /* powerbook with external dual or single link tmds */
1443                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1444                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1445                            of_machine_is_compatible("PowerBook5,8") ||
1446                            of_machine_is_compatible("PowerBook5,9")) {
1447                         /* PowerBook6,2 ? */
1448                         /* powerbook with external dual link tmds (sil1178?) */
1449                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1450                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1451                            of_machine_is_compatible("PowerBook4,2") ||
1452                            of_machine_is_compatible("PowerBook4,3") ||
1453                            of_machine_is_compatible("PowerBook6,3") ||
1454                            of_machine_is_compatible("PowerBook6,5") ||
1455                            of_machine_is_compatible("PowerBook6,7")) {
1456                         /* ibook */
1457                         rdev->mode_info.connector_table = CT_IBOOK;
1458                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1459                         /* emac */
1460                         rdev->mode_info.connector_table = CT_EMAC;
1461                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1462                         /* mini with internal tmds */
1463                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1464                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1465                         /* mini with external tmds */
1466                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1467                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1468                         /* PowerMac8,1 ? */
1469                         /* imac g5 isight */
1470                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1471                 } else
1472 #endif /* CONFIG_PPC_PMAC */
1473 #ifdef CONFIG_PPC64
1474                 if (ASIC_IS_RN50(rdev))
1475                         rdev->mode_info.connector_table = CT_RN50_POWER;
1476                 else
1477 #endif
1478                         rdev->mode_info.connector_table = CT_GENERIC;
1479         }
1480
1481         switch (rdev->mode_info.connector_table) {
1482         case CT_GENERIC:
1483                 DRM_INFO("Connector Table: %d (generic)\n",
1484                          rdev->mode_info.connector_table);
1485                 /* these are the most common settings */
1486                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1487                         /* VGA - primary dac */
1488                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1489                         hpd.hpd = RADEON_HPD_NONE;
1490                         radeon_add_legacy_encoder(dev,
1491                                                   radeon_get_encoder_id(dev,
1492                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1493                                                                         1),
1494                                                   ATOM_DEVICE_CRT1_SUPPORT);
1495                         radeon_add_legacy_connector(dev, 0,
1496                                                     ATOM_DEVICE_CRT1_SUPPORT,
1497                                                     DRM_MODE_CONNECTOR_VGA,
1498                                                     &ddc_i2c,
1499                                                     CONNECTOR_OBJECT_ID_VGA,
1500                                                     &hpd);
1501                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1502                         /* LVDS */
1503                         ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1504                         hpd.hpd = RADEON_HPD_NONE;
1505                         radeon_add_legacy_encoder(dev,
1506                                                   radeon_get_encoder_id(dev,
1507                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1508                                                                         0),
1509                                                   ATOM_DEVICE_LCD1_SUPPORT);
1510                         radeon_add_legacy_connector(dev, 0,
1511                                                     ATOM_DEVICE_LCD1_SUPPORT,
1512                                                     DRM_MODE_CONNECTOR_LVDS,
1513                                                     &ddc_i2c,
1514                                                     CONNECTOR_OBJECT_ID_LVDS,
1515                                                     &hpd);
1516
1517                         /* VGA - primary dac */
1518                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1519                         hpd.hpd = RADEON_HPD_NONE;
1520                         radeon_add_legacy_encoder(dev,
1521                                                   radeon_get_encoder_id(dev,
1522                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1523                                                                         1),
1524                                                   ATOM_DEVICE_CRT1_SUPPORT);
1525                         radeon_add_legacy_connector(dev, 1,
1526                                                     ATOM_DEVICE_CRT1_SUPPORT,
1527                                                     DRM_MODE_CONNECTOR_VGA,
1528                                                     &ddc_i2c,
1529                                                     CONNECTOR_OBJECT_ID_VGA,
1530                                                     &hpd);
1531                 } else {
1532                         /* DVI-I - tv dac, int tmds */
1533                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1534                         hpd.hpd = RADEON_HPD_1;
1535                         radeon_add_legacy_encoder(dev,
1536                                                   radeon_get_encoder_id(dev,
1537                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1538                                                                         0),
1539                                                   ATOM_DEVICE_DFP1_SUPPORT);
1540                         radeon_add_legacy_encoder(dev,
1541                                                   radeon_get_encoder_id(dev,
1542                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1543                                                                         2),
1544                                                   ATOM_DEVICE_CRT2_SUPPORT);
1545                         radeon_add_legacy_connector(dev, 0,
1546                                                     ATOM_DEVICE_DFP1_SUPPORT |
1547                                                     ATOM_DEVICE_CRT2_SUPPORT,
1548                                                     DRM_MODE_CONNECTOR_DVII,
1549                                                     &ddc_i2c,
1550                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1551                                                     &hpd);
1552
1553                         /* VGA - primary dac */
1554                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1555                         hpd.hpd = RADEON_HPD_NONE;
1556                         radeon_add_legacy_encoder(dev,
1557                                                   radeon_get_encoder_id(dev,
1558                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1559                                                                         1),
1560                                                   ATOM_DEVICE_CRT1_SUPPORT);
1561                         radeon_add_legacy_connector(dev, 1,
1562                                                     ATOM_DEVICE_CRT1_SUPPORT,
1563                                                     DRM_MODE_CONNECTOR_VGA,
1564                                                     &ddc_i2c,
1565                                                     CONNECTOR_OBJECT_ID_VGA,
1566                                                     &hpd);
1567                 }
1568
1569                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1570                         /* TV - tv dac */
1571                         ddc_i2c.valid = false;
1572                         hpd.hpd = RADEON_HPD_NONE;
1573                         radeon_add_legacy_encoder(dev,
1574                                                   radeon_get_encoder_id(dev,
1575                                                                         ATOM_DEVICE_TV1_SUPPORT,
1576                                                                         2),
1577                                                   ATOM_DEVICE_TV1_SUPPORT);
1578                         radeon_add_legacy_connector(dev, 2,
1579                                                     ATOM_DEVICE_TV1_SUPPORT,
1580                                                     DRM_MODE_CONNECTOR_SVIDEO,
1581                                                     &ddc_i2c,
1582                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1583                                                     &hpd);
1584                 }
1585                 break;
1586         case CT_IBOOK:
1587                 DRM_INFO("Connector Table: %d (ibook)\n",
1588                          rdev->mode_info.connector_table);
1589                 /* LVDS */
1590                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1591                 hpd.hpd = RADEON_HPD_NONE;
1592                 radeon_add_legacy_encoder(dev,
1593                                           radeon_get_encoder_id(dev,
1594                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1595                                                                 0),
1596                                           ATOM_DEVICE_LCD1_SUPPORT);
1597                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1598                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1599                                             CONNECTOR_OBJECT_ID_LVDS,
1600                                             &hpd);
1601                 /* VGA - TV DAC */
1602                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1603                 hpd.hpd = RADEON_HPD_NONE;
1604                 radeon_add_legacy_encoder(dev,
1605                                           radeon_get_encoder_id(dev,
1606                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1607                                                                 2),
1608                                           ATOM_DEVICE_CRT2_SUPPORT);
1609                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1610                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1611                                             CONNECTOR_OBJECT_ID_VGA,
1612                                             &hpd);
1613                 /* TV - TV DAC */
1614                 ddc_i2c.valid = false;
1615                 hpd.hpd = RADEON_HPD_NONE;
1616                 radeon_add_legacy_encoder(dev,
1617                                           radeon_get_encoder_id(dev,
1618                                                                 ATOM_DEVICE_TV1_SUPPORT,
1619                                                                 2),
1620                                           ATOM_DEVICE_TV1_SUPPORT);
1621                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1622                                             DRM_MODE_CONNECTOR_SVIDEO,
1623                                             &ddc_i2c,
1624                                             CONNECTOR_OBJECT_ID_SVIDEO,
1625                                             &hpd);
1626                 break;
1627         case CT_POWERBOOK_EXTERNAL:
1628                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1629                          rdev->mode_info.connector_table);
1630                 /* LVDS */
1631                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1632                 hpd.hpd = RADEON_HPD_NONE;
1633                 radeon_add_legacy_encoder(dev,
1634                                           radeon_get_encoder_id(dev,
1635                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1636                                                                 0),
1637                                           ATOM_DEVICE_LCD1_SUPPORT);
1638                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1639                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1640                                             CONNECTOR_OBJECT_ID_LVDS,
1641                                             &hpd);
1642                 /* DVI-I - primary dac, ext tmds */
1643                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1644                 hpd.hpd = RADEON_HPD_2; /* ??? */
1645                 radeon_add_legacy_encoder(dev,
1646                                           radeon_get_encoder_id(dev,
1647                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1648                                                                 0),
1649                                           ATOM_DEVICE_DFP2_SUPPORT);
1650                 radeon_add_legacy_encoder(dev,
1651                                           radeon_get_encoder_id(dev,
1652                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1653                                                                 1),
1654                                           ATOM_DEVICE_CRT1_SUPPORT);
1655                 /* XXX some are SL */
1656                 radeon_add_legacy_connector(dev, 1,
1657                                             ATOM_DEVICE_DFP2_SUPPORT |
1658                                             ATOM_DEVICE_CRT1_SUPPORT,
1659                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1660                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1661                                             &hpd);
1662                 /* TV - TV DAC */
1663                 ddc_i2c.valid = false;
1664                 hpd.hpd = RADEON_HPD_NONE;
1665                 radeon_add_legacy_encoder(dev,
1666                                           radeon_get_encoder_id(dev,
1667                                                                 ATOM_DEVICE_TV1_SUPPORT,
1668                                                                 2),
1669                                           ATOM_DEVICE_TV1_SUPPORT);
1670                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1671                                             DRM_MODE_CONNECTOR_SVIDEO,
1672                                             &ddc_i2c,
1673                                             CONNECTOR_OBJECT_ID_SVIDEO,
1674                                             &hpd);
1675                 break;
1676         case CT_POWERBOOK_INTERNAL:
1677                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1678                          rdev->mode_info.connector_table);
1679                 /* LVDS */
1680                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1681                 hpd.hpd = RADEON_HPD_NONE;
1682                 radeon_add_legacy_encoder(dev,
1683                                           radeon_get_encoder_id(dev,
1684                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1685                                                                 0),
1686                                           ATOM_DEVICE_LCD1_SUPPORT);
1687                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1688                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1689                                             CONNECTOR_OBJECT_ID_LVDS,
1690                                             &hpd);
1691                 /* DVI-I - primary dac, int tmds */
1692                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1693                 hpd.hpd = RADEON_HPD_1; /* ??? */
1694                 radeon_add_legacy_encoder(dev,
1695                                           radeon_get_encoder_id(dev,
1696                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1697                                                                 0),
1698                                           ATOM_DEVICE_DFP1_SUPPORT);
1699                 radeon_add_legacy_encoder(dev,
1700                                           radeon_get_encoder_id(dev,
1701                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1702                                                                 1),
1703                                           ATOM_DEVICE_CRT1_SUPPORT);
1704                 radeon_add_legacy_connector(dev, 1,
1705                                             ATOM_DEVICE_DFP1_SUPPORT |
1706                                             ATOM_DEVICE_CRT1_SUPPORT,
1707                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1708                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1709                                             &hpd);
1710                 /* TV - TV DAC */
1711                 ddc_i2c.valid = false;
1712                 hpd.hpd = RADEON_HPD_NONE;
1713                 radeon_add_legacy_encoder(dev,
1714                                           radeon_get_encoder_id(dev,
1715                                                                 ATOM_DEVICE_TV1_SUPPORT,
1716                                                                 2),
1717                                           ATOM_DEVICE_TV1_SUPPORT);
1718                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1719                                             DRM_MODE_CONNECTOR_SVIDEO,
1720                                             &ddc_i2c,
1721                                             CONNECTOR_OBJECT_ID_SVIDEO,
1722                                             &hpd);
1723                 break;
1724         case CT_POWERBOOK_VGA:
1725                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1726                          rdev->mode_info.connector_table);
1727                 /* LVDS */
1728                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1729                 hpd.hpd = RADEON_HPD_NONE;
1730                 radeon_add_legacy_encoder(dev,
1731                                           radeon_get_encoder_id(dev,
1732                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1733                                                                 0),
1734                                           ATOM_DEVICE_LCD1_SUPPORT);
1735                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1736                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1737                                             CONNECTOR_OBJECT_ID_LVDS,
1738                                             &hpd);
1739                 /* VGA - primary dac */
1740                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1741                 hpd.hpd = RADEON_HPD_NONE;
1742                 radeon_add_legacy_encoder(dev,
1743                                           radeon_get_encoder_id(dev,
1744                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1745                                                                 1),
1746                                           ATOM_DEVICE_CRT1_SUPPORT);
1747                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1748                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1749                                             CONNECTOR_OBJECT_ID_VGA,
1750                                             &hpd);
1751                 /* TV - TV DAC */
1752                 ddc_i2c.valid = false;
1753                 hpd.hpd = RADEON_HPD_NONE;
1754                 radeon_add_legacy_encoder(dev,
1755                                           radeon_get_encoder_id(dev,
1756                                                                 ATOM_DEVICE_TV1_SUPPORT,
1757                                                                 2),
1758                                           ATOM_DEVICE_TV1_SUPPORT);
1759                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1760                                             DRM_MODE_CONNECTOR_SVIDEO,
1761                                             &ddc_i2c,
1762                                             CONNECTOR_OBJECT_ID_SVIDEO,
1763                                             &hpd);
1764                 break;
1765         case CT_MINI_EXTERNAL:
1766                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1767                          rdev->mode_info.connector_table);
1768                 /* DVI-I - tv dac, ext tmds */
1769                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1770                 hpd.hpd = RADEON_HPD_2; /* ??? */
1771                 radeon_add_legacy_encoder(dev,
1772                                           radeon_get_encoder_id(dev,
1773                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1774                                                                 0),
1775                                           ATOM_DEVICE_DFP2_SUPPORT);
1776                 radeon_add_legacy_encoder(dev,
1777                                           radeon_get_encoder_id(dev,
1778                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1779                                                                 2),
1780                                           ATOM_DEVICE_CRT2_SUPPORT);
1781                 /* XXX are any DL? */
1782                 radeon_add_legacy_connector(dev, 0,
1783                                             ATOM_DEVICE_DFP2_SUPPORT |
1784                                             ATOM_DEVICE_CRT2_SUPPORT,
1785                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1786                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1787                                             &hpd);
1788                 /* TV - TV DAC */
1789                 ddc_i2c.valid = false;
1790                 hpd.hpd = RADEON_HPD_NONE;
1791                 radeon_add_legacy_encoder(dev,
1792                                           radeon_get_encoder_id(dev,
1793                                                                 ATOM_DEVICE_TV1_SUPPORT,
1794                                                                 2),
1795                                           ATOM_DEVICE_TV1_SUPPORT);
1796                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1797                                             DRM_MODE_CONNECTOR_SVIDEO,
1798                                             &ddc_i2c,
1799                                             CONNECTOR_OBJECT_ID_SVIDEO,
1800                                             &hpd);
1801                 break;
1802         case CT_MINI_INTERNAL:
1803                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1804                          rdev->mode_info.connector_table);
1805                 /* DVI-I - tv dac, int tmds */
1806                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1807                 hpd.hpd = RADEON_HPD_1; /* ??? */
1808                 radeon_add_legacy_encoder(dev,
1809                                           radeon_get_encoder_id(dev,
1810                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1811                                                                 0),
1812                                           ATOM_DEVICE_DFP1_SUPPORT);
1813                 radeon_add_legacy_encoder(dev,
1814                                           radeon_get_encoder_id(dev,
1815                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1816                                                                 2),
1817                                           ATOM_DEVICE_CRT2_SUPPORT);
1818                 radeon_add_legacy_connector(dev, 0,
1819                                             ATOM_DEVICE_DFP1_SUPPORT |
1820                                             ATOM_DEVICE_CRT2_SUPPORT,
1821                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1822                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1823                                             &hpd);
1824                 /* TV - TV DAC */
1825                 ddc_i2c.valid = false;
1826                 hpd.hpd = RADEON_HPD_NONE;
1827                 radeon_add_legacy_encoder(dev,
1828                                           radeon_get_encoder_id(dev,
1829                                                                 ATOM_DEVICE_TV1_SUPPORT,
1830                                                                 2),
1831                                           ATOM_DEVICE_TV1_SUPPORT);
1832                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1833                                             DRM_MODE_CONNECTOR_SVIDEO,
1834                                             &ddc_i2c,
1835                                             CONNECTOR_OBJECT_ID_SVIDEO,
1836                                             &hpd);
1837                 break;
1838         case CT_IMAC_G5_ISIGHT:
1839                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1840                          rdev->mode_info.connector_table);
1841                 /* DVI-D - int tmds */
1842                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1843                 hpd.hpd = RADEON_HPD_1; /* ??? */
1844                 radeon_add_legacy_encoder(dev,
1845                                           radeon_get_encoder_id(dev,
1846                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1847                                                                 0),
1848                                           ATOM_DEVICE_DFP1_SUPPORT);
1849                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1850                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1851                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1852                                             &hpd);
1853                 /* VGA - tv dac */
1854                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1855                 hpd.hpd = RADEON_HPD_NONE;
1856                 radeon_add_legacy_encoder(dev,
1857                                           radeon_get_encoder_id(dev,
1858                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1859                                                                 2),
1860                                           ATOM_DEVICE_CRT2_SUPPORT);
1861                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1862                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1863                                             CONNECTOR_OBJECT_ID_VGA,
1864                                             &hpd);
1865                 /* TV - TV DAC */
1866                 ddc_i2c.valid = false;
1867                 hpd.hpd = RADEON_HPD_NONE;
1868                 radeon_add_legacy_encoder(dev,
1869                                           radeon_get_encoder_id(dev,
1870                                                                 ATOM_DEVICE_TV1_SUPPORT,
1871                                                                 2),
1872                                           ATOM_DEVICE_TV1_SUPPORT);
1873                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1874                                             DRM_MODE_CONNECTOR_SVIDEO,
1875                                             &ddc_i2c,
1876                                             CONNECTOR_OBJECT_ID_SVIDEO,
1877                                             &hpd);
1878                 break;
1879         case CT_EMAC:
1880                 DRM_INFO("Connector Table: %d (emac)\n",
1881                          rdev->mode_info.connector_table);
1882                 /* VGA - primary dac */
1883                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1884                 hpd.hpd = RADEON_HPD_NONE;
1885                 radeon_add_legacy_encoder(dev,
1886                                           radeon_get_encoder_id(dev,
1887                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1888                                                                 1),
1889                                           ATOM_DEVICE_CRT1_SUPPORT);
1890                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1891                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1892                                             CONNECTOR_OBJECT_ID_VGA,
1893                                             &hpd);
1894                 /* VGA - tv dac */
1895                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1896                 hpd.hpd = RADEON_HPD_NONE;
1897                 radeon_add_legacy_encoder(dev,
1898                                           radeon_get_encoder_id(dev,
1899                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1900                                                                 2),
1901                                           ATOM_DEVICE_CRT2_SUPPORT);
1902                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1903                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1904                                             CONNECTOR_OBJECT_ID_VGA,
1905                                             &hpd);
1906                 /* TV - TV DAC */
1907                 ddc_i2c.valid = false;
1908                 hpd.hpd = RADEON_HPD_NONE;
1909                 radeon_add_legacy_encoder(dev,
1910                                           radeon_get_encoder_id(dev,
1911                                                                 ATOM_DEVICE_TV1_SUPPORT,
1912                                                                 2),
1913                                           ATOM_DEVICE_TV1_SUPPORT);
1914                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1915                                             DRM_MODE_CONNECTOR_SVIDEO,
1916                                             &ddc_i2c,
1917                                             CONNECTOR_OBJECT_ID_SVIDEO,
1918                                             &hpd);
1919                 break;
1920         case CT_RN50_POWER:
1921                 DRM_INFO("Connector Table: %d (rn50-power)\n",
1922                          rdev->mode_info.connector_table);
1923                 /* VGA - primary dac */
1924                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1925                 hpd.hpd = RADEON_HPD_NONE;
1926                 radeon_add_legacy_encoder(dev,
1927                                           radeon_get_encoder_id(dev,
1928                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1929                                                                 1),
1930                                           ATOM_DEVICE_CRT1_SUPPORT);
1931                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1932                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1933                                             CONNECTOR_OBJECT_ID_VGA,
1934                                             &hpd);
1935                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1936                 hpd.hpd = RADEON_HPD_NONE;
1937                 radeon_add_legacy_encoder(dev,
1938                                           radeon_get_encoder_id(dev,
1939                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1940                                                                 2),
1941                                           ATOM_DEVICE_CRT2_SUPPORT);
1942                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1943                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1944                                             CONNECTOR_OBJECT_ID_VGA,
1945                                             &hpd);
1946                 break;
1947         default:
1948                 DRM_INFO("Connector table: %d (invalid)\n",
1949                          rdev->mode_info.connector_table);
1950                 return false;
1951         }
1952
1953         radeon_link_encoder_connector(dev);
1954
1955         return true;
1956 }
1957
1958 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1959                                        int bios_index,
1960                                        enum radeon_combios_connector
1961                                        *legacy_connector,
1962                                        struct radeon_i2c_bus_rec *ddc_i2c,
1963                                        struct radeon_hpd *hpd)
1964 {
1965         struct radeon_device *rdev = dev->dev_private;
1966
1967         /* XPRESS DDC quirks */
1968         if ((rdev->family == CHIP_RS400 ||
1969              rdev->family == CHIP_RS480) &&
1970             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1971                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1972         else if ((rdev->family == CHIP_RS400 ||
1973                   rdev->family == CHIP_RS480) &&
1974                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1975                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1976                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1977                 ddc_i2c->mask_data_mask = 0x80;
1978                 ddc_i2c->a_clk_mask = (0x20 << 8);
1979                 ddc_i2c->a_data_mask = 0x80;
1980                 ddc_i2c->en_clk_mask = (0x20 << 8);
1981                 ddc_i2c->en_data_mask = 0x80;
1982                 ddc_i2c->y_clk_mask = (0x20 << 8);
1983                 ddc_i2c->y_data_mask = 0x80;
1984                 ddc_i2c->i2c_id = RADEON_I2C_GPIO_ID;
1985                 radeon_i2c_add(rdev, ddc_i2c, "GPIO_DDC");
1986         }
1987
1988         /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1989         if ((rdev->family >= CHIP_R300) &&
1990             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1991                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1992
1993         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1994            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1995         if (dev->pdev->device == 0x515e &&
1996             dev->pdev->subsystem_vendor == 0x1014) {
1997                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1998                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1999                         return false;
2000         }
2001
2002         /* X300 card with extra non-existent DVI port */
2003         if (dev->pdev->device == 0x5B60 &&
2004             dev->pdev->subsystem_vendor == 0x17af &&
2005             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2006                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2007                         return false;
2008         }
2009
2010         return true;
2011 }
2012
2013 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2014 {
2015         /* Acer 5102 has non-existent TV port */
2016         if (dev->pdev->device == 0x5975 &&
2017             dev->pdev->subsystem_vendor == 0x1025 &&
2018             dev->pdev->subsystem_device == 0x009f)
2019                 return false;
2020
2021         /* HP dc5750 has non-existent TV port */
2022         if (dev->pdev->device == 0x5974 &&
2023             dev->pdev->subsystem_vendor == 0x103c &&
2024             dev->pdev->subsystem_device == 0x280a)
2025                 return false;
2026
2027         /* MSI S270 has non-existent TV port */
2028         if (dev->pdev->device == 0x5955 &&
2029             dev->pdev->subsystem_vendor == 0x1462 &&
2030             dev->pdev->subsystem_device == 0x0131)
2031                 return false;
2032
2033         return true;
2034 }
2035
2036 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2037 {
2038         struct radeon_device *rdev = dev->dev_private;
2039         uint32_t ext_tmds_info;
2040
2041         if (rdev->flags & RADEON_IS_IGP) {
2042                 if (is_dvi_d)
2043                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2044                 else
2045                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2046         }
2047         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2048         if (ext_tmds_info) {
2049                 uint8_t rev = RBIOS8(ext_tmds_info);
2050                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2051                 if (rev >= 3) {
2052                         if (is_dvi_d)
2053                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2054                         else
2055                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2056                 } else {
2057                         if (flags & 1) {
2058                                 if (is_dvi_d)
2059                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2060                                 else
2061                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2062                         }
2063                 }
2064         }
2065         if (is_dvi_d)
2066                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2067         else
2068                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2069 }
2070
2071 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2072 {
2073         struct radeon_device *rdev = dev->dev_private;
2074         uint32_t conn_info, entry, devices;
2075         uint16_t tmp, connector_object_id;
2076         enum radeon_combios_ddc ddc_type;
2077         enum radeon_combios_connector connector;
2078         int i = 0;
2079         struct radeon_i2c_bus_rec ddc_i2c;
2080         struct radeon_hpd hpd;
2081
2082         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2083         if (conn_info) {
2084                 for (i = 0; i < 4; i++) {
2085                         entry = conn_info + 2 + i * 2;
2086
2087                         if (!RBIOS16(entry))
2088                                 break;
2089
2090                         tmp = RBIOS16(entry);
2091
2092                         connector = (tmp >> 12) & 0xf;
2093
2094                         ddc_type = (tmp >> 8) & 0xf;
2095                         switch (ddc_type) {
2096                         case DDC_MONID:
2097                                 ddc_i2c =
2098                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2099                                 break;
2100                         case DDC_DVI:
2101                                 ddc_i2c =
2102                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2103                                 break;
2104                         case DDC_VGA:
2105                                 ddc_i2c =
2106                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2107                                 break;
2108                         case DDC_CRT2:
2109                                 ddc_i2c =
2110                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2111                                 break;
2112                         default:
2113                                 ddc_i2c.valid = false;
2114                                 break;
2115                         }
2116
2117                         switch (connector) {
2118                         case CONNECTOR_PROPRIETARY_LEGACY:
2119                         case CONNECTOR_DVI_I_LEGACY:
2120                         case CONNECTOR_DVI_D_LEGACY:
2121                                 if ((tmp >> 4) & 0x1)
2122                                         hpd.hpd = RADEON_HPD_2;
2123                                 else
2124                                         hpd.hpd = RADEON_HPD_1;
2125                                 break;
2126                         default:
2127                                 hpd.hpd = RADEON_HPD_NONE;
2128                                 break;
2129                         }
2130
2131                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2132                                                         &ddc_i2c, &hpd))
2133                                 continue;
2134
2135                         switch (connector) {
2136                         case CONNECTOR_PROPRIETARY_LEGACY:
2137                                 if ((tmp >> 4) & 0x1)
2138                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2139                                 else
2140                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2141                                 radeon_add_legacy_encoder(dev,
2142                                                           radeon_get_encoder_id
2143                                                           (dev, devices, 0),
2144                                                           devices);
2145                                 radeon_add_legacy_connector(dev, i, devices,
2146                                                             legacy_connector_convert
2147                                                             [connector],
2148                                                             &ddc_i2c,
2149                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2150                                                             &hpd);
2151                                 break;
2152                         case CONNECTOR_CRT_LEGACY:
2153                                 if (tmp & 0x1) {
2154                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2155                                         radeon_add_legacy_encoder(dev,
2156                                                                   radeon_get_encoder_id
2157                                                                   (dev,
2158                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2159                                                                    2),
2160                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2161                                 } else {
2162                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2163                                         radeon_add_legacy_encoder(dev,
2164                                                                   radeon_get_encoder_id
2165                                                                   (dev,
2166                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2167                                                                    1),
2168                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2169                                 }
2170                                 radeon_add_legacy_connector(dev,
2171                                                             i,
2172                                                             devices,
2173                                                             legacy_connector_convert
2174                                                             [connector],
2175                                                             &ddc_i2c,
2176                                                             CONNECTOR_OBJECT_ID_VGA,
2177                                                             &hpd);
2178                                 break;
2179                         case CONNECTOR_DVI_I_LEGACY:
2180                                 devices = 0;
2181                                 if (tmp & 0x1) {
2182                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2183                                         radeon_add_legacy_encoder(dev,
2184                                                                   radeon_get_encoder_id
2185                                                                   (dev,
2186                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2187                                                                    2),
2188                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2189                                 } else {
2190                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2191                                         radeon_add_legacy_encoder(dev,
2192                                                                   radeon_get_encoder_id
2193                                                                   (dev,
2194                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2195                                                                    1),
2196                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2197                                 }
2198                                 if ((tmp >> 4) & 0x1) {
2199                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2200                                         radeon_add_legacy_encoder(dev,
2201                                                                   radeon_get_encoder_id
2202                                                                   (dev,
2203                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2204                                                                    0),
2205                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2206                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2207                                 } else {
2208                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2209                                         radeon_add_legacy_encoder(dev,
2210                                                                   radeon_get_encoder_id
2211                                                                   (dev,
2212                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2213                                                                    0),
2214                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2215                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2216                                 }
2217                                 radeon_add_legacy_connector(dev,
2218                                                             i,
2219                                                             devices,
2220                                                             legacy_connector_convert
2221                                                             [connector],
2222                                                             &ddc_i2c,
2223                                                             connector_object_id,
2224                                                             &hpd);
2225                                 break;
2226                         case CONNECTOR_DVI_D_LEGACY:
2227                                 if ((tmp >> 4) & 0x1) {
2228                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2229                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2230                                 } else {
2231                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2232                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2233                                 }
2234                                 radeon_add_legacy_encoder(dev,
2235                                                           radeon_get_encoder_id
2236                                                           (dev, devices, 0),
2237                                                           devices);
2238                                 radeon_add_legacy_connector(dev, i, devices,
2239                                                             legacy_connector_convert
2240                                                             [connector],
2241                                                             &ddc_i2c,
2242                                                             connector_object_id,
2243                                                             &hpd);
2244                                 break;
2245                         case CONNECTOR_CTV_LEGACY:
2246                         case CONNECTOR_STV_LEGACY:
2247                                 radeon_add_legacy_encoder(dev,
2248                                                           radeon_get_encoder_id
2249                                                           (dev,
2250                                                            ATOM_DEVICE_TV1_SUPPORT,
2251                                                            2),
2252                                                           ATOM_DEVICE_TV1_SUPPORT);
2253                                 radeon_add_legacy_connector(dev, i,
2254                                                             ATOM_DEVICE_TV1_SUPPORT,
2255                                                             legacy_connector_convert
2256                                                             [connector],
2257                                                             &ddc_i2c,
2258                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2259                                                             &hpd);
2260                                 break;
2261                         default:
2262                                 DRM_ERROR("Unknown connector type: %d\n",
2263                                           connector);
2264                                 continue;
2265                         }
2266
2267                 }
2268         } else {
2269                 uint16_t tmds_info =
2270                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2271                 if (tmds_info) {
2272                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2273
2274                         radeon_add_legacy_encoder(dev,
2275                                                   radeon_get_encoder_id(dev,
2276                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2277                                                                         1),
2278                                                   ATOM_DEVICE_CRT1_SUPPORT);
2279                         radeon_add_legacy_encoder(dev,
2280                                                   radeon_get_encoder_id(dev,
2281                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2282                                                                         0),
2283                                                   ATOM_DEVICE_DFP1_SUPPORT);
2284
2285                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2286                         hpd.hpd = RADEON_HPD_1;
2287                         radeon_add_legacy_connector(dev,
2288                                                     0,
2289                                                     ATOM_DEVICE_CRT1_SUPPORT |
2290                                                     ATOM_DEVICE_DFP1_SUPPORT,
2291                                                     DRM_MODE_CONNECTOR_DVII,
2292                                                     &ddc_i2c,
2293                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2294                                                     &hpd);
2295                 } else {
2296                         uint16_t crt_info =
2297                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2298                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2299                         if (crt_info) {
2300                                 radeon_add_legacy_encoder(dev,
2301                                                           radeon_get_encoder_id(dev,
2302                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2303                                                                                 1),
2304                                                           ATOM_DEVICE_CRT1_SUPPORT);
2305                                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2306                                 hpd.hpd = RADEON_HPD_NONE;
2307                                 radeon_add_legacy_connector(dev,
2308                                                             0,
2309                                                             ATOM_DEVICE_CRT1_SUPPORT,
2310                                                             DRM_MODE_CONNECTOR_VGA,
2311                                                             &ddc_i2c,
2312                                                             CONNECTOR_OBJECT_ID_VGA,
2313                                                             &hpd);
2314                         } else {
2315                                 DRM_DEBUG_KMS("No connector info found\n");
2316                                 return false;
2317                         }
2318                 }
2319         }
2320
2321         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2322                 uint16_t lcd_info =
2323                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2324                 if (lcd_info) {
2325                         uint16_t lcd_ddc_info =
2326                             combios_get_table_offset(dev,
2327                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2328
2329                         radeon_add_legacy_encoder(dev,
2330                                                   radeon_get_encoder_id(dev,
2331                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2332                                                                         0),
2333                                                   ATOM_DEVICE_LCD1_SUPPORT);
2334
2335                         if (lcd_ddc_info) {
2336                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2337                                 switch (ddc_type) {
2338                                 case DDC_MONID:
2339                                         ddc_i2c =
2340                                             combios_setup_i2c_bus
2341                                                 (rdev, RADEON_GPIO_MONID);
2342                                         break;
2343                                 case DDC_DVI:
2344                                         ddc_i2c =
2345                                             combios_setup_i2c_bus
2346                                                 (rdev, RADEON_GPIO_DVI_DDC);
2347                                         break;
2348                                 case DDC_VGA:
2349                                         ddc_i2c =
2350                                             combios_setup_i2c_bus
2351                                                 (rdev, RADEON_GPIO_VGA_DDC);
2352                                         break;
2353                                 case DDC_CRT2:
2354                                         ddc_i2c =
2355                                             combios_setup_i2c_bus
2356                                                 (rdev, RADEON_GPIO_CRT2_DDC);
2357                                         break;
2358                                 case DDC_LCD:
2359                                         ddc_i2c =
2360                                             combios_setup_i2c_bus
2361                                                 (rdev, RADEON_GPIOPAD_MASK);
2362                                         ddc_i2c.mask_clk_mask =
2363                                             RBIOS32(lcd_ddc_info + 3);
2364                                         ddc_i2c.mask_data_mask =
2365                                             RBIOS32(lcd_ddc_info + 7);
2366                                         ddc_i2c.a_clk_mask =
2367                                             RBIOS32(lcd_ddc_info + 3);
2368                                         ddc_i2c.a_data_mask =
2369                                             RBIOS32(lcd_ddc_info + 7);
2370                                         ddc_i2c.en_clk_mask =
2371                                             RBIOS32(lcd_ddc_info + 3);
2372                                         ddc_i2c.en_data_mask =
2373                                             RBIOS32(lcd_ddc_info + 7);
2374                                         ddc_i2c.y_clk_mask =
2375                                             RBIOS32(lcd_ddc_info + 3);
2376                                         ddc_i2c.y_data_mask =
2377                                             RBIOS32(lcd_ddc_info + 7);
2378                                         ddc_i2c.i2c_id = RADEON_I2C_LCD_ID;
2379                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2380                                         break;
2381                                 case DDC_GPIO:
2382                                         ddc_i2c =
2383                                             combios_setup_i2c_bus
2384                                                 (rdev, RADEON_MDGPIO_MASK);
2385                                         ddc_i2c.mask_clk_mask =
2386                                             RBIOS32(lcd_ddc_info + 3);
2387                                         ddc_i2c.mask_data_mask =
2388                                             RBIOS32(lcd_ddc_info + 7);
2389                                         ddc_i2c.a_clk_mask =
2390                                             RBIOS32(lcd_ddc_info + 3);
2391                                         ddc_i2c.a_data_mask =
2392                                             RBIOS32(lcd_ddc_info + 7);
2393                                         ddc_i2c.en_clk_mask =
2394                                             RBIOS32(lcd_ddc_info + 3);
2395                                         ddc_i2c.en_data_mask =
2396                                             RBIOS32(lcd_ddc_info + 7);
2397                                         ddc_i2c.y_clk_mask =
2398                                             RBIOS32(lcd_ddc_info + 3);
2399                                         ddc_i2c.y_data_mask =
2400                                             RBIOS32(lcd_ddc_info + 7);
2401                                         ddc_i2c.i2c_id = RADEON_I2C_LCD_ID;
2402                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2403                                         break;
2404                                 default:
2405                                         ddc_i2c.valid = false;
2406                                         break;
2407                                 }
2408                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2409                         } else
2410                                 ddc_i2c.valid = false;
2411
2412                         hpd.hpd = RADEON_HPD_NONE;
2413                         radeon_add_legacy_connector(dev,
2414                                                     5,
2415                                                     ATOM_DEVICE_LCD1_SUPPORT,
2416                                                     DRM_MODE_CONNECTOR_LVDS,
2417                                                     &ddc_i2c,
2418                                                     CONNECTOR_OBJECT_ID_LVDS,
2419                                                     &hpd);
2420                 }
2421         }
2422
2423         /* check TV table */
2424         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2425                 uint32_t tv_info =
2426                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2427                 if (tv_info) {
2428                         if (RBIOS8(tv_info + 6) == 'T') {
2429                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2430                                         hpd.hpd = RADEON_HPD_NONE;
2431                                         ddc_i2c.valid = false;
2432                                         radeon_add_legacy_encoder(dev,
2433                                                                   radeon_get_encoder_id
2434                                                                   (dev,
2435                                                                    ATOM_DEVICE_TV1_SUPPORT,
2436                                                                    2),
2437                                                                   ATOM_DEVICE_TV1_SUPPORT);
2438                                         radeon_add_legacy_connector(dev, 6,
2439                                                                     ATOM_DEVICE_TV1_SUPPORT,
2440                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2441                                                                     &ddc_i2c,
2442                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2443                                                                     &hpd);
2444                                 }
2445                         }
2446                 }
2447         }
2448
2449         radeon_link_encoder_connector(dev);
2450
2451         return true;
2452 }
2453
2454 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2455 {
2456         struct drm_device *dev = rdev->ddev;
2457         u16 offset, misc, misc2 = 0;
2458         u8 rev, blocks, tmp;
2459         int state_index = 0;
2460
2461         rdev->pm.default_power_state_index = -1;
2462
2463         if (rdev->flags & RADEON_IS_MOBILITY) {
2464                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2465                 if (offset) {
2466                         rev = RBIOS8(offset);
2467                         blocks = RBIOS8(offset + 0x2);
2468                         /* power mode 0 tends to be the only valid one */
2469                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2470                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2471                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2472                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2473                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2474                                 goto default_mode;
2475                         rdev->pm.power_state[state_index].type =
2476                                 POWER_STATE_TYPE_BATTERY;
2477                         misc = RBIOS16(offset + 0x5 + 0x0);
2478                         if (rev > 4)
2479                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2480                         rdev->pm.power_state[state_index].misc = misc;
2481                         rdev->pm.power_state[state_index].misc2 = misc2;
2482                         if (misc & 0x4) {
2483                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2484                                 if (misc & 0x8)
2485                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2486                                                 true;
2487                                 else
2488                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2489                                                 false;
2490                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2491                                 if (rev < 6) {
2492                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2493                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2494                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2495                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2496                                 } else {
2497                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2498                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2499                                         if (entries && voltage_table_offset) {
2500                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2501                                                         RBIOS16(voltage_table_offset) * 4;
2502                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2503                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2504                                         } else
2505                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2506                                 }
2507                                 switch ((misc2 & 0x700) >> 8) {
2508                                 case 0:
2509                                 default:
2510                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2511                                         break;
2512                                 case 1:
2513                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2514                                         break;
2515                                 case 2:
2516                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2517                                         break;
2518                                 case 3:
2519                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2520                                         break;
2521                                 case 4:
2522                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2523                                         break;
2524                                 }
2525                         } else
2526                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2527                         if (rev > 6)
2528                                 rdev->pm.power_state[state_index].pcie_lanes =
2529                                         RBIOS8(offset + 0x5 + 0x10);
2530                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2531                         state_index++;
2532                 } else {
2533                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2534                 }
2535         } else {
2536                 /* XXX figure out some good default low power mode for desktop cards */
2537         }
2538
2539 default_mode:
2540         /* add the default mode */
2541         rdev->pm.power_state[state_index].type =
2542                 POWER_STATE_TYPE_DEFAULT;
2543         rdev->pm.power_state[state_index].num_clock_modes = 1;
2544         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2545         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2546         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2547         if ((state_index > 0) &&
2548             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2549                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2550                         rdev->pm.power_state[0].clock_info[0].voltage;
2551         else
2552                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2553         rdev->pm.power_state[state_index].pcie_lanes = 16;
2554         rdev->pm.power_state[state_index].flags = 0;
2555         rdev->pm.default_power_state_index = state_index;
2556         rdev->pm.num_power_states = state_index + 1;
2557
2558         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2559         rdev->pm.current_clock_mode_index = 0;
2560 }
2561
2562 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2563 {
2564         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2565         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2566
2567         if (!tmds)
2568                 return;
2569
2570         switch (tmds->dvo_chip) {
2571         case DVO_SIL164:
2572                 /* sil 164 */
2573                 radeon_i2c_put_byte(tmds->i2c_bus,
2574                                     tmds->slave_addr,
2575                                     0x08, 0x30);
2576                 radeon_i2c_put_byte(tmds->i2c_bus,
2577                                        tmds->slave_addr,
2578                                        0x09, 0x00);
2579                 radeon_i2c_put_byte(tmds->i2c_bus,
2580                                     tmds->slave_addr,
2581                                     0x0a, 0x90);
2582                 radeon_i2c_put_byte(tmds->i2c_bus,
2583                                     tmds->slave_addr,
2584                                     0x0c, 0x89);
2585                 radeon_i2c_put_byte(tmds->i2c_bus,
2586                                        tmds->slave_addr,
2587                                        0x08, 0x3b);
2588                 break;
2589         case DVO_SIL1178:
2590                 /* sil 1178 - untested */
2591                 /*
2592                  * 0x0f, 0x44
2593                  * 0x0f, 0x4c
2594                  * 0x0e, 0x01
2595                  * 0x0a, 0x80
2596                  * 0x09, 0x30
2597                  * 0x0c, 0xc9
2598                  * 0x0d, 0x70
2599                  * 0x08, 0x32
2600                  * 0x08, 0x33
2601                  */
2602                 break;
2603         default:
2604                 break;
2605         }
2606
2607 }
2608
2609 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2610 {
2611         struct drm_device *dev = encoder->dev;
2612         struct radeon_device *rdev = dev->dev_private;
2613         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2614         uint16_t offset;
2615         uint8_t blocks, slave_addr, rev;
2616         uint32_t index, id;
2617         uint32_t reg, val, and_mask, or_mask;
2618         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2619
2620         if (!tmds)
2621                 return false;
2622
2623         if (rdev->flags & RADEON_IS_IGP) {
2624                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2625                 rev = RBIOS8(offset);
2626                 if (offset) {
2627                         rev = RBIOS8(offset);
2628                         if (rev > 1) {
2629                                 blocks = RBIOS8(offset + 3);
2630                                 index = offset + 4;
2631                                 while (blocks > 0) {
2632                                         id = RBIOS16(index);
2633                                         index += 2;
2634                                         switch (id >> 13) {
2635                                         case 0:
2636                                                 reg = (id & 0x1fff) * 4;
2637                                                 val = RBIOS32(index);
2638                                                 index += 4;
2639                                                 WREG32(reg, val);
2640                                                 break;
2641                                         case 2:
2642                                                 reg = (id & 0x1fff) * 4;
2643                                                 and_mask = RBIOS32(index);
2644                                                 index += 4;
2645                                                 or_mask = RBIOS32(index);
2646                                                 index += 4;
2647                                                 val = RREG32(reg);
2648                                                 val = (val & and_mask) | or_mask;
2649                                                 WREG32(reg, val);
2650                                                 break;
2651                                         case 3:
2652                                                 val = RBIOS16(index);
2653                                                 index += 2;
2654                                                 udelay(val);
2655                                                 break;
2656                                         case 4:
2657                                                 val = RBIOS16(index);
2658                                                 index += 2;
2659                                                 udelay(val * 1000);
2660                                                 break;
2661                                         case 6:
2662                                                 slave_addr = id & 0xff;
2663                                                 slave_addr >>= 1; /* 7 bit addressing */
2664                                                 index++;
2665                                                 reg = RBIOS8(index);
2666                                                 index++;
2667                                                 val = RBIOS8(index);
2668                                                 index++;
2669                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2670                                                                     slave_addr,
2671                                                                     reg, val);
2672                                                 break;
2673                                         default:
2674                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2675                                                 break;
2676                                         }
2677                                         blocks--;
2678                                 }
2679                                 return true;
2680                         }
2681                 }
2682         } else {
2683                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2684                 if (offset) {
2685                         index = offset + 10;
2686                         id = RBIOS16(index);
2687                         while (id != 0xffff) {
2688                                 index += 2;
2689                                 switch (id >> 13) {
2690                                 case 0:
2691                                         reg = (id & 0x1fff) * 4;
2692                                         val = RBIOS32(index);
2693                                         WREG32(reg, val);
2694                                         break;
2695                                 case 2:
2696                                         reg = (id & 0x1fff) * 4;
2697                                         and_mask = RBIOS32(index);
2698                                         index += 4;
2699                                         or_mask = RBIOS32(index);
2700                                         index += 4;
2701                                         val = RREG32(reg);
2702                                         val = (val & and_mask) | or_mask;
2703                                         WREG32(reg, val);
2704                                         break;
2705                                 case 4:
2706                                         val = RBIOS16(index);
2707                                         index += 2;
2708                                         udelay(val);
2709                                         break;
2710                                 case 5:
2711                                         reg = id & 0x1fff;
2712                                         and_mask = RBIOS32(index);
2713                                         index += 4;
2714                                         or_mask = RBIOS32(index);
2715                                         index += 4;
2716                                         val = RREG32_PLL(reg);
2717                                         val = (val & and_mask) | or_mask;
2718                                         WREG32_PLL(reg, val);
2719                                         break;
2720                                 case 6:
2721                                         reg = id & 0x1fff;
2722                                         val = RBIOS8(index);
2723                                         index += 1;
2724                                         radeon_i2c_put_byte(tmds->i2c_bus,
2725                                                             tmds->slave_addr,
2726                                                             reg, val);
2727                                         break;
2728                                 default:
2729                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2730                                         break;
2731                                 }
2732                                 id = RBIOS16(index);
2733                         }
2734                         return true;
2735                 }
2736         }
2737         return false;
2738 }
2739
2740 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2741 {
2742         struct radeon_device *rdev = dev->dev_private;
2743
2744         if (offset) {
2745                 while (RBIOS16(offset)) {
2746                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2747                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2748                         uint32_t val, and_mask, or_mask;
2749                         uint32_t tmp;
2750
2751                         offset += 2;
2752                         switch (cmd) {
2753                         case 0:
2754                                 val = RBIOS32(offset);
2755                                 offset += 4;
2756                                 WREG32(addr, val);
2757                                 break;
2758                         case 1:
2759                                 val = RBIOS32(offset);
2760                                 offset += 4;
2761                                 WREG32(addr, val);
2762                                 break;
2763                         case 2:
2764                                 and_mask = RBIOS32(offset);
2765                                 offset += 4;
2766                                 or_mask = RBIOS32(offset);
2767                                 offset += 4;
2768                                 tmp = RREG32(addr);
2769                                 tmp &= and_mask;
2770                                 tmp |= or_mask;
2771                                 WREG32(addr, tmp);
2772                                 break;
2773                         case 3:
2774                                 and_mask = RBIOS32(offset);
2775                                 offset += 4;
2776                                 or_mask = RBIOS32(offset);
2777                                 offset += 4;
2778                                 tmp = RREG32(addr);
2779                                 tmp &= and_mask;
2780                                 tmp |= or_mask;
2781                                 WREG32(addr, tmp);
2782                                 break;
2783                         case 4:
2784                                 val = RBIOS16(offset);
2785                                 offset += 2;
2786                                 udelay(val);
2787                                 break;
2788                         case 5:
2789                                 val = RBIOS16(offset);
2790                                 offset += 2;
2791                                 switch (addr) {
2792                                 case 8:
2793                                         while (val--) {
2794                                                 if (!
2795                                                     (RREG32_PLL
2796                                                      (RADEON_CLK_PWRMGT_CNTL) &
2797                                                      RADEON_MC_BUSY))
2798                                                         break;
2799                                         }
2800                                         break;
2801                                 case 9:
2802                                         while (val--) {
2803                                                 if ((RREG32(RADEON_MC_STATUS) &
2804                                                      RADEON_MC_IDLE))
2805                                                         break;
2806                                         }
2807                                         break;
2808                                 default:
2809                                         break;
2810                                 }
2811                                 break;
2812                         default:
2813                                 break;
2814                         }
2815                 }
2816         }
2817 }
2818
2819 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2820 {
2821         struct radeon_device *rdev = dev->dev_private;
2822
2823         if (offset) {
2824                 while (RBIOS8(offset)) {
2825                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2826                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2827                         uint32_t val, shift, tmp;
2828                         uint32_t and_mask, or_mask;
2829
2830                         offset++;
2831                         switch (cmd) {
2832                         case 0:
2833                                 val = RBIOS32(offset);
2834                                 offset += 4;
2835                                 WREG32_PLL(addr, val);
2836                                 break;
2837                         case 1:
2838                                 shift = RBIOS8(offset) * 8;
2839                                 offset++;
2840                                 and_mask = RBIOS8(offset) << shift;
2841                                 and_mask |= ~(0xff << shift);
2842                                 offset++;
2843                                 or_mask = RBIOS8(offset) << shift;
2844                                 offset++;
2845                                 tmp = RREG32_PLL(addr);
2846                                 tmp &= and_mask;
2847                                 tmp |= or_mask;
2848                                 WREG32_PLL(addr, tmp);
2849                                 break;
2850                         case 2:
2851                         case 3:
2852                                 tmp = 1000;
2853                                 switch (addr) {
2854                                 case 1:
2855                                         udelay(150);
2856                                         break;
2857                                 case 2:
2858                                         udelay(1000);
2859                                         break;
2860                                 case 3:
2861                                         while (tmp--) {
2862                                                 if (!
2863                                                     (RREG32_PLL
2864                                                      (RADEON_CLK_PWRMGT_CNTL) &
2865                                                      RADEON_MC_BUSY))
2866                                                         break;
2867                                         }
2868                                         break;
2869                                 case 4:
2870                                         while (tmp--) {
2871                                                 if (RREG32_PLL
2872                                                     (RADEON_CLK_PWRMGT_CNTL) &
2873                                                     RADEON_DLL_READY)
2874                                                         break;
2875                                         }
2876                                         break;
2877                                 case 5:
2878                                         tmp =
2879                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2880                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2881 #if 0
2882                                                 uint32_t mclk_cntl =
2883                                                     RREG32_PLL
2884                                                     (RADEON_MCLK_CNTL);
2885                                                 mclk_cntl &= 0xffff0000;
2886                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2887                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2888                                                            mclk_cntl);
2889                                                 udelay(10000);
2890 #endif
2891                                                 WREG32_PLL
2892                                                     (RADEON_CLK_PWRMGT_CNTL,
2893                                                      tmp &
2894                                                      ~RADEON_CG_NO1_DEBUG_0);
2895                                                 udelay(10000);
2896                                         }
2897                                         break;
2898                                 default:
2899                                         break;
2900                                 }
2901                                 break;
2902                         default:
2903                                 break;
2904                         }
2905                 }
2906         }
2907 }
2908
2909 static void combios_parse_ram_reset_table(struct drm_device *dev,
2910                                           uint16_t offset)
2911 {
2912         struct radeon_device *rdev = dev->dev_private;
2913         uint32_t tmp;
2914
2915         if (offset) {
2916                 uint8_t val = RBIOS8(offset);
2917                 while (val != 0xff) {
2918                         offset++;
2919
2920                         if (val == 0x0f) {
2921                                 uint32_t channel_complete_mask;
2922
2923                                 if (ASIC_IS_R300(rdev))
2924                                         channel_complete_mask =
2925                                             R300_MEM_PWRUP_COMPLETE;
2926                                 else
2927                                         channel_complete_mask =
2928                                             RADEON_MEM_PWRUP_COMPLETE;
2929                                 tmp = 20000;
2930                                 while (tmp--) {
2931                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2932                                              channel_complete_mask) ==
2933                                             channel_complete_mask)
2934                                                 break;
2935                                 }
2936                         } else {
2937                                 uint32_t or_mask = RBIOS16(offset);
2938                                 offset += 2;
2939
2940                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2941                                 tmp &= RADEON_SDRAM_MODE_MASK;
2942                                 tmp |= or_mask;
2943                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2944
2945                                 or_mask = val << 24;
2946                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2947                                 tmp &= RADEON_B3MEM_RESET_MASK;
2948                                 tmp |= or_mask;
2949                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2950                         }
2951                         val = RBIOS8(offset);
2952                 }
2953         }
2954 }
2955
2956 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2957                                    int mem_addr_mapping)
2958 {
2959         struct radeon_device *rdev = dev->dev_private;
2960         uint32_t mem_cntl;
2961         uint32_t mem_size;
2962         uint32_t addr = 0;
2963
2964         mem_cntl = RREG32(RADEON_MEM_CNTL);
2965         if (mem_cntl & RV100_HALF_MODE)
2966                 ram /= 2;
2967         mem_size = ram;
2968         mem_cntl &= ~(0xff << 8);
2969         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2970         WREG32(RADEON_MEM_CNTL, mem_cntl);
2971         RREG32(RADEON_MEM_CNTL);
2972
2973         /* sdram reset ? */
2974
2975         /* something like this????  */
2976         while (ram--) {
2977                 addr = ram * 1024 * 1024;
2978                 /* write to each page */
2979                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2980                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2981                 /* read back and verify */
2982                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2983                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2984                         return 0;
2985         }
2986
2987         return mem_size;
2988 }
2989
2990 static void combios_write_ram_size(struct drm_device *dev)
2991 {
2992         struct radeon_device *rdev = dev->dev_private;
2993         uint8_t rev;
2994         uint16_t offset;
2995         uint32_t mem_size = 0;
2996         uint32_t mem_cntl = 0;
2997
2998         /* should do something smarter here I guess... */
2999         if (rdev->flags & RADEON_IS_IGP)
3000                 return;
3001
3002         /* first check detected mem table */
3003         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3004         if (offset) {
3005                 rev = RBIOS8(offset);
3006                 if (rev < 3) {
3007                         mem_cntl = RBIOS32(offset + 1);
3008                         mem_size = RBIOS16(offset + 5);
3009                         if ((rdev->family < CHIP_R200) &&
3010                             !ASIC_IS_RN50(rdev))
3011                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3012                 }
3013         }
3014
3015         if (!mem_size) {
3016                 offset =
3017                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3018                 if (offset) {
3019                         rev = RBIOS8(offset - 1);
3020                         if (rev < 1) {
3021                                 if ((rdev->family < CHIP_R200)
3022                                     && !ASIC_IS_RN50(rdev)) {
3023                                         int ram = 0;
3024                                         int mem_addr_mapping = 0;
3025
3026                                         while (RBIOS8(offset)) {
3027                                                 ram = RBIOS8(offset);
3028                                                 mem_addr_mapping =
3029                                                     RBIOS8(offset + 1);
3030                                                 if (mem_addr_mapping != 0x25)
3031                                                         ram *= 2;
3032                                                 mem_size =
3033                                                     combios_detect_ram(dev, ram,
3034                                                                        mem_addr_mapping);
3035                                                 if (mem_size)
3036                                                         break;
3037                                                 offset += 2;
3038                                         }
3039                                 } else
3040                                         mem_size = RBIOS8(offset);
3041                         } else {
3042                                 mem_size = RBIOS8(offset);
3043                                 mem_size *= 2;  /* convert to MB */
3044                         }
3045                 }
3046         }
3047
3048         mem_size *= (1024 * 1024);      /* convert to bytes */
3049         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3050 }
3051
3052 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3053 {
3054         uint16_t dyn_clk_info =
3055             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3056
3057         if (dyn_clk_info)
3058                 combios_parse_pll_table(dev, dyn_clk_info);
3059 }
3060
3061 void radeon_combios_asic_init(struct drm_device *dev)
3062 {
3063         struct radeon_device *rdev = dev->dev_private;
3064         uint16_t table;
3065
3066         /* port hardcoded mac stuff from radeonfb */
3067         if (rdev->bios == NULL)
3068                 return;
3069
3070         /* ASIC INIT 1 */
3071         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3072         if (table)
3073                 combios_parse_mmio_table(dev, table);
3074
3075         /* PLL INIT */
3076         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3077         if (table)
3078                 combios_parse_pll_table(dev, table);
3079
3080         /* ASIC INIT 2 */
3081         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3082         if (table)
3083                 combios_parse_mmio_table(dev, table);
3084
3085         if (!(rdev->flags & RADEON_IS_IGP)) {
3086                 /* ASIC INIT 4 */
3087                 table =
3088                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3089                 if (table)
3090                         combios_parse_mmio_table(dev, table);
3091
3092                 /* RAM RESET */
3093                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3094                 if (table)
3095                         combios_parse_ram_reset_table(dev, table);
3096
3097                 /* ASIC INIT 3 */
3098                 table =
3099                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3100                 if (table)
3101                         combios_parse_mmio_table(dev, table);
3102
3103                 /* write CONFIG_MEMSIZE */
3104                 combios_write_ram_size(dev);
3105         }
3106
3107         /* quirk for rs4xx HP nx6125 laptop to make it resume
3108          * - it hangs on resume inside the dynclk 1 table.
3109          */
3110         if (rdev->family == CHIP_RS480 &&
3111             rdev->pdev->subsystem_vendor == 0x103c &&
3112             rdev->pdev->subsystem_device == 0x308b)
3113                 return;
3114
3115         /* quirk for rs4xx HP dv5000 laptop to make it resume
3116          * - it hangs on resume inside the dynclk 1 table.
3117          */
3118         if (rdev->family == CHIP_RS480 &&
3119             rdev->pdev->subsystem_vendor == 0x103c &&
3120             rdev->pdev->subsystem_device == 0x30a4)
3121                 return;
3122
3123         /* DYN CLK 1 */
3124         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3125         if (table)
3126                 combios_parse_pll_table(dev, table);
3127
3128 }
3129
3130 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3131 {
3132         struct radeon_device *rdev = dev->dev_private;
3133         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3134
3135         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3136         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3137         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3138
3139         /* let the bios control the backlight */
3140         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3141
3142         /* tell the bios not to handle mode switching */
3143         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3144                            RADEON_ACC_MODE_CHANGE);
3145
3146         /* tell the bios a driver is loaded */
3147         bios_7_scratch |= RADEON_DRV_LOADED;
3148
3149         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3150         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3151         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3152 }
3153
3154 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3155 {
3156         struct drm_device *dev = encoder->dev;
3157         struct radeon_device *rdev = dev->dev_private;
3158         uint32_t bios_6_scratch;
3159
3160         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3161
3162         if (lock)
3163                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3164         else
3165                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3166
3167         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3168 }
3169
3170 void
3171 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3172                                       struct drm_encoder *encoder,
3173                                       bool connected)
3174 {
3175         struct drm_device *dev = connector->dev;
3176         struct radeon_device *rdev = dev->dev_private;
3177         struct radeon_connector *radeon_connector =
3178             to_radeon_connector(connector);
3179         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3180         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3181         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3182
3183         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3184             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3185                 if (connected) {
3186                         DRM_DEBUG_KMS("TV1 connected\n");
3187                         /* fix me */
3188                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3189                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3190                         bios_5_scratch |= RADEON_TV1_ON;
3191                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3192                 } else {
3193                         DRM_DEBUG_KMS("TV1 disconnected\n");
3194                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3195                         bios_5_scratch &= ~RADEON_TV1_ON;
3196                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3197                 }
3198         }
3199         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3200             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3201                 if (connected) {
3202                         DRM_DEBUG_KMS("LCD1 connected\n");
3203                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3204                         bios_5_scratch |= RADEON_LCD1_ON;
3205                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3206                 } else {
3207                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3208                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3209                         bios_5_scratch &= ~RADEON_LCD1_ON;
3210                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3211                 }
3212         }
3213         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3214             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3215                 if (connected) {
3216                         DRM_DEBUG_KMS("CRT1 connected\n");
3217                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3218                         bios_5_scratch |= RADEON_CRT1_ON;
3219                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3220                 } else {
3221                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3222                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3223                         bios_5_scratch &= ~RADEON_CRT1_ON;
3224                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3225                 }
3226         }
3227         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3228             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3229                 if (connected) {
3230                         DRM_DEBUG_KMS("CRT2 connected\n");
3231                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3232                         bios_5_scratch |= RADEON_CRT2_ON;
3233                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3234                 } else {
3235                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3236                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3237                         bios_5_scratch &= ~RADEON_CRT2_ON;
3238                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3239                 }
3240         }
3241         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3242             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3243                 if (connected) {
3244                         DRM_DEBUG_KMS("DFP1 connected\n");
3245                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3246                         bios_5_scratch |= RADEON_DFP1_ON;
3247                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3248                 } else {
3249                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3250                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3251                         bios_5_scratch &= ~RADEON_DFP1_ON;
3252                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3253                 }
3254         }
3255         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3256             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3257                 if (connected) {
3258                         DRM_DEBUG_KMS("DFP2 connected\n");
3259                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3260                         bios_5_scratch |= RADEON_DFP2_ON;
3261                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3262                 } else {
3263                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3264                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3265                         bios_5_scratch &= ~RADEON_DFP2_ON;
3266                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3267                 }
3268         }
3269         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3270         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3271 }
3272
3273 void
3274 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3275 {
3276         struct drm_device *dev = encoder->dev;
3277         struct radeon_device *rdev = dev->dev_private;
3278         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3279         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3280
3281         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3282                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3283                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3284         }
3285         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3286                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3287                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3288         }
3289         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3290                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3291                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3292         }
3293         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3294                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3295                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3296         }
3297         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3298                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3299                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3300         }
3301         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3302                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3303                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3304         }
3305         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3306 }
3307
3308 void
3309 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3310 {
3311         struct drm_device *dev = encoder->dev;
3312         struct radeon_device *rdev = dev->dev_private;
3313         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3314         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3315
3316         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3317                 if (on)
3318                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3319                 else
3320                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3321         }
3322         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3323                 if (on)
3324                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3325                 else
3326                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3327         }
3328         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3329                 if (on)
3330                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3331                 else
3332                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3333         }
3334         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3335                 if (on)
3336                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3337                 else
3338                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3339         }
3340         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3341 }