2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
91 extern int radeon_new_pll;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
101 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
102 /* RADEON_IB_POOL_SIZE must be a power of 2 */
103 #define RADEON_IB_POOL_SIZE 16
104 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
105 #define RADEONFB_CONN_LIMIT 4
106 #define RADEON_BIOS_NUM_SCRATCH 8
109 * Errata workarounds.
111 enum radeon_pll_errata {
112 CHIP_ERRATA_R300_CG = 0x00000001,
113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
114 CHIP_ERRATA_PLL_DELAY = 0x00000004
118 struct radeon_device;
124 #define ATRM_BIOS_PAGE 4096
126 #if defined(CONFIG_VGA_SWITCHEROO)
127 bool radeon_atrm_supported(struct pci_dev *pdev);
128 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
130 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
135 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
139 bool radeon_get_bios(struct radeon_device *rdev);
145 struct radeon_dummy_page {
149 int radeon_dummy_page_init(struct radeon_device *rdev);
150 void radeon_dummy_page_fini(struct radeon_device *rdev);
156 struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
159 struct radeon_pll dcpll;
160 struct radeon_pll spll;
161 struct radeon_pll mpll;
163 uint32_t default_mclk;
164 uint32_t default_sclk;
165 uint32_t default_dispclk;
172 int radeon_pm_init(struct radeon_device *rdev);
173 void radeon_pm_fini(struct radeon_device *rdev);
174 void radeon_pm_compute_clocks(struct radeon_device *rdev);
175 void radeon_pm_suspend(struct radeon_device *rdev);
176 void radeon_pm_resume(struct radeon_device *rdev);
177 void radeon_combios_get_power_modes(struct radeon_device *rdev);
178 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
179 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
180 void rs690_pm_info(struct radeon_device *rdev);
181 extern u32 rv6xx_get_temp(struct radeon_device *rdev);
182 extern u32 rv770_get_temp(struct radeon_device *rdev);
183 extern u32 evergreen_get_temp(struct radeon_device *rdev);
188 struct radeon_fence_driver {
189 uint32_t scratch_reg;
192 unsigned long last_jiffies;
193 unsigned long last_timeout;
194 wait_queue_head_t queue;
196 struct list_head created;
197 struct list_head emited;
198 struct list_head signaled;
202 struct radeon_fence {
203 struct radeon_device *rdev;
205 struct list_head list;
206 /* protected by radeon_fence.lock */
212 int radeon_fence_driver_init(struct radeon_device *rdev);
213 void radeon_fence_driver_fini(struct radeon_device *rdev);
214 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
215 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
216 void radeon_fence_process(struct radeon_device *rdev);
217 bool radeon_fence_signaled(struct radeon_fence *fence);
218 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
219 int radeon_fence_wait_next(struct radeon_device *rdev);
220 int radeon_fence_wait_last(struct radeon_device *rdev);
221 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
222 void radeon_fence_unref(struct radeon_fence **fence);
227 struct radeon_surface_reg {
228 struct radeon_bo *bo;
231 #define RADEON_GEM_MAX_SURFACES 8
237 struct ttm_bo_global_ref bo_global_ref;
238 struct ttm_global_reference mem_global_ref;
239 struct ttm_bo_device bdev;
240 bool mem_global_referenced;
245 /* Protected by gem.mutex */
246 struct list_head list;
247 /* Protected by tbo.reserved */
249 struct ttm_placement placement;
250 struct ttm_buffer_object tbo;
251 struct ttm_bo_kmap_obj kmap;
257 /* Constant after initialization */
258 struct radeon_device *rdev;
259 struct drm_gem_object *gobj;
262 struct radeon_bo_list {
263 struct list_head list;
264 struct radeon_bo *bo;
277 struct list_head objects;
280 int radeon_gem_init(struct radeon_device *rdev);
281 void radeon_gem_fini(struct radeon_device *rdev);
282 int radeon_gem_object_create(struct radeon_device *rdev, int size,
283 int alignment, int initial_domain,
284 bool discardable, bool kernel,
285 struct drm_gem_object **obj);
286 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
288 void radeon_gem_object_unpin(struct drm_gem_object *obj);
292 * GART structures, functions & helpers
296 struct radeon_gart_table_ram {
297 volatile uint32_t *ptr;
300 struct radeon_gart_table_vram {
301 struct radeon_bo *robj;
302 volatile uint32_t *ptr;
305 union radeon_gart_table {
306 struct radeon_gart_table_ram ram;
307 struct radeon_gart_table_vram vram;
310 #define RADEON_GPU_PAGE_SIZE 4096
311 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
314 dma_addr_t table_addr;
315 unsigned num_gpu_pages;
316 unsigned num_cpu_pages;
318 union radeon_gart_table table;
320 dma_addr_t *pages_addr;
324 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
325 void radeon_gart_table_ram_free(struct radeon_device *rdev);
326 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
327 void radeon_gart_table_vram_free(struct radeon_device *rdev);
328 int radeon_gart_init(struct radeon_device *rdev);
329 void radeon_gart_fini(struct radeon_device *rdev);
330 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
332 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
333 int pages, struct page **pagelist);
337 * GPU MC structures, functions & helpers
340 resource_size_t aper_size;
341 resource_size_t aper_base;
342 resource_size_t agp_base;
343 /* for some chips with <= 32MB we need to lie
344 * about vram size near mc fb location */
346 u64 visible_vram_size;
356 bool igp_sideport_enabled;
359 bool radeon_combios_sideport_present(struct radeon_device *rdev);
360 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
363 * GPU scratch registers structures, functions & helpers
365 struct radeon_scratch {
371 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
372 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
381 /* FIXME: use a define max crtc rather than hardcode it */
382 bool crtc_vblank_int[6];
383 wait_queue_head_t vblank_queue;
384 /* FIXME: use defines for max hpd/dacs */
388 wait_queue_head_t idle_queue;
389 /* FIXME: use defines for max HDMI blocks */
395 int radeon_irq_kms_init(struct radeon_device *rdev);
396 void radeon_irq_kms_fini(struct radeon_device *rdev);
397 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
398 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
404 struct list_head list;
407 struct radeon_fence *fence;
415 * mutex protects scheduled_ibs, ready, alloc_bm
417 struct radeon_ib_pool {
419 struct radeon_bo *robj;
420 struct list_head bogus_ib;
421 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
427 struct radeon_bo *ring_obj;
428 volatile uint32_t *ring;
433 unsigned ring_free_dw;
446 struct radeon_bo *ring_obj;
447 volatile uint32_t *ring;
460 struct radeon_bo *shader_obj;
462 u32 vs_offset, ps_offset;
465 u32 vb_used, vb_total;
466 struct radeon_ib *vb_ib;
469 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
470 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
471 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
472 int radeon_ib_pool_init(struct radeon_device *rdev);
473 void radeon_ib_pool_fini(struct radeon_device *rdev);
474 int radeon_ib_test(struct radeon_device *rdev);
475 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
476 /* Ring access between begin & end cannot sleep */
477 void radeon_ring_free_size(struct radeon_device *rdev);
478 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
479 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
480 void radeon_ring_commit(struct radeon_device *rdev);
481 void radeon_ring_unlock_commit(struct radeon_device *rdev);
482 void radeon_ring_unlock_undo(struct radeon_device *rdev);
483 int radeon_ring_test(struct radeon_device *rdev);
484 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
485 void radeon_ring_fini(struct radeon_device *rdev);
491 struct radeon_cs_reloc {
492 struct drm_gem_object *gobj;
493 struct radeon_bo *robj;
494 struct radeon_bo_list lobj;
499 struct radeon_cs_chunk {
505 void __user *user_ptr;
506 int last_copied_page;
510 struct radeon_cs_parser {
512 struct radeon_device *rdev;
513 struct drm_file *filp;
516 struct radeon_cs_chunk *chunks;
517 uint64_t *chunks_array;
522 struct radeon_cs_reloc *relocs;
523 struct radeon_cs_reloc **relocs_ptr;
524 struct list_head validated;
525 /* indices of various chunks */
527 int chunk_relocs_idx;
528 struct radeon_ib *ib;
534 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
535 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
538 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
540 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
541 u32 pg_idx, pg_offset;
545 pg_idx = (idx * 4) / PAGE_SIZE;
546 pg_offset = (idx * 4) % PAGE_SIZE;
548 if (ibc->kpage_idx[0] == pg_idx)
549 return ibc->kpage[0][pg_offset/4];
550 if (ibc->kpage_idx[1] == pg_idx)
551 return ibc->kpage[1][pg_offset/4];
553 new_page = radeon_cs_update_pages(p, pg_idx);
555 p->parser_error = new_page;
559 idx_value = ibc->kpage[new_page][pg_offset/4];
563 struct radeon_cs_packet {
572 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
573 struct radeon_cs_packet *pkt,
574 unsigned idx, unsigned reg);
575 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
576 struct radeon_cs_packet *pkt);
582 int radeon_agp_init(struct radeon_device *rdev);
583 void radeon_agp_resume(struct radeon_device *rdev);
584 void radeon_agp_suspend(struct radeon_device *rdev);
585 void radeon_agp_fini(struct radeon_device *rdev);
592 struct radeon_bo *wb_obj;
593 volatile uint32_t *wb;
598 * struct radeon_pm - power management datas
599 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
600 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
601 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
602 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
603 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
604 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
605 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
606 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
607 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
608 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
609 * @needed_bandwidth: current bandwidth needs
611 * It keeps track of various data needed to take powermanagement decision.
612 * Bandwith need is used to determine minimun clock of the GPU and memory.
613 * Equation between gpu/memory clock and available bandwidth is hw dependent
614 * (type of memory, bus size, efficiency, ...)
617 enum radeon_pm_method {
622 enum radeon_dynpm_state {
623 DYNPM_STATE_DISABLED,
627 DYNPM_STATE_SUSPENDED,
629 enum radeon_dynpm_action {
631 DYNPM_ACTION_MINIMUM,
632 DYNPM_ACTION_DOWNCLOCK,
633 DYNPM_ACTION_UPCLOCK,
637 enum radeon_voltage_type {
644 enum radeon_pm_state_type {
645 POWER_STATE_TYPE_DEFAULT,
646 POWER_STATE_TYPE_POWERSAVE,
647 POWER_STATE_TYPE_BATTERY,
648 POWER_STATE_TYPE_BALANCED,
649 POWER_STATE_TYPE_PERFORMANCE,
652 enum radeon_pm_profile_type {
660 #define PM_PROFILE_DEFAULT_IDX 0
661 #define PM_PROFILE_LOW_SH_IDX 1
662 #define PM_PROFILE_MID_SH_IDX 2
663 #define PM_PROFILE_HIGH_SH_IDX 3
664 #define PM_PROFILE_LOW_MH_IDX 4
665 #define PM_PROFILE_MID_MH_IDX 5
666 #define PM_PROFILE_HIGH_MH_IDX 6
667 #define PM_PROFILE_MAX 7
669 struct radeon_pm_profile {
676 enum radeon_int_thermal_type {
680 THERMAL_TYPE_EVERGREEN,
683 struct radeon_voltage {
684 enum radeon_voltage_type type;
686 struct radeon_gpio_rec gpio;
687 u32 delay; /* delay in usec from voltage drop to sclk change */
688 bool active_high; /* voltage drop is active when bit is high */
690 u8 vddc_id; /* index into vddc voltage table */
691 u8 vddci_id; /* index into vddci voltage table */
697 /* clock mode flags */
698 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
700 struct radeon_pm_clock_info {
706 struct radeon_voltage voltage;
707 /* standardized clock flags */
712 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
714 struct radeon_power_state {
715 enum radeon_pm_state_type type;
716 /* XXX: use a define for num clock modes */
717 struct radeon_pm_clock_info clock_info[8];
718 /* number of valid clock modes in this power state */
720 struct radeon_pm_clock_info *default_clock_mode;
721 /* standardized state flags */
723 u32 misc; /* vbios specific flags */
724 u32 misc2; /* vbios specific flags */
725 int pcie_lanes; /* pcie lanes */
729 * Some modes are overclocked by very low value, accept them
731 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
736 int active_crtc_count;
740 fixed20_12 max_bandwidth;
741 fixed20_12 igp_sideport_mclk;
742 fixed20_12 igp_system_mclk;
743 fixed20_12 igp_ht_link_clk;
744 fixed20_12 igp_ht_link_width;
745 fixed20_12 k8_bandwidth;
746 fixed20_12 sideport_bandwidth;
747 fixed20_12 ht_bandwidth;
748 fixed20_12 core_bandwidth;
751 fixed20_12 needed_bandwidth;
752 /* XXX: use a define for num power modes */
753 struct radeon_power_state power_state[8];
754 /* number of valid power states */
755 int num_power_states;
756 int current_power_state_index;
757 int current_clock_mode_index;
758 int requested_power_state_index;
759 int requested_clock_mode_index;
760 int default_power_state_index;
764 struct radeon_i2c_chan *i2c_bus;
765 /* selected pm method */
766 enum radeon_pm_method pm_method;
767 /* dynpm power management */
768 struct delayed_work dynpm_idle_work;
769 enum radeon_dynpm_state dynpm_state;
770 enum radeon_dynpm_action dynpm_planned_action;
771 unsigned long dynpm_action_timeout;
772 bool dynpm_can_upclock;
773 bool dynpm_can_downclock;
774 /* profile-based power management */
775 enum radeon_pm_profile_type profile;
777 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
778 /* internal thermal controller on rv6xx+ */
779 enum radeon_int_thermal_type int_thermal_type;
780 struct device *int_hwmon_dev;
787 void radeon_benchmark(struct radeon_device *rdev);
793 void radeon_test_moves(struct radeon_device *rdev);
799 int radeon_debugfs_add_files(struct radeon_device *rdev,
800 struct drm_info_list *files,
802 int radeon_debugfs_fence_init(struct radeon_device *rdev);
806 * ASIC specific functions.
809 int (*init)(struct radeon_device *rdev);
810 void (*fini)(struct radeon_device *rdev);
811 int (*resume)(struct radeon_device *rdev);
812 int (*suspend)(struct radeon_device *rdev);
813 void (*vga_set_state)(struct radeon_device *rdev, bool state);
814 bool (*gpu_is_lockup)(struct radeon_device *rdev);
815 int (*asic_reset)(struct radeon_device *rdev);
816 void (*gart_tlb_flush)(struct radeon_device *rdev);
817 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
818 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
819 void (*cp_fini)(struct radeon_device *rdev);
820 void (*cp_disable)(struct radeon_device *rdev);
821 void (*cp_commit)(struct radeon_device *rdev);
822 void (*ring_start)(struct radeon_device *rdev);
823 int (*ring_test)(struct radeon_device *rdev);
824 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
825 int (*irq_set)(struct radeon_device *rdev);
826 int (*irq_process)(struct radeon_device *rdev);
827 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
828 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
829 int (*cs_parse)(struct radeon_cs_parser *p);
830 int (*copy_blit)(struct radeon_device *rdev,
834 struct radeon_fence *fence);
835 int (*copy_dma)(struct radeon_device *rdev,
839 struct radeon_fence *fence);
840 int (*copy)(struct radeon_device *rdev,
844 struct radeon_fence *fence);
845 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
846 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
847 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
848 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
849 int (*get_pcie_lanes)(struct radeon_device *rdev);
850 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
851 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
852 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
853 uint32_t tiling_flags, uint32_t pitch,
854 uint32_t offset, uint32_t obj_size);
855 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
856 void (*bandwidth_update)(struct radeon_device *rdev);
857 void (*hpd_init)(struct radeon_device *rdev);
858 void (*hpd_fini)(struct radeon_device *rdev);
859 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
860 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
861 /* ioctl hw specific callback. Some hw might want to perform special
862 * operation on specific ioctl. For instance on wait idle some hw
863 * might want to perform and HDP flush through MMIO as it seems that
864 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
867 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
868 bool (*gui_idle)(struct radeon_device *rdev);
869 /* power management */
870 void (*pm_misc)(struct radeon_device *rdev);
871 void (*pm_prepare)(struct radeon_device *rdev);
872 void (*pm_finish)(struct radeon_device *rdev);
873 void (*pm_init_profile)(struct radeon_device *rdev);
874 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
880 struct r100_gpu_lockup {
881 unsigned long last_jiffies;
886 const unsigned *reg_safe_bm;
887 unsigned reg_safe_bm_size;
889 struct r100_gpu_lockup lockup;
893 const unsigned *reg_safe_bm;
894 unsigned reg_safe_bm_size;
897 struct r100_gpu_lockup lockup;
902 unsigned max_tile_pipes;
904 unsigned max_backends;
906 unsigned max_threads;
907 unsigned max_stack_entries;
908 unsigned max_hw_contexts;
909 unsigned max_gs_threads;
910 unsigned sx_max_export_size;
911 unsigned sx_max_export_pos_size;
912 unsigned sx_max_export_smx_size;
913 unsigned sq_num_cf_insts;
914 unsigned tiling_nbanks;
915 unsigned tiling_npipes;
916 unsigned tiling_group_size;
917 unsigned tile_config;
918 struct r100_gpu_lockup lockup;
923 unsigned max_tile_pipes;
925 unsigned max_backends;
927 unsigned max_threads;
928 unsigned max_stack_entries;
929 unsigned max_hw_contexts;
930 unsigned max_gs_threads;
931 unsigned sx_max_export_size;
932 unsigned sx_max_export_pos_size;
933 unsigned sx_max_export_smx_size;
934 unsigned sq_num_cf_insts;
935 unsigned sx_num_of_sets;
936 unsigned sc_prim_fifo_size;
937 unsigned sc_hiz_tile_fifo_size;
938 unsigned sc_earlyz_tile_fifo_fize;
939 unsigned tiling_nbanks;
940 unsigned tiling_npipes;
941 unsigned tiling_group_size;
942 unsigned tile_config;
943 struct r100_gpu_lockup lockup;
946 struct evergreen_asic {
949 unsigned max_tile_pipes;
951 unsigned max_backends;
953 unsigned max_threads;
954 unsigned max_stack_entries;
955 unsigned max_hw_contexts;
956 unsigned max_gs_threads;
957 unsigned sx_max_export_size;
958 unsigned sx_max_export_pos_size;
959 unsigned sx_max_export_smx_size;
960 unsigned sq_num_cf_insts;
961 unsigned sx_num_of_sets;
962 unsigned sc_prim_fifo_size;
963 unsigned sc_hiz_tile_fifo_size;
964 unsigned sc_earlyz_tile_fifo_size;
965 unsigned tiling_nbanks;
966 unsigned tiling_npipes;
967 unsigned tiling_group_size;
968 unsigned tile_config;
971 union radeon_asic_config {
972 struct r300_asic r300;
973 struct r100_asic r100;
974 struct r600_asic r600;
975 struct rv770_asic rv770;
976 struct evergreen_asic evergreen;
980 * asic initizalization from radeon_asic.c
982 void radeon_agp_disable(struct radeon_device *rdev);
983 int radeon_asic_init(struct radeon_device *rdev);
989 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
990 struct drm_file *filp);
991 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *filp);
993 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
994 struct drm_file *file_priv);
995 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file_priv);
997 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
998 struct drm_file *file_priv);
999 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1000 struct drm_file *file_priv);
1001 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1002 struct drm_file *filp);
1003 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1004 struct drm_file *filp);
1005 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *filp);
1007 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *filp);
1009 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1010 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1011 struct drm_file *filp);
1012 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1013 struct drm_file *filp);
1017 * Core structure, functions and helpers.
1019 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1020 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1022 struct radeon_device {
1024 struct drm_device *ddev;
1025 struct pci_dev *pdev;
1027 union radeon_asic_config config;
1028 enum radeon_family family;
1029 unsigned long flags;
1031 enum radeon_pll_errata pll_errata;
1038 uint16_t bios_header_start;
1039 struct radeon_bo *stollen_vga_memory;
1041 resource_size_t rmmio_base;
1042 resource_size_t rmmio_size;
1044 radeon_rreg_t mc_rreg;
1045 radeon_wreg_t mc_wreg;
1046 radeon_rreg_t pll_rreg;
1047 radeon_wreg_t pll_wreg;
1048 uint32_t pcie_reg_mask;
1049 radeon_rreg_t pciep_rreg;
1050 radeon_wreg_t pciep_wreg;
1051 struct radeon_clock clock;
1052 struct radeon_mc mc;
1053 struct radeon_gart gart;
1054 struct radeon_mode_info mode_info;
1055 struct radeon_scratch scratch;
1056 struct radeon_mman mman;
1057 struct radeon_fence_driver fence_drv;
1058 struct radeon_cp cp;
1059 struct radeon_ib_pool ib_pool;
1060 struct radeon_irq irq;
1061 struct radeon_asic *asic;
1062 struct radeon_gem gem;
1063 struct radeon_pm pm;
1064 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1065 struct mutex cs_mutex;
1066 struct radeon_wb wb;
1067 struct radeon_dummy_page dummy_page;
1073 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1074 const struct firmware *me_fw; /* all family ME firmware */
1075 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1076 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1077 struct r600_blit r600_blit;
1078 int msi_enabled; /* msi enabled */
1079 struct r600_ih ih; /* r6/700 interrupt ring */
1080 struct workqueue_struct *wq;
1081 struct work_struct hotplug_work;
1082 int num_crtc; /* number of crtcs */
1083 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1084 struct mutex vram_mutex;
1088 struct timer_list audio_timer;
1091 int audio_bits_per_sample;
1092 uint8_t audio_status_bits;
1093 uint8_t audio_category_code;
1096 struct notifier_block acpi_nb;
1099 int radeon_device_init(struct radeon_device *rdev,
1100 struct drm_device *ddev,
1101 struct pci_dev *pdev,
1103 void radeon_device_fini(struct radeon_device *rdev);
1104 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1107 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1108 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1109 void r600_kms_blit_copy(struct radeon_device *rdev,
1110 u64 src_gpu_addr, u64 dst_gpu_addr,
1113 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1115 if (reg < rdev->rmmio_size)
1116 return readl(((void __iomem *)rdev->rmmio) + reg);
1118 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1119 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1123 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1125 if (reg < rdev->rmmio_size)
1126 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1128 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1129 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1136 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1139 * Registers read & write functions.
1141 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1142 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1143 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1144 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1145 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1146 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1147 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1148 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1149 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1150 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1151 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1152 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1153 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1154 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1155 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1156 #define WREG32_P(reg, val, mask) \
1158 uint32_t tmp_ = RREG32(reg); \
1160 tmp_ |= ((val) & ~(mask)); \
1161 WREG32(reg, tmp_); \
1163 #define WREG32_PLL_P(reg, val, mask) \
1165 uint32_t tmp_ = RREG32_PLL(reg); \
1167 tmp_ |= ((val) & ~(mask)); \
1168 WREG32_PLL(reg, tmp_); \
1170 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1173 * Indirect registers accessor
1175 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1179 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1180 r = RREG32(RADEON_PCIE_DATA);
1184 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1186 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1187 WREG32(RADEON_PCIE_DATA, (v));
1190 void r100_pll_errata_after_index(struct radeon_device *rdev);
1196 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1197 (rdev->pdev->device == 0x5969))
1198 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1199 (rdev->family == CHIP_RV200) || \
1200 (rdev->family == CHIP_RS100) || \
1201 (rdev->family == CHIP_RS200) || \
1202 (rdev->family == CHIP_RV250) || \
1203 (rdev->family == CHIP_RV280) || \
1204 (rdev->family == CHIP_RS300))
1205 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1206 (rdev->family == CHIP_RV350) || \
1207 (rdev->family == CHIP_R350) || \
1208 (rdev->family == CHIP_RV380) || \
1209 (rdev->family == CHIP_R420) || \
1210 (rdev->family == CHIP_R423) || \
1211 (rdev->family == CHIP_RV410) || \
1212 (rdev->family == CHIP_RS400) || \
1213 (rdev->family == CHIP_RS480))
1214 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1215 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1216 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1217 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1222 #define RBIOS8(i) (rdev->bios[i])
1223 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1224 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1226 int radeon_combios_init(struct radeon_device *rdev);
1227 void radeon_combios_fini(struct radeon_device *rdev);
1228 int radeon_atombios_init(struct radeon_device *rdev);
1229 void radeon_atombios_fini(struct radeon_device *rdev);
1235 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1238 if (rdev->cp.count_dw <= 0) {
1239 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1242 rdev->cp.ring[rdev->cp.wptr++] = v;
1243 rdev->cp.wptr &= rdev->cp.ptr_mask;
1244 rdev->cp.count_dw--;
1245 rdev->cp.ring_free_dw--;
1252 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1253 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1254 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1255 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1256 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1257 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1258 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1259 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1260 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1261 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1262 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1263 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1264 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1265 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1266 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1267 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1268 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1269 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1270 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1271 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1272 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1273 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1274 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1275 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1276 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1277 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1278 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1279 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1280 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1281 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1282 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1283 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1284 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1285 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1286 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1287 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1288 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1289 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1290 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1291 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1292 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1294 /* Common functions */
1296 extern int radeon_gpu_reset(struct radeon_device *rdev);
1297 extern void radeon_agp_disable(struct radeon_device *rdev);
1298 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1299 extern void radeon_gart_restore(struct radeon_device *rdev);
1300 extern int radeon_modeset_init(struct radeon_device *rdev);
1301 extern void radeon_modeset_fini(struct radeon_device *rdev);
1302 extern bool radeon_card_posted(struct radeon_device *rdev);
1303 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1304 extern void radeon_update_display_priority(struct radeon_device *rdev);
1305 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1306 extern int radeon_clocks_init(struct radeon_device *rdev);
1307 extern void radeon_clocks_fini(struct radeon_device *rdev);
1308 extern void radeon_scratch_init(struct radeon_device *rdev);
1309 extern void radeon_surface_init(struct radeon_device *rdev);
1310 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1311 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1312 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1313 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1314 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1315 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1316 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1317 extern int radeon_resume_kms(struct drm_device *dev);
1318 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1320 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1321 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1322 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1324 /* rv200,rv250,rv280 */
1325 extern void r200_set_safe_registers(struct radeon_device *rdev);
1327 /* r300,r350,rv350,rv370,rv380 */
1328 extern void r300_set_reg_safe(struct radeon_device *rdev);
1329 extern void r300_mc_program(struct radeon_device *rdev);
1330 extern void r300_mc_init(struct radeon_device *rdev);
1331 extern void r300_clock_startup(struct radeon_device *rdev);
1332 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1333 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1334 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1335 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1336 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1338 /* r420,r423,rv410 */
1339 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1340 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1341 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1342 extern void r420_pipes_init(struct radeon_device *rdev);
1345 struct rv515_mc_save {
1348 u32 vga_render_control;
1349 u32 vga_hdp_control;
1353 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1354 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1355 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1356 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1357 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1358 extern void rv515_clock_startup(struct radeon_device *rdev);
1359 extern void rv515_debugfs(struct radeon_device *rdev);
1360 extern int rv515_suspend(struct radeon_device *rdev);
1363 extern int rs400_gart_init(struct radeon_device *rdev);
1364 extern int rs400_gart_enable(struct radeon_device *rdev);
1365 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1366 extern void rs400_gart_disable(struct radeon_device *rdev);
1367 extern void rs400_gart_fini(struct radeon_device *rdev);
1370 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1371 extern int rs600_irq_set(struct radeon_device *rdev);
1372 extern void rs600_irq_disable(struct radeon_device *rdev);
1375 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1376 struct drm_display_mode *mode1,
1377 struct drm_display_mode *mode2);
1379 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1380 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1381 extern bool r600_card_posted(struct radeon_device *rdev);
1382 extern void r600_cp_stop(struct radeon_device *rdev);
1383 extern int r600_cp_start(struct radeon_device *rdev);
1384 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1385 extern int r600_cp_resume(struct radeon_device *rdev);
1386 extern void r600_cp_fini(struct radeon_device *rdev);
1387 extern int r600_count_pipe_bits(uint32_t val);
1388 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1389 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1390 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1391 extern int r600_ib_test(struct radeon_device *rdev);
1392 extern int r600_ring_test(struct radeon_device *rdev);
1393 extern void r600_wb_fini(struct radeon_device *rdev);
1394 extern int r600_wb_enable(struct radeon_device *rdev);
1395 extern void r600_wb_disable(struct radeon_device *rdev);
1396 extern void r600_scratch_init(struct radeon_device *rdev);
1397 extern int r600_blit_init(struct radeon_device *rdev);
1398 extern void r600_blit_fini(struct radeon_device *rdev);
1399 extern int r600_init_microcode(struct radeon_device *rdev);
1400 extern int r600_asic_reset(struct radeon_device *rdev);
1402 extern int r600_irq_init(struct radeon_device *rdev);
1403 extern void r600_irq_fini(struct radeon_device *rdev);
1404 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1405 extern int r600_irq_set(struct radeon_device *rdev);
1406 extern void r600_irq_suspend(struct radeon_device *rdev);
1407 extern void r600_disable_interrupts(struct radeon_device *rdev);
1408 extern void r600_rlc_stop(struct radeon_device *rdev);
1410 extern int r600_audio_init(struct radeon_device *rdev);
1411 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1412 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1413 extern int r600_audio_channels(struct radeon_device *rdev);
1414 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1415 extern int r600_audio_rate(struct radeon_device *rdev);
1416 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1417 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1418 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1419 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1420 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1421 extern void r600_audio_fini(struct radeon_device *rdev);
1422 extern void r600_hdmi_init(struct drm_encoder *encoder);
1423 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1424 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1425 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1426 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1427 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1429 extern void r700_cp_stop(struct radeon_device *rdev);
1430 extern void r700_cp_fini(struct radeon_device *rdev);
1431 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1432 extern int evergreen_irq_set(struct radeon_device *rdev);
1435 #if defined(CONFIG_ACPI)
1436 extern int radeon_acpi_init(struct radeon_device *rdev);
1438 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1442 struct evergreen_mc_save {
1444 u32 vga_render_control;
1445 u32 vga_hdp_control;
1446 u32 crtc_control[6];
1449 #include "radeon_object.h"