drivers/gpu/drm/radeon/r600_cs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kernel.h>
  29 #include "drmP.h"
  30 #include "radeon.h"
  31 #include "r600d.h"
  32 #include "r600_reg_safe.h"
  33
  34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  35                                         struct radeon_cs_reloc **cs_reloc);
  36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  37                                         struct radeon_cs_reloc **cs_reloc);
  38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
  39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
  40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
  41
  42
  43 struct r600_cs_track {
  44         /* configuration we miror so that we use same code btw kms/ums */
  45         u32                     group_size;
  46         u32                     nbanks;
  47         u32                     npipes;
  48         /* value we track */
  49         u32                     sq_config;
  50         u32                     nsamples;
  51         u32                     cb_color_base_last[8];
  52         struct radeon_bo        *cb_color_bo[8];
  53         u32                     cb_color_bo_offset[8];
  54         struct radeon_bo        *cb_color_frag_bo[8];
  55         struct radeon_bo        *cb_color_tile_bo[8];
  56         u32                     cb_color_info[8];
  57         u32                     cb_color_size_idx[8];
  58         u32                     cb_target_mask;
  59         u32                     cb_shader_mask;
  60         u32                     cb_color_size[8];
  61         u32                     vgt_strmout_en;
  62         u32                     vgt_strmout_buffer_en;
  63         u32                     db_depth_control;
  64         u32                     db_depth_info;
  65         u32                     db_depth_size_idx;
  66         u32                     db_depth_view;
  67         u32                     db_depth_size;
  68         u32                     db_offset;
  69         struct radeon_bo        *db_bo;
  70 };
  71
  72 static inline int r600_bpe_from_format(u32 *bpe, u32 format)
  73 {
  74         switch (format) {
  75         case V_038004_COLOR_8:
  76         case V_038004_COLOR_4_4:
  77         case V_038004_COLOR_3_3_2:
  78         case V_038004_FMT_1:
  79                 *bpe = 1;
  80                 break;
  81         case V_038004_COLOR_16:
  82         case V_038004_COLOR_16_FLOAT:
  83         case V_038004_COLOR_8_8:
  84         case V_038004_COLOR_5_6_5:
  85         case V_038004_COLOR_6_5_5:
  86         case V_038004_COLOR_1_5_5_5:
  87         case V_038004_COLOR_4_4_4_4:
  88         case V_038004_COLOR_5_5_5_1:
  89                 *bpe = 2;
  90                 break;
  91         case V_038004_FMT_8_8_8:
  92                 *bpe = 3;
  93                 break;
  94         case V_038004_COLOR_32:
  95         case V_038004_COLOR_32_FLOAT:
  96         case V_038004_COLOR_16_16:
  97         case V_038004_COLOR_16_16_FLOAT:
  98         case V_038004_COLOR_8_24:
  99         case V_038004_COLOR_8_24_FLOAT:
 100         case V_038004_COLOR_24_8:
 101         case V_038004_COLOR_24_8_FLOAT:
 102         case V_038004_COLOR_10_11_11:
 103         case V_038004_COLOR_10_11_11_FLOAT:
 104         case V_038004_COLOR_11_11_10:
 105         case V_038004_COLOR_11_11_10_FLOAT:
 106         case V_038004_COLOR_2_10_10_10:
 107         case V_038004_COLOR_8_8_8_8:
 108         case V_038004_COLOR_10_10_10_2:
 109         case V_038004_FMT_5_9_9_9_SHAREDEXP:
 110         case V_038004_FMT_32_AS_8:
 111         case V_038004_FMT_32_AS_8_8:
 112                 *bpe = 4;
 113                 break;
 114         case V_038004_COLOR_X24_8_32_FLOAT:
 115         case V_038004_COLOR_32_32:
 116         case V_038004_COLOR_32_32_FLOAT:
 117         case V_038004_COLOR_16_16_16_16:
 118         case V_038004_COLOR_16_16_16_16_FLOAT:
 119                 *bpe = 8;
 120                 break;
 121         case V_038004_FMT_16_16_16:
 122         case V_038004_FMT_16_16_16_FLOAT:
 123                 *bpe = 6;
 124                 break;
 125         case V_038004_FMT_32_32_32:
 126         case V_038004_FMT_32_32_32_FLOAT:
 127                 *bpe = 12;
 128                 break;
 129         case V_038004_COLOR_32_32_32_32:
 130         case V_038004_COLOR_32_32_32_32_FLOAT:
 131                 *bpe = 16;
 132                 break;
 133         case V_038004_FMT_GB_GR:
 134         case V_038004_FMT_BG_RG:
 135         case V_038004_COLOR_INVALID:
 136         default:
 137                 *bpe = 16;
 138                 return -EINVAL;
 139         }
 140         return 0;
 141 }
 142
 143 static void r600_cs_track_init(struct r600_cs_track *track)
 144 {
 145         int i;
 146
 147         /* assume DX9 mode */
 148         track->sq_config = DX9_CONSTS;
 149         for (i = 0; i < 8; i++) {
 150                 track->cb_color_base_last[i] = 0;
 151                 track->cb_color_size[i] = 0;
 152                 track->cb_color_size_idx[i] = 0;
 153                 track->cb_color_info[i] = 0;
 154                 track->cb_color_bo[i] = NULL;
 155                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 156         }
 157         track->cb_target_mask = 0xFFFFFFFF;
 158         track->cb_shader_mask = 0xFFFFFFFF;
 159         track->db_bo = NULL;
 160         /* assume the biggest format and that htile is enabled */
 161         track->db_depth_info = 7 | (1 << 25);
 162         track->db_depth_view = 0xFFFFC000;
 163         track->db_depth_size = 0xFFFFFFFF;
 164         track->db_depth_size_idx = 0;
 165         track->db_depth_control = 0xFFFFFFFF;
 166 }
 167
 168 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 169 {
 170         struct r600_cs_track *track = p->track;
 171         u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
 172         volatile u32 *ib = p->ib->ptr;
 173         unsigned array_mode;
 174
 175         if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
 176                 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
 177                 return -EINVAL;
 178         }
 179         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
 180         if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
 181                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
 182                          __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
 183                         i, track->cb_color_info[i]);
 184                 return -EINVAL;
 185         }
 186         /* pitch is the number of 8x8 tiles per row */
 187         pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
 188         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
 189         slice_tile_max *= 64;
 190         height = slice_tile_max / (pitch * 8);
 191         if (height > 8192)
 192                 height = 8192;
 193         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
 194         switch (array_mode) {
 195         case V_0280A0_ARRAY_LINEAR_GENERAL:
 196                 /* technically height & 0x7 */
 197                 break;
 198         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 199                 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
 200                 if (!IS_ALIGNED(pitch, pitch_align)) {
 201                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
 202                                  __func__, __LINE__, pitch);
 203                         return -EINVAL;
 204                 }
 205                 if (!IS_ALIGNED(height, 8)) {
 206                         dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
 207                                  __func__, __LINE__, height);
 208                         return -EINVAL;
 209                 }
 210                 break;
 211         case V_0280A0_ARRAY_1D_TILED_THIN1:
 212                 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
 213                 if (!IS_ALIGNED(pitch, pitch_align)) {
 214                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
 215                                  __func__, __LINE__, pitch);
 216                         return -EINVAL;
 217                 }
 218                 /* avoid breaking userspace */
 219                 if (height > 7)
 220                         height &= ~0x7;
 221                 if (!IS_ALIGNED(height, 8)) {
 222                         dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
 223                                  __func__, __LINE__, height);
 224                         return -EINVAL;
 225                 }
 226                 break;
 227         case V_0280A0_ARRAY_2D_TILED_THIN1:
 228                 pitch_align = max((u32)track->nbanks,
 229                                   (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks)) / 8;
 230                 if (!IS_ALIGNED(pitch, pitch_align)) {
 231                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
 232                                 __func__, __LINE__, pitch);
 233                         return -EINVAL;
 234                 }
 235                 if (!IS_ALIGNED((height / 8), track->npipes)) {
 236                         dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
 237                                  __func__, __LINE__, height);
 238                         return -EINVAL;
 239                 }
 240                 break;
 241         default:
 242                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 243                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 244                         track->cb_color_info[i]);
 245                 return -EINVAL;
 246         }
 247         /* check offset */
 248         tmp = height * pitch * 8 * bpe;
 249         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
 250                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
 251                         /* the initial DDX does bad things with the CB size occasionally */
 252                         /* it rounds up height too far for slice tile max but the BO is smaller */
 253                         tmp = (height - 7) * 8 * bpe;
 254                         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
 255                                 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
 256                                 return -EINVAL;
 257                         }
 258                 } else {
 259                         dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
 260                         return -EINVAL;
 261                 }
 262         }
 263         if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
 264                 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
 265                 return -EINVAL;
 266         }
 267         /* limit max tile */
 268         tmp = (height * pitch * 8) >> 6;
 269         if (tmp < slice_tile_max)
 270                 slice_tile_max = tmp;
 271         tmp = S_028060_PITCH_TILE_MAX(pitch - 1) |
 272                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
 273         ib[track->cb_color_size_idx[i]] = tmp;
 274         return 0;
 275 }
 276
 277 static int r600_cs_track_check(struct radeon_cs_parser *p)
 278 {
 279         struct r600_cs_track *track = p->track;
 280         u32 tmp;
 281         int r, i;
 282         volatile u32 *ib = p->ib->ptr;
 283
 284         /* on legacy kernel we don't perform advanced check */
 285         if (p->rdev == NULL)
 286                 return 0;
 287         /* we don't support out buffer yet */
 288         if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
 289                 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
 290                 return -EINVAL;
 291         }
 292         /* check that we have a cb for each enabled target, we don't check
 293          * shader_mask because it seems mesa isn't always setting it :(
 294          */
 295         tmp = track->cb_target_mask;
 296         for (i = 0; i < 8; i++) {
 297                 if ((tmp >> (i * 4)) & 0xF) {
 298                         /* at least one component is enabled */
 299                         if (track->cb_color_bo[i] == NULL) {
 300                                 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 301                                         __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 302                                 return -EINVAL;
 303                         }
 304                         /* perform rewrite of CB_COLOR[0-7]_SIZE */
 305                         r = r600_cs_track_validate_cb(p, i);
 306                         if (r)
 307                                 return r;
 308                 }
 309         }
 310         /* Check depth buffer */
 311         if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
 312                 G_028800_Z_ENABLE(track->db_depth_control)) {
 313                 u32 nviews, bpe, ntiles, pitch, pitch_align, height, size, slice_tile_max;
 314                 if (track->db_bo == NULL) {
 315                         dev_warn(p->dev, "z/stencil with no depth buffer\n");
 316                         return -EINVAL;
 317                 }
 318                 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
 319                         dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
 320                         return -EINVAL;
 321                 }
 322                 switch (G_028010_FORMAT(track->db_depth_info)) {
 323                 case V_028010_DEPTH_16:
 324                         bpe = 2;
 325                         break;
 326                 case V_028010_DEPTH_X8_24:
 327                 case V_028010_DEPTH_8_24:
 328                 case V_028010_DEPTH_X8_24_FLOAT:
 329                 case V_028010_DEPTH_8_24_FLOAT:
 330                 case V_028010_DEPTH_32_FLOAT:
 331                         bpe = 4;
 332                         break;
 333                 case V_028010_DEPTH_X24_8_32_FLOAT:
 334                         bpe = 8;
 335                         break;
 336                 default:
 337                         dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
 338                         return -EINVAL;
 339                 }
 340                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
 341                         if (!track->db_depth_size_idx) {
 342                                 dev_warn(p->dev, "z/stencil buffer size not set\n");
 343                                 return -EINVAL;
 344                         }
 345                         tmp = radeon_bo_size(track->db_bo) - track->db_offset;
 346                         tmp = (tmp / bpe) >> 6;
 347                         if (!tmp) {
 348                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
 349                                                 track->db_depth_size, bpe, track->db_offset,
 350                                                 radeon_bo_size(track->db_bo));
 351                                 return -EINVAL;
 352                         }
 353                         ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
 354                 } else {
 355                         size = radeon_bo_size(track->db_bo);
 356                         pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
 357                         slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 358                         slice_tile_max *= 64;
 359                         height = slice_tile_max / (pitch * 8);
 360                         if (height > 8192)
 361                                 height = 8192;
 362                         switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
 363                         case V_028010_ARRAY_1D_TILED_THIN1:
 364                                 pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
 365                                 if (!IS_ALIGNED(pitch, pitch_align)) {
 366                                         dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
 367                                                  __func__, __LINE__, pitch);
 368                                         return -EINVAL;
 369                                 }
 370                                 /* don't break userspace */
 371                                 height &= ~0x7;
 372                                 if (!IS_ALIGNED(height, 8)) {
 373                                         dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
 374                                                  __func__, __LINE__, height);
 375                                         return -EINVAL;
 376                                 }
 377                                 break;
 378                         case V_028010_ARRAY_2D_TILED_THIN1:
 379                                 pitch_align = max((u32)track->nbanks,
 380                                                   (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
 381                                 if (!IS_ALIGNED(pitch, pitch_align)) {
 382                                         dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
 383                                                  __func__, __LINE__, pitch);
 384                                         return -EINVAL;
 385                                 }
 386                                 if (!IS_ALIGNED((height / 8), track->npipes)) {
 387                                         dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
 388                                                  __func__, __LINE__, height);
 389                                         return -EINVAL;
 390                                 }
 391                                 break;
 392                         default:
 393                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 394                                          G_028010_ARRAY_MODE(track->db_depth_info),
 395                                          track->db_depth_info);
 396                                 return -EINVAL;
 397                         }
 398                         if (!IS_ALIGNED(track->db_offset, track->group_size)) {
 399                                 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset);
 400                                 return -EINVAL;
 401                         }
 402                         ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 403                         nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
 404                         tmp = ntiles * bpe * 64 * nviews;
 405                         if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
 406                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
 407                                                 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
 408                                                 radeon_bo_size(track->db_bo));
 409                                 return -EINVAL;
 410                         }
 411                 }
 412         }
 413         return 0;
 414 }
 415
 416 /**
 417  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
 418  * @parser:     parser structure holding parsing context.
 419  * @pkt:        where to store packet informations
 420  *
 421  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 422  * if packet is bigger than remaining ib size. or if packets is unknown.
 423  **/
 424 int r600_cs_packet_parse(struct radeon_cs_parser *p,
 425                         struct radeon_cs_packet *pkt,
 426                         unsigned idx)
 427 {
 428         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 429         uint32_t header;
 430
 431         if (idx >= ib_chunk->length_dw) {
 432                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 433                           idx, ib_chunk->length_dw);
 434                 return -EINVAL;
 435         }
 436         header = radeon_get_ib_value(p, idx);
 437         pkt->idx = idx;
 438         pkt->type = CP_PACKET_GET_TYPE(header);
 439         pkt->count = CP_PACKET_GET_COUNT(header);
 440         pkt->one_reg_wr = 0;
 441         switch (pkt->type) {
 442         case PACKET_TYPE0:
 443                 pkt->reg = CP_PACKET0_GET_REG(header);
 444                 break;
 445         case PACKET_TYPE3:
 446                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 447                 break;
 448         case PACKET_TYPE2:
 449                 pkt->count = -1;
 450                 break;
 451         default:
 452                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 453                 return -EINVAL;
 454         }
 455         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 456                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 457                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 458                 return -EINVAL;
 459         }
 460         return 0;
 461 }
 462
 463 /**
 464  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
 465  * @parser:             parser structure holding parsing context.
 466  * @data:               pointer to relocation data
 467  * @offset_start:       starting offset
 468  * @offset_mask:        offset mask (to align start offset on)
 469  * @reloc:              reloc informations
 470  *
 471  * Check next packet is relocation packet3, do bo validation and compute
 472  * GPU offset using the provided start.
 473  **/
 474 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
 475                                         struct radeon_cs_reloc **cs_reloc)
 476 {
 477         struct radeon_cs_chunk *relocs_chunk;
 478         struct radeon_cs_packet p3reloc;
 479         unsigned idx;
 480         int r;
 481
 482         if (p->chunk_relocs_idx == -1) {
 483                 DRM_ERROR("No relocation chunk !\n");
 484                 return -EINVAL;
 485         }
 486         *cs_reloc = NULL;
 487         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 488         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 489         if (r) {
 490                 return r;
 491         }
 492         p->idx += p3reloc.count + 2;
 493         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 494                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 495                           p3reloc.idx);
 496                 return -EINVAL;
 497         }
 498         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 499         if (idx >= relocs_chunk->length_dw) {
 500                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 501                           idx, relocs_chunk->length_dw);
 502                 return -EINVAL;
 503         }
 504         /* FIXME: we assume reloc size is 4 dwords */
 505         *cs_reloc = p->relocs_ptr[(idx / 4)];
 506         return 0;
 507 }
 508
 509 /**
 510  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
 511  * @parser:             parser structure holding parsing context.
 512  * @data:               pointer to relocation data
 513  * @offset_start:       starting offset
 514  * @offset_mask:        offset mask (to align start offset on)
 515  * @reloc:              reloc informations
 516  *
 517  * Check next packet is relocation packet3, do bo validation and compute
 518  * GPU offset using the provided start.
 519  **/
 520 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
 521                                         struct radeon_cs_reloc **cs_reloc)
 522 {
 523         struct radeon_cs_chunk *relocs_chunk;
 524         struct radeon_cs_packet p3reloc;
 525         unsigned idx;
 526         int r;
 527
 528         if (p->chunk_relocs_idx == -1) {
 529                 DRM_ERROR("No relocation chunk !\n");
 530                 return -EINVAL;
 531         }
 532         *cs_reloc = NULL;
 533         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 534         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 535         if (r) {
 536                 return r;
 537         }
 538         p->idx += p3reloc.count + 2;
 539         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 540                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 541                           p3reloc.idx);
 542                 return -EINVAL;
 543         }
 544         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 545         if (idx >= relocs_chunk->length_dw) {
 546                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 547                           idx, relocs_chunk->length_dw);
 548                 return -EINVAL;
 549         }
 550         *cs_reloc = p->relocs;
 551         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
 552         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
 553         return 0;
 554 }
 555
 556 /**
 557  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
 558  * @parser:             parser structure holding parsing context.
 559  *
 560  * Check next packet is relocation packet3, do bo validation and compute
 561  * GPU offset using the provided start.
 562  **/
 563 static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 564 {
 565         struct radeon_cs_packet p3reloc;
 566         int r;
 567
 568         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 569         if (r) {
 570                 return 0;
 571         }
 572         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 573                 return 0;
 574         }
 575         return 1;
 576 }
 577
 578 /**
 579  * r600_cs_packet_next_vline() - parse userspace VLINE packet
 580  * @parser:             parser structure holding parsing context.
 581  *
 582  * Userspace sends a special sequence for VLINE waits.
 583  * PACKET0 - VLINE_START_END + value
 584  * PACKET3 - WAIT_REG_MEM poll vline status reg
 585  * RELOC (P3) - crtc_id in reloc.
 586  *
 587  * This function parses this and relocates the VLINE START END
 588  * and WAIT_REG_MEM packets to the correct crtc.
 589  * It also detects a switched off crtc and nulls out the
 590  * wait in that case.
 591  */
 592 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 593 {
 594         struct drm_mode_object *obj;
 595         struct drm_crtc *crtc;
 596         struct radeon_crtc *radeon_crtc;
 597         struct radeon_cs_packet p3reloc, wait_reg_mem;
 598         int crtc_id;
 599         int r;
 600         uint32_t header, h_idx, reg, wait_reg_mem_info;
 601         volatile uint32_t *ib;
 602
 603         ib = p->ib->ptr;
 604
 605         /* parse the WAIT_REG_MEM */
 606         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
 607         if (r)
 608                 return r;
 609
 610         /* check its a WAIT_REG_MEM */
 611         if (wait_reg_mem.type != PACKET_TYPE3 ||
 612             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
 613                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
 614                 r = -EINVAL;
 615                 return r;
 616         }
 617
 618         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
 619         /* bit 4 is reg (0) or mem (1) */
 620         if (wait_reg_mem_info & 0x10) {
 621                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
 622                 r = -EINVAL;
 623                 return r;
 624         }
 625         /* waiting for value to be equal */
 626         if ((wait_reg_mem_info & 0x7) != 0x3) {
 627                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
 628                 r = -EINVAL;
 629                 return r;
 630         }
 631         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
 632                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
 633                 r = -EINVAL;
 634                 return r;
 635         }
 636
 637         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
 638                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
 639                 r = -EINVAL;
 640                 return r;
 641         }
 642
 643         /* jump over the NOP */
 644         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
 645         if (r)
 646                 return r;
 647
 648         h_idx = p->idx - 2;
 649         p->idx += wait_reg_mem.count + 2;
 650         p->idx += p3reloc.count + 2;
 651
 652         header = radeon_get_ib_value(p, h_idx);
 653         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
 654         reg = CP_PACKET0_GET_REG(header);
 655
 656         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 657         if (!obj) {
 658                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 659                 r = -EINVAL;
 660                 goto out;
 661         }
 662         crtc = obj_to_crtc(obj);
 663         radeon_crtc = to_radeon_crtc(crtc);
 664         crtc_id = radeon_crtc->crtc_id;
 665
 666         if (!crtc->enabled) {
 667                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
 668                 ib[h_idx + 2] = PACKET2(0);
 669                 ib[h_idx + 3] = PACKET2(0);
 670                 ib[h_idx + 4] = PACKET2(0);
 671                 ib[h_idx + 5] = PACKET2(0);
 672                 ib[h_idx + 6] = PACKET2(0);
 673                 ib[h_idx + 7] = PACKET2(0);
 674                 ib[h_idx + 8] = PACKET2(0);
 675         } else if (crtc_id == 1) {
 676                 switch (reg) {
 677                 case AVIVO_D1MODE_VLINE_START_END:
 678                         header &= ~R600_CP_PACKET0_REG_MASK;
 679                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 680                         break;
 681                 default:
 682                         DRM_ERROR("unknown crtc reloc\n");
 683                         r = -EINVAL;
 684                         goto out;
 685                 }
 686                 ib[h_idx] = header;
 687                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
 688         }
 689 out:
 690         return r;
 691 }
 692
 693 static int r600_packet0_check(struct radeon_cs_parser *p,
 694                                 struct radeon_cs_packet *pkt,
 695                                 unsigned idx, unsigned reg)
 696 {
 697         int r;
 698
 699         switch (reg) {
 700         case AVIVO_D1MODE_VLINE_START_END:
 701                 r = r600_cs_packet_parse_vline(p);
 702                 if (r) {
 703                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 704                                         idx, reg);
 705                         return r;
 706                 }
 707                 break;
 708         default:
 709                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
 710                        reg, idx);
 711                 return -EINVAL;
 712         }
 713         return 0;
 714 }
 715
 716 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
 717                                 struct radeon_cs_packet *pkt)
 718 {
 719         unsigned reg, i;
 720         unsigned idx;
 721         int r;
 722
 723         idx = pkt->idx + 1;
 724         reg = pkt->reg;
 725         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
 726                 r = r600_packet0_check(p, pkt, idx, reg);
 727                 if (r) {
 728                         return r;
 729                 }
 730         }
 731         return 0;
 732 }
 733
 734 /**
 735  * r600_cs_check_reg() - check if register is authorized or not
 736  * @parser: parser structure holding parsing context
 737  * @reg: register we are testing
 738  * @idx: index into the cs buffer
 739  *
 740  * This function will test against r600_reg_safe_bm and return 0
 741  * if register is safe. If register is not flag as safe this function
 742  * will test it against a list of register needind special handling.
 743  */
 744 static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
 745 {
 746         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
 747         struct radeon_cs_reloc *reloc;
 748         u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
 749         u32 m, i, tmp, *ib;
 750         int r;
 751
 752         i = (reg >> 7);
 753         if (i > last_reg) {
 754                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
 755                 return -EINVAL;
 756         }
 757         m = 1 << ((reg >> 2) & 31);
 758         if (!(r600_reg_safe_bm[i] & m))
 759                 return 0;
 760         ib = p->ib->ptr;
 761         switch (reg) {
 762         /* force following reg to 0 in an attemp to disable out buffer
 763          * which will need us to better understand how it works to perform
 764          * security check on it (Jerome)
 765          */
 766         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
 767         case R_008C44_SQ_ESGS_RING_SIZE:
 768         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
 769         case R_008C54_SQ_ESTMP_RING_SIZE:
 770         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
 771         case R_008C74_SQ_FBUF_RING_SIZE:
 772         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
 773         case R_008C5C_SQ_GSTMP_RING_SIZE:
 774         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
 775         case R_008C4C_SQ_GSVS_RING_SIZE:
 776         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
 777         case R_008C6C_SQ_PSTMP_RING_SIZE:
 778         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
 779         case R_008C7C_SQ_REDUC_RING_SIZE:
 780         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
 781         case R_008C64_SQ_VSTMP_RING_SIZE:
 782         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
 783                 /* get value to populate the IB don't remove */
 784                 tmp =radeon_get_ib_value(p, idx);
 785                 ib[idx] = 0;
 786                 break;
 787         case SQ_CONFIG:
 788                 track->sq_config = radeon_get_ib_value(p, idx);
 789                 break;
 790         case R_028800_DB_DEPTH_CONTROL:
 791                 track->db_depth_control = radeon_get_ib_value(p, idx);
 792                 break;
 793         case R_028010_DB_DEPTH_INFO:
 794                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
 795                         r = r600_cs_packet_next_reloc(p, &reloc);
 796                         if (r) {
 797                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
 798                                          "0x%04X\n", reg);
 799                                 return -EINVAL;
 800                         }
 801                         track->db_depth_info = radeon_get_ib_value(p, idx);
 802                         ib[idx] &= C_028010_ARRAY_MODE;
 803                         track->db_depth_info &= C_028010_ARRAY_MODE;
 804                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
 805                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
 806                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
 807                         } else {
 808                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
 809                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
 810                         }
 811                 } else
 812                         track->db_depth_info = radeon_get_ib_value(p, idx);
 813                 break;
 814         case R_028004_DB_DEPTH_VIEW:
 815                 track->db_depth_view = radeon_get_ib_value(p, idx);
 816                 break;
 817         case R_028000_DB_DEPTH_SIZE:
 818                 track->db_depth_size = radeon_get_ib_value(p, idx);
 819                 track->db_depth_size_idx = idx;
 820                 break;
 821         case R_028AB0_VGT_STRMOUT_EN:
 822                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
 823                 break;
 824         case R_028B20_VGT_STRMOUT_BUFFER_EN:
 825                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
 826                 break;
 827         case R_028238_CB_TARGET_MASK:
 828                 track->cb_target_mask = radeon_get_ib_value(p, idx);
 829                 break;
 830         case R_02823C_CB_SHADER_MASK:
 831                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
 832                 break;
 833         case R_028C04_PA_SC_AA_CONFIG:
 834                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
 835                 track->nsamples = 1 << tmp;
 836                 break;
 837         case R_0280A0_CB_COLOR0_INFO:
 838         case R_0280A4_CB_COLOR1_INFO:
 839         case R_0280A8_CB_COLOR2_INFO:
 840         case R_0280AC_CB_COLOR3_INFO:
 841         case R_0280B0_CB_COLOR4_INFO:
 842         case R_0280B4_CB_COLOR5_INFO:
 843         case R_0280B8_CB_COLOR6_INFO:
 844         case R_0280BC_CB_COLOR7_INFO:
 845                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
 846                         r = r600_cs_packet_next_reloc(p, &reloc);
 847                         if (r) {
 848                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
 849                                 return -EINVAL;
 850                         }
 851                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
 852                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
 853                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
 854                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
 855                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
 856                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
 857                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
 858                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
 859                         }
 860                 } else {
 861                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
 862                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
 863                 }
 864                 break;
 865         case R_028060_CB_COLOR0_SIZE:
 866         case R_028064_CB_COLOR1_SIZE:
 867         case R_028068_CB_COLOR2_SIZE:
 868         case R_02806C_CB_COLOR3_SIZE:
 869         case R_028070_CB_COLOR4_SIZE:
 870         case R_028074_CB_COLOR5_SIZE:
 871         case R_028078_CB_COLOR6_SIZE:
 872         case R_02807C_CB_COLOR7_SIZE:
 873                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
 874                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
 875                 track->cb_color_size_idx[tmp] = idx;
 876                 break;
 877                 /* This register were added late, there is userspace
 878                  * which does provide relocation for those but set
 879                  * 0 offset. In order to avoid breaking old userspace
 880                  * we detect this and set address to point to last
 881                  * CB_COLOR0_BASE, note that if userspace doesn't set
 882                  * CB_COLOR0_BASE before this register we will report
 883                  * error. Old userspace always set CB_COLOR0_BASE
 884                  * before any of this.
 885                  */
 886         case R_0280E0_CB_COLOR0_FRAG:
 887         case R_0280E4_CB_COLOR1_FRAG:
 888         case R_0280E8_CB_COLOR2_FRAG:
 889         case R_0280EC_CB_COLOR3_FRAG:
 890         case R_0280F0_CB_COLOR4_FRAG:
 891         case R_0280F4_CB_COLOR5_FRAG:
 892         case R_0280F8_CB_COLOR6_FRAG:
 893         case R_0280FC_CB_COLOR7_FRAG:
 894                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
 895                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
 896                         if (!track->cb_color_base_last[tmp]) {
 897                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
 898                                 return -EINVAL;
 899                         }
 900                         ib[idx] = track->cb_color_base_last[tmp];
 901                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
 902                 } else {
 903                         r = r600_cs_packet_next_reloc(p, &reloc);
 904                         if (r) {
 905                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
 906                                 return -EINVAL;
 907                         }
 908                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 909                         track->cb_color_frag_bo[tmp] = reloc->robj;
 910                 }
 911                 break;
 912         case R_0280C0_CB_COLOR0_TILE:
 913         case R_0280C4_CB_COLOR1_TILE:
 914         case R_0280C8_CB_COLOR2_TILE:
 915         case R_0280CC_CB_COLOR3_TILE:
 916         case R_0280D0_CB_COLOR4_TILE:
 917         case R_0280D4_CB_COLOR5_TILE:
 918         case R_0280D8_CB_COLOR6_TILE:
 919         case R_0280DC_CB_COLOR7_TILE:
 920                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
 921                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
 922                         if (!track->cb_color_base_last[tmp]) {
 923                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
 924                                 return -EINVAL;
 925                         }
 926                         ib[idx] = track->cb_color_base_last[tmp];
 927                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
 928                 } else {
 929                         r = r600_cs_packet_next_reloc(p, &reloc);
 930                         if (r) {
 931                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
 932                                 return -EINVAL;
 933                         }
 934                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 935                         track->cb_color_tile_bo[tmp] = reloc->robj;
 936                 }
 937                 break;
 938         case CB_COLOR0_BASE:
 939         case CB_COLOR1_BASE:
 940         case CB_COLOR2_BASE:
 941         case CB_COLOR3_BASE:
 942         case CB_COLOR4_BASE:
 943         case CB_COLOR5_BASE:
 944         case CB_COLOR6_BASE:
 945         case CB_COLOR7_BASE:
 946                 r = r600_cs_packet_next_reloc(p, &reloc);
 947                 if (r) {
 948                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 949                                         "0x%04X\n", reg);
 950                         return -EINVAL;
 951                 }
 952                 tmp = (reg - CB_COLOR0_BASE) / 4;
 953                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
 954                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 955                 track->cb_color_base_last[tmp] = ib[idx];
 956                 track->cb_color_bo[tmp] = reloc->robj;
 957                 break;
 958         case DB_DEPTH_BASE:
 959                 r = r600_cs_packet_next_reloc(p, &reloc);
 960                 if (r) {
 961                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 962                                         "0x%04X\n", reg);
 963                         return -EINVAL;
 964                 }
 965                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
 966                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 967                 track->db_bo = reloc->robj;
 968                 break;
 969         case DB_HTILE_DATA_BASE:
 970         case SQ_PGM_START_FS:
 971         case SQ_PGM_START_ES:
 972         case SQ_PGM_START_VS:
 973         case SQ_PGM_START_GS:
 974         case SQ_PGM_START_PS:
 975         case SQ_ALU_CONST_CACHE_GS_0:
 976         case SQ_ALU_CONST_CACHE_GS_1:
 977         case SQ_ALU_CONST_CACHE_GS_2:
 978         case SQ_ALU_CONST_CACHE_GS_3:
 979         case SQ_ALU_CONST_CACHE_GS_4:
 980         case SQ_ALU_CONST_CACHE_GS_5:
 981         case SQ_ALU_CONST_CACHE_GS_6:
 982         case SQ_ALU_CONST_CACHE_GS_7:
 983         case SQ_ALU_CONST_CACHE_GS_8:
 984         case SQ_ALU_CONST_CACHE_GS_9:
 985         case SQ_ALU_CONST_CACHE_GS_10:
 986         case SQ_ALU_CONST_CACHE_GS_11:
 987         case SQ_ALU_CONST_CACHE_GS_12:
 988         case SQ_ALU_CONST_CACHE_GS_13:
 989         case SQ_ALU_CONST_CACHE_GS_14:
 990         case SQ_ALU_CONST_CACHE_GS_15:
 991         case SQ_ALU_CONST_CACHE_PS_0:
 992         case SQ_ALU_CONST_CACHE_PS_1:
 993         case SQ_ALU_CONST_CACHE_PS_2:
 994         case SQ_ALU_CONST_CACHE_PS_3:
 995         case SQ_ALU_CONST_CACHE_PS_4:
 996         case SQ_ALU_CONST_CACHE_PS_5:
 997         case SQ_ALU_CONST_CACHE_PS_6:
 998         case SQ_ALU_CONST_CACHE_PS_7:
 999         case SQ_ALU_CONST_CACHE_PS_8:
1000         case SQ_ALU_CONST_CACHE_PS_9:
1001         case SQ_ALU_CONST_CACHE_PS_10:
1002         case SQ_ALU_CONST_CACHE_PS_11:
1003         case SQ_ALU_CONST_CACHE_PS_12:
1004         case SQ_ALU_CONST_CACHE_PS_13:
1005         case SQ_ALU_CONST_CACHE_PS_14:
1006         case SQ_ALU_CONST_CACHE_PS_15:
1007         case SQ_ALU_CONST_CACHE_VS_0:
1008         case SQ_ALU_CONST_CACHE_VS_1:
1009         case SQ_ALU_CONST_CACHE_VS_2:
1010         case SQ_ALU_CONST_CACHE_VS_3:
1011         case SQ_ALU_CONST_CACHE_VS_4:
1012         case SQ_ALU_CONST_CACHE_VS_5:
1013         case SQ_ALU_CONST_CACHE_VS_6:
1014         case SQ_ALU_CONST_CACHE_VS_7:
1015         case SQ_ALU_CONST_CACHE_VS_8:
1016         case SQ_ALU_CONST_CACHE_VS_9:
1017         case SQ_ALU_CONST_CACHE_VS_10:
1018         case SQ_ALU_CONST_CACHE_VS_11:
1019         case SQ_ALU_CONST_CACHE_VS_12:
1020         case SQ_ALU_CONST_CACHE_VS_13:
1021         case SQ_ALU_CONST_CACHE_VS_14:
1022         case SQ_ALU_CONST_CACHE_VS_15:
1023                 r = r600_cs_packet_next_reloc(p, &reloc);
1024                 if (r) {
1025                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1026                                         "0x%04X\n", reg);
1027                         return -EINVAL;
1028                 }
1029                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1030                 break;
1031         default:
1032                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1033                 return -EINVAL;
1034         }
1035         return 0;
1036 }
1037
1038 static inline unsigned minify(unsigned size, unsigned levels)
1039 {
1040         size = size >> levels;
1041         if (size < 1)
1042                 size = 1;
1043         return size;
1044 }
1045
1046 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
1047                               unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
1048                               unsigned pitch_align,
1049                               unsigned *l0_size, unsigned *mipmap_size)
1050 {
1051         unsigned offset, i, level, face;
1052         unsigned width, height, depth, rowstride, size;
1053
1054         w0 = minify(w0, 0);
1055         h0 = minify(h0, 0);
1056         d0 = minify(d0, 0);
1057         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1058                 width = minify(w0, i);
1059                 height = minify(h0, i);
1060                 depth = minify(d0, i);
1061                 for(face = 0; face < nfaces; face++) {
1062                         rowstride = ALIGN((width * bpe), pitch_align);
1063                         size = height * rowstride * depth;
1064                         offset += size;
1065                         offset = (offset + 0x1f) & ~0x1f;
1066                 }
1067         }
1068         *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
1069         *mipmap_size = offset;
1070         if (!nlevels)
1071                 *mipmap_size = *l0_size;
1072         if (!blevel)
1073                 *mipmap_size -= *l0_size;
1074 }
1075
1076 /**
1077  * r600_check_texture_resource() - check if register is authorized or not
1078  * @p: parser structure holding parsing context
1079  * @idx: index into the cs buffer
1080  * @texture: texture's bo structure
1081  * @mipmap: mipmap's bo structure
1082  *
1083  * This function will check that the resource has valid field and that
1084  * the texture and mipmap bo object are big enough to cover this resource.
1085  */
1086 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1087                                               struct radeon_bo *texture,
1088                                               struct radeon_bo *mipmap,
1089                                               u32 tiling_flags)
1090 {
1091         struct r600_cs_track *track = p->track;
1092         u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
1093         u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align;
1094
1095         /* on legacy kernel we don't perform advanced check */
1096         if (p->rdev == NULL)
1097                 return 0;
1098
1099         word0 = radeon_get_ib_value(p, idx + 0);
1100         if (tiling_flags & RADEON_TILING_MACRO)
1101                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1102         else if (tiling_flags & RADEON_TILING_MICRO)
1103                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1104         word1 = radeon_get_ib_value(p, idx + 1);
1105         w0 = G_038000_TEX_WIDTH(word0) + 1;
1106         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1107         d0 = G_038004_TEX_DEPTH(word1);
1108         nfaces = 1;
1109         switch (G_038000_DIM(word0)) {
1110         case V_038000_SQ_TEX_DIM_1D:
1111         case V_038000_SQ_TEX_DIM_2D:
1112         case V_038000_SQ_TEX_DIM_3D:
1113                 break;
1114         case V_038000_SQ_TEX_DIM_CUBEMAP:
1115                 nfaces = 6;
1116                 break;
1117         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1118         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1119         case V_038000_SQ_TEX_DIM_2D_MSAA:
1120         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1121         default:
1122                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1123                 return -EINVAL;
1124         }
1125         if (r600_bpe_from_format(&bpe,  G_038004_DATA_FORMAT(word1))) {
1126                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1127                          __func__, __LINE__, G_038004_DATA_FORMAT(word1));
1128                 return -EINVAL;
1129         }
1130
1131         pitch = G_038000_PITCH(word0) + 1;
1132         switch (G_038000_TILE_MODE(word0)) {
1133         case V_038000_ARRAY_LINEAR_GENERAL:
1134                 pitch_align = 1;
1135                 /* XXX check height align */
1136                 break;
1137         case V_038000_ARRAY_LINEAR_ALIGNED:
1138                 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
1139                 if (!IS_ALIGNED(pitch, pitch_align)) {
1140                         dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1141                                  __func__, __LINE__, pitch);
1142                         return -EINVAL;
1143                 }
1144                 /* XXX check height align */
1145                 break;
1146         case V_038000_ARRAY_1D_TILED_THIN1:
1147                 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8;
1148                 if (!IS_ALIGNED(pitch, pitch_align)) {
1149                         dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1150                                  __func__, __LINE__, pitch);
1151                         return -EINVAL;
1152                 }
1153                 /* XXX check height align */
1154                 break;
1155         case V_038000_ARRAY_2D_TILED_THIN1:
1156                 pitch_align = max((u32)track->nbanks,
1157                                   (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
1158                 if (!IS_ALIGNED(pitch, pitch_align)) {
1159                         dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1160                                 __func__, __LINE__, pitch);
1161                         return -EINVAL;
1162                 }
1163                 /* XXX check height align */
1164                 break;
1165         default:
1166                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
1167                          G_038000_TILE_MODE(word0), word0);
1168                 return -EINVAL;
1169         }
1170         /* XXX check offset align */
1171
1172         word0 = radeon_get_ib_value(p, idx + 4);
1173         word1 = radeon_get_ib_value(p, idx + 5);
1174         blevel = G_038010_BASE_LEVEL(word0);
1175         nlevels = G_038014_LAST_LEVEL(word1);
1176         r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe,
1177                           (pitch_align * bpe),
1178                           &l0_size, &mipmap_size);
1179         /* using get ib will give us the offset into the texture bo */
1180         word0 = radeon_get_ib_value(p, idx + 2) << 8;
1181         if ((l0_size + word0) > radeon_bo_size(texture)) {
1182                 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1183                         w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
1184                 return -EINVAL;
1185         }
1186         /* using get ib will give us the offset into the mipmap bo */
1187         word0 = radeon_get_ib_value(p, idx + 3) << 8;
1188         if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1189                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1190                   w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/
1191         }
1192         return 0;
1193 }
1194
1195 static int r600_packet3_check(struct radeon_cs_parser *p,
1196                                 struct radeon_cs_packet *pkt)
1197 {
1198         struct radeon_cs_reloc *reloc;
1199         struct r600_cs_track *track;
1200         volatile u32 *ib;
1201         unsigned idx;
1202         unsigned i;
1203         unsigned start_reg, end_reg, reg;
1204         int r;
1205         u32 idx_value;
1206
1207         track = (struct r600_cs_track *)p->track;
1208         ib = p->ib->ptr;
1209         idx = pkt->idx + 1;
1210         idx_value = radeon_get_ib_value(p, idx);
1211
1212         switch (pkt->opcode) {
1213         case PACKET3_START_3D_CMDBUF:
1214                 if (p->family >= CHIP_RV770 || pkt->count) {
1215                         DRM_ERROR("bad START_3D\n");
1216                         return -EINVAL;
1217                 }
1218                 break;
1219         case PACKET3_CONTEXT_CONTROL:
1220                 if (pkt->count != 1) {
1221                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1222                         return -EINVAL;
1223                 }
1224                 break;
1225         case PACKET3_INDEX_TYPE:
1226         case PACKET3_NUM_INSTANCES:
1227                 if (pkt->count) {
1228                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1229                         return -EINVAL;
1230                 }
1231                 break;
1232         case PACKET3_DRAW_INDEX:
1233                 if (pkt->count != 3) {
1234                         DRM_ERROR("bad DRAW_INDEX\n");
1235                         return -EINVAL;
1236                 }
1237                 r = r600_cs_packet_next_reloc(p, &reloc);
1238                 if (r) {
1239                         DRM_ERROR("bad DRAW_INDEX\n");
1240                         return -EINVAL;
1241                 }
1242                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1243                 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1244                 r = r600_cs_track_check(p);
1245                 if (r) {
1246                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1247                         return r;
1248                 }
1249                 break;
1250         case PACKET3_DRAW_INDEX_AUTO:
1251                 if (pkt->count != 1) {
1252                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1253                         return -EINVAL;
1254                 }
1255                 r = r600_cs_track_check(p);
1256                 if (r) {
1257                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1258                         return r;
1259                 }
1260                 break;
1261         case PACKET3_DRAW_INDEX_IMMD_BE:
1262         case PACKET3_DRAW_INDEX_IMMD:
1263                 if (pkt->count < 2) {
1264                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1265                         return -EINVAL;
1266                 }
1267                 r = r600_cs_track_check(p);
1268                 if (r) {
1269                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1270                         return r;
1271                 }
1272                 break;
1273         case PACKET3_WAIT_REG_MEM:
1274                 if (pkt->count != 5) {
1275                         DRM_ERROR("bad WAIT_REG_MEM\n");
1276                         return -EINVAL;
1277                 }
1278                 /* bit 4 is reg (0) or mem (1) */
1279                 if (idx_value & 0x10) {
1280                         r = r600_cs_packet_next_reloc(p, &reloc);
1281                         if (r) {
1282                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1283                                 return -EINVAL;
1284                         }
1285                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1286                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1287                 }
1288                 break;
1289         case PACKET3_SURFACE_SYNC:
1290                 if (pkt->count != 3) {
1291                         DRM_ERROR("bad SURFACE_SYNC\n");
1292                         return -EINVAL;
1293                 }
1294                 /* 0xffffffff/0x0 is flush all cache flag */
1295                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1296                     radeon_get_ib_value(p, idx + 2) != 0) {
1297                         r = r600_cs_packet_next_reloc(p, &reloc);
1298                         if (r) {
1299                                 DRM_ERROR("bad SURFACE_SYNC\n");
1300                                 return -EINVAL;
1301                         }
1302                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1303                 }
1304                 break;
1305         case PACKET3_EVENT_WRITE:
1306                 if (pkt->count != 2 && pkt->count != 0) {
1307                         DRM_ERROR("bad EVENT_WRITE\n");
1308                         return -EINVAL;
1309                 }
1310                 if (pkt->count) {
1311                         r = r600_cs_packet_next_reloc(p, &reloc);
1312                         if (r) {
1313                                 DRM_ERROR("bad EVENT_WRITE\n");
1314                                 return -EINVAL;
1315                         }
1316                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1317                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1318                 }
1319                 break;
1320         case PACKET3_EVENT_WRITE_EOP:
1321                 if (pkt->count != 4) {
1322                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1323                         return -EINVAL;
1324                 }
1325                 r = r600_cs_packet_next_reloc(p, &reloc);
1326                 if (r) {
1327                         DRM_ERROR("bad EVENT_WRITE\n");
1328                         return -EINVAL;
1329                 }
1330                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1331                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1332                 break;
1333         case PACKET3_SET_CONFIG_REG:
1334                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1335                 end_reg = 4 * pkt->count + start_reg - 4;
1336                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1337                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1338                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1339                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1340                         return -EINVAL;
1341                 }
1342                 for (i = 0; i < pkt->count; i++) {
1343                         reg = start_reg + (4 * i);
1344                         r = r600_cs_check_reg(p, reg, idx+1+i);
1345                         if (r)
1346                                 return r;
1347                 }
1348                 break;
1349         case PACKET3_SET_CONTEXT_REG:
1350                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1351                 end_reg = 4 * pkt->count + start_reg - 4;
1352                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1353                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1354                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1355                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1356                         return -EINVAL;
1357                 }
1358                 for (i = 0; i < pkt->count; i++) {
1359                         reg = start_reg + (4 * i);
1360                         r = r600_cs_check_reg(p, reg, idx+1+i);
1361                         if (r)
1362                                 return r;
1363                 }
1364                 break;
1365         case PACKET3_SET_RESOURCE:
1366                 if (pkt->count % 7) {
1367                         DRM_ERROR("bad SET_RESOURCE\n");
1368                         return -EINVAL;
1369                 }
1370                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1371                 end_reg = 4 * pkt->count + start_reg - 4;
1372                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1373                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1374                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1375                         DRM_ERROR("bad SET_RESOURCE\n");
1376                         return -EINVAL;
1377                 }
1378                 for (i = 0; i < (pkt->count / 7); i++) {
1379                         struct radeon_bo *texture, *mipmap;
1380                         u32 size, offset, base_offset, mip_offset;
1381
1382                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1383                         case SQ_TEX_VTX_VALID_TEXTURE:
1384                                 /* tex base */
1385                                 r = r600_cs_packet_next_reloc(p, &reloc);
1386                                 if (r) {
1387                                         DRM_ERROR("bad SET_RESOURCE\n");
1388                                         return -EINVAL;
1389                                 }
1390                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1391                                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1392                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1393                                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1394                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1395                                 texture = reloc->robj;
1396                                 /* tex mip base */
1397                                 r = r600_cs_packet_next_reloc(p, &reloc);
1398                                 if (r) {
1399                                         DRM_ERROR("bad SET_RESOURCE\n");
1400                                         return -EINVAL;
1401                                 }
1402                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1403                                 mipmap = reloc->robj;
1404                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
1405                                                                 texture, mipmap, reloc->lobj.tiling_flags);
1406                                 if (r)
1407                                         return r;
1408                                 ib[idx+1+(i*7)+2] += base_offset;
1409                                 ib[idx+1+(i*7)+3] += mip_offset;
1410                                 break;
1411                         case SQ_TEX_VTX_VALID_BUFFER:
1412                                 /* vtx base */
1413                                 r = r600_cs_packet_next_reloc(p, &reloc);
1414                                 if (r) {
1415                                         DRM_ERROR("bad SET_RESOURCE\n");
1416                                         return -EINVAL;
1417                                 }
1418                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1419                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1420                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1421                                         /* force size to size of the buffer */
1422                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1423                                                  size + offset, radeon_bo_size(reloc->robj));
1424                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1425                                 }
1426                                 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1427                                 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1428                                 break;
1429                         case SQ_TEX_VTX_INVALID_TEXTURE:
1430                         case SQ_TEX_VTX_INVALID_BUFFER:
1431                         default:
1432                                 DRM_ERROR("bad SET_RESOURCE\n");
1433                                 return -EINVAL;
1434                         }
1435                 }
1436                 break;
1437         case PACKET3_SET_ALU_CONST:
1438                 if (track->sq_config & DX9_CONSTS) {
1439                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1440                         end_reg = 4 * pkt->count + start_reg - 4;
1441                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1442                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1443                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1444                                 DRM_ERROR("bad SET_ALU_CONST\n");
1445                                 return -EINVAL;
1446                         }
1447                 }
1448                 break;
1449         case PACKET3_SET_BOOL_CONST:
1450                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1451                 end_reg = 4 * pkt->count + start_reg - 4;
1452                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1453                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1454                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1455                         DRM_ERROR("bad SET_BOOL_CONST\n");
1456                         return -EINVAL;
1457                 }
1458                 break;
1459         case PACKET3_SET_LOOP_CONST:
1460                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1461                 end_reg = 4 * pkt->count + start_reg - 4;
1462                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1463                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1464                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1465                         DRM_ERROR("bad SET_LOOP_CONST\n");
1466                         return -EINVAL;
1467                 }
1468                 break;
1469         case PACKET3_SET_CTL_CONST:
1470                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1471                 end_reg = 4 * pkt->count + start_reg - 4;
1472                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1473                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1474                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1475                         DRM_ERROR("bad SET_CTL_CONST\n");
1476                         return -EINVAL;
1477                 }
1478                 break;
1479         case PACKET3_SET_SAMPLER:
1480                 if (pkt->count % 3) {
1481                         DRM_ERROR("bad SET_SAMPLER\n");
1482                         return -EINVAL;
1483                 }
1484                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1485                 end_reg = 4 * pkt->count + start_reg - 4;
1486                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1487                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
1488                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
1489                         DRM_ERROR("bad SET_SAMPLER\n");
1490                         return -EINVAL;
1491                 }
1492                 break;
1493         case PACKET3_SURFACE_BASE_UPDATE:
1494                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1495                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1496                         return -EINVAL;
1497                 }
1498                 if (pkt->count) {
1499                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1500                         return -EINVAL;
1501                 }
1502                 break;
1503         case PACKET3_NOP:
1504                 break;
1505         default:
1506                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1507                 return -EINVAL;
1508         }
1509         return 0;
1510 }
1511
1512 int r600_cs_parse(struct radeon_cs_parser *p)
1513 {
1514         struct radeon_cs_packet pkt;
1515         struct r600_cs_track *track;
1516         int r;
1517
1518         if (p->track == NULL) {
1519                 /* initialize tracker, we are in kms */
1520                 track = kzalloc(sizeof(*track), GFP_KERNEL);
1521                 if (track == NULL)
1522                         return -ENOMEM;
1523                 r600_cs_track_init(track);
1524                 if (p->rdev->family < CHIP_RV770) {
1525                         track->npipes = p->rdev->config.r600.tiling_npipes;
1526                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
1527                         track->group_size = p->rdev->config.r600.tiling_group_size;
1528                 } else if (p->rdev->family <= CHIP_RV740) {
1529                         track->npipes = p->rdev->config.rv770.tiling_npipes;
1530                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1531                         track->group_size = p->rdev->config.rv770.tiling_group_size;
1532                 }
1533                 p->track = track;
1534         }
1535         do {
1536                 r = r600_cs_packet_parse(p, &pkt, p->idx);
1537                 if (r) {
1538                         kfree(p->track);
1539                         p->track = NULL;
1540                         return r;
1541                 }
1542                 p->idx += pkt.count + 2;
1543                 switch (pkt.type) {
1544                 case PACKET_TYPE0:
1545                         r = r600_cs_parse_packet0(p, &pkt);
1546                         break;
1547                 case PACKET_TYPE2:
1548                         break;
1549                 case PACKET_TYPE3:
1550                         r = r600_packet3_check(p, &pkt);
1551                         break;
1552                 default:
1553                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1554                         kfree(p->track);
1555                         p->track = NULL;
1556                         return -EINVAL;
1557                 }
1558                 if (r) {
1559                         kfree(p->track);
1560                         p->track = NULL;
1561                         return r;
1562                 }
1563         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1564 #if 0
1565         for (r = 0; r < p->ib->length_dw; r++) {
1566                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
1567                 mdelay(1);
1568         }
1569 #endif
1570         kfree(p->track);
1571         p->track = NULL;
1572         return 0;
1573 }
1574
1575 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1576 {
1577         if (p->chunk_relocs_idx == -1) {
1578                 return 0;
1579         }
1580         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1581         if (p->relocs == NULL) {
1582                 return -ENOMEM;
1583         }
1584         return 0;
1585 }
1586
1587 /**
1588  * cs_parser_fini() - clean parser states
1589  * @parser:     parser structure holding parsing context.
1590  * @error:      error number
1591  *
1592  * If error is set than unvalidate buffer, otherwise just free memory
1593  * used by parsing context.
1594  **/
1595 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1596 {
1597         unsigned i;
1598
1599         kfree(parser->relocs);
1600         for (i = 0; i < parser->nchunks; i++) {
1601                 kfree(parser->chunks[i].kdata);
1602                 kfree(parser->chunks[i].kpage[0]);
1603                 kfree(parser->chunks[i].kpage[1]);
1604         }
1605         kfree(parser->chunks);
1606         kfree(parser->chunks_array);
1607 }
1608
1609 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1610                         unsigned family, u32 *ib, int *l)
1611 {
1612         struct radeon_cs_parser parser;
1613         struct radeon_cs_chunk *ib_chunk;
1614         struct radeon_ib fake_ib;
1615         struct r600_cs_track *track;
1616         int r;
1617
1618         /* initialize tracker */
1619         track = kzalloc(sizeof(*track), GFP_KERNEL);
1620         if (track == NULL)
1621                 return -ENOMEM;
1622         r600_cs_track_init(track);
1623         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1624         /* initialize parser */
1625         memset(&parser, 0, sizeof(struct radeon_cs_parser));
1626         parser.filp = filp;
1627         parser.dev = &dev->pdev->dev;
1628         parser.rdev = NULL;
1629         parser.family = family;
1630         parser.ib = &fake_ib;
1631         parser.track = track;
1632         fake_ib.ptr = ib;
1633         r = radeon_cs_parser_init(&parser, data);
1634         if (r) {
1635                 DRM_ERROR("Failed to initialize parser !\n");
1636                 r600_cs_parser_fini(&parser, r);
1637                 return r;
1638         }
1639         r = r600_cs_parser_relocs_legacy(&parser);
1640         if (r) {
1641                 DRM_ERROR("Failed to parse relocation !\n");
1642                 r600_cs_parser_fini(&parser, r);
1643                 return r;
1644         }
1645         /* Copy the packet into the IB, the parser will read from the
1646          * input memory (cached) and write to the IB (which can be
1647          * uncached). */
1648         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1649         parser.ib->length_dw = ib_chunk->length_dw;
1650         *l = parser.ib->length_dw;
1651         r = r600_cs_parse(&parser);
1652         if (r) {
1653                 DRM_ERROR("Invalid command stream !\n");
1654                 r600_cs_parser_fini(&parser, r);
1655                 return r;
1656         }
1657         r = radeon_cs_finish_pages(&parser);
1658         if (r) {
1659                 DRM_ERROR("Invalid command stream !\n");
1660                 r600_cs_parser_fini(&parser, r);
1661                 return r;
1662         }
1663         r600_cs_parser_fini(&parser, r);
1664         return r;
1665 }
1666
1667 void r600_cs_legacy_init(void)
1668 {
1669         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1670 }