drivers/gpu/drm/radeon/r600_blit_shaders.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29
  30 /*
  31  * R6xx+ cards need to use the 3D engine to blit data which requires
  32  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
  33  * (which normally generates the 3D state) into the DRM, we opt to use
  34  * statically generated state tables.  The regsiter state and shaders
  35  * were hand generated to support blitting functionality.  See the 3D
  36  * driver or documentation for descriptions of the registers and
  37  * shader instructions.
  38  */
  39
  40 const u32 r6xx_default_state[] =
  41 {
  42         0xc0002400, /* START_3D_CMDBUF */
  43         0x00000000,
  44
  45         0xc0012800, /* CONTEXT_CONTROL */
  46         0x80000000,
  47         0x80000000,
  48
  49         0xc0016800,
  50         0x00000010,
  51         0x00008000, /* WAIT_UNTIL */
  52
  53         0xc0016800,
  54         0x00000542,
  55         0x07000003, /* TA_CNTL_AUX */
  56
  57         0xc0016800,
  58         0x000005c5,
  59         0x00000000, /* VC_ENHANCE */
  60
  61         0xc0016800,
  62         0x00000363,
  63         0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
  64
  65         0xc0016800,
  66         0x0000060c,
  67         0x82000000, /* DB_DEBUG */
  68
  69         0xc0016800,
  70         0x0000060e,
  71         0x01020204, /* DB_WATERMARKS */
  72
  73         0xc0026f00,
  74         0x00000000,
  75         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
  76         0x00000000, /* SQ_VTX_START_INST_LOC */
  77
  78         0xc0096900,
  79         0x0000022a,
  80         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
  81         0x00000000,
  82         0x00000000,
  83         0x00000000,
  84         0x00000000,
  85         0x00000000,
  86         0x00000000,
  87         0x00000000,
  88         0x00000000,
  89
  90         0xc0016900,
  91         0x00000004,
  92         0x00000000, /* DB_DEPTH_INFO */
  93
  94         0xc0026900,
  95         0x0000000a,
  96         0x00000000, /* DB_STENCIL_CLEAR */
  97         0x00000000, /* DB_DEPTH_CLEAR */
  98
  99         0xc0016900,
 100         0x00000200,
 101         0x00000000, /* DB_DEPTH_CONTROL */
 102
 103         0xc0026900,
 104         0x00000343,
 105         0x00000060, /* DB_RENDER_CONTROL */
 106         0x00000040, /* DB_RENDER_OVERRIDE */
 107
 108         0xc0016900,
 109         0x00000351,
 110         0x0000aa00, /* DB_ALPHA_TO_MASK */
 111
 112         0xc0036900,
 113         0x00000100,
 114         0x00000800, /* VGT_MAX_VTX_INDX */
 115         0x00000000, /* VGT_MIN_VTX_INDX */
 116         0x00000000, /* VGT_INDX_OFFSET */
 117
 118         0xc0016900,
 119         0x00000103,
 120         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 121
 122         0xc0016900,
 123         0x00000104,
 124         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 125
 126         0xc0076900,
 127         0x00000105,
 128         0x00000000, /* CB_BLEND_RED */
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000, /* CB_FOG_RED */
 133         0x00000000,
 134         0x00000000,
 135
 136         0xc0026900,
 137         0x0000010c,
 138         0x00000000, /* DB_STENCILREFMASK */
 139         0x00000000, /* DB_STENCILREFMASK_BF */
 140
 141         0xc0016900,
 142         0x0000010e,
 143         0x00000000, /* SX_ALPHA_REF */
 144
 145         0xc0046900,
 146         0x0000030c,
 147         0x01000000, /* CB_CLRCMP_CNTL */
 148         0x00000000,
 149         0x00000000,
 150         0x00000000,
 151
 152         0xc0046900,
 153         0x00000048,
 154         0x3f800000, /* CB_CLEAR_RED */
 155         0x00000000,
 156         0x3f800000,
 157         0x3f800000,
 158
 159         0xc0016900,
 160         0x00000080,
 161         0x00000000, /* PA_SC_WINDOW_OFFSET */
 162
 163         0xc00a6900,
 164         0x00000083,
 165         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 166         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 167         0x20002000,
 168         0x00000000,
 169         0x20002000,
 170         0x00000000,
 171         0x20002000,
 172         0x00000000,
 173         0x20002000,
 174         0x00000000, /* PA_SC_EDGERULE */
 175
 176         0xc0406900,
 177         0x00000094,
 178         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 179         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 180         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 181         0x20002000,
 182         0x80000000,
 183         0x20002000,
 184         0x80000000,
 185         0x20002000,
 186         0x80000000,
 187         0x20002000,
 188         0x80000000,
 189         0x20002000,
 190         0x80000000,
 191         0x20002000,
 192         0x80000000,
 193         0x20002000,
 194         0x80000000,
 195         0x20002000,
 196         0x80000000,
 197         0x20002000,
 198         0x80000000,
 199         0x20002000,
 200         0x80000000,
 201         0x20002000,
 202         0x80000000,
 203         0x20002000,
 204         0x80000000,
 205         0x20002000,
 206         0x80000000,
 207         0x20002000,
 208         0x80000000,
 209         0x20002000,
 210         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 211         0x3f800000,
 212         0x00000000,
 213         0x3f800000,
 214         0x00000000,
 215         0x3f800000,
 216         0x00000000,
 217         0x3f800000,
 218         0x00000000,
 219         0x3f800000,
 220         0x00000000,
 221         0x3f800000,
 222         0x00000000,
 223         0x3f800000,
 224         0x00000000,
 225         0x3f800000,
 226         0x00000000,
 227         0x3f800000,
 228         0x00000000,
 229         0x3f800000,
 230         0x00000000,
 231         0x3f800000,
 232         0x00000000,
 233         0x3f800000,
 234         0x00000000,
 235         0x3f800000,
 236         0x00000000,
 237         0x3f800000,
 238         0x00000000,
 239         0x3f800000,
 240         0x00000000,
 241         0x3f800000,
 242
 243         0xc0016900,
 244         0x00000292,
 245         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 246
 247         0xc0016900,
 248         0x00000293,
 249         0x00004010, /* PA_SC_MODE_CNTL */
 250
 251         0xc0066900,
 252         0x0000010f,
 253         0x00000000, /* PA_CL_VPORT_0_XSCALE */
 254         0x00000000,
 255         0x00000000,
 256         0x00000000,
 257         0x00000000,
 258         0x00000000,
 259
 260         0xc0026900,
 261         0x00000300,
 262         0x00000000, /* PA_SC_LINE_CNTL */
 263         0x00000000, /* PA_SC_AA_CONFIG */
 264
 265         0xc0016900,
 266         0x00000302,
 267         0x0000002d, /* PA_SU_VTX_CNTL */
 268
 269         0xc0046900,
 270         0x00000303,
 271         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 272         0x3f800000,
 273         0x3f800000,
 274         0x3f800000,
 275
 276         0xc0026900,
 277         0x00000307,
 278         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 279         0x00000000,
 280
 281         0xc0016900,
 282         0x00000312,
 283         0xffffffff, /* PA_SC_AA_MASK */
 284
 285         0xc0016900,
 286         0x0000037e,
 287         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 288
 289         0xc0016900,
 290         0x0000037f,
 291         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 292
 293         0xc0016900,
 294         0x00000380,
 295         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 296
 297         0xc0016900,
 298         0x00000381,
 299         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 300
 301         0xc0016900,
 302         0x00000382,
 303         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 304
 305         0xc0016900,
 306         0x00000383,
 307         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 308
 309         0xc0046900,
 310         0x000001b6,
 311         0x00000000, /* SPI_INPUT_Z */
 312         0x00000000, /* SPI_FOG_CNTL */
 313         0x00000000, /* SPI_FOG_FUNC_SCALE */
 314         0x00000000, /* SPI_FOG_FUNC_BIAS */
 315
 316         0xc0016900,
 317         0x00000225,
 318         0x00000000, /* SQ_PGM_START_FS */
 319
 320         0xc0016900,
 321         0x00000229,
 322         0x00000000, /* SQ_PGM_RESOURCES_FS */
 323
 324         0xc0016900,
 325         0x00000237,
 326         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 327
 328         0xc0026900,
 329         0x000002a8,
 330         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 331         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 332
 333         0xc0026900,
 334         0x00000280,
 335         0x00000000, /* PA_SU_POINT_SIZE */
 336         0x00000000, /* PA_SU_POINT_MINMAX */
 337
 338         0xc0016900,
 339         0x00000282,
 340         0x00000008, /* PA_SU_LINE_CNTL */
 341
 342         0xc0016900,
 343         0x00000283,
 344         0x00000000, /* PA_SC_LINE_STIPPLE */
 345
 346         0xc0016900,
 347         0x00000284,
 348         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 349
 350         0xc0016900,
 351         0x00000285,
 352         0x00000000, /* VGT_HOS_CNTL */
 353
 354         0xc00a6900,
 355         0x00000286,
 356         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 357         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 358         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 359         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 360         0x00000000, /* VGT_GROUP_FIRST_DECR */
 361         0x00000000, /* VGT_GROUP_DECR */
 362         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 363         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 364         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 365         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 366
 367         0xc0016900,
 368         0x00000290,
 369         0x00000000, /* VGT_GS_MODE */
 370
 371         0xc0016900,
 372         0x000002a1,
 373         0x00000000, /* VGT_PRIMITIVEID_EN */
 374
 375         0xc0016900,
 376         0x000002a5,
 377         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 378
 379         0xc0036900,
 380         0x000002ac,
 381         0x00000000, /* VGT_STRMOUT_EN */
 382         0x00000000, /* VGT_REUSE_OFF */
 383         0x00000000, /* VGT_VTX_CNT_EN */
 384
 385         0xc0016900,
 386         0x000002c8,
 387         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 388
 389         0xc0016900,
 390         0x00000202,
 391         0x00cc0000, /* CB_COLOR_CONTROL */
 392
 393         0xc0016900,
 394         0x00000203,
 395         0x00000210, /* DB_SHADER_CNTL */
 396
 397         0xc0016900,
 398         0x00000204,
 399         0x00010000, /* PA_CL_CLIP_CNTL */
 400
 401         0xc0016900,
 402         0x00000205,
 403         0x00000244, /* PA_SU_SC_MODE_CNTL */
 404
 405         0xc0016900,
 406         0x00000206,
 407         0x00000100, /* PA_CL_VTE_CNTL */
 408
 409         0xc0026900,
 410         0x00000207,
 411         0x00000000, /* PA_CL_VS_OUT_CNTL */
 412         0x00000000, /* PA_CL_NANINF_CNTL */
 413
 414         0xc0016900,
 415         0x0000008e,
 416         0x0000000f, /* CB_TARGET_MASK */
 417
 418         0xc0016900,
 419         0x0000008f,
 420         0x0000000f, /* CB_SHADER_MASK */
 421
 422         0xc0016900,
 423         0x000001e8,
 424         0x00000001, /* CB_SHADER_CONTROL */
 425
 426         0xc0016900,
 427         0x00000185,
 428         0x00000000, /* SPI_VS_OUT_ID_0 */
 429
 430         0xc0016900,
 431         0x00000191,
 432         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 433
 434         0xc0016900,
 435         0x000001b1,
 436         0x00000000, /* SPI_VS_OUT_CONFIG */
 437
 438         0xc0016900,
 439         0x000001b2,
 440         0x00000000, /* SPI_THREAD_GROUPING */
 441
 442         0xc0026900,
 443         0x000001b3,
 444         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 445         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 446
 447         0xc0016900,
 448         0x000001b5,
 449         0x00000000, /* SPI_INTERP_CONTROL_0 */
 450
 451         0xc0036e00, /* SET_SAMPLER */
 452         0x00000000,
 453         0x00000012,
 454         0x00000000,
 455         0x00000000,
 456 };
 457
 458 const u32 r7xx_default_state[] =
 459 {
 460         0xc0012800, /* CONTEXT_CONTROL */
 461         0x80000000,
 462         0x80000000,
 463
 464         0xc0016800,
 465         0x00000010,
 466         0x00008000, /* WAIT_UNTIL */
 467
 468         0xc0016800,
 469         0x00000542,
 470         0x07000002, /* TA_CNTL_AUX */
 471
 472         0xc0016800,
 473         0x000005c5,
 474         0x00000000, /* VC_ENHANCE */
 475
 476         0xc0016800,
 477         0x00000363,
 478         0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
 479
 480         0xc0016800,
 481         0x0000060c,
 482         0x00000000, /* DB_DEBUG */
 483
 484         0xc0016800,
 485         0x0000060e,
 486         0x00420204, /* DB_WATERMARKS */
 487
 488         0xc0026f00,
 489         0x00000000,
 490         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
 491         0x00000000, /* SQ_VTX_START_INST_LOC */
 492
 493         0xc0096900,
 494         0x0000022a,
 495         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
 496         0x00000000,
 497         0x00000000,
 498         0x00000000,
 499         0x00000000,
 500         0x00000000,
 501         0x00000000,
 502         0x00000000,
 503         0x00000000,
 504
 505         0xc0016900,
 506         0x00000004,
 507         0x00000000, /* DB_DEPTH_INFO */
 508
 509         0xc0026900,
 510         0x0000000a,
 511         0x00000000, /* DB_STENCIL_CLEAR */
 512         0x00000000, /* DB_DEPTH_CLEAR */
 513
 514         0xc0016900,
 515         0x00000200,
 516         0x00000000, /* DB_DEPTH_CONTROL */
 517
 518         0xc0026900,
 519         0x00000343,
 520         0x00000060, /* DB_RENDER_CONTROL */
 521         0x00000000, /* DB_RENDER_OVERRIDE */
 522
 523         0xc0016900,
 524         0x00000351,
 525         0x0000aa00, /* DB_ALPHA_TO_MASK */
 526
 527         0xc0036900,
 528         0x00000100,
 529         0x00000800, /* VGT_MAX_VTX_INDX */
 530         0x00000000, /* VGT_MIN_VTX_INDX */
 531         0x00000000, /* VGT_INDX_OFFSET */
 532
 533         0xc0016900,
 534         0x00000103,
 535         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 536
 537         0xc0016900,
 538         0x00000104,
 539         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 540
 541         0xc0046900,
 542         0x00000105,
 543         0x00000000, /* CB_BLEND_RED */
 544         0x00000000,
 545         0x00000000,
 546         0x00000000,
 547
 548         0xc0026900,
 549         0x0000010c,
 550         0x00000000, /* DB_STENCILREFMASK */
 551         0x00000000, /* DB_STENCILREFMASK_BF */
 552
 553         0xc0016900,
 554         0x0000010e,
 555         0x00000000, /* SX_ALPHA_REF */
 556
 557         0xc0046900,
 558         0x0000030c, /* CB_CLRCMP_CNTL */
 559         0x01000000,
 560         0x00000000,
 561         0x00000000,
 562         0x00000000,
 563
 564         0xc0016900,
 565         0x00000080,
 566         0x00000000, /* PA_SC_WINDOW_OFFSET */
 567
 568         0xc00a6900,
 569         0x00000083,
 570         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 571         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 572         0x20002000,
 573         0x00000000,
 574         0x20002000,
 575         0x00000000,
 576         0x20002000,
 577         0x00000000,
 578         0x20002000,
 579         0xaaaaaaaa, /* PA_SC_EDGERULE */
 580
 581         0xc0406900,
 582         0x00000094,
 583         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 584         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 585         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 586         0x20002000,
 587         0x80000000,
 588         0x20002000,
 589         0x80000000,
 590         0x20002000,
 591         0x80000000,
 592         0x20002000,
 593         0x80000000,
 594         0x20002000,
 595         0x80000000,
 596         0x20002000,
 597         0x80000000,
 598         0x20002000,
 599         0x80000000,
 600         0x20002000,
 601         0x80000000,
 602         0x20002000,
 603         0x80000000,
 604         0x20002000,
 605         0x80000000,
 606         0x20002000,
 607         0x80000000,
 608         0x20002000,
 609         0x80000000,
 610         0x20002000,
 611         0x80000000,
 612         0x20002000,
 613         0x80000000,
 614         0x20002000,
 615         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 616         0x3f800000,
 617         0x00000000,
 618         0x3f800000,
 619         0x00000000,
 620         0x3f800000,
 621         0x00000000,
 622         0x3f800000,
 623         0x00000000,
 624         0x3f800000,
 625         0x00000000,
 626         0x3f800000,
 627         0x00000000,
 628         0x3f800000,
 629         0x00000000,
 630         0x3f800000,
 631         0x00000000,
 632         0x3f800000,
 633         0x00000000,
 634         0x3f800000,
 635         0x00000000,
 636         0x3f800000,
 637         0x00000000,
 638         0x3f800000,
 639         0x00000000,
 640         0x3f800000,
 641         0x00000000,
 642         0x3f800000,
 643         0x00000000,
 644         0x3f800000,
 645         0x00000000,
 646         0x3f800000,
 647
 648         0xc0016900,
 649         0x00000292,
 650         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 651
 652         0xc0016900,
 653         0x00000293,
 654         0x00514000, /* PA_SC_MODE_CNTL */
 655
 656         0xc0066900,
 657         0x0000010f,
 658         0x00000000, /* PA_CL_VPORT_0_XSCALE */
 659         0x00000000,
 660         0x00000000,
 661         0x00000000,
 662         0x00000000,
 663         0x00000000,
 664
 665         0xc0026900,
 666         0x00000300,
 667         0x00000000, /* PA_SC_LINE_CNTL */
 668         0x00000000, /* PA_SC_AA_CONFIG */
 669
 670         0xc0016900,
 671         0x00000302,
 672         0x0000002d, /* PA_SU_VTX_CNTL */
 673
 674         0xc0046900,
 675         0x00000303,
 676         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 677         0x3f800000,
 678         0x3f800000,
 679         0x3f800000,
 680
 681         0xc0026900,
 682         0x00000307,
 683         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 684         0x00000000,
 685
 686         0xc0016900,
 687         0x00000312,
 688         0xffffffff, /* PA_SC_AA_MASK */
 689
 690         0xc0016900,
 691         0x0000037e,
 692         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 693
 694         0xc0016900,
 695         0x0000037f,
 696         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 697
 698         0xc0016900,
 699         0x00000380,
 700         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 701
 702         0xc0016900,
 703         0x00000381,
 704         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 705
 706         0xc0016900,
 707         0x00000382,
 708         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 709
 710         0xc0016900,
 711         0x00000383,
 712         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 713
 714         0xc0046900,
 715         0x000001b6,
 716         0x00000000, /* SPI_INPUT_Z */
 717         0x00000000, /* SPI_FOG_CNTL */
 718         0x00000000, /* SPI_FOG_FUNC_SCALE */
 719         0x00000000, /* SPI_FOG_FUNC_BIAS */
 720
 721         0xc0016900,
 722         0x00000225,
 723         0x00000000, /* SQ_PGM_START_FS */
 724
 725         0xc0016900,
 726         0x00000229,
 727         0x00000000, /* SQ_PGM_RESOURCES_FS */
 728
 729         0xc0016900,
 730         0x00000237,
 731         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 732
 733         0xc0026900,
 734         0x000002a8,
 735         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 736         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 737
 738         0xc0026900,
 739         0x00000280,
 740         0x00000000, /* PA_SU_POINT_SIZE */
 741         0x00000000, /* PA_SU_POINT_MINMAX */
 742
 743         0xc0016900,
 744         0x00000282,
 745         0x00000008, /* PA_SU_LINE_CNTL */
 746
 747         0xc0016900,
 748         0x00000283,
 749         0x00000000, /* PA_SC_LINE_STIPPLE */
 750
 751         0xc0016900,
 752         0x00000284,
 753         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 754
 755         0xc00b6900,
 756         0x00000285,
 757         0x00000000, /* VGT_HOS_CNTL */
 758         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 759         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 760         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 761         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 762         0x00000000, /* VGT_GROUP_FIRST_DECR */
 763         0x00000000, /* VGT_GROUP_DECR */
 764         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 765         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 766         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 767         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 768
 769         0xc0016900,
 770         0x00000290,
 771         0x00000000, /* VGT_GS_MODE */
 772
 773         0xc0016900,
 774         0x000002a1,
 775         0x00000000, /* VGT_PRIMITIVEID_EN */
 776
 777         0xc0016900,
 778         0x000002a5,
 779         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 780
 781         0xc0036900,
 782         0x000002ac,
 783         0x00000000, /* VGT_STRMOUT_EN */
 784         0x00000000, /* VGT_REUSE_OFF */
 785         0x00000000, /* VGT_VTX_CNT_EN */
 786
 787         0xc0016900,
 788         0x000002c8,
 789         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 790
 791         0xc0016900,
 792         0x00000202,
 793         0x00cc0000, /* CB_COLOR_CONTROL */
 794
 795         0xc0016900,
 796         0x00000203,
 797         0x00000210, /* DB_SHADER_CNTL */
 798
 799         0xc0016900,
 800         0x00000204,
 801         0x00010000, /* PA_CL_CLIP_CNTL */
 802
 803         0xc0016900,
 804         0x00000205,
 805         0x00000244, /* PA_SU_SC_MODE_CNTL */
 806
 807         0xc0016900,
 808         0x00000206,
 809         0x00000100, /* PA_CL_VTE_CNTL */
 810
 811         0xc0026900,
 812         0x00000207,
 813         0x00000000, /* PA_CL_VS_OUT_CNTL */
 814         0x00000000, /* PA_CL_NANINF_CNTL */
 815
 816         0xc0016900,
 817         0x0000008e,
 818         0x0000000f, /* CB_TARGET_MASK */
 819
 820         0xc0016900,
 821         0x0000008f,
 822         0x0000000f, /* CB_SHADER_MASK */
 823
 824         0xc0016900,
 825         0x000001e8,
 826         0x00000001, /* CB_SHADER_CONTROL */
 827
 828         0xc0016900,
 829         0x00000185,
 830         0x00000000, /* SPI_VS_OUT_ID_0 */
 831
 832         0xc0016900,
 833         0x00000191,
 834         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 835
 836         0xc0016900,
 837         0x000001b1,
 838         0x00000000, /* SPI_VS_OUT_CONFIG */
 839
 840         0xc0016900,
 841         0x000001b2,
 842         0x00000001, /* SPI_THREAD_GROUPING */
 843
 844         0xc0026900,
 845         0x000001b3,
 846         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 847         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 848
 849         0xc0016900,
 850         0x000001b5,
 851         0x00000000, /* SPI_INTERP_CONTROL_0 */
 852
 853         0xc0036e00, /* SET_SAMPLER */
 854         0x00000000,
 855         0x00000012,
 856         0x00000000,
 857         0x00000000,
 858 };
 859
 860 /* same for r6xx/r7xx */
 861 const u32 r6xx_vs[] =
 862 {
 863         0x00000004,
 864         0x81000000,
 865         0x0000203c,
 866         0x94000b08,
 867         0x00004000,
 868         0x14200b1a,
 869         0x00000000,
 870         0x00000000,
 871         0x3c000000,
 872         0x68cd1000,
 873         0x00080000,
 874         0x00000000,
 875 };
 876
 877 const u32 r6xx_ps[] =
 878 {
 879         0x00000002,
 880         0x80800000,
 881         0x00000000,
 882         0x94200688,
 883         0x00000010,
 884         0x000d1000,
 885         0xb0800000,
 886         0x00000000,
 887 };
 888
 889 const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
 890 const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
 891 const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
 892 const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);