drivers/gpu/drm/radeon/r600_blit_shaders.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29
  30 /*
  31  * R6xx+ cards need to use the 3D engine to blit data which requires
  32  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
  33  * (which normally generates the 3D state) into the DRM, we opt to use
  34  * statically generated state tables.  The regsiter state and shaders
  35  * were hand generated to support blitting functionality.  See the 3D
  36  * driver or documentation for descriptions of the registers and
  37  * shader instructions.
  38  */
  39
  40 const u32 r6xx_default_state[] =
  41 {
  42         0xc0002400, /* START_3D_CMDBUF */
  43         0x00000000,
  44
  45         0xc0012800, /* CONTEXT_CONTROL */
  46         0x80000000,
  47         0x80000000,
  48
  49         0xc0016800,
  50         0x00000010,
  51         0x00008000, /* WAIT_UNTIL */
  52
  53         0xc0016800,
  54         0x00000542,
  55         0x07000003, /* TA_CNTL_AUX */
  56
  57         0xc0016800,
  58         0x000005c5,
  59         0x00000000, /* VC_ENHANCE */
  60
  61         0xc0016800,
  62         0x00000363,
  63         0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
  64
  65         0xc0016800,
  66         0x0000060c,
  67         0x82000000, /* DB_DEBUG */
  68
  69         0xc0016800,
  70         0x0000060e,
  71         0x01020204, /* DB_WATERMARKS */
  72
  73         0xc0026f00,
  74         0x00000000,
  75         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
  76         0x00000000, /* SQ_VTX_START_INST_LOC */
  77
  78         0xc0096900,
  79         0x0000022a,
  80         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
  81         0x00000000,
  82         0x00000000,
  83         0x00000000,
  84         0x00000000,
  85         0x00000000,
  86         0x00000000,
  87         0x00000000,
  88         0x00000000,
  89
  90         0xc0016900,
  91         0x00000004,
  92         0x00000000, /* DB_DEPTH_INFO */
  93
  94         0xc0026900,
  95         0x0000000a,
  96         0x00000000, /* DB_STENCIL_CLEAR */
  97         0x00000000, /* DB_DEPTH_CLEAR */
  98
  99         0xc0026900,
 100         0x0000010c,
 101         0x00000000, /* DB_STENCILREFMASK */
 102         0x00000000, /* DB_STENCILREFMASK_BF */
 103
 104         0xc0016900,
 105         0x00000200,
 106         0x00000000, /* DB_DEPTH_CONTROL */
 107
 108         0xc0026900,
 109         0x00000343,
 110         0x00000060, /* DB_RENDER_CONTROL */
 111         0x00000040, /* DB_RENDER_OVERRIDE */
 112
 113         0xc0016900,
 114         0x00000351,
 115         0x0000aa00, /* DB_ALPHA_TO_MASK */
 116
 117         0xc0016900,
 118         0x00000104,
 119         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 120
 121         0xc0016900,
 122         0x0000010e,
 123         0x00000000, /* SX_ALPHA_REF */
 124
 125         0xc0076900,
 126         0x00000105,
 127         0x00000000, /* CB_BLEND_RED */
 128         0x00000000,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000, /* CB_FOG_RED */
 132         0x00000000,
 133         0x00000000,
 134
 135         0xc0046900,
 136         0x0000030c,
 137         0x01000000, /* CB_CLRCMP_CNTL */
 138         0x00000000,
 139         0x00000000,
 140         0x00000000,
 141
 142         0xc0046900,
 143         0x00000048,
 144         0x3f800000, /* CB_CLEAR_RED */
 145         0x00000000,
 146         0x3f800000,
 147         0x3f800000,
 148
 149         0xc0016900,
 150         0x0000008e,
 151         0x0000000f, /* CB_TARGET_MASK */
 152
 153         0xc0016900,
 154         0x00000080,
 155         0x00000000, /* PA_SC_WINDOW_OFFSET */
 156
 157         0xc00a6900,
 158         0x00000083,
 159         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 160         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 161         0x20002000,
 162         0x00000000,
 163         0x20002000,
 164         0x00000000,
 165         0x20002000,
 166         0x00000000,
 167         0x20002000,
 168         0x00000000, /* PA_SC_EDGERULE */
 169
 170         0xc0026900,
 171         0x00000094,
 172         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 173         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 174
 175         0xc0026900,
 176         0x000000b4,
 177         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 178         0x3f800000,
 179
 180         0xc0026900,
 181         0x00000096,
 182         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 183         0x20002000,
 184
 185         0xc0026900,
 186         0x000000b6,
 187         0x00000000,
 188         0x3f800000,
 189
 190         0xc0026900,
 191         0x00000098,
 192         0x80000000,
 193         0x20002000,
 194
 195         0xc0026900,
 196         0x000000b8,
 197         0x00000000,
 198         0x3f800000,
 199
 200         0xc0026900,
 201         0x0000009a,
 202         0x80000000,
 203         0x20002000,
 204
 205         0xc0026900,
 206         0x000000ba,
 207         0x00000000,
 208         0x3f800000,
 209
 210         0xc0026900,
 211         0x0000009c,
 212         0x80000000,
 213         0x20002000,
 214
 215         0xc0026900,
 216         0x000000bc,
 217         0x00000000,
 218         0x3f800000,
 219
 220         0xc0026900,
 221         0x0000009e,
 222         0x80000000,
 223         0x20002000,
 224
 225         0xc0026900,
 226         0x000000be,
 227         0x00000000,
 228         0x3f800000,
 229
 230         0xc0026900,
 231         0x000000a0,
 232         0x80000000,
 233         0x20002000,
 234
 235         0xc0026900,
 236         0x000000c0,
 237         0x00000000,
 238         0x3f800000,
 239
 240         0xc0026900,
 241         0x000000a2,
 242         0x80000000,
 243         0x20002000,
 244
 245         0xc0026900,
 246         0x000000c2,
 247         0x00000000,
 248         0x3f800000,
 249
 250         0xc0026900,
 251         0x000000a4,
 252         0x80000000,
 253         0x20002000,
 254
 255         0xc0026900,
 256         0x000000c4,
 257         0x00000000,
 258         0x3f800000,
 259
 260         0xc0026900,
 261         0x000000a6,
 262         0x80000000,
 263         0x20002000,
 264
 265         0xc0026900,
 266         0x000000c6,
 267         0x00000000,
 268         0x3f800000,
 269
 270         0xc0026900,
 271         0x000000a8,
 272         0x80000000,
 273         0x20002000,
 274
 275         0xc0026900,
 276         0x000000c8,
 277         0x00000000,
 278         0x3f800000,
 279
 280         0xc0026900,
 281         0x000000aa,
 282         0x80000000,
 283         0x20002000,
 284
 285         0xc0026900,
 286         0x000000ca,
 287         0x00000000,
 288         0x3f800000,
 289
 290         0xc0026900,
 291         0x000000ac,
 292         0x80000000,
 293         0x20002000,
 294
 295         0xc0026900,
 296         0x000000cc,
 297         0x00000000,
 298         0x3f800000,
 299
 300         0xc0026900,
 301         0x000000ae,
 302         0x80000000,
 303         0x20002000,
 304
 305         0xc0026900,
 306         0x000000ce,
 307         0x00000000,
 308         0x3f800000,
 309
 310         0xc0026900,
 311         0x000000b0,
 312         0x80000000,
 313         0x20002000,
 314
 315         0xc0026900,
 316         0x000000d0,
 317         0x00000000,
 318         0x3f800000,
 319
 320         0xc0026900,
 321         0x000000b2,
 322         0x80000000,
 323         0x20002000,
 324
 325         0xc0026900,
 326         0x000000d2,
 327         0x00000000,
 328         0x3f800000,
 329
 330         0xc0016900,
 331         0x00000293,
 332         0x00004010, /* PA_SC_MODE_CNTL */
 333
 334         0xc0026900,
 335         0x00000300,
 336         0x00000000, /* PA_SC_LINE_CNTL */
 337         0x00000000, /* PA_SC_AA_CONFIG */
 338
 339         0xc0016900,
 340         0x00000312,
 341         0xffffffff, /* PA_SC_AA_MASK */
 342
 343         0xc0026900,
 344         0x00000307,
 345         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 346         0x00000000,
 347
 348         0xc0016900,
 349         0x00000283,
 350         0x00000000, /* PA_SC_LINE_STIPPLE */
 351
 352         0xc0016900,
 353         0x00000292,
 354         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 355
 356         0xc0066900,
 357         0x0000010f,
 358         0x00000000, /* PA_CL_VPORT_0_XSCALE */
 359         0x00000000,
 360         0x00000000,
 361         0x00000000,
 362         0x00000000,
 363         0x00000000,
 364
 365         0xc0026900,
 366         0x00000207,
 367         0x00000000, /* PA_CL_VS_OUT_CNTL */
 368         0x00000000, /* PA_CL_NANINF_CNTL */
 369
 370         0xc0046900,
 371         0x00000303,
 372         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 373         0x3f800000,
 374         0x3f800000,
 375         0x3f800000,
 376
 377         0xc0026900,
 378         0x00000280,
 379         0x00000000, /* PA_SU_POINT_SIZE */
 380         0x00000000, /* PA_SU_POINT_MINMAX */
 381
 382         0xc0016900,
 383         0x0000037e,
 384         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 385
 386         0xc0016900,
 387         0x00000382,
 388         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 389
 390         0xc0016900,
 391         0x00000380,
 392         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 393
 394         0xc0016900,
 395         0x00000383,
 396         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 397
 398         0xc0016900,
 399         0x00000381,
 400         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 401
 402         0xc0016900,
 403         0x00000282,
 404         0x00000008, /* PA_SU_LINE_CNTL */
 405
 406         0xc0016900,
 407         0x00000302,
 408         0x0000002d, /* PA_SU_VTX_CNTL */
 409
 410         0xc0016900,
 411         0x0000037f,
 412         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 413
 414         0xc0016900,
 415         0x000001b2,
 416         0x00000000, /* SPI_THREAD_GROUPING */
 417
 418         0xc0046900,
 419         0x000001b6,
 420         0x00000000, /* SPI_INPUT_Z */
 421         0x00000000, /* SPI_FOG_CNTL */
 422         0x00000000, /* SPI_FOG_FUNC_SCALE */
 423         0x00000000, /* SPI_FOG_FUNC_BIAS */
 424
 425         0xc0016900,
 426         0x00000225,
 427         0x00000000, /* SQ_PGM_START_FS */
 428
 429         0xc0016900,
 430         0x00000229,
 431         0x00000000, /* SQ_PGM_RESOURCES_FS */
 432
 433         0xc0016900,
 434         0x00000237,
 435         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 436
 437         0xc0036900,
 438         0x00000100,
 439         0x00000800, /* VGT_MAX_VTX_INDX */
 440         0x00000000, /* VGT_MIN_VTX_INDX */
 441         0x00000000, /* VGT_INDX_OFFSET */
 442
 443         0xc0026900,
 444         0x000002a8,
 445         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 446         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 447
 448         0xc0016900,
 449         0x00000103,
 450         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 451
 452         0xc0016900,
 453         0x00000284,
 454         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 455
 456         0xc0016900,
 457         0x00000290,
 458         0x00000000, /* VGT_GS_MODE */
 459
 460         0xc0016900,
 461         0x00000285,
 462         0x00000000, /* VGT_HOS_CNTL */
 463
 464         0xc00a6900,
 465         0x00000286,
 466         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 467         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 468         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 469         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 470         0x00000000, /* VGT_GROUP_FIRST_DECR */
 471         0x00000000, /* VGT_GROUP_DECR */
 472         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 473         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 474         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 475         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 476
 477         0xc0016900,
 478         0x000002a1,
 479         0x00000000, /* VGT_PRIMITIVEID_EN */
 480
 481         0xc0016900,
 482         0x000002a5,
 483         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 484
 485         0xc0036900,
 486         0x000002ac,
 487         0x00000000, /* VGT_STRMOUT_EN */
 488         0x00000000, /* VGT_REUSE_OFF */
 489         0x00000000, /* VGT_VTX_CNT_EN */
 490
 491         0xc0016900,
 492         0x000002c8,
 493         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 494
 495         0xc0016900,
 496         0x00000206,
 497         0x00000100, /* PA_CL_VTE_CNTL */
 498
 499         0xc0016900,
 500         0x00000204,
 501         0x00010000, /* PA_CL_CLIP_CNTL */
 502
 503         0xc0036e00, /* SET_SAMPLER */
 504         0x00000000,
 505         0x00000012,
 506         0x00000000,
 507         0x00000000,
 508
 509         0xc0016900,
 510         0x0000008f,
 511         0x0000000f, /* CB_SHADER_MASK */
 512
 513         0xc0016900,
 514         0x000001e8,
 515         0x00000001, /* CB_SHADER_CONTROL */
 516
 517         0xc0016900,
 518         0x00000202,
 519         0x00cc0000, /* CB_COLOR_CONTROL */
 520
 521         0xc0016900,
 522         0x00000205,
 523         0x00000244, /* PA_SU_SC_MODE_CNTL */
 524
 525         0xc0016900,
 526         0x00000203,
 527         0x00000210, /* DB_SHADER_CNTL */
 528
 529         0xc0016900,
 530         0x000001b1,
 531         0x00000000, /* SPI_VS_OUT_CONFIG */
 532
 533         0xc0016900,
 534         0x00000185,
 535         0x00000000, /* SPI_VS_OUT_ID_0 */
 536
 537         0xc0026900,
 538         0x000001b3,
 539         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 540         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 541
 542         0xc0016900,
 543         0x00000191,
 544         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 545
 546         0xc0016900,
 547         0x000001b5,
 548         0x00000000, /* SPI_INTERP_CONTROL_0 */
 549 };
 550
 551 const u32 r7xx_default_state[] =
 552 {
 553         0xc0012800, /* CONTEXT_CONTROL */
 554         0x80000000,
 555         0x80000000,
 556
 557         0xc0016800,
 558         0x00000010,
 559         0x00008000, /* WAIT_UNTIL */
 560
 561         0xc0016800,
 562         0x00000542,
 563         0x07000002, /* TA_CNTL_AUX */
 564
 565         0xc0016800,
 566         0x000005c5,
 567         0x00000000, /* VC_ENHANCE */
 568
 569         0xc0016800,
 570         0x00000363,
 571         0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
 572
 573         0xc0016800,
 574         0x0000060c,
 575         0x00000000, /* DB_DEBUG */
 576
 577         0xc0016800,
 578         0x0000060e,
 579         0x00420204, /* DB_WATERMARKS */
 580
 581         0xc0026f00,
 582         0x00000000,
 583         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
 584         0x00000000, /* SQ_VTX_START_INST_LOC */
 585
 586         0xc0096900,
 587         0x0000022a,
 588         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
 589         0x00000000,
 590         0x00000000,
 591         0x00000000,
 592         0x00000000,
 593         0x00000000,
 594         0x00000000,
 595         0x00000000,
 596         0x00000000,
 597
 598         0xc0016900,
 599         0x00000004,
 600         0x00000000, /* DB_DEPTH_INFO */
 601
 602         0xc0026900,
 603         0x0000000a,
 604         0x00000000, /* DB_STENCIL_CLEAR */
 605         0x00000000, /* DB_DEPTH_CLEAR */
 606
 607         0xc0026900,
 608         0x0000010c,
 609         0x00000000, /* DB_STENCILREFMASK */
 610         0x00000000, /* DB_STENCILREFMASK_BF */
 611
 612         0xc0016900,
 613         0x00000200,
 614         0x00000000, /* DB_DEPTH_CONTROL */
 615
 616         0xc0026900,
 617         0x00000343,
 618         0x00000060, /* DB_RENDER_CONTROL */
 619         0x00000000, /* DB_RENDER_OVERRIDE */
 620
 621         0xc0016900,
 622         0x00000351,
 623         0x0000aa00, /* DB_ALPHA_TO_MASK */
 624
 625         0xc0016900,
 626         0x00000104,
 627         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 628
 629         0xc0016900,
 630         0x0000010e,
 631         0x00000000, /* SX_ALPHA_REF */
 632
 633         0xc0046900,
 634         0x00000105,
 635         0x00000000, /* CB_BLEND_RED */
 636         0x00000000,
 637         0x00000000,
 638         0x00000000,
 639
 640         0xc0046900,
 641         0x0000030c, /* CB_CLRCMP_CNTL */
 642         0x01000000,
 643         0x00000000,
 644         0x00000000,
 645         0x00000000,
 646
 647         0xc0016900,
 648         0x0000008e,
 649         0x0000000f, /* CB_TARGET_MASK */
 650
 651         0xc0016900,
 652         0x00000080,
 653         0x00000000, /* PA_SC_WINDOW_OFFSET */
 654
 655         0xc00a6900,
 656         0x00000083,
 657         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 658         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 659         0x20002000,
 660         0x00000000,
 661         0x20002000,
 662         0x00000000,
 663         0x20002000,
 664         0x00000000,
 665         0x20002000,
 666         0xaaaaaaaa, /* PA_SC_EDGERULE */
 667
 668         0xc0026900,
 669         0x00000094,
 670         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 671         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 672
 673         0xc0026900,
 674         0x000000b4,
 675         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 676         0x3f800000,
 677
 678         0xc0026900,
 679         0x00000096,
 680         0x80000000,
 681         0x20002000,
 682
 683         0xc0026900,
 684         0x000000b6,
 685         0x00000000,
 686         0x3f800000,
 687
 688         0xc0026900,
 689         0x00000098,
 690         0x80000000,
 691         0x20002000,
 692
 693         0xc0026900,
 694         0x000000b8,
 695         0x00000000,
 696         0x3f800000,
 697
 698         0xc0016900,
 699         0x0000009a,
 700         0x80000000,
 701         0x20002000,
 702
 703         0xc0026900,
 704         0x000000ba,
 705         0x00000000,
 706         0x3f800000,
 707
 708         0xc0026900,
 709         0x0000009c,
 710         0x80000000,
 711         0x20002000,
 712
 713         0xc0026900,
 714         0x000000bc,
 715         0x00000000,
 716         0x3f800000,
 717
 718         0xc0026900,
 719         0x0000009e,
 720         0x80000000,
 721         0x20002000,
 722
 723         0xc0026900,
 724         0x000000be,
 725         0x00000000,
 726         0x3f800000,
 727
 728         0xc0026900,
 729         0x000000a0,
 730         0x80000000,
 731         0x20002000,
 732
 733         0xc0026900,
 734         0x000000c0,
 735         0x00000000,
 736         0x3f800000,
 737
 738         0xc0026900,
 739         0x000000a2,
 740         0x80000000,
 741         0x20002000,
 742
 743         0xc0026900,
 744         0x000000c2,
 745         0x00000000,
 746         0x3f800000,
 747
 748         0xc0026900,
 749         0x000000a4,
 750         0x80000000,
 751         0x20002000,
 752
 753         0xc0026900,
 754         0x000000c4,
 755         0x00000000,
 756         0x3f800000,
 757
 758         0xc0026900,
 759         0x000000a6,
 760         0x80000000,
 761         0x20002000,
 762
 763         0xc0026900,
 764         0x000000c6,
 765         0x00000000,
 766         0x3f800000,
 767
 768         0xc0026900,
 769         0x000000a8,
 770         0x80000000,
 771         0x20002000,
 772
 773         0xc0026900,
 774         0x000000c8,
 775         0x00000000,
 776         0x3f800000,
 777
 778         0xc0026900,
 779         0x000000aa,
 780         0x80000000,
 781         0x20002000,
 782
 783         0xc0026900,
 784         0x000000ca,
 785         0x00000000,
 786         0x3f800000,
 787
 788         0xc0026900,
 789         0x000000ac,
 790         0x80000000,
 791         0x20002000,
 792
 793         0xc0026900,
 794         0x000000cc,
 795         0x00000000,
 796         0x3f800000,
 797
 798         0xc0026900,
 799         0x000000ae,
 800         0x80000000,
 801         0x20002000,
 802
 803         0xc0026900,
 804         0x000000ce,
 805         0x00000000,
 806         0x3f800000,
 807
 808         0xc0026900,
 809         0x000000b0,
 810         0x80000000,
 811         0x20002000,
 812
 813         0xc0026900,
 814         0x000000d0,
 815         0x00000000,
 816         0x3f800000,
 817
 818         0xc0026900,
 819         0x000000b2,
 820         0x80000000,
 821         0x20002000,
 822
 823         0xc0026900,
 824         0x000000d2,
 825         0x00000000,
 826         0x3f800000,
 827
 828         0xc0016900,
 829         0x00000293,
 830         0x00514000, /* PA_SC_MODE_CNTL */
 831
 832         0xc0026900,
 833         0x00000300,
 834         0x00000000, /* PA_SC_LINE_CNTL */
 835         0x00000000, /* PA_SC_AA_CONFIG */
 836
 837         0xc0016900,
 838         0x00000312,
 839         0xffffffff, /* PA_SC_AA_MASK */
 840
 841         0xc0026900,
 842         0x00000307,
 843         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 844         0x00000000,
 845
 846         0xc0016900,
 847         0x00000283,
 848         0x00000000, /* PA_SC_LINE_STIPPLE */
 849
 850         0xc0016900,
 851         0x00000292,
 852         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 853
 854         0xc0066900,
 855         0x0000010f,
 856         0x00000000, /* PA_CL_VPORT_0_XSCALE */
 857         0x00000000,
 858         0x00000000,
 859         0x00000000,
 860         0x00000000,
 861         0x00000000,
 862
 863         0xc0026900,
 864         0x00000207,
 865         0x00000000, /* PA_CL_VS_OUT_CNTL */
 866         0x00000000, /* PA_CL_NANINF_CNTL */
 867
 868         0xc0046900,
 869         0x00000303,
 870         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 871         0x3f800000,
 872         0x3f800000,
 873         0x3f800000,
 874
 875         0xc0026900,
 876         0x00000280,
 877         0x00000000, /* PA_SU_POINT_SIZE */
 878         0x00000000, /* PA_SU_POINT_MINMAX */
 879
 880         0xc0016900,
 881         0x0000037e,
 882         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 883
 884         0xc0016900,
 885         0x00000382,
 886         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 887
 888         0xc0016900,
 889         0x00000380,
 890         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 891
 892         0xc0016900,
 893         0x00000383,
 894         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 895
 896         0xc0016900,
 897         0x00000381,
 898         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 899
 900         0xc0016900,
 901         0x00000282,
 902         0x00000008, /* PA_SU_LINE_CNTL */
 903
 904         0xc0016900,
 905         0x00000302,
 906         0x0000002d, /* PA_SU_VTX_CNTL */
 907
 908         0xc0016900,
 909         0x0000037f,
 910         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 911
 912         0xc0016900,
 913         0x000001b2,
 914         0x00000001, /* SPI_THREAD_GROUPING */
 915
 916         0xc0046900,
 917         0x000001b6,
 918         0x00000000, /* SPI_INPUT_Z */
 919         0x00000000, /* SPI_FOG_CNTL */
 920         0x00000000, /* SPI_FOG_FUNC_SCALE */
 921         0x00000000, /* SPI_FOG_FUNC_BIAS */
 922
 923         0xc0016900,
 924         0x00000225,
 925         0x00000000, /* SQ_PGM_START_FS */
 926
 927         0xc0016900,
 928         0x00000229,
 929         0x00000000, /* SQ_PGM_RESOURCES_FS */
 930
 931         0xc0016900,
 932         0x00000237,
 933         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 934
 935         0xc0036900,
 936         0x00000100,
 937         0x00000800, /* VGT_MAX_VTX_INDX */
 938         0x00000000, /* VGT_MIN_VTX_INDX */
 939         0x00000000, /* VGT_INDX_OFFSET */
 940
 941         0xc0026900,
 942         0x000002a8,
 943         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 944         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 945
 946         0xc0016900,
 947         0x00000103,
 948         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 949
 950         0xc0016900,
 951         0x00000284,
 952         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 953
 954         0xc0016900,
 955         0x00000290,
 956         0x00000000, /* VGT_GS_MODE */
 957
 958         0xc00b6900,
 959         0x00000285,
 960         0x00000000, /* VGT_HOS_CNTL */
 961         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 962         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 963         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 964         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 965         0x00000000, /* VGT_GROUP_FIRST_DECR */
 966         0x00000000, /* VGT_GROUP_DECR */
 967         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 968         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 969         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 970         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 971
 972         0xc0016900,
 973         0x000002a1,
 974         0x00000000, /* VGT_PRIMITIVEID_EN */
 975
 976         0xc0016900,
 977         0x000002a5,
 978         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 979
 980         0xc0036900,
 981         0x000002ac,
 982         0x00000000, /* VGT_STRMOUT_EN */
 983         0x00000000, /* VGT_REUSE_OFF */
 984         0x00000000, /* VGT_VTX_CNT_EN */
 985
 986         0xc0016900,
 987         0x000002c8,
 988         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 989
 990         0xc0016900,
 991         0x00000206,
 992         0x00000100, /* PA_CL_VTE_CNTL */
 993
 994         0xc0016900,
 995         0x00000204,
 996         0x00010000, /* PA_CL_CLIP_CNTL */
 997
 998         0xc0036e00, /* SET_SAMPLER */
 999         0x00000000,
1000         0x00000012,
1001         0x00000000,
1002         0x00000000,
1003
1004         0xc0016900,
1005         0x0000008f,
1006         0x0000000f, /* CB_SHADER_MASK */
1007
1008         0xc0016900,
1009         0x000001e8,
1010         0x00000001, /* CB_SHADER_CONTROL */
1011
1012         0xc0016900,
1013         0x00000202,
1014         0x00cc0000, /* CB_COLOR_CONTROL */
1015
1016         0xc0016900,
1017         0x00000205,
1018         0x00000244, /* PA_SU_SC_MODE_CNTL */
1019
1020         0xc0016900,
1021         0x00000203,
1022         0x00000210, /* DB_SHADER_CNTL */
1023
1024         0xc0016900,
1025         0x000001b1,
1026         0x00000000, /* SPI_VS_OUT_CONFIG */
1027
1028         0xc0016900,
1029         0x00000185,
1030         0x00000000, /* SPI_VS_OUT_ID_0 */
1031
1032         0xc0026900,
1033         0x000001b3,
1034         0x00000001, /* SPI_PS_IN_CONTROL_0 */
1035         0x00000000, /* SPI_PS_IN_CONTROL_1 */
1036
1037         0xc0016900,
1038         0x00000191,
1039         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
1040
1041         0xc0016900,
1042         0x000001b5,
1043         0x00000000, /* SPI_INTERP_CONTROL_0 */
1044 };
1045
1046 /* same for r6xx/r7xx */
1047 const u32 r6xx_vs[] =
1048 {
1049         0x00000004,
1050         0x81000000,
1051         0x0000203c,
1052         0x94000b08,
1053         0x00004000,
1054         0x14200b1a,
1055         0x00000000,
1056         0x00000000,
1057         0x3c000000,
1058         0x68cd1000,
1059         0x00080000,
1060         0x00000000,
1061 };
1062
1063 const u32 r6xx_ps[] =
1064 {
1065         0x00000002,
1066         0x80800000,
1067         0x00000000,
1068         0x94200688,
1069         0x00000010,
1070         0x000d1000,
1071         0xb0800000,
1072         0x00000000,
1073 };
1074
1075 const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
1076 const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
1077 const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
1078 const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);