drivers/gpu/drm/radeon/r300.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_reg.h"
  32 #include "radeon.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_share.h"
  35 #include "r100_track.h"
  36
  37 #include "r300_reg_safe.h"
  38
  39 /* r300,r350,rv350,rv370,rv380 depends on : */
  40 void r100_hdp_reset(struct radeon_device *rdev);
  41 int r100_cp_reset(struct radeon_device *rdev);
  42 int r100_rb2d_reset(struct radeon_device *rdev);
  43 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  44 int r100_pci_gart_enable(struct radeon_device *rdev);
  45 void r100_pci_gart_disable(struct radeon_device *rdev);
  46 void r100_mc_setup(struct radeon_device *rdev);
  47 void r100_mc_disable_clients(struct radeon_device *rdev);
  48 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  49 int r100_cs_packet_parse(struct radeon_cs_parser *p,
  50                          struct radeon_cs_packet *pkt,
  51                          unsigned idx);
  52 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
  53 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  54                           struct radeon_cs_packet *pkt,
  55                           const unsigned *auth, unsigned n,
  56                           radeon_packet0_check_t check);
  57 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  58                                          struct radeon_cs_packet *pkt,
  59                                          struct radeon_object *robj);
  60
  61 /* This files gather functions specifics to:
  62  * r300,r350,rv350,rv370,rv380
  63  *
  64  * Some of these functions might be used by newer ASICs.
  65  */
  66 void r300_gpu_init(struct radeon_device *rdev);
  67 int r300_mc_wait_for_idle(struct radeon_device *rdev);
  68 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  69
  70
  71 /*
  72  * rv370,rv380 PCIE GART
  73  */
  74 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  75 {
  76         uint32_t tmp;
  77         int i;
  78
  79         /* Workaround HW bug do flush 2 times */
  80         for (i = 0; i < 2; i++) {
  81                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  82                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  83                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  84                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  85         }
  86         mb();
  87 }
  88
  89 int rv370_pcie_gart_enable(struct radeon_device *rdev)
  90 {
  91         uint32_t table_addr;
  92         uint32_t tmp;
  93         int r;
  94
  95         /* Initialize common gart structure */
  96         r = radeon_gart_init(rdev);
  97         if (r) {
  98                 return r;
  99         }
 100         r = rv370_debugfs_pcie_gart_info_init(rdev);
 101         if (r) {
 102                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 103         }
 104         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 105         r = radeon_gart_table_vram_alloc(rdev);
 106         if (r) {
 107                 return r;
 108         }
 109         /* discard memory request outside of configured range */
 110         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 111         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 112         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
 113         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
 114         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 115         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 116         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 117         table_addr = rdev->gart.table_addr;
 118         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 119         /* FIXME: setup default page */
 120         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
 121         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 122         /* Clear error */
 123         WREG32_PCIE(0x18, 0);
 124         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 125         tmp |= RADEON_PCIE_TX_GART_EN;
 126         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 127         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 128         rv370_pcie_gart_tlb_flush(rdev);
 129         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
 130                  rdev->mc.gtt_size >> 20, table_addr);
 131         rdev->gart.ready = true;
 132         return 0;
 133 }
 134
 135 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 136 {
 137         uint32_t tmp;
 138
 139         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 140         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 141         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 142         if (rdev->gart.table.vram.robj) {
 143                 radeon_object_kunmap(rdev->gart.table.vram.robj);
 144                 radeon_object_unpin(rdev->gart.table.vram.robj);
 145         }
 146 }
 147
 148 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 149 {
 150         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 151
 152         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 153                 return -EINVAL;
 154         }
 155         addr = (lower_32_bits(addr) >> 8) |
 156                ((upper_32_bits(addr) & 0xff) << 24) |
 157                0xc;
 158         /* on x86 we want this to be CPU endian, on powerpc
 159          * on powerpc without HW swappers, it'll get swapped on way
 160          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
 161         writel(addr, ((void __iomem *)ptr) + (i * 4));
 162         return 0;
 163 }
 164
 165 int r300_gart_enable(struct radeon_device *rdev)
 166 {
 167 #if __OS_HAS_AGP
 168         if (rdev->flags & RADEON_IS_AGP) {
 169                 if (rdev->family > CHIP_RV350) {
 170                         rv370_pcie_gart_disable(rdev);
 171                 } else {
 172                         r100_pci_gart_disable(rdev);
 173                 }
 174                 return 0;
 175         }
 176 #endif
 177         if (rdev->flags & RADEON_IS_PCIE) {
 178                 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
 179                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 180                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 181                 return rv370_pcie_gart_enable(rdev);
 182         }
 183         return r100_pci_gart_enable(rdev);
 184 }
 185
 186
 187 /*
 188  * MC
 189  */
 190 int r300_mc_init(struct radeon_device *rdev)
 191 {
 192         int r;
 193
 194         if (r100_debugfs_rbbm_init(rdev)) {
 195                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 196         }
 197
 198         r300_gpu_init(rdev);
 199         r100_pci_gart_disable(rdev);
 200         if (rdev->flags & RADEON_IS_PCIE) {
 201                 rv370_pcie_gart_disable(rdev);
 202         }
 203
 204         /* Setup GPU memory space */
 205         rdev->mc.vram_location = 0xFFFFFFFFUL;
 206         rdev->mc.gtt_location = 0xFFFFFFFFUL;
 207         if (rdev->flags & RADEON_IS_AGP) {
 208                 r = radeon_agp_init(rdev);
 209                 if (r) {
 210                         printk(KERN_WARNING "[drm] Disabling AGP\n");
 211                         rdev->flags &= ~RADEON_IS_AGP;
 212                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 213                 } else {
 214                         rdev->mc.gtt_location = rdev->mc.agp_base;
 215                 }
 216         }
 217         r = radeon_mc_setup(rdev);
 218         if (r) {
 219                 return r;
 220         }
 221
 222         /* Program GPU memory space */
 223         r100_mc_disable_clients(rdev);
 224         if (r300_mc_wait_for_idle(rdev)) {
 225                 printk(KERN_WARNING "Failed to wait MC idle while "
 226                        "programming pipes. Bad things might happen.\n");
 227         }
 228         r100_mc_setup(rdev);
 229         return 0;
 230 }
 231
 232 void r300_mc_fini(struct radeon_device *rdev)
 233 {
 234         if (rdev->flags & RADEON_IS_PCIE) {
 235                 rv370_pcie_gart_disable(rdev);
 236                 radeon_gart_table_vram_free(rdev);
 237         } else {
 238                 r100_pci_gart_disable(rdev);
 239                 radeon_gart_table_ram_free(rdev);
 240         }
 241         radeon_gart_fini(rdev);
 242 }
 243
 244
 245 /*
 246  * Fence emission
 247  */
 248 void r300_fence_ring_emit(struct radeon_device *rdev,
 249                           struct radeon_fence *fence)
 250 {
 251         /* Who ever call radeon_fence_emit should call ring_lock and ask
 252          * for enough space (today caller are ib schedule and buffer move) */
 253         /* Write SC register so SC & US assert idle */
 254         radeon_ring_write(rdev, PACKET0(0x43E0, 0));
 255         radeon_ring_write(rdev, 0);
 256         radeon_ring_write(rdev, PACKET0(0x43E4, 0));
 257         radeon_ring_write(rdev, 0);
 258         /* Flush 3D cache */
 259         radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
 260         radeon_ring_write(rdev, (2 << 0));
 261         radeon_ring_write(rdev, PACKET0(0x4F18, 0));
 262         radeon_ring_write(rdev, (1 << 0));
 263         /* Wait until IDLE & CLEAN */
 264         radeon_ring_write(rdev, PACKET0(0x1720, 0));
 265         radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
 266         /* Emit fence sequence & fire IRQ */
 267         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 268         radeon_ring_write(rdev, fence->seq);
 269         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 270         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 271 }
 272
 273
 274 /*
 275  * Global GPU functions
 276  */
 277 int r300_copy_dma(struct radeon_device *rdev,
 278                   uint64_t src_offset,
 279                   uint64_t dst_offset,
 280                   unsigned num_pages,
 281                   struct radeon_fence *fence)
 282 {
 283         uint32_t size;
 284         uint32_t cur_size;
 285         int i, num_loops;
 286         int r = 0;
 287
 288         /* radeon pitch is /64 */
 289         size = num_pages << PAGE_SHIFT;
 290         num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
 291         r = radeon_ring_lock(rdev, num_loops * 4 + 64);
 292         if (r) {
 293                 DRM_ERROR("radeon: moving bo (%d).\n", r);
 294                 return r;
 295         }
 296         /* Must wait for 2D idle & clean before DMA or hangs might happen */
 297         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
 298         radeon_ring_write(rdev, (1 << 16));
 299         for (i = 0; i < num_loops; i++) {
 300                 cur_size = size;
 301                 if (cur_size > 0x1FFFFF) {
 302                         cur_size = 0x1FFFFF;
 303                 }
 304                 size -= cur_size;
 305                 radeon_ring_write(rdev, PACKET0(0x720, 2));
 306                 radeon_ring_write(rdev, src_offset);
 307                 radeon_ring_write(rdev, dst_offset);
 308                 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
 309                 src_offset += cur_size;
 310                 dst_offset += cur_size;
 311         }
 312         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 313         radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
 314         if (fence) {
 315                 r = radeon_fence_emit(rdev, fence);
 316         }
 317         radeon_ring_unlock_commit(rdev);
 318         return r;
 319 }
 320
 321 void r300_ring_start(struct radeon_device *rdev)
 322 {
 323         unsigned gb_tile_config;
 324         int r;
 325
 326         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 327         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 328         switch(rdev->num_gb_pipes) {
 329         case 2:
 330                 gb_tile_config |= R300_PIPE_COUNT_R300;
 331                 break;
 332         case 3:
 333                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 334                 break;
 335         case 4:
 336                 gb_tile_config |= R300_PIPE_COUNT_R420;
 337                 break;
 338         case 1:
 339         default:
 340                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 341                 break;
 342         }
 343
 344         r = radeon_ring_lock(rdev, 64);
 345         if (r) {
 346                 return;
 347         }
 348         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 349         radeon_ring_write(rdev,
 350                           RADEON_ISYNC_ANY2D_IDLE3D |
 351                           RADEON_ISYNC_ANY3D_IDLE2D |
 352                           RADEON_ISYNC_WAIT_IDLEGUI |
 353                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 354         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
 355         radeon_ring_write(rdev, gb_tile_config);
 356         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 357         radeon_ring_write(rdev,
 358                           RADEON_WAIT_2D_IDLECLEAN |
 359                           RADEON_WAIT_3D_IDLECLEAN);
 360         radeon_ring_write(rdev, PACKET0(0x170C, 0));
 361         radeon_ring_write(rdev, 1 << 31);
 362         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
 363         radeon_ring_write(rdev, 0);
 364         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
 365         radeon_ring_write(rdev, 0);
 366         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 367         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 368         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 369         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 370         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 371         radeon_ring_write(rdev,
 372                           RADEON_WAIT_2D_IDLECLEAN |
 373                           RADEON_WAIT_3D_IDLECLEAN);
 374         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
 375         radeon_ring_write(rdev, 0);
 376         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 377         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 378         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 379         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 380         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
 381         radeon_ring_write(rdev,
 382                           ((6 << R300_MS_X0_SHIFT) |
 383                            (6 << R300_MS_Y0_SHIFT) |
 384                            (6 << R300_MS_X1_SHIFT) |
 385                            (6 << R300_MS_Y1_SHIFT) |
 386                            (6 << R300_MS_X2_SHIFT) |
 387                            (6 << R300_MS_Y2_SHIFT) |
 388                            (6 << R300_MSBD0_Y_SHIFT) |
 389                            (6 << R300_MSBD0_X_SHIFT)));
 390         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
 391         radeon_ring_write(rdev,
 392                           ((6 << R300_MS_X3_SHIFT) |
 393                            (6 << R300_MS_Y3_SHIFT) |
 394                            (6 << R300_MS_X4_SHIFT) |
 395                            (6 << R300_MS_Y4_SHIFT) |
 396                            (6 << R300_MS_X5_SHIFT) |
 397                            (6 << R300_MS_Y5_SHIFT) |
 398                            (6 << R300_MSBD1_SHIFT)));
 399         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
 400         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 401         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
 402         radeon_ring_write(rdev,
 403                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 404         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
 405         radeon_ring_write(rdev,
 406                           R300_GEOMETRY_ROUND_NEAREST |
 407                           R300_COLOR_ROUND_NEAREST);
 408         radeon_ring_unlock_commit(rdev);
 409 }
 410
 411 void r300_errata(struct radeon_device *rdev)
 412 {
 413         rdev->pll_errata = 0;
 414
 415         if (rdev->family == CHIP_R300 &&
 416             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 417                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 418         }
 419 }
 420
 421 int r300_mc_wait_for_idle(struct radeon_device *rdev)
 422 {
 423         unsigned i;
 424         uint32_t tmp;
 425
 426         for (i = 0; i < rdev->usec_timeout; i++) {
 427                 /* read MC_STATUS */
 428                 tmp = RREG32(0x0150);
 429                 if (tmp & (1 << 4)) {
 430                         return 0;
 431                 }
 432                 DRM_UDELAY(1);
 433         }
 434         return -1;
 435 }
 436
 437 void r300_gpu_init(struct radeon_device *rdev)
 438 {
 439         uint32_t gb_tile_config, tmp;
 440
 441         r100_hdp_reset(rdev);
 442         /* FIXME: rv380 one pipes ? */
 443         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
 444                 /* r300,r350 */
 445                 rdev->num_gb_pipes = 2;
 446         } else {
 447                 /* rv350,rv370,rv380 */
 448                 rdev->num_gb_pipes = 1;
 449         }
 450         rdev->num_z_pipes = 1;
 451         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 452         switch (rdev->num_gb_pipes) {
 453         case 2:
 454                 gb_tile_config |= R300_PIPE_COUNT_R300;
 455                 break;
 456         case 3:
 457                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 458                 break;
 459         case 4:
 460                 gb_tile_config |= R300_PIPE_COUNT_R420;
 461                 break;
 462         default:
 463         case 1:
 464                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 465                 break;
 466         }
 467         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 468
 469         if (r100_gui_wait_for_idle(rdev)) {
 470                 printk(KERN_WARNING "Failed to wait GUI idle while "
 471                        "programming pipes. Bad things might happen.\n");
 472         }
 473
 474         tmp = RREG32(0x170C);
 475         WREG32(0x170C, tmp | (1 << 31));
 476
 477         WREG32(R300_RB2D_DSTCACHE_MODE,
 478                R300_DC_AUTOFLUSH_ENABLE |
 479                R300_DC_DC_DISABLE_IGNORE_PE);
 480
 481         if (r100_gui_wait_for_idle(rdev)) {
 482                 printk(KERN_WARNING "Failed to wait GUI idle while "
 483                        "programming pipes. Bad things might happen.\n");
 484         }
 485         if (r300_mc_wait_for_idle(rdev)) {
 486                 printk(KERN_WARNING "Failed to wait MC idle while "
 487                        "programming pipes. Bad things might happen.\n");
 488         }
 489         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 490                  rdev->num_gb_pipes, rdev->num_z_pipes);
 491 }
 492
 493 int r300_ga_reset(struct radeon_device *rdev)
 494 {
 495         uint32_t tmp;
 496         bool reinit_cp;
 497         int i;
 498
 499         reinit_cp = rdev->cp.ready;
 500         rdev->cp.ready = false;
 501         for (i = 0; i < rdev->usec_timeout; i++) {
 502                 WREG32(RADEON_CP_CSQ_MODE, 0);
 503                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 504                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
 505                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
 506                 udelay(200);
 507                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 508                 /* Wait to prevent race in RBBM_STATUS */
 509                 mdelay(1);
 510                 tmp = RREG32(RADEON_RBBM_STATUS);
 511                 if (tmp & ((1 << 20) | (1 << 26))) {
 512                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
 513                         /* GA still busy soft reset it */
 514                         WREG32(0x429C, 0x200);
 515                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 516                         WREG32(0x43E0, 0);
 517                         WREG32(0x43E4, 0);
 518                         WREG32(0x24AC, 0);
 519                 }
 520                 /* Wait to prevent race in RBBM_STATUS */
 521                 mdelay(1);
 522                 tmp = RREG32(RADEON_RBBM_STATUS);
 523                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 524                         break;
 525                 }
 526         }
 527         for (i = 0; i < rdev->usec_timeout; i++) {
 528                 tmp = RREG32(RADEON_RBBM_STATUS);
 529                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 530                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
 531                                  tmp);
 532                         if (reinit_cp) {
 533                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 534                         }
 535                         return 0;
 536                 }
 537                 DRM_UDELAY(1);
 538         }
 539         tmp = RREG32(RADEON_RBBM_STATUS);
 540         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
 541         return -1;
 542 }
 543
 544 int r300_gpu_reset(struct radeon_device *rdev)
 545 {
 546         uint32_t status;
 547
 548         /* reset order likely matter */
 549         status = RREG32(RADEON_RBBM_STATUS);
 550         /* reset HDP */
 551         r100_hdp_reset(rdev);
 552         /* reset rb2d */
 553         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
 554                 r100_rb2d_reset(rdev);
 555         }
 556         /* reset GA */
 557         if (status & ((1 << 20) | (1 << 26))) {
 558                 r300_ga_reset(rdev);
 559         }
 560         /* reset CP */
 561         status = RREG32(RADEON_RBBM_STATUS);
 562         if (status & (1 << 16)) {
 563                 r100_cp_reset(rdev);
 564         }
 565         /* Check if GPU is idle */
 566         status = RREG32(RADEON_RBBM_STATUS);
 567         if (status & (1 << 31)) {
 568                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
 569                 return -1;
 570         }
 571         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
 572         return 0;
 573 }
 574
 575
 576 /*
 577  * r300,r350,rv350,rv380 VRAM info
 578  */
 579 void r300_vram_info(struct radeon_device *rdev)
 580 {
 581         uint32_t tmp;
 582
 583         /* DDR for all card after R300 & IGP */
 584         rdev->mc.vram_is_ddr = true;
 585         tmp = RREG32(RADEON_MEM_CNTL);
 586         if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
 587                 rdev->mc.vram_width = 128;
 588         } else {
 589                 rdev->mc.vram_width = 64;
 590         }
 591
 592         r100_vram_init_sizes(rdev);
 593 }
 594
 595
 596 /*
 597  * PCIE Lanes
 598  */
 599
 600 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 601 {
 602         uint32_t link_width_cntl, mask;
 603
 604         if (rdev->flags & RADEON_IS_IGP)
 605                 return;
 606
 607         if (!(rdev->flags & RADEON_IS_PCIE))
 608                 return;
 609
 610         /* FIXME wait for idle */
 611
 612         switch (lanes) {
 613         case 0:
 614                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 615                 break;
 616         case 1:
 617                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 618                 break;
 619         case 2:
 620                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 621                 break;
 622         case 4:
 623                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 624                 break;
 625         case 8:
 626                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 627                 break;
 628         case 12:
 629                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 630                 break;
 631         case 16:
 632         default:
 633                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 634                 break;
 635         }
 636
 637         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 638
 639         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 640             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 641                 return;
 642
 643         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 644                              RADEON_PCIE_LC_RECONFIG_NOW |
 645                              RADEON_PCIE_LC_RECONFIG_LATER |
 646                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 647         link_width_cntl |= mask;
 648         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 649         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 650                                                      RADEON_PCIE_LC_RECONFIG_NOW));
 651
 652         /* wait for lane set to complete */
 653         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 654         while (link_width_cntl == 0xffffffff)
 655                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 656
 657 }
 658
 659
 660 /*
 661  * Debugfs info
 662  */
 663 #if defined(CONFIG_DEBUG_FS)
 664 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 665 {
 666         struct drm_info_node *node = (struct drm_info_node *) m->private;
 667         struct drm_device *dev = node->minor->dev;
 668         struct radeon_device *rdev = dev->dev_private;
 669         uint32_t tmp;
 670
 671         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 672         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 673         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 674         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 675         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 676         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 677         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 678         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 679         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 680         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 681         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 682         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 683         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 684         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 685         return 0;
 686 }
 687
 688 static struct drm_info_list rv370_pcie_gart_info_list[] = {
 689         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 690 };
 691 #endif
 692
 693 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 694 {
 695 #if defined(CONFIG_DEBUG_FS)
 696         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 697 #else
 698         return 0;
 699 #endif
 700 }
 701
 702
 703 /*
 704  * CS functions
 705  */
 706 static int r300_packet0_check(struct radeon_cs_parser *p,
 707                 struct radeon_cs_packet *pkt,
 708                 unsigned idx, unsigned reg)
 709 {
 710         struct radeon_cs_chunk *ib_chunk;
 711         struct radeon_cs_reloc *reloc;
 712         struct r100_cs_track *track;
 713         volatile uint32_t *ib;
 714         uint32_t tmp, tile_flags = 0;
 715         unsigned i;
 716         int r;
 717
 718         ib = p->ib->ptr;
 719         ib_chunk = &p->chunks[p->chunk_ib_idx];
 720         track = (struct r100_cs_track *)p->track;
 721         switch(reg) {
 722         case AVIVO_D1MODE_VLINE_START_END:
 723         case RADEON_CRTC_GUI_TRIG_VLINE:
 724                 r = r100_cs_packet_parse_vline(p);
 725                 if (r) {
 726                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 727                                         idx, reg);
 728                         r100_cs_dump_packet(p, pkt);
 729                         return r;
 730                 }
 731                 break;
 732         case RADEON_DST_PITCH_OFFSET:
 733         case RADEON_SRC_PITCH_OFFSET:
 734                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 735                 if (r)
 736                         return r;
 737                 break;
 738         case R300_RB3D_COLOROFFSET0:
 739         case R300_RB3D_COLOROFFSET1:
 740         case R300_RB3D_COLOROFFSET2:
 741         case R300_RB3D_COLOROFFSET3:
 742                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 743                 r = r100_cs_packet_next_reloc(p, &reloc);
 744                 if (r) {
 745                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 746                                         idx, reg);
 747                         r100_cs_dump_packet(p, pkt);
 748                         return r;
 749                 }
 750                 track->cb[i].robj = reloc->robj;
 751                 track->cb[i].offset = ib_chunk->kdata[idx];
 752                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
 753                 break;
 754         case R300_ZB_DEPTHOFFSET:
 755                 r = r100_cs_packet_next_reloc(p, &reloc);
 756                 if (r) {
 757                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 758                                         idx, reg);
 759                         r100_cs_dump_packet(p, pkt);
 760                         return r;
 761                 }
 762                 track->zb.robj = reloc->robj;
 763                 track->zb.offset = ib_chunk->kdata[idx];
 764                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
 765                 break;
 766         case R300_TX_OFFSET_0:
 767         case R300_TX_OFFSET_0+4:
 768         case R300_TX_OFFSET_0+8:
 769         case R300_TX_OFFSET_0+12:
 770         case R300_TX_OFFSET_0+16:
 771         case R300_TX_OFFSET_0+20:
 772         case R300_TX_OFFSET_0+24:
 773         case R300_TX_OFFSET_0+28:
 774         case R300_TX_OFFSET_0+32:
 775         case R300_TX_OFFSET_0+36:
 776         case R300_TX_OFFSET_0+40:
 777         case R300_TX_OFFSET_0+44:
 778         case R300_TX_OFFSET_0+48:
 779         case R300_TX_OFFSET_0+52:
 780         case R300_TX_OFFSET_0+56:
 781         case R300_TX_OFFSET_0+60:
 782                 i = (reg - R300_TX_OFFSET_0) >> 2;
 783                 r = r100_cs_packet_next_reloc(p, &reloc);
 784                 if (r) {
 785                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 786                                         idx, reg);
 787                         r100_cs_dump_packet(p, pkt);
 788                         return r;
 789                 }
 790                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
 791                 track->textures[i].robj = reloc->robj;
 792                 break;
 793         /* Tracked registers */
 794         case 0x2084:
 795                 /* VAP_VF_CNTL */
 796                 track->vap_vf_cntl = ib_chunk->kdata[idx];
 797                 break;
 798         case 0x20B4:
 799                 /* VAP_VTX_SIZE */
 800                 track->vtx_size = ib_chunk->kdata[idx] & 0x7F;
 801                 break;
 802         case 0x2134:
 803                 /* VAP_VF_MAX_VTX_INDX */
 804                 track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
 805                 break;
 806         case 0x43E4:
 807                 /* SC_SCISSOR1 */
 808                 track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1;
 809                 if (p->rdev->family < CHIP_RV515) {
 810                         track->maxy -= 1440;
 811                 }
 812                 break;
 813         case 0x4E00:
 814                 /* RB3D_CCTL */
 815                 track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1;
 816                 break;
 817         case 0x4E38:
 818         case 0x4E3C:
 819         case 0x4E40:
 820         case 0x4E44:
 821                 /* RB3D_COLORPITCH0 */
 822                 /* RB3D_COLORPITCH1 */
 823                 /* RB3D_COLORPITCH2 */
 824                 /* RB3D_COLORPITCH3 */
 825                 r = r100_cs_packet_next_reloc(p, &reloc);
 826                 if (r) {
 827                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 828                                   idx, reg);
 829                         r100_cs_dump_packet(p, pkt);
 830                         return r;
 831                 }
 832
 833                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 834                         tile_flags |= R300_COLOR_TILE_ENABLE;
 835                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 836                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 837
 838                 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
 839                 tmp |= tile_flags;
 840                 ib[idx] = tmp;
 841
 842                 i = (reg - 0x4E38) >> 2;
 843                 track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE;
 844                 switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) {
 845                 case 9:
 846                 case 11:
 847                 case 12:
 848                         track->cb[i].cpp = 1;
 849                         break;
 850                 case 3:
 851                 case 4:
 852                 case 13:
 853                 case 15:
 854                         track->cb[i].cpp = 2;
 855                         break;
 856                 case 6:
 857                         track->cb[i].cpp = 4;
 858                         break;
 859                 case 10:
 860                         track->cb[i].cpp = 8;
 861                         break;
 862                 case 7:
 863                         track->cb[i].cpp = 16;
 864                         break;
 865                 default:
 866                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 867                                   ((ib_chunk->kdata[idx] >> 21) & 0xF));
 868                         return -EINVAL;
 869                 }
 870                 break;
 871         case 0x4F00:
 872                 /* ZB_CNTL */
 873                 if (ib_chunk->kdata[idx] & 2) {
 874                         track->z_enabled = true;
 875                 } else {
 876                         track->z_enabled = false;
 877                 }
 878                 break;
 879         case 0x4F10:
 880                 /* ZB_FORMAT */
 881                 switch ((ib_chunk->kdata[idx] & 0xF)) {
 882                 case 0:
 883                 case 1:
 884                         track->zb.cpp = 2;
 885                         break;
 886                 case 2:
 887                         track->zb.cpp = 4;
 888                         break;
 889                 default:
 890                         DRM_ERROR("Invalid z buffer format (%d) !\n",
 891                                   (ib_chunk->kdata[idx] & 0xF));
 892                         return -EINVAL;
 893                 }
 894                 break;
 895         case 0x4F24:
 896                 /* ZB_DEPTHPITCH */
 897                 r = r100_cs_packet_next_reloc(p, &reloc);
 898                 if (r) {
 899                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 900                                   idx, reg);
 901                         r100_cs_dump_packet(p, pkt);
 902                         return r;
 903                 }
 904
 905                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 906                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 907                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 908                         tile_flags |= R300_DEPTHMICROTILE_TILED;;
 909
 910                 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
 911                 tmp |= tile_flags;
 912                 ib[idx] = tmp;
 913
 914                 track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC;
 915                 break;
 916         case 0x4104:
 917                 for (i = 0; i < 16; i++) {
 918                         bool enabled;
 919
 920                         enabled = !!(ib_chunk->kdata[idx] & (1 << i));
 921                         track->textures[i].enabled = enabled;
 922                 }
 923                 break;
 924         case 0x44C0:
 925         case 0x44C4:
 926         case 0x44C8:
 927         case 0x44CC:
 928         case 0x44D0:
 929         case 0x44D4:
 930         case 0x44D8:
 931         case 0x44DC:
 932         case 0x44E0:
 933         case 0x44E4:
 934         case 0x44E8:
 935         case 0x44EC:
 936         case 0x44F0:
 937         case 0x44F4:
 938         case 0x44F8:
 939         case 0x44FC:
 940                 /* TX_FORMAT1_[0-15] */
 941                 i = (reg - 0x44C0) >> 2;
 942                 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
 943                 track->textures[i].tex_coord_type = tmp;
 944                 switch ((ib_chunk->kdata[idx] & 0x1F)) {
 945                 case R300_TX_FORMAT_X8:
 946                 case R300_TX_FORMAT_Y4X4:
 947                 case R300_TX_FORMAT_Z3Y3X2:
 948                         track->textures[i].cpp = 1;
 949                         break;
 950                 case R300_TX_FORMAT_X16:
 951                 case R300_TX_FORMAT_Y8X8:
 952                 case R300_TX_FORMAT_Z5Y6X5:
 953                 case R300_TX_FORMAT_Z6Y5X5:
 954                 case R300_TX_FORMAT_W4Z4Y4X4:
 955                 case R300_TX_FORMAT_W1Z5Y5X5:
 956                 case R300_TX_FORMAT_DXT1:
 957                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
 958                 case R300_TX_FORMAT_B8G8_B8G8:
 959                 case R300_TX_FORMAT_G8R8_G8B8:
 960                         track->textures[i].cpp = 2;
 961                         break;
 962                 case R300_TX_FORMAT_Y16X16:
 963                 case R300_TX_FORMAT_Z11Y11X10:
 964                 case R300_TX_FORMAT_Z10Y11X11:
 965                 case R300_TX_FORMAT_W8Z8Y8X8:
 966                 case R300_TX_FORMAT_W2Z10Y10X10:
 967                 case 0x17:
 968                 case R300_TX_FORMAT_FL_I32:
 969                 case 0x1e:
 970                 case R300_TX_FORMAT_DXT3:
 971                 case R300_TX_FORMAT_DXT5:
 972                         track->textures[i].cpp = 4;
 973                         break;
 974                 case R300_TX_FORMAT_W16Z16Y16X16:
 975                 case R300_TX_FORMAT_FL_R16G16B16A16:
 976                 case R300_TX_FORMAT_FL_I32A32:
 977                         track->textures[i].cpp = 8;
 978                         break;
 979                 case R300_TX_FORMAT_FL_R32G32B32A32:
 980                         track->textures[i].cpp = 16;
 981                         break;
 982                 default:
 983                         DRM_ERROR("Invalid texture format %u\n",
 984                                   (ib_chunk->kdata[idx] & 0x1F));
 985                         return -EINVAL;
 986                         break;
 987                 }
 988                 break;
 989         case 0x4400:
 990         case 0x4404:
 991         case 0x4408:
 992         case 0x440C:
 993         case 0x4410:
 994         case 0x4414:
 995         case 0x4418:
 996         case 0x441C:
 997         case 0x4420:
 998         case 0x4424:
 999         case 0x4428:
1000         case 0x442C:
1001         case 0x4430:
1002         case 0x4434:
1003         case 0x4438:
1004         case 0x443C:
1005                 /* TX_FILTER0_[0-15] */
1006                 i = (reg - 0x4400) >> 2;
1007                 tmp = ib_chunk->kdata[idx] & 0x7;
1008                 if (tmp == 2 || tmp == 4 || tmp == 6) {
1009                         track->textures[i].roundup_w = false;
1010                 }
1011                 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;
1012                 if (tmp == 2 || tmp == 4 || tmp == 6) {
1013                         track->textures[i].roundup_h = false;
1014                 }
1015                 break;
1016         case 0x4500:
1017         case 0x4504:
1018         case 0x4508:
1019         case 0x450C:
1020         case 0x4510:
1021         case 0x4514:
1022         case 0x4518:
1023         case 0x451C:
1024         case 0x4520:
1025         case 0x4524:
1026         case 0x4528:
1027         case 0x452C:
1028         case 0x4530:
1029         case 0x4534:
1030         case 0x4538:
1031         case 0x453C:
1032                 /* TX_FORMAT2_[0-15] */
1033                 i = (reg - 0x4500) >> 2;
1034                 tmp = ib_chunk->kdata[idx] & 0x3FFF;
1035                 track->textures[i].pitch = tmp + 1;
1036                 if (p->rdev->family >= CHIP_RV515) {
1037                         tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11;
1038                         track->textures[i].width_11 = tmp;
1039                         tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11;
1040                         track->textures[i].height_11 = tmp;
1041                 }
1042                 break;
1043         case 0x4480:
1044         case 0x4484:
1045         case 0x4488:
1046         case 0x448C:
1047         case 0x4490:
1048         case 0x4494:
1049         case 0x4498:
1050         case 0x449C:
1051         case 0x44A0:
1052         case 0x44A4:
1053         case 0x44A8:
1054         case 0x44AC:
1055         case 0x44B0:
1056         case 0x44B4:
1057         case 0x44B8:
1058         case 0x44BC:
1059                 /* TX_FORMAT0_[0-15] */
1060                 i = (reg - 0x4480) >> 2;
1061                 tmp = ib_chunk->kdata[idx] & 0x7FF;
1062                 track->textures[i].width = tmp + 1;
1063                 tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF;
1064                 track->textures[i].height = tmp + 1;
1065                 tmp = (ib_chunk->kdata[idx] >> 26) & 0xF;
1066                 track->textures[i].num_levels = tmp;
1067                 tmp = ib_chunk->kdata[idx] & (1 << 31);
1068                 track->textures[i].use_pitch = !!tmp;
1069                 tmp = (ib_chunk->kdata[idx] >> 22) & 0xF;
1070                 track->textures[i].txdepth = tmp;
1071                 break;
1072         case R300_ZB_ZPASS_ADDR:
1073                 r = r100_cs_packet_next_reloc(p, &reloc);
1074                 if (r) {
1075                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1076                                         idx, reg);
1077                         r100_cs_dump_packet(p, pkt);
1078                         return r;
1079                 }
1080                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1081                 break;
1082         case 0x4be8:
1083                 /* valid register only on RV530 */
1084                 if (p->rdev->family == CHIP_RV530)
1085                         break;
1086                 /* fallthrough do not move */
1087         default:
1088                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1089                        reg, idx);
1090                 return -EINVAL;
1091         }
1092         return 0;
1093 }
1094
1095 static int r300_packet3_check(struct radeon_cs_parser *p,
1096                               struct radeon_cs_packet *pkt)
1097 {
1098         struct radeon_cs_chunk *ib_chunk;
1099
1100         struct radeon_cs_reloc *reloc;
1101         struct r100_cs_track *track;
1102         volatile uint32_t *ib;
1103         unsigned idx;
1104         unsigned i, c;
1105         int r;
1106
1107         ib = p->ib->ptr;
1108         ib_chunk = &p->chunks[p->chunk_ib_idx];
1109         idx = pkt->idx + 1;
1110         track = (struct r100_cs_track *)p->track;
1111         switch(pkt->opcode) {
1112         case PACKET3_3D_LOAD_VBPNTR:
1113                 c = ib_chunk->kdata[idx++] & 0x1F;
1114                 track->num_arrays = c;
1115                 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1116                         r = r100_cs_packet_next_reloc(p, &reloc);
1117                         if (r) {
1118                                 DRM_ERROR("No reloc for packet3 %d\n",
1119                                           pkt->opcode);
1120                                 r100_cs_dump_packet(p, pkt);
1121                                 return r;
1122                         }
1123                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1124                         track->arrays[i + 0].robj = reloc->robj;
1125                         track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1126                         track->arrays[i + 0].esize &= 0x7F;
1127                         r = r100_cs_packet_next_reloc(p, &reloc);
1128                         if (r) {
1129                                 DRM_ERROR("No reloc for packet3 %d\n",
1130                                           pkt->opcode);
1131                                 r100_cs_dump_packet(p, pkt);
1132                                 return r;
1133                         }
1134                         ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1135                         track->arrays[i + 1].robj = reloc->robj;
1136                         track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
1137                         track->arrays[i + 1].esize &= 0x7F;
1138                 }
1139                 if (c & 1) {
1140                         r = r100_cs_packet_next_reloc(p, &reloc);
1141                         if (r) {
1142                                 DRM_ERROR("No reloc for packet3 %d\n",
1143                                           pkt->opcode);
1144                                 r100_cs_dump_packet(p, pkt);
1145                                 return r;
1146                         }
1147                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1148                         track->arrays[i + 0].robj = reloc->robj;
1149                         track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1150                         track->arrays[i + 0].esize &= 0x7F;
1151                 }
1152                 break;
1153         case PACKET3_INDX_BUFFER:
1154                 r = r100_cs_packet_next_reloc(p, &reloc);
1155                 if (r) {
1156                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1157                         r100_cs_dump_packet(p, pkt);
1158                         return r;
1159                 }
1160                 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1161                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1162                 if (r) {
1163                         return r;
1164                 }
1165                 break;
1166         /* Draw packet */
1167         case PACKET3_3D_DRAW_IMMD:
1168                 /* Number of dwords is vtx_size * (num_vertices - 1)
1169                  * PRIM_WALK must be equal to 3 vertex data in embedded
1170                  * in cmd stream */
1171                 if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
1172                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1173                         return -EINVAL;
1174                 }
1175                 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1176                 track->immd_dwords = pkt->count - 1;
1177                 r = r100_cs_track_check(p->rdev, track);
1178                 if (r) {
1179                         return r;
1180                 }
1181                 break;
1182         case PACKET3_3D_DRAW_IMMD_2:
1183                 /* Number of dwords is vtx_size * (num_vertices - 1)
1184                  * PRIM_WALK must be equal to 3 vertex data in embedded
1185                  * in cmd stream */
1186                 if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
1187                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1188                         return -EINVAL;
1189                 }
1190                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1191                 track->immd_dwords = pkt->count;
1192                 r = r100_cs_track_check(p->rdev, track);
1193                 if (r) {
1194                         return r;
1195                 }
1196                 break;
1197         case PACKET3_3D_DRAW_VBUF:
1198                 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1199                 r = r100_cs_track_check(p->rdev, track);
1200                 if (r) {
1201                         return r;
1202                 }
1203                 break;
1204         case PACKET3_3D_DRAW_VBUF_2:
1205                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1206                 r = r100_cs_track_check(p->rdev, track);
1207                 if (r) {
1208                         return r;
1209                 }
1210                 break;
1211         case PACKET3_3D_DRAW_INDX:
1212                 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1213                 r = r100_cs_track_check(p->rdev, track);
1214                 if (r) {
1215                         return r;
1216                 }
1217                 break;
1218         case PACKET3_3D_DRAW_INDX_2:
1219                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1220                 r = r100_cs_track_check(p->rdev, track);
1221                 if (r) {
1222                         return r;
1223                 }
1224                 break;
1225         case PACKET3_NOP:
1226                 break;
1227         default:
1228                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1229                 return -EINVAL;
1230         }
1231         return 0;
1232 }
1233
1234 int r300_cs_parse(struct radeon_cs_parser *p)
1235 {
1236         struct radeon_cs_packet pkt;
1237         struct r100_cs_track track;
1238         int r;
1239
1240         r100_cs_track_clear(p->rdev, &track);
1241         p->track = &track;
1242         do {
1243                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1244                 if (r) {
1245                         return r;
1246                 }
1247                 p->idx += pkt.count + 2;
1248                 switch (pkt.type) {
1249                 case PACKET_TYPE0:
1250                         r = r100_cs_parse_packet0(p, &pkt,
1251                                                   p->rdev->config.r300.reg_safe_bm,
1252                                                   p->rdev->config.r300.reg_safe_bm_size,
1253                                                   &r300_packet0_check);
1254                         break;
1255                 case PACKET_TYPE2:
1256                         break;
1257                 case PACKET_TYPE3:
1258                         r = r300_packet3_check(p, &pkt);
1259                         break;
1260                 default:
1261                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1262                         return -EINVAL;
1263                 }
1264                 if (r) {
1265                         return r;
1266                 }
1267         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1268         return 0;
1269 }
1270
1271 int r300_init(struct radeon_device *rdev)
1272 {
1273         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1274         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1275         return 0;
1276 }