2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include <linux/swab.h>
27 #include <linux/slab.h>
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nv50_display.h"
40 static void nouveau_stub_takedown(struct drm_device *dev) {}
42 static int nouveau_init_engine_ptrs(struct drm_device *dev)
44 struct drm_nouveau_private *dev_priv = dev->dev_private;
45 struct nouveau_engine *engine = &dev_priv->engine;
47 switch (dev_priv->chipset & 0xf0) {
49 engine->instmem.init = nv04_instmem_init;
50 engine->instmem.takedown = nv04_instmem_takedown;
51 engine->instmem.suspend = nv04_instmem_suspend;
52 engine->instmem.resume = nv04_instmem_resume;
53 engine->instmem.populate = nv04_instmem_populate;
54 engine->instmem.clear = nv04_instmem_clear;
55 engine->instmem.bind = nv04_instmem_bind;
56 engine->instmem.unbind = nv04_instmem_unbind;
57 engine->instmem.flush = nv04_instmem_flush;
58 engine->mc.init = nv04_mc_init;
59 engine->mc.takedown = nv04_mc_takedown;
60 engine->timer.init = nv04_timer_init;
61 engine->timer.read = nv04_timer_read;
62 engine->timer.takedown = nv04_timer_takedown;
63 engine->fb.init = nv04_fb_init;
64 engine->fb.takedown = nv04_fb_takedown;
65 engine->graph.grclass = nv04_graph_grclass;
66 engine->graph.init = nv04_graph_init;
67 engine->graph.takedown = nv04_graph_takedown;
68 engine->graph.fifo_access = nv04_graph_fifo_access;
69 engine->graph.channel = nv04_graph_channel;
70 engine->graph.create_context = nv04_graph_create_context;
71 engine->graph.destroy_context = nv04_graph_destroy_context;
72 engine->graph.load_context = nv04_graph_load_context;
73 engine->graph.unload_context = nv04_graph_unload_context;
74 engine->fifo.channels = 16;
75 engine->fifo.init = nv04_fifo_init;
76 engine->fifo.takedown = nouveau_stub_takedown;
77 engine->fifo.disable = nv04_fifo_disable;
78 engine->fifo.enable = nv04_fifo_enable;
79 engine->fifo.reassign = nv04_fifo_reassign;
80 engine->fifo.cache_flush = nv04_fifo_cache_flush;
81 engine->fifo.cache_pull = nv04_fifo_cache_pull;
82 engine->fifo.channel_id = nv04_fifo_channel_id;
83 engine->fifo.create_context = nv04_fifo_create_context;
84 engine->fifo.destroy_context = nv04_fifo_destroy_context;
85 engine->fifo.load_context = nv04_fifo_load_context;
86 engine->fifo.unload_context = nv04_fifo_unload_context;
87 engine->display.early_init = nv04_display_early_init;
88 engine->display.late_takedown = nv04_display_late_takedown;
89 engine->display.create = nv04_display_create;
90 engine->display.init = nv04_display_init;
91 engine->display.destroy = nv04_display_destroy;
94 engine->instmem.init = nv04_instmem_init;
95 engine->instmem.takedown = nv04_instmem_takedown;
96 engine->instmem.suspend = nv04_instmem_suspend;
97 engine->instmem.resume = nv04_instmem_resume;
98 engine->instmem.populate = nv04_instmem_populate;
99 engine->instmem.clear = nv04_instmem_clear;
100 engine->instmem.bind = nv04_instmem_bind;
101 engine->instmem.unbind = nv04_instmem_unbind;
102 engine->instmem.flush = nv04_instmem_flush;
103 engine->mc.init = nv04_mc_init;
104 engine->mc.takedown = nv04_mc_takedown;
105 engine->timer.init = nv04_timer_init;
106 engine->timer.read = nv04_timer_read;
107 engine->timer.takedown = nv04_timer_takedown;
108 engine->fb.init = nv10_fb_init;
109 engine->fb.takedown = nv10_fb_takedown;
110 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
111 engine->graph.grclass = nv10_graph_grclass;
112 engine->graph.init = nv10_graph_init;
113 engine->graph.takedown = nv10_graph_takedown;
114 engine->graph.channel = nv10_graph_channel;
115 engine->graph.create_context = nv10_graph_create_context;
116 engine->graph.destroy_context = nv10_graph_destroy_context;
117 engine->graph.fifo_access = nv04_graph_fifo_access;
118 engine->graph.load_context = nv10_graph_load_context;
119 engine->graph.unload_context = nv10_graph_unload_context;
120 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
121 engine->fifo.channels = 32;
122 engine->fifo.init = nv10_fifo_init;
123 engine->fifo.takedown = nouveau_stub_takedown;
124 engine->fifo.disable = nv04_fifo_disable;
125 engine->fifo.enable = nv04_fifo_enable;
126 engine->fifo.reassign = nv04_fifo_reassign;
127 engine->fifo.cache_flush = nv04_fifo_cache_flush;
128 engine->fifo.cache_pull = nv04_fifo_cache_pull;
129 engine->fifo.channel_id = nv10_fifo_channel_id;
130 engine->fifo.create_context = nv10_fifo_create_context;
131 engine->fifo.destroy_context = nv10_fifo_destroy_context;
132 engine->fifo.load_context = nv10_fifo_load_context;
133 engine->fifo.unload_context = nv10_fifo_unload_context;
134 engine->display.early_init = nv04_display_early_init;
135 engine->display.late_takedown = nv04_display_late_takedown;
136 engine->display.create = nv04_display_create;
137 engine->display.init = nv04_display_init;
138 engine->display.destroy = nv04_display_destroy;
141 engine->instmem.init = nv04_instmem_init;
142 engine->instmem.takedown = nv04_instmem_takedown;
143 engine->instmem.suspend = nv04_instmem_suspend;
144 engine->instmem.resume = nv04_instmem_resume;
145 engine->instmem.populate = nv04_instmem_populate;
146 engine->instmem.clear = nv04_instmem_clear;
147 engine->instmem.bind = nv04_instmem_bind;
148 engine->instmem.unbind = nv04_instmem_unbind;
149 engine->instmem.flush = nv04_instmem_flush;
150 engine->mc.init = nv04_mc_init;
151 engine->mc.takedown = nv04_mc_takedown;
152 engine->timer.init = nv04_timer_init;
153 engine->timer.read = nv04_timer_read;
154 engine->timer.takedown = nv04_timer_takedown;
155 engine->fb.init = nv10_fb_init;
156 engine->fb.takedown = nv10_fb_takedown;
157 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
158 engine->graph.grclass = nv20_graph_grclass;
159 engine->graph.init = nv20_graph_init;
160 engine->graph.takedown = nv20_graph_takedown;
161 engine->graph.channel = nv10_graph_channel;
162 engine->graph.create_context = nv20_graph_create_context;
163 engine->graph.destroy_context = nv20_graph_destroy_context;
164 engine->graph.fifo_access = nv04_graph_fifo_access;
165 engine->graph.load_context = nv20_graph_load_context;
166 engine->graph.unload_context = nv20_graph_unload_context;
167 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
168 engine->fifo.channels = 32;
169 engine->fifo.init = nv10_fifo_init;
170 engine->fifo.takedown = nouveau_stub_takedown;
171 engine->fifo.disable = nv04_fifo_disable;
172 engine->fifo.enable = nv04_fifo_enable;
173 engine->fifo.reassign = nv04_fifo_reassign;
174 engine->fifo.cache_flush = nv04_fifo_cache_flush;
175 engine->fifo.cache_pull = nv04_fifo_cache_pull;
176 engine->fifo.channel_id = nv10_fifo_channel_id;
177 engine->fifo.create_context = nv10_fifo_create_context;
178 engine->fifo.destroy_context = nv10_fifo_destroy_context;
179 engine->fifo.load_context = nv10_fifo_load_context;
180 engine->fifo.unload_context = nv10_fifo_unload_context;
181 engine->display.early_init = nv04_display_early_init;
182 engine->display.late_takedown = nv04_display_late_takedown;
183 engine->display.create = nv04_display_create;
184 engine->display.init = nv04_display_init;
185 engine->display.destroy = nv04_display_destroy;
188 engine->instmem.init = nv04_instmem_init;
189 engine->instmem.takedown = nv04_instmem_takedown;
190 engine->instmem.suspend = nv04_instmem_suspend;
191 engine->instmem.resume = nv04_instmem_resume;
192 engine->instmem.populate = nv04_instmem_populate;
193 engine->instmem.clear = nv04_instmem_clear;
194 engine->instmem.bind = nv04_instmem_bind;
195 engine->instmem.unbind = nv04_instmem_unbind;
196 engine->instmem.flush = nv04_instmem_flush;
197 engine->mc.init = nv04_mc_init;
198 engine->mc.takedown = nv04_mc_takedown;
199 engine->timer.init = nv04_timer_init;
200 engine->timer.read = nv04_timer_read;
201 engine->timer.takedown = nv04_timer_takedown;
202 engine->fb.init = nv30_fb_init;
203 engine->fb.takedown = nv30_fb_takedown;
204 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
205 engine->graph.grclass = nv30_graph_grclass;
206 engine->graph.init = nv30_graph_init;
207 engine->graph.takedown = nv20_graph_takedown;
208 engine->graph.fifo_access = nv04_graph_fifo_access;
209 engine->graph.channel = nv10_graph_channel;
210 engine->graph.create_context = nv20_graph_create_context;
211 engine->graph.destroy_context = nv20_graph_destroy_context;
212 engine->graph.load_context = nv20_graph_load_context;
213 engine->graph.unload_context = nv20_graph_unload_context;
214 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
215 engine->fifo.channels = 32;
216 engine->fifo.init = nv10_fifo_init;
217 engine->fifo.takedown = nouveau_stub_takedown;
218 engine->fifo.disable = nv04_fifo_disable;
219 engine->fifo.enable = nv04_fifo_enable;
220 engine->fifo.reassign = nv04_fifo_reassign;
221 engine->fifo.cache_flush = nv04_fifo_cache_flush;
222 engine->fifo.cache_pull = nv04_fifo_cache_pull;
223 engine->fifo.channel_id = nv10_fifo_channel_id;
224 engine->fifo.create_context = nv10_fifo_create_context;
225 engine->fifo.destroy_context = nv10_fifo_destroy_context;
226 engine->fifo.load_context = nv10_fifo_load_context;
227 engine->fifo.unload_context = nv10_fifo_unload_context;
228 engine->display.early_init = nv04_display_early_init;
229 engine->display.late_takedown = nv04_display_late_takedown;
230 engine->display.create = nv04_display_create;
231 engine->display.init = nv04_display_init;
232 engine->display.destroy = nv04_display_destroy;
236 engine->instmem.init = nv04_instmem_init;
237 engine->instmem.takedown = nv04_instmem_takedown;
238 engine->instmem.suspend = nv04_instmem_suspend;
239 engine->instmem.resume = nv04_instmem_resume;
240 engine->instmem.populate = nv04_instmem_populate;
241 engine->instmem.clear = nv04_instmem_clear;
242 engine->instmem.bind = nv04_instmem_bind;
243 engine->instmem.unbind = nv04_instmem_unbind;
244 engine->instmem.flush = nv04_instmem_flush;
245 engine->mc.init = nv40_mc_init;
246 engine->mc.takedown = nv40_mc_takedown;
247 engine->timer.init = nv04_timer_init;
248 engine->timer.read = nv04_timer_read;
249 engine->timer.takedown = nv04_timer_takedown;
250 engine->fb.init = nv40_fb_init;
251 engine->fb.takedown = nv40_fb_takedown;
252 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
253 engine->graph.grclass = nv40_graph_grclass;
254 engine->graph.init = nv40_graph_init;
255 engine->graph.takedown = nv40_graph_takedown;
256 engine->graph.fifo_access = nv04_graph_fifo_access;
257 engine->graph.channel = nv40_graph_channel;
258 engine->graph.create_context = nv40_graph_create_context;
259 engine->graph.destroy_context = nv40_graph_destroy_context;
260 engine->graph.load_context = nv40_graph_load_context;
261 engine->graph.unload_context = nv40_graph_unload_context;
262 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
263 engine->fifo.channels = 32;
264 engine->fifo.init = nv40_fifo_init;
265 engine->fifo.takedown = nouveau_stub_takedown;
266 engine->fifo.disable = nv04_fifo_disable;
267 engine->fifo.enable = nv04_fifo_enable;
268 engine->fifo.reassign = nv04_fifo_reassign;
269 engine->fifo.cache_flush = nv04_fifo_cache_flush;
270 engine->fifo.cache_pull = nv04_fifo_cache_pull;
271 engine->fifo.channel_id = nv10_fifo_channel_id;
272 engine->fifo.create_context = nv40_fifo_create_context;
273 engine->fifo.destroy_context = nv40_fifo_destroy_context;
274 engine->fifo.load_context = nv40_fifo_load_context;
275 engine->fifo.unload_context = nv40_fifo_unload_context;
276 engine->display.early_init = nv04_display_early_init;
277 engine->display.late_takedown = nv04_display_late_takedown;
278 engine->display.create = nv04_display_create;
279 engine->display.init = nv04_display_init;
280 engine->display.destroy = nv04_display_destroy;
283 case 0x80: /* gotta love NVIDIA's consistency.. */
286 engine->instmem.init = nv50_instmem_init;
287 engine->instmem.takedown = nv50_instmem_takedown;
288 engine->instmem.suspend = nv50_instmem_suspend;
289 engine->instmem.resume = nv50_instmem_resume;
290 engine->instmem.populate = nv50_instmem_populate;
291 engine->instmem.clear = nv50_instmem_clear;
292 engine->instmem.bind = nv50_instmem_bind;
293 engine->instmem.unbind = nv50_instmem_unbind;
294 if (dev_priv->chipset == 0x50)
295 engine->instmem.flush = nv50_instmem_flush;
297 engine->instmem.flush = nv84_instmem_flush;
298 engine->mc.init = nv50_mc_init;
299 engine->mc.takedown = nv50_mc_takedown;
300 engine->timer.init = nv04_timer_init;
301 engine->timer.read = nv04_timer_read;
302 engine->timer.takedown = nv04_timer_takedown;
303 engine->fb.init = nv50_fb_init;
304 engine->fb.takedown = nv50_fb_takedown;
305 engine->graph.grclass = nv50_graph_grclass;
306 engine->graph.init = nv50_graph_init;
307 engine->graph.takedown = nv50_graph_takedown;
308 engine->graph.fifo_access = nv50_graph_fifo_access;
309 engine->graph.channel = nv50_graph_channel;
310 engine->graph.create_context = nv50_graph_create_context;
311 engine->graph.destroy_context = nv50_graph_destroy_context;
312 engine->graph.load_context = nv50_graph_load_context;
313 engine->graph.unload_context = nv50_graph_unload_context;
314 engine->fifo.channels = 128;
315 engine->fifo.init = nv50_fifo_init;
316 engine->fifo.takedown = nv50_fifo_takedown;
317 engine->fifo.disable = nv04_fifo_disable;
318 engine->fifo.enable = nv04_fifo_enable;
319 engine->fifo.reassign = nv04_fifo_reassign;
320 engine->fifo.channel_id = nv50_fifo_channel_id;
321 engine->fifo.create_context = nv50_fifo_create_context;
322 engine->fifo.destroy_context = nv50_fifo_destroy_context;
323 engine->fifo.load_context = nv50_fifo_load_context;
324 engine->fifo.unload_context = nv50_fifo_unload_context;
325 engine->display.early_init = nv50_display_early_init;
326 engine->display.late_takedown = nv50_display_late_takedown;
327 engine->display.create = nv50_display_create;
328 engine->display.init = nv50_display_init;
329 engine->display.destroy = nv50_display_destroy;
332 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
340 nouveau_vga_set_decode(void *priv, bool state)
342 struct drm_device *dev = priv;
343 struct drm_nouveau_private *dev_priv = dev->dev_private;
345 if (dev_priv->chipset >= 0x40)
346 nv_wr32(dev, 0x88054, state);
348 nv_wr32(dev, 0x1854, state);
351 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
352 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
354 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
358 nouveau_card_init_channel(struct drm_device *dev)
360 struct drm_nouveau_private *dev_priv = dev->dev_private;
361 struct nouveau_gpuobj *gpuobj;
364 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
365 (struct drm_file *)-2,
371 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
372 0, dev_priv->vram_size,
373 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
378 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
384 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
385 dev_priv->gart_info.aper_size,
386 NV_DMA_ACCESS_RW, &gpuobj, NULL);
390 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
397 nouveau_gpuobj_del(dev, &gpuobj);
398 nouveau_channel_free(dev_priv->channel);
399 dev_priv->channel = NULL;
403 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
404 enum vga_switcheroo_state state)
406 struct drm_device *dev = pci_get_drvdata(pdev);
407 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
408 if (state == VGA_SWITCHEROO_ON) {
409 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
410 nouveau_pci_resume(pdev);
411 drm_kms_helper_poll_enable(dev);
413 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
414 drm_kms_helper_poll_disable(dev);
415 nouveau_pci_suspend(pdev, pmm);
419 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
421 struct drm_device *dev = pci_get_drvdata(pdev);
424 spin_lock(&dev->count_lock);
425 can_switch = (dev->open_count == 0);
426 spin_unlock(&dev->count_lock);
431 nouveau_card_init(struct drm_device *dev)
433 struct drm_nouveau_private *dev_priv = dev->dev_private;
434 struct nouveau_engine *engine;
437 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
438 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
439 nouveau_switcheroo_can_switch);
441 /* Initialise internal driver API hooks */
442 ret = nouveau_init_engine_ptrs(dev);
445 engine = &dev_priv->engine;
446 spin_lock_init(&dev_priv->context_switch_lock);
448 /* Make the CRTCs and I2C buses accessible */
449 ret = engine->display.early_init(dev);
453 /* Parse BIOS tables / Run init tables if card not POSTed */
454 ret = nouveau_bios_init(dev);
456 goto out_display_early;
458 ret = nouveau_mem_detect(dev);
462 ret = nouveau_gpuobj_early_init(dev);
466 /* Initialise instance memory, must happen before mem_init so we
467 * know exactly how much VRAM we're able to use for "normal"
470 ret = engine->instmem.init(dev);
472 goto out_gpuobj_early;
474 /* Setup the memory manager */
475 ret = nouveau_mem_init(dev);
479 ret = nouveau_gpuobj_init(dev);
484 ret = engine->mc.init(dev);
489 ret = engine->timer.init(dev);
494 ret = engine->fb.init(dev);
499 engine->graph.accel_blocked = true;
502 ret = engine->graph.init(dev);
507 ret = engine->fifo.init(dev);
512 ret = engine->display.create(dev);
516 /* this call irq_preinstall, register irq handler and
517 * call irq_postinstall
519 ret = drm_irq_install(dev);
523 ret = drm_vblank_init(dev, 0);
527 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
529 if (!engine->graph.accel_blocked) {
530 ret = nouveau_card_init_channel(dev);
535 ret = nouveau_backlight_init(dev);
537 NV_ERROR(dev, "Error %d registering backlight\n", ret);
539 nouveau_fbcon_init(dev);
540 drm_kms_helper_poll_init(dev);
544 drm_irq_uninstall(dev);
546 engine->display.destroy(dev);
548 if (!nouveau_noaccel)
549 engine->fifo.takedown(dev);
551 if (!nouveau_noaccel)
552 engine->graph.takedown(dev);
554 engine->fb.takedown(dev);
556 engine->timer.takedown(dev);
558 engine->mc.takedown(dev);
560 nouveau_gpuobj_takedown(dev);
562 nouveau_sgdma_takedown(dev);
563 nouveau_mem_close(dev);
565 engine->instmem.takedown(dev);
567 nouveau_gpuobj_late_takedown(dev);
569 nouveau_bios_takedown(dev);
571 engine->display.late_takedown(dev);
573 vga_client_register(dev->pdev, NULL, NULL, NULL);
577 static void nouveau_card_takedown(struct drm_device *dev)
579 struct drm_nouveau_private *dev_priv = dev->dev_private;
580 struct nouveau_engine *engine = &dev_priv->engine;
582 nouveau_backlight_exit(dev);
584 if (dev_priv->channel) {
585 nouveau_channel_free(dev_priv->channel);
586 dev_priv->channel = NULL;
589 if (!nouveau_noaccel) {
590 engine->fifo.takedown(dev);
591 engine->graph.takedown(dev);
593 engine->fb.takedown(dev);
594 engine->timer.takedown(dev);
595 engine->mc.takedown(dev);
596 engine->display.late_takedown(dev);
598 mutex_lock(&dev->struct_mutex);
599 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
600 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
601 mutex_unlock(&dev->struct_mutex);
602 nouveau_sgdma_takedown(dev);
604 nouveau_gpuobj_takedown(dev);
605 nouveau_mem_close(dev);
606 engine->instmem.takedown(dev);
608 drm_irq_uninstall(dev);
610 nouveau_gpuobj_late_takedown(dev);
611 nouveau_bios_takedown(dev);
613 vga_client_register(dev->pdev, NULL, NULL, NULL);
616 /* here a client dies, release the stuff that was allocated for its
618 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
620 nouveau_channel_cleanup(dev, file_priv);
623 /* first module load, setup the mmio/fb mapping */
624 /* KMS: we need mmio at load time, not when the first drm client opens. */
625 int nouveau_firstopen(struct drm_device *dev)
630 /* if we have an OF card, copy vbios to RAMIN */
631 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
633 #if defined(__powerpc__)
635 const uint32_t *bios;
636 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
638 NV_INFO(dev, "Unable to get the OF node\n");
642 bios = of_get_property(dn, "NVDA,BMP", &size);
644 for (i = 0; i < size; i += 4)
645 nv_wi32(dev, i, bios[i/4]);
646 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
648 NV_INFO(dev, "Unable to get the OF bios\n");
653 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
655 struct pci_dev *pdev = dev->pdev;
656 struct apertures_struct *aper = alloc_apertures(3);
660 aper->ranges[0].base = pci_resource_start(pdev, 1);
661 aper->ranges[0].size = pci_resource_len(pdev, 1);
664 if (pci_resource_len(pdev, 2)) {
665 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
666 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
670 if (pci_resource_len(pdev, 3)) {
671 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
672 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
679 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
681 struct drm_nouveau_private *dev_priv = dev->dev_private;
682 bool primary = false;
683 dev_priv->apertures = nouveau_get_apertures(dev);
684 if (!dev_priv->apertures)
688 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
691 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
695 int nouveau_load(struct drm_device *dev, unsigned long flags)
697 struct drm_nouveau_private *dev_priv;
699 resource_size_t mmio_start_offs;
702 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
705 dev->dev_private = dev_priv;
708 dev_priv->flags = flags & NOUVEAU_FLAGS;
710 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
711 dev->pci_vendor, dev->pci_device, dev->pdev->class);
713 dev_priv->wq = create_workqueue("nouveau");
717 /* resource 0 is mmio regs */
718 /* resource 1 is linear FB */
719 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
720 /* resource 6 is bios */
722 /* map the mmio regs */
723 mmio_start_offs = pci_resource_start(dev->pdev, 0);
724 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
725 if (!dev_priv->mmio) {
726 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
727 "Please report your setup to " DRIVER_EMAIL "\n");
730 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
731 (unsigned long long)mmio_start_offs);
734 /* Put the card in BE mode if it's not */
735 if (nv_rd32(dev, NV03_PMC_BOOT_1))
736 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
741 /* Time to determine the card architecture */
742 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
744 /* We're dealing with >=NV10 */
745 if ((reg0 & 0x0f000000) > 0) {
746 /* Bit 27-20 contain the architecture in hex */
747 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
749 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
750 if (reg0 & 0x00f00000)
751 dev_priv->chipset = 0x05;
753 dev_priv->chipset = 0x04;
755 dev_priv->chipset = 0xff;
757 switch (dev_priv->chipset & 0xf0) {
762 dev_priv->card_type = dev_priv->chipset & 0xf0;
766 dev_priv->card_type = NV_40;
772 dev_priv->card_type = NV_50;
775 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
779 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
780 dev_priv->card_type, reg0);
782 ret = nouveau_remove_conflicting_drivers(dev);
786 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
787 if (dev_priv->card_type >= NV_40) {
789 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
792 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
794 ioremap(pci_resource_start(dev->pdev, ramin_bar),
795 dev_priv->ramin_size);
796 if (!dev_priv->ramin) {
797 NV_ERROR(dev, "Failed to PRAMIN BAR");
801 dev_priv->ramin_size = 1 * 1024 * 1024;
802 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
803 dev_priv->ramin_size);
804 if (!dev_priv->ramin) {
805 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
810 nouveau_OF_copy_vbios_to_ramin(dev);
813 if (dev->pci_device == 0x01a0)
814 dev_priv->flags |= NV_NFORCE;
815 else if (dev->pci_device == 0x01f0)
816 dev_priv->flags |= NV_NFORCE2;
818 /* For kernel modesetting, init card now and bring up fbcon */
819 ret = nouveau_card_init(dev);
826 void nouveau_lastclose(struct drm_device *dev)
830 int nouveau_unload(struct drm_device *dev)
832 struct drm_nouveau_private *dev_priv = dev->dev_private;
833 struct nouveau_engine *engine = &dev_priv->engine;
835 drm_kms_helper_poll_fini(dev);
836 nouveau_fbcon_fini(dev);
837 engine->display.destroy(dev);
838 nouveau_card_takedown(dev);
840 iounmap(dev_priv->mmio);
841 iounmap(dev_priv->ramin);
844 dev->dev_private = NULL;
848 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
849 struct drm_file *file_priv)
851 struct drm_nouveau_private *dev_priv = dev->dev_private;
852 struct drm_nouveau_getparam *getparam = data;
854 switch (getparam->param) {
855 case NOUVEAU_GETPARAM_CHIPSET_ID:
856 getparam->value = dev_priv->chipset;
858 case NOUVEAU_GETPARAM_PCI_VENDOR:
859 getparam->value = dev->pci_vendor;
861 case NOUVEAU_GETPARAM_PCI_DEVICE:
862 getparam->value = dev->pci_device;
864 case NOUVEAU_GETPARAM_BUS_TYPE:
865 if (drm_device_is_agp(dev))
866 getparam->value = NV_AGP;
867 else if (drm_device_is_pcie(dev))
868 getparam->value = NV_PCIE;
870 getparam->value = NV_PCI;
872 case NOUVEAU_GETPARAM_FB_PHYSICAL:
873 getparam->value = dev_priv->fb_phys;
875 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
876 getparam->value = dev_priv->gart_info.aper_base;
878 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
880 getparam->value = (unsigned long)dev->sg->virtual;
882 NV_ERROR(dev, "Requested PCIGART address, "
883 "while no PCIGART was created\n");
887 case NOUVEAU_GETPARAM_FB_SIZE:
888 getparam->value = dev_priv->fb_available_size;
890 case NOUVEAU_GETPARAM_AGP_SIZE:
891 getparam->value = dev_priv->gart_info.aper_size;
893 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
894 getparam->value = dev_priv->vm_vram_base;
896 case NOUVEAU_GETPARAM_PTIMER_TIME:
897 getparam->value = dev_priv->engine.timer.read(dev);
899 case NOUVEAU_GETPARAM_GRAPH_UNITS:
900 /* NV40 and NV50 versions are quite different, but register
901 * address is the same. User is supposed to know the card
902 * family anyway... */
903 if (dev_priv->chipset >= 0x40) {
904 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
909 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
917 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
918 struct drm_file *file_priv)
920 struct drm_nouveau_setparam *setparam = data;
922 switch (setparam->param) {
924 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
931 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
932 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
933 uint32_t reg, uint32_t mask, uint32_t val)
935 struct drm_nouveau_private *dev_priv = dev->dev_private;
936 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
937 uint64_t start = ptimer->read(dev);
940 if ((nv_rd32(dev, reg) & mask) == val)
942 } while (ptimer->read(dev) - start < timeout);
947 /* Waits for PGRAPH to go completely idle */
948 bool nouveau_wait_for_idle(struct drm_device *dev)
950 if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
951 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
952 nv_rd32(dev, NV04_PGRAPH_STATUS));