2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/console.h>
29 #include "drm_crtc_helper.h"
30 #include "nouveau_drv.h"
31 #include "nouveau_hw.h"
32 #include "nouveau_fb.h"
33 #include "nouveau_fbcon.h"
34 #include "nv50_display.h"
36 #include "drm_pciids.h"
38 MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
39 int nouveau_ctxfw = 0;
40 module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
42 MODULE_PARM_DESC(noagp, "Disable AGP");
44 module_param_named(noagp, nouveau_noagp, int, 0400);
46 MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
47 static int nouveau_modeset = -1; /* kms */
48 module_param_named(modeset, nouveau_modeset, int, 0400);
50 MODULE_PARM_DESC(vbios, "Override default VBIOS location");
52 module_param_named(vbios, nouveau_vbios, charp, 0400);
54 MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
55 int nouveau_vram_pushbuf;
56 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
58 MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
59 int nouveau_vram_notify = 0;
60 module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
62 MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
63 int nouveau_duallink = 1;
64 module_param_named(duallink, nouveau_duallink, int, 0400);
66 MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
67 int nouveau_uscript_lvds = -1;
68 module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
70 MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
71 int nouveau_uscript_tmds = -1;
72 module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
74 MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
75 int nouveau_ignorelid = 0;
76 module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
78 MODULE_PARM_DESC(noaccel, "Disable all acceleration");
79 int nouveau_noaccel = 0;
80 module_param_named(noaccel, nouveau_noaccel, int, 0400);
82 MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
83 int nouveau_nofbaccel = 0;
84 module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
86 MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
87 int nouveau_override_conntype = 0;
88 module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
90 MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
91 int nouveau_tv_disable = 0;
92 module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
94 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
95 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
96 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
98 "\t\t*NOTE* Ignored for cards with external TV encoders.");
99 char *nouveau_tv_norm;
100 module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
102 MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
103 "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
104 "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
105 "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
106 int nouveau_reg_debug;
107 module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
109 int nouveau_fbpercrtc;
111 module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
114 static struct pci_device_id pciidlist[] = {
116 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
117 .class = PCI_BASE_CLASS_DISPLAY << 16,
118 .class_mask = 0xff << 16,
121 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
122 .class = PCI_BASE_CLASS_DISPLAY << 16,
123 .class_mask = 0xff << 16,
128 MODULE_DEVICE_TABLE(pci, pciidlist);
130 static struct drm_driver driver;
133 nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
135 return drm_get_pci_dev(pdev, ent, &driver);
139 nouveau_pci_remove(struct pci_dev *pdev)
141 struct drm_device *dev = pci_get_drvdata(pdev);
147 nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
149 struct drm_device *dev = pci_get_drvdata(pdev);
150 struct drm_nouveau_private *dev_priv = dev->dev_private;
151 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
152 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
153 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
154 struct nouveau_channel *chan;
155 struct drm_crtc *crtc;
158 if (pm_state.event == PM_EVENT_PRETHAW)
161 NV_INFO(dev, "Disabling fbcon acceleration...\n");
162 nouveau_fbcon_save_disable_accel(dev);
164 NV_INFO(dev, "Unpinning framebuffer(s)...\n");
165 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
166 struct nouveau_framebuffer *nouveau_fb;
168 nouveau_fb = nouveau_framebuffer(crtc->fb);
169 if (!nouveau_fb || !nouveau_fb->nvbo)
172 nouveau_bo_unpin(nouveau_fb->nvbo);
175 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
176 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
178 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
179 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
182 NV_INFO(dev, "Evicting buffers...\n");
183 ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
185 NV_INFO(dev, "Idling channels...\n");
186 for (i = 0; i < pfifo->channels; i++) {
187 struct nouveau_fence *fence = NULL;
189 chan = dev_priv->fifos[i];
190 if (!chan || (dev_priv->card_type >= NV_50 &&
191 chan == dev_priv->fifos[0]))
194 ret = nouveau_fence_new(chan, &fence, true);
196 ret = nouveau_fence_wait(fence, NULL, false, false);
197 nouveau_fence_unref((void *)&fence);
201 NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
206 pgraph->fifo_access(dev, false);
207 nouveau_wait_for_idle(dev);
208 pfifo->reassign(dev, false);
210 pfifo->unload_context(dev);
211 pgraph->unload_context(dev);
213 NV_INFO(dev, "Suspending GPU objects...\n");
214 ret = nouveau_gpuobj_suspend(dev);
216 NV_ERROR(dev, "... failed: %d\n", ret);
220 ret = pinstmem->suspend(dev);
222 NV_ERROR(dev, "... failed: %d\n", ret);
223 nouveau_gpuobj_suspend_cleanup(dev);
227 NV_INFO(dev, "And we're gone!\n");
228 pci_save_state(pdev);
229 if (pm_state.event == PM_EVENT_SUSPEND) {
230 pci_disable_device(pdev);
231 pci_set_power_state(pdev, PCI_D3hot);
234 acquire_console_sem();
235 nouveau_fbcon_set_suspend(dev, 1);
236 release_console_sem();
237 nouveau_fbcon_restore_accel(dev);
241 NV_INFO(dev, "Re-enabling acceleration..\n");
243 pfifo->reassign(dev, true);
244 pgraph->fifo_access(dev, true);
249 nouveau_pci_resume(struct pci_dev *pdev)
251 struct drm_device *dev = pci_get_drvdata(pdev);
252 struct drm_nouveau_private *dev_priv = dev->dev_private;
253 struct nouveau_engine *engine = &dev_priv->engine;
254 struct drm_crtc *crtc;
257 nouveau_fbcon_save_disable_accel(dev);
259 NV_INFO(dev, "We're back, enabling device...\n");
260 pci_set_power_state(pdev, PCI_D0);
261 pci_restore_state(pdev);
262 if (pci_enable_device(pdev))
264 pci_set_master(dev->pdev);
266 NV_INFO(dev, "POSTing device...\n");
267 ret = nouveau_run_vbios_init(dev);
271 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
272 ret = nouveau_mem_init_agp(dev);
274 NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
279 NV_INFO(dev, "Reinitialising engines...\n");
280 engine->instmem.resume(dev);
281 engine->mc.init(dev);
282 engine->timer.init(dev);
283 engine->fb.init(dev);
284 engine->graph.init(dev);
285 engine->fifo.init(dev);
287 NV_INFO(dev, "Restoring GPU objects...\n");
288 nouveau_gpuobj_resume(dev);
290 nouveau_irq_postinstall(dev);
292 /* Re-write SKIPS, they'll have been lost over the suspend */
293 if (nouveau_vram_pushbuf) {
294 struct nouveau_channel *chan;
297 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
298 chan = dev_priv->fifos[i];
299 if (!chan || !chan->pushbuf_bo)
302 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
303 nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
307 NV_INFO(dev, "Restoring mode...\n");
308 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
309 struct nouveau_framebuffer *nouveau_fb;
311 nouveau_fb = nouveau_framebuffer(crtc->fb);
312 if (!nouveau_fb || !nouveau_fb->nvbo)
315 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
318 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
319 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
322 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
324 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
326 NV_ERROR(dev, "Could not pin/map cursor.\n");
329 if (dev_priv->card_type < NV_50) {
330 nv04_display_restore(dev);
331 NVLockVgaCrtcs(dev, false);
333 nv50_display_init(dev);
335 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
336 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
338 nv_crtc->cursor.set_offset(nv_crtc,
339 nv_crtc->cursor.nvbo->bo.offset -
340 dev_priv->vm_vram_base);
342 nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
343 nv_crtc->cursor_saved_y);
346 /* Force CLUT to get re-loaded during modeset */
347 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
348 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
350 nv_crtc->lut.depth = 0;
353 acquire_console_sem();
354 nouveau_fbcon_set_suspend(dev, 0);
355 release_console_sem();
357 nouveau_fbcon_zfill_all(dev);
359 drm_helper_resume_force_mode(dev);
361 nouveau_fbcon_restore_accel(dev);
365 static struct drm_driver driver = {
367 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
368 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
370 .load = nouveau_load,
371 .firstopen = nouveau_firstopen,
372 .lastclose = nouveau_lastclose,
373 .unload = nouveau_unload,
374 .preclose = nouveau_preclose,
375 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
376 .debugfs_init = nouveau_debugfs_init,
377 .debugfs_cleanup = nouveau_debugfs_takedown,
379 .irq_preinstall = nouveau_irq_preinstall,
380 .irq_postinstall = nouveau_irq_postinstall,
381 .irq_uninstall = nouveau_irq_uninstall,
382 .irq_handler = nouveau_irq_handler,
383 .reclaim_buffers = drm_core_reclaim_buffers,
384 .get_map_ofs = drm_core_get_map_ofs,
385 .get_reg_ofs = drm_core_get_reg_ofs,
386 .ioctls = nouveau_ioctls,
388 .owner = THIS_MODULE,
390 .release = drm_release,
391 .unlocked_ioctl = drm_ioctl,
392 .mmap = nouveau_ttm_mmap,
394 .fasync = drm_fasync,
395 #if defined(CONFIG_COMPAT)
396 .compat_ioctl = nouveau_compat_ioctl,
401 .id_table = pciidlist,
402 .probe = nouveau_pci_probe,
403 .remove = nouveau_pci_remove,
404 .suspend = nouveau_pci_suspend,
405 .resume = nouveau_pci_resume
408 .gem_init_object = nouveau_gem_object_new,
409 .gem_free_object = nouveau_gem_object_del,
414 .date = GIT_REVISION,
418 .major = DRIVER_MAJOR,
419 .minor = DRIVER_MINOR,
420 .patchlevel = DRIVER_PATCHLEVEL,
423 static int __init nouveau_init(void)
425 driver.num_ioctls = nouveau_max_ioctl;
427 if (nouveau_modeset == -1) {
428 #ifdef CONFIG_VGA_CONSOLE
429 if (vgacon_text_force())
436 if (!nouveau_modeset)
439 nouveau_register_dsm_handler();
440 return drm_init(&driver);
443 static void __exit nouveau_exit(void)
445 if (!nouveau_modeset)
449 nouveau_unregister_dsm_handler();
452 module_init(nouveau_init);
453 module_exit(nouveau_exit);
455 MODULE_AUTHOR(DRIVER_AUTHOR);
456 MODULE_DESCRIPTION(DRIVER_DESC);
457 MODULE_LICENSE("GPL and additional rights");